rockchip: add Radxa CM3 IO board support
[openwrt/staging/jow.git] / target / linux / ramips / dts / mt7621_tplink_deco-m4r-v4.dts
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include "mt7621.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8
9 / {
10 compatible = "tplink,deco-m4r-v4", "mediatek,mt7621-soc";
11 model = "TP-Link Deco M4R v4";
12
13 aliases {
14 label-mac-device = &gmac0;
15 led-boot = &led_power;
16 led-failsafe = &led_power;
17 led-running = &led_power;
18 led-upgrade = &led_power;
19 };
20
21 chosen {
22 bootargs = "console=ttyS0,115200n8";
23 };
24
25 keys {
26 compatible = "gpio-keys";
27
28 wps {
29 label = "wps";
30 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
31 debounce-interval = <60>;
32 linux,code = <KEY_WPS_BUTTON>;
33 };
34
35 led {
36 label = "led";
37 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
38 debounce_interval = <60>;
39 linux,code = <KEY_BRIGHTNESS_TOGGLE>;
40 };
41
42 reset {
43 label = "reset";
44 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
45 debounce-interval = <60>;
46 linux,code = <KEY_RESTART>;
47 };
48 };
49
50 leds {
51 compatible = "gpio-leds";
52
53 rssi {
54 label = "green:rssi";
55 gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
56 };
57
58 lan {
59 function = LED_FUNCTION_LAN;
60 color = <LED_COLOR_ID_GREEN>;
61 gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
62 };
63
64 sys {
65 label = "green:sys";
66 gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
67 };
68
69 wifi2g {
70 label = "green:wifi2g";
71 gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
72 linux,default-trigger = "phy0tpt";
73 };
74
75 logo_red {
76 label = "red:logo";
77 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
78 /* match usage in v1 and v2 */
79 linux,default-trigger = "phy0tpt";
80 };
81
82 logo_blue {
83 label = "blue:logo";
84 gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
85 /* match usage in v1 and v2 */
86 linux,default-trigger = "phy1tpt";
87
88 };
89
90 led_power: logo_green {
91 label = "green:logo";
92 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
93 /* match usage in v1 and v2 */
94 default_state = "on";
95 };
96 };
97 };
98
99 &state_default {
100 gpio {
101 groups = "i2c", "uart2", "uart3", "jtag", "wdt";
102 function = "gpio";
103 };
104 };
105
106 &spi0 {
107 status = "okay";
108
109 flash@0 {
110 compatible = "jedec,spi-nor";
111 reg = <0>;
112 spi-max-frequency = <40000000>;
113
114 partitions {
115 compatible = "fixed-partitions";
116 #address-cells = <1>;
117 #size-cells = <1>;
118
119 partition@0 {
120 label = "u-boot";
121 reg = <0x0 0x40000>;
122 read-only;
123 };
124
125 partition@40000 {
126 label = "firmware";
127 compatible = "denx,uimage";
128 reg = <0x40000 0xf60000>;
129 };
130
131 config: partition@fa0000 {
132 label = "config";
133 reg = <0xfa0000 0x010000>;
134 read-only;
135
136 nvmem-layout {
137 compatible = "fixed-layout";
138 #address-cells = <1>;
139 #size-cells = <1>;
140
141 macaddr_config_8: macaddr@8 {
142 reg = <0x8 0x6>;
143 };
144 };
145 };
146
147 partition@fb0000 {
148 label = "tplink";
149 reg = <0xfb0000 0x040000>;
150 read-only;
151 };
152
153 radio: partition@ff0000 {
154 label = "radio";
155 reg = <0xff0000 0x10000>;
156 read-only;
157
158 nvmem-layout {
159 compatible = "fixed-layout";
160 #address-cells = <1>;
161 #size-cells = <1>;
162
163 eeprom_radio_0: eeprom@0 {
164 reg = <0x0 0x400>;
165 };
166
167 eeprom_radio_8000: eeprom@8000 {
168 reg = <0x8000 0x4da8>;
169 };
170 };
171 };
172 };
173 };
174 };
175
176 &ethernet {
177 pinctrl-names = "default";
178 pinctrl-0 = <&rgmii1_pins &mdio_pins>;
179 };
180
181 &gmac0 {
182 nvmem-cells = <&macaddr_config_8>;
183 nvmem-cell-names = "mac-address";
184 label = "dsa";
185 };
186
187 &switch0 {
188 ports {
189 port@0 {
190 status = "okay";
191 label = "eth0";
192 };
193
194 port@1 {
195 status = "okay";
196 label = "eth1";
197 };
198 };
199 };
200
201 &pcie {
202 status = "okay";
203 };
204
205 &pcie0 {
206 wifi@0,0 {
207 compatible = "mediatek,mt76";
208 reg = <0x0000 0 0 0 0>;
209 nvmem-cells = <&eeprom_radio_0>;
210 nvmem-cell-names = "eeprom";
211 ieee80211-freq-limit = <2400000 2500000>;
212 };
213 };
214
215 &pcie1 {
216 wifi@0,0 {
217 compatible = "mediatek,mt76";
218 reg = <0x0000 0 0 0 0>;
219 nvmem-cells = <&eeprom_radio_8000>;
220 nvmem-cell-names = "eeprom";
221 ieee80211-freq-limit = <5000000 6000000>;
222 };
223 };