rockchip: add Radxa CM3 IO board support
[openwrt/staging/jow.git] / target / linux / ramips / dts / mt7621_snr_snr-cpe-me2-sfp.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 #include "mt7621.dtsi"
3
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/leds/common.h>
7
8 / {
9 compatible = "snr,snr-cpe-me2-sfp", "mediatek,mt7621-soc";
10 model = "SNR-CPE-ME2-SFP";
11
12 aliases {
13 led-boot = &led_sys;
14 led-failsafe = &led_sys;
15 led-running = &led_sys;
16 led-upgrade = &led_sys;
17 };
18
19 leds {
20 compatible = "gpio-leds";
21
22 led_sys: sys {
23 color = <LED_COLOR_ID_GREEN>;
24 function = LED_FUNCTION_STATUS;
25 gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
26 };
27
28 vpn {
29 color = <LED_COLOR_ID_GREEN>;
30 function = LED_FUNCTION_STATUS;
31 gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
32 };
33
34 usb {
35 color = <LED_COLOR_ID_GREEN>;
36 function = LED_FUNCTION_USB;
37 gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
38 trigger-sources = <&xhci_ehci_port1>;
39 linux,default-trigger = "usbport";
40 };
41 };
42
43 keys {
44 compatible = "gpio-keys";
45
46 reset {
47 label = "reset";
48 gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
49 linux,code = <KEY_RESTART>;
50 };
51 };
52
53 sfp_wan: sfp0 {
54 compatible = "sff,sfp";
55 i2c-bus = <&i2c>;
56 los-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
57 mod-def0-gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
58 tx-disable-gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
59 maximum-power-milliwatt = <1000>;
60 };
61
62 reg_usb_vbus: regulator-usb {
63 compatible = "regulator-fixed";
64 regulator-name = "usb_vbus";
65 regulator-min-microvolt = <5000000>;
66 regulator-max-microvolt = <5000000>;
67 gpio = <&gpio 17 GPIO_ACTIVE_HIGH>;
68 enable-active-high;
69 };
70
71 reg_3p3v: regulator-3p3v {
72 compatible = "regulator-fixed";
73 regulator-name = "fixed-3.3V";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
76 regulator-boot-on;
77 regulator-always-on;
78 };
79 };
80
81 &state_default {
82 gpio {
83 groups = "uart2", "uart3", "jtag";
84 function = "gpio";
85 };
86 };
87
88 &spi0 {
89 status = "okay";
90
91 flash@0 { // GD25Q127CSIG
92 compatible = "jedec,spi-nor";
93 reg = <0>;
94 spi-max-frequency = <44000000>;
95
96 partitions {
97 compatible = "fixed-partitions";
98 #address-cells = <1>;
99 #size-cells = <1>;
100
101 partition@0 {
102 label = "u-boot";
103 reg = <0x0 0x30000>;
104 read-only;
105 };
106
107 partition@30000 {
108 label = "config";
109 reg = <0x30000 0x10000>;
110 };
111
112 factory: partition@40000 {
113 label = "factory";
114 reg = <0x40000 0x10000>;
115 read-only;
116
117 nvmem-layout {
118 compatible = "fixed-layout";
119 #address-cells = <1>;
120 #size-cells = <1>;
121
122 eeprom_factory_0: eeprom@0 {
123 reg = <0x0 0x4da8>;
124 };
125
126 macaddr_factory_e000: macaddr@e000 {
127 reg = <0xe000 0x6>;
128 };
129
130 macaddr_factory_e006: macaddr@e006 {
131 reg = <0xe006 0x6>;
132 };
133 };
134 };
135
136 partition@50000 {
137 compatible = "denx,uimage";
138 label = "firmware";
139 reg = <0x50000 0xfb0000>;
140 };
141
142 partition@30001 {
143 label = "uboot-env";
144 reg = <0x30000 0x1000>;
145 };
146 };
147 };
148 };
149
150 &gpio {
151 // driver issue, bypass
152 enable_sfp {
153 gpio-hog;
154 gpios = <9 GPIO_ACTIVE_LOW>;
155 output-low;
156 };
157 };
158
159 &mdio {
160 phy_sfp: ethernet-phy@0 {
161 reg = <0>;
162 sfp = <&sfp_wan>;
163 };
164 };
165
166 &gmac0 {
167 nvmem-cells = <&macaddr_factory_e000>;
168 nvmem-cell-names = "mac-address";
169 };
170
171 &gmac1 {
172 status = "okay";
173 label = "wan";
174 phy-mode = "rgmii-rxid";
175 phy-handle = <&phy_sfp>;
176
177 nvmem-cells = <&macaddr_factory_e006>;
178 nvmem-cell-names = "mac-address";
179 };
180
181 &switch0 {
182 ports {
183 port@1 {
184 status = "okay";
185 label = "lan1";
186 };
187
188 port@2 {
189 status = "okay";
190 label = "lan2";
191 };
192
193 port@3 {
194 status = "okay";
195 label = "lan3";
196 };
197
198 port@4 {
199 status = "okay";
200 label = "lan4";
201 };
202 };
203 };
204
205 &xhci {
206 vusb33-supply = <&reg_3p3v>;
207 vbus-supply = <&reg_usb_vbus>;
208 };
209
210 &pcie {
211 status = "okay";
212 };
213
214 &pcie0 {
215 wifi@0,0 {
216 compatible = "mediatek,mt76";
217 reg = <0x0000 0 0 0 0>;
218 nvmem-cells = <&eeprom_factory_0>;
219 nvmem-cell-names = "eeprom";
220 };
221 };