rockchip: add Radxa CM3 IO board support
[openwrt/staging/jow.git] / target / linux / ramips / dts / mt7621_linksys_re6500.dts
1 #include "mt7621.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6
7 / {
8 compatible = "linksys,re6500", "mediatek,mt7621-soc";
9 model = "Linksys RE6500";
10
11 aliases {
12 led-boot = &led_power;
13 led-failsafe = &led_power;
14 led-running = &led_power;
15 led-upgrade = &led_power;
16 };
17
18 leds {
19 compatible = "gpio-leds";
20
21 wifi {
22 label = "orange:wifi";
23 gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
24 };
25
26 led_power: power {
27 function = LED_FUNCTION_POWER;
28 color = <LED_COLOR_ID_WHITE>;
29 gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
30 };
31 };
32
33 keys {
34 compatible = "gpio-keys";
35
36 wps {
37 label = "wps";
38 gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
39 linux,code = <KEY_WPS_BUTTON>;
40 };
41
42 reset {
43 label = "reset";
44 gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
45 linux,code = <KEY_RESTART>;
46 };
47 };
48 };
49
50 &spi0 {
51 status = "okay";
52
53 flash@0 {
54 compatible = "jedec,spi-nor";
55 reg = <0>;
56 spi-max-frequency = <10000000>;
57
58 partitions {
59 compatible = "fixed-partitions";
60 #address-cells = <1>;
61 #size-cells = <1>;
62
63 partition@0 {
64 label = "u-boot";
65 reg = <0x0 0x30000>;
66 read-only;
67 };
68
69 partition@30000 {
70 label = "u-boot-env";
71 reg = <0x30000 0x10000>;
72 read-only;
73 };
74
75 factory: partition@40000 {
76 label = "factory";
77 reg = <0x40000 0x10000>;
78 read-only;
79
80 nvmem-layout {
81 compatible = "fixed-layout";
82 #address-cells = <1>;
83 #size-cells = <1>;
84
85 eeprom_factory_0: eeprom@0 {
86 reg = <0x0 0x200>;
87 };
88
89 eeprom_factory_8000: eeprom@8000 {
90 reg = <0x8000 0x200>;
91 };
92
93 macaddr_factory_2e: macaddr@2e {
94 reg = <0x2e 0x6>;
95 };
96 };
97 };
98
99 partition@50000 {
100 compatible = "denx,uimage";
101 label = "firmware";
102 reg = <0x50000 0x7b0000>;
103 };
104 };
105 };
106 };
107
108 &state_default {
109 gpio {
110 groups = "i2c", "uart2";
111 function = "gpio";
112 };
113 };
114
115 &pcie {
116 status = "okay";
117 };
118
119 &pcie0 {
120 mt76@0,0 {
121 reg = <0x0000 0 0 0 0>;
122 nvmem-cells = <&eeprom_factory_0>;
123 nvmem-cell-names = "eeprom";
124 ieee80211-freq-limit = <5000000 6000000>;
125 };
126 };
127
128 &pcie1 {
129 mt76@0,0 {
130 reg = <0x0000 0 0 0 0>;
131 nvmem-cells = <&eeprom_factory_8000>;
132 nvmem-cell-names = "eeprom";
133 ieee80211-freq-limit = <2400000 2500000>;
134 };
135 };
136
137 &gmac0 {
138 nvmem-cells = <&macaddr_factory_2e>;
139 nvmem-cell-names = "mac-address";
140 };
141
142 &gmac1 {
143 status = "okay";
144 label = "lan1";
145 phy-handle = <&ethphy0>;
146
147 nvmem-cells = <&macaddr_factory_2e>;
148 nvmem-cell-names = "mac-address";
149 };
150
151 &mdio {
152 ethphy0: ethernet-phy@0 {
153 reg = <0>;
154 };
155 };
156
157 &switch0 {
158 ports {
159 port@1 {
160 status = "okay";
161 label = "lan2";
162 };
163
164 port@2 {
165 status = "okay";
166 label = "lan3";
167 };
168
169 port@3 {
170 status = "okay";
171 label = "lan4";
172 };
173 };
174 };
175
176 &xhci {
177 status = "disabled";
178 };