rockchip: add Radxa CM3 IO board support
[openwrt/staging/jow.git] / target / linux / ramips / dts / mt7620n_dlink_dwr-116-a1.dts
1 #include "mt7620n.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/leds/common.h>
6 #include <dt-bindings/mtd/partitions/uimage.h>
7
8 / {
9 compatible = "dlink,dwr-116-a1", "ralink,mt7620n-soc";
10 model = "D-Link DWR-116 A1/A2";
11
12 aliases {
13 led-boot = &led_status;
14 led-failsafe = &led_status;
15 led-running = &led_status;
16 led-upgrade = &led_status;
17 };
18
19 keys {
20 compatible = "gpio-keys";
21
22 wps {
23 label = "wps";
24 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
25 linux,code = <KEY_WPS_BUTTON>;
26 };
27
28 reset {
29 label = "reset";
30 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
31 linux,code = <KEY_RESTART>;
32 };
33 };
34
35 leds {
36 compatible = "gpio-leds";
37
38 led_status: status {
39 function = LED_FUNCTION_STATUS;
40 color = <LED_COLOR_ID_GREEN>;
41 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
42 };
43
44 wifi {
45 label = "green:wifi";
46 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
47 };
48 };
49 };
50
51 &gpio3 {
52 status = "okay";
53 };
54
55 &spi0 {
56 status = "okay";
57
58 flash@0 {
59 compatible = "jedec,spi-nor";
60 reg = <0>;
61 spi-max-frequency = <50000000>;
62
63 partitions {
64 compatible = "fixed-partitions";
65 #address-cells = <1>;
66 #size-cells = <1>;
67
68 partition@0 {
69 label = "jboot";
70 reg = <0x0 0x10000>;
71 read-only;
72 };
73
74 partition@10000 {
75 compatible = "openwrt,uimage", "denx,uimage";
76 openwrt,ih-magic = <IH_MAGIC_OKLI>;
77 openwrt,offset = <0x10000>;
78 label = "firmware";
79 reg = <0x10000 0x7e0000>;
80 };
81
82 config: partition@7f0000 {
83 label = "config";
84 reg = <0x7f0000 0x10000>;
85 read-only;
86 };
87 };
88 };
89 };
90
91 &ehci {
92 status = "okay";
93 };
94
95 &ohci {
96 status = "okay";
97 };
98
99 &state_default {
100 default {
101 groups = "i2c", "wled";
102 function = "gpio";
103 };
104 };
105
106 &ethernet {
107 pinctrl-names = "default";
108 pinctrl-0 = <&ephy_pins>;
109
110 mediatek,portmap = "llllw";
111 };