target/linux/ramips/dts/mt7620a_wavlink_wl-wn530hg4.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #include "mt7620a.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 / {
  10         compatible = "wavlink,wl-wn530hg4", "ralink,mt7620a-soc";
  11         model = "Wavlink WL-WN530HG4";
  12
  13         aliases {
  14                 led-boot = &led_status_blue;
  15                 led-failsafe = &led_status_blue;
  16                 led-running = &led_status_blue;
  17                 led-upgrade = &led_status_blue;
  18         };
  19
  20         leds {
  21                 compatible = "gpio-leds";
  22
  23                 led_status_blue: status_blue {
  24                         function = LED_FUNCTION_STATUS;
  25                         color = <LED_COLOR_ID_BLUE>;
  26                         gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
  27                 };
  28
  29                 status_yellow {
  30                         function = LED_FUNCTION_STATUS;
  31                         color = <LED_COLOR_ID_YELLOW>;
  32                         gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
  33                 };
  34
  35                 status_red {
  36                         function = LED_FUNCTION_STATUS;
  37                         color = <LED_COLOR_ID_RED>;
  38                         gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
  39                 };
  40         };
  41
  42         keys {
  43                 compatible = "gpio-keys";
  44
  45                 reset {
  46                         label = "reset";
  47                         gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
  48                         linux,code = <KEY_RESTART>;
  49                 };
  50         };
  51 };
  52
  53 &spi0 {
  54         status = "okay";
  55
  56         flash@0 {
  57                 compatible = "jedec,spi-nor";
  58                 reg = <0>;
  59                 spi-max-frequency = <24000000>;
  60
  61                 partitions {
  62                         compatible = "fixed-partitions";
  63                         #address-cells = <1>;
  64                         #size-cells = <1>;
  65
  66                         partition@0 {
  67                                 label = "u-boot";
  68                                 reg = <0x0 0x30000>;
  69                                 read-only;
  70                         };
  71
  72                         partition@30000 {
  73                                 label = "config";
  74                                 reg = <0x30000 0x10000>;
  75                                 read-only;
  76                         };
  77
  78                         factory: partition@40000 {
  79                                 label = "factory";
  80                                 reg = <0x40000 0x10000>;
  81                                 read-only;
  82
  83                                 nvmem-layout {
  84                                         compatible = "fixed-layout";
  85                                         #address-cells = <1>;
  86                                         #size-cells = <1>;
  87
  88                                         eeprom_factory_0: eeprom@0 {
  89                                                 reg = <0x0 0x200>;
  90                                         };
  91
  92                                         eeprom_factory_8000: eeprom@8000 {
  93                                                 reg = <0x8000 0x200>;
  94                                         };
  95
  96                                         macaddr_factory_28: macaddr@28 {
  97                                                 reg = <0x28 0x6>;
  98                                         };
  99                                 };
 100                         };
 101
 102                         partition@50000 {
 103                                 compatible = "denx,uimage";
 104                                 label = "firmware";
 105                                 reg = <0x50000 0x7b0000>;
 106                         };
 107                 };
 108         };
 109 };
 110
 111 &state_default {
 112         gpio {
 113                 groups = "i2c", "uartf";
 114                 function = "gpio";
 115         };
 116 };
 117
 118 &ethernet {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&rgmii2_pins &mdio_pins>;
 121
 122         nvmem-cells = <&macaddr_factory_28>;
 123         nvmem-cell-names = "mac-address";
 124
 125         mediatek,portmap = "llllw";
 126
 127         port@5 {
 128                 status = "okay";
 129                 phy-handle = <&phy5>;
 130                 phy-mode = "rgmii";
 131         };
 132
 133         mdio-bus {
 134                 status = "okay";
 135
 136                 phy5: ethernet-phy@5 {
 137                         reg = <5>;
 138                         phy-mode = "rgmii";
 139                 };
 140         };
 141 };
 142
 143 &pcie {
 144         status = "okay";
 145 };
 146
 147 &pcie0 {
 148         mt76@0,0 {
 149                 reg = <0x0000 0 0 0 0>;
 150                 nvmem-cells = <&eeprom_factory_8000>;
 151                 nvmem-cell-names = "eeprom";
 152                 ieee80211-freq-limit = <5000000 6000000>;
 153         };
 154 };
 155
 156 &wmac {
 157         pinctrl-names = "default", "pa_gpio";
 158         pinctrl-0 = <&pa_pins>;
 159         pinctrl-1 = <&pa_gpio_pins>;
 160         nvmem-cells = <&eeprom_factory_0>;
 161         nvmem-cell-names = "eeprom";
 162 };