Refresh kernel 6.6 patches.
Removed backpored patches.
Signed-off-by: Antonio Flores <antflores627@gmail.com>
+++ /dev/null
-From b75a52b0dda353aeefb4830a320589a363f49579 Mon Sep 17 00:00:00 2001
-From: Shawn Lin <shawn.lin@rock-chips.com>
-Date: Thu, 2 Feb 2023 08:35:16 +0800
-Subject: [PATCH] mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for
- rockchip platform
-
-For Rockchip platform, DLL bypass bit and start bit need to be set if
-DLL is not locked. And adjust pre-change delay to 0x3 for better signal
-test result.
-
-Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
-Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++----
- 1 file changed, 9 insertions(+), 4 deletions(-)
-
---- a/drivers/mmc/host/sdhci-of-dwcmshc.c
-+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
-@@ -48,6 +48,7 @@
- #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
- #define DWCMSHC_EMMC_DLL_START_POINT 16
- #define DWCMSHC_EMMC_DLL_INC 8
-+#define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
- #define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
- #define DLL_TXCLK_TAPNUM_DEFAULT 0x10
- #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA
-@@ -60,6 +61,7 @@
- #define DLL_RXCLK_NO_INVERTER 1
- #define DLL_RXCLK_INVERTER 0
- #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
-+#define DLL_RXCLK_ORI_GATE BIT(31)
- #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
- #define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
- #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
-@@ -234,9 +236,12 @@ static void dwcmshc_rk3568_set_clock(str
- sdhci_writel(host, extra, reg);
-
- if (clock <= 52000000) {
-- /* Disable DLL and reset both of sample and drive clock */
-- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
-- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
-+ /*
-+ * Disable DLL and reset both of sample and drive clock.
-+ * The bypass bit and start bit need to be set if DLL is not locked.
-+ */
-+ sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
-+ sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
- sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
- /*
-@@ -279,7 +284,7 @@ static void dwcmshc_rk3568_set_clock(str
- }
-
- extra = 0x1 << 16 | /* tune clock stop en */
-- 0x2 << 17 | /* pre-change delay */
-+ 0x3 << 17 | /* pre-change delay */
- 0x3 << 19; /* post-change delay */
- sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL);
-
+++ /dev/null
-From 49502408007b77ff290ce62e6218cefaeedcb31a Mon Sep 17 00:00:00 2001
-From: Vasily Khoruzhick <anarsoul@gmail.com>
-Date: Thu, 9 Mar 2023 17:03:49 -0800
-Subject: [PATCH] mmc: sdhci-of-dwcmshc: properly determine max clock on
- Rockchip
-
-Currently .get_max_clock returns the current clock rate for cclk_emmc
-on rk35xx, thus max clock gets set to whatever bootloader set it to.
-
-In case of u-boot, it is intentionally reset to 50 MHz if it boots
-from eMMC, see mmc_deinit() in u-boot sources. As a result, HS200 and
-HS400 modes are never selected by Linux, because dwcmshc_rk35xx_postinit
-clears appropriate caps if host->mmc->f_max is < 52MHz
-
-cclk_emmc is not a fixed clock on rk35xx, so using
-sdhci_pltfm_clk_get_max_clock is not appropriate here.
-
-Implement rk35xx_get_max_clock that returns actual max clock for cclk_emmc.
-
-Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Acked-by: Adrian Hunter <adrian.hunter@intel.com>
-Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com
-Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
----
- drivers/mmc/host/sdhci-of-dwcmshc.c | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/drivers/mmc/host/sdhci-of-dwcmshc.c
-+++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
-@@ -126,6 +126,13 @@ static unsigned int dwcmshc_get_max_cloc
- return pltfm_host->clock;
- }
-
-+static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
-+{
-+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
-+
-+ return clk_round_rate(pltfm_host->clk, ULONG_MAX);
-+}
-+
- static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
- struct mmc_request *mrq)
- {
-@@ -343,7 +350,7 @@ static const struct sdhci_ops sdhci_dwcm
- .set_clock = dwcmshc_rk3568_set_clock,
- .set_bus_width = sdhci_set_bus_width,
- .set_uhs_signaling = dwcmshc_set_uhs_signaling,
-- .get_max_clock = sdhci_pltfm_clk_get_max_clock,
-+ .get_max_clock = rk35xx_get_max_clock,
- .reset = rk35xx_sdhci_reset,
- .adma_write_desc = dwcmshc_adma_write_desc,
- };
+++ /dev/null
-From 004589ff9df5b75672a78b6c3c4cba93202b14c9 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 25 Mar 2023 15:40:20 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C
-
-The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
-chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3328-nanopi-r2c.dts | 40 +++++++++++++++++++
- 2 files changed, 41 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
-@@ -0,0 +1,40 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3328-nanopi-r2s.dts"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R2C";
-+ compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
-+};
-+
-+&gmac2io {
-+ phy-handle = <&yt8521s>;
-+ tx_delay = <0x22>;
-+ rx_delay = <0x12>;
-+
-+ mdio {
-+ /delete-node/ ethernet-phy@1;
-+
-+ yt8521s: ethernet-phy@3 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <3>;
-+
-+ motorcomm,clk-out-frequency-hz = <125000000>;
-+ motorcomm,keep-pll-enabled;
-+ motorcomm,auto-sleep-disabled;
-+
-+ pinctrl-0 = <ð_phy_reset_pin>;
-+ pinctrl-names = "default";
-+ reset-assert-us = <10000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+};
+++ /dev/null
-From 51712e1d014aaaa4c6e1e7e84932d58b5c0f59ed Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Sat, 3 Dec 2022 15:41:49 +0800
-Subject: [PATCH] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus
-
-Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
-
-This device is similar to the NanoPi R2S, and has a 16MB
-SPI NOR (mx25l12805d). The reset button is changed to
-directly reset the power supply, another detail is that
-both network ports have independent MAC addresses.
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../dts/rockchip/rk3328-orangepi-r1-plus.dts | 373 ++++++++++++++++++
- 2 files changed, 374 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-@@ -0,0 +1,373 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Based on rk3328-nanopi-r2s.dts, which is:
-+ * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
-+ */
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include "rk3328.dtsi"
-+
-+/ {
-+ model = "Xunlong Orange Pi R1 Plus";
-+ compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
-+
-+ aliases {
-+ ethernet1 = &rtl8153;
-+ mmc0 = &sdmmc;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ gmac_clk: gmac-clock {
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ clock-output-names = "gmac_clkin";
-+ #clock-cells = <0>;
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
-+ pinctrl-names = "default";
-+
-+ led-0 {
-+ function = LED_FUNCTION_LAN;
-+ color = <LED_COLOR_ID_GREEN>;
-+ gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ led-1 {
-+ function = LED_FUNCTION_STATUS;
-+ color = <LED_COLOR_ID_RED>;
-+ gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
-+ linux,default-trigger = "heartbeat";
-+ };
-+
-+ led-2 {
-+ function = LED_FUNCTION_WAN;
-+ color = <LED_COLOR_ID_GREEN>;
-+ gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+
-+ vcc_sd: sdmmc-regulator {
-+ compatible = "regulator-fixed";
-+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
-+ pinctrl-0 = <&sdmmc0m1_pin>;
-+ pinctrl-names = "default";
-+ regulator-name = "vcc_sd";
-+ regulator-boot-on;
-+ vin-supply = <&vcc_io>;
-+ };
-+
-+ vcc_sys: vcc-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vdd_5v_lan: vdd-5v-lan-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-0 = <&lan_vdd_pin>;
-+ pinctrl-names = "default";
-+ regulator-name = "vdd_5v_lan";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ vin-supply = <&vcc_sys>;
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_arm>;
-+};
-+
-+&display_subsystem {
-+ status = "disabled";
-+};
-+
-+&gmac2io {
-+ assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
-+ assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
-+ clock_in_out = "input";
-+ phy-handle = <&rtl8211e>;
-+ phy-mode = "rgmii";
-+ phy-supply = <&vcc_io>;
-+ pinctrl-0 = <&rgmiim1_pins>;
-+ pinctrl-names = "default";
-+ snps,aal;
-+ rx_delay = <0x18>;
-+ tx_delay = <0x24>;
-+ status = "okay";
-+
-+ mdio {
-+ compatible = "snps,dwmac-mdio";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ rtl8211e: ethernet-phy@1 {
-+ reg = <1>;
-+ pinctrl-0 = <ð_phy_reset_pin>;
-+ pinctrl-names = "default";
-+ reset-assert-us = <10000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+};
-+
-+&i2c1 {
-+ status = "okay";
-+
-+ rk805: pmic@18 {
-+ compatible = "rockchip,rk805";
-+ reg = <0x18>;
-+ interrupt-parent = <&gpio1>;
-+ interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <1>;
-+ clock-output-names = "xin32k", "rk805-clkout2";
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ pinctrl-0 = <&pmic_int_l>;
-+ pinctrl-names = "default";
-+ rockchip,system-power-controller;
-+ wakeup-source;
-+
-+ vcc1-supply = <&vcc_sys>;
-+ vcc2-supply = <&vcc_sys>;
-+ vcc3-supply = <&vcc_sys>;
-+ vcc4-supply = <&vcc_sys>;
-+ vcc5-supply = <&vcc_io>;
-+ vcc6-supply = <&vcc_sys>;
-+
-+ regulators {
-+ vdd_log: DCDC_REG1 {
-+ regulator-name = "vdd_log";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1450000>;
-+ regulator-ramp-delay = <12500>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1000000>;
-+ };
-+ };
-+
-+ vdd_arm: DCDC_REG2 {
-+ regulator-name = "vdd_arm";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1450000>;
-+ regulator-ramp-delay = <12500>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <950000>;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc_io: DCDC_REG4 {
-+ regulator-name = "vcc_io";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcc_18: LDO_REG1 {
-+ regulator-name = "vcc_18";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcc18_emmc: LDO_REG2 {
-+ regulator-name = "vcc18_emmc";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vdd_10: LDO_REG3 {
-+ regulator-name = "vdd_10";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1000000>;
-+ regulator-max-microvolt = <1000000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1000000>;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&io_domains {
-+ pmuio-supply = <&vcc_io>;
-+ vccio1-supply = <&vcc_io>;
-+ vccio2-supply = <&vcc18_emmc>;
-+ vccio3-supply = <&vcc_io>;
-+ vccio4-supply = <&vcc_io>;
-+ vccio5-supply = <&vcc_io>;
-+ vccio6-supply = <&vcc_io>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ gmac2io {
-+ eth_phy_reset_pin: eth-phy-reset-pin {
-+ rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+ };
-+
-+ leds {
-+ lan_led_pin: lan-led-pin {
-+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ sys_led_pin: sys-led-pin {
-+ rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wan_led_pin: wan-led-pin {
-+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ lan {
-+ lan_vdd_pin: lan-vdd-pin {
-+ rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int_l: pmic-int-l {
-+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+};
-+
-+&pwm2 {
-+ status = "okay";
-+};
-+
-+&sdmmc {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
-+ pinctrl-names = "default";
-+ vmmc-supply = <&vcc_sd>;
-+ status = "okay";
-+};
-+
-+&spi0 {
-+ status = "okay";
-+
-+ flash@0 {
-+ compatible = "jedec,spi-nor";
-+ reg = <0>;
-+ spi-max-frequency = <50000000>;
-+ };
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <0>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&u2phy {
-+ status = "okay";
-+};
-+
-+&u2phy_host {
-+ status = "okay";
-+};
-+
-+&u2phy_otg {
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb20_otg {
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
-+&usbdrd3 {
-+ dr_mode = "host";
-+ status = "okay";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ /* Second port is for USB 3.0 */
-+ rtl8153: device@2 {
-+ compatible = "usbbda,8153";
-+ reg = <2>;
-+ };
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
+++ /dev/null
-From 387b3bbac5ea6a0a105d685237f033ffe0f184f1 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 25 Mar 2023 15:40:22 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS
-
-The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
-the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
-identical to OrangePi R1 Plus.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../rockchip/rk3328-orangepi-r1-plus-lts.dts | 40 +++++++++++++++++++
- 2 files changed, 41 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -13,6 +13,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-@@ -0,0 +1,40 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
-+ * (http://www.orangepi.org)
-+ *
-+ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3328-orangepi-r1-plus.dts"
-+
-+/ {
-+ model = "Xunlong Orange Pi R1 Plus LTS";
-+ compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
-+};
-+
-+&gmac2io {
-+ phy-handle = <&yt8531c>;
-+ tx_delay = <0x19>;
-+ rx_delay = <0x05>;
-+
-+ mdio {
-+ /delete-node/ ethernet-phy@1;
-+
-+ yt8531c: ethernet-phy@0 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <0>;
-+
-+ motorcomm,clk-out-frequency-hz = <125000000>;
-+ motorcomm,keep-pll-enabled;
-+ motorcomm,auto-sleep-disabled;
-+
-+ pinctrl-0 = <ð_phy_reset_pin>;
-+ pinctrl-names = "default";
-+ reset-assert-us = <15000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+};
+++ /dev/null
-From c6629b9a6738a64507478527da6c7b83c10a6d2c Mon Sep 17 00:00:00 2001
-From: Vasily Khoruzhick <anarsoul@gmail.com>
-Date: Tue, 7 Mar 2023 22:32:40 -0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyElec Nanopi R5S
-
-FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device.
-
-Board Specifications
-- Rockchip RK3568
-- 2 or 4GB LPDDR4X
-- 8GB or 16GB eMMC, SD card slot
-- GbE LAN (Native)
-- 2x 2.5G LAN (PCIe)
-- M.2 Connector
-- HDMI 2.0, MIPI DSI/CSI
-- 2xUSB 3.0 Host
-- USB Type C PD, 5V/9V/12V
-- GPIO: 12-pin 0.5mm FPC connector
-
-Based on Tianling Shen's <cnsztl@gmail.com> work.
-
-Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
-Link: https://lore.kernel.org/r/20230308063240.107178-2-anarsoul@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 713 ++++++++++++++++++
- 2 files changed, 714 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -74,4 +74,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -0,0 +1,713 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyelec.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R5S";
-+ compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
-+
-+ aliases {
-+ ethernet0 = &gmac0;
-+ mmc0 = &sdmmc0;
-+ mmc1 = &sdhci;
-+ };
-+
-+ chosen: chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ hdmi-con {
-+ compatible = "hdmi-connector";
-+ type = "a";
-+
-+ port {
-+ hdmi_con_in: endpoint {
-+ remote-endpoint = <&hdmi_out_con>;
-+ };
-+ };
-+ };
-+
-+ gpio-leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
-+
-+ led-lan1 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_LAN;
-+ function-enumerator = <1>;
-+ gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ led-lan2 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_LAN;
-+ function-enumerator = <2>;
-+ gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ power_led: led-power {
-+ color = <LED_COLOR_ID_RED>;
-+ function = LED_FUNCTION_POWER;
-+ linux,default-trigger = "heartbeat";
-+ gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ led-wan {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_WAN;
-+ gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+
-+ vdd_usbc: vdd-usbc-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vdd_usbc";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vcc3v3_sys: vcc3v3-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc5v0_sys: vcc5v0-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc3v3_pcie: vcc3v3-pcie-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_pcie";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ enable-active-high;
-+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-+ startup-delay-us = <200000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc5v0_usb: vcc5v0-usb-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_usb";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb_host_en>;
-+ regulator-name = "vcc5v0_usb_host";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_usb>;
-+ };
-+
-+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
-+ regulator-name = "vcc5v0_usb_otg";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_usb>;
-+ };
-+
-+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+};
-+
-+&combphy0 {
-+ status = "okay";
-+};
-+
-+&combphy1 {
-+ status = "okay";
-+};
-+
-+&combphy2 {
-+ status = "okay";
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gmac0 {
-+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
-+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
-+ assigned-clock-rates = <0>, <125000000>;
-+ clock_in_out = "output";
-+ phy-handle = <&rgmii_phy0>;
-+ phy-mode = "rgmii-id";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac0_miim
-+ &gmac0_tx_bus2
-+ &gmac0_rx_bus2
-+ &gmac0_rgmii_clk
-+ &gmac0_rgmii_bus>;
-+ snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
-+ snps,reset-active-low;
-+ /* Reset time is 15ms, 50ms for rtl8211f */
-+ snps,reset-delays-us = <0 15000 50000>;
-+ tx_delay = <0x3c>;
-+ rx_delay = <0x2f>;
-+ status = "okay";
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu>;
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ avdd-0v9-supply = <&vdda0v9_image>;
-+ avdd-1v8-supply = <&vcca1v8_image>;
-+ status = "okay";
-+};
-+
-+&hdmi_in {
-+ hdmi_in_vp0: endpoint {
-+ remote-endpoint = <&vp0_out_hdmi>;
-+ };
-+};
-+
-+&hdmi_out {
-+ hdmi_out_con: endpoint {
-+ remote-endpoint = <&hdmi_con_in>;
-+ };
-+};
-+
-+&hdmi_sound {
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ vdd_cpu: regulator@1c {
-+ compatible = "tcs,tcs4525";
-+ reg = <0x1c>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1150000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ rk809: pmic@20 {
-+ compatible = "rockchip,rk809";
-+ reg = <0x20>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int>;
-+ rockchip,system-power-controller;
-+ vcc1-supply = <&vcc3v3_sys>;
-+ vcc2-supply = <&vcc3v3_sys>;
-+ vcc3-supply = <&vcc3v3_sys>;
-+ vcc4-supply = <&vcc3v3_sys>;
-+ vcc5-supply = <&vcc3v3_sys>;
-+ vcc6-supply = <&vcc3v3_sys>;
-+ vcc7-supply = <&vcc3v3_sys>;
-+ vcc8-supply = <&vcc3v3_sys>;
-+ vcc9-supply = <&vcc3v3_sys>;
-+ wakeup-source;
-+
-+ regulators {
-+ vdd_logic: DCDC_REG1 {
-+ regulator-name = "vdd_logic";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_gpu: DCDC_REG2 {
-+ regulator-name = "vdd_gpu";
-+ regulator-always-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vdd_npu: DCDC_REG4 {
-+ regulator-name = "vdd_npu";
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8: DCDC_REG5 {
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_image: LDO_REG1 {
-+ regulator-name = "vdda0v9_image";
-+ regulator-min-microvolt = <950000>;
-+ regulator-max-microvolt = <950000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda_0v9: LDO_REG2 {
-+ regulator-name = "vdda_0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_pmu: LDO_REG3 {
-+ regulator-name = "vdda0v9_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vccio_acodec: LDO_REG4 {
-+ regulator-name = "vccio_acodec";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd: LDO_REG5 {
-+ regulator-name = "vccio_sd";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_pmu: LDO_REG6 {
-+ regulator-name = "vcc3v3_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcca_1v8: LDO_REG7 {
-+ regulator-name = "vcca_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca1v8_pmu: LDO_REG8 {
-+ regulator-name = "vcca1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcca1v8_image: LDO_REG9 {
-+ regulator-name = "vcca1v8_image";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_3v3: SWITCH_REG1 {
-+ regulator-name = "vcc_3v3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_sd: SWITCH_REG2 {
-+ regulator-name = "vcc3v3_sd";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+
-+ };
-+};
-+
-+&i2c5 {
-+ status = "okay";
-+
-+ hym8563: rtc@51 {
-+ compatible = "haoyu,hym8563";
-+ reg = <0x51>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <0>;
-+ clock-output-names = "rtcic_32kout";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hym8563_int>;
-+ wakeup-source;
-+ };
-+};
-+
-+&i2s0_8ch {
-+ status = "okay";
-+};
-+
-+&i2s1_8ch {
-+ rockchip,trcm-sync-tx-only;
-+ status = "okay";
-+};
-+
-+&mdio0 {
-+ rgmii_phy0: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ pinctrl-0 = <ð_phy0_reset_pin>;
-+ pinctrl-names = "default";
-+ reset-assert-us = <10000>;
-+ reset-deassert-us = <50000>;
-+ reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
-+ };
-+};
-+
-+&pcie2x1 {
-+ num-lanes = <1>;
-+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+};
-+
-+&pcie30phy {
-+ data-lanes = <1 2>;
-+ status = "okay";
-+};
-+
-+&pcie3x1 {
-+ num-lanes = <1>;
-+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie>;
-+ status = "okay";
-+};
-+
-+&pcie3x2 {
-+ num-lanes = <1>;
-+ num-ib-windows = <8>;
-+ num-ob-windows = <8>;
-+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ gmac0 {
-+ eth_phy0_reset_pin: eth-phy0-reset-pin {
-+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
-+ };
-+ };
-+
-+ gpio-leds {
-+ lan1_led_pin: lan1-led-pin {
-+ rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ lan2_led_pin: lan2-led-pin {
-+ rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ power_led_pin: power-led-pin {
-+ rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wan_led_pin: wan-led-pin {
-+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ hym8563 {
-+ hym8563_int: hym8563-int {
-+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int: pmic-int {
-+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ usb {
-+ vcc5v0_usb_host_en: vcc5v0-usb-host-en {
-+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
-+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pmu_io_domains {
-+ pmuio1-supply = <&vcc3v3_pmu>;
-+ pmuio2-supply = <&vcc3v3_pmu>;
-+ vccio1-supply = <&vccio_acodec>;
-+ vccio3-supply = <&vccio_sd>;
-+ vccio4-supply = <&vcc_1v8>;
-+ vccio5-supply = <&vcc_3v3>;
-+ vccio6-supply = <&vcc_1v8>;
-+ vccio7-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ max-frequency = <200000000>;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
-+ status = "okay";
-+};
-+
-+&sdmmc0 {
-+ max-frequency = <150000000>;
-+ no-sdio;
-+ no-mmc;
-+ bus-width = <4>;
-+ cap-mmc-highspeed;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ vmmc-supply = <&vcc3v3_sd>;
-+ vqmmc-supply = <&vccio_sd>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <1>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ extcon = <&usb2phy0>;
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+ status = "okay";
-+};
-+
-+&usb2phy0 {
-+ status = "okay";
-+};
-+
-+&usb2phy0_host {
-+ phy-supply = <&vcc5v0_usb_host>;
-+ status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+ status = "okay";
-+};
-+
-+&usb2phy1 {
-+ status = "okay";
-+};
-+
-+&usb2phy1_host {
-+ phy-supply = <&vcc5v0_usb_otg>;
-+ status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+ status = "okay";
-+};
-+
-+&vop {
-+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+ status = "okay";
-+};
-+
-+&vop_mmu {
-+ status = "okay";
-+};
-+
-+&vp0 {
-+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+ remote-endpoint = <&hdmi_in_vp0>;
-+ };
-+};
+++ /dev/null
-From c8ec73b05a95d9f0969ae0f28dd8799a54fcdfc7 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:41 +0800
-Subject: [PATCH] arm64: dts: rockchip: create common dtsi for NanoPi R5 series
-
-Create common dtsi for the FriendlyElec NanoPi R5 series.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-2-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3568-nanopi-r5s.dts | 575 +----------------
- .../boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 596 ++++++++++++++++++
- 2 files changed, 597 insertions(+), 574 deletions(-)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -7,12 +7,7 @@
- */
-
- /dts-v1/;
--#include <dt-bindings/gpio/gpio.h>
--#include <dt-bindings/input/input.h>
--#include <dt-bindings/leds/common.h>
--#include <dt-bindings/pinctrl/rockchip.h>
--#include <dt-bindings/soc/rockchip,vop2.h>
--#include "rk3568.dtsi"
-+#include "rk3568-nanopi-r5s.dtsi"
-
- / {
- model = "FriendlyElec NanoPi R5S";
-@@ -20,23 +15,6 @@
-
- aliases {
- ethernet0 = &gmac0;
-- mmc0 = &sdmmc0;
-- mmc1 = &sdhci;
-- };
--
-- chosen: chosen {
-- stdout-path = "serial2:1500000n8";
-- };
--
-- hdmi-con {
-- compatible = "hdmi-connector";
-- type = "a";
--
-- port {
-- hdmi_con_in: endpoint {
-- remote-endpoint = <&hdmi_out_con>;
-- };
-- };
- };
-
- gpio-leds {
-@@ -71,130 +49,6 @@
- gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
- };
- };
--
-- vdd_usbc: vdd-usbc-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vdd_usbc";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- };
--
-- vcc3v3_sys: vcc3v3-sys-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc3v3_sys";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- vin-supply = <&vdd_usbc>;
-- };
--
-- vcc5v0_sys: vcc5v0-sys-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc5v0_sys";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vdd_usbc>;
-- };
--
-- vcc3v3_pcie: vcc3v3-pcie-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc3v3_pcie";
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
-- enable-active-high;
-- gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-- startup-delay-us = <200000>;
-- vin-supply = <&vcc5v0_sys>;
-- };
--
-- vcc5v0_usb: vcc5v0-usb-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "vcc5v0_usb";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vdd_usbc>;
-- };
--
-- vcc5v0_usb_host: vcc5v0-usb-host-regulator {
-- compatible = "regulator-fixed";
-- enable-active-high;
-- gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&vcc5v0_usb_host_en>;
-- regulator-name = "vcc5v0_usb_host";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vcc5v0_usb>;
-- };
--
-- vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
-- compatible = "regulator-fixed";
-- enable-active-high;
-- gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&vcc5v0_usb_otg_en>;
-- regulator-name = "vcc5v0_usb_otg";
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vcc5v0_usb>;
-- };
--
-- pcie30_avdd0v9: pcie30-avdd0v9-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "pcie30_avdd0v9";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <900000>;
-- regulator-max-microvolt = <900000>;
-- vin-supply = <&vcc3v3_sys>;
-- };
--
-- pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-- compatible = "regulator-fixed";
-- regulator-name = "pcie30_avdd1v8";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
-- vin-supply = <&vcc3v3_sys>;
-- };
--};
--
--&combphy0 {
-- status = "okay";
--};
--
--&combphy1 {
-- status = "okay";
--};
--
--&combphy2 {
-- status = "okay";
--};
--
--&cpu0 {
-- cpu-supply = <&vdd_cpu>;
--};
--
--&cpu1 {
-- cpu-supply = <&vdd_cpu>;
--};
--
--&cpu2 {
-- cpu-supply = <&vdd_cpu>;
--};
--
--&cpu3 {
-- cpu-supply = <&vdd_cpu>;
- };
-
- &gmac0 {
-@@ -219,292 +73,6 @@
- status = "okay";
- };
-
--&gpu {
-- mali-supply = <&vdd_gpu>;
-- status = "okay";
--};
--
--&hdmi {
-- avdd-0v9-supply = <&vdda0v9_image>;
-- avdd-1v8-supply = <&vcca1v8_image>;
-- status = "okay";
--};
--
--&hdmi_in {
-- hdmi_in_vp0: endpoint {
-- remote-endpoint = <&vp0_out_hdmi>;
-- };
--};
--
--&hdmi_out {
-- hdmi_out_con: endpoint {
-- remote-endpoint = <&hdmi_con_in>;
-- };
--};
--
--&hdmi_sound {
-- status = "okay";
--};
--
--&i2c0 {
-- status = "okay";
--
-- vdd_cpu: regulator@1c {
-- compatible = "tcs,tcs4525";
-- reg = <0x1c>;
-- fcs,suspend-voltage-selector = <1>;
-- regulator-name = "vdd_cpu";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <800000>;
-- regulator-max-microvolt = <1150000>;
-- regulator-ramp-delay = <2300>;
-- vin-supply = <&vcc5v0_sys>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- rk809: pmic@20 {
-- compatible = "rockchip,rk809";
-- reg = <0x20>;
-- interrupt-parent = <&gpio0>;
-- interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-- #clock-cells = <1>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&pmic_int>;
-- rockchip,system-power-controller;
-- vcc1-supply = <&vcc3v3_sys>;
-- vcc2-supply = <&vcc3v3_sys>;
-- vcc3-supply = <&vcc3v3_sys>;
-- vcc4-supply = <&vcc3v3_sys>;
-- vcc5-supply = <&vcc3v3_sys>;
-- vcc6-supply = <&vcc3v3_sys>;
-- vcc7-supply = <&vcc3v3_sys>;
-- vcc8-supply = <&vcc3v3_sys>;
-- vcc9-supply = <&vcc3v3_sys>;
-- wakeup-source;
--
-- regulators {
-- vdd_logic: DCDC_REG1 {
-- regulator-name = "vdd_logic";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-init-microvolt = <900000>;
-- regulator-initial-mode = <0x2>;
-- regulator-min-microvolt = <500000>;
-- regulator-max-microvolt = <1350000>;
-- regulator-ramp-delay = <6001>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdd_gpu: DCDC_REG2 {
-- regulator-name = "vdd_gpu";
-- regulator-always-on;
-- regulator-init-microvolt = <900000>;
-- regulator-initial-mode = <0x2>;
-- regulator-min-microvolt = <500000>;
-- regulator-max-microvolt = <1350000>;
-- regulator-ramp-delay = <6001>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc_ddr: DCDC_REG3 {
-- regulator-name = "vcc_ddr";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-initial-mode = <0x2>;
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- };
-- };
--
-- vdd_npu: DCDC_REG4 {
-- regulator-name = "vdd_npu";
-- regulator-init-microvolt = <900000>;
-- regulator-initial-mode = <0x2>;
-- regulator-min-microvolt = <500000>;
-- regulator-max-microvolt = <1350000>;
-- regulator-ramp-delay = <6001>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc_1v8: DCDC_REG5 {
-- regulator-name = "vcc_1v8";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdda0v9_image: LDO_REG1 {
-- regulator-name = "vdda0v9_image";
-- regulator-min-microvolt = <950000>;
-- regulator-max-microvolt = <950000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdda_0v9: LDO_REG2 {
-- regulator-name = "vdda_0v9";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <900000>;
-- regulator-max-microvolt = <900000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vdda0v9_pmu: LDO_REG3 {
-- regulator-name = "vdda0v9_pmu";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <900000>;
-- regulator-max-microvolt = <900000>;
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <900000>;
-- };
-- };
--
-- vccio_acodec: LDO_REG4 {
-- regulator-name = "vccio_acodec";
-- regulator-always-on;
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vccio_sd: LDO_REG5 {
-- regulator-name = "vccio_sd";
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <3300000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc3v3_pmu: LDO_REG6 {
-- regulator-name = "vcc3v3_pmu";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <3300000>;
-- regulator-max-microvolt = <3300000>;
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <3300000>;
-- };
-- };
--
-- vcca_1v8: LDO_REG7 {
-- regulator-name = "vcca_1v8";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcca1v8_pmu: LDO_REG8 {
-- regulator-name = "vcca1v8_pmu";
-- regulator-always-on;
-- regulator-boot-on;
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
--
-- regulator-state-mem {
-- regulator-on-in-suspend;
-- regulator-suspend-microvolt = <1800000>;
-- };
-- };
--
-- vcca1v8_image: LDO_REG9 {
-- regulator-name = "vcca1v8_image";
-- regulator-min-microvolt = <1800000>;
-- regulator-max-microvolt = <1800000>;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc_3v3: SWITCH_REG1 {
-- regulator-name = "vcc_3v3";
-- regulator-always-on;
-- regulator-boot-on;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
--
-- vcc3v3_sd: SWITCH_REG2 {
-- regulator-name = "vcc3v3_sd";
-- regulator-always-on;
-- regulator-boot-on;
--
-- regulator-state-mem {
-- regulator-off-in-suspend;
-- };
-- };
-- };
--
-- };
--};
--
--&i2c5 {
-- status = "okay";
--
-- hym8563: rtc@51 {
-- compatible = "haoyu,hym8563";
-- reg = <0x51>;
-- interrupt-parent = <&gpio0>;
-- interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-- #clock-cells = <0>;
-- clock-output-names = "rtcic_32kout";
-- pinctrl-names = "default";
-- pinctrl-0 = <&hym8563_int>;
-- wakeup-source;
-- };
--};
--
--&i2s0_8ch {
-- status = "okay";
--};
--
--&i2s1_8ch {
-- rockchip,trcm-sync-tx-only;
-- status = "okay";
--};
--
- &mdio0 {
- rgmii_phy0: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
-@@ -568,146 +136,5 @@
- rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
--
-- hym8563 {
-- hym8563_int: hym8563-int {
-- rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-- };
-- };
--
-- pmic {
-- pmic_int: pmic-int {
-- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-- };
-- };
--
-- usb {
-- vcc5v0_usb_host_en: vcc5v0-usb-host-en {
-- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
--
-- vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
-- rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-- };
-- };
--};
--
--&pmu_io_domains {
-- pmuio1-supply = <&vcc3v3_pmu>;
-- pmuio2-supply = <&vcc3v3_pmu>;
-- vccio1-supply = <&vccio_acodec>;
-- vccio3-supply = <&vccio_sd>;
-- vccio4-supply = <&vcc_1v8>;
-- vccio5-supply = <&vcc_3v3>;
-- vccio6-supply = <&vcc_1v8>;
-- vccio7-supply = <&vcc_3v3>;
-- status = "okay";
--};
--
--&saradc {
-- vref-supply = <&vcca_1v8>;
-- status = "okay";
--};
--
--&sdhci {
-- bus-width = <8>;
-- max-frequency = <200000000>;
-- non-removable;
-- pinctrl-names = "default";
-- pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
-- status = "okay";
--};
--
--&sdmmc0 {
-- max-frequency = <150000000>;
-- no-sdio;
-- no-mmc;
-- bus-width = <4>;
-- cap-mmc-highspeed;
-- cap-sd-highspeed;
-- disable-wp;
-- vmmc-supply = <&vcc3v3_sd>;
-- vqmmc-supply = <&vccio_sd>;
-- pinctrl-names = "default";
-- pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-- status = "okay";
--};
--
--&tsadc {
-- rockchip,hw-tshut-mode = <1>;
-- rockchip,hw-tshut-polarity = <0>;
-- status = "okay";
--};
--
--&uart2 {
-- status = "okay";
--};
--
--&usb_host0_ehci {
-- status = "okay";
--};
--
--&usb_host0_ohci {
-- status = "okay";
--};
--
--&usb_host0_xhci {
-- extcon = <&usb2phy0>;
-- dr_mode = "host";
-- status = "okay";
--};
--
--&usb_host1_ehci {
-- status = "okay";
--};
--
--&usb_host1_ohci {
-- status = "okay";
- };
-
--&usb_host1_xhci {
-- status = "okay";
--};
--
--&usb2phy0 {
-- status = "okay";
--};
--
--&usb2phy0_host {
-- phy-supply = <&vcc5v0_usb_host>;
-- status = "okay";
--};
--
--&usb2phy0_otg {
-- status = "okay";
--};
--
--&usb2phy1 {
-- status = "okay";
--};
--
--&usb2phy1_host {
-- phy-supply = <&vcc5v0_usb_otg>;
-- status = "okay";
--};
--
--&usb2phy1_otg {
-- status = "okay";
--};
--
--&vop {
-- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-- status = "okay";
--};
--
--&vop_mmu {
-- status = "okay";
--};
--
--&vp0 {
-- vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-- reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-- remote-endpoint = <&hdmi_in_vp0>;
-- };
--};
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-@@ -0,0 +1,596 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyelec.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+ aliases {
-+ mmc0 = &sdmmc0;
-+ mmc1 = &sdhci;
-+ };
-+
-+ chosen: chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ hdmi-con {
-+ compatible = "hdmi-connector";
-+ type = "a";
-+
-+ port {
-+ hdmi_con_in: endpoint {
-+ remote-endpoint = <&hdmi_out_con>;
-+ };
-+ };
-+ };
-+
-+ vdd_usbc: vdd-usbc-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vdd_usbc";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vcc3v3_sys: vcc3v3-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc5v0_sys: vcc5v0-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc3v3_pcie: vcc3v3-pcie-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_pcie";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ enable-active-high;
-+ gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
-+ startup-delay-us = <200000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc5v0_usb: vcc5v0-usb-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_usb";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vdd_usbc>;
-+ };
-+
-+ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb_host_en>;
-+ regulator-name = "vcc5v0_usb_host";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_usb>;
-+ };
-+
-+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb_otg_en>;
-+ regulator-name = "vcc5v0_usb_otg";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_usb>;
-+ };
-+
-+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+};
-+
-+&combphy0 {
-+ status = "okay";
-+};
-+
-+&combphy1 {
-+ status = "okay";
-+};
-+
-+&combphy2 {
-+ status = "okay";
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu>;
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ avdd-0v9-supply = <&vdda0v9_image>;
-+ avdd-1v8-supply = <&vcca1v8_image>;
-+ status = "okay";
-+};
-+
-+&hdmi_in {
-+ hdmi_in_vp0: endpoint {
-+ remote-endpoint = <&vp0_out_hdmi>;
-+ };
-+};
-+
-+&hdmi_out {
-+ hdmi_out_con: endpoint {
-+ remote-endpoint = <&hdmi_con_in>;
-+ };
-+};
-+
-+&hdmi_sound {
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ vdd_cpu: regulator@1c {
-+ compatible = "tcs,tcs4525";
-+ reg = <0x1c>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1150000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v0_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ rk809: pmic@20 {
-+ compatible = "rockchip,rk809";
-+ reg = <0x20>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int>;
-+ rockchip,system-power-controller;
-+ vcc1-supply = <&vcc3v3_sys>;
-+ vcc2-supply = <&vcc3v3_sys>;
-+ vcc3-supply = <&vcc3v3_sys>;
-+ vcc4-supply = <&vcc3v3_sys>;
-+ vcc5-supply = <&vcc3v3_sys>;
-+ vcc6-supply = <&vcc3v3_sys>;
-+ vcc7-supply = <&vcc3v3_sys>;
-+ vcc8-supply = <&vcc3v3_sys>;
-+ vcc9-supply = <&vcc3v3_sys>;
-+ wakeup-source;
-+
-+ regulators {
-+ vdd_logic: DCDC_REG1 {
-+ regulator-name = "vdd_logic";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_gpu: DCDC_REG2 {
-+ regulator-name = "vdd_gpu";
-+ regulator-always-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vdd_npu: DCDC_REG4 {
-+ regulator-name = "vdd_npu";
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8: DCDC_REG5 {
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_image: LDO_REG1 {
-+ regulator-name = "vdda0v9_image";
-+ regulator-min-microvolt = <950000>;
-+ regulator-max-microvolt = <950000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda_0v9: LDO_REG2 {
-+ regulator-name = "vdda_0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_pmu: LDO_REG3 {
-+ regulator-name = "vdda0v9_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vccio_acodec: LDO_REG4 {
-+ regulator-name = "vccio_acodec";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd: LDO_REG5 {
-+ regulator-name = "vccio_sd";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_pmu: LDO_REG6 {
-+ regulator-name = "vcc3v3_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcca_1v8: LDO_REG7 {
-+ regulator-name = "vcca_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca1v8_pmu: LDO_REG8 {
-+ regulator-name = "vcca1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcca1v8_image: LDO_REG9 {
-+ regulator-name = "vcca1v8_image";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_3v3: SWITCH_REG1 {
-+ regulator-name = "vcc_3v3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_sd: SWITCH_REG2 {
-+ regulator-name = "vcc3v3_sd";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+
-+ };
-+};
-+
-+&i2c5 {
-+ status = "okay";
-+
-+ hym8563: rtc@51 {
-+ compatible = "haoyu,hym8563";
-+ reg = <0x51>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <0>;
-+ clock-output-names = "rtcic_32kout";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&hym8563_int>;
-+ wakeup-source;
-+ };
-+};
-+
-+&i2s0_8ch {
-+ status = "okay";
-+};
-+
-+&i2s1_8ch {
-+ rockchip,trcm-sync-tx-only;
-+ status = "okay";
-+};
-+
-+&pcie30phy {
-+ data-lanes = <1 2>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ hym8563 {
-+ hym8563_int: hym8563-int {
-+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int: pmic-int {
-+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ usb {
-+ vcc5v0_usb_host_en: vcc5v0-usb-host-en {
-+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
-+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pmu_io_domains {
-+ pmuio1-supply = <&vcc3v3_pmu>;
-+ pmuio2-supply = <&vcc3v3_pmu>;
-+ vccio1-supply = <&vccio_acodec>;
-+ vccio3-supply = <&vccio_sd>;
-+ vccio4-supply = <&vcc_1v8>;
-+ vccio5-supply = <&vcc_3v3>;
-+ vccio6-supply = <&vcc_1v8>;
-+ vccio7-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ max-frequency = <200000000>;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
-+ status = "okay";
-+};
-+
-+&sdmmc0 {
-+ max-frequency = <150000000>;
-+ no-sdio;
-+ no-mmc;
-+ bus-width = <4>;
-+ cap-mmc-highspeed;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ vmmc-supply = <&vcc3v3_sd>;
-+ vqmmc-supply = <&vccio_sd>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <1>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ extcon = <&usb2phy0>;
-+ dr_mode = "host";
-+ status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+ status = "okay";
-+};
-+
-+&usb2phy0 {
-+ status = "okay";
-+};
-+
-+&usb2phy0_host {
-+ phy-supply = <&vcc5v0_usb_host>;
-+ status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+ status = "okay";
-+};
-+
-+&usb2phy1 {
-+ status = "okay";
-+};
-+
-+&usb2phy1_host {
-+ phy-supply = <&vcc5v0_usb_otg>;
-+ status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+ status = "okay";
-+};
-+
-+&vop {
-+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+ status = "okay";
-+};
-+
-+&vop_mmu {
-+ status = "okay";
-+};
-+
-+&vp0 {
-+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+ remote-endpoint = <&hdmi_in_vp0>;
-+ };
-+};
+++ /dev/null
-From 31425b1fadb2040b359e52ffc24c049a78d56c96 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:44 +0800
-Subject: [PATCH] arm64: dts: rockchip: fix gmac support for NanoPi R5S
-
-- Changed phy-mode to rgmii.
-
-- Fixed pull type in pinctrl for gmac0.
-
-- Removed duplicate properties in mdio node.
- These properties are defined in the gmac0 node already.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-5-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
- 1 file changed, 2 insertions(+), 5 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -57,7 +57,7 @@
- assigned-clock-rates = <0>, <125000000>;
- clock_in_out = "output";
- phy-handle = <&rgmii_phy0>;
-- phy-mode = "rgmii-id";
-+ phy-mode = "rgmii";
- pinctrl-names = "default";
- pinctrl-0 = <&gmac0_miim
- &gmac0_tx_bus2
-@@ -79,9 +79,6 @@
- reg = <1>;
- pinctrl-0 = <ð_phy0_reset_pin>;
- pinctrl-names = "default";
-- reset-assert-us = <10000>;
-- reset-deassert-us = <50000>;
-- reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
- };
- };
-
-@@ -115,7 +112,7 @@
- &pinctrl {
- gmac0 {
- eth_phy0_reset_pin: eth-phy0-reset-pin {
-- rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
-+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
-
+++ /dev/null
-From 975e9bbad11950fc8276f1fa260d8bf2c341aa41 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:45 +0800
-Subject: [PATCH] arm64: dts: rockchip: remove I2S1 TDM node for the NanoPi R5
- series
-
-This is for the audio output which does not exist on the boards.
-Also disable regulator-always-on for vccio_acodec since it's only
-used by the audio output.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-6-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 6 ------
- 1 file changed, 6 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
-@@ -330,7 +330,6 @@
-
- vccio_acodec: LDO_REG4 {
- regulator-name = "vccio_acodec";
-- regulator-always-on;
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-
-@@ -441,11 +440,6 @@
- status = "okay";
- };
-
--&i2s1_8ch {
-- rockchip,trcm-sync-tx-only;
-- status = "okay";
--};
--
- &pcie30phy {
- data-lanes = <1 2>;
- status = "okay";
+++ /dev/null
-From 05620031408ac6cfc6d5c048431827e49aa0ade1 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 18 Mar 2023 16:37:43 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R5C
-
-FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device.
-
-Specification:
-- Rockchip RK3568
-- 1/4GB LPDDR4X RAM
-- 8/32GB eMMC
-- SD card slot
-- M.2 Connector
-- 2x USB 3.0 Port
-- 2x 2500 Base-T (PCIe, r8125)
-- HDMI 2.0
-- MIPI DSI/CSI
-- USB Type C 5V
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230318083745.6181-4-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3568-nanopi-r5c.dts | 112 ++++++++++++++++++
- 2 files changed, 113 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -74,5 +74,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-@@ -0,0 +1,112 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyelec.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3568-nanopi-r5s.dtsi"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R5C";
-+ compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
-+
-+ gpio-keys {
-+ compatible = "gpio-keys";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&reset_button_pin>;
-+
-+ button-reset {
-+ debounce-interval = <50>;
-+ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
-+ label = "reset";
-+ linux,code = <KEY_RESTART>;
-+ };
-+ };
-+
-+ gpio-leds {
-+ compatible = "gpio-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
-+
-+ led-lan {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_LAN;
-+ gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ power_led: led-power {
-+ color = <LED_COLOR_ID_RED>;
-+ function = LED_FUNCTION_POWER;
-+ linux,default-trigger = "heartbeat";
-+ gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ led-wan {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_WAN;
-+ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ led-wlan {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_WLAN;
-+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
-+ };
-+ };
-+};
-+
-+&pcie2x1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie20_reset_pin>;
-+ reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
-+ status = "okay";
-+};
-+
-+&pcie3x1 {
-+ num-lanes = <1>;
-+ reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie>;
-+ status = "okay";
-+};
-+
-+&pcie3x2 {
-+ num-lanes = <1>;
-+ reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ gpio-leds {
-+ lan_led_pin: lan-led-pin {
-+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ power_led_pin: power-led-pin {
-+ rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wan_led_pin: wan-led-pin {
-+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wlan_led_pin: wlan-led-pin {
-+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pcie {
-+ pcie20_reset_pin: pcie20-reset-pin {
-+ rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ rockchip-key {
-+ reset_button_pin: reset-button-pin {
-+ rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+};
+++ /dev/null
-From 5325593377f07de31f7e473a9677a28a04c891f3 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Thu, 11 May 2023 00:18:50 +0800
-Subject: [PATCH] arm64: dts: rockchip: fix button reset pin for nanopi r5c
-
-The reset pin was wrongly assigned due to a copy/paste error,
-fix it to match actual gpio pin.
-
-While at it, remove a blank line from nanopi r5s dts.
-
-Fixes: 05620031408a ("arm64: dts: rockchip: Add FriendlyARM NanoPi R5C")
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230510161850.4866-1-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts | 2 +-
- arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 1 -
- 2 files changed, 1 insertion(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
-@@ -106,7 +106,7 @@
-
- rockchip-key {
- reset_button_pin: reset-button-pin {
-- rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
-+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
- };
- };
- };
---- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
-@@ -134,4 +134,3 @@
- };
- };
- };
--
+++ /dev/null
-From fc5a80a432607d05e85bba37971712405f75c546 Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 16 Dec 2023 12:07:23 +0800
-Subject: [PATCH] arm64: dts: rockchip: configure eth pad driver strength
- for orangepi r1 plus lts
-
-The default strength is not enough to provide stable connection
-under 3.3v LDO voltage.
-
-Fixes: 387b3bbac5ea ("arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus LTS")
-Cc: stable@vger.kernel.org # 6.6+
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20231216040723.17864-1-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-@@ -26,9 +26,11 @@
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <0>;
-
-+ motorcomm,auto-sleep-disabled;
- motorcomm,clk-out-frequency-hz = <125000000>;
- motorcomm,keep-pll-enabled;
-- motorcomm,auto-sleep-disabled;
-+ motorcomm,rx-clk-drv-microamp = <5020>;
-+ motorcomm,rx-data-drv-microamp = <5020>;
-
- pinctrl-0 = <ð_phy_reset_pin>;
- pinctrl-names = "default";
+++ /dev/null
-From 096ebfb74b19f2d4bdcbc33ae02e857ff4b3e0a0 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Thu, 12 Jan 2023 16:29:02 +0530
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa Compute Module 3 IO board
-
-Radxa Compute Module 3(CM3) IO board is an application board from Radxa
-and is compatible with Raspberry Pi CM4 IO form factor.
-
-Specification:
-- 1x HDMI,
-- 2x MIPI DSI
-- 2x MIPI CSI2
-- 1x eDP
-- 1x PCIe card
-- 2x SATA
-- 2x USB 2.0 Host
-- 1x USB 3.0
-- 1x USB 2.0 OTG
-- Phone jack
-- microSD slot
-- 40-pin GPIO expansion header
-- 12V DC
-
-Radxa CM3 needs to mount on top of this IO board in order to create
-complete Radxa CM3 IO board platform.
-
-Add support for Radxa CM3 IO Board.
-
-Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
-Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230112105902.192852-3-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 179 ++++++++++++++++++
- 2 files changed, 180 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -0,0 +1,179 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2022 Radxa Limited
-+ * Copyright (c) 2022 Amarula Solutions(India)
-+ */
-+
-+/dts-v1/;
-+#include <dt-bindings/soc/rockchip,vop2.h>
-+#include "rk3566.dtsi"
-+#include "rk3566-radxa-cm3.dtsi"
-+
-+/ {
-+ model = "Radxa Compute Module 3(CM3) IO Board";
-+ compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
-+
-+ aliases {
-+ mmc1 = &sdmmc0;
-+ };
-+
-+ chosen: chosen {
-+ stdout-path = "serial2:1500000n8";
-+ };
-+
-+ hdmi-con {
-+ compatible = "hdmi-connector";
-+ type = "a";
-+
-+ port {
-+ hdmi_con_in: endpoint {
-+ remote-endpoint = <&hdmi_out_con>;
-+ };
-+ };
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ led-1 {
-+ gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>;
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_ACTIVITY;
-+ linux,default-trigger = "heartbeat";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pi_nled_activity>;
-+ };
-+ };
-+
-+ vcc5v0_usb30: vcc5v0-usb30-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_usb30";
-+ enable-active-high;
-+ gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vcc5v0_usb30_en_h>;
-+ regulator-always-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc_sys>;
-+ };
-+
-+ vcca1v8_image: vcca1v8-image-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcca1v8_image";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc_1v8_p>;
-+ };
-+
-+ vdda0v9_image: vdda0v9-image-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcca0v9_image";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ vin-supply = <&vdda_0v9>;
-+ };
-+};
-+
-+&combphy1 {
-+ status = "okay";
-+};
-+
-+&hdmi {
-+ avdd-0v9-supply = <&vdda0v9_image>;
-+ avdd-1v8-supply = <&vcca1v8_image>;
-+ status = "okay";
-+};
-+
-+&hdmi_in {
-+ hdmi_in_vp0: endpoint {
-+ remote-endpoint = <&vp0_out_hdmi>;
-+ };
-+};
-+
-+&hdmi_out {
-+ hdmi_out_con: endpoint {
-+ remote-endpoint = <&hdmi_con_in>;
-+ };
-+};
-+
-+&hdmi_sound {
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ leds {
-+ pi_nled_activity: pi-nled-activity {
-+ rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ sdcard {
-+ sdmmc_pwren: sdmmc-pwren {
-+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ usb {
-+ vcc5v0_usb30_en_h: vcc5v0-host-en-h {
-+ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&sdmmc0 {
-+ bus-width = <4>;
-+ cap-mmc-highspeed;
-+ cap-sd-highspeed;
-+ disable-wp;
-+ vqmmc-supply = <&vccio_sd>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb2phy0_host {
-+ phy-supply = <&vcc5v0_usb30>;
-+ status = "okay";
-+};
-+
-+&usb2phy1_host {
-+ status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_xhci {
-+ status = "okay";
-+};
-+
-+&vop {
-+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
-+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
-+ status = "okay";
-+};
-+
-+&vop_mmu {
-+ status = "okay";
-+};
-+
-+&vp0 {
-+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
-+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
-+ remote-endpoint = <&hdmi_in_vp0>;
-+ };
-+};
+++ /dev/null
-From d211665c5a833873ee37e501af58adbf028e6b5f Mon Sep 17 00:00:00 2001
-From: Tianling Shen <cnsztl@gmail.com>
-Date: Sat, 13 May 2023 21:53:07 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C Plus
-
-The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
-eMMC flash (8G) included.
-
-Signed-off-by: Tianling Shen <cnsztl@gmail.com>
-Link: https://lore.kernel.org/r/20230513135307.26554-2-cnsztl@gmail.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts | 33 ++++++++++++++++++++++
- 2 files changed, 34 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
-@@ -0,0 +1,33 @@
-+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-+/*
-+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
-+ */
-+
-+/dts-v1/;
-+#include "rk3328-nanopi-r2c.dts"
-+
-+/ {
-+ model = "FriendlyElec NanoPi R2C Plus";
-+ compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
-+
-+ aliases {
-+ mmc1 = &emmc;
-+ };
-+};
-+
-+&emmc {
-+ bus-width = <8>;
-+ cap-mmc-highspeed;
-+ max-frequency = <150000000>;
-+ mmc-ddr-1_8v;
-+ mmc-hs200-1_8v;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
-+ vmmc-supply = <&vcc_io_33>;
-+ vqmmc-supply = <&vcc18_emmc>;
-+ status = "okay";
-+};
+++ /dev/null
-From cc52bfc04726a574fc4440bbbe0c710890e7040a Mon Sep 17 00:00:00 2001
-From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Date: Wed, 25 Jan 2023 21:40:22 +0530
-Subject: [PATCH] arm64: dts: rockchip: Enable Ethernet for Radxa CM3 IO
-
-Add ethernet nodes for enabling gmac1 on the Radxa CM3 IO board.
-
-Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230125161023.12115-1-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 93 +++++++++++++++++++
- 1 file changed, 93 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -21,6 +21,13 @@
- stdout-path = "serial2:1500000n8";
- };
-
-+ gmac1_clkin: external-gmac1-clock {
-+ compatible = "fixed-clock";
-+ clock-frequency = <125000000>;
-+ clock-output-names = "gmac1_clkin";
-+ #clock-cells = <0>;
-+ };
-+
- hdmi-con {
- compatible = "hdmi-connector";
- type = "a";
-@@ -83,6 +90,29 @@
- status = "okay";
- };
-
-+&gmac1 {
-+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
-+ assigned-clock-rates = <0>, <125000000>;
-+ clock_in_out = "input";
-+ phy-handle = <&rgmii_phy1>;
-+ phy-mode = "rgmii";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&gmac1m0_miim
-+ &gmac1m0_tx_bus2
-+ &gmac1m0_rx_bus2
-+ &gmac1m0_rgmii_clk
-+ &gmac1m0_rgmii_bus
-+ &gmac1m0_clkinout>;
-+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
-+ snps,reset-active-low;
-+ /* Reset time is 20ms, 100ms for rtl8211f */
-+ snps,reset-delays-us = <0 20000 100000>;
-+ tx_delay = <0x46>;
-+ rx_delay = <0x2e>;
-+ status = "okay";
-+};
-+
- &hdmi {
- avdd-0v9-supply = <&vdda0v9_image>;
- avdd-1v8-supply = <&vcca1v8_image>;
-@@ -105,7 +135,70 @@
- status = "okay";
- };
-
-+&mdio1 {
-+ rgmii_phy1: ethernet-phy@0 {
-+ compatible="ethernet-phy-ieee802.3-c22";
-+ reg= <0x0>;
-+ };
-+};
-+
- &pinctrl {
-+ gmac1 {
-+ gmac1m0_miim: gmac1m0-miim {
-+ rockchip,pins =
-+ /* gmac1_mdcm0 */
-+ <3 RK_PC4 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_mdiom0 */
-+ <3 RK_PC5 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+
-+ gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
-+ rockchip,pins =
-+ /* gmac1_rxd0m0 */
-+ <3 RK_PB1 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_rxd1m0 */
-+ <3 RK_PB2 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_rxdvcrsm0 */
-+ <3 RK_PB3 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+
-+ gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
-+ rockchip,pins =
-+ /* gmac1_txd0m0 */
-+ <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_txd1m0 */
-+ <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_txenm0 */
-+ <3 RK_PB7 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+
-+ gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
-+ rockchip,pins =
-+ /* gmac1_rxclkm0 */
-+ <3 RK_PA7 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_txclkm0 */
-+ <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+
-+ gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
-+ rockchip,pins =
-+ /* gmac1_rxd2m0 */
-+ <3 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_rxd3m0 */
-+ <3 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_txd2m0 */
-+ <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
-+ /* gmac1_txd3m0 */
-+ <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+
-+ gmac1m0_clkinout: gmac1m0-clkinout {
-+ rockchip,pins =
-+ /* gmac1_mclkinoutm0 */
-+ <3 RK_PC0 3 &pcfg_pull_none_drv_level_15>;
-+ };
-+ };
-+
- leds {
- pi_nled_activity: pi-nled-activity {
- rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+++ /dev/null
-From 7469ab529bcad50490f6ff651c3e4f03bfa88fe0 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Thu, 12 Jan 2023 16:29:01 +0530
-Subject: [PATCH] arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Radxa Compute Module 3(CM3) is one of the modules from a series
-System On Module based on the Radxa ROCK 3 series and is compatible
-with Raspberry Pi CM4 pinout and form factor.
-
-Specification:
-- Rockchip RK3566
-- up to 8GB LPDDR4
-- up to 128GB high performance eMMC
-- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless,
- BT 5.0, BLE with onboard and external antenna.
-- Gigabit Ethernet PHY
-
-Radxa CM3 needs to mount on top of this IO board in order to create
-complete Radxa CM3 IO board platform.
-
-Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is
-possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board.
-
-Add support for Radxa CM3.
-
-Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230112105902.192852-2-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 345 ++++++++++++++++++
- 1 file changed, 345 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-@@ -0,0 +1,345 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2022 Radxa Limited
-+ * Copyright (c) 2022 Amarula Solutions(India)
-+ */
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+
-+/ {
-+ compatible = "radxa,radxa-cm3", "rockchip,rk3566";
-+
-+ aliases {
-+ mmc0 = &sdhci;
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ led-0 {
-+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_STATUS;
-+ linux,default-trigger = "timer";
-+ default-state = "on";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&user_led2>;
-+ };
-+ };
-+
-+ vcc_sys: vcc-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ vcc_1v8: vcc-1v8-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc_1v8_p>;
-+ };
-+
-+ vcc_3v3: vcc-3v3-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc_3v3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ vcca_1v8: vcca-1v8-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcca_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc_1v8_p>;
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu_npu>;
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ vdd_cpu: regulator@1c {
-+ compatible = "tcs,tcs4525";
-+ reg = <0x1c>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <712500>;
-+ regulator-max-microvolt = <1390000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc_sys>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ rk817: pmic@20 {
-+ compatible = "rockchip,rk817";
-+ reg = <0x20>;
-+ #clock-cells = <1>;
-+ clock-output-names = "rk817-clkout1", "rk817-clkout2";
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int_l>;
-+ rockchip,system-power-controller;
-+ wakeup-source;
-+
-+ vcc1-supply = <&vcc_sys>;
-+ vcc2-supply = <&vcc_sys>;
-+ vcc3-supply = <&vcc_sys>;
-+ vcc4-supply = <&vcc_sys>;
-+ vcc5-supply = <&vcc_sys>;
-+ vcc6-supply = <&vcc_sys>;
-+ vcc7-supply = <&vcc_sys>;
-+
-+ regulators {
-+ vdd_logic: DCDC_REG1 {
-+ regulator-name = "vdd_logic";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vdd_gpu_npu: DCDC_REG2 {
-+ regulator-name = "vdd_gpu_npu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_sys: DCDC_REG4 {
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcca1v8_pmu: LDO_REG1 {
-+ regulator-name = "vcca1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vdda_0v9: LDO_REG2 {
-+ regulator-name = "vdda_0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_pmu: LDO_REG3 {
-+ regulator-name = "vdda0v9_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vccio_acodec: LDO_REG4 {
-+ regulator-name = "vccio_acodec";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd: LDO_REG5 {
-+ regulator-name = "vccio_sd";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_pmu: LDO_REG6 {
-+ regulator-name = "vcc3v3_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcc_1v8_p: LDO_REG7 {
-+ regulator-name = "vcc_1v8_p";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc1v8_dvp: LDO_REG8 {
-+ regulator-name = "vcc1v8_dvp";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc2v8_dvp: LDO_REG9 {
-+ regulator-name = "vcc2v8_dvp";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <2800000>;
-+ regulator-max-microvolt = <2800000>;
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ };
-+ };
-+};
-+
-+&pinctrl {
-+ pmic {
-+ pmic_int_l: pmic-int-l {
-+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+
-+ leds {
-+ user_led2: user-led2 {
-+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pmu_io_domains {
-+ pmuio1-supply = <&vcc3v3_pmu>;
-+ pmuio2-supply = <&vcc_3v3>;
-+ vccio1-supply = <&vccio_acodec>;
-+ vccio2-supply = <&vcc_1v8>;
-+ vccio3-supply = <&vccio_sd>;
-+ vccio4-supply = <&vcc_1v8>;
-+ vccio5-supply = <&vcc_3v3>;
-+ vccio6-supply = <&vcc_3v3>;
-+ vccio7-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ max-frequency = <200000000>;
-+ mmc-hs200-1_8v;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-+ vmmc-supply = <&vcc_3v3>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "okay";
-+};
-+
-+&usb2phy0 {
-+ status = "okay";
-+};
-+
-+&usb2phy1 {
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <1>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
+++ /dev/null
-From af5a803bf212e077e5fb7a1d4cf6be02f74a74ca Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Wed, 25 Jan 2023 21:40:23 +0530
-Subject: [PATCH] arm64: dts: rockchip: rk3566: Enable WiFi, BT support for
- Radxa CM3
-
-Radxa Compute Module 3 has an onboard AW_CM256SM WiFi/BT module.
-
-Add nodes for enabling it.
-
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230125161023.12115-2-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 80 +++++++++++++++++++
- 1 file changed, 80 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-@@ -66,6 +66,15 @@
- regulator-max-microvolt = <1800000>;
- vin-supply = <&vcc_1v8_p>;
- };
-+
-+ sdio_pwrseq: pwrseq-sdio {
-+ compatible = "mmc-pwrseq-simple";
-+ clocks = <&rk817 1>;
-+ clock-names = "ext_clock";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_reg_on_h>;
-+ reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
-+ };
- };
-
- &cpu0 {
-@@ -287,6 +296,20 @@
- };
-
- &pinctrl {
-+ bluetooth {
-+ bt_host_wake_h: bt-host-wake-h {
-+ rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ bt_reg_on_h: bt-reg-on-h {
-+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ bt_wake_host_h: bt-wake-host-h {
-+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
- pmic {
- pmic_int_l: pmic-int-l {
- rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-@@ -298,6 +321,16 @@
- rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
- };
- };
-+
-+ wifi {
-+ wifi_reg_on_h: wifi-reg-on-h {
-+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ wifi_host_wake_h: wifi-host-wake-h {
-+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
- };
-
- &pmu_io_domains {
-@@ -318,6 +351,34 @@
- status = "okay";
- };
-
-+&sdmmc1 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ bus-width = <4>;
-+ disable-wp;
-+ cap-sd-highspeed;
-+ cap-sdio-irq;
-+ keep-power-in-suspend;
-+ mmc-pwrseq = <&sdio_pwrseq>;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc_3v3>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "okay";
-+
-+ wifi@1 {
-+ compatible = "brcm,bcm43455-fmac";
-+ reg = <1>;
-+ interrupt-parent = <&gpio2>;
-+ interrupts = <RK_PC1 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "host-wake";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&wifi_host_wake_h>;
-+ };
-+};
-+
- &sdhci {
- bus-width = <8>;
- max-frequency = <200000000>;
-@@ -330,6 +391,25 @@
- status = "okay";
- };
-
-+&uart1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
-+ status = "okay";
-+
-+ bluetooth {
-+ compatible = "brcm,bcm4345c5";
-+ clocks = <&rk817 1>;
-+ clock-names = "lpo";
-+ device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
-+ host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
-+ reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>;
-+ vbat-supply = <&vcc_3v3>;
-+ vddio-supply = <&vcc_1v8>;
-+ };
-+};
-+
- &usb2phy0 {
- status = "okay";
- };
+++ /dev/null
-From 477ed3ade6a46e445b4e2348b710c51df4f6f4b1 Mon Sep 17 00:00:00 2001
-From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Date: Thu, 23 Feb 2023 19:29:29 +0530
-Subject: [PATCH] arm64: dts: rockchip: Enable USB OTG for rk3566 Radxa CM3
-
-Enable USB OTG support for Radxa Compute Module 3 IO Board
-
-Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230223135929.630787-1-abbaraju.manojsai@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -254,6 +254,14 @@
- status = "okay";
- };
-
-+&usb2phy0_otg {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ status = "okay";
-+};
-+
- &vop {
- assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
- assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+++ /dev/null
-From 8f19828844f20b22182719cf53be64f8c955aee8 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Mon, 23 Jan 2023 12:46:50 +0530
-Subject: [PATCH] arm64: dts: rockchip: Fix compatible for Radxa CM3
-
-The compatible string "radxa,radxa-cm3" referring the product name
-as "Radxa Radxa CM3" but the actual product name is "Radxa CM3".
-
-Fix the compatible strings.
-
-Fixes: 24a28d3eb07d ("dt-bindings: arm: rockchip: Add Radxa Compute Module 3")
-Fixes: 7469ab529bca ("arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3")
-Fixes: 096ebfb74b19 ("arm64: dts: rockchip: Add Radxa Compute Module 3 IO board")
-Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20230123071654.73139-1-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 2 +-
- arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -11,7 +11,7 @@
-
- / {
- model = "Radxa Compute Module 3(CM3) IO Board";
-- compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
-+ compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
-
- aliases {
- mmc1 = &sdmmc0;
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
-@@ -8,7 +8,7 @@
- #include <dt-bindings/leds/common.h>
-
- / {
-- compatible = "radxa,radxa-cm3", "rockchip,rk3566";
-+ compatible = "radxa,cm3", "rockchip,rk3566";
-
- aliases {
- mmc0 = &sdhci;
+++ /dev/null
-From f99a75f11f46a24dabb33e90893eebf61dca0566 Mon Sep 17 00:00:00 2001
-From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Date: Sun, 2 Jul 2023 20:52:42 +0200
-Subject: [PATCH] arm64: dts: rockchip: minor whitespace cleanup around '='
-
-The DTS code coding style expects exactly one space before and after '='
-sign.
-
-Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Link: https://lore.kernel.org/r/20230702185242.44421-1-krzysztof.kozlowski@linaro.org
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 4 ++--
- 1 files changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
-@@ -137,8 +137,8 @@
-
- &mdio1 {
- rgmii_phy1: ethernet-phy@0 {
-- compatible="ethernet-phy-ieee802.3-c22";
-- reg= <0x0>;
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <0x0>;
- };
- };
-
+++ /dev/null
-From 2bf2f4d9f673013a58109626b87329310537a611 Mon Sep 17 00:00:00 2001
-From: Chukun Pan <amadeus@jmu.edu.cn>
-Date: Fri, 9 Dec 2022 18:25:24 +0800
-Subject: [PATCH] arm64: dts: rockchip: Add Radxa CM3I E25
-
-Radxa E25 is a network application carrier board for the Radxa CM3
-Industrial (CM3I) SoM, which is based on the Rockchip RK3568 SoC.
-
-It has the following features:
-
-- MicroSD card socket, on board eMMC flash
-- 2x 2.5GbE Realtek RTL8125B Ethernet transceiver
-- 1x USB Type-C port (Power and Serial console)
-- 1x USB 3.0 OTG port
-- mini PCIe socket (USB or PCIe)
-- ngff PCIe socket (USB or SATA)
-- 1x User LED and 16x RGB LEDs
-- 26-pin expansion header
-
-Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
-Link: https://lore.kernel.org/r/20221209102524.129367-3-amadeus@jmu.edu.cn
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/Makefile | 1 +
- .../boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 416 ++++++++++++++++++
- .../boot/dts/rockchip/rk3568-radxa-e25.dts | 229 ++++++++++
- 3 files changed, 646 insertions(+)
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
- create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -78,4 +78,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bp
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
-@@ -0,0 +1,416 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include "rk3568.dtsi"
-+
-+/ {
-+ model = "Radxa CM3 Industrial Board";
-+ compatible = "radxa,cm3i", "rockchip,rk3568";
-+
-+ aliases {
-+ mmc0 = &sdhci;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial2:115200n8";
-+ };
-+
-+ gpio-leds {
-+ compatible = "gpio-leds";
-+
-+ led_user: led-0 {
-+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
-+ function = LED_FUNCTION_HEARTBEAT;
-+ color = <LED_COLOR_ID_GREEN>;
-+ linux,default-trigger = "heartbeat";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&led_user_en>;
-+ };
-+ };
-+
-+ pcie30_avdd0v9: pcie30-avdd0v9-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ pcie30_avdd1v8: pcie30-avdd1v8-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "pcie30_avdd1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vin-supply = <&vcc3v3_sys>;
-+ };
-+
-+ vcc3v3_sys: vcc3v3-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc3v3_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v_input>;
-+ };
-+
-+ vcc5v0_sys: vcc5v0-sys-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v0_sys";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v_input>;
-+ };
-+
-+ /* labeled +5v_input in schematic */
-+ vcc5v_input: vcc5v-input-regulator {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc5v_input";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+};
-+
-+&combphy0 {
-+ status = "okay";
-+};
-+
-+&combphy1 {
-+ status = "okay";
-+};
-+
-+&combphy2 {
-+ status = "okay";
-+};
-+
-+&cpu0 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+ cpu-supply = <&vdd_cpu>;
-+};
-+
-+&display_subsystem {
-+ status = "disabled";
-+};
-+
-+&gpu {
-+ mali-supply = <&vdd_gpu>;
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ status = "okay";
-+
-+ vdd_cpu: regulator@1c {
-+ compatible = "tcs,tcs4525";
-+ reg = <0x1c>;
-+ fcs,suspend-voltage-selector = <1>;
-+ regulator-name = "vdd_cpu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <800000>;
-+ regulator-max-microvolt = <1150000>;
-+ regulator-ramp-delay = <2300>;
-+ vin-supply = <&vcc5v_input>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ rk809: pmic@20 {
-+ compatible = "rockchip,rk809";
-+ reg = <0x20>;
-+ interrupt-parent = <&gpio0>;
-+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+ #clock-cells = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pmic_int>;
-+ rockchip,system-power-controller;
-+ wakeup-source;
-+
-+ vcc1-supply = <&vcc3v3_sys>;
-+ vcc2-supply = <&vcc3v3_sys>;
-+ vcc3-supply = <&vcc3v3_sys>;
-+ vcc4-supply = <&vcc3v3_sys>;
-+ vcc5-supply = <&vcc3v3_sys>;
-+ vcc6-supply = <&vcc3v3_sys>;
-+ vcc7-supply = <&vcc3v3_sys>;
-+ vcc8-supply = <&vcc3v3_sys>;
-+ vcc9-supply = <&vcc3v3_sys>;
-+
-+ regulators {
-+ vdd_logic: DCDC_REG1 {
-+ regulator-name = "vdd_logic";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdd_gpu: DCDC_REG2 {
-+ regulator-name = "vdd_gpu";
-+ regulator-always-on;
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_ddr: DCDC_REG3 {
-+ regulator-name = "vcc_ddr";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-initial-mode = <0x2>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ };
-+ };
-+
-+ vdd_npu: DCDC_REG4 {
-+ regulator-name = "vdd_npu";
-+ regulator-init-microvolt = <900000>;
-+ regulator-initial-mode = <0x2>;
-+ regulator-min-microvolt = <500000>;
-+ regulator-max-microvolt = <1350000>;
-+ regulator-ramp-delay = <6001>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_1v8: DCDC_REG5 {
-+ regulator-name = "vcc_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_image: LDO_REG1 {
-+ regulator-name = "vdda0v9_image";
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda_0v9: LDO_REG2 {
-+ regulator-name = "vdda_0v9";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vdda0v9_pmu: LDO_REG3 {
-+ regulator-name = "vdda0v9_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <900000>;
-+ };
-+ };
-+
-+ vccio_acodec: LDO_REG4 {
-+ regulator-name = "vccio_acodec";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vccio_sd: LDO_REG5 {
-+ regulator-name = "vccio_sd";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_pmu: LDO_REG6 {
-+ regulator-name = "vcc3v3_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <3300000>;
-+ };
-+ };
-+
-+ vcca_1v8: LDO_REG7 {
-+ regulator-name = "vcca_1v8";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcca1v8_pmu: LDO_REG8 {
-+ regulator-name = "vcca1v8_pmu";
-+ regulator-always-on;
-+ regulator-boot-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-on-in-suspend;
-+ regulator-suspend-microvolt = <1800000>;
-+ };
-+ };
-+
-+ vcca1v8_image: LDO_REG9 {
-+ regulator-name = "vcca1v8_image";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc_3v3: SWITCH_REG1 {
-+ regulator-name = "vcc_3v3";
-+ regulator-always-on;
-+ regulator-boot-on;
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+
-+ vcc3v3_sd: SWITCH_REG2 {
-+ regulator-name = "vcc3v3_sd";
-+
-+ regulator-state-mem {
-+ regulator-off-in-suspend;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&pinctrl {
-+ leds {
-+ led_user_en: led_user_en {
-+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ pmic {
-+ pmic_int: pmic_int {
-+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+ };
-+ };
-+};
-+
-+&pmu_io_domains {
-+ pmuio1-supply = <&vcc3v3_pmu>;
-+ pmuio2-supply = <&vcc3v3_pmu>;
-+ vccio1-supply = <&vccio_acodec>;
-+ vccio2-supply = <&vcc_1v8>;
-+ vccio3-supply = <&vccio_sd>;
-+ vccio4-supply = <&vcc_1v8>;
-+ vccio5-supply = <&vcc_3v3>;
-+ vccio6-supply = <&vcc_1v8>;
-+ vccio7-supply = <&vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&saradc {
-+ vref-supply = <&vcca_1v8>;
-+ status = "okay";
-+};
-+
-+&sdhci {
-+ bus-width = <8>;
-+ max-frequency = <200000000>;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
-+ vmmc-supply = <&vcc_3v3>;
-+ vqmmc-supply = <&vcc_1v8>;
-+ status = "okay";
-+};
-+
-+&tsadc {
-+ rockchip,hw-tshut-mode = <1>;
-+ rockchip,hw-tshut-polarity = <0>;
-+ status = "okay";
-+};
-+
-+&uart2 {
-+ status = "okay";
-+};
-+
-+&usb2phy0 {
-+ status = "okay";
-+};
-+
-+&usb2phy1 {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ extcon = <&usb2phy0>;
-+};
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -0,0 +1,229 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+
-+/dts-v1/;
-+#include "rk3568-radxa-cm3i.dtsi"
-+
-+/ {
-+ model = "Radxa E25";
-+ compatible = "radxa,e25", "rockchip,rk3568";
-+
-+ aliases {
-+ mmc0 = &sdmmc0;
-+ mmc1 = &sdhci;
-+ };
-+
-+ pwm-leds {
-+ compatible = "pwm-leds-multicolor";
-+
-+ multi-led {
-+ color = <LED_COLOR_ID_RGB>;
-+ max-brightness = <255>;
-+
-+ led-red {
-+ color = <LED_COLOR_ID_RED>;
-+ pwms = <&pwm1 0 1000000 0>;
-+ };
-+
-+ led-green {
-+ color = <LED_COLOR_ID_GREEN>;
-+ pwms = <&pwm2 0 1000000 0>;
-+ };
-+
-+ led-blue {
-+ color = <LED_COLOR_ID_BLUE>;
-+ pwms = <&pwm12 0 1000000 0>;
-+ };
-+ };
-+ };
-+
-+ vbus_typec: vbus-typec-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&vbus_typec_en>;
-+ regulator-name = "vbus_typec";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc3v3_minipcie: vcc3v3-minipcie-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&minipcie_enable_h>;
-+ regulator-name = "vcc3v3_minipcie";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ vcc3v3_ngff: vcc3v3-ngff-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&ngffpcie_enable_h>;
-+ regulator-name = "vcc3v3_ngff";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+
-+ /* actually fed by vcc5v0_sys, dependent
-+ * on pi6c clock generator
-+ */
-+ vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie30x1_enable_h>;
-+ regulator-name = "vcc3v3_pcie30x1";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc3v3_pi6c_05>;
-+ };
-+
-+ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie_enable_h>;
-+ regulator-name = "vcc3v3_pcie";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc5v0_sys>;
-+ };
-+};
-+
-+&pcie2x1 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie20_reset_h>;
-+ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
-+ status = "okay";
-+};
-+
-+&pcie30phy {
-+ data-lanes = <1 2>;
-+ status = "okay";
-+};
-+
-+&pcie3x1 {
-+ num-lanes = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie30x1m0_pins>;
-+ reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pcie30x1>;
-+ status = "okay";
-+};
-+
-+&pcie3x2 {
-+ num-lanes = <1>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pcie30x2_reset_h>;
-+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
-+ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
-+ status = "okay";
-+};
-+
-+&pinctrl {
-+ pcie {
-+ pcie20_reset_h: pcie20-reset-h {
-+ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie30x1_enable_h: pcie30x1-enable-h {
-+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie30x2_reset_h: pcie30x2-reset-h {
-+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ pcie_enable_h: pcie-enable-h {
-+ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+
-+ usb {
-+ minipcie_enable_h: minipcie-enable-h {
-+ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ ngffpcie_enable_h: ngffpcie-enable-h {
-+ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+
-+ vbus_typec_en: vbus_typec_en {
-+ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
-+ };
-+ };
-+};
-+
-+&pwm1 {
-+ status = "okay";
-+};
-+
-+&pwm2 {
-+ status = "okay";
-+};
-+
-+&pwm12 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pwm12m1_pins>;
-+ status = "okay";
-+};
-+
-+&sdmmc0 {
-+ bus-width = <4>;
-+ cap-sd-highspeed;
-+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
-+ /* Also used in pcie30x1_clkreqnm0 */
-+ disable-wp;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
-+ sd-uhs-sdr104;
-+ vmmc-supply = <&vcc3v3_sd>;
-+ vqmmc-supply = <&vccio_sd>;
-+ status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+ status = "okay";
-+};
-+
-+&usb_host0_xhci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+ status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+ status = "okay";
-+};
-+
-+&usb2phy0_otg {
-+ phy-supply = <&vbus_typec>;
-+ status = "okay";
-+};
-+
-+&usb2phy1_host {
-+ phy-supply = <&vcc3v3_minipcie>;
-+ status = "okay";
-+};
-+
-+&usb2phy1_otg {
-+ phy-supply = <&vcc3v3_ngff>;
-+ status = "okay";
-+};
+++ /dev/null
-From c80992abd2877590059e9cb254213c16824e2106 Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Wed, 18 Jan 2023 13:34:53 +0530
-Subject: [PATCH] arm64: dts: rockchip: Update eMMC, SD aliases for Radxa SoM
- boards
-
-Radxa has produced Compute Modules like RK3399pro VMARC and CM3i with
-onboarding eMMC flash, so the eMMC is the primary MMC device.
-
-On the other hand, Rockchip boot orders start from eMMC from an MMC
-device perspective.
-
-Mark, the eMMC has mmc0 to satisfy the above two conditions.
-
-Reported-by: FUKAUMI Naoki <naoki@radxa.com>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230118080454.11643-1-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 4 ++--
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 3 +--
- 2 files changed, 3 insertions(+), 4 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
-@@ -13,8 +13,8 @@
- compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
-
- aliases {
-- mmc0 = &sdmmc;
-- mmc1 = &sdhci;
-+ mmc0 = &sdhci;
-+ mmc1 = &sdmmc;
- };
-
- vcc3v3_pcie: vcc-pcie-regulator {
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -8,8 +8,7 @@
- compatible = "radxa,e25", "rockchip,rk3568";
-
- aliases {
-- mmc0 = &sdmmc0;
-- mmc1 = &sdhci;
-+ mmc1 = &sdmmc0;
- };
-
- pwm-leds {
+++ /dev/null
-From c4d2b02d63ee38b381fbc886c02eecfec4f981cc Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Mon, 23 Jan 2023 12:46:51 +0530
-Subject: [PATCH] arm64: dts: rockchip: Add missing CM3i fallback compatible
- for Radxa E25
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-In order to function the Radxa E25 Carrier board, it is mandatory to
-mount the Radxa CM3i module.
-
-Add Radxa CM3i compatible as fallback compatible to string to satisfy
-the Module and Carrier board topology.
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Cc: Chukun Pan <amadeus@jmu.edu.cn>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230123071654.73139-2-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -5,7 +5,7 @@
-
- / {
- model = "Radxa E25";
-- compatible = "radxa,e25", "rockchip,rk3568";
-+ compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
-
- aliases {
- mmc1 = &sdmmc0;
+++ /dev/null
-From ef9134d9bbce071c9e4ebdcbb6f8fb1a5dd0a67e Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Mon, 23 Jan 2023 12:46:53 +0530
-Subject: [PATCH] arm64: dts: rockchip: Correct the model name for Radxa E25
-
-Radxa E25 is a Carrier board, so update the model name for Radxa E25
-as suggested by the Radxa website.
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Cc: Chukun Pan <amadeus@jmu.edu.cn>
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Link: https://lore.kernel.org/r/20230123071654.73139-4-jagan@amarulasolutions.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -4,7 +4,7 @@
- #include "rk3568-radxa-cm3i.dtsi"
-
- / {
-- model = "Radxa E25";
-+ model = "Radxa E25 Carrier Board";
- compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
-
- aliases {
+++ /dev/null
-From a87852e37f782257ebc57cc44a0d3fbf806471f6 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 24 Jul 2023 14:52:16 +0000
-Subject: [PATCH] arm64: dts: rockchip: Fix PCIe regulators on Radxa E25
-
-Despite its name, the regulator vcc3v3_pcie30x1 has nothing to do with
-pcie30x1. Instead, it supply power to VBAT1-5 on the M.2 KEY B port as
-seen on page 8 of the schematic [1].
-
-pcie30x1 is used for the mini PCIe slot, and as seen on page 9 the
-vcc3v3_minipcie regulator is instead related to pcie30x1.
-
-The M.2 KEY B port can be used for WWAN USB2 modules or SATA drives.
-
-Use correct regulator vcc3v3_minipcie for pcie30x1.
-
-[1] https://dl.radxa.com/cm3p/e25/radxa-e25-v1.4-sch.pdf
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20230724145213.3833099-1-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- .../arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 16 ++++++++--------
- 1 file changed, 8 insertions(+), 8 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -47,6 +47,9 @@
- vin-supply = <&vcc5v0_sys>;
- };
-
-+ /* actually fed by vcc5v0_sys, dependent
-+ * on pi6c clock generator
-+ */
- vcc3v3_minipcie: vcc3v3-minipcie-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
-@@ -54,9 +57,9 @@
- pinctrl-names = "default";
- pinctrl-0 = <&minipcie_enable_h>;
- regulator-name = "vcc3v3_minipcie";
-- regulator-min-microvolt = <5000000>;
-- regulator-max-microvolt = <5000000>;
-- vin-supply = <&vcc5v0_sys>;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <&vcc3v3_pi6c_05>;
- };
-
- vcc3v3_ngff: vcc3v3-ngff-regulator {
-@@ -71,9 +74,6 @@
- vin-supply = <&vcc5v0_sys>;
- };
-
-- /* actually fed by vcc5v0_sys, dependent
-- * on pi6c clock generator
-- */
- vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
- compatible = "regulator-fixed";
- enable-active-high;
-@@ -83,7 +83,7 @@
- regulator-name = "vcc3v3_pcie30x1";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
-- vin-supply = <&vcc3v3_pi6c_05>;
-+ vin-supply = <&vcc5v0_sys>;
- };
-
- vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
-@@ -117,7 +117,7 @@
- pinctrl-names = "default";
- pinctrl-0 = <&pcie30x1m0_pins>;
- reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
-- vpcie3v3-supply = <&vcc3v3_pcie30x1>;
-+ vpcie3v3-supply = <&vcc3v3_minipcie>;
- status = "okay";
- };
-
+++ /dev/null
-From 2bdfe84fbd57a4ed9fd65a67210442559ce078f0 Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Mon, 24 Jul 2023 14:52:16 +0000
-Subject: [PATCH] arm64: dts: rockchip: Enable SATA on Radxa E25
-
-The M.2 KEY B port can be used for WWAN USB2 modules or SATA drives.
-
-Enable sata1 node to fix use of SATA drives on the M.2 slot.
-
-Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
-Link: https://lore.kernel.org/r/20230724145213.3833099-1-jonas@kwiboo.se
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
-@@ -99,6 +99,10 @@
- };
- };
-
-+&combphy1 {
-+ phy-supply = <&vcc3v3_pcie30x1>;
-+};
-+
- &pcie2x1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie20_reset_h>;
-@@ -178,6 +182,10 @@
- status = "okay";
- };
-
-+&sata1 {
-+ status = "okay";
-+};
-+
- &sdmmc0 {
- bus-width = <4>;
- cap-sd-highspeed;
+++ /dev/null
-From a2ac2a1b02590a22a236c43c455f421cdede45f5 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
-Date: Thu, 14 Mar 2024 15:24:35 +0300
-Subject: [PATCH] arm64: dts: rockchip: set PHY address of MT7531 switch to
- 0x1f
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The MT7531 switch listens on PHY address 0x1f on an MDIO bus. I've got two
-findings that support this. There's no bootstrapping option to change the
-PHY address of the switch. The Linux driver hardcodes 0x1f as the PHY
-address of the switch. So the reg property on the device tree is currently
-ignored by the Linux driver.
-
-Therefore, describe the correct PHY address on Banana Pi BPI-R2 Pro that
-has this switch.
-
-Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
-Fixes: c1804463e5c6 ("arm64: dts: rockchip: Add mt7531 dsa node to BPI-R2-Pro board")
-Link: https://lore.kernel.org/r/20240314-for-rockchip-mt7531-phy-address-v1-1-743b5873358f@arinc9.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
-@@ -521,9 +521,9 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-- switch@0 {
-+ switch@1f {
- compatible = "mediatek,mt7531";
-- reg = <0>;
-+ reg = <0x1f>;
-
- ports {
- #address-cells = <1>;
+++ /dev/null
-From 433d54818f64a2fe0562f8c04c7a81f562368515 Mon Sep 17 00:00:00 2001
-From: Jose Ignacio Tornos Martinez <jtornosm@redhat.com>
-Date: Tue, 5 Mar 2024 15:32:18 +0100
-Subject: [PATCH] arm64: dts: rockchip: regulator for sd needs to be always on
- for BPI-R2Pro
-
-With default dts configuration for BPI-R2Pro, the regulator for sd card is
-powered off when reboot is commanded, and the only solution to detect the
-sd card again, and therefore, allow rebooting from there, is to do a
-hardware reset.
-
-Configure the regulator for sd to be always on for BPI-R2Pro in order to
-avoid this issue.
-
-Fixes: f901aaadaa2a ("arm64: dts: rockchip: Add Bananapi R2 Pro")
-Signed-off-by: Jose Ignacio Tornos Martinez <jtornosm@redhat.com>
-Link: https://lore.kernel.org/r/20240305143222.189413-1-jtornosm@redhat.com
-Signed-off-by: Heiko Stuebner <heiko@sntech.de>
----
- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
-@@ -412,6 +412,8 @@
-
- vccio_sd: LDO_REG5 {
- regulator-name = "vccio_sd";
-+ regulator-always-on;
-+ regulator-boot-on;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
-
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
-@@ -549,6 +549,20 @@ config HW_RANDOM_CN10K
- To compile this driver as a module, choose M here.
- The module will be called cn10k_rng. If unsure, say Y.
+@@ -573,6 +573,20 @@ config HW_RANDOM_JH7110
+ To compile this driver as a module, choose M here.
+ The module will be called jh7110-trng.
+config HW_RANDOM_ROCKCHIP
+ tristate "Rockchip True Random Number Generator"
config UML_RANDOM
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
-@@ -47,3 +47,4 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe
+@@ -48,4 +48,5 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphe
obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
+ obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
--- /dev/null
+++ b/drivers/char/hw_random/rockchip-rng.c
@@ -0,0 +1,251 @@
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1773,6 +1773,15 @@
+@@ -1807,6 +1807,15 @@
};
};
projects / openwrt / staging / pepe2k.git / commitdiff