target/linux/ipq806x/patches-6.1/122-04-clk-qcom-krait-cc-rework-mux-reset-logic-and-reset-h.patch

   1 From 6a77cf3f5f95ec0058e1b4d1ada018748cb0b83b Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Thu, 15 Sep 2022 03:33:13 +0200
   4 Subject: [PATCH 9/9] clk: qcom: krait-cc: rework mux reset logic and reset
   5  hfpll
   6
   7 Rework and clean mux reset logic.
   8 Compact it to a for loop to handle both CPU and L2 in one place.
   9 Move hardcoded aux_rate to define and add a new hfpll_rate value to
  10 reset hfpll settings.
  11 Change logic to now reset the hfpll to the lowest value of 600 Mhz and
  12 then restoring the previous frequency. This permits to reset the hfpll if
  13 the primary mux was set to source out of the secondary mux.
  14
  15 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  16 ---
  17  drivers/clk/qcom/krait-cc.c | 50 +++++++++++++++++--------------------
  18  1 file changed, 23 insertions(+), 27 deletions(-)
  19
  20 --- a/drivers/clk/qcom/krait-cc.c
  21 +++ b/drivers/clk/qcom/krait-cc.c
  22 @@ -25,7 +25,9 @@ enum {
  23         clks_max,
  24  };
  25
  26 -#define QSB_RATE       2250000000
  27 +#define QSB_RATE       225000000
  28 +#define AUX_RATE       384000000
  29 +#define HFPLL_RATE     600000000
  30
  31  static unsigned int sec_mux_map[] = {
  32         2,
  33 @@ -350,7 +352,7 @@ static int krait_cc_probe(struct platfor
  34  {
  35         struct device *dev = &pdev->dev;
  36         const struct of_device_id *id;
  37 -       unsigned long cur_rate, aux_rate, qsb_rate;
  38 +       unsigned long cur_rate, qsb_rate;
  39         int cpu;
  40         struct clk_hw *mux, *l2_pri_mux;
  41         struct clk *clk, **clks;
  42 @@ -420,28 +422,29 @@ static int krait_cc_probe(struct platfor
  43          * two different rates to force a HFPLL reinit under all
  44          * circumstances.
  45          */
  46 -       cur_rate = clk_get_rate(clks[l2_mux]);
  47 -       aux_rate = 384000000;
  48 -       if (cur_rate < aux_rate) {
  49 -               dev_info(dev, "L2 @ Undefined rate. Forcing new rate.\n");
  50 -               cur_rate = aux_rate;
  51 -       }
  52 -       clk_set_rate(clks[l2_mux], aux_rate);
  53 -       clk_set_rate(clks[l2_mux], 2);
  54 -       clk_set_rate(clks[l2_mux], cur_rate);
  55 -       dev_info(dev, "L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000);
  56 -       for_each_possible_cpu(cpu) {
  57 +       for (cpu = 0; cpu < 5; cpu++) {
  58 +               const char *l2_s = "L2";
  59 +               char cpu_s[5];
  60 +
  61                 clk = clks[cpu];
  62 +               if (!clk)
  63 +                       continue;
  64 +
  65 +               if (cpu < 4)
  66 +                       snprintf(cpu_s, 5, "CPU%d", cpu);
  67 +
  68                 cur_rate = clk_get_rate(clk);
  69 -               if (cur_rate < aux_rate) {
  70 -                       dev_info(dev, "CPU%d @ Undefined rate. Forcing new rate.\n", cpu);
  71 -                       cur_rate = aux_rate;
  72 +               if (cur_rate < AUX_RATE) {
  73 +                       dev_info(dev, "%s @ Undefined rate. Forcing new rate.\n",
  74 +                                cpu < 4 ? cpu_s : l2_s);
  75 +                       cur_rate = AUX_RATE;
  76                 }
  77
  78 -               clk_set_rate(clk, aux_rate);
  79 -               clk_set_rate(clk, 2);
  80 +               clk_set_rate(clk, AUX_RATE);
  81 +               clk_set_rate(clk, HFPLL_RATE);
  82                 clk_set_rate(clk, cur_rate);
  83 -               dev_info(dev, "CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
  84 +               dev_info(dev, "%s @ %lu KHz\n", cpu < 4 ? cpu_s : l2_s,
  85 +                        clk_get_rate(clk) / 1000);
  86         }
  87
  88         of_clk_add_provider(dev->of_node, krait_of_get, clks);