target/linux/ipq806x/files-6.1/arch/arm/boot/dts/qcom-ipq8064-fap-421e.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "qcom-ipq8064-smb208.dtsi"
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/leds/common.h>
   6
   7 / {
   8         model = "Fortinet FAP-421E";
   9         compatible = "fortinet,fap-421e", "qcom,ipq8064";
  10
  11         memory@42000000 {
  12                 device_type = "memory";
  13                 reg = <0x42000000 0xe000000>;
  14         };
  15
  16         reserved-memory {
  17                 rsvd@41200000 {
  18                         no-map;
  19                         reg = <0x41200000 0x300000>;
  20                 };
  21                 wifi_dump@44000000 {
  22                         no-map;
  23                         reg = <0x44000000 0x600000>;
  24                 };
  25         };
  26
  27         aliases {
  28                 led-boot = &led_power_yellow;
  29                 led-failsafe = &led_power_yellow;
  30                 led-running = &led_power_yellow;
  31                 led-upgrade = &led_power_yellow;
  32                 label-mac-device = &gmac0;
  33         };
  34
  35         chosen {
  36                 bootargs-override = "console=ttyMSM0,9600n8";
  37         };
  38
  39         keys {
  40                 compatible = "gpio-keys";
  41                 pinctrl-0 = <&button_pins>;
  42                 pinctrl-names = "default";
  43
  44                 reset {
  45                         label = "reset";
  46                         gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
  47                         linux,code = <KEY_RESTART>;
  48                 };
  49         };
  50
  51         leds {
  52                 compatible = "gpio-leds";
  53                 pinctrl-0 = <&led_pins>;
  54                 pinctrl-names = "default";
  55
  56                 eth1-amber {
  57                         label = "amber:eth1";
  58                         gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>;
  59                 };
  60
  61                 eth1-yellow {
  62                         label = "yellow:eth1";
  63                         gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
  64                 };
  65
  66                 eth2-amber {
  67                         label = "amber:eth2";
  68                         gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>;
  69                 };
  70
  71                 eth2-yellow {
  72                         label = "yellow:eth2";
  73                         gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
  74                 };
  75
  76                 power-amber {
  77                         function = LED_FUNCTION_POWER;
  78                         color = <LED_COLOR_ID_AMBER>;
  79                         gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
  80                 };
  81
  82                 led_power_yellow: power-yellow {
  83                         function = LED_FUNCTION_POWER;
  84                         color = <LED_COLOR_ID_YELLOW>;
  85                         gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
  86                 };
  87
  88                 2g-yellow {
  89                         label = "yellow:2g";
  90                         gpios = <&qcom_pinmux 30 GPIO_ACTIVE_LOW>;
  91                 };
  92
  93                 5g-yellow {
  94                         label = "yellow:5g";
  95                         gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
  96                 };
  97         };
  98 };
  99
 100 &qcom_pinmux {
 101         button_pins: button_pins {
 102                 mux {
 103                         bias-pull-up;
 104                         drive-strength = <2>;
 105                         pins = "gpio56";
 106                 };
 107         };
 108
 109         led_pins: led_pins {
 110                 mux {
 111                         bias-pull-down;
 112                         drive-strength = <2>;
 113                         function = "gpio";
 114                         output-low;
 115                         pins = "gpio23";
 116                 };
 117         };
 118
 119         rgmii2_pins: rgmii2-pins {
 120                 mux {
 121                         bias-disable;
 122                         drive-strength = <16>;
 123                         function = "rgmii2";
 124                         pins = "gpio66";
 125                 };
 126         };
 127
 128         spi_pins: spi_pins {
 129                 mux {
 130                         pins = "gpio18", "gpio19", "gpio21";
 131                         function = "gsbi5";
 132                         bias-pull-down;
 133                 };
 134
 135                 data {
 136                         pins = "gpio18", "gpio19";
 137                         drive-strength = <10>;
 138                 };
 139
 140                 cs {
 141                         pins = "gpio20";
 142                         drive-strength = <10>;
 143                         bias-pull-up;
 144                 };
 145
 146                 clk {
 147                         pins = "gpio21";
 148                         drive-strength = <12>;
 149                 };
 150         };
 151
 152         uart0_pins: uart0_pins {
 153                 mux {
 154                         bias-disable;
 155                         drive-strength = <12>;
 156                         function = "gsbi7";
 157                         pins = "gpio6", "gpio7";
 158                 };
 159         };
 160
 161         usb_pwr_en_pins: usb_pwr_en_pins {
 162                 mux {
 163                         pins = "gpio22";
 164                         function = "gpio";
 165                         drive-strength = <12>;
 166                         bias-pull-down;
 167                         output-low;
 168                 };
 169         };
 170 };
 171
 172 &gsbi7 {
 173         qcom,mode = <GSBI_PROT_I2C_UART>;
 174
 175         status = "okay";
 176 };
 177
 178 &gsbi7_serial{
 179         pinctrl-0 = <&uart0_pins>;
 180         pinctrl-names = "default";
 181
 182         status = "okay";
 183 };
 184
 185 &gsbi5 {
 186         qcom,mode = <GSBI_PROT_SPI>;
 187
 188         status = "okay";
 189
 190         spi@1a280000 {
 191                 status = "okay";
 192
 193                 pinctrl-0 = <&spi_pins>;
 194                 pinctrl-names = "default";
 195                 cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
 196
 197                 flash@0 {
 198                         compatible = "jedec,spi-nor";
 199                         #address-cells = <1>;
 200                         #size-cells = <1>;
 201                         spi-max-frequency = <50000000>;
 202                         reg = <0>;
 203                         m25p,fast-read;
 204
 205                         partition@0 {
 206                                 label = "SBL1";
 207                                 reg = <0x0 0x20000>;
 208                                 read-only;
 209                         };
 210
 211                         partition@20000 {
 212                                 label = "MIBIB";
 213                                 reg = <0x20000 0x20000>;
 214                                 read-only;
 215                         };
 216
 217                         partition@40000 {
 218                                 label = "SBL2";
 219                                 reg = <0x40000 0x40000>;
 220                                 read-only;
 221                         };
 222
 223                         partition@80000 {
 224                                 label = "SBL3";
 225                                 reg = <0x80000 0x80000>;
 226                                 read-only;
 227                         };
 228
 229                         partition@100000 {
 230                                 label = "DDRCONFIG";
 231                                 reg = <0x100000 0x10000>;
 232                                 read-only;
 233                         };
 234
 235                         partition@110000 {
 236                                 label = "SSD";
 237                                 reg = <0x110000 0x10000>;
 238                                 read-only;
 239                         };
 240
 241                         partition@120000 {
 242                                 label = "TZ";
 243                                 reg = <0x120000 0x80000>;
 244                                 read-only;
 245                         };
 246
 247                         partition@1a0000 {
 248                                 label = "RPM";
 249                                 reg = <0x1a0000 0x80000>;
 250                                 read-only;
 251                         };
 252
 253                         partition@220000 {
 254                                 label = "APPSBL";
 255                                 reg = <0x220000 0x80000>;
 256                                 read-only;
 257
 258                                 nvmem-layout {
 259                                         compatible = "fixed-layout";
 260                                         #address-cells = <1>;
 261                                         #size-cells = <1>;
 262
 263                                         macaddr_appsbl_7ff80: mac-address@7ff80 {
 264                                                 compatible = "mac-base";
 265                                                 reg = <0x7ff80 0xc>;
 266                                                 #nvmem-cell-cells = <1>;
 267                                         };
 268                                 };
 269                         };
 270
 271                         partition@2a0000 {
 272                                 label = "APPSBLENV";
 273                                 reg = <0x2a0000 0x40000>;
 274                         };
 275
 276                         partition@2e0000 {
 277                                 label = "ART";
 278                                 reg = <0x2e0000 0x40000>;
 279                                 read-only;
 280                         };
 281
 282                         partition@320000 {
 283                                 label = "kernel";
 284                                 reg = <0x320000 0x600000>;
 285                         };
 286
 287                         partition@920000 {
 288                                 label = "ubi";
 289                                 reg = <0x920000 0x1400000>;
 290                         };
 291
 292                         partition@1d20000 {
 293                                 label = "reserved";
 294                                 reg = <0x1d20000 0x260000>;
 295                                 read-only;
 296                         };
 297
 298                         partition@1f80000 {
 299                                 label = "config";
 300                                 reg = <0x1f80000 0x80000>;
 301                                 read-only;
 302                         };
 303                 };
 304         };
 305 };
 306
 307 &hs_phy_1 {
 308         status = "okay";
 309 };
 310
 311 &ss_phy_1 {
 312         status = "okay";
 313 };
 314
 315 &usb3_1 {
 316         status = "okay";
 317
 318         pinctrl-0 = <&usb_pwr_en_pins>;
 319         pinctrl-names = "default";
 320 };
 321
 322 &pcie0 {
 323         status = "okay";
 324
 325         bridge@0,0 {
 326                 reg = <0x00000000 0 0 0 0>;
 327                 #address-cells = <3>;
 328                 #size-cells = <2>;
 329                 ranges;
 330
 331                 wifi@1,0 {
 332                         compatible = "pci168c,0040";
 333                         reg = <0x00010000 0 0 0 0>;
 334
 335                         nvmem-cells = <&macaddr_appsbl_7ff80 8>;
 336                         nvmem-cell-names = "mac-address";
 337                 };
 338         };
 339 };
 340
 341 &pcie1 {
 342         status = "okay";
 343
 344         max-link-speed = <1>;
 345
 346         bridge@0,0 {
 347                 reg = <0x00000000 0 0 0 0>;
 348                 #address-cells = <3>;
 349                 #size-cells = <2>;
 350                 ranges;
 351
 352                 wifi@1,0 {
 353                         compatible = "pci168c,0040";
 354                         reg = <0x00010000 0 0 0 0>;
 355
 356                         nvmem-cells = <&macaddr_appsbl_7ff80 16>;
 357                         nvmem-cell-names = "mac-address";
 358                 };
 359         };
 360 };
 361
 362 &adm_dma {
 363         status = "okay";
 364 };
 365
 366 &mdio0 {
 367         status = "okay";
 368
 369         #address-cells = <0x1>;
 370         #size-cells = <0x0>;
 371         gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
 372                         <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
 373         pinctrl-0 = <&mdio0_pins>;
 374         pinctrl-names = "default";
 375
 376         phy1: ethernet-phy@1 {
 377                 reg = <1>;
 378         };
 379
 380         phy2: ethernet-phy@2 {
 381                 reg = <2>;
 382         };
 383 };
 384
 385 &gmac0 {
 386         status = "okay";
 387
 388         phy-mode = "rgmii";
 389         qcom,id = <0>;
 390         pinctrl-0 = <&rgmii2_pins>;
 391         pinctrl-names = "default";
 392         nvmem-cells = <&macaddr_appsbl_7ff80 0>;
 393         nvmem-cell-names = "mac-address";
 394
 395         fixed-link {
 396                 speed = <1000>;
 397                 full-duplex;
 398         };
 399 };
 400
 401 &gmac2 {
 402         status = "okay";
 403
 404         phy-mode = "sgmii";
 405         qcom,id = <2>;
 406         nvmem-cells = <&macaddr_appsbl_7ff80 1>;
 407         nvmem-cell-names = "mac-address";
 408
 409         fixed-link {
 410                 speed = <1000>;
 411                 full-duplex;
 412         };
 413 };