target/linux/ipq40xx/files-6.1/arch/arm/boot/dts/qcom-ipq4029-ap-303h.dts

   1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
   2
   3 #include "qcom-ipq4019.dtsi"
   4 #include <dt-bindings/gpio/gpio.h>
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/soc/qcom,tcsr.h>
   7
   8 / {
   9         model = "Aruba AP-303H";
  10         compatible = "aruba,ap-303h";
  11
  12         aliases {
  13                 led-boot = &led_system_green;
  14                 led-failsafe = &led_system_red;
  15                 led-running = &led_system_green;
  16                 led-upgrade = &led_system_amber;
  17         };
  18
  19         memory {
  20                 device_type = "memory";
  21                 reg = <0x80000000 0x10000000>;
  22         };
  23
  24         soc {
  25                 rng@22000 {
  26                         status = "okay";
  27                 };
  28
  29                 mdio@90000 {
  30                         status = "okay";
  31                         pinctrl-0 = <&mdio_pins>;
  32                         pinctrl-names = "default";
  33
  34                         reset-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
  35                         reset-delay-us = <2000>;
  36                 };
  37
  38                 counter@4a1000 {
  39                         compatible = "qcom,qca-gcnt";
  40                         reg = <0x4a1000 0x4>;
  41                 };
  42
  43                 ess_tcsr@1953000 {
  44                         compatible = "qcom,tcsr";
  45                         reg = <0x1953000 0x1000>;
  46                         qcom,ess-interface-select = <TCSR_ESS_PSGMII>;
  47                 };
  48
  49                 tcsr@1949000 {
  50                         compatible = "qcom,tcsr";
  51                         reg = <0x1949000 0x100>;
  52                         qcom,wifi_glb_cfg = <TCSR_WIFI_GLB_CFG>;
  53                 };
  54
  55                 tcsr@194b000 {
  56                         compatible = "qcom,tcsr";
  57                         reg = <0x194b000 0x100>;
  58                         qcom,usb-hsphy-mode-select = <TCSR_USB_HSPHY_HOST_MODE>;
  59                 };
  60
  61                 tcsr@1957000 {
  62                         compatible = "qcom,tcsr";
  63                         reg = <0x1957000 0x100>;
  64                         qcom,wifi_noc_memtype_m0_m2 = <TCSR_WIFI_NOC_MEMTYPE_M0_M2>;
  65                 };
  66
  67                 usb2@60f8800 {
  68                         status = "okay";
  69                 };
  70
  71                 crypto@8e3a000 {
  72                         status = "okay";
  73                 };
  74
  75                 watchdog@b017000 {
  76                         status = "okay";
  77                 };
  78
  79                 i2c_0: i2c@78b7000 {
  80                         pinctrl-0 = <&i2c_0_pins>;
  81                         pinctrl-names = "default";
  82                         status = "okay";
  83
  84                         tpm@29 {
  85                                 /* No Driver */
  86                                 compatible = "atmel,at97sc3203";
  87                                 reg = <0x29>;
  88                                 read-only;
  89                         };
  90
  91                         power-monitor@40 {
  92                                 /* No driver */
  93                                 compatible = "isl,isl28022";
  94                                 reg = <0x40>;
  95                         };
  96                 };
  97         };
  98
  99         leds {
 100                 compatible = "gpio-leds";
 101
 102                 wifi_green {
 103                         label = "green:wifi";
 104                         gpios = <&tlmm 27 GPIO_ACTIVE_HIGH>;
 105                         linux,default-trigger = "phy0tpt";
 106                 };
 107
 108                 wifi_amber {
 109                         label = "amber:wifi";
 110                         gpios = <&tlmm 28 GPIO_ACTIVE_HIGH>;
 111                         linux,default-trigger = "phy1tpt";
 112                 };
 113
 114                 pse {
 115                         label = "green:pse";
 116                         gpios = <&tlmm 42 GPIO_ACTIVE_HIGH>;
 117                 };
 118
 119                 led_system_red: system_red {
 120                         label = "red:system";
 121                         gpios = <&tlmm 25 GPIO_ACTIVE_HIGH>;
 122                 };
 123
 124                 led_system_green: system_green {
 125                         label = "green:system";
 126                         gpios = <&tlmm 24 GPIO_ACTIVE_HIGH>;
 127                 };
 128
 129                 led_system_amber: system_amber {
 130                         label = "amber:system";
 131                         gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>;
 132                 };
 133         };
 134
 135         keys {
 136                 compatible = "gpio-keys";
 137
 138                 reset {
 139                         label = "Reset button";
 140                         gpios = <&tlmm 18 GPIO_ACTIVE_LOW>;
 141                         linux,code = <KEY_RESTART>;
 142                 };
 143         };
 144 };
 145
 146 &blsp_dma {
 147         status = "okay";
 148 };
 149
 150 &blsp1_uart1 {
 151         pinctrl-0 = <&serial_0_pins>;
 152         pinctrl-names = "default";
 153         status = "okay";
 154 };
 155
 156 &blsp1_uart2 {
 157         /* Texas Instruments CC2540T BLE radio */
 158         pinctrl-0 = <&serial_1_pins>;
 159         pinctrl-names = "default";
 160         status = "okay";
 161 };
 162
 163 &cryptobam {
 164         status = "okay";
 165 };
 166
 167 &qpic_bam {
 168         status = "okay";
 169 };
 170
 171 &tlmm {
 172         /*
 173          * In addition to the Pins listed below,
 174          * the following GPIOs have "features":
 175          * 39 - out - active low to force HW reset
 176          * 32 - out - active low to reset TPM
 177          * 43 - out - active low to reset BLE radio
 178          * 41 - out - pulse to set warm reset status
 179          * 34 - out - active low to enable PSE port
 180          * 22 - in  - active low when 802.3at powered
 181          * 29 - in  - active high when DC powered
 182          * 40 - in  - active low when reset due to cold HW reset
 183          * 30 - in  - active low when USB overcurrent detected
 184          * 35 - in  - interrupt line for power monitor chip
 185          * 31 - in  - active low when PSE port active
 186          */
 187         mdio_pins: mdio_pinmux {
 188                 mux_1 {
 189                         pins = "gpio6";
 190                         function = "mdio";
 191                         bias-pull-up;
 192                 };
 193                 mux_2 {
 194                         pins = "gpio7";
 195                         function = "mdc";
 196                         bias-pull-up;
 197                 };
 198         };
 199
 200         spi_0_pins: spi_0_pinmux {
 201                 pin {
 202                         function = "blsp_spi0";
 203                         pins = "gpio13", "gpio14", "gpio15";
 204                         drive-strength = <12>;
 205                         bias-disable;
 206                 };
 207                 pin_cs {
 208                         function = "gpio";
 209                         pins = "gpio12", "gpio59";
 210                         drive-strength = <2>;
 211                         bias-disable;
 212                         output-high;
 213                 };
 214         };
 215
 216         i2c_0_pins: i2c_0_pinmux {
 217                 mux {
 218                         pins = "gpio20", "gpio21";
 219                         function = "blsp_i2c0";
 220                         drive-strength = <4>;
 221                         bias-disable;
 222                 };
 223         };
 224
 225         serial_0_pins: serial_0_pinmux {
 226                 mux {
 227                         pins = "gpio16", "gpio17";
 228                         function = "blsp_uart0";
 229                         bias-disable;
 230                 };
 231         };
 232
 233         serial_1_pins: serial_1_pinmux {
 234                 mux {
 235                         pins = "gpio8", "gpio9";
 236                         function = "blsp_uart1";
 237                         bias-disable;
 238                 };
 239         };
 240
 241         usb-power {
 242                 line-name = "USB-power";
 243                 gpios = <23 GPIO_ACTIVE_HIGH>;
 244                 gpio-hog;
 245                 output-high;
 246         };
 247 };
 248
 249 &blsp1_spi1 {
 250         pinctrl-0 = <&spi_0_pins>;
 251         pinctrl-names = "default";
 252         status = "okay";
 253         cs-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>, <&tlmm 59 GPIO_ACTIVE_HIGH>;
 254
 255         flash@0 {
 256                 compatible = "jedec,spi-nor";
 257                 reg = <0>;
 258                 spi-max-frequency = <24000000>;
 259
 260                 partitions {
 261                         compatible = "fixed-partitions";
 262                         #address-cells = <1>;
 263                         #size-cells = <1>;
 264
 265                         /*
 266                          * There is no partition map for the NOR flash
 267                          * in the stock firmware.
 268                          *
 269                          * All partitions here are based on offsets
 270                          * found in the U-Boot GPL code and information
 271                          * from smem.
 272                          */
 273
 274                         partition@0 {
 275                                 label = "sbl1";
 276                                 reg = <0x0 0x40000>;
 277                                 read-only;
 278                         };
 279
 280                         partition@40000 {
 281                                 label = "mibib";
 282                                 reg = <0x40000 0x20000>;
 283                                 read-only;
 284                         };
 285
 286                         partition@60000 {
 287                                 label = "qsee";
 288                                 reg = <0x60000 0x60000>;
 289                                 read-only;
 290                         };
 291
 292                         partition@c0000 {
 293                                 label = "cdt";
 294                                 reg = <0xc0000 0x10000>;
 295                                 read-only;
 296                         };
 297
 298                         partition@d0000 {
 299                                 label = "ddrparams";
 300                                 reg = <0xd0000 0x10000>;
 301                                 read-only;
 302                         };
 303
 304                         partition@e0000 {
 305                                 label = "appsblenv";
 306                                 reg = <0xe0000 0x10000>;
 307                                 read-only;
 308                         };
 309
 310                         partition@f0000 {
 311                                 label = "appsbl";
 312                                 reg = <0xf0000 0x100000>;
 313                                 read-only;
 314                         };
 315
 316                         partition@1e0000 {
 317                                 label = "ART";
 318                                 reg = <0x1f0000 0x10000>;
 319                                 read-only;
 320
 321                                 nvmem-layout {
 322                                         compatible = "fixed-layout";
 323                                         #address-cells = <1>;
 324                                         #size-cells = <1>;
 325
 326                                         precal_art_1000: precal@1000 {
 327                                                 reg = <0x1000 0x2f20>;
 328                                         };
 329
 330                                         precal_art_5000: precal@5000 {
 331                                                 reg = <0x5000 0x2f20>;
 332                                         };
 333                                 };
 334                         };
 335
 336                         partition@1f0000 {
 337                                 label = "osss";
 338                                 reg = <0x200000 0x170000>;
 339                                 read-only;
 340                         };
 341
 342                         partition@200000 {
 343                                 label = "pds";
 344                                 reg = <0x370000 0x10000>;
 345                                 read-only;
 346                         };
 347
 348                         partition@380000 {
 349                                 label = "apcd";
 350                                 reg = <0x380000 0x10000>;
 351                                 read-only;
 352                         };
 353
 354                         partition@390000 {
 355                                 label = "mfginfo";
 356                                 reg = <0x390000 0x10000>;
 357                                 read-only;
 358
 359                                 nvmem-layout {
 360                                         compatible = "fixed-layout";
 361                                         #address-cells = <1>;
 362                                         #size-cells = <1>;
 363
 364                                         macaddr_mfginfo_1d: macaddr@1d {
 365                                                 reg = <0x1d 0x6>;
 366                                         };
 367
 368                                         macaddr_mfginfo_45: macaddr@45 {
 369                                                 compatible = "mac-base";
 370                                                 reg = <0x45 0x6>;
 371                                                 #nvmem-cell-cells = <1>;
 372                                         };
 373                                 };
 374                         };
 375
 376                         partition@3a0000 {
 377                                 label = "fcache";
 378                                 reg = <0x3a0000 0x10000>;
 379                                 read-only;
 380                         };
 381
 382                         partition@3b0000 {
 383                                 /* Called osss1 in smem */
 384                                 label = "u-boot-env-bak";
 385                                 reg = <0x3b0000 0x10000>;
 386                                 read-only;
 387                         };
 388
 389                         partition@3f0000 {
 390                                 label = "u-boot-env";
 391                                 reg = <0x3c0000 0x40000>;
 392                                 read-only;
 393                         };
 394                 };
 395         };
 396
 397         flash@1 {
 398                 status = "okay";
 399
 400                 compatible = "spi-nand";
 401                 reg = <1>;
 402                 spi-max-frequency = <24000000>;
 403
 404                 partitions {
 405                         compatible = "fixed-partitions";
 406                         #address-cells = <1>;
 407                         #size-cells = <1>;
 408
 409                         partition@0 {
 410                                 /* 'aos0' in Aruba firmware */
 411                                 label = "aos0";
 412                                 reg = <0x0 0x2000000>;
 413                                 read-only;
 414                         };
 415
 416                         partition@2000000 {
 417                                 /* 'aos1' in Aruba firmware */
 418                                 label = "ubi";
 419                                 reg = <0x2000000 0x2000000>;
 420                         };
 421
 422                         partition@4000000 {
 423                                 label = "aruba-ubifs";
 424                                 reg = <0x4000000 0x4000000>;
 425                                 read-only;
 426                         };
 427                 };
 428         };
 429 };
 430
 431 &usb2_hs_phy {
 432         status = "okay";
 433 };
 434
 435 &gmac {
 436         status = "okay";
 437 };
 438
 439 &switch {
 440         status = "okay";
 441 };
 442
 443 &swport2 {
 444         status = "okay";
 445
 446         label = "lan1";
 447 };
 448
 449 &swport3 {
 450         status = "okay";
 451
 452         label = "lan2";
 453 };
 454
 455 &swport4 {
 456         status = "okay";
 457
 458         label = "lan3";
 459 };
 460
 461 &swport5 {
 462         status = "okay";
 463
 464         label = "wan";
 465 };
 466
 467 &wifi0 {
 468         status = "okay";
 469         nvmem-cell-names = "pre-calibration", "mac-address";
 470         nvmem-cells = <&precal_art_1000>, <&macaddr_mfginfo_45 0>;
 471         qcom,ath10k-calibration-variant = "Aruba-AP-303";
 472 };
 473
 474 &wifi1 {
 475         status = "okay";
 476         nvmem-cell-names = "pre-calibration", "mac-address";
 477         nvmem-cells = <&precal_art_5000>, <&macaddr_mfginfo_45 1>;
 478         qcom,ath10k-calibration-variant = "Aruba-AP-303";
 479 };