arm64: versal: Add support for new Xilinx Versal ACAPs
authorMichal Simek <michal.simek@xilinx.com>
Wed, 22 Aug 2018 12:55:27 +0000 (14:55 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Tue, 16 Oct 2018 14:53:21 +0000 (16:53 +0200)
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
Engines with leading-edge memory and interfacing technologies to deliver
powerful heterogeneous acceleration for any application. The Versal AI
Core series has five devices, offering 128 to 400 AI Engines. The series
includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
than 1,900 DSP engines optimized for high-precision floating point with
low latency.

The patch is adding necessary infrastructure in place without enabling
platform which is done in separate patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
19 files changed:
Kconfig
MAINTAINERS
arch/arm/Kconfig
arch/arm/Makefile
arch/arm/mach-versal/Kconfig [new file with mode: 0644]
arch/arm/mach-versal/Makefile [new file with mode: 0644]
arch/arm/mach-versal/clk.c [new file with mode: 0644]
arch/arm/mach-versal/cpu.c [new file with mode: 0644]
arch/arm/mach-versal/include/mach/gpio.h [new file with mode: 0644]
arch/arm/mach-versal/include/mach/hardware.h [new file with mode: 0644]
arch/arm/mach-versal/include/mach/sys_proto.h [new file with mode: 0644]
board/xilinx/versal/MAINTAINERS [new file with mode: 0644]
board/xilinx/versal/Makefile [new file with mode: 0644]
board/xilinx/versal/board.c [new file with mode: 0644]
drivers/mmc/Kconfig
drivers/net/Kconfig
drivers/spi/Kconfig
env/Kconfig
include/configs/xilinx_versal.h [new file with mode: 0644]

diff --git a/Kconfig b/Kconfig
index 1aadf5dd2d793bcb85368e9554085ad45c102eeb..dca9bb4e432929863ae79ab85b5e2f8100cfa16d 100644 (file)
--- a/Kconfig
+++ b/Kconfig
@@ -144,7 +144,7 @@ config SYS_MALLOC_F_LEN
 
 config SYS_MALLOC_LEN
        hex "Define memory for Dynamic allocation"
-       depends on ARCH_ZYNQ
+       depends on ARCH_ZYNQ || ARCH_VERSAL
        help
          This defines memory to be allocated for Dynamic allocation
          TODO: Use for other architectures
index ace7d9a4b64dbdada0f75c739cde22da59896b5a..fcb963e3bef3cf95e52cce28b6bdae8b627f5bc3 100644 (file)
@@ -287,6 +287,12 @@ F: arch/arm/mach-uniphier/
 F:     configs/uniphier_*_defconfig
 N:     uniphier
 
+ARM VERSAL
+M:     Michal Simek <michal.simek@xilinx.com>
+S:     Maintained
+T:     git git://git.denx.de/u-boot-microblaze.git
+F:     arch/arm/mach-versal/
+
 ARM VERSATILE EXPRESS DRIVERS
 M:     Liviu Dudau <liviu.dudau@foss.arm.com>
 S:     Maintained
index ccf2a844be8d44e5ba471e186143c86c6c939b60..3ba8efd9b62be7f05a8d1d0039d4ff612e339d10 100644 (file)
@@ -853,6 +853,14 @@ config ARCH_SUNXI
        imply SPL_SERIAL_SUPPORT
        imply USB_GADGET
 
+config ARCH_VERSAL
+       bool "Support Xilinx Versal Platform"
+       select ARM64
+       select CLK
+       select DM
+       select DM_SERIAL
+       select OF_CONTROL
+
 config ARCH_VF610
        bool "Freescale Vybrid"
        select CPU_V7A
@@ -1449,6 +1457,8 @@ source "arch/arm/cpu/armv7/vf610/Kconfig"
 
 source "arch/arm/mach-zynq/Kconfig"
 
+source "arch/arm/mach-versal/Kconfig"
+
 source "arch/arm/mach-zynqmp-r5/Kconfig"
 
 source "arch/arm/cpu/armv7/Kconfig"
index 8f50560434b91d0f1daa5528833791f7e8041a9d..e52a35db181038c26a078358e936aa7fa19880ee 100644 (file)
@@ -80,6 +80,7 @@ machine-$(CONFIG_ARCH_STM32MP)                += stm32mp
 machine-$(CONFIG_TEGRA)                        += tegra
 machine-$(CONFIG_ARCH_UNIPHIER)                += uniphier
 machine-$(CONFIG_ARCH_ZYNQ)            += zynq
+machine-$(CONFIG_ARCH_VERSAL)          += versal
 machine-$(CONFIG_ARCH_ZYNQMP_R5)       += zynqmp-r5
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
new file mode 100644 (file)
index 0000000..04dbaea
--- /dev/null
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+if ARCH_VERSAL
+
+config SYS_BOARD
+       string "Board name"
+       default "versal"
+
+config SYS_VENDOR
+       string "Vendor name"
+       default "xilinx"
+
+config SYS_SOC
+       default "versal"
+
+config SYS_CONFIG_NAME
+       string "Board configuration name"
+       default "xilinx_versal"
+       help
+         This option contains information about board configuration name.
+         Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
+         will be used for board configuration.
+
+config GICV3
+       def_bool y
+
+config SYS_MALLOC_LEN
+       default 0x2000000
+
+config COUNTER_FREQUENCY
+       int "Timer clock frequency"
+       default 0
+       help
+         Setup time clock frequency for certain platform
+
+config ZYNQ_SDHCI_MAX_FREQ
+       default 200000000
+
+endif
diff --git a/arch/arm/mach-versal/Makefile b/arch/arm/mach-versal/Makefile
new file mode 100644 (file)
index 0000000..c230239
--- /dev/null
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 - 2018 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+
+obj-y  += clk.o
+obj-y  += cpu.o
diff --git a/arch/arm/mach-versal/clk.c b/arch/arm/mach-versal/clk.c
new file mode 100644 (file)
index 0000000..b82cea4
--- /dev/null
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 - 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CLOCKS
+/**
+ * set_cpu_clk_info - Initialize clock framework
+ *
+ * Return: 0 always.
+ *
+ * This function is called from common code after relocation and sets up the
+ * clock framework. The framework must not be used before this function had been
+ * called.
+ */
+int set_cpu_clk_info(void)
+{
+       gd->cpu_clk = get_tbclk();
+
+       gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
+       gd->bd->bi_dsp_freq = 0;
+
+       return 0;
+}
+#endif
diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c
new file mode 100644 (file)
index 0000000..959570e
--- /dev/null
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 - 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <asm/io.h>
+
+static struct mm_region versal_mem_map[] = {
+       {
+               .virt = 0x0UL,
+               .phys = 0x0UL,
+               .size = 0x80000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0x80000000UL,
+               .phys = 0x80000000UL,
+               .size = 0x70000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               .virt = 0xf0000000UL,
+               .phys = 0xf0000000UL,
+               .size = 0x0fe00000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               .virt = 0xffe00000UL,
+               .phys = 0xffe00000UL,
+               .size = 0x00200000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0x400000000UL,
+               .phys = 0x400000000UL,
+               .size = 0x200000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               .virt = 0x600000000UL,
+               .phys = 0x600000000UL,
+               .size = 0x800000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+                        PTE_BLOCK_INNER_SHARE
+       }, {
+               .virt = 0xe00000000UL,
+               .phys = 0xe00000000UL,
+               .size = 0xf200000000UL,
+               .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+                        PTE_BLOCK_NON_SHARE |
+                        PTE_BLOCK_PXN | PTE_BLOCK_UXN
+       }, {
+               /* List terminator */
+               0,
+       }
+};
+
+struct mm_region *mem_map = versal_mem_map;
+
+u64 get_page_table_size(void)
+{
+       return 0x14000;
+}
diff --git a/arch/arm/mach-versal/include/mach/gpio.h b/arch/arm/mach-versal/include/mach/gpio.h
new file mode 100644 (file)
index 0000000..677facb
--- /dev/null
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - 2018 Xilinx, Inc.
+ */
+
+/* Empty file - for compilation */
diff --git a/arch/arm/mach-versal/include/mach/hardware.h b/arch/arm/mach-versal/include/mach/hardware.h
new file mode 100644 (file)
index 0000000..aad7426
--- /dev/null
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - 2018 Xilinx, Inc.
+ */
+
+#define VERSAL_CRL_APB_BASEADDR        0xFF5E0000
+
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT  BIT(25)
+
+#define IOU_SWITCH_CTRL_CLKACT_BIT     BIT(25)
+#define IOU_SWITCH_CTRL_DIVISOR0_SHIFT 8
+
+struct crlapb_regs {
+       u32 reserved0[69];
+       u32 iou_switch_ctrl; /* 0x114 */
+       u32 reserved1[13];
+       u32 timestamp_ref_ctrl; /* 0x14c */
+       u32 reserved2[126];
+       u32 rst_timestamp; /* 0x348 */
+};
+
+#define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR)
+
+#define VERSAL_IOU_SCNTR_SECURE        0xFF140000
+
+#define IOU_SCNTRS_CONTROL_EN  1
+
+struct iou_scntrs_regs {
+       u32 counter_control_register; /* 0x0 */
+       u32 reserved0[7];
+       u32 base_frequency_id_register; /* 0x20 */
+};
+
+#define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_IOU_SCNTR_SECURE)
diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h
new file mode 100644 (file)
index 0000000..677facb
--- /dev/null
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2016 - 2018 Xilinx, Inc.
+ */
+
+/* Empty file - for compilation */
diff --git a/board/xilinx/versal/MAINTAINERS b/board/xilinx/versal/MAINTAINERS
new file mode 100644 (file)
index 0000000..2d2b808
--- /dev/null
@@ -0,0 +1,7 @@
+XILINX_VERSAL BOARDS
+M:     Michal Simek <michal.simek@xilinx.com>
+S:     Maintained
+F:     arch/arm/dts/versal*
+F:     board/xilinx/versal/
+F:     include/configs/xilinx_versal*
+F:     configs/xilinx_versal*
diff --git a/board/xilinx/versal/Makefile b/board/xilinx/versal/Makefile
new file mode 100644 (file)
index 0000000..2b81276
--- /dev/null
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2016 - 2018 Xilinx, Inc.
+# Michal Simek <michal.simek@xilinx.com>
+#
+
+obj-y  := board.o
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
new file mode 100644 (file)
index 0000000..2b3a40b
--- /dev/null
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2014 - 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+       printf("EL Level:\tEL%d\n", current_el());
+
+       return 0;
+}
+
+int board_early_init_r(void)
+{
+       if (current_el() == 3) {
+               u32 val;
+
+               writel(IOU_SWITCH_CTRL_CLKACT_BIT |
+                      (0x20 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
+                      &crlapb_base->iou_switch_ctrl);
+
+               /* Global timer init - Program time stamp reference clk */
+               val = readl(&crlapb_base->timestamp_ref_ctrl);
+               val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
+               writel(val, &crlapb_base->timestamp_ref_ctrl);
+
+               debug("ref ctrl 0x%x\n",
+                     readl(&crlapb_base->timestamp_ref_ctrl));
+
+               /* Clear reset of timestamp reg */
+               writel(0, &crlapb_base->rst_timestamp);
+
+               /*
+                * Program freq register in System counter and
+                * enable system counter.
+                */
+               writel(COUNTER_FREQUENCY,
+                      &iou_scntr_secure->base_frequency_id_register);
+
+               debug("counter val 0x%x\n",
+                     readl(&iou_scntr_secure->base_frequency_id_register));
+
+               writel(IOU_SCNTRS_CONTROL_EN,
+                      &iou_scntr_secure->counter_control_register);
+
+               debug("scntrs control 0x%x\n",
+                     readl(&iou_scntr_secure->counter_control_register));
+               debug("timer 0x%llx\n", get_ticks());
+               debug("timer 0x%llx\n", get_ticks());
+       }
+
+       return 0;
+}
+
+int dram_init_banksize(void)
+{
+       fdtdec_setup_memory_banksize();
+
+       return 0;
+}
+
+int dram_init(void)
+{
+       if (fdtdec_setup_mem_size_base() != 0)
+               return -EINVAL;
+
+       return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
index 0a0d4aaf6ca0d4438fd184261108ee5aceaf1839..27246ee465807a033eb3356aea6302309a35a48d 100644 (file)
@@ -538,7 +538,7 @@ config MMC_SDHCI_TEGRA
 
 config MMC_SDHCI_ZYNQ
        bool "Arasan SDHCI controller support"
-       depends on ARCH_ZYNQ || ARCH_ZYNQMP
+       depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
        depends on DM_MMC && OF_CONTROL && BLK
        depends on MMC_SDHCI
        help
index 5441da47d13ef55a27cb70fda4a8021b5e4964f3..f1f0e2d94ef164ce4666bc6bf222006e374c510f 100644 (file)
@@ -344,7 +344,7 @@ config XILINX_EMACLITE
          This MAC is present in Xilinx Microblaze, Zynq and ZynqMP SoCs.
 
 config ZYNQ_GEM
-       depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP)
+       depends on DM_ETH && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL)
        select PHYLIB
        bool "Xilinx Ethernet GEM"
        help
index 1df6876e9bdad08a47060483ae29198ba2d416ae..516188ea88e141fb421f8ee45b973f21ed59f22d 100644 (file)
@@ -243,7 +243,7 @@ config XILINX_SPI
 
 config ZYNQ_SPI
        bool "Zynq SPI driver"
-       depends on ARCH_ZYNQ || ARCH_ZYNQMP
+       depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
        help
          Enable the Zynq SPI driver. This driver can be used to
          access the SPI NOR flash on platforms embedding this Zynq
@@ -260,7 +260,7 @@ config ZYNQ_QSPI
 
 config ZYNQMP_GQSPI
        bool "Configure ZynqMP Generic QSPI"
-       depends on ARCH_ZYNQMP
+       depends on ARCH_ZYNQMP || ARCH_VERSAL
        help
          This option is used to enable ZynqMP QSPI controller driver which
          is used to communicate with qspi flash devices.
index f23be00a547fd43c4b127778b73000e56a3105c2..9011109b47b781f30220f1c8b8296ac3d32de2f8 100644 (file)
@@ -431,7 +431,7 @@ config ENV_EXT4_FILE
          It's a string of the EXT4 file name. This file use to store the
          environment (explicit path to the file)
 
-if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP
+if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
 
 config ENV_OFFSET
        hex "Environment Offset"
@@ -448,7 +448,7 @@ config ENV_SIZE
        hex "Environment Size"
        default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
        default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ
-       default 0x8000 if ARCH_ROCKCHIP || ARCH_ZYNQMP
+       default 0x8000 if ARCH_ROCKCHIP || ARCH_ZYNQMP || ARCH_VERSAL
        help
          Size of the environment storage area
 
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
new file mode 100644 (file)
index 0000000..bfe4c43
--- /dev/null
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration for Xilinx Versal
+ * (C) Copyright 2016 - 2018 Xilinx, Inc.
+ * Michal Simek <michal.simek@xilinx.com>
+ *
+ * Based on Configuration for Xilinx ZynqMP
+ */
+
+#ifndef __XILINX_VERSAL_H
+#define __XILINX_VERSAL_H
+
+#define CONFIG_REMAKE_ELF
+
+/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE      0xF9000000
+#define GICR_BASE      0xF9080000
+
+#define CONFIG_SYS_MEMTEST_SCRATCH     0xfffc0000
+
+#define CONFIG_SYS_MEMTEST_START       0
+#define CONFIG_SYS_MEMTEST_END         1000
+
+#define CONFIG_SYS_INIT_SP_ADDR                CONFIG_SYS_TEXT_BASE
+
+/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */
+#if CONFIG_COUNTER_FREQUENCY
+# define COUNTER_FREQUENCY     CONFIG_COUNTER_FREQUENCY
+#endif
+
+/* Serial setup */
+#define CONFIG_ARM_DCC
+#define CONFIG_CPU_ARMV8
+
+#define CONFIG_SYS_BAUDRATE_TABLE \
+       { 4800, 9600, 19200, 38400, 57600, 115200 }
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_MAY_FAIL
+
+#define CONFIG_IP_DEFRAG
+#define CONFIG_TFTP_BLOCKSIZE  4096
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR           0x8000000
+
+/* Monitor Command Prompt */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_MAXARGS             64
+
+/* Ethernet driver */
+#if defined(CONFIG_ZYNQ_GEM)
+# define CONFIG_NET_MULTI
+# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+# define PHY_ANEG_TIMEOUT       20000
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN   (60 * 1024 * 1024)
+
+#define CONFIG_CLOCKS
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+       "fdt_high=10000000\0" \
+       "initrd_high=10000000\0" \
+       "fdt_addr_r=0x40000000\0" \
+       "pxefile_addr_r=0x10000000\0" \
+       "kernel_addr_r=0x18000000\0" \
+       "scriptaddr=0x02000000\0" \
+       "ramdisk_addr_r=0x02100000\0"
+
+#define BOOT_TARGET_DEVICES(func) \
+       func(PXE, pxe, na) \
+       func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+/* Initial environment variables */
+#ifndef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+       ENV_MEM_LAYOUT_SETTINGS \
+       BOOTENV
+#endif
+
+#endif /* __XILINX_VERSAL_H */