Merge changes from topic "stm32mp_corrections_w40" into integration

* changes:
  gpio: stm32_gpio: do not mix error code types
  fdts: stm32mp1: move FDCAN to PLL4_R
  mmc: increase delay between ACMD41 retries
  crypto: stm32_hash: align stm32_hash_update() prototype

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index db6f3f9e47b9edbf189aba3b7db5c348ab8fb4b8..b5f6a10d38189a919e458f5727aac1447a41b9f0 100644 (file)
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -361,7 +361,7 @@ static int sd_send_op_cond(void)
                        return 0;
                }
 
-               mdelay(1);
+               mdelay(10);
        }
 
        ERROR("ACMD41 failed after %d retries\n", SEND_OP_COND_MAX_RETRIES);

diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 343ad6c1de831412d91bb75d868b130cf2e96b84..a13c341a81657bc3f3b1dae1b9cac1456ea60dc5 100644 (file)
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -165,7 +165,7 @@ int dt_set_pinctrl_config(int node)
        void *fdt;
 
        if (fdt_get_address(&fdt) == 0) {
-               return -ENOENT;
+               return -FDT_ERR_NOTFOUND;
        }
 
        if (status == DT_DISABLED) {

diff --git a/fdts/stm32mp157a-avenger96.dts b/fdts/stm32mp157a-avenger96.dts
index 9df72b44446a965e02a7ffe33b060fcf9407fcb2..907940c785429fe218ffbc155eb08c7d852e431e 100644 (file)
--- a/fdts/stm32mp157a-avenger96.dts
+++ b/fdts/stm32mp157a-avenger96.dts
@@ -246,7 +246,7 @@
                CLK_UART6_HSI
                CLK_UART78_HSI
                CLK_SPDIF_PLL4P
-               CLK_FDCAN_PLL4Q
+               CLK_FDCAN_PLL4R
                CLK_SAI1_PLL3Q
                CLK_SAI2_PLL3Q
                CLK_SAI3_PLL3Q

diff --git a/fdts/stm32mp157a-dk1.dts b/fdts/stm32mp157a-dk1.dts
index b17d50194e203081749d7813be2e4210b18d89c8..4ea83f7cde68dc5f4cdf9d12db0fcae1565ba624 100644 (file)
--- a/fdts/stm32mp157a-dk1.dts
+++ b/fdts/stm32mp157a-dk1.dts
@@ -266,7 +266,7 @@
                CLK_UART6_HSI
                CLK_UART78_HSI
                CLK_SPDIF_PLL4P
-               CLK_FDCAN_PLL4Q
+               CLK_FDCAN_PLL4R
                CLK_SAI1_PLL3Q
                CLK_SAI2_PLL3Q
                CLK_SAI3_PLL3Q

diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
index ed55725b02b4bfa5eafc8f3f5b153dd908345937..7794925523aec7c99454ca968e534310fae41b59 100644 (file)
--- a/fdts/stm32mp157c-ed1.dts
+++ b/fdts/stm32mp157c-ed1.dts
@@ -272,7 +272,7 @@
                CLK_UART6_HSI
                CLK_UART78_HSI
                CLK_SPDIF_PLL4P
-               CLK_FDCAN_PLL4Q
+               CLK_FDCAN_PLL4R
                CLK_SAI1_PLL3Q
                CLK_SAI2_PLL3Q
                CLK_SAI3_PLL3Q

diff --git a/include/drivers/st/stm32_hash.h b/include/drivers/st/stm32_hash.h
index 969d7aa1346e1b5a98ebef37a3563aba1390dde3..df04730d6d60dbb7b46924c12ddab751aea99ae8 100644 (file)
--- a/include/drivers/st/stm32_hash.h
+++ b/include/drivers/st/stm32_hash.h
@@ -14,7 +14,7 @@ enum stm32_hash_algo_mode {
        HASH_SHA256
 };
 
-int stm32_hash_update(const uint8_t *buffer, uint32_t length);
+int stm32_hash_update(const uint8_t *buffer, size_t length);
 int stm32_hash_final(uint8_t *digest);
 int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length,
                            uint8_t *digest);