#error "Invalid granule size. AArch32 supports 4KB pages only."
#endif
-#define MIN_LVL_BLOCK_DESC 1
+#define MIN_LVL_BLOCK_DESC U(1)
#define XLAT_TABLE_LEVEL_MIN U(1)
* [1] See the ARMv8-A Architecture Reference Manual (DDI 0487A.j) for more
* information, Section G4.6.5
*/
-#define MIN_VIRT_ADDR_SPACE_SIZE (1 << (32 - TTBCR_TxSZ_MAX))
+#define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (32 - TTBCR_TxSZ_MAX))
#define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (32 - TTBCR_TxSZ_MIN))
/*
* CHECK_VIRT_ADDR_SPACE_SIZE() macro first.
*/
#define GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size) \
- (((virt_addr_space_size) > (1 << L1_XLAT_ADDRESS_SHIFT)) ? 1 : 2)
+ (((virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) ? 1 : 2)
#endif /* __XLAT_TABLES_AARCH32_H__ */
* descriptors.
*/
#if PAGE_SIZE == (4 * 1024)
-# define MIN_LVL_BLOCK_DESC 1
+# define MIN_LVL_BLOCK_DESC U(1)
#elif PAGE_SIZE == (16 * 1024) || PAGE_SIZE == (64 * 1024)
-# define MIN_LVL_BLOCK_DESC 2
+# define MIN_LVL_BLOCK_DESC U(2)
#endif
#define XLAT_TABLE_LEVEL_MIN U(0)
* information:
* Page 1730: 'Input address size', 'For all translation stages'.
*/
-#define MIN_VIRT_ADDR_SPACE_SIZE (1 << (64 - TCR_TxSZ_MAX))
+#define MIN_VIRT_ADDR_SPACE_SIZE (ULL(1) << (64 - TCR_TxSZ_MAX))
#define MAX_VIRT_ADDR_SPACE_SIZE (ULL(1) << (64 - TCR_TxSZ_MIN))
/*
#define GET_XLAT_TABLE_LEVEL_BASE(virt_addr_space_size) \
(((virt_addr_space_size) > (ULL(1) << L0_XLAT_ADDRESS_SHIFT)) \
? 0 \
- : (((virt_addr_space_size) > (1 << L1_XLAT_ADDRESS_SHIFT)) ? 1 : 2))
+ : (((virt_addr_space_size) > (ULL(1) << L1_XLAT_ADDRESS_SHIFT)) \
+ ? 1 : 2))
#endif /* __XLAT_TABLES_AARCH64_H__ */
ttbcr = TTBCR_EAE_BIT |
TTBCR_SH0_NON_SHAREABLE | TTBCR_RGN0_OUTER_NC |
TTBCR_RGN0_INNER_NC |
- (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
+ (32 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE));
} else {
/* Inner & outer WBWA & shareable. */
ttbcr = TTBCR_EAE_BIT |
TTBCR_SH0_INNER_SHAREABLE | TTBCR_RGN0_OUTER_WBA |
TTBCR_RGN0_INNER_WBA |
- (32 - __builtin_ctzl((uintptr_t)PLAT_VIRT_ADDR_SPACE_SIZE));
+ (32 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE));
}
ttbcr |= TTBCR_EPD1_BIT;
write_ttbcr(ttbcr);
/* Inner & outer non-cacheable non-shareable. */\
tcr = TCR_SH_NON_SHAREABLE | \
TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC | \
- (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+ (64 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE));\
} else { \
/* Inner & outer WBWA & shareable. */ \
tcr = TCR_SH_INNER_SHAREABLE | \
TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \
- (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+ (64 - __builtin_ctzll(PLAT_VIRT_ADDR_SPACE_SIZE));\
} \
tcr |= _tcr_extra; \
write_tcr_el##_el(tcr); \
uintptr_t virtual_addr_space_size = max_va + 1;
assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size));
/*
- * __builtin_ctzl(0) is undefined but here we are guaranteed
+ * __builtin_ctzll(0) is undefined but here we are guaranteed
* that virtual_addr_space_size is in the range [1, UINT32_MAX].
*/
- ttbcr |= 32 - __builtin_ctzl(virtual_addr_space_size);
+ ttbcr |= 32 - __builtin_ctzll(virtual_addr_space_size);
}
/*
uintptr_t virtual_addr_space_size = max_va + 1;
assert(CHECK_VIRT_ADDR_SPACE_SIZE(virtual_addr_space_size));
/*
- * __builtin_ctzl(0) is undefined but here we are guaranteed that
+ * __builtin_ctzll(0) is undefined but here we are guaranteed that
* virtual_addr_space_size is in the range [1,UINTPTR_MAX].
*/
- tcr = 64 - __builtin_ctzl(virtual_addr_space_size);
+ tcr = 64 - __builtin_ctzll(virtual_addr_space_size);
/*
* Set the cacheability and shareability attributes for memory
*/
static action_t xlat_tables_map_region_action(const mmap_region_t *mm,
const int desc_type, const unsigned long long dest_pa,
- const uintptr_t table_entry_base_va, const int level)
+ const uintptr_t table_entry_base_va, const unsigned int level)
{
uintptr_t mm_end_va = mm->base_va + mm->size - 1;
uintptr_t table_entry_end_va =