target/linux/ramips/patches-6.1/005-v6.5-02-clk-ralink-add-clock-and-reset-driver-for-MTMIPS-SoC.patch

   1 From 6f3b15586eef736831abe6a14f2a6906bc0dc074 Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Mon, 19 Jun 2023 06:09:34 +0200
   4 Subject: [PATCH 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs
   5
   6 Until now, clock related code for old ralink SoCs was based in fixed clocks
   7 using 'clk_register_fixed_rate' and 'clkdev_create' directly doing in code
   8 and not using device tree at all for their definition. Including this driver
   9 is an effort to be able to define proper clocks using device tree and also
  10 cleaning all the clock and reset related code from 'arch/mips/ralink' dir.
  11 This clock and reset driver covers all the ralink SoCs but MT7621 which is
  12 the newest and provides gating and some differences that make it different
  13 from its predecesors. It has its own driver since some time ago. The ralink
  14 SoCs we are taking about are RT2880, RT3050, RT3052, RT3350, RT3352, RT3883,
  15 RT5350, MT7620, MT7628 and MT7688. Mostly the code in this new driver has
  16 been extracted from 'arch/mips/ralink' and cleanly put using kernel clock
  17 driver APIs. The clock plans for this SoCs only talks about relation between
  18 CPU frequency and BUS frequency. This relation is different depending on the
  19 particular SoC. CPU clock is derived from XTAL frequencies.
  20
  21 Depending on the SoC we have the following frequencies:
  22 * RT2880 SoC:
  23     - XTAL: 40 MHz.
  24     - CPU: 250, 266, 280 or 300 MHz.
  25     - BUS: CPU / 2 MHz.
  26 * RT3050, RT3052, RT3350:
  27     - XTAL: 40 MHz.
  28     - CPU: 320 or 384 MHz.
  29     - BUS: CPU / 3 MHz.
  30 * RT3352:
  31     - XTAL: 40 MHz.
  32     - CPU: 384 or 400 MHz.
  33     - BUS: CPU / 3 MHz.
  34     - PERIPH: 40 MHz.
  35 * RT3383:
  36     - XTAL: 40 MHz.
  37     - CPU: 250, 384, 480 or 500 MHz.
  38     - BUS: Depends on RAM Type and CPU:
  39         + RAM DDR2: 125. ELSE 83 MHz.
  40         + RAM DDR2: 128. ELSE 96 MHz.
  41         + RAM DDR2: 160. ELSE 120 MHz.
  42         + RAM DDR2: 166. ELSE 125 MHz.
  43 * RT5350:
  44     - XTAL: 40 MHz.
  45     - CPU: 300, 320 or 360 MHz.
  46     - BUS: CPU / 3, CPU / 4, CPU / 3 MHz.
  47     - PERIPH: 40 MHz.
  48 * MT7628 and MT7688:
  49     - XTAL: 20 MHz or 40 MHz.
  50     - CPU: 575 or 580 MHz.
  51     - BUS: CPU / 3.
  52     - PCMI2S: 480 MHz.
  53     - PERIPH: 40 MHz.
  54 * MT7620:
  55     - XTAL: 20 MHz or 40 MHz.
  56     - PLL: XTAL, 480, 600 MHz.
  57     - CPU: depends on PLL and some mult and dividers.
  58     - BUS: depends on PLL and some mult and dividers.
  59     - PERIPH: 40 or XTAL MHz.
  60
  61 MT7620 is a bit more complex deriving CPU clock from a PLL and an bunch of
  62 register reads and predividers. To derive CPU and BUS frequencies in the
  63 MT7620 SoC 'mt7620_calc_rate()' helper is used.
  64
  65 In the case XTAL can have different frequencies and we need a different
  66 clock frequency for peripherals 'periph' clock in introduced.
  67
  68 The rest of the peripherals present in the SoC just follow their parent
  69 frequencies.
  70
  71 With this information the clk driver will provide all the clock and reset
  72 functionality from a set of hardcoded clocks allowing to define a nice
  73 device tree without fixed clocks.
  74
  75 Acked-by: Stephen Boyd <sboyd@kernel.org>
  76 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  77 Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
  78 ---
  79  drivers/clk/ralink/Kconfig      |    7 +
  80  drivers/clk/ralink/Makefile     |    1 +
  81  drivers/clk/ralink/clk-mtmips.c | 1115 +++++++++++++++++++++++++++++++++++++++
  82  3 files changed, 1123 insertions(+)
  83  create mode 100644 drivers/clk/ralink/clk-mtmips.c
  84
  85 --- a/drivers/clk/ralink/Kconfig
  86 +++ b/drivers/clk/ralink/Kconfig
  87 @@ -9,3 +9,10 @@ config CLK_MT7621
  88         select MFD_SYSCON
  89         help
  90           This driver supports MediaTek MT7621 basic clocks.
  91 +
  92 +config CLK_MTMIPS
  93 +       bool "Clock driver for MTMIPS SoCs"
  94 +       depends on SOC_RT305X || SOC_RT288X || SOC_RT3883 || SOC_MT7620 || COMPILE_TEST
  95 +       select MFD_SYSCON
  96 +       help
  97 +         This driver supports MTMIPS basic clocks.
  98 --- a/drivers/clk/ralink/Makefile
  99 +++ b/drivers/clk/ralink/Makefile
 100 @@ -1,2 +1,3 @@
 101  # SPDX-License-Identifier: GPL-2.0
 102  obj-$(CONFIG_CLK_MT7621) += clk-mt7621.o
 103 +obj-$(CONFIG_CLK_MTMIPS) += clk-mtmips.o
 104 --- /dev/null
 105 +++ b/drivers/clk/ralink/clk-mtmips.c
 106 @@ -0,0 +1,1115 @@
 107 +// SPDX-License-Identifier: GPL-2.0
 108 +/*
 109 + * MTMIPS SoCs Clock Driver
 110 + * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
 111 + */
 112 +
 113 +#include <linux/bitops.h>
 114 +#include <linux/clk-provider.h>
 115 +#include <linux/mfd/syscon.h>
 116 +#include <linux/platform_device.h>
 117 +#include <linux/regmap.h>
 118 +#include <linux/reset-controller.h>
 119 +#include <linux/slab.h>
 120 +
 121 +/* Configuration registers */
 122 +#define SYSC_REG_SYSTEM_CONFIG         0x10
 123 +#define SYSC_REG_CLKCFG0               0x2c
 124 +#define SYSC_REG_RESET_CTRL            0x34
 125 +#define SYSC_REG_CPU_SYS_CLKCFG                0x3c
 126 +#define SYSC_REG_CPLL_CONFIG0          0x54
 127 +#define SYSC_REG_CPLL_CONFIG1          0x58
 128 +
 129 +/* RT2880 SoC */
 130 +#define RT2880_CONFIG_CPUCLK_SHIFT     20
 131 +#define RT2880_CONFIG_CPUCLK_MASK      0x3
 132 +#define RT2880_CONFIG_CPUCLK_250       0x0
 133 +#define RT2880_CONFIG_CPUCLK_266       0x1
 134 +#define RT2880_CONFIG_CPUCLK_280       0x2
 135 +#define RT2880_CONFIG_CPUCLK_300       0x3
 136 +
 137 +/* RT305X SoC */
 138 +#define RT305X_SYSCFG_CPUCLK_SHIFT     18
 139 +#define RT305X_SYSCFG_CPUCLK_MASK      0x1
 140 +#define RT305X_SYSCFG_CPUCLK_LOW       0x0
 141 +#define RT305X_SYSCFG_CPUCLK_HIGH      0x1
 142 +
 143 +/* RT3352 SoC */
 144 +#define RT3352_SYSCFG0_CPUCLK_SHIFT    8
 145 +#define RT3352_SYSCFG0_CPUCLK_MASK     0x1
 146 +#define RT3352_SYSCFG0_CPUCLK_LOW      0x0
 147 +#define RT3352_SYSCFG0_CPUCLK_HIGH     0x1
 148 +
 149 +/* RT3383 SoC */
 150 +#define RT3883_SYSCFG0_DRAM_TYPE_DDR2  BIT(17)
 151 +#define RT3883_SYSCFG0_CPUCLK_SHIFT    8
 152 +#define RT3883_SYSCFG0_CPUCLK_MASK     0x3
 153 +#define RT3883_SYSCFG0_CPUCLK_250      0x0
 154 +#define RT3883_SYSCFG0_CPUCLK_384      0x1
 155 +#define RT3883_SYSCFG0_CPUCLK_480      0x2
 156 +#define RT3883_SYSCFG0_CPUCLK_500      0x3
 157 +
 158 +/* RT5350 SoC */
 159 +#define RT5350_CLKCFG0_XTAL_SEL                BIT(20)
 160 +#define RT5350_SYSCFG0_CPUCLK_SHIFT    8
 161 +#define RT5350_SYSCFG0_CPUCLK_MASK     0x3
 162 +#define RT5350_SYSCFG0_CPUCLK_360      0x0
 163 +#define RT5350_SYSCFG0_CPUCLK_320      0x2
 164 +#define RT5350_SYSCFG0_CPUCLK_300      0x3
 165 +
 166 +/* MT7620 and MT76x8 SoCs */
 167 +#define MT7620_XTAL_FREQ_SEL           BIT(6)
 168 +#define CPLL_CFG0_SW_CFG               BIT(31)
 169 +#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
 170 +#define CPLL_CFG0_PLL_MULT_RATIO_MASK   0x7
 171 +#define CPLL_CFG0_LC_CURFCK            BIT(15)
 172 +#define CPLL_CFG0_BYPASS_REF_CLK       BIT(14)
 173 +#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT  10
 174 +#define CPLL_CFG0_PLL_DIV_RATIO_MASK   0x3
 175 +#define CPLL_CFG1_CPU_AUX1             BIT(25)
 176 +#define CPLL_CFG1_CPU_AUX0             BIT(24)
 177 +#define CLKCFG0_PERI_CLK_SEL           BIT(4)
 178 +#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
 179 +#define CPU_SYS_CLKCFG_OCP_RATIO_MASK  0xf
 180 +#define CPU_SYS_CLKCFG_OCP_RATIO_1     0       /* 1:1   (Reserved) */
 181 +#define CPU_SYS_CLKCFG_OCP_RATIO_1_5   1       /* 1:1.5 (Reserved) */
 182 +#define CPU_SYS_CLKCFG_OCP_RATIO_2     2       /* 1:2   */
 183 +#define CPU_SYS_CLKCFG_OCP_RATIO_2_5   3       /* 1:2.5 (Reserved) */
 184 +#define CPU_SYS_CLKCFG_OCP_RATIO_3     4       /* 1:3   */
 185 +#define CPU_SYS_CLKCFG_OCP_RATIO_3_5   5       /* 1:3.5 (Reserved) */
 186 +#define CPU_SYS_CLKCFG_OCP_RATIO_4     6       /* 1:4   */
 187 +#define CPU_SYS_CLKCFG_OCP_RATIO_5     7       /* 1:5   */
 188 +#define CPU_SYS_CLKCFG_OCP_RATIO_10    8       /* 1:10  */
 189 +#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT  8
 190 +#define CPU_SYS_CLKCFG_CPU_FDIV_MASK   0x1f
 191 +#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
 192 +#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK  0x1f
 193 +
 194 +/* clock scaling */
 195 +#define CLKCFG_FDIV_MASK               0x1f00
 196 +#define CLKCFG_FDIV_USB_VAL            0x0300
 197 +#define CLKCFG_FFRAC_MASK              0x001f
 198 +#define CLKCFG_FFRAC_USB_VAL           0x0003
 199 +
 200 +struct mtmips_clk;
 201 +struct mtmips_clk_fixed;
 202 +struct mtmips_clk_factor;
 203 +
 204 +struct mtmips_clk_data {
 205 +       struct mtmips_clk *clk_base;
 206 +       size_t num_clk_base;
 207 +       struct mtmips_clk_fixed *clk_fixed;
 208 +       size_t num_clk_fixed;
 209 +       struct mtmips_clk_factor *clk_factor;
 210 +       size_t num_clk_factor;
 211 +       struct mtmips_clk *clk_periph;
 212 +       size_t num_clk_periph;
 213 +};
 214 +
 215 +struct mtmips_clk_priv {
 216 +       struct regmap *sysc;
 217 +       const struct mtmips_clk_data *data;
 218 +};
 219 +
 220 +struct mtmips_clk {
 221 +       struct clk_hw hw;
 222 +       struct mtmips_clk_priv *priv;
 223 +};
 224 +
 225 +struct mtmips_clk_fixed {
 226 +       const char *name;
 227 +       const char *parent;
 228 +       unsigned long rate;
 229 +       struct clk_hw *hw;
 230 +};
 231 +
 232 +struct mtmips_clk_factor {
 233 +       const char *name;
 234 +       const char *parent;
 235 +       int mult;
 236 +       int div;
 237 +       unsigned long flags;
 238 +       struct clk_hw *hw;
 239 +};
 240 +
 241 +static unsigned long mtmips_pherip_clk_rate(struct clk_hw *hw,
 242 +                                           unsigned long parent_rate)
 243 +{
 244 +       return parent_rate;
 245 +}
 246 +
 247 +static const struct clk_ops mtmips_periph_clk_ops = {
 248 +       .recalc_rate = mtmips_pherip_clk_rate,
 249 +};
 250 +
 251 +#define CLK_PERIPH(_name, _parent) {                           \
 252 +       .init = &(const struct clk_init_data) {                 \
 253 +               .name = _name,                                  \
 254 +               .ops = &mtmips_periph_clk_ops,                  \
 255 +               .parent_data = &(const struct clk_parent_data) {\
 256 +                       .name = _parent,                        \
 257 +                       .fw_name = _parent                      \
 258 +               },                                              \
 259 +               .num_parents = 1,                               \
 260 +               /*                                              \
 261 +                * There are drivers for these SoCs that are    \
 262 +                * older than clock driver and are not prepared \
 263 +                * for the clock. We don't want the kernel to   \
 264 +                * disable anything so we add CLK_IS_CRITICAL   \
 265 +                * flag here.                                   \
 266 +                */                                             \
 267 +               .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL  \
 268 +       },                                                      \
 269 +}
 270 +
 271 +static struct mtmips_clk rt2880_pherip_clks[] = {
 272 +       { CLK_PERIPH("300100.timer", "bus") },
 273 +       { CLK_PERIPH("300120.watchdog", "bus") },
 274 +       { CLK_PERIPH("300500.uart", "bus") },
 275 +       { CLK_PERIPH("300900.i2c", "bus") },
 276 +       { CLK_PERIPH("300c00.uartlite", "bus") },
 277 +       { CLK_PERIPH("400000.ethernet", "bus") },
 278 +       { CLK_PERIPH("480000.wmac", "xtal") }
 279 +};
 280 +
 281 +static struct mtmips_clk rt305x_pherip_clks[] = {
 282 +       { CLK_PERIPH("10000100.timer", "bus") },
 283 +       { CLK_PERIPH("10000120.watchdog", "bus") },
 284 +       { CLK_PERIPH("10000500.uart", "bus") },
 285 +       { CLK_PERIPH("10000900.i2c", "bus") },
 286 +       { CLK_PERIPH("10000a00.i2s", "bus") },
 287 +       { CLK_PERIPH("10000b00.spi", "bus") },
 288 +       { CLK_PERIPH("10000b40.spi", "bus") },
 289 +       { CLK_PERIPH("10000c00.uartlite", "bus") },
 290 +       { CLK_PERIPH("10100000.ethernet", "bus") },
 291 +       { CLK_PERIPH("10180000.wmac", "xtal") }
 292 +};
 293 +
 294 +static struct mtmips_clk rt5350_pherip_clks[] = {
 295 +       { CLK_PERIPH("10000100.timer", "bus") },
 296 +       { CLK_PERIPH("10000120.watchdog", "bus") },
 297 +       { CLK_PERIPH("10000500.uart", "periph") },
 298 +       { CLK_PERIPH("10000900.i2c", "periph") },
 299 +       { CLK_PERIPH("10000a00.i2s", "periph") },
 300 +       { CLK_PERIPH("10000b00.spi", "bus") },
 301 +       { CLK_PERIPH("10000b40.spi", "bus") },
 302 +       { CLK_PERIPH("10000c00.uartlite", "periph") },
 303 +       { CLK_PERIPH("10100000.ethernet", "bus") },
 304 +       { CLK_PERIPH("10180000.wmac", "xtal") }
 305 +};
 306 +
 307 +static struct mtmips_clk mt7620_pherip_clks[] = {
 308 +       { CLK_PERIPH("10000100.timer", "periph") },
 309 +       { CLK_PERIPH("10000120.watchdog", "periph") },
 310 +       { CLK_PERIPH("10000500.uart", "periph") },
 311 +       { CLK_PERIPH("10000900.i2c", "periph") },
 312 +       { CLK_PERIPH("10000a00.i2s", "periph") },
 313 +       { CLK_PERIPH("10000b00.spi", "bus") },
 314 +       { CLK_PERIPH("10000b40.spi", "bus") },
 315 +       { CLK_PERIPH("10000c00.uartlite", "periph") },
 316 +       { CLK_PERIPH("10180000.wmac", "xtal") }
 317 +};
 318 +
 319 +static struct mtmips_clk mt76x8_pherip_clks[] = {
 320 +       { CLK_PERIPH("10000100.timer", "periph") },
 321 +       { CLK_PERIPH("10000120.watchdog", "periph") },
 322 +       { CLK_PERIPH("10000900.i2c", "periph") },
 323 +       { CLK_PERIPH("10000a00.i2s", "pcmi2s") },
 324 +       { CLK_PERIPH("10000b00.spi", "bus") },
 325 +       { CLK_PERIPH("10000b40.spi", "bus") },
 326 +       { CLK_PERIPH("10000c00.uart0", "periph") },
 327 +       { CLK_PERIPH("10000d00.uart1", "periph") },
 328 +       { CLK_PERIPH("10000e00.uart2", "periph") },
 329 +       { CLK_PERIPH("10300000.wmac", "xtal") }
 330 +};
 331 +
 332 +static int mtmips_register_pherip_clocks(struct device_node *np,
 333 +                                        struct clk_hw_onecell_data *clk_data,
 334 +                                        struct mtmips_clk_priv *priv)
 335 +{
 336 +       struct clk_hw **hws = clk_data->hws;
 337 +       struct mtmips_clk *sclk;
 338 +       size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed +
 339 +                          priv->data->num_clk_factor;
 340 +       int ret, i;
 341 +
 342 +       for (i = 0; i < priv->data->num_clk_periph; i++) {
 343 +               int idx = idx_start + i;
 344 +
 345 +               sclk = &priv->data->clk_periph[i];
 346 +               ret = of_clk_hw_register(np, &sclk->hw);
 347 +               if (ret) {
 348 +                       pr_err("Couldn't register peripheral clock %d\n", idx);
 349 +                       goto err_clk_unreg;
 350 +               }
 351 +
 352 +               hws[idx] = &sclk->hw;
 353 +       }
 354 +
 355 +       return 0;
 356 +
 357 +err_clk_unreg:
 358 +       while (--i >= 0) {
 359 +               sclk = &priv->data->clk_periph[i];
 360 +               clk_hw_unregister(&sclk->hw);
 361 +       }
 362 +       return ret;
 363 +}
 364 +
 365 +#define CLK_FIXED(_name, _parent, _rate) \
 366 +       {                                \
 367 +               .name = _name,           \
 368 +               .parent = _parent,       \
 369 +               .rate = _rate            \
 370 +       }
 371 +
 372 +static struct mtmips_clk_fixed rt305x_fixed_clocks[] = {
 373 +       CLK_FIXED("xtal", NULL, 40000000)
 374 +};
 375 +
 376 +static struct mtmips_clk_fixed rt3352_fixed_clocks[] = {
 377 +       CLK_FIXED("periph", "xtal", 40000000)
 378 +};
 379 +
 380 +static struct mtmips_clk_fixed mt76x8_fixed_clocks[] = {
 381 +       CLK_FIXED("pcmi2s", "xtal", 480000000),
 382 +       CLK_FIXED("periph", "xtal", 40000000)
 383 +};
 384 +
 385 +static int mtmips_register_fixed_clocks(struct clk_hw_onecell_data *clk_data,
 386 +                                       struct mtmips_clk_priv *priv)
 387 +{
 388 +       struct clk_hw **hws = clk_data->hws;
 389 +       struct mtmips_clk_fixed *sclk;
 390 +       size_t idx_start = priv->data->num_clk_base;
 391 +       int ret, i;
 392 +
 393 +       for (i = 0; i < priv->data->num_clk_fixed; i++) {
 394 +               int idx = idx_start + i;
 395 +
 396 +               sclk = &priv->data->clk_fixed[i];
 397 +               sclk->hw = clk_hw_register_fixed_rate(NULL, sclk->name,
 398 +                                                     sclk->parent, 0,
 399 +                                                     sclk->rate);
 400 +               if (IS_ERR(sclk->hw)) {
 401 +                       pr_err("Couldn't register fixed clock %d\n", idx);
 402 +                       goto err_clk_unreg;
 403 +               }
 404 +
 405 +               hws[idx] = sclk->hw;
 406 +       }
 407 +
 408 +       return 0;
 409 +
 410 +err_clk_unreg:
 411 +       while (--i >= 0) {
 412 +               sclk = &priv->data->clk_fixed[i];
 413 +               clk_hw_unregister_fixed_rate(sclk->hw);
 414 +       }
 415 +       return ret;
 416 +}
 417 +
 418 +#define CLK_FACTOR(_name, _parent, _mult, _div)                \
 419 +       {                                               \
 420 +               .name = _name,                          \
 421 +               .parent = _parent,                      \
 422 +               .mult = _mult,                          \
 423 +               .div = _div,                            \
 424 +               .flags = CLK_SET_RATE_PARENT            \
 425 +       }
 426 +
 427 +static struct mtmips_clk_factor rt2880_factor_clocks[] = {
 428 +       CLK_FACTOR("bus", "cpu", 1, 2)
 429 +};
 430 +
 431 +static struct mtmips_clk_factor rt305x_factor_clocks[] = {
 432 +       CLK_FACTOR("bus", "cpu", 1, 3)
 433 +};
 434 +
 435 +static int mtmips_register_factor_clocks(struct clk_hw_onecell_data *clk_data,
 436 +                                        struct mtmips_clk_priv *priv)
 437 +{
 438 +       struct clk_hw **hws = clk_data->hws;
 439 +       struct mtmips_clk_factor *sclk;
 440 +       size_t idx_start = priv->data->num_clk_base + priv->data->num_clk_fixed;
 441 +       int ret, i;
 442 +
 443 +       for (i = 0; i < priv->data->num_clk_factor; i++) {
 444 +               int idx = idx_start + i;
 445 +
 446 +               sclk = &priv->data->clk_factor[i];
 447 +               sclk->hw = clk_hw_register_fixed_factor(NULL, sclk->name,
 448 +                                                 sclk->parent, sclk->flags,
 449 +                                                 sclk->mult, sclk->div);
 450 +               if (IS_ERR(sclk->hw)) {
 451 +                       pr_err("Couldn't register factor clock %d\n", idx);
 452 +                       goto err_clk_unreg;
 453 +               }
 454 +
 455 +               hws[idx] = sclk->hw;
 456 +       }
 457 +
 458 +       return 0;
 459 +
 460 +err_clk_unreg:
 461 +       while (--i >= 0) {
 462 +               sclk = &priv->data->clk_factor[i];
 463 +               clk_hw_unregister_fixed_factor(sclk->hw);
 464 +       }
 465 +       return ret;
 466 +}
 467 +
 468 +static inline struct mtmips_clk *to_mtmips_clk(struct clk_hw *hw)
 469 +{
 470 +       return container_of(hw, struct mtmips_clk, hw);
 471 +}
 472 +
 473 +static unsigned long rt5350_xtal_recalc_rate(struct clk_hw *hw,
 474 +                                            unsigned long parent_rate)
 475 +{
 476 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 477 +       struct regmap *sysc = clk->priv->sysc;
 478 +       u32 val;
 479 +
 480 +       regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &val);
 481 +       if (!(val & RT5350_CLKCFG0_XTAL_SEL))
 482 +               return 20000000;
 483 +
 484 +       return 40000000;
 485 +}
 486 +
 487 +static unsigned long rt5350_cpu_recalc_rate(struct clk_hw *hw,
 488 +                                           unsigned long xtal_clk)
 489 +{
 490 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 491 +       struct regmap *sysc = clk->priv->sysc;
 492 +       u32 t;
 493 +
 494 +       regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
 495 +       t = (t >> RT5350_SYSCFG0_CPUCLK_SHIFT) & RT5350_SYSCFG0_CPUCLK_MASK;
 496 +
 497 +       switch (t) {
 498 +       case RT5350_SYSCFG0_CPUCLK_360:
 499 +               return 360000000;
 500 +       case RT5350_SYSCFG0_CPUCLK_320:
 501 +               return 320000000;
 502 +       case RT5350_SYSCFG0_CPUCLK_300:
 503 +               return 300000000;
 504 +       default:
 505 +               BUG();
 506 +       }
 507 +}
 508 +
 509 +static unsigned long rt5350_bus_recalc_rate(struct clk_hw *hw,
 510 +                                           unsigned long parent_rate)
 511 +{
 512 +       if (parent_rate == 320000000)
 513 +               return parent_rate / 4;
 514 +
 515 +       return parent_rate / 3;
 516 +}
 517 +
 518 +static unsigned long rt3352_cpu_recalc_rate(struct clk_hw *hw,
 519 +                                           unsigned long xtal_clk)
 520 +{
 521 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 522 +       struct regmap *sysc = clk->priv->sysc;
 523 +       u32 t;
 524 +
 525 +       regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
 526 +       t = (t >> RT3352_SYSCFG0_CPUCLK_SHIFT) & RT3352_SYSCFG0_CPUCLK_MASK;
 527 +
 528 +       switch (t) {
 529 +       case RT3352_SYSCFG0_CPUCLK_LOW:
 530 +               return 384000000;
 531 +       case RT3352_SYSCFG0_CPUCLK_HIGH:
 532 +               return 400000000;
 533 +       default:
 534 +               BUG();
 535 +       }
 536 +}
 537 +
 538 +static unsigned long rt305x_cpu_recalc_rate(struct clk_hw *hw,
 539 +                                           unsigned long xtal_clk)
 540 +{
 541 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 542 +       struct regmap *sysc = clk->priv->sysc;
 543 +       u32 t;
 544 +
 545 +       regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
 546 +       t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK;
 547 +
 548 +       switch (t) {
 549 +       case RT305X_SYSCFG_CPUCLK_LOW:
 550 +               return 320000000;
 551 +       case RT305X_SYSCFG_CPUCLK_HIGH:
 552 +               return 384000000;
 553 +       default:
 554 +               BUG();
 555 +       }
 556 +}
 557 +
 558 +static unsigned long rt3883_cpu_recalc_rate(struct clk_hw *hw,
 559 +                                           unsigned long xtal_clk)
 560 +{
 561 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 562 +       struct regmap *sysc = clk->priv->sysc;
 563 +       u32 t;
 564 +
 565 +       regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
 566 +       t = (t >> RT3883_SYSCFG0_CPUCLK_SHIFT) & RT3883_SYSCFG0_CPUCLK_MASK;
 567 +
 568 +       switch (t) {
 569 +       case RT3883_SYSCFG0_CPUCLK_250:
 570 +               return 250000000;
 571 +       case RT3883_SYSCFG0_CPUCLK_384:
 572 +               return 384000000;
 573 +       case RT3883_SYSCFG0_CPUCLK_480:
 574 +               return 480000000;
 575 +       case RT3883_SYSCFG0_CPUCLK_500:
 576 +               return 500000000;
 577 +       default:
 578 +               BUG();
 579 +       }
 580 +}
 581 +
 582 +static unsigned long rt3883_bus_recalc_rate(struct clk_hw *hw,
 583 +                                           unsigned long parent_rate)
 584 +{
 585 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 586 +       struct regmap *sysc = clk->priv->sysc;
 587 +       u32 ddr2;
 588 +       u32 t;
 589 +
 590 +       regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
 591 +       ddr2 = t & RT3883_SYSCFG0_DRAM_TYPE_DDR2;
 592 +
 593 +       switch (parent_rate) {
 594 +       case 250000000:
 595 +               return (ddr2) ? 125000000 : 83000000;
 596 +       case 384000000:
 597 +               return (ddr2) ? 128000000 : 96000000;
 598 +       case 480000000:
 599 +               return (ddr2) ? 160000000 : 120000000;
 600 +       case 500000000:
 601 +               return (ddr2) ? 166000000 : 125000000;
 602 +       default:
 603 +               WARN_ON_ONCE(parent_rate == 0);
 604 +               return parent_rate / 4;
 605 +       }
 606 +}
 607 +
 608 +static unsigned long rt2880_cpu_recalc_rate(struct clk_hw *hw,
 609 +                                           unsigned long xtal_clk)
 610 +{
 611 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 612 +       struct regmap *sysc = clk->priv->sysc;
 613 +       u32 t;
 614 +
 615 +       regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
 616 +       t = (t >> RT2880_CONFIG_CPUCLK_SHIFT) & RT2880_CONFIG_CPUCLK_MASK;
 617 +
 618 +       switch (t) {
 619 +       case RT2880_CONFIG_CPUCLK_250:
 620 +               return 250000000;
 621 +       case RT2880_CONFIG_CPUCLK_266:
 622 +               return 266000000;
 623 +       case RT2880_CONFIG_CPUCLK_280:
 624 +               return 280000000;
 625 +       case RT2880_CONFIG_CPUCLK_300:
 626 +               return 300000000;
 627 +       default:
 628 +               BUG();
 629 +       }
 630 +}
 631 +
 632 +static u32 mt7620_calc_rate(u32 ref_rate, u32 mul, u32 div)
 633 +{
 634 +       u64 t;
 635 +
 636 +       t = ref_rate;
 637 +       t *= mul;
 638 +       t = div_u64(t, div);
 639 +
 640 +       return t;
 641 +}
 642 +
 643 +static unsigned long mt7620_pll_recalc_rate(struct clk_hw *hw,
 644 +                                           unsigned long parent_rate)
 645 +{
 646 +       static const u32 clk_divider[] = { 2, 3, 4, 8 };
 647 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 648 +       struct regmap *sysc = clk->priv->sysc;
 649 +       unsigned long cpu_pll;
 650 +       u32 t;
 651 +       u32 mul;
 652 +       u32 div;
 653 +
 654 +       regmap_read(sysc, SYSC_REG_CPLL_CONFIG0, &t);
 655 +       if (t & CPLL_CFG0_BYPASS_REF_CLK) {
 656 +               cpu_pll = parent_rate;
 657 +       } else if ((t & CPLL_CFG0_SW_CFG) == 0) {
 658 +               cpu_pll = 600000000;
 659 +       } else {
 660 +               mul = (t >> CPLL_CFG0_PLL_MULT_RATIO_SHIFT) &
 661 +                       CPLL_CFG0_PLL_MULT_RATIO_MASK;
 662 +               mul += 24;
 663 +               if (t & CPLL_CFG0_LC_CURFCK)
 664 +                       mul *= 2;
 665 +
 666 +               div = (t >> CPLL_CFG0_PLL_DIV_RATIO_SHIFT) &
 667 +                       CPLL_CFG0_PLL_DIV_RATIO_MASK;
 668 +
 669 +               WARN_ON_ONCE(div >= ARRAY_SIZE(clk_divider));
 670 +
 671 +               cpu_pll = mt7620_calc_rate(parent_rate, mul, clk_divider[div]);
 672 +       }
 673 +
 674 +       regmap_read(sysc, SYSC_REG_CPLL_CONFIG1, &t);
 675 +       if (t & CPLL_CFG1_CPU_AUX1)
 676 +               return parent_rate;
 677 +
 678 +       if (t & CPLL_CFG1_CPU_AUX0)
 679 +               return 480000000;
 680 +
 681 +       return cpu_pll;
 682 +}
 683 +
 684 +static unsigned long mt7620_cpu_recalc_rate(struct clk_hw *hw,
 685 +                                           unsigned long parent_rate)
 686 +{
 687 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 688 +       struct regmap *sysc = clk->priv->sysc;
 689 +       u32 t;
 690 +       u32 mul;
 691 +       u32 div;
 692 +
 693 +       regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
 694 +       mul = t & CPU_SYS_CLKCFG_CPU_FFRAC_MASK;
 695 +       div = (t >> CPU_SYS_CLKCFG_CPU_FDIV_SHIFT) &
 696 +               CPU_SYS_CLKCFG_CPU_FDIV_MASK;
 697 +
 698 +       return mt7620_calc_rate(parent_rate, mul, div);
 699 +}
 700 +
 701 +static unsigned long mt7620_bus_recalc_rate(struct clk_hw *hw,
 702 +                                           unsigned long parent_rate)
 703 +{
 704 +       static const u32 ocp_dividers[16] = {
 705 +               [CPU_SYS_CLKCFG_OCP_RATIO_2] = 2,
 706 +               [CPU_SYS_CLKCFG_OCP_RATIO_3] = 3,
 707 +               [CPU_SYS_CLKCFG_OCP_RATIO_4] = 4,
 708 +               [CPU_SYS_CLKCFG_OCP_RATIO_5] = 5,
 709 +               [CPU_SYS_CLKCFG_OCP_RATIO_10] = 10,
 710 +       };
 711 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 712 +       struct regmap *sysc = clk->priv->sysc;
 713 +       u32 t;
 714 +       u32 ocp_ratio;
 715 +       u32 div;
 716 +
 717 +       regmap_read(sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
 718 +       ocp_ratio = (t >> CPU_SYS_CLKCFG_OCP_RATIO_SHIFT) &
 719 +               CPU_SYS_CLKCFG_OCP_RATIO_MASK;
 720 +
 721 +       if (WARN_ON_ONCE(ocp_ratio >= ARRAY_SIZE(ocp_dividers)))
 722 +               return parent_rate;
 723 +
 724 +       div = ocp_dividers[ocp_ratio];
 725 +
 726 +       if (WARN(!div, "invalid divider for OCP ratio %u", ocp_ratio))
 727 +               return parent_rate;
 728 +
 729 +       return parent_rate / div;
 730 +}
 731 +
 732 +static unsigned long mt7620_periph_recalc_rate(struct clk_hw *hw,
 733 +                                              unsigned long parent_rate)
 734 +{
 735 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 736 +       struct regmap *sysc = clk->priv->sysc;
 737 +       u32 t;
 738 +
 739 +       regmap_read(sysc, SYSC_REG_CLKCFG0, &t);
 740 +       if (t & CLKCFG0_PERI_CLK_SEL)
 741 +               return parent_rate;
 742 +
 743 +       return 40000000;
 744 +}
 745 +
 746 +static unsigned long mt76x8_xtal_recalc_rate(struct clk_hw *hw,
 747 +                                            unsigned long parent_rate)
 748 +{
 749 +       struct mtmips_clk *clk = to_mtmips_clk(hw);
 750 +       struct regmap *sysc = clk->priv->sysc;
 751 +       u32 t;
 752 +
 753 +       regmap_read(sysc, SYSC_REG_SYSTEM_CONFIG, &t);
 754 +       if (t & MT7620_XTAL_FREQ_SEL)
 755 +               return 40000000;
 756 +
 757 +       return 20000000;
 758 +}
 759 +
 760 +static unsigned long mt76x8_cpu_recalc_rate(struct clk_hw *hw,
 761 +                                           unsigned long xtal_clk)
 762 +{
 763 +       if (xtal_clk == 40000000)
 764 +               return 580000000;
 765 +
 766 +       return 575000000;
 767 +}
 768 +
 769 +#define CLK_BASE(_name, _parent, _recalc) {                            \
 770 +       .init = &(const struct clk_init_data) {                         \
 771 +               .name = _name,                                          \
 772 +               .ops = &(const struct clk_ops) {                        \
 773 +                       .recalc_rate = _recalc,                         \
 774 +               },                                                      \
 775 +               .parent_data = &(const struct clk_parent_data) {        \
 776 +                       .name = _parent,                                \
 777 +                       .fw_name = _parent                              \
 778 +               },                                                      \
 779 +               .num_parents = _parent ? 1 : 0                          \
 780 +       },                                                              \
 781 +}
 782 +
 783 +static struct mtmips_clk rt2880_clks_base[] = {
 784 +       { CLK_BASE("cpu", "xtal", rt2880_cpu_recalc_rate) }
 785 +};
 786 +
 787 +static struct mtmips_clk rt305x_clks_base[] = {
 788 +       { CLK_BASE("cpu", "xtal", rt305x_cpu_recalc_rate) }
 789 +};
 790 +
 791 +static struct mtmips_clk rt3352_clks_base[] = {
 792 +       { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
 793 +       { CLK_BASE("cpu", "xtal", rt3352_cpu_recalc_rate) }
 794 +};
 795 +
 796 +static struct mtmips_clk rt3883_clks_base[] = {
 797 +       { CLK_BASE("cpu", "xtal", rt3883_cpu_recalc_rate) },
 798 +       { CLK_BASE("bus", "cpu", rt3883_bus_recalc_rate) }
 799 +};
 800 +
 801 +static struct mtmips_clk rt5350_clks_base[] = {
 802 +       { CLK_BASE("xtal", NULL, rt5350_xtal_recalc_rate) },
 803 +       { CLK_BASE("cpu", "xtal", rt5350_cpu_recalc_rate) },
 804 +       { CLK_BASE("bus", "cpu", rt5350_bus_recalc_rate) }
 805 +};
 806 +
 807 +static struct mtmips_clk mt7620_clks_base[] = {
 808 +       { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
 809 +       { CLK_BASE("pll", "xtal", mt7620_pll_recalc_rate) },
 810 +       { CLK_BASE("cpu", "pll", mt7620_cpu_recalc_rate) },
 811 +       { CLK_BASE("periph", "xtal", mt7620_periph_recalc_rate) },
 812 +       { CLK_BASE("bus", "cpu", mt7620_bus_recalc_rate) }
 813 +};
 814 +
 815 +static struct mtmips_clk mt76x8_clks_base[] = {
 816 +       { CLK_BASE("xtal", NULL, mt76x8_xtal_recalc_rate) },
 817 +       { CLK_BASE("cpu", "xtal", mt76x8_cpu_recalc_rate) }
 818 +};
 819 +
 820 +static int mtmips_register_clocks(struct device_node *np,
 821 +                                 struct clk_hw_onecell_data *clk_data,
 822 +                                 struct mtmips_clk_priv *priv)
 823 +{
 824 +       struct clk_hw **hws = clk_data->hws;
 825 +       struct mtmips_clk *sclk;
 826 +       int ret, i;
 827 +
 828 +       for (i = 0; i < priv->data->num_clk_base; i++) {
 829 +               sclk = &priv->data->clk_base[i];
 830 +               sclk->priv = priv;
 831 +               ret = of_clk_hw_register(np, &sclk->hw);
 832 +               if (ret) {
 833 +                       pr_err("Couldn't register top clock %i\n", i);
 834 +                       goto err_clk_unreg;
 835 +               }
 836 +
 837 +               hws[i] = &sclk->hw;
 838 +       }
 839 +
 840 +       return 0;
 841 +
 842 +err_clk_unreg:
 843 +       while (--i >= 0) {
 844 +               sclk = &priv->data->clk_base[i];
 845 +               clk_hw_unregister(&sclk->hw);
 846 +       }
 847 +       return ret;
 848 +}
 849 +
 850 +static const struct mtmips_clk_data rt2880_clk_data = {
 851 +       .clk_base = rt2880_clks_base,
 852 +       .num_clk_base = ARRAY_SIZE(rt2880_clks_base),
 853 +       .clk_fixed = rt305x_fixed_clocks,
 854 +       .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
 855 +       .clk_factor = rt2880_factor_clocks,
 856 +       .num_clk_factor = ARRAY_SIZE(rt2880_factor_clocks),
 857 +       .clk_periph = rt2880_pherip_clks,
 858 +       .num_clk_periph = ARRAY_SIZE(rt2880_pherip_clks),
 859 +};
 860 +
 861 +static const struct mtmips_clk_data rt305x_clk_data = {
 862 +       .clk_base = rt305x_clks_base,
 863 +       .num_clk_base = ARRAY_SIZE(rt305x_clks_base),
 864 +       .clk_fixed = rt305x_fixed_clocks,
 865 +       .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
 866 +       .clk_factor = rt305x_factor_clocks,
 867 +       .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
 868 +       .clk_periph = rt305x_pherip_clks,
 869 +       .num_clk_periph = ARRAY_SIZE(rt305x_pherip_clks),
 870 +};
 871 +
 872 +static const struct mtmips_clk_data rt3352_clk_data = {
 873 +       .clk_base = rt3352_clks_base,
 874 +       .num_clk_base = ARRAY_SIZE(rt3352_clks_base),
 875 +       .clk_fixed = rt3352_fixed_clocks,
 876 +       .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
 877 +       .clk_factor = rt305x_factor_clocks,
 878 +       .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
 879 +       .clk_periph = rt5350_pherip_clks,
 880 +       .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
 881 +};
 882 +
 883 +static const struct mtmips_clk_data rt3883_clk_data = {
 884 +       .clk_base = rt3883_clks_base,
 885 +       .num_clk_base = ARRAY_SIZE(rt3883_clks_base),
 886 +       .clk_fixed = rt305x_fixed_clocks,
 887 +       .num_clk_fixed = ARRAY_SIZE(rt305x_fixed_clocks),
 888 +       .clk_factor = NULL,
 889 +       .num_clk_factor = 0,
 890 +       .clk_periph = rt5350_pherip_clks,
 891 +       .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
 892 +};
 893 +
 894 +static const struct mtmips_clk_data rt5350_clk_data = {
 895 +       .clk_base = rt5350_clks_base,
 896 +       .num_clk_base = ARRAY_SIZE(rt5350_clks_base),
 897 +       .clk_fixed = rt3352_fixed_clocks,
 898 +       .num_clk_fixed = ARRAY_SIZE(rt3352_fixed_clocks),
 899 +       .clk_factor = NULL,
 900 +       .num_clk_factor = 0,
 901 +       .clk_periph = rt5350_pherip_clks,
 902 +       .num_clk_periph = ARRAY_SIZE(rt5350_pherip_clks),
 903 +};
 904 +
 905 +static const struct mtmips_clk_data mt7620_clk_data = {
 906 +       .clk_base = mt7620_clks_base,
 907 +       .num_clk_base = ARRAY_SIZE(mt7620_clks_base),
 908 +       .clk_fixed = NULL,
 909 +       .num_clk_fixed = 0,
 910 +       .clk_factor = NULL,
 911 +       .num_clk_factor = 0,
 912 +       .clk_periph = mt7620_pherip_clks,
 913 +       .num_clk_periph = ARRAY_SIZE(mt7620_pherip_clks),
 914 +};
 915 +
 916 +static const struct mtmips_clk_data mt76x8_clk_data = {
 917 +       .clk_base = mt76x8_clks_base,
 918 +       .num_clk_base = ARRAY_SIZE(mt76x8_clks_base),
 919 +       .clk_fixed = mt76x8_fixed_clocks,
 920 +       .num_clk_fixed = ARRAY_SIZE(mt76x8_fixed_clocks),
 921 +       .clk_factor = rt305x_factor_clocks,
 922 +       .num_clk_factor = ARRAY_SIZE(rt305x_factor_clocks),
 923 +       .clk_periph = mt76x8_pherip_clks,
 924 +       .num_clk_periph = ARRAY_SIZE(mt76x8_pherip_clks),
 925 +};
 926 +
 927 +static const struct of_device_id mtmips_of_match[] = {
 928 +       {
 929 +               .compatible = "ralink,rt2880-sysc",
 930 +               .data = &rt2880_clk_data,
 931 +       },
 932 +       {
 933 +               .compatible = "ralink,rt3050-sysc",
 934 +               .data = &rt305x_clk_data,
 935 +       },
 936 +       {
 937 +               .compatible = "ralink,rt3052-sysc",
 938 +               .data = &rt305x_clk_data,
 939 +       },
 940 +       {
 941 +               .compatible = "ralink,rt3352-sysc",
 942 +               .data = &rt3352_clk_data,
 943 +       },
 944 +       {
 945 +               .compatible = "ralink,rt3883-sysc",
 946 +               .data = &rt3883_clk_data,
 947 +       },
 948 +       {
 949 +               .compatible = "ralink,rt5350-sysc",
 950 +               .data = &rt5350_clk_data,
 951 +       },
 952 +       {
 953 +               .compatible = "ralink,mt7620-sysc",
 954 +               .data = &mt7620_clk_data,
 955 +       },
 956 +       {
 957 +               .compatible = "ralink,mt7628-sysc",
 958 +               .data = &mt76x8_clk_data,
 959 +       },
 960 +       {
 961 +               .compatible = "ralink,mt7688-sysc",
 962 +               .data = &mt76x8_clk_data,
 963 +       },
 964 +       {}
 965 +};
 966 +
 967 +static void __init mtmips_clk_regs_init(struct device_node *node,
 968 +                                       struct mtmips_clk_priv *priv)
 969 +{
 970 +       u32 t;
 971 +
 972 +       if (!of_device_is_compatible(node, "ralink,mt7620-sysc"))
 973 +               return;
 974 +
 975 +       /*
 976 +        * When the CPU goes into sleep mode, the BUS
 977 +        * clock will be too low for USB to function properly.
 978 +        * Adjust the busses fractional divider to fix this
 979 +        */
 980 +       regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
 981 +       t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
 982 +       t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
 983 +       regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t);
 984 +}
 985 +
 986 +static void __init mtmips_clk_init(struct device_node *node)
 987 +{
 988 +       const struct of_device_id *match;
 989 +       const struct mtmips_clk_data *data;
 990 +       struct mtmips_clk_priv *priv;
 991 +       struct clk_hw_onecell_data *clk_data;
 992 +       int ret, i, count;
 993 +
 994 +       priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 995 +       if (!priv)
 996 +               return;
 997 +
 998 +       priv->sysc = syscon_node_to_regmap(node);
 999 +       if (IS_ERR(priv->sysc)) {
1000 +               pr_err("Could not get sysc syscon regmap\n");
1001 +               goto free_clk_priv;
1002 +       }
1003 +
1004 +       mtmips_clk_regs_init(node, priv);
1005 +
1006 +       match = of_match_node(mtmips_of_match, node);
1007 +       if (WARN_ON(!match))
1008 +               return;
1009 +
1010 +       data = match->data;
1011 +       priv->data = data;
1012 +       count = priv->data->num_clk_base + priv->data->num_clk_fixed +
1013 +               priv->data->num_clk_factor + priv->data->num_clk_periph;
1014 +       clk_data = kzalloc(struct_size(clk_data, hws, count), GFP_KERNEL);
1015 +       if (!clk_data)
1016 +               goto free_clk_priv;
1017 +
1018 +       ret = mtmips_register_clocks(node, clk_data, priv);
1019 +       if (ret) {
1020 +               pr_err("Couldn't register top clocks\n");
1021 +               goto free_clk_data;
1022 +       }
1023 +
1024 +       ret = mtmips_register_fixed_clocks(clk_data, priv);
1025 +       if (ret) {
1026 +               pr_err("Couldn't register fixed clocks\n");
1027 +               goto unreg_clk_top;
1028 +       }
1029 +
1030 +       ret = mtmips_register_factor_clocks(clk_data, priv);
1031 +       if (ret) {
1032 +               pr_err("Couldn't register factor clocks\n");
1033 +               goto unreg_clk_fixed;
1034 +       }
1035 +
1036 +       ret = mtmips_register_pherip_clocks(node, clk_data, priv);
1037 +       if (ret) {
1038 +               pr_err("Couldn't register peripheral clocks\n");
1039 +               goto unreg_clk_factor;
1040 +       }
1041 +
1042 +       clk_data->num = count;
1043 +
1044 +       ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1045 +       if (ret) {
1046 +               pr_err("Couldn't add clk hw provider\n");
1047 +               goto unreg_clk_periph;
1048 +       }
1049 +
1050 +       return;
1051 +
1052 +unreg_clk_periph:
1053 +       for (i = 0; i < priv->data->num_clk_periph; i++) {
1054 +               struct mtmips_clk *sclk = &priv->data->clk_periph[i];
1055 +
1056 +               clk_hw_unregister(&sclk->hw);
1057 +       }
1058 +
1059 +unreg_clk_factor:
1060 +       for (i = 0; i < priv->data->num_clk_factor; i++) {
1061 +               struct mtmips_clk_factor *sclk = &priv->data->clk_factor[i];
1062 +
1063 +               clk_hw_unregister_fixed_factor(sclk->hw);
1064 +       }
1065 +
1066 +unreg_clk_fixed:
1067 +       for (i = 0; i < priv->data->num_clk_fixed; i++) {
1068 +               struct mtmips_clk_fixed *sclk = &priv->data->clk_fixed[i];
1069 +
1070 +               clk_hw_unregister_fixed_rate(sclk->hw);
1071 +       }
1072 +
1073 +unreg_clk_top:
1074 +       for (i = 0; i < priv->data->num_clk_base; i++) {
1075 +               struct mtmips_clk *sclk = &priv->data->clk_base[i];
1076 +
1077 +               clk_hw_unregister(&sclk->hw);
1078 +       }
1079 +
1080 +free_clk_data:
1081 +       kfree(clk_data);
1082 +
1083 +free_clk_priv:
1084 +       kfree(priv);
1085 +}
1086 +CLK_OF_DECLARE_DRIVER(rt2880_clk, "ralink,rt2880-sysc", mtmips_clk_init);
1087 +CLK_OF_DECLARE_DRIVER(rt3050_clk, "ralink,rt3050-sysc", mtmips_clk_init);
1088 +CLK_OF_DECLARE_DRIVER(rt3052_clk, "ralink,rt3052-sysc", mtmips_clk_init);
1089 +CLK_OF_DECLARE_DRIVER(rt3352_clk, "ralink,rt3352-sysc", mtmips_clk_init);
1090 +CLK_OF_DECLARE_DRIVER(rt3883_clk, "ralink,rt3883-sysc", mtmips_clk_init);
1091 +CLK_OF_DECLARE_DRIVER(rt5350_clk, "ralink,rt5350-sysc", mtmips_clk_init);
1092 +CLK_OF_DECLARE_DRIVER(mt7620_clk, "ralink,mt7620-sysc", mtmips_clk_init);
1093 +CLK_OF_DECLARE_DRIVER(mt7628_clk, "ralink,mt7628-sysc", mtmips_clk_init);
1094 +CLK_OF_DECLARE_DRIVER(mt7688_clk, "ralink,mt7688-sysc", mtmips_clk_init);
1095 +
1096 +struct mtmips_rst {
1097 +       struct reset_controller_dev rcdev;
1098 +       struct regmap *sysc;
1099 +};
1100 +
1101 +static struct mtmips_rst *to_mtmips_rst(struct reset_controller_dev *dev)
1102 +{
1103 +       return container_of(dev, struct mtmips_rst, rcdev);
1104 +}
1105 +
1106 +static int mtmips_assert_device(struct reset_controller_dev *rcdev,
1107 +                               unsigned long id)
1108 +{
1109 +       struct mtmips_rst *data = to_mtmips_rst(rcdev);
1110 +       struct regmap *sysc = data->sysc;
1111 +
1112 +       return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
1113 +}
1114 +
1115 +static int mtmips_deassert_device(struct reset_controller_dev *rcdev,
1116 +                                 unsigned long id)
1117 +{
1118 +       struct mtmips_rst *data = to_mtmips_rst(rcdev);
1119 +       struct regmap *sysc = data->sysc;
1120 +
1121 +       return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
1122 +}
1123 +
1124 +static int mtmips_reset_device(struct reset_controller_dev *rcdev,
1125 +                              unsigned long id)
1126 +{
1127 +       int ret;
1128 +
1129 +       ret = mtmips_assert_device(rcdev, id);
1130 +       if (ret < 0)
1131 +               return ret;
1132 +
1133 +       return mtmips_deassert_device(rcdev, id);
1134 +}
1135 +
1136 +static int mtmips_rst_xlate(struct reset_controller_dev *rcdev,
1137 +                           const struct of_phandle_args *reset_spec)
1138 +{
1139 +       unsigned long id = reset_spec->args[0];
1140 +
1141 +       if (id == 0 || id >= rcdev->nr_resets)
1142 +               return -EINVAL;
1143 +
1144 +       return id;
1145 +}
1146 +
1147 +static const struct reset_control_ops reset_ops = {
1148 +       .reset = mtmips_reset_device,
1149 +       .assert = mtmips_assert_device,
1150 +       .deassert = mtmips_deassert_device
1151 +};
1152 +
1153 +static int mtmips_reset_init(struct device *dev, struct regmap *sysc)
1154 +{
1155 +       struct mtmips_rst *rst_data;
1156 +
1157 +       rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
1158 +       if (!rst_data)
1159 +               return -ENOMEM;
1160 +
1161 +       rst_data->sysc = sysc;
1162 +       rst_data->rcdev.ops = &reset_ops;
1163 +       rst_data->rcdev.owner = THIS_MODULE;
1164 +       rst_data->rcdev.nr_resets = 32;
1165 +       rst_data->rcdev.of_reset_n_cells = 1;
1166 +       rst_data->rcdev.of_xlate = mtmips_rst_xlate;
1167 +       rst_data->rcdev.of_node = dev_of_node(dev);
1168 +
1169 +       return devm_reset_controller_register(dev, &rst_data->rcdev);
1170 +}
1171 +
1172 +static int mtmips_clk_probe(struct platform_device *pdev)
1173 +{
1174 +       struct device_node *np = pdev->dev.of_node;
1175 +       struct device *dev = &pdev->dev;
1176 +       struct mtmips_clk_priv *priv;
1177 +       int ret;
1178 +
1179 +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1180 +       if (!priv)
1181 +               return -ENOMEM;
1182 +
1183 +       priv->sysc = syscon_node_to_regmap(np);
1184 +       if (IS_ERR(priv->sysc))
1185 +               return dev_err_probe(dev, PTR_ERR(priv->sysc),
1186 +                                    "Could not get sysc syscon regmap\n");
1187 +
1188 +       ret = mtmips_reset_init(dev, priv->sysc);
1189 +       if (ret)
1190 +               return dev_err_probe(dev, ret, "Could not init reset controller\n");
1191 +
1192 +       return 0;
1193 +}
1194 +
1195 +static const struct of_device_id mtmips_clk_of_match[] = {
1196 +       { .compatible = "ralink,rt2880-reset" },
1197 +       { .compatible = "ralink,rt2880-sysc" },
1198 +       { .compatible = "ralink,rt3050-sysc" },
1199 +       { .compatible = "ralink,rt3052-sysc" },
1200 +       { .compatible = "ralink,rt3352-sysc" },
1201 +       { .compatible = "ralink,rt3883-sysc" },
1202 +       { .compatible = "ralink,rt5350-sysc" },
1203 +       { .compatible = "ralink,mt7620-sysc" },
1204 +       { .compatible = "ralink,mt7628-sysc" },
1205 +       { .compatible = "ralink,mt7688-sysc" },
1206 +       {}
1207 +};
1208 +
1209 +static struct platform_driver mtmips_clk_driver = {
1210 +       .probe = mtmips_clk_probe,
1211 +       .driver = {
1212 +               .name = "mtmips-clk",
1213 +               .of_match_table = mtmips_clk_of_match,
1214 +       },
1215 +};
1216 +
1217 +static int __init mtmips_clk_reset_init(void)
1218 +{
1219 +       return platform_driver_register(&mtmips_clk_driver);
1220 +}
1221 +arch_initcall(mtmips_clk_reset_init);