target/linux/mvebu/files-6.6/arch/arm64/boot/dts/marvell/cn9131-puzzle-m901.dts

   1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
   2 /*
   3  * Copyright (C) 2019 Marvell International Ltd.
   4  *
   5  * Device tree for the CN9131-DB board.
   6  */
   7
   8 #include "cn9130.dtsi"
   9 #include "puzzle-thermal.dtsi"
  10
  11 #include <dt-bindings/gpio/gpio.h>
  12 #include <dt-bindings/input/input.h>
  13 #include <dt-bindings/leds/common.h>
  14
  15 / {
  16         model = "iEi Puzzle-M901";
  17         compatible = "iei,puzzle-m901",
  18                      "marvell,armada-ap807-quad", "marvell,armada-ap807";
  19
  20         chosen {
  21                 stdout-path = "serial0:115200n8";
  22         };
  23
  24         aliases {
  25                 i2c0 = &cp1_i2c0;
  26                 i2c1 = &cp0_i2c0;
  27                 ethernet0 = &cp0_eth0;
  28                 ethernet1 = &cp0_eth1;
  29                 ethernet2 = &cp0_eth2;
  30                 ethernet3 = &cp1_eth0;
  31                 ethernet4 = &cp1_eth1;
  32                 ethernet5 = &cp1_eth2;
  33                 gpio1 = &cp0_gpio1;
  34                 gpio2 = &cp0_gpio2;
  35                 gpio3 = &cp1_gpio1;
  36                 gpio4 = &cp1_gpio2;
  37                 led-boot = &led_power;
  38                 led-failsafe = &led_info;
  39                 led-running = &led_power;
  40                 led-upgrade = &led_info;
  41         };
  42
  43         memory@00000000 {
  44                 device_type = "memory";
  45                 reg = <0x0 0x0 0x0 0x80000000>;
  46         };
  47
  48         gpio_keys {
  49                 compatible = "gpio-keys";
  50
  51                 reset {
  52                         label = "Reset";
  53                         linux,code = <KEY_RESTART>;
  54                         gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
  55                 };
  56         };
  57 };
  58
  59 &uart0 {
  60         status = "okay";
  61 };
  62
  63 &cp0_uart0 {
  64         status = "okay";
  65
  66         puzzle-mcu {
  67                 compatible = "iei,wt61p803-puzzle";
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 current-speed = <115200>;
  71                 enable-beep;
  72                 status = "okay";
  73
  74                 leds {
  75                         compatible = "iei,wt61p803-puzzle-leds";
  76                         #address-cells = <1>;
  77                         #size-cells = <0>;
  78                         status = "okay";
  79
  80                         led@0 {
  81                                 reg = <0>;
  82                                 label = "white:network";
  83                                 active-low;
  84                         };
  85
  86                         led@1 {
  87                                 reg = <1>;
  88                                 label = "green:cloud";
  89                                 active-low;
  90                         };
  91
  92                         led_info: led@2 {
  93                                 reg = <2>;
  94                                 label = "orange:info";
  95                                 active-low;
  96                         };
  97
  98                         led_power: led@3 {
  99                                 reg = <3>;
 100                                 function = LED_FUNCTION_POWER;
 101                                 color = <LED_COLOR_ID_YELLOW>;
 102                                 active-low;
 103                                 default-state = "on";
 104                         };
 105                 };
 106
 107                 hwmon {
 108                         compatible = "iei,wt61p803-puzzle-hwmon";
 109                         #address-cells = <1>;
 110                         #size-cells = <0>;
 111
 112                         chassis_fan_group0: fan-group@0 {
 113                                 #cooling-cells = <2>;
 114                                 reg = <0x00>;
 115                                 cooling-levels = <0 159 195 211 223 241 255>;
 116                         };
 117                 };
 118         };
 119 };
 120
 121 &ap_thermal_ic {
 122         PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
 123 };
 124
 125 &cp0_thermal_ic {
 126         PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
 127 };
 128
 129 /* on-board eMMC - U9 */
 130 &ap_sdhci0 {
 131         pinctrl-names = "default";
 132         bus-width = <8>;
 133         status = "okay";
 134         mmc-ddr-1_8v;
 135         mmc-hs400-1_8v;
 136 };
 137
 138 &cp0_crypto {
 139         status = "okay";
 140 };
 141
 142 &cp0_xmdio {
 143         status = "okay";
 144         cp0_nbaset_phy0: ethernet-phy@0 {
 145                 compatible = "ethernet-phy-ieee802.3-c45";
 146                 reg = <2>;
 147         };
 148         cp0_nbaset_phy1: ethernet-phy@1 {
 149                 compatible = "ethernet-phy-ieee802.3-c45";
 150                 reg = <0>;
 151         };
 152         cp0_nbaset_phy2: ethernet-phy@2 {
 153                 compatible = "ethernet-phy-ieee802.3-c45";
 154                 reg = <8>;
 155         };
 156 };
 157
 158 &cp0_ethernet {
 159         status = "okay";
 160 };
 161
 162 /* SLM-1521-V2, CON9 */
 163 &cp0_eth0 {
 164         status = "okay";
 165         phy-mode = "2500base-x";
 166         phys = <&cp0_comphy2 0>;
 167         phy = <&cp0_nbaset_phy0>;
 168 };
 169
 170 &cp0_eth1 {
 171         status = "okay";
 172         phy-mode = "2500base-x";
 173         phys = <&cp0_comphy4 1>;
 174         phy = <&cp0_nbaset_phy1>;
 175 };
 176
 177 &cp0_eth2 {
 178         status = "okay";
 179         phy-mode = "2500base-x";
 180         phys = <&cp0_comphy5 2>;
 181         phy = <&cp0_nbaset_phy2>;
 182 };
 183
 184 &cp0_gpio1 {
 185         status = "okay";
 186 };
 187
 188 &cp0_gpio2 {
 189         status = "okay";
 190 };
 191
 192 &cp0_i2c0 {
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&cp0_i2c0_pins>;
 195         status = "okay";
 196         clock-frequency = <100000>;
 197         rtc@32 {
 198                 compatible = "epson,rx8130";
 199                 reg = <0x32>;
 200                 wakeup-source;
 201         };
 202 };
 203
 204 /* SLM-1521-V2, CON6 */
 205 &cp0_pcie0 {
 206         status = "okay";
 207         num-lanes = <2>;
 208         num-viewport = <8>;
 209         phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>;
 210 };
 211
 212 /* U55 */
 213 &cp0_spi1 {
 214         pinctrl-names = "default";
 215         pinctrl-0 = <&cp0_spi0_pins>;
 216         reg = <0x700680 0x50>,          /* control */
 217               <0x2000000 0x1000000>;    /* CS0 */
 218         status = "okay";
 219         spi-flash@0 {
 220                 #address-cells = <0x1>;
 221                 #size-cells = <0x1>;
 222                 compatible = "jedec,spi-nor";
 223                 reg = <0x0>;
 224                 spi-max-frequency = <40000000>;
 225                 partitions {
 226                         compatible = "fixed-partitions";
 227                         #address-cells = <1>;
 228                         #size-cells = <1>;
 229                         partition@0 {
 230                                 label = "U-Boot";
 231                                 reg = <0x0 0x1f0000>;
 232                         };
 233                         partition@1f0000 {
 234                                 label = "U-Boot ENV Factory";
 235                                 reg = <0x1f0000 0x10000>;
 236                         };
 237                         partition@200000 {
 238                                 label = "Reserved";
 239                                 reg = <0x200000 0x1f0000>;
 240                         };
 241                         partition@3f0000 {
 242                                 label = "U-Boot ENV";
 243                                 reg = <0x3f0000 0x10000>;
 244                         };
 245                 };
 246         };
 247 };
 248
 249 &cp0_rtc {
 250         status = "disabled";
 251 };
 252
 253 &cp0_syscon0 {
 254         cp0_pinctrl: pinctrl {
 255                 compatible = "marvell,cp115-standalone-pinctrl";
 256                 cp0_i2c0_pins: cp0-i2c-pins-0 {
 257                         marvell,pins = "mpp37", "mpp38";
 258                         marvell,function = "i2c0";
 259                 };
 260                 cp0_i2c1_pins: cp0-i2c-pins-1 {
 261                         marvell,pins = "mpp35", "mpp36";
 262                         marvell,function = "i2c1";
 263                 };
 264                 cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
 265                         marvell,pins = "mpp0", "mpp1", "mpp2",
 266                                        "mpp3", "mpp4", "mpp5",
 267                                        "mpp6", "mpp7", "mpp8",
 268                                        "mpp9", "mpp10", "mpp11";
 269                         marvell,function = "ge0";
 270                 };
 271                 cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
 272                         marvell,pins = "mpp44", "mpp45", "mpp46",
 273                                        "mpp47", "mpp48", "mpp49",
 274                                        "mpp50", "mpp51", "mpp52",
 275                                        "mpp53", "mpp54", "mpp55";
 276                         marvell,function = "ge1";
 277                 };
 278                 cp0_spi0_pins: cp0-spi-pins-0 {
 279                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 280                         marvell,function = "spi1";
 281                 };
 282         };
 283 };
 284
 285 /*
 286  * Instantiate the first connected CP115
 287  */
 288
 289 #define CP11X_NAME              cp1
 290 #define CP11X_BASE              f6000000
 291 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
 292 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 293 #define CP11X_PCIE0_BASE        f6600000
 294 #define CP11X_PCIE1_BASE        f6620000
 295 #define CP11X_PCIE2_BASE        f6640000
 296
 297 #include "armada-cp115.dtsi"
 298
 299 #undef CP11X_NAME
 300 #undef CP11X_BASE
 301 #undef CP11X_PCIEx_MEM_BASE
 302 #undef CP11X_PCIEx_MEM_SIZE
 303 #undef CP11X_PCIE0_BASE
 304 #undef CP11X_PCIE1_BASE
 305 #undef CP11X_PCIE2_BASE
 306
 307 &cp1_crypto {
 308         status = "okay";
 309 };
 310
 311 &cp1_xmdio {
 312         status = "okay";
 313         cp1_nbaset_phy0: ethernet-phy@3 {
 314                 compatible = "ethernet-phy-ieee802.3-c45";
 315                 reg = <2>;
 316         };
 317         cp1_nbaset_phy1: ethernet-phy@4 {
 318                 compatible = "ethernet-phy-ieee802.3-c45";
 319                 reg = <0>;
 320         };
 321         cp1_nbaset_phy2: ethernet-phy@5 {
 322                 compatible = "ethernet-phy-ieee802.3-c45";
 323                 reg = <8>;
 324         };
 325 };
 326
 327 &cp1_ethernet {
 328         status = "okay";
 329 };
 330
 331 /* CON50 */
 332 &cp1_eth0 {
 333         status = "okay";
 334         phy-mode = "2500base-x";
 335         phys = <&cp1_comphy2 0>;
 336         phy = <&cp1_nbaset_phy0>;
 337 };
 338
 339 &cp1_eth1 {
 340         status = "okay";
 341         phy-mode = "2500base-x";
 342         phys = <&cp1_comphy4 1>;
 343         phy = <&cp1_nbaset_phy1>;
 344 };
 345
 346 &cp1_eth2 {
 347         status = "okay";
 348         phy-mode = "2500base-x";
 349         phys = <&cp1_comphy5 2>;
 350         phy = <&cp1_nbaset_phy2>;
 351 };
 352
 353 &cp1_sata0 {
 354         status = "okay";
 355         sata-port@1 {
 356                 status = "okay";
 357                 phys = <&cp1_comphy0 1>;
 358         };
 359 };
 360
 361 &cp1_gpio1 {
 362         status = "okay";
 363 };
 364
 365 &cp1_gpio2 {
 366         status = "okay";
 367 };
 368
 369 &cp1_i2c0 {
 370         status = "okay";
 371         pinctrl-names = "default";
 372         pinctrl-0 = <&cp1_i2c0_pins>;
 373         clock-frequency = <100000>;
 374 };
 375
 376 &cp1_rtc {
 377         status = "disabled";
 378 };
 379
 380 &cp1_syscon0 {
 381         cp1_pinctrl: pinctrl {
 382                 compatible = "marvell,cp115-standalone-pinctrl";
 383                 cp1_i2c0_pins: cp1-i2c-pins-0 {
 384                         marvell,pins = "mpp37", "mpp38";
 385                         marvell,function = "i2c0";
 386                 };
 387                 cp1_spi0_pins: cp1-spi-pins-0 {
 388                         marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
 389                         marvell,function = "spi1";
 390                 };
 391                 cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
 392                         marvell,pins = "mpp3";
 393                         marvell,function = "gpio";
 394                 };
 395                 cp1_sfp_pins: sfp-pins {
 396                         marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
 397                         marvell,function = "gpio";
 398                 };
 399         };
 400 };
 401
 402 &cp1_thermal_ic {
 403         PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
 404 };
 405
 406 &cp1_usb3_1 {
 407         status = "okay";
 408         phys = <&cp1_comphy3 1>;
 409         phy-names = "usb";
 410 };