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+ 31 Dec 2022 17:01:49 -0500 (EST)
+From: Samuel Holland <samuel@sholland.org>
+To: Corentin Labbe <clabbe.montjoie@gmail.com>,
+ Herbert Xu <herbert@gondor.apana.org.au>,
+ "David S . Miller" <davem@davemloft.net>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Jernej Skrabec <jernej.skrabec@gmail.com>,
+ Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+ Rob Herring <robh+dt@kernel.org>
+Cc: Samuel Holland <samuel@sholland.org>,
+ Albert Ou <aou@eecs.berkeley.edu>,
+ Conor Dooley <conor@kernel.org>,
+ Palmer Dabbelt <palmer@dabbelt.com>,
+ Paul Walmsley <paul.walmsley@sifive.com>,
+ devicetree@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org,
+ linux-crypto@vger.kernel.org,
+ linux-kernel@vger.kernel.org,
+ linux-riscv@lists.infradead.org,
+ linux-sunxi@lists.linux.dev
+Subject: [PATCH v2 1/3] dt-bindings: crypto: sun8i-ce: Add compatible for D1
+Date: Sat, 31 Dec 2022 16:01:43 -0600
+Message-Id: <20221231220146.646-2-samuel@sholland.org>
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+
+D1 has a crypto engine similar to the one in other Allwinner SoCs.
+Like H6, it has a separate MBUS clock gate.
+
+It also requires the internal RC oscillator to be enabled for the TRNG
+to return data, presumably because noise from the oscillator is used as
+an entropy source. This is likely the case for earlier variants as well,
+but it really only matters for H616 and newer SoCs, as H6 provides no
+way to disable the internal oscillator.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Acked-by: Corentin Labbe <clabbe.montjoie@gmail.com>
+---
+I noticed that the vendor driver has code to explicitly enable IOSC when
+using the TRNG on A83T (search SS_TRNG_OSC_ADDR), but that is covered by
+a different binding/driver in mainline.
+
+Changes in v2:
+ - Add TRNG clock
+
+ .../bindings/crypto/allwinner,sun8i-ce.yaml | 33 ++++++++++++++-----
+ 1 file changed, 25 insertions(+), 8 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
+index 026a9f9e1aeb..4287678aa79f 100644
+--- a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
++++ b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
+@@ -14,6 +14,7 @@ properties:
+ enum:
+ - allwinner,sun8i-h3-crypto
+ - allwinner,sun8i-r40-crypto
++ - allwinner,sun20i-d1-crypto
+ - allwinner,sun50i-a64-crypto
+ - allwinner,sun50i-h5-crypto
+ - allwinner,sun50i-h6-crypto
+@@ -29,6 +30,7 @@ properties:
+ - description: Bus clock
+ - description: Module clock
+ - description: MBus clock
++ - description: TRNG clock (RC oscillator)
+ minItems: 2
+
+ clock-names:
+@@ -36,6 +38,7 @@ properties:
+ - const: bus
+ - const: mod
+ - const: ram
++ - const: trng
+ minItems: 2
+
+ resets:
+@@ -44,19 +47,33 @@ properties:
+ if:
+ properties:
+ compatible:
+- const: allwinner,sun50i-h6-crypto
++ enum:
++ - allwinner,sun20i-d1-crypto
+ then:
+ properties:
+ clocks:
+- minItems: 3
++ minItems: 4
+ clock-names:
+- minItems: 3
++ minItems: 4
+ else:
+- properties:
+- clocks:
+- maxItems: 2
+- clock-names:
+- maxItems: 2
++ if:
++ properties:
++ compatible:
++ const: allwinner,sun50i-h6-crypto
++ then:
++ properties:
++ clocks:
++ minItems: 3
++ maxItems: 3
++ clock-names:
++ minItems: 3
++ maxItems: 3
++ else:
++ properties:
++ clocks:
++ maxItems: 2
++ clock-names:
++ maxItems: 2
+
+ required:
+ - compatible
+
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+From: Samuel Holland <samuel@sholland.org>
+To: Corentin Labbe <clabbe.montjoie@gmail.com>,
+ Herbert Xu <herbert@gondor.apana.org.au>,
+ "David S . Miller" <davem@davemloft.net>,
+ Chen-Yu Tsai <wens@csie.org>,
+ Jernej Skrabec <jernej.skrabec@gmail.com>,
+ Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+ Rob Herring <robh+dt@kernel.org>
+Cc: Samuel Holland <samuel@sholland.org>,
+ Albert Ou <aou@eecs.berkeley.edu>,
+ Conor Dooley <conor@kernel.org>,
+ Palmer Dabbelt <palmer@dabbelt.com>,
+ Paul Walmsley <paul.walmsley@sifive.com>,
+ devicetree@vger.kernel.org,
+ linux-arm-kernel@lists.infradead.org,
+ linux-crypto@vger.kernel.org,
+ linux-kernel@vger.kernel.org,
+ linux-riscv@lists.infradead.org,
+ linux-sunxi@lists.linux.dev
+Subject: [PATCH v2 3/3] riscv: dts: allwinner: d1: Add crypto engine node
+Date: Sat, 31 Dec 2022 16:01:45 -0600
+Message-Id: <20221231220146.646-4-samuel@sholland.org>
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+D1 contains a crypto engine which is supported by the sun8i-ce driver.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
+---
+
+Changes in v2:
+ - New patch for v2
+
+ arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+index dff363a3c934..b30b4b1465f6 100644
+--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+@@ -378,6 +378,18 @@ sid: efuse@3006000 {
+ #size-cells = <1>;
+ };
+
++ crypto: crypto@3040000 {
++ compatible = "allwinner,sun20i-d1-crypto";
++ reg = <0x3040000 0x800>;
++ interrupts = <SOC_PERIPHERAL_IRQ(52) IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_CE>,
++ <&ccu CLK_CE>,
++ <&ccu CLK_MBUS_CE>,
++ <&rtc CLK_IOSC>;
++ clock-names = "bus", "mod", "ram", "trng";
++ resets = <&ccu RST_BUS_CE>;
++ };
++
+ mbus: dram-controller@3102000 {
+ compatible = "allwinner,sun20i-d1-mbus";
+ reg = <0x3102000 0x1000>,
projects / openwrt / staging / wigyori.git / commitdiff