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kernel/at91: Restore kernel files for v5.15
[openwrt/staging/stintel.git] / target / linux / at91 / patches-5.15 / 107-clk-at91-clk-master-add-notifier-for-divider.patch
1 From 75d5d1d584ae73ba0c36d1d7255db6153ca4d3f3 Mon Sep 17 00:00:00 2001
2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
3 Date: Mon, 11 Oct 2021 14:27:16 +0300
4 Subject: [PATCH 244/247] clk: at91: clk-master: add notifier for divider
5
6 SAMA7G5 supports DVFS by changing cpuck. On SAMA7G5 mck0 shares the same
7 parent with cpuck as seen in the following clock tree:
8
9 +----------> cpuck
10 |
11 FRAC PLL ---> DIV PLL -+-> DIV ---> mck0
12
13 mck0 could go b/w 32KHz and 200MHz on SAMA7G5. To avoid mck0 overclocking
14 while changing FRAC PLL or DIV PLL the commit implements a notifier for
15 mck0 which applies a safe divider to register (maximum value of the divider
16 which is 5) on PRE_RATE_CHANGE events (such that changes on PLL to not
17 overclock mck0) and sets the maximum allowed rate on POST_RATE_CHANGE
18 events.
19
20 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
21 Link: https://lore.kernel.org/r/20211011112719.3951784-13-claudiu.beznea@microchip.com
22 Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
23 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
24 ---
25 drivers/clk/at91/at91rm9200.c | 2 +-
26 drivers/clk/at91/at91sam9260.c | 2 +-
27 drivers/clk/at91/at91sam9g45.c | 2 +-
28 drivers/clk/at91/at91sam9n12.c | 2 +-
29 drivers/clk/at91/at91sam9rl.c | 2 +-
30 drivers/clk/at91/at91sam9x5.c | 2 +-
31 drivers/clk/at91/clk-master.c | 244 +++++++++++++++++++++++----------
32 drivers/clk/at91/dt-compat.c | 2 +-
33 drivers/clk/at91/pmc.h | 2 +-
34 drivers/clk/at91/sama5d2.c | 2 +-
35 drivers/clk/at91/sama5d3.c | 2 +-
36 drivers/clk/at91/sama5d4.c | 2 +-
37 drivers/clk/at91/sama7g5.c | 2 +-
38 13 files changed, 186 insertions(+), 82 deletions(-)
39
40 --- a/drivers/clk/at91/at91rm9200.c
41 +++ b/drivers/clk/at91/at91rm9200.c
42 @@ -152,7 +152,7 @@ static void __init at91rm9200_pmc_setup(
43 "masterck_pres",
44 &at91rm9200_master_layout,
45 &rm9200_mck_characteristics,
46 - &rm9200_mck_lock, CLK_SET_RATE_GATE);
47 + &rm9200_mck_lock, CLK_SET_RATE_GATE, 0);
48 if (IS_ERR(hw))
49 goto err_free;
50
51 --- a/drivers/clk/at91/at91sam9260.c
52 +++ b/drivers/clk/at91/at91sam9260.c
53 @@ -429,7 +429,7 @@ static void __init at91sam926x_pmc_setup
54 &at91rm9200_master_layout,
55 data->mck_characteristics,
56 &at91sam9260_mck_lock,
57 - CLK_SET_RATE_GATE);
58 + CLK_SET_RATE_GATE, 0);
59 if (IS_ERR(hw))
60 goto err_free;
61
62 --- a/drivers/clk/at91/at91sam9g45.c
63 +++ b/drivers/clk/at91/at91sam9g45.c
64 @@ -164,7 +164,7 @@ static void __init at91sam9g45_pmc_setup
65 &at91rm9200_master_layout,
66 &mck_characteristics,
67 &at91sam9g45_mck_lock,
68 - CLK_SET_RATE_GATE);
69 + CLK_SET_RATE_GATE, 0);
70 if (IS_ERR(hw))
71 goto err_free;
72
73 --- a/drivers/clk/at91/at91sam9n12.c
74 +++ b/drivers/clk/at91/at91sam9n12.c
75 @@ -191,7 +191,7 @@ static void __init at91sam9n12_pmc_setup
76 &at91sam9x5_master_layout,
77 &mck_characteristics,
78 &at91sam9n12_mck_lock,
79 - CLK_SET_RATE_GATE);
80 + CLK_SET_RATE_GATE, 0);
81 if (IS_ERR(hw))
82 goto err_free;
83
84 --- a/drivers/clk/at91/at91sam9rl.c
85 +++ b/drivers/clk/at91/at91sam9rl.c
86 @@ -132,7 +132,7 @@ static void __init at91sam9rl_pmc_setup(
87 "masterck_pres",
88 &at91rm9200_master_layout,
89 &sam9rl_mck_characteristics,
90 - &sam9rl_mck_lock, CLK_SET_RATE_GATE);
91 + &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0);
92 if (IS_ERR(hw))
93 goto err_free;
94
95 --- a/drivers/clk/at91/at91sam9x5.c
96 +++ b/drivers/clk/at91/at91sam9x5.c
97 @@ -210,7 +210,7 @@ static void __init at91sam9x5_pmc_setup(
98 "masterck_pres",
99 &at91sam9x5_master_layout,
100 &mck_characteristics, &mck_lock,
101 - CLK_SET_RATE_GATE);
102 + CLK_SET_RATE_GATE, 0);
103 if (IS_ERR(hw))
104 goto err_free;
105
106 --- a/drivers/clk/at91/clk-master.c
107 +++ b/drivers/clk/at91/clk-master.c
108 @@ -5,6 +5,7 @@
109
110 #include <linux/clk-provider.h>
111 #include <linux/clkdev.h>
112 +#include <linux/clk.h>
113 #include <linux/clk/at91_pmc.h>
114 #include <linux/of.h>
115 #include <linux/mfd/syscon.h>
116 @@ -36,8 +37,12 @@ struct clk_master {
117 u8 id;
118 u8 parent;
119 u8 div;
120 + u32 safe_div;
121 };
122
123 +/* MCK div reference to be used by notifier. */
124 +static struct clk_master *master_div;
125 +
126 static inline bool clk_master_ready(struct clk_master *master)
127 {
128 unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;
129 @@ -153,107 +158,81 @@ static const struct clk_ops master_div_o
130 .restore_context = clk_master_div_restore_context,
131 };
132
133 -static int clk_master_div_set_rate(struct clk_hw *hw, unsigned long rate,
134 - unsigned long parent_rate)
135 +/* This function must be called with lock acquired. */
136 +static int clk_master_div_set(struct clk_master *master,
137 + unsigned long parent_rate, int div)
138 {
139 - struct clk_master *master = to_clk_master(hw);
140 const struct clk_master_characteristics *characteristics =
141 master->characteristics;
142 - unsigned long flags;
143 - unsigned int mckr, tmp;
144 - int div, i;
145 + unsigned long rate = parent_rate;
146 + unsigned int max_div = 0, div_index = 0, max_div_index = 0;
147 + unsigned int i, mckr, tmp;
148 int ret;
149
150 - div = DIV_ROUND_CLOSEST(parent_rate, rate);
151 - if (div > ARRAY_SIZE(characteristics->divisors))
152 - return -EINVAL;
153 -
154 for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
155 if (!characteristics->divisors[i])
156 break;
157
158 - if (div == characteristics->divisors[i]) {
159 - div = i;
160 - break;
161 + if (div == characteristics->divisors[i])
162 + div_index = i;
163 +
164 + if (max_div < characteristics->divisors[i]) {
165 + max_div = characteristics->divisors[i];
166 + max_div_index = i;
167 }
168 }
169
170 - if (i == ARRAY_SIZE(characteristics->divisors))
171 - return -EINVAL;
172 + if (div > max_div)
173 + div_index = max_div_index;
174
175 - spin_lock_irqsave(master->lock, flags);
176 ret = regmap_read(master->regmap, master->layout->offset, &mckr);
177 if (ret)
178 - goto unlock;
179 + return ret;
180
181 mckr &= master->layout->mask;
182 tmp = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
183 - if (tmp == div)
184 - goto unlock;
185 + if (tmp == div_index)
186 + return 0;
187 +
188 + rate /= characteristics->divisors[div_index];
189 + if (rate < characteristics->output.min)
190 + pr_warn("master clk div is underclocked");
191 + else if (rate > characteristics->output.max)
192 + pr_warn("master clk div is overclocked");
193
194 mckr &= ~(MASTER_DIV_MASK << MASTER_DIV_SHIFT);
195 - mckr |= (div << MASTER_DIV_SHIFT);
196 + mckr |= (div_index << MASTER_DIV_SHIFT);
197 ret = regmap_write(master->regmap, master->layout->offset, mckr);
198 if (ret)
199 - goto unlock;
200 + return ret;
201
202 while (!clk_master_ready(master))
203 cpu_relax();
204 -unlock:
205 - spin_unlock_irqrestore(master->lock, flags);
206 +
207 + master->div = characteristics->divisors[div_index];
208
209 return 0;
210 }
211
212 -static int clk_master_div_determine_rate(struct clk_hw *hw,
213 - struct clk_rate_request *req)
214 +static unsigned long clk_master_div_recalc_rate_chg(struct clk_hw *hw,
215 + unsigned long parent_rate)
216 {
217 struct clk_master *master = to_clk_master(hw);
218 - const struct clk_master_characteristics *characteristics =
219 - master->characteristics;
220 - struct clk_hw *parent;
221 - unsigned long parent_rate, tmp_rate, best_rate = 0;
222 - int i, best_diff = INT_MIN, tmp_diff;
223 -
224 - parent = clk_hw_get_parent(hw);
225 - if (!parent)
226 - return -EINVAL;
227 -
228 - parent_rate = clk_hw_get_rate(parent);
229 - if (!parent_rate)
230 - return -EINVAL;
231
232 - for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
233 - if (!characteristics->divisors[i])
234 - break;
235 -
236 - tmp_rate = DIV_ROUND_CLOSEST_ULL(parent_rate,
237 - characteristics->divisors[i]);
238 - tmp_diff = abs(tmp_rate - req->rate);
239 -
240 - if (!best_rate || best_diff > tmp_diff) {
241 - best_diff = tmp_diff;
242 - best_rate = tmp_rate;
243 - }
244 -
245 - if (!best_diff)
246 - break;
247 - }
248 -
249 - req->best_parent_rate = best_rate;
250 - req->best_parent_hw = parent;
251 - req->rate = best_rate;
252 -
253 - return 0;
254 + return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div);
255 }
256
257 static void clk_master_div_restore_context_chg(struct clk_hw *hw)
258 {
259 struct clk_master *master = to_clk_master(hw);
260 + unsigned long flags;
261 int ret;
262
263 - ret = clk_master_div_set_rate(hw, master->pms.rate,
264 - master->pms.parent_rate);
265 + spin_lock_irqsave(master->lock, flags);
266 + ret = clk_master_div_set(master, master->pms.parent_rate,
267 + DIV_ROUND_CLOSEST(master->pms.parent_rate,
268 + master->pms.rate));
269 + spin_unlock_irqrestore(master->lock, flags);
270 if (ret)
271 pr_warn("Failed to restore MCK DIV clock\n");
272 }
273 @@ -261,13 +240,116 @@ static void clk_master_div_restore_conte
274 static const struct clk_ops master_div_ops_chg = {
275 .prepare = clk_master_prepare,
276 .is_prepared = clk_master_is_prepared,
277 - .recalc_rate = clk_master_div_recalc_rate,
278 - .determine_rate = clk_master_div_determine_rate,
279 - .set_rate = clk_master_div_set_rate,
280 + .recalc_rate = clk_master_div_recalc_rate_chg,
281 .save_context = clk_master_div_save_context,
282 .restore_context = clk_master_div_restore_context_chg,
283 };
284
285 +static int clk_master_div_notifier_fn(struct notifier_block *notifier,
286 + unsigned long code, void *data)
287 +{
288 + const struct clk_master_characteristics *characteristics =
289 + master_div->characteristics;
290 + struct clk_notifier_data *cnd = data;
291 + unsigned long flags, new_parent_rate, new_rate;
292 + unsigned int mckr, div, new_div = 0;
293 + int ret, i;
294 + long tmp_diff;
295 + long best_diff = -1;
296 +
297 + spin_lock_irqsave(master_div->lock, flags);
298 + switch (code) {
299 + case PRE_RATE_CHANGE:
300 + /*
301 + * We want to avoid any overclocking of MCK DIV domain. To do
302 + * this we set a safe divider (the underclocking is not of
303 + * interest as we can go as low as 32KHz). The relation
304 + * b/w this clock and its parents are as follows:
305 + *
306 + * FRAC PLL -> DIV PLL -> MCK DIV
307 + *
308 + * With the proper safe divider we should be good even with FRAC
309 + * PLL at its maximum value.
310 + */
311 + ret = regmap_read(master_div->regmap, master_div->layout->offset,
312 + &mckr);
313 + if (ret) {
314 + ret = NOTIFY_STOP_MASK;
315 + goto unlock;
316 + }
317 +
318 + mckr &= master_div->layout->mask;
319 + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
320 +
321 + /* Switch to safe divider. */
322 + clk_master_div_set(master_div,
323 + cnd->old_rate * characteristics->divisors[div],
324 + master_div->safe_div);
325 + break;
326 +
327 + case POST_RATE_CHANGE:
328 + /*
329 + * At this point we want to restore MCK DIV domain to its maximum
330 + * allowed rate.
331 + */
332 + ret = regmap_read(master_div->regmap, master_div->layout->offset,
333 + &mckr);
334 + if (ret) {
335 + ret = NOTIFY_STOP_MASK;
336 + goto unlock;
337 + }
338 +
339 + mckr &= master_div->layout->mask;
340 + div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
341 + new_parent_rate = cnd->new_rate * characteristics->divisors[div];
342 +
343 + for (i = 0; i < ARRAY_SIZE(characteristics->divisors); i++) {
344 + if (!characteristics->divisors[i])
345 + break;
346 +
347 + new_rate = DIV_ROUND_CLOSEST_ULL(new_parent_rate,
348 + characteristics->divisors[i]);
349 +
350 + tmp_diff = characteristics->output.max - new_rate;
351 + if (tmp_diff < 0)
352 + continue;
353 +
354 + if (best_diff < 0 || best_diff > tmp_diff) {
355 + new_div = characteristics->divisors[i];
356 + best_diff = tmp_diff;
357 + }
358 +
359 + if (!tmp_diff)
360 + break;
361 + }
362 +
363 + if (!new_div) {
364 + ret = NOTIFY_STOP_MASK;
365 + goto unlock;
366 + }
367 +
368 + /* Update the div to preserve MCK DIV clock rate. */
369 + clk_master_div_set(master_div, new_parent_rate,
370 + new_div);
371 +
372 + ret = NOTIFY_OK;
373 + break;
374 +
375 + default:
376 + ret = NOTIFY_DONE;
377 + break;
378 + }
379 +
380 +unlock:
381 + spin_unlock_irqrestore(master_div->lock, flags);
382 +
383 + return ret;
384 +}
385 +
386 +static struct notifier_block clk_master_div_notifier = {
387 + .notifier_call = clk_master_div_notifier_fn,
388 +};
389 +
390 static void clk_sama7g5_master_best_diff(struct clk_rate_request *req,
391 struct clk_hw *parent,
392 unsigned long parent_rate,
393 @@ -496,6 +578,8 @@ at91_clk_register_master_internal(struct
394 struct clk_master *master;
395 struct clk_init_data init;
396 struct clk_hw *hw;
397 + unsigned int mckr;
398 + unsigned long irqflags;
399 int ret;
400
401 if (!name || !num_parents || !parent_names || !lock)
402 @@ -518,6 +602,16 @@ at91_clk_register_master_internal(struct
403 master->chg_pid = chg_pid;
404 master->lock = lock;
405
406 + if (ops == &master_div_ops_chg) {
407 + spin_lock_irqsave(master->lock, irqflags);
408 + regmap_read(master->regmap, master->layout->offset, &mckr);
409 + spin_unlock_irqrestore(master->lock, irqflags);
410 +
411 + mckr &= layout->mask;
412 + mckr = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
413 + master->div = characteristics->divisors[mckr];
414 + }
415 +
416 hw = &master->hw;
417 ret = clk_hw_register(NULL, &master->hw);
418 if (ret) {
419 @@ -554,19 +648,29 @@ at91_clk_register_master_div(struct regm
420 const char *name, const char *parent_name,
421 const struct clk_master_layout *layout,
422 const struct clk_master_characteristics *characteristics,
423 - spinlock_t *lock, u32 flags)
424 + spinlock_t *lock, u32 flags, u32 safe_div)
425 {
426 const struct clk_ops *ops;
427 + struct clk_hw *hw;
428
429 if (flags & CLK_SET_RATE_GATE)
430 ops = &master_div_ops;
431 else
432 ops = &master_div_ops_chg;
433
434 - return at91_clk_register_master_internal(regmap, name, 1,
435 - &parent_name, layout,
436 - characteristics, ops,
437 - lock, flags, -EINVAL);
438 + hw = at91_clk_register_master_internal(regmap, name, 1,
439 + &parent_name, layout,
440 + characteristics, ops,
441 + lock, flags, -EINVAL);
442 +
443 + if (!IS_ERR(hw) && safe_div) {
444 + master_div = to_clk_master(hw);
445 + master_div->safe_div = safe_div;
446 + clk_notifier_register(hw->clk,
447 + &clk_master_div_notifier);
448 + }
449 +
450 + return hw;
451 }
452
453 static unsigned long
454 --- a/drivers/clk/at91/dt-compat.c
455 +++ b/drivers/clk/at91/dt-compat.c
456 @@ -399,7 +399,7 @@ of_at91_clk_master_setup(struct device_n
457
458 hw = at91_clk_register_master_div(regmap, name, "masterck_pres",
459 layout, characteristics,
460 - &mck_lock, CLK_SET_RATE_GATE);
461 + &mck_lock, CLK_SET_RATE_GATE, 0);
462 if (IS_ERR(hw))
463 goto out_free_characteristics;
464
465 --- a/drivers/clk/at91/pmc.h
466 +++ b/drivers/clk/at91/pmc.h
467 @@ -182,7 +182,7 @@ at91_clk_register_master_div(struct regm
468 const char *parent_names,
469 const struct clk_master_layout *layout,
470 const struct clk_master_characteristics *characteristics,
471 - spinlock_t *lock, u32 flags);
472 + spinlock_t *lock, u32 flags, u32 safe_div);
473
474 struct clk_hw * __init
475 at91_clk_sama7g5_register_master(struct regmap *regmap,
476 --- a/drivers/clk/at91/sama5d2.c
477 +++ b/drivers/clk/at91/sama5d2.c
478 @@ -249,7 +249,7 @@ static void __init sama5d2_pmc_setup(str
479 "masterck_pres",
480 &at91sam9x5_master_layout,
481 &mck_characteristics, &mck_lock,
482 - CLK_SET_RATE_GATE);
483 + CLK_SET_RATE_GATE, 0);
484 if (IS_ERR(hw))
485 goto err_free;
486
487 --- a/drivers/clk/at91/sama5d3.c
488 +++ b/drivers/clk/at91/sama5d3.c
489 @@ -184,7 +184,7 @@ static void __init sama5d3_pmc_setup(str
490 "masterck_pres",
491 &at91sam9x5_master_layout,
492 &mck_characteristics, &mck_lock,
493 - CLK_SET_RATE_GATE);
494 + CLK_SET_RATE_GATE, 0);
495 if (IS_ERR(hw))
496 goto err_free;
497
498 --- a/drivers/clk/at91/sama5d4.c
499 +++ b/drivers/clk/at91/sama5d4.c
500 @@ -199,7 +199,7 @@ static void __init sama5d4_pmc_setup(str
501 "masterck_pres",
502 &at91sam9x5_master_layout,
503 &mck_characteristics, &mck_lock,
504 - CLK_SET_RATE_GATE);
505 + CLK_SET_RATE_GATE, 0);
506 if (IS_ERR(hw))
507 goto err_free;
508
509 --- a/drivers/clk/at91/sama7g5.c
510 +++ b/drivers/clk/at91/sama7g5.c
511 @@ -993,7 +993,7 @@ static void __init sama7g5_pmc_setup(str
512 parent_names[0] = "cpupll_divpmcck";
513 hw = at91_clk_register_master_div(regmap, "mck0", "cpupll_divpmcck",
514 &mck0_layout, &mck0_characteristics,
515 - &pmc_mck0_lock, 0);
516 + &pmc_mck0_lock, CLK_GET_RATE_NOCACHE, 5);
517 if (IS_ERR(hw))
518 goto err_free;
519
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