target/linux/ramips/files/drivers/net/ethernet/ralink/soc_mt7620.c

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  12  *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/if_vlan.h>
  18 #include <linux/of_net.h>
  19
  20 #include <asm/mach-ralink/ralink_regs.h>
  21
  22 #include <mt7620.h>
  23 #include "mtk_eth_soc.h"
  24 #include "gsw_mt7620.h"
  25 #include "mt7530.h"
  26 #include "mdio.h"
  27
  28 #define MT7620A_CDMA_CSG_CFG    0x400
  29 #define MT7620_DMA_VID          (MT7620A_CDMA_CSG_CFG | 0x30)
  30 #define MT7620A_RESET_FE        BIT(21)
  31 #define MT7620A_RESET_ESW       BIT(23)
  32 #define MT7620_L4_VALID         BIT(23)
  33
  34 #define MT7620_TX_DMA_UDF       BIT(15)
  35 #define TX_DMA_FP_BMAP          ((0xff) << 19)
  36
  37 #define CDMA_ICS_EN             BIT(2)
  38 #define CDMA_UCS_EN             BIT(1)
  39 #define CDMA_TCS_EN             BIT(0)
  40
  41 #define GDMA_ICS_EN             BIT(22)
  42 #define GDMA_TCS_EN             BIT(21)
  43 #define GDMA_UCS_EN             BIT(20)
  44
  45 /* frame engine counters */
  46 #define MT7620_REG_MIB_OFFSET   0x1000
  47 #define MT7620_PPE_AC_BCNT0     (MT7620_REG_MIB_OFFSET + 0x00)
  48 #define MT7620_GDM1_TX_GBCNT    (MT7620_REG_MIB_OFFSET + 0x300)
  49 #define MT7620_GDM2_TX_GBCNT    (MT7620_GDM1_TX_GBCNT + 0x40)
  50
  51 #define GSW_REG_GDMA1_MAC_ADRL  0x508
  52 #define GSW_REG_GDMA1_MAC_ADRH  0x50C
  53
  54 #define MT7621_FE_RST_GL        (FE_FE_OFFSET + 0x04)
  55 #define MT7620_FE_INT_STATUS2   (FE_FE_OFFSET + 0x08)
  56
  57 /* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
  58  * but after test it should be BIT(13).
  59  */
  60 #define MT7620_FE_GDM1_AF       BIT(13)
  61
  62 static const u16 mt7620_reg_table[FE_REG_COUNT] = {
  63         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  64         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  65         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  66         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  67         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  68         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  69         [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  70         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  71         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  72         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  73         [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  74         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  75         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  76         [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
  77         [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
  78         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
  79         [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
  80 };
  81
  82 static int mt7620_gsw_config(struct fe_priv *priv)
  83 {
  84         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
  85
  86         /* is the mt7530 internal or external */
  87         if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) {
  88                 mt7530_probe(priv->dev, gsw->base, NULL, 0);
  89                 mt7530_probe(priv->dev, NULL, priv->mii_bus, 1);
  90         } else {
  91                 mt7530_probe(priv->dev, gsw->base, NULL, 1);
  92         }
  93
  94         return 0;
  95 }
  96
  97 static void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
  98 {
  99         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 100         unsigned long flags;
 101
 102         spin_lock_irqsave(&priv->page_lock, flags);
 103         mtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
 104         mtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 105                 GSW_REG_SMACCR0);
 106         spin_unlock_irqrestore(&priv->page_lock, flags);
 107 }
 108
 109 static void mt7620_auto_poll(struct mt7620_gsw *gsw, int port)
 110 {
 111         int phy;
 112         int lsb = -1, msb = 0;
 113
 114         for_each_set_bit(phy, &gsw->autopoll, 32) {
 115                 if (lsb < 0)
 116                         lsb = phy;
 117                 msb = phy;
 118         }
 119
 120         if (lsb == msb && port ==  4)
 121                 msb++;
 122         else if (lsb == msb && port ==  5)
 123                 lsb--;
 124
 125         mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
 126                 (msb << 8) | lsb, ESW_PHY_POLLING);
 127 }
 128
 129 static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 130 {
 131         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 132         const __be32 *_id = of_get_property(np, "reg", NULL);
 133         const __be32 *phy_addr;
 134 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)
 135         int phy_mode;
 136 #else
 137         phy_interface_t phy_mode = PHY_INTERFACE_MODE_NA;
 138 #endif
 139         int size, id;
 140         int shift = 12;
 141         u32 val, mask = 0;
 142         u32 val_delay = 0;
 143         u32 mask_delay = GSW_REG_GPCx_TXDELAY | GSW_REG_GPCx_RXDELAY;
 144         int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
 145
 146         if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
 147                 if (_id)
 148                         pr_err("%s: invalid port id %d\n", np->name,
 149                                be32_to_cpu(*_id));
 150                 else
 151                         pr_err("%s: invalid port id\n", np->name);
 152                 return;
 153         }
 154
 155         id = be32_to_cpu(*_id);
 156
 157         if (id == 4)
 158                 shift = 14;
 159
 160         priv->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
 161                                                    &size);
 162         if (priv->phy->phy_fixed[id] &&
 163             (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
 164                 pr_err("%s: invalid fixed link property\n", np->name);
 165                 priv->phy->phy_fixed[id] = NULL;
 166                 return;
 167         }
 168
 169 #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)
 170         phy_mode = of_get_phy_mode(np);
 171 #else
 172         of_get_phy_mode(np, &phy_mode);
 173 #endif
 174         switch (phy_mode) {
 175         case PHY_INTERFACE_MODE_RGMII:
 176                 mask = 0;
 177                 /* Do not touch rx/tx delay in this state to avoid problems with
 178                  * backward compability.
 179                  */
 180                 mask_delay = 0;
 181                 break;
 182         case PHY_INTERFACE_MODE_RGMII_ID:
 183                 mask = 0;
 184                 val_delay |= GSW_REG_GPCx_TXDELAY;
 185                 val_delay &= ~GSW_REG_GPCx_RXDELAY;
 186                 break;
 187         case PHY_INTERFACE_MODE_RGMII_RXID:
 188                 mask = 0;
 189                 val_delay &= ~GSW_REG_GPCx_TXDELAY;
 190                 val_delay &= ~GSW_REG_GPCx_RXDELAY;
 191                 break;
 192         case PHY_INTERFACE_MODE_RGMII_TXID:
 193                 mask = 0;
 194                 val_delay &= ~GSW_REG_GPCx_TXDELAY;
 195                 val_delay |= GSW_REG_GPCx_RXDELAY;
 196                 break;
 197         case PHY_INTERFACE_MODE_MII:
 198                 mask = 1;
 199                 break;
 200         case PHY_INTERFACE_MODE_RMII:
 201                 mask = 2;
 202                 break;
 203         default:
 204                 dev_err(priv->dev, "port %d - invalid phy mode\n", id);
 205                 return;
 206         }
 207
 208         priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
 209         if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
 210                 return;
 211
 212         val = rt_sysc_r32(SYSC_REG_CFG1);
 213         val &= ~(3 << shift);
 214         val |= mask << shift;
 215         rt_sysc_w32(val, SYSC_REG_CFG1);
 216
 217         if (id == 4) {
 218                 val = mtk_switch_r32(gsw, GSW_REG_GPC2);
 219                 val &= ~(mask_delay);
 220                 val |= val_delay & mask_delay;
 221                 mtk_switch_w32(gsw, val, GSW_REG_GPC2);
 222         }
 223         else if (id == 5) {
 224                 val = mtk_switch_r32(gsw, GSW_REG_GPC1);
 225                 val &= ~(mask_delay);
 226                 val |= val_delay & mask_delay;
 227                 mtk_switch_w32(gsw, val, GSW_REG_GPC1);
 228         }
 229
 230         if (priv->phy->phy_fixed[id]) {
 231                 const __be32 *link = priv->phy->phy_fixed[id];
 232                 int tx_fc, rx_fc;
 233                 u32 val = 0;
 234
 235                 priv->phy->speed[id] = be32_to_cpup(link++);
 236                 tx_fc = be32_to_cpup(link++);
 237                 rx_fc = be32_to_cpup(link++);
 238                 priv->phy->duplex[id] = be32_to_cpup(link++);
 239                 priv->link[id] = 1;
 240
 241                 switch (priv->phy->speed[id]) {
 242                 case SPEED_10:
 243                         val = 0;
 244                         break;
 245                 case SPEED_100:
 246                         val = 1;
 247                         break;
 248                 case SPEED_1000:
 249                         val = 2;
 250                         break;
 251                 default:
 252                         dev_err(priv->dev, "invalid link speed: %d\n",
 253                                 priv->phy->speed[id]);
 254                         priv->phy->phy_fixed[id] = 0;
 255                         return;
 256                 }
 257                 val = PMCR_SPEED(val);
 258                 val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 259                         PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
 260                 if (tx_fc)
 261                         val |= PMCR_TX_FC;
 262                 if (rx_fc)
 263                         val |= PMCR_RX_FC;
 264                 if (priv->phy->duplex[id])
 265                         val |= PMCR_DUPLEX;
 266                 mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 267                 dev_info(priv->dev, "using fixed link parameters\n");
 268                 return;
 269         }
 270
 271         phy_addr = of_get_property(priv->phy->phy_node[id], "reg", NULL);
 272         if (phy_addr && mdiobus_get_phy(priv->mii_bus, be32_to_cpup(phy_addr))) {
 273                 u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 274                         PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
 275
 276                 mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 277                 fe_connect_phy_node(priv, priv->phy->phy_node[id], id);
 278                 gsw->autopoll |= BIT(be32_to_cpup(phy_addr));
 279                 mt7620_auto_poll(gsw,id);
 280                 return;
 281         }
 282 }
 283
 284 static void mt7620_fe_reset(void)
 285 {
 286         fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
 287 }
 288
 289 static void mt7620_rxcsum_config(bool enable)
 290 {
 291         if (enable)
 292                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
 293                                         GDMA_TCS_EN | GDMA_UCS_EN),
 294                                 MT7620A_GDMA1_FWD_CFG);
 295         else
 296                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
 297                                         GDMA_TCS_EN | GDMA_UCS_EN),
 298                                 MT7620A_GDMA1_FWD_CFG);
 299 }
 300
 301 static void mt7620_txcsum_config(bool enable)
 302 {
 303         if (enable)
 304                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
 305                                         CDMA_UCS_EN | CDMA_TCS_EN),
 306                                 MT7620A_CDMA_CSG_CFG);
 307         else
 308                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
 309                                         CDMA_UCS_EN | CDMA_TCS_EN),
 310                                 MT7620A_CDMA_CSG_CFG);
 311 }
 312
 313 static int mt7620_fwd_config(struct fe_priv *priv)
 314 {
 315         struct net_device *dev = priv_netdev(priv);
 316
 317         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
 318
 319         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 320         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 321
 322         return 0;
 323 }
 324
 325 static void mt7620_tx_dma(struct fe_tx_dma *txd)
 326 {
 327 }
 328
 329 static void mt7620_init_data(struct fe_soc_data *data,
 330                              struct net_device *netdev)
 331 {
 332         struct fe_priv *priv = netdev_priv(netdev);
 333
 334         priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
 335                 FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
 336
 337         netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 338                 NETIF_F_HW_VLAN_CTAG_TX;
 339         if (mt7620_get_eco() >= 5)
 340                 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
 341                         NETIF_F_IPV6_CSUM;
 342 }
 343
 344 static struct fe_soc_data mt7620_data = {
 345         .init_data = mt7620_init_data,
 346         .reset_fe = mt7620_fe_reset,
 347         .set_mac = mt7620_set_mac,
 348         .fwd_config = mt7620_fwd_config,
 349         .tx_dma = mt7620_tx_dma,
 350         .switch_init = mtk_gsw_init,
 351         .switch_config = mt7620_gsw_config,
 352         .port_init = mt7620_port_init,
 353         .reg_table = mt7620_reg_table,
 354         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
 355         .rx_int = RT5350_RX_DONE_INT,
 356         .tx_int = RT5350_TX_DONE_INT,
 357         .status_int = MT7620_FE_GDM1_AF,
 358         .checksum_bit = MT7620_L4_VALID,
 359         .has_carrier = mt7620_has_carrier,
 360         .mdio_read = mt7620_mdio_read,
 361         .mdio_write = mt7620_mdio_write,
 362         .mdio_adjust_link = mt7620_mdio_link_adjust,
 363 };
 364
 365 const struct of_device_id of_fe_match[] = {
 366         { .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
 367         {},
 368 };
 369
 370 MODULE_DEVICE_TABLE(of, of_fe_match);