package/boot/uboot-bcm53xx/patches/0002-mtd-rawnand-nand_base-Handle-algorithm-selection.patch

   1 From d75483f8892f3a0dfb8f5aa4147e72c02c8b034c Mon Sep 17 00:00:00 2001
   2 From: Linus Walleij <linus.walleij@linaro.org>
   3 Date: Fri, 7 Apr 2023 15:40:05 +0200
   4 Subject: [PATCH 2/5] mtd: rawnand: nand_base: Handle algorithm selection
   5
   6 For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
   7 D-Link DIR-885L and DIR-890L routers, we need to explicitly
   8 select the ECC like this in the device tree:
   9
  10   nand-ecc-algo = "bch";
  11   nand-ecc-strength = <1>;
  12   nand-ecc-step-size = <512>;
  13
  14 This is handled by the Linux kernel but U-Boot core does
  15 not respect this. Fix it up by parsing the algorithm and
  16 preserve the behaviour using this property to select
  17 software BCH as far as possible.
  18
  19 Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
  20 Acked-by: William Zhang <william.zhang@broadcom.com>
  21 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  22 Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm]
  23 Link: https://lore.kernel.org/all/20230407134008.1939717-3-linus.walleij@linaro.org/
  24 Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
  25 ---
  26  drivers/mtd/nand/raw/nand_base.c | 29 +++++++++++++++++++++++++----
  27  1 file changed, 25 insertions(+), 4 deletions(-)
  28
  29 --- a/drivers/mtd/nand/raw/nand_base.c
  30 +++ b/drivers/mtd/nand/raw/nand_base.c
  31 @@ -4487,6 +4487,7 @@ EXPORT_SYMBOL(nand_detect);
  32  static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node)
  33  {
  34         int ret, ecc_mode = -1, ecc_strength, ecc_step;
  35 +       int ecc_algo = NAND_ECC_UNKNOWN;
  36         const char *str;
  37
  38         ret = ofnode_read_s32_default(node, "nand-bus-width", -1);
  39 @@ -4512,10 +4513,22 @@ static int nand_dt_init(struct mtd_info
  40                         ecc_mode = NAND_ECC_SOFT_BCH;
  41         }
  42
  43 -       if (ecc_mode == NAND_ECC_SOFT) {
  44 -               str = ofnode_read_string(node, "nand-ecc-algo");
  45 -               if (str && !strcmp(str, "bch"))
  46 -                       ecc_mode = NAND_ECC_SOFT_BCH;
  47 +       str = ofnode_read_string(node, "nand-ecc-algo");
  48 +       if (str) {
  49 +               /*
  50 +                * If we are in NAND_ECC_SOFT mode, just alter the
  51 +                * soft mode to BCH here. No change of algorithm.
  52 +                */
  53 +               if (ecc_mode == NAND_ECC_SOFT) {
  54 +                       if (!strcmp(str, "bch"))
  55 +                               ecc_mode = NAND_ECC_SOFT_BCH;
  56 +               } else {
  57 +                       if (!strcmp(str, "bch")) {
  58 +                               ecc_algo = NAND_ECC_BCH;
  59 +                       } else if (!strcmp(str, "hamming")) {
  60 +                               ecc_algo = NAND_ECC_HAMMING;
  61 +                       }
  62 +               }
  63         }
  64
  65         ecc_strength = ofnode_read_s32_default(node,
  66 @@ -4529,6 +4542,14 @@ static int nand_dt_init(struct mtd_info
  67                 return -EINVAL;
  68         }
  69
  70 +       /*
  71 +        * Chip drivers may have assigned default algorithms here,
  72 +        * onlt override it if we have found something explicitly
  73 +        * specified in the device tree.
  74 +        */
  75 +       if (ecc_algo != NAND_ECC_UNKNOWN)
  76 +               chip->ecc.algo = ecc_algo;
  77 +
  78         if (ecc_mode >= 0)
  79                 chip->ecc.mode = ecc_mode;
  80