target/linux/generic/backport-5.15/737-02-v6.7-net-phy-aquantia-move-MMD_VEND-define-to-header.patch

   1 From e1fbfa4a995d42e02e22b0dff2f8b4fdee1504b3 Mon Sep 17 00:00:00 2001
   2 From: Christian Marangi <ansuelsmth@gmail.com>
   3 Date: Tue, 14 Nov 2023 15:08:42 +0100
   4 Subject: [PATCH 2/3] net: phy: aquantia: move MMD_VEND define to header
   5
   6 Move MMD_VEND define to header to clean things up and in preparation for
   7 firmware loading support that require some define placed in
   8 aquantia_main.
   9
  10 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  11 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  12 Signed-off-by: David S. Miller <davem@davemloft.net>
  13 ---
  14  drivers/net/phy/aquantia/aquantia.h       | 69 +++++++++++++++++++++++
  15  drivers/net/phy/aquantia/aquantia_hwmon.c | 14 -----
  16  drivers/net/phy/aquantia/aquantia_main.c  | 55 ------------------
  17  3 files changed, 69 insertions(+), 69 deletions(-)
  18
  19 --- a/drivers/net/phy/aquantia/aquantia.h
  20 +++ b/drivers/net/phy/aquantia/aquantia.h
  21 @@ -9,6 +9,75 @@
  22  #include <linux/device.h>
  23  #include <linux/phy.h>
  24
  25 +/* Vendor specific 1, MDIO_MMD_VEND1 */
  26 +#define VEND1_GLOBAL_FW_ID                     0x0020
  27 +#define VEND1_GLOBAL_FW_ID_MAJOR               GENMASK(15, 8)
  28 +#define VEND1_GLOBAL_FW_ID_MINOR               GENMASK(7, 0)
  29 +
  30 +/* The following registers all have similar layouts; first the registers... */
  31 +#define VEND1_GLOBAL_CFG_10M                   0x0310
  32 +#define VEND1_GLOBAL_CFG_100M                  0x031b
  33 +#define VEND1_GLOBAL_CFG_1G                    0x031c
  34 +#define VEND1_GLOBAL_CFG_2_5G                  0x031d
  35 +#define VEND1_GLOBAL_CFG_5G                    0x031e
  36 +#define VEND1_GLOBAL_CFG_10G                   0x031f
  37 +/* ...and now the fields */
  38 +#define VEND1_GLOBAL_CFG_RATE_ADAPT            GENMASK(8, 7)
  39 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE       0
  40 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX                1
  41 +#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE      2
  42 +
  43 +/* Vendor specific 1, MDIO_MMD_VEND2 */
  44 +#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL      0xc421
  45 +#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL       0xc422
  46 +#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN      0xc423
  47 +#define VEND1_THERMAL_PROV_LOW_TEMP_WARN       0xc424
  48 +#define VEND1_THERMAL_STAT1                    0xc820
  49 +#define VEND1_THERMAL_STAT2                    0xc821
  50 +#define VEND1_THERMAL_STAT2_VALID              BIT(0)
  51 +#define VEND1_GENERAL_STAT1                    0xc830
  52 +#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL     BIT(14)
  53 +#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL      BIT(13)
  54 +#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN     BIT(12)
  55 +#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN      BIT(11)
  56 +
  57 +#define VEND1_GLOBAL_GEN_STAT2                 0xc831
  58 +#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG      BIT(15)
  59 +
  60 +#define VEND1_GLOBAL_RSVD_STAT1                        0xc885
  61 +#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID    GENMASK(7, 4)
  62 +#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID                GENMASK(3, 0)
  63 +
  64 +#define VEND1_GLOBAL_RSVD_STAT9                        0xc88d
  65 +#define VEND1_GLOBAL_RSVD_STAT9_MODE           GENMASK(7, 0)
  66 +#define VEND1_GLOBAL_RSVD_STAT9_1000BT2                0x23
  67 +
  68 +#define VEND1_GLOBAL_INT_STD_STATUS            0xfc00
  69 +#define VEND1_GLOBAL_INT_VEND_STATUS           0xfc01
  70 +
  71 +#define VEND1_GLOBAL_INT_STD_MASK              0xff00
  72 +#define VEND1_GLOBAL_INT_STD_MASK_PMA1         BIT(15)
  73 +#define VEND1_GLOBAL_INT_STD_MASK_PMA2         BIT(14)
  74 +#define VEND1_GLOBAL_INT_STD_MASK_PCS1         BIT(13)
  75 +#define VEND1_GLOBAL_INT_STD_MASK_PCS2         BIT(12)
  76 +#define VEND1_GLOBAL_INT_STD_MASK_PCS3         BIT(11)
  77 +#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1      BIT(10)
  78 +#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2      BIT(9)
  79 +#define VEND1_GLOBAL_INT_STD_MASK_AN1          BIT(8)
  80 +#define VEND1_GLOBAL_INT_STD_MASK_AN2          BIT(7)
  81 +#define VEND1_GLOBAL_INT_STD_MASK_GBE          BIT(6)
  82 +#define VEND1_GLOBAL_INT_STD_MASK_ALL          BIT(0)
  83 +
  84 +#define VEND1_GLOBAL_INT_VEND_MASK             0xff01
  85 +#define VEND1_GLOBAL_INT_VEND_MASK_PMA         BIT(15)
  86 +#define VEND1_GLOBAL_INT_VEND_MASK_PCS         BIT(14)
  87 +#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS      BIT(13)
  88 +#define VEND1_GLOBAL_INT_VEND_MASK_AN          BIT(12)
  89 +#define VEND1_GLOBAL_INT_VEND_MASK_GBE         BIT(11)
  90 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1     BIT(2)
  91 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2     BIT(1)
  92 +#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3     BIT(0)
  93 +
  94  #if IS_REACHABLE(CONFIG_HWMON)
  95  int aqr_hwmon_probe(struct phy_device *phydev);
  96  #else
  97 --- a/drivers/net/phy/aquantia/aquantia_hwmon.c
  98 +++ b/drivers/net/phy/aquantia/aquantia_hwmon.c
  99 @@ -13,20 +13,6 @@
 100
 101  #include "aquantia.h"
 102
 103 -/* Vendor specific 1, MDIO_MMD_VEND2 */
 104 -#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL      0xc421
 105 -#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL       0xc422
 106 -#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN      0xc423
 107 -#define VEND1_THERMAL_PROV_LOW_TEMP_WARN       0xc424
 108 -#define VEND1_THERMAL_STAT1                    0xc820
 109 -#define VEND1_THERMAL_STAT2                    0xc821
 110 -#define VEND1_THERMAL_STAT2_VALID              BIT(0)
 111 -#define VEND1_GENERAL_STAT1                    0xc830
 112 -#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL     BIT(14)
 113 -#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL      BIT(13)
 114 -#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN     BIT(12)
 115 -#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN      BIT(11)
 116 -
 117  #if IS_REACHABLE(CONFIG_HWMON)
 118
 119  static umode_t aqr_hwmon_is_visible(const void *data,
 120 --- a/drivers/net/phy/aquantia/aquantia_main.c
 121 +++ b/drivers/net/phy/aquantia/aquantia_main.c
 122 @@ -89,61 +89,6 @@
 123  #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR      0xd31a
 124  #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES          0xd31b
 125
 126 -/* Vendor specific 1, MDIO_MMD_VEND1 */
 127 -#define VEND1_GLOBAL_FW_ID                     0x0020
 128 -#define VEND1_GLOBAL_FW_ID_MAJOR               GENMASK(15, 8)
 129 -#define VEND1_GLOBAL_FW_ID_MINOR               GENMASK(7, 0)
 130 -
 131 -#define VEND1_GLOBAL_GEN_STAT2                 0xc831
 132 -#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG      BIT(15)
 133 -
 134 -/* The following registers all have similar layouts; first the registers... */
 135 -#define VEND1_GLOBAL_CFG_10M                   0x0310
 136 -#define VEND1_GLOBAL_CFG_100M                  0x031b
 137 -#define VEND1_GLOBAL_CFG_1G                    0x031c
 138 -#define VEND1_GLOBAL_CFG_2_5G                  0x031d
 139 -#define VEND1_GLOBAL_CFG_5G                    0x031e
 140 -#define VEND1_GLOBAL_CFG_10G                   0x031f
 141 -/* ...and now the fields */
 142 -#define VEND1_GLOBAL_CFG_RATE_ADAPT            GENMASK(8, 7)
 143 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE       0
 144 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX                1
 145 -#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE      2
 146 -
 147 -#define VEND1_GLOBAL_RSVD_STAT1                        0xc885
 148 -#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID    GENMASK(7, 4)
 149 -#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID                GENMASK(3, 0)
 150 -
 151 -#define VEND1_GLOBAL_RSVD_STAT9                        0xc88d
 152 -#define VEND1_GLOBAL_RSVD_STAT9_MODE           GENMASK(7, 0)
 153 -#define VEND1_GLOBAL_RSVD_STAT9_1000BT2                0x23
 154 -
 155 -#define VEND1_GLOBAL_INT_STD_STATUS            0xfc00
 156 -#define VEND1_GLOBAL_INT_VEND_STATUS           0xfc01
 157 -
 158 -#define VEND1_GLOBAL_INT_STD_MASK              0xff00
 159 -#define VEND1_GLOBAL_INT_STD_MASK_PMA1         BIT(15)
 160 -#define VEND1_GLOBAL_INT_STD_MASK_PMA2         BIT(14)
 161 -#define VEND1_GLOBAL_INT_STD_MASK_PCS1         BIT(13)
 162 -#define VEND1_GLOBAL_INT_STD_MASK_PCS2         BIT(12)
 163 -#define VEND1_GLOBAL_INT_STD_MASK_PCS3         BIT(11)
 164 -#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1      BIT(10)
 165 -#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2      BIT(9)
 166 -#define VEND1_GLOBAL_INT_STD_MASK_AN1          BIT(8)
 167 -#define VEND1_GLOBAL_INT_STD_MASK_AN2          BIT(7)
 168 -#define VEND1_GLOBAL_INT_STD_MASK_GBE          BIT(6)
 169 -#define VEND1_GLOBAL_INT_STD_MASK_ALL          BIT(0)
 170 -
 171 -#define VEND1_GLOBAL_INT_VEND_MASK             0xff01
 172 -#define VEND1_GLOBAL_INT_VEND_MASK_PMA         BIT(15)
 173 -#define VEND1_GLOBAL_INT_VEND_MASK_PCS         BIT(14)
 174 -#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS      BIT(13)
 175 -#define VEND1_GLOBAL_INT_VEND_MASK_AN          BIT(12)
 176 -#define VEND1_GLOBAL_INT_VEND_MASK_GBE         BIT(11)
 177 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1     BIT(2)
 178 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2     BIT(1)
 179 -#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3     BIT(0)
 180 -
 181  /* Sleep and timeout for checking if the Processor-Intensive
 182   * MDIO operation is finished
 183   */