target/linux/bcm27xx/patches-6.1/950-0943-drm-vc4-hvs-Create-hw_init-function.patch

   1 From f3c84bb53107cef0009347d071c1a188ce24b8a3 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Fri, 17 Feb 2023 14:36:28 +0100
   4 Subject: [PATCH] drm/vc4: hvs: Create hw_init function
   5
   6 Since the BCM2712 will feature a significantly different HVS, let's move
   7 the hardware initialisation part of our bind function into a separate
   8 function.
   9
  10 That way, it will be easier to extend in the future.
  11
  12 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  13 ---
  14  drivers/gpu/drm/vc4/vc4_hvs.c | 155 ++++++++++++++++++----------------
  15  1 file changed, 83 insertions(+), 72 deletions(-)
  16
  17 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
  18 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
  19 @@ -1291,79 +1291,10 @@ struct vc4_hvs *__vc4_hvs_alloc(struct v
  20         return hvs;
  21  }
  22
  23 -static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
  24 +static int vc4_hvs_hw_init(struct vc4_hvs *hvs)
  25  {
  26 -       struct platform_device *pdev = to_platform_device(dev);
  27 -       struct drm_device *drm = dev_get_drvdata(master);
  28 -       struct vc4_dev *vc4 = to_vc4_dev(drm);
  29 -       struct vc4_hvs *hvs = NULL;
  30 -       int ret;
  31 -       u32 dispctrl;
  32 -       u32 reg, top;
  33 -
  34 -       hvs = __vc4_hvs_alloc(vc4, NULL);
  35 -       if (IS_ERR(hvs))
  36 -               return PTR_ERR(hvs);
  37 -
  38 -       hvs->regs = vc4_ioremap_regs(pdev, 0);
  39 -       if (IS_ERR(hvs->regs))
  40 -               return PTR_ERR(hvs->regs);
  41 -
  42 -       hvs->regset.base = hvs->regs;
  43 -       hvs->regset.regs = hvs_regs;
  44 -       hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
  45 -
  46 -       if (vc4->gen == VC4_GEN_5) {
  47 -               struct rpi_firmware *firmware;
  48 -               struct device_node *node;
  49 -               unsigned int max_rate;
  50 -
  51 -               node = rpi_firmware_find_node();
  52 -               if (!node)
  53 -                       return -EINVAL;
  54 -
  55 -               firmware = rpi_firmware_get(node);
  56 -               of_node_put(node);
  57 -               if (!firmware)
  58 -                       return -EPROBE_DEFER;
  59 -
  60 -               hvs->core_clk = devm_clk_get(&pdev->dev, NULL);
  61 -               if (IS_ERR(hvs->core_clk)) {
  62 -                       dev_err(&pdev->dev, "Couldn't get core clock\n");
  63 -                       return PTR_ERR(hvs->core_clk);
  64 -               }
  65 -
  66 -               max_rate = rpi_firmware_clk_get_max_rate(firmware,
  67 -                                                        RPI_FIRMWARE_CORE_CLK_ID);
  68 -               rpi_firmware_put(firmware);
  69 -               if (max_rate >= 550000000)
  70 -                       hvs->vc5_hdmi_enable_hdmi_20 = true;
  71 -
  72 -               if (max_rate >= 600000000)
  73 -                       hvs->vc5_hdmi_enable_4096by2160 = true;
  74 -
  75 -               hvs->max_core_rate = max_rate;
  76 -
  77 -               ret = clk_prepare_enable(hvs->core_clk);
  78 -               if (ret) {
  79 -                       dev_err(&pdev->dev, "Couldn't enable the core clock\n");
  80 -                       return ret;
  81 -               }
  82 -       }
  83 -
  84 -       if (vc4->gen == VC4_GEN_4)
  85 -               hvs->dlist = hvs->regs + SCALER_DLIST_START;
  86 -       else
  87 -               hvs->dlist = hvs->regs + SCALER5_DLIST_START;
  88 -
  89 -       /* Upload filter kernels.  We only have the one for now, so we
  90 -        * keep it around for the lifetime of the driver.
  91 -        */
  92 -       ret = vc4_hvs_upload_linear_kernel(hvs,
  93 -                                          &hvs->mitchell_netravali_filter,
  94 -                                          mitchell_netravali_1_3_1_3_kernel);
  95 -       if (ret)
  96 -               return ret;
  97 +       struct vc4_dev *vc4 = hvs->vc4;
  98 +       u32 dispctrl, reg;
  99
 100         reg = HVS_READ(SCALER_DISPECTRL);
 101         reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK;
 102 @@ -1445,6 +1376,86 @@ static int vc4_hvs_bind(struct device *d
 103
 104         HVS_WRITE(SCALER_DISPCTRL, dispctrl);
 105
 106 +       return 0;
 107 +}
 108 +
 109 +static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
 110 +{
 111 +       struct platform_device *pdev = to_platform_device(dev);
 112 +       struct drm_device *drm = dev_get_drvdata(master);
 113 +       struct vc4_dev *vc4 = to_vc4_dev(drm);
 114 +       struct vc4_hvs *hvs = NULL;
 115 +       int ret;
 116 +       u32 reg, top;
 117 +
 118 +       hvs = __vc4_hvs_alloc(vc4, NULL);
 119 +       if (IS_ERR(hvs))
 120 +               return PTR_ERR(hvs);
 121 +
 122 +       hvs->regs = vc4_ioremap_regs(pdev, 0);
 123 +       if (IS_ERR(hvs->regs))
 124 +               return PTR_ERR(hvs->regs);
 125 +
 126 +       hvs->regset.base = hvs->regs;
 127 +       hvs->regset.regs = hvs_regs;
 128 +       hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
 129 +
 130 +       if (vc4->gen == VC4_GEN_5) {
 131 +               struct rpi_firmware *firmware;
 132 +               struct device_node *node;
 133 +               unsigned int max_rate;
 134 +
 135 +               node = rpi_firmware_find_node();
 136 +               if (!node)
 137 +                       return -EINVAL;
 138 +
 139 +               firmware = rpi_firmware_get(node);
 140 +               of_node_put(node);
 141 +               if (!firmware)
 142 +                       return -EPROBE_DEFER;
 143 +
 144 +               hvs->core_clk = devm_clk_get(&pdev->dev, NULL);
 145 +               if (IS_ERR(hvs->core_clk)) {
 146 +                       dev_err(&pdev->dev, "Couldn't get core clock\n");
 147 +                       return PTR_ERR(hvs->core_clk);
 148 +               }
 149 +
 150 +               max_rate = rpi_firmware_clk_get_max_rate(firmware,
 151 +                                                        RPI_FIRMWARE_CORE_CLK_ID);
 152 +               rpi_firmware_put(firmware);
 153 +               if (max_rate >= 550000000)
 154 +                       hvs->vc5_hdmi_enable_hdmi_20 = true;
 155 +
 156 +               if (max_rate >= 600000000)
 157 +                       hvs->vc5_hdmi_enable_4096by2160 = true;
 158 +
 159 +               hvs->max_core_rate = max_rate;
 160 +
 161 +               ret = clk_prepare_enable(hvs->core_clk);
 162 +               if (ret) {
 163 +                       dev_err(&pdev->dev, "Couldn't enable the core clock\n");
 164 +                       return ret;
 165 +               }
 166 +       }
 167 +
 168 +       if (vc4->gen == VC4_GEN_4)
 169 +               hvs->dlist = hvs->regs + SCALER_DLIST_START;
 170 +       else
 171 +               hvs->dlist = hvs->regs + SCALER5_DLIST_START;
 172 +
 173 +       /* Upload filter kernels.  We only have the one for now, so we
 174 +        * keep it around for the lifetime of the driver.
 175 +        */
 176 +       ret = vc4_hvs_upload_linear_kernel(hvs,
 177 +                                          &hvs->mitchell_netravali_filter,
 178 +                                          mitchell_netravali_1_3_1_3_kernel);
 179 +       if (ret)
 180 +               return ret;
 181 +
 182 +       ret = vc4_hvs_hw_init(hvs);
 183 +       if (ret)
 184 +               return ret;
 185 +
 186         /* Recompute Composite Output Buffer (COB) allocations for the displays
 187          */
 188         if (vc4->gen == VC4_GEN_4) {