target/linux/bcm27xx/patches-6.1/950-0893-ASoC-dwc-Add-DMACR-handling.patch

   1 From b3b1177092d4d2ba6df74042d39aa42c5055f687 Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.com>
   3 Date: Mon, 3 Jul 2023 09:08:16 +0100
   4 Subject: [PATCH] ASoC: dwc: Add DMACR handling
   5
   6 Add control of the DMACR register, which is required for paced DMA
   7 (i.e. DREQ) support.
   8
   9 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  10 ---
  11  sound/soc/dwc/dwc-i2s.c | 13 ++++++++++---
  12  sound/soc/dwc/local.h   | 13 +++++++++++++
  13  2 files changed, 23 insertions(+), 3 deletions(-)
  14
  15 --- a/sound/soc/dwc/dwc-i2s.c
  16 +++ b/sound/soc/dwc/dwc-i2s.c
  17 @@ -185,9 +185,9 @@ static void i2s_stop(struct dw_i2s_dev *
  18
  19  static void dw_i2s_config(struct dw_i2s_dev *dev, int stream)
  20  {
  21 -       u32 ch_reg;
  22         struct i2s_clk_config_data *config = &dev->config;
  23 -
  24 +       u32 ch_reg;
  25 +       u32 dmacr = 0;
  26
  27         i2s_disable_channels(dev, stream);
  28
  29 @@ -198,15 +198,22 @@ static void dw_i2s_config(struct dw_i2s_
  30                         i2s_write_reg(dev->i2s_base, TFCR(ch_reg),
  31                                       dev->fifo_th - 1);
  32                         i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
  33 +                       dmacr |= (DMACR_DMAEN_TXCH0 << ch_reg);
  34                 } else {
  35                         i2s_write_reg(dev->i2s_base, RCR(ch_reg),
  36                                       dev->xfer_resolution);
  37                         i2s_write_reg(dev->i2s_base, RFCR(ch_reg),
  38                                       dev->fifo_th - 1);
  39                         i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
  40 +                       dmacr |= (DMACR_DMAEN_RXCH0 << ch_reg);
  41                 }
  42 -
  43         }
  44 +       if (stream == SNDRV_PCM_STREAM_PLAYBACK)
  45 +               dmacr |= DMACR_DMAEN_TX;
  46 +       else if (stream == SNDRV_PCM_STREAM_CAPTURE)
  47 +               dmacr |= DMACR_DMAEN_RX;
  48 +
  49 +       i2s_write_reg(dev->i2s_base, DMACR, dmacr);
  50  }
  51
  52  static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
  53 --- a/sound/soc/dwc/local.h
  54 +++ b/sound/soc/dwc/local.h
  55 @@ -25,6 +25,8 @@
  56  #define RXFFR          0x014
  57  #define TXFFR          0x018
  58
  59 +#define DMACR   0x200
  60 +
  61  /* Interrupt status register fields */
  62  #define ISR_TXFO       BIT(5)
  63  #define ISR_TXFE       BIT(4)
  64 @@ -47,6 +49,17 @@
  65  #define RFF(x)         (0x40 * x + 0x050)
  66  #define TFF(x)         (0x40 * x + 0x054)
  67
  68 +#define DMACR_DMAEN_TX         BIT(17)
  69 +#define DMACR_DMAEN_RX         BIT(16)
  70 +#define DMACR_DMAEN_TXCH3      BIT(11)
  71 +#define DMACR_DMAEN_TXCH2      BIT(10)
  72 +#define DMACR_DMAEN_TXCH1      BIT(9)
  73 +#define DMACR_DMAEN_TXCH0      BIT(8)
  74 +#define DMACR_DMAEN_RXCH3      BIT(3)
  75 +#define DMACR_DMAEN_RXCH2      BIT(2)
  76 +#define DMACR_DMAEN_RXCH1      BIT(1)
  77 +#define DMACR_DMAEN_RXCH0      BIT(0)
  78 +
  79  /* I2SCOMPRegisters */
  80  #define I2S_COMP_PARAM_2       0x01F0
  81  #define I2S_COMP_PARAM_1       0x01F4