target/linux/bcm27xx/patches-6.1/950-0881-i2c-designware-Add-SMBUS-quick-command-support.patch

   1 From 50adadfaf324ed5cbb59ce2b85eda59de4e3801a Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.com>
   3 Date: Fri, 4 Dec 2020 15:20:36 +0000
   4 Subject: [PATCH] i2c: designware: Add SMBUS quick command support
   5
   6 The SMBUS emulation code turns an SMBUS quick command into a zero-
   7 length read. This controller can't do zero length accesses, but it
   8 can do quick commands, so reverse the emulation. The alternative
   9 would be to properly implement the SMBUS support but that is a lot
  10 more work, and unnecessary just to get i2cdetect working.
  11
  12 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  13 ---
  14  drivers/i2c/busses/i2c-designware-core.h   |  2 ++
  15  drivers/i2c/busses/i2c-designware-master.c | 17 +++++++++++++++--
  16  2 files changed, 17 insertions(+), 2 deletions(-)
  17
  18 --- a/drivers/i2c/busses/i2c-designware-core.h
  19 +++ b/drivers/i2c/busses/i2c-designware-core.h
  20 @@ -117,7 +117,9 @@
  21
  22  #define DW_IC_ERR_TX_ABRT      0x1
  23
  24 +#define DW_IC_TAR_SPECIAL              BIT(11)
  25  #define DW_IC_TAR_10BITADDR_MASTER     BIT(12)
  26 +#define DW_IC_TAR_SMBUS_QUICK_CMD      BIT(16)
  27
  28  #define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH     (BIT(2) | BIT(3))
  29  #define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK     GENMASK(3, 2)
  30 --- a/drivers/i2c/busses/i2c-designware-master.c
  31 +++ b/drivers/i2c/busses/i2c-designware-master.c
  32 @@ -228,6 +228,10 @@ static void i2c_dw_xfer_init(struct dw_i
  33                 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
  34         }
  35
  36 +       /* Convert a zero-length read into an SMBUS quick command */
  37 +       if (!msgs[dev->msg_write_idx].len)
  38 +               ic_tar = DW_IC_TAR_SPECIAL | DW_IC_TAR_SMBUS_QUICK_CMD;
  39 +
  40         regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
  41                            ic_con);
  42
  43 @@ -409,6 +413,14 @@ i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
  44                 regmap_read(dev->map, DW_IC_RXFLR, &flr);
  45                 rx_limit = dev->rx_fifo_depth - flr;
  46
  47 +               /* Handle SMBUS quick commands */
  48 +               if (!buf_len) {
  49 +                       if (msgs[dev->msg_write_idx].flags & I2C_M_RD)
  50 +                               regmap_write(dev->map, DW_IC_DATA_CMD, 0x300);
  51 +                       else
  52 +                               regmap_write(dev->map, DW_IC_DATA_CMD, 0x200);
  53 +               }
  54 +
  55                 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
  56                         u32 cmd = 0;
  57
  58 @@ -673,7 +685,7 @@ static const struct i2c_algorithm i2c_dw
  59  };
  60
  61  static const struct i2c_adapter_quirks i2c_dw_quirks = {
  62 -       .flags = I2C_AQ_NO_ZERO_LEN,
  63 +       .flags = 0,
  64  };
  65
  66  static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
  67 @@ -813,7 +825,8 @@ void i2c_dw_configure_master(struct dw_i
  68  {
  69         struct i2c_timings *t = &dev->timings;
  70
  71 -       dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
  72 +       dev->functionality = I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_QUICK |
  73 +                            DW_IC_DEFAULT_FUNCTIONALITY;
  74
  75         dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
  76                           DW_IC_CON_RESTART_EN;