tools/zstd: enable position independent code compilation
[openwrt/staging/blocktrron.git] / target / linux / oxnas / patches-5.15 / 320-oxnas-phy-pcie.patch
1 --- a/arch/arm/boot/dts/ox820.dtsi
2 +++ b/arch/arm/boot/dts/ox820.dtsi
3 @@ -247,6 +247,15 @@
4 };
5 };
6
7 + pcie_phy: pcie-phy@a00000 {
8 + compatible = "oxsemi,ox820-pcie-phy";
9 + reg = <0xa00000 0x10>;
10 + #phy-cells = <0>;
11 + resets = <&reset RESET_PCIEPHY>;
12 + reset-names = "phy";
13 + status = "disabled";
14 + };
15 +
16 sys: sys-ctrl@e00000 {
17 compatible = "oxsemi,ox820-sys-ctrl", "syscon", "simple-mfd";
18 reg = <0xe00000 0x200000>;
19 --- a/drivers/phy/Kconfig
20 +++ b/drivers/phy/Kconfig
21 @@ -35,6 +35,13 @@ config PHY_LPC18XX_USB_OTG
22 This driver is need for USB0 support on LPC18xx/43xx and takes
23 care of enabling and clock setup.
24
25 +config PHY_OXNAS
26 + tristate "Oxford Semi. OX820 PCI-E PHY support"
27 + depends on HAS_IOMEM && OF && (ARM || COMPILE_TEST)
28 + select GENERIC_PHY
29 + help
30 + This option enables support for OXNAS OX820 SoC PCIE PHY.
31 +
32 config PHY_PISTACHIO_USB
33 tristate "IMG Pistachio USB2.0 PHY driver"
34 depends on MIPS || COMPILE_TEST
35 --- a/drivers/phy/Makefile
36 +++ b/drivers/phy/Makefile
37 @@ -7,6 +7,7 @@ obj-$(CONFIG_GENERIC_PHY) += phy-core.o
38 obj-$(CONFIG_GENERIC_PHY_MIPI_DPHY) += phy-core-mipi-dphy.o
39 obj-$(CONFIG_PHY_CAN_TRANSCEIVER) += phy-can-transceiver.o
40 obj-$(CONFIG_PHY_LPC18XX_USB_OTG) += phy-lpc18xx-usb-otg.o
41 +obj-$(CONFIG_PHY_OXNAS) += phy-oxnas-pcie.o
42 obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
43 obj-$(CONFIG_PHY_PISTACHIO_USB) += phy-pistachio-usb.o
44 obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o