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bd39ce7b1b874b1b077315a3c4795752d0697493
[openwrt/staging/blocktrron.git] / target / linux / oxnas / files / drivers / ata / sata_oxnas.c
1 /*
2 * sata_oxnas
3 * A driver to interface the 934 based sata core present in the ox820
4 * with libata and scsi
5 * based on sata_oxnas driver by Ma Haijun <mahaijuns@gmail.com>
6 * based on ox820 sata code by:
7 * Copyright (c) 2007 Oxford Semiconductor Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #include <linux/ata.h>
21 #include <linux/libata.h>
22 #include <linux/of_platform.h>
23 #include <linux/delay.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/clk.h>
30 #include <linux/reset.h>
31
32 #include <linux/io.h>
33 #include <linux/sizes.h>
34 #include <linux/version.h>
35
36 static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
37 {
38 u32 val = readl_relaxed(p);
39
40 val &= ~mask;
41 writel_relaxed(val, p);
42 }
43
44 static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
45 {
46 u32 val = readl_relaxed(p);
47
48 val |= mask;
49 writel_relaxed(val, p);
50 }
51
52 static inline void oxnas_register_value_mask(void __iomem *p,
53 unsigned mask, unsigned new_value)
54 {
55 /* TODO sanity check mask & new_value = new_value */
56 u32 val = readl_relaxed(p);
57
58 val &= ~mask;
59 val |= new_value;
60 writel_relaxed(val, p);
61 }
62
63 /* sgdma request structure */
64 struct sgdma_request {
65 volatile u32 qualifier;
66 volatile u32 control;
67 dma_addr_t src_pa;
68 dma_addr_t dst_pa;
69 } __packed __aligned(4);
70
71
72 /* Controller information */
73 enum {
74 SATA_OXNAS_MAX_PRD = 63,
75 SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *
76 sizeof(struct ata_bmdma_prd) +
77 sizeof(struct sgdma_request),
78 SATA_OXNAS_MAX_PORTS = 2,
79 /** The different Oxsemi SATA core version numbers */
80 SATA_OXNAS_CORE_VERSION = 0x1f3,
81 SATA_OXNAS_IRQ_FLAG = IRQF_SHARED,
82 SATA_OXNAS_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
83 ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),
84 SATA_OXNAS_QUEUE_DEPTH = 32,
85
86 SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,
87 };
88
89
90 /*
91 * SATA Port Registers
92 */
93 enum {
94 /** sata host port register offsets */
95 ORB1 = 0x00,
96 ORB2 = 0x04,
97 ORB3 = 0x08,
98 ORB4 = 0x0C,
99 ORB5 = 0x10,
100 MASTER_STATUS = 0x10,
101 FIS_CTRL = 0x18,
102 FIS_DATA = 0x1C,
103 INT_STATUS = 0x30,
104 INT_CLEAR = 0x30,
105 INT_ENABLE = 0x34,
106 INT_DISABLE = 0x38,
107 VERSION = 0x3C,
108 SATA_CONTROL = 0x5C,
109 SATA_COMMAND = 0x60,
110 HID_FEATURES = 0x64,
111 PORT_CONTROL = 0x68,
112 DRIVE_CONTROL = 0x6C,
113 /** These registers allow access to the link layer registers
114 that reside in a different clock domain to the processor bus */
115 LINK_DATA = 0x70,
116 LINK_RD_ADDR = 0x74,
117 LINK_WR_ADDR = 0x78,
118 LINK_CONTROL = 0x7C,
119 /* window control */
120 WIN1LO = 0x80,
121 WIN1HI = 0x84,
122 WIN2LO = 0x88,
123 WIN2HI = 0x8C,
124 WIN0_CONTROL = 0x90,
125 };
126
127 /** sata port register bits */
128 enum{
129 /**
130 * commands to issue in the master status to tell it to move shadow ,
131 * registers to the actual device ,
132 */
133 SATA_OPCODE_MASK = 0x00000007,
134 CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,
135 CMD_WRITE_TO_ORB_REGS = 0x2,
136 CMD_SYNC_ESCAPE = 0x7,
137 CMD_CORE_BUSY = (1 << 7),
138 CMD_DRIVE_SELECT_SHIFT = 12,
139 CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),
140
141 /** interrupt bits */
142 INT_END_OF_CMD = 1 << 0,
143 INT_LINK_SERROR = 1 << 1,
144 INT_ERROR = 1 << 2,
145 INT_LINK_IRQ = 1 << 3,
146 INT_REG_ACCESS_ERR = 1 << 7,
147 INT_BIST_FIS = 1 << 11,
148 INT_MASKABLE = INT_END_OF_CMD |
149 INT_LINK_SERROR |
150 INT_ERROR |
151 INT_LINK_IRQ |
152 INT_REG_ACCESS_ERR |
153 INT_BIST_FIS,
154 INT_WANT = INT_END_OF_CMD |
155 INT_LINK_SERROR |
156 INT_REG_ACCESS_ERR |
157 INT_ERROR,
158 INT_ERRORS = INT_LINK_SERROR |
159 INT_REG_ACCESS_ERR |
160 INT_ERROR,
161
162 /** raw interrupt bits, unmaskable, but do not generate interrupts */
163 RAW_END_OF_CMD = INT_END_OF_CMD << 16,
164 RAW_LINK_SERROR = INT_LINK_SERROR << 16,
165 RAW_ERROR = INT_ERROR << 16,
166 RAW_LINK_IRQ = INT_LINK_IRQ << 16,
167 RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,
168 RAW_BIST_FIS = INT_BIST_FIS << 16,
169 RAW_WANT = INT_WANT << 16,
170 RAW_ERRORS = INT_ERRORS << 16,
171
172 /**
173 * variables to write to the device control register to set the current
174 * device, ie. master or slave.
175 */
176 DR_CON_48 = 2,
177 DR_CON_28 = 0,
178
179 SATA_CTL_ERR_MASK = 0x00000016,
180
181 };
182
183 /* ATA SGDMA register offsets */
184 enum {
185 SGDMA_CONTROL = 0x0,
186 SGDMA_STATUS = 0x4,
187 SGDMA_REQUESTPTR = 0x8,
188 SGDMA_RESETS = 0xC,
189 SGDMA_CORESIZE = 0x10,
190 };
191
192 /* DMA controller register offsets */
193 enum {
194 DMA_CONTROL = 0x0,
195 DMA_CORESIZE = 0x20,
196
197 DMA_CONTROL_RESET = (1 << 12),
198 };
199
200 enum {
201 /* see DMA core docs for the values. Out means from memory (bus A) out
202 * to disk (bus B) */
203 SGDMA_REQCTL0OUT = 0x0497c03d,
204 /* burst mode disabled when no micro code used */
205 SGDMA_REQCTL0IN = 0x0493a3c1,
206 SGDMA_REQCTL1OUT = 0x0497c07d,
207 SGDMA_REQCTL1IN = 0x0497a3c5,
208 SGDMA_CONTROL_NOGO = 0x3e,
209 SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,
210 SGDMA_ERRORMASK = 0x3f,
211 SGDMA_BUSY = 0x80,
212
213 SGDMA_RESETS_CTRL = 1 << 0,
214 SGDMA_RESETS_ARBT = 1 << 1,
215 SGDMA_RESETS_AHB = 1 << 2,
216 SGDMA_RESETS_ALL = SGDMA_RESETS_CTRL |
217 SGDMA_RESETS_ARBT |
218 SGDMA_RESETS_AHB,
219
220 /* Final EOTs */
221 SGDMA_REQQUAL = 0x00220001,
222
223 };
224
225 /** SATA core register offsets */
226 enum {
227 DM_DBG1 = 0x000,
228 RAID_SET = 0x004,
229 DM_DBG2 = 0x008,
230 DATACOUNT_PORT0 = 0x010,
231 DATACOUNT_PORT1 = 0x014,
232 CORE_INT_STATUS = 0x030,
233 CORE_INT_CLEAR = 0x030,
234 CORE_INT_ENABLE = 0x034,
235 CORE_INT_DISABLE = 0x038,
236 CORE_REBUILD_ENABLE = 0x050,
237 CORE_FAILED_PORT_R = 0x054,
238 DEVICE_CONTROL = 0x068,
239 EXCESS = 0x06C,
240 RAID_SIZE_LOW = 0x070,
241 RAID_SIZE_HIGH = 0x074,
242 PORT_ERROR_MASK = 0x078,
243 IDLE_STATUS = 0x07C,
244 RAID_CONTROL = 0x090,
245 DATA_PLANE_CTRL = 0x0AC,
246 CORE_DATAPLANE_STAT = 0x0b8,
247 PROC_PC = 0x100,
248 CONFIG_IN = 0x3d8,
249 PROC_START = 0x3f0,
250 PROC_RESET = 0x3f4,
251 UCODE_STORE = 0x1000,
252 RAID_WP_BOT_LOW = 0x1FF0,
253 RAID_WP_BOT_HIGH = 0x1FF4,
254 RAID_WP_TOP_LOW = 0x1FF8,
255 RAID_WP_TOP_HIGH = 0x1FFC,
256 DATA_MUX_RAM0 = 0x8000,
257 DATA_MUX_RAM1 = 0xA000,
258 PORT_SIZE = 0x10000,
259 };
260
261 enum {
262 /* Sata core debug1 register bits */
263 CORE_PORT0_DATA_DIR_BIT = 20,
264 CORE_PORT1_DATA_DIR_BIT = 21,
265 CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,
266 CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,
267
268 /** sata core control register bits */
269 SCTL_CLR_ERR = 0x00003016,
270 RAID_CLR_ERR = 0x0000011e,
271
272 /* Interrupts direct from the ports */
273 NORMAL_INTS_WANTED = 0x00000303,
274
275 /* shift these left by port number */
276 COREINT_HOST = 0x00000001,
277 COREINT_END = 0x00000100,
278 CORERAW_HOST = COREINT_HOST << 16,
279 CORERAW_END = COREINT_END << 16,
280
281 /* Interrupts from the RAID controller only */
282 RAID_INTS_WANTED = 0x00008300,
283
284 /* The bits in the IDLE_STATUS that, when set indicate an idle core */
285 IDLE_CORES = (1 << 18) | (1 << 19),
286
287 /* Data plane control error-mask mask and bit, these bit in the data
288 * plane control mask out errors from the ports that prevent the SGDMA
289 * care from sending an interrupt */
290 DPC_ERROR_MASK = 0x00000300,
291 DPC_ERROR_MASK_BIT = 0x00000100,
292 /* enable jbod micro-code */
293 DPC_JBOD_UCODE = 1 << 0,
294 DPC_FIS_SWCH = 1 << 1,
295
296 /** Device Control register bits */
297 DEVICE_CONTROL_DMABT = 1 << 4,
298 DEVICE_CONTROL_ABORT = 1 << 2,
299 DEVICE_CONTROL_PAD = 1 << 3,
300 DEVICE_CONTROL_PADPAT = 1 << 16,
301 DEVICE_CONTROL_PRTRST = 1 << 8,
302 DEVICE_CONTROL_RAMRST = 1 << 12,
303 DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,
304
305 /** oxsemi HW raid modes */
306 OXNASSATA_NOTRAID = 0,
307 OXNASSATA_RAID0 = 1,
308 OXNASSATA_RAID1 = 2,
309 /** OX820 specific HW-RAID register values */
310 RAID_TWODISKS = 3,
311 UNKNOWN_MODE = ~0,
312
313 CONFIG_IN_RESUME = 2,
314 };
315
316 /* SATA PHY Registers */
317 enum {
318 PHY_STAT = 0x00,
319 PHY_DATA = 0x04,
320 };
321
322 enum {
323 STAT_READ_VALID = (1 << 21),
324 STAT_CR_ACK = (1 << 20),
325 STAT_CR_READ = (1 << 19),
326 STAT_CR_WRITE = (1 << 18),
327 STAT_CAP_DATA = (1 << 17),
328 STAT_CAP_ADDR = (1 << 16),
329
330 STAT_ACK_ANY = STAT_CR_ACK |
331 STAT_CR_READ |
332 STAT_CR_WRITE |
333 STAT_CAP_DATA |
334 STAT_CAP_ADDR,
335
336 CR_READ_ENABLE = (1 << 16),
337 CR_WRITE_ENABLE = (1 << 17),
338 CR_CAP_DATA = (1 << 18),
339 };
340
341 enum {
342 /* Link layer registers */
343 SERROR_IRQ_MASK = 5,
344 };
345
346 enum {
347 OXNAS_SATA_SOFTRESET = 1,
348 OXNAS_SATA_REINIT = 2,
349 };
350
351 enum {
352 OXNAS_SATA_UCODE_RAID0,
353 OXNAS_SATA_UCODE_RAID1,
354 OXNAS_SATA_UCODE_JBOD,
355 OXNAS_SATA_UCODE_NONE,
356 };
357
358 enum {
359 SATA_UNLOCKED,
360 SATA_WRITER,
361 SATA_READER,
362 SATA_REBUILD,
363 SATA_HWRAID,
364 SATA_SCSI_STACK
365 };
366
367 typedef irqreturn_t (*oxnas_sata_isr_callback_t)(int, unsigned long, int);
368
369 struct sata_oxnas_host_priv {
370 void __iomem *port_base;
371 void __iomem *dmactl_base;
372 void __iomem *sgdma_base;
373 void __iomem *core_base;
374 void __iomem *phy_base;
375 dma_addr_t dma_base;
376 void __iomem *dma_base_va;
377 size_t dma_size;
378 int irq;
379 int n_ports;
380 int current_ucode;
381 u32 port_frozen;
382 u32 port_in_eh;
383 struct clk *clk;
384 struct reset_control *rst_sata;
385 struct reset_control *rst_link;
386 struct reset_control *rst_phy;
387 spinlock_t phy_lock;
388 spinlock_t core_lock;
389 int core_locked;
390 int reentrant_port_no;
391 int hw_lock_count;
392 int direct_lock_count;
393 void *locker_uid;
394 int current_locker_type;
395 int scsi_nonblocking_attempts;
396 oxnas_sata_isr_callback_t isr_callback;
397 void *isr_arg;
398 wait_queue_head_t fast_wait_queue;
399 wait_queue_head_t scsi_wait_queue;
400 };
401
402
403 struct sata_oxnas_port_priv {
404 void __iomem *port_base;
405 void __iomem *dmactl_base;
406 void __iomem *sgdma_base;
407 void __iomem *core_base;
408 struct sgdma_request *sgdma_request;
409 dma_addr_t sgdma_request_pa;
410 };
411
412 static u8 sata_oxnas_check_status(struct ata_port *ap);
413 static int sata_oxnas_cleanup(struct ata_host *ah);
414 static void sata_oxnas_tf_load(struct ata_port *ap,
415 const struct ata_taskfile *tf);
416 static void sata_oxnas_irq_on(struct ata_port *ap);
417 static void sata_oxnas_post_reset_init(struct ata_port *ap);
418
419 static int sata_oxnas_acquire_hw(struct ata_port *ap, int may_sleep,
420 int timeout_jiffies);
421 static void sata_oxnas_release_hw(struct ata_port *ap);
422
423 static const void *HW_LOCKER_UID = (void *)0xdeadbeef;
424
425 /***************************************************************************
426 * ASIC access
427 ***************************************************************************/
428 static void wait_cr_ack(void __iomem *phy_base)
429 {
430 while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)
431 ; /* wait for an ack bit to be set */
432 }
433
434 static u16 read_cr(void __iomem *phy_base, u16 address)
435 {
436 iowrite32((u32)address, phy_base + PHY_STAT);
437 wait_cr_ack(phy_base);
438 iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);
439 wait_cr_ack(phy_base);
440 return (u16)ioread32(phy_base + PHY_STAT);
441 }
442
443 static void write_cr(void __iomem *phy_base, u16 data, u16 address)
444 {
445 iowrite32((u32)address, phy_base + PHY_STAT);
446 wait_cr_ack(phy_base);
447 iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);
448 wait_cr_ack(phy_base);
449 iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);
450 wait_cr_ack(phy_base);
451 }
452
453 #define PH_GAIN 2
454 #define FR_GAIN 3
455 #define PH_GAIN_OFFSET 6
456 #define FR_GAIN_OFFSET 8
457 #define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
458 #define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
459 #define USE_INT_SETTING (1<<5)
460
461 void workaround5458(struct ata_host *ah)
462 {
463 struct sata_oxnas_host_priv *hd = ah->private_data;
464 void __iomem *phy_base = hd->phy_base;
465 u16 rx_control;
466 unsigned i;
467
468 for (i = 0; i < 2; i++) {
469 rx_control = read_cr(phy_base, 0x201d + (i << 8));
470 rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
471 rx_control |= PH_GAIN << PH_GAIN_OFFSET;
472 rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;
473 write_cr(phy_base, rx_control, 0x201d+(i<<8));
474 }
475 }
476
477 /**
478 * allows access to the link layer registers
479 * @param link_reg the link layer register to access (oxsemi indexing ie
480 * 00 = static config, 04 = phy ctrl)
481 */
482 void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)
483 {
484 struct sata_oxnas_port_priv *pd = ap->private_data;
485 struct sata_oxnas_host_priv *hd = ap->host->private_data;
486 void __iomem *port_base = pd->port_base;
487 u32 patience;
488 unsigned long flags;
489
490 DPRINTK("P%d [0x%02x]->0x%08x\n", ap->port_no, link_reg, val);
491
492 spin_lock_irqsave(&hd->phy_lock, flags);
493 iowrite32(val, port_base + LINK_DATA);
494
495 /* accessed twice as a work around for a bug in the SATA abp bridge
496 * hardware (bug 6828) */
497 iowrite32(link_reg , port_base + LINK_WR_ADDR);
498 ioread32(port_base + LINK_WR_ADDR);
499
500 for (patience = 0x100000; patience > 0; --patience) {
501 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
502 break;
503 }
504 spin_unlock_irqrestore(&hd->phy_lock, flags);
505 }
506
507 static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,
508 u32 val)
509 {
510 sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);
511 return 0;
512 }
513
514 static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,
515 u32 val)
516 {
517 return sata_oxnas_scr_write_port(link->ap, sc_reg, val);
518 }
519
520 u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)
521 {
522 struct sata_oxnas_port_priv *pd = ap->private_data;
523 struct sata_oxnas_host_priv *hd = ap->host->private_data;
524 void __iomem *port_base = pd->port_base;
525 u32 result;
526 u32 patience;
527 unsigned long flags;
528
529 spin_lock_irqsave(&hd->phy_lock, flags);
530 /* accessed twice as a work around for a bug in the SATA abp bridge
531 * hardware (bug 6828) */
532 iowrite32(link_reg, port_base + LINK_RD_ADDR);
533 ioread32(port_base + LINK_RD_ADDR);
534
535 for (patience = 0x100000; patience > 0; --patience) {
536 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
537 break;
538 }
539 if (patience == 0)
540 DPRINTK("link read timed out for port %d\n", ap->port_no);
541
542 result = ioread32(port_base + LINK_DATA);
543 spin_unlock_irqrestore(&hd->phy_lock, flags);
544
545 return result;
546 }
547
548 static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,
549 u32 *val)
550 {
551 *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));
552 return 0;
553 }
554
555 static int sata_oxnas_scr_read(struct ata_link *link,
556 unsigned int sc_reg, u32 *val)
557 {
558 return sata_oxnas_scr_read_port(link->ap, sc_reg, val);
559 }
560
561 /**
562 * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
563 * registered, to be sure hardware is quiet. It clears and masks interrupt bits
564 * in the SATA core.
565 *
566 * @param ap hardware with the registers in
567 */
568 static void sata_oxnas_irq_clear(struct ata_port *ap)
569 {
570 struct sata_oxnas_port_priv *port_priv = ap->private_data;
571
572 /* clear pending interrupts */
573 iowrite32(~0, port_priv->port_base + INT_CLEAR);
574 iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);
575 }
576
577 /**
578 * qc_issue is used to make a command active, once the hardware and S/G tables
579 * have been prepared. IDE BMDMA drivers use the helper function
580 * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
581 * drivers roll their own ->qc_issue implementation, using this as the
582 * "issue new ATA command to hardware" hook.
583 * @param qc the queued command to issue
584 */
585 static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)
586 {
587 struct sata_oxnas_port_priv *pd = qc->ap->private_data;
588 struct sata_oxnas_host_priv *hd = qc->ap->host->private_data;
589
590 void __iomem *port_base = pd->port_base;
591 void __iomem *core_base = pd->core_base;
592 int port_no = qc->ap->port_no;
593 int no_microcode = (hd->current_ucode == UNKNOWN_MODE);
594 u32 reg;
595
596 /* check the core is idle */
597 if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {
598 int count = 0;
599
600 DPRINTK("core busy for a command on port %d\n",
601 qc->ap->port_no);
602 do {
603 mdelay(1);
604 if (++count > 100) {
605 DPRINTK("core busy for a command on port %d\n",
606 qc->ap->port_no);
607 /* CrazyDumpDebug(); */
608 sata_oxnas_cleanup(qc->ap->host);
609 }
610 } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);
611 }
612
613 /* enable passing of error signals to DMA sub-core by clearing the
614 * appropriate bit */
615 reg = ioread32(core_base + DATA_PLANE_CTRL);
616 if (no_microcode)
617 reg |= (DPC_ERROR_MASK_BIT | (DPC_ERROR_MASK_BIT << 1));
618 reg &= ~(DPC_ERROR_MASK_BIT << port_no);
619 iowrite32(reg, core_base + DATA_PLANE_CTRL);
620
621 /* Disable all interrupts for ports and RAID controller */
622 iowrite32(~0, port_base + INT_DISABLE);
623
624 /* Disable all interrupts for core */
625 iowrite32(~0, core_base + CORE_INT_DISABLE);
626 wmb();
627
628 /* Load the command settings into the orb registers */
629 sata_oxnas_tf_load(qc->ap, &qc->tf);
630
631 /* both pio and dma commands use dma */
632 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
633 /* Start the DMA */
634 iowrite32(SGDMA_CONTROL_GO, pd->sgdma_base + SGDMA_CONTROL);
635 wmb();
636 }
637
638 /* enable End of command interrupt */
639 iowrite32(INT_WANT, port_base + INT_ENABLE);
640 iowrite32(COREINT_END, core_base + CORE_INT_ENABLE);
641 wmb();
642
643 /* Start the command */
644 reg = ioread32(port_base + SATA_COMMAND);
645 reg &= ~SATA_OPCODE_MASK;
646 reg |= CMD_WRITE_TO_ORB_REGS;
647 iowrite32(reg , port_base + SATA_COMMAND);
648 wmb();
649
650 return 0;
651 }
652
653 /**
654 * Will schedule the libATA error handler on the premise that there has
655 * been a hotplug event on the port specified
656 */
657 void sata_oxnas_checkforhotplug(struct ata_port *ap)
658 {
659 DPRINTK("ENTER\n");
660
661 ata_ehi_hotplugged(&ap->link.eh_info);
662 ata_port_freeze(ap);
663 }
664
665
666 /**************************************************************************/
667 /* Locking */
668 /**************************************************************************/
669 /**
670 * The underlying function that controls access to the sata core
671 *
672 * @return non-zero indicates that you have acquired exclusive access to the
673 * sata core.
674 */
675 static int __acquire_sata_core(
676 struct ata_host *ah,
677 int port_no,
678 oxnas_sata_isr_callback_t callback,
679 void *arg,
680 int may_sleep,
681 int timeout_jiffies,
682 int hw_access,
683 void *uid,
684 int locker_type)
685 {
686 unsigned long end = jiffies + timeout_jiffies;
687 int acquired = 0;
688 unsigned long flags;
689 int timed_out = 0;
690 struct sata_oxnas_host_priv *hd;
691
692 DEFINE_WAIT(wait);
693
694 if (!ah)
695 return acquired;
696
697 hd = ah->private_data;
698
699 spin_lock_irqsave(&hd->core_lock, flags);
700
701 DPRINTK("Entered uid %p, port %d, h/w count %d, d count %d, "
702 "callback %p, hw_access %d, core_locked %d, "
703 "reentrant_port_no %d, isr_callback %p\n",
704 uid, port_no, hd->hw_lock_count, hd->direct_lock_count,
705 callback, hw_access, hd->core_locked, hd->reentrant_port_no,
706 hd->isr_callback);
707
708 while (!timed_out) {
709 if (hd->core_locked ||
710 (!hw_access && hd->scsi_nonblocking_attempts)) {
711 /* Can only allow access if from SCSI/SATA stack and if
712 * reentrant access is allowed and this access is to the
713 * same port for which the lock is current held
714 */
715 if (hw_access && (port_no == hd->reentrant_port_no)) {
716 BUG_ON(!hd->hw_lock_count);
717 ++(hd->hw_lock_count);
718
719 DPRINTK("Allow SCSI/SATA re-entrant access to "
720 "uid %p port %d\n", uid, port_no);
721 acquired = 1;
722 break;
723 } else if (!hw_access) {
724 if ((locker_type == SATA_READER) &&
725 (hd->current_locker_type == SATA_READER)) {
726 WARN(1,
727 "Already locked by reader, "
728 "uid %p, locker_uid %p, "
729 "port %d, h/w count %d, "
730 "d count %d, hw_access %d\n",
731 uid, hd->locker_uid, port_no,
732 hd->hw_lock_count,
733 hd->direct_lock_count,
734 hw_access);
735 goto check_uid;
736 }
737
738 if ((locker_type != SATA_READER) &&
739 (locker_type != SATA_WRITER)) {
740 goto wait_for_lock;
741 }
742
743 check_uid:
744 WARN(uid == hd->locker_uid, "Attempt to lock "
745 "by locker type %d uid %p, already "
746 "locked by locker type %d with "
747 "locker_uid %p, port %d, "
748 "h/w count %d, d count %d, "
749 "hw_access %d\n", locker_type, uid,
750 hd->current_locker_type,
751 hd->locker_uid, port_no,
752 hd->hw_lock_count,
753 hd->direct_lock_count, hw_access);
754 }
755 } else {
756 WARN(hd->hw_lock_count || hd->direct_lock_count,
757 "Core unlocked but counts non-zero: uid %p, "
758 "locker_uid %p, port %d, h/w count %d, "
759 "d count %d, hw_access %d\n", uid,
760 hd->locker_uid, port_no, hd->hw_lock_count,
761 hd->direct_lock_count, hw_access);
762
763 BUG_ON(hd->current_locker_type != SATA_UNLOCKED);
764
765 WARN(hd->locker_uid, "Attempt to lock uid %p when "
766 "locker_uid %p is non-zero, port %d, "
767 "h/w count %d, d count %d, hw_access %d\n",
768 uid, hd->locker_uid, port_no, hd->hw_lock_count,
769 hd->direct_lock_count, hw_access);
770
771 if (!hw_access) {
772 /* Direct access attempting to acquire
773 * non-contented lock
774 */
775 /* Must have callback for direct access */
776 BUG_ON(!callback);
777 /* Sanity check lock state */
778 BUG_ON(hd->reentrant_port_no != -1);
779
780 hd->isr_callback = callback;
781 hd->isr_arg = arg;
782 ++(hd->direct_lock_count);
783
784 hd->current_locker_type = locker_type;
785 } else {
786 /* SCSI/SATA attempting to acquire
787 * non-contented lock
788 */
789 /* No callbacks for SCSI/SATA access */
790 BUG_ON(callback);
791 /* No callback args for SCSI/SATA access */
792 BUG_ON(arg);
793
794 /* Sanity check lock state */
795 BUG_ON(hd->isr_callback);
796 BUG_ON(hd->isr_arg);
797
798 ++(hd->hw_lock_count);
799 hd->reentrant_port_no = port_no;
800
801 hd->current_locker_type = SATA_SCSI_STACK;
802 }
803
804 hd->core_locked = 1;
805 hd->locker_uid = uid;
806 acquired = 1;
807 break;
808 }
809
810 wait_for_lock:
811 if (!may_sleep) {
812 DPRINTK("Denying for uid %p locker_type %d, "
813 "hw_access %d, port %d, current_locker_type %d as "
814 "cannot sleep\n", uid, locker_type, hw_access, port_no,
815 hd->current_locker_type);
816
817 if (hw_access)
818 ++(hd->scsi_nonblocking_attempts);
819
820 break;
821 }
822
823 /* Core is locked and we're allowed to sleep, so wait to be
824 * awoken when the core is unlocked
825 */
826 for (;;) {
827 prepare_to_wait(hw_access ? &hd->scsi_wait_queue :
828 &hd->fast_wait_queue,
829 &wait, TASK_UNINTERRUPTIBLE);
830 if (!hd->core_locked &&
831 !(!hw_access && hd->scsi_nonblocking_attempts)) {
832 /* We're going to use variables that will have
833 * been changed by the waker prior to clearing
834 * core_locked so we need to ensure we see
835 * changes to all those variables
836 */
837 smp_rmb();
838 break;
839 }
840 if (time_after(jiffies, end)) {
841 printk(KERN_WARNING "__acquire_sata_core() "
842 "uid %p failing for port %d timed out, "
843 "locker_uid %p, h/w count %d, "
844 "d count %d, callback %p, hw_access %d, "
845 "core_locked %d, reentrant_port_no %d, "
846 "isr_callback %p, isr_arg %p\n", uid,
847 port_no, hd->locker_uid,
848 hd->hw_lock_count,
849 hd->direct_lock_count, callback,
850 hw_access, hd->core_locked,
851 hd->reentrant_port_no, hd->isr_callback,
852 hd->isr_arg);
853 timed_out = 1;
854 break;
855 }
856 spin_unlock_irqrestore(&hd->core_lock, flags);
857 if (!schedule_timeout(4*HZ)) {
858 printk(KERN_INFO "__acquire_sata_core() uid %p, "
859 "locker_uid %p, timed-out of "
860 "schedule(), checking overall timeout\n",
861 uid, hd->locker_uid);
862 }
863 spin_lock_irqsave(&hd->core_lock, flags);
864 }
865 finish_wait(hw_access ? &hd->scsi_wait_queue :
866 &hd->fast_wait_queue, &wait);
867 }
868
869 if (hw_access && acquired) {
870 if (hd->scsi_nonblocking_attempts)
871 hd->scsi_nonblocking_attempts = 0;
872
873 /* Wake any other SCSI/SATA waiters so they can get reentrant
874 * access to the same port if appropriate. This is because if
875 * the SATA core is locked by fast access, or SCSI/SATA access
876 * to other port, then can have >1 SCSI/SATA waiters on the wait
877 * list so want to give reentrant accessors a chance to get
878 * access ASAP
879 */
880 if (!list_empty(&hd->scsi_wait_queue.head))
881 wake_up(&hd->scsi_wait_queue);
882 }
883
884 DPRINTK("Leaving uid %p with acquired = %d, port %d, callback %p\n",
885 uid, acquired, port_no, callback);
886
887 spin_unlock_irqrestore(&hd->core_lock, flags);
888
889 return acquired;
890 }
891
892 int sata_core_has_fast_waiters(struct ata_host *ah)
893 {
894 int has_waiters;
895 unsigned long flags;
896 struct sata_oxnas_host_priv *hd = ah->private_data;
897
898 spin_lock_irqsave(&hd->core_lock, flags);
899 has_waiters = !list_empty(&hd->fast_wait_queue.head);
900 spin_unlock_irqrestore(&hd->core_lock, flags);
901
902 return has_waiters;
903 }
904 EXPORT_SYMBOL(sata_core_has_fast_waiters);
905
906 int sata_core_has_scsi_waiters(struct ata_host *ah)
907 {
908 int has_waiters;
909 unsigned long flags;
910 struct sata_oxnas_host_priv *hd = ah->private_data;
911
912 spin_lock_irqsave(&hd->core_lock, flags);
913 has_waiters = hd->scsi_nonblocking_attempts ||
914 !list_empty(&hd->scsi_wait_queue.head);
915 spin_unlock_irqrestore(&hd->core_lock, flags);
916
917 return has_waiters;
918 }
919 EXPORT_SYMBOL(sata_core_has_scsi_waiters);
920
921 /*
922 * ata_port operation to gain ownership of the SATA hardware prior to issuing
923 * a command against a SATA host. Allows any number of users of the port against
924 * which the lock was first acquired, thus enforcing that only one SATA core
925 * port may be operated on at once.
926 */
927 static int sata_oxnas_acquire_hw(
928 struct ata_port *ap,
929 int may_sleep,
930 int timeout_jiffies)
931 {
932 return __acquire_sata_core(ap->host, ap->port_no, NULL, 0, may_sleep,
933 timeout_jiffies, 1, (void *)HW_LOCKER_UID,
934 SATA_SCSI_STACK);
935 }
936
937 /*
938 * operation to release ownership of the SATA hardware
939 */
940 static void sata_oxnas_release_hw(struct ata_port *ap)
941 {
942 unsigned long flags;
943 int released = 0;
944 struct sata_oxnas_host_priv *hd = ap->host->private_data;
945
946 spin_lock_irqsave(&hd->core_lock, flags);
947
948 DPRINTK("Entered port_no = %d, h/w count %d, d count %d, "
949 "core locked = %d, reentrant_port_no = %d, isr_callback %p\n",
950 ap->port_no, hd->hw_lock_count, hd->direct_lock_count,
951 hd->core_locked, hd->reentrant_port_no, hd->isr_callback);
952
953 if (!hd->core_locked) {
954 /* Nobody holds the SATA lock */
955 printk(KERN_WARNING "Nobody holds SATA lock, port_no %d\n",
956 ap->port_no);
957 released = 1;
958 } else if (!hd->hw_lock_count) {
959 /* SCSI/SATA has released without holding the lock */
960 printk(KERN_WARNING "SCSI/SATA does not hold SATA lock, "
961 "port_no %d\n", ap->port_no);
962 } else {
963 /* Trap incorrect usage */
964 BUG_ON(hd->reentrant_port_no == -1);
965 BUG_ON(ap->port_no != hd->reentrant_port_no);
966 BUG_ON(hd->direct_lock_count);
967 BUG_ON(hd->current_locker_type != SATA_SCSI_STACK);
968
969 WARN(!hd->locker_uid || (hd->locker_uid != HW_LOCKER_UID),
970 "Invalid locker uid %p, h/w count %d, d count %d, "
971 "reentrant_port_no %d, core_locked %d, "
972 "isr_callback %p\n", hd->locker_uid, hd->hw_lock_count,
973 hd->direct_lock_count, hd->reentrant_port_no,
974 hd->core_locked, hd->isr_callback);
975
976 if (--(hd->hw_lock_count)) {
977 DPRINTK("Still nested port_no %d\n", ap->port_no);
978 } else {
979 DPRINTK("Release port_no %d\n", ap->port_no);
980 hd->reentrant_port_no = -1;
981 hd->isr_callback = NULL;
982 hd->current_locker_type = SATA_UNLOCKED;
983 hd->locker_uid = 0;
984 hd->core_locked = 0;
985 released = 1;
986 wake_up(!list_empty(&hd->scsi_wait_queue.head) ?
987 &hd->scsi_wait_queue :
988 &hd->fast_wait_queue);
989 }
990 }
991
992 DPRINTK("Leaving, port_no %d, count %d\n", ap->port_no,
993 hd->hw_lock_count);
994
995 spin_unlock_irqrestore(&hd->core_lock, flags);
996
997 /* CONFIG_SATA_OX820_DIRECT_HWRAID */
998 /* if (released)
999 ox820hwraid_restart_queue();
1000 } */
1001 }
1002
1003 static inline int sata_oxnas_is_host_frozen(struct ata_host *ah)
1004 {
1005 struct sata_oxnas_host_priv *hd = ah->private_data;
1006
1007 smp_rmb();
1008 return hd->port_in_eh || hd->port_frozen;
1009 }
1010
1011
1012 static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)
1013 {
1014 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1015
1016 return (ioread32(hd->port_base + SATA_COMMAND) & CMD_CORE_BUSY) ||
1017 (hd->n_ports > 1 &&
1018 (ioread32(hd->port_base + PORT_SIZE + SATA_COMMAND) &
1019 CMD_CORE_BUSY));
1020 }
1021
1022 static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)
1023 {
1024 struct sata_oxnas_port_priv *pd = ap->private_data;
1025
1026 return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;
1027 }
1028
1029
1030 /**
1031 * Turns on the cores clock and resets it
1032 */
1033 static void sata_oxnas_reset_core(struct ata_host *ah)
1034 {
1035 struct sata_oxnas_host_priv *host_priv = ah->private_data;
1036 int n;
1037
1038 DPRINTK("ENTER\n");
1039 clk_prepare_enable(host_priv->clk);
1040
1041 reset_control_assert(host_priv->rst_sata);
1042 reset_control_assert(host_priv->rst_link);
1043 reset_control_assert(host_priv->rst_phy);
1044
1045 udelay(50);
1046
1047 /* un-reset the PHY, then Link and Controller */
1048 reset_control_deassert(host_priv->rst_phy);
1049 udelay(50);
1050
1051 reset_control_deassert(host_priv->rst_sata);
1052 reset_control_deassert(host_priv->rst_link);
1053 udelay(50);
1054
1055 workaround5458(ah);
1056 /* tune for sata compatibility */
1057 sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);
1058
1059 for (n = 0; n < host_priv->n_ports; n++) {
1060 /* each port in turn */
1061 sata_oxnas_link_write(ah->ports[n], 0x70, 0x55629);
1062 }
1063 udelay(50);
1064 }
1065
1066
1067 /**
1068 * Called after an identify device command has worked out what kind of device
1069 * is on the port
1070 *
1071 * @param port The port to configure
1072 * @param pdev The hardware associated with controlling the port
1073 */
1074 static void sata_oxnas_dev_config(struct ata_device *pdev)
1075 {
1076 struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;
1077 void __iomem *port_base = pd->port_base;
1078 u32 reg;
1079
1080 DPRINTK("ENTER\n");
1081 /* Set the bits to put the port into 28 or 48-bit node */
1082 reg = ioread32(port_base + DRIVE_CONTROL);
1083 reg &= ~3;
1084 reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;
1085 iowrite32(reg, port_base + DRIVE_CONTROL);
1086
1087 /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
1088 if (pdev->flags & ATA_DFLAG_LBA48) {
1089 reg = ioread32(port_base + PORT_CONTROL);
1090 reg |= 2;
1091 iowrite32(reg, port_base + PORT_CONTROL);
1092 }
1093 }
1094 /**
1095 * called to write a taskfile into the ORB registers
1096 * @param ap hardware with the registers in
1097 * @param tf taskfile to write to the registers
1098 */
1099 static void sata_oxnas_tf_load(struct ata_port *ap,
1100 const struct ata_taskfile *tf)
1101 {
1102 u32 count = 0;
1103 u32 Orb1 = 0;
1104 u32 Orb2 = 0;
1105 u32 Orb3 = 0;
1106 u32 Orb4 = 0;
1107 u32 Command_Reg;
1108
1109 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1110 void __iomem *port_base = port_priv->port_base;
1111 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
1112
1113 /* wait a maximum of 10ms for the core to be idle */
1114 do {
1115 Command_Reg = ioread32(port_base + SATA_COMMAND);
1116 if (!(Command_Reg & CMD_CORE_BUSY))
1117 break;
1118 count++;
1119 udelay(50);
1120 } while (count < 200);
1121
1122 /* check if the ctl register has interrupts disabled or enabled and
1123 * modify the interrupt enable registers on the ata core as required */
1124 if (tf->ctl & ATA_NIEN) {
1125 /* interrupts disabled */
1126 u32 mask = (COREINT_END << ap->port_no);
1127
1128 iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);
1129 sata_oxnas_irq_clear(ap);
1130 } else {
1131 sata_oxnas_irq_on(ap);
1132 }
1133
1134 Orb2 |= (tf->command) << 24;
1135
1136 /* write 48 or 28 bit tf parameters */
1137 if (is_addr) {
1138 /* set LBA bit as it's an address */
1139 Orb1 |= (tf->device & ATA_LBA) << 24;
1140
1141 if (tf->flags & ATA_TFLAG_LBA48) {
1142 Orb1 |= ATA_LBA << 24;
1143 Orb2 |= (tf->hob_nsect) << 8;
1144 Orb3 |= (tf->hob_lbal) << 24;
1145 Orb4 |= (tf->hob_lbam) << 0;
1146 Orb4 |= (tf->hob_lbah) << 8;
1147 Orb4 |= (tf->hob_feature) << 16;
1148 } else {
1149 Orb3 |= (tf->device & 0xf) << 24;
1150 }
1151
1152 /* write 28-bit lba */
1153 Orb2 |= (tf->nsect) << 0;
1154 Orb2 |= (tf->feature) << 16;
1155 Orb3 |= (tf->lbal) << 0;
1156 Orb3 |= (tf->lbam) << 8;
1157 Orb3 |= (tf->lbah) << 16;
1158 Orb4 |= (tf->ctl) << 24;
1159 }
1160
1161 if (tf->flags & ATA_TFLAG_DEVICE)
1162 Orb1 |= (tf->device) << 24;
1163
1164 ap->last_ctl = tf->ctl;
1165
1166 /* write values to registers */
1167 iowrite32(Orb1, port_base + ORB1);
1168 iowrite32(Orb2, port_base + ORB2);
1169 iowrite32(Orb3, port_base + ORB3);
1170 iowrite32(Orb4, port_base + ORB4);
1171 }
1172
1173
1174 void sata_oxnas_set_mode(struct ata_host *ah, u32 mode, u32 force)
1175 {
1176 struct sata_oxnas_host_priv *host_priv = ah->private_data;
1177 void __iomem *core_base = host_priv->core_base;
1178
1179 unsigned int *src;
1180 void __iomem *dst;
1181 unsigned int progmicrocode = 0;
1182 unsigned int changeparameters = 0;
1183
1184 u32 previous_mode;
1185
1186 /* these micro-code programs _should_ include the version word */
1187
1188 /* JBOD */
1189 static const unsigned int jbod[] = {
1190 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
1191 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
1192 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
1193 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
1194 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
1195 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
1196 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
1197 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
1198 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
1199 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
1200 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
1201 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1202 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
1203 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
1204 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
1205 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
1206 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
1207 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
1208 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
1209 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
1210 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
1211 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
1212 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
1213 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
1214 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
1215 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
1216 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
1217 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
1218 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
1219 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
1220 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
1221 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
1222 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
1223 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
1224 0x00718908, 0x0208A206, 0x00EE0005, ~0
1225 };
1226
1227 /* Bi-Modal RAID-0/1 */
1228 static const unsigned int raid[] = {
1229 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
1230 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
1231 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
1232 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
1233 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
1234 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
1235 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
1236 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
1237 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
1238 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
1239 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
1240 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
1241 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
1242 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
1243 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
1244 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
1245 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
1246 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
1247 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
1248 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
1249 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
1250 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
1251 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
1252 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
1253 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
1254 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
1255 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
1256 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
1257 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
1258 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
1259 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
1260 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
1261 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
1262 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
1263 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
1264 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
1265 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
1266 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
1267 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
1268 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
1269 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
1270 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
1271 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
1272 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
1273 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
1274 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
1275 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
1276 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
1277 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
1278 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
1279 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
1280 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
1281 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
1282 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
1283 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
1284 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
1285 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
1286 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
1287 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
1288 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
1289 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
1290 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
1291 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
1292 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
1293 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
1294 0x02400000, ~0
1295 };
1296
1297 DPRINTK("ENTER: mode:%d, force:%d\n", mode, force);
1298
1299 if (force)
1300 previous_mode = UNKNOWN_MODE;
1301 else
1302 previous_mode = host_priv->current_ucode;
1303
1304 if (mode == previous_mode)
1305 return;
1306
1307 host_priv->current_ucode = mode;
1308
1309 /* decide what needs to be done using the STD in my logbook */
1310 switch (previous_mode) {
1311 case OXNASSATA_RAID1:
1312 switch (mode) {
1313 case OXNASSATA_RAID0:
1314 changeparameters = 1;
1315 break;
1316 case OXNASSATA_NOTRAID:
1317 changeparameters = 1;
1318 progmicrocode = 1;
1319 break;
1320 }
1321 break;
1322 case OXNASSATA_RAID0:
1323 switch (mode) {
1324 case OXNASSATA_RAID1:
1325 changeparameters = 1;
1326 break;
1327 case OXNASSATA_NOTRAID:
1328 changeparameters = 1;
1329 progmicrocode = 1;
1330 break;
1331 }
1332 break;
1333 case OXNASSATA_NOTRAID:
1334 switch (mode) {
1335 case OXNASSATA_RAID0:
1336 case OXNASSATA_RAID1:
1337 changeparameters = 1;
1338 progmicrocode = 1;
1339 break;
1340 }
1341 break;
1342 case UNKNOWN_MODE:
1343 changeparameters = 1;
1344 progmicrocode = 1;
1345 break;
1346 }
1347
1348 /* no need to reprogram everything if already in the right mode */
1349 if (progmicrocode) {
1350 /* reset micro-code processor */
1351 iowrite32(1, core_base + PROC_RESET);
1352 wmb();
1353
1354 /* select micro-code */
1355 switch (mode) {
1356 case OXNASSATA_RAID1:
1357 case OXNASSATA_RAID0:
1358 VPRINTK("Loading RAID micro-code\n");
1359 src = (unsigned int *)&raid[1];
1360 break;
1361 case OXNASSATA_NOTRAID:
1362 VPRINTK("Loading JBOD micro-code\n");
1363 src = (unsigned int *)&jbod[1];
1364 break;
1365 default:
1366 BUG();
1367 break;
1368 }
1369
1370 /* load micro code */
1371 dst = core_base + UCODE_STORE;
1372 while (*src != ~0) {
1373 iowrite32(*src, dst);
1374 src++;
1375 dst += sizeof(*src);
1376 }
1377 wmb();
1378 }
1379
1380 if (changeparameters) {
1381 u32 reg;
1382 /* set other mode dependent flags */
1383 switch (mode) {
1384 case OXNASSATA_RAID1:
1385 /* clear JBOD mode */
1386 reg = ioread32(core_base + DATA_PLANE_CTRL);
1387 reg |= DPC_JBOD_UCODE;
1388 reg &= ~DPC_FIS_SWCH;
1389 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1390 wmb();
1391
1392 /* set the hardware up for RAID-1 */
1393 iowrite32(0, core_base + RAID_WP_BOT_LOW);
1394 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
1395 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
1396 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
1397 iowrite32(0, core_base + RAID_SIZE_LOW);
1398 iowrite32(0, core_base + RAID_SIZE_HIGH);
1399 wmb();
1400 break;
1401 case OXNASSATA_RAID0:
1402 /* clear JBOD mode */
1403 reg = ioread32(core_base + DATA_PLANE_CTRL);
1404 reg |= DPC_JBOD_UCODE;
1405 reg &= ~DPC_FIS_SWCH;
1406 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1407 wmb();
1408
1409 /* set the hardware up for RAID-1 */
1410 iowrite32(0, core_base + RAID_WP_BOT_LOW);
1411 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
1412 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
1413 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
1414 iowrite32(0xffffffff, core_base + RAID_SIZE_LOW);
1415 iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);
1416 wmb();
1417 break;
1418 case OXNASSATA_NOTRAID:
1419 /* enable jbod mode */
1420 reg = ioread32(core_base + DATA_PLANE_CTRL);
1421 reg &= ~DPC_JBOD_UCODE;
1422 reg &= ~DPC_FIS_SWCH;
1423 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1424 wmb();
1425
1426 /* start micro-code processor*/
1427 iowrite32(1, core_base + PROC_START);
1428 break;
1429 default:
1430 reg = ioread32(core_base + DATA_PLANE_CTRL);
1431 reg |= DPC_JBOD_UCODE;
1432 reg &= ~DPC_FIS_SWCH;
1433 iowrite32(reg, core_base + DATA_PLANE_CTRL);
1434 wmb();
1435 break;
1436 }
1437 }
1438 }
1439
1440 /**
1441 * sends a sync-escape if there is a link present
1442 */
1443 static inline void sata_oxnas_send_sync_escape(struct ata_port *ap)
1444 {
1445 struct sata_oxnas_port_priv *pd = ap->private_data;
1446 u32 reg;
1447
1448 /* read the SSTATUS register and only send a sync escape if there is a
1449 * link active */
1450 if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {
1451 reg = ioread32(pd->port_base + SATA_COMMAND);
1452 reg &= ~SATA_OPCODE_MASK;
1453 reg |= CMD_SYNC_ESCAPE;
1454 iowrite32(reg, pd->port_base + SATA_COMMAND);
1455 }
1456 }
1457
1458 /* clears errors */
1459 static inline void sata_oxnas_clear_CS_error(struct ata_port *ap)
1460 {
1461 struct sata_oxnas_port_priv *pd = ap->private_data;
1462 u32 *base = pd->port_base;
1463 u32 reg;
1464
1465 reg = ioread32(base + SATA_CONTROL);
1466 reg &= SATA_CTL_ERR_MASK;
1467 iowrite32(reg, base + SATA_CONTROL);
1468 }
1469
1470 static inline void sata_oxnas_reset_sgdma(struct ata_port *ap)
1471 {
1472 struct sata_oxnas_port_priv *pd = ap->private_data;
1473
1474 iowrite32(SGDMA_RESETS_CTRL, pd->sgdma_base + SGDMA_RESETS);
1475 }
1476
1477 static inline void sata_oxnas_reset_dma(struct ata_port *ap, int assert)
1478 {
1479 struct sata_oxnas_port_priv *pd = ap->private_data;
1480 u32 reg;
1481
1482 reg = ioread32(pd->dmactl_base + DMA_CONTROL);
1483 if (assert)
1484 reg |= DMA_CONTROL_RESET;
1485 else
1486 reg &= ~DMA_CONTROL_RESET;
1487
1488 iowrite32(reg, pd->dmactl_base + DMA_CONTROL);
1489 };
1490
1491 /**
1492 * Clears the error caused by the core's registers being accessed when the
1493 * core is busy.
1494 */
1495 static inline void sata_oxnas_clear_reg_access_error(struct ata_port *ap)
1496 {
1497 struct sata_oxnas_port_priv *pd = ap->private_data;
1498 u32 *base = pd->port_base;
1499 u32 reg;
1500
1501 reg = ioread32(base + INT_STATUS);
1502
1503 DPRINTK("ENTER\n");
1504 if (reg & INT_REG_ACCESS_ERR) {
1505 DPRINTK("clearing register access error on port %d\n",
1506 ap->port_no);
1507 iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);
1508 }
1509 reg = ioread32(base + INT_STATUS);
1510 if (reg & INT_REG_ACCESS_ERR)
1511 DPRINTK("register access error didn't clear\n");
1512 }
1513
1514 static inline void sata_oxnas_clear_sctl_error(struct ata_port *ap)
1515 {
1516 struct sata_oxnas_port_priv *pd = ap->private_data;
1517 u32 *base = pd->port_base;
1518 u32 reg;
1519
1520 reg = ioread32(base + SATA_CONTROL);
1521 reg |= SCTL_CLR_ERR;
1522 iowrite32(reg, base + SATA_CONTROL);
1523 }
1524
1525 static inline void sata_oxnas_clear_raid_error(struct ata_host *ah)
1526 {
1527 return;
1528 };
1529
1530 /**
1531 * Clean up all the state machines in the sata core.
1532 * @return post cleanup action required
1533 */
1534 static int sata_oxnas_cleanup(struct ata_host *ah)
1535 {
1536 struct sata_oxnas_host_priv *hd = ah->private_data;
1537 int actions_required = 0;
1538 int n;
1539
1540 printk(KERN_INFO "sata_oxnas: resetting SATA core\n");
1541 /* core not recovering, reset it */
1542 mdelay(5);
1543 sata_oxnas_reset_core(ah);
1544 mdelay(5);
1545 actions_required |= OXNAS_SATA_REINIT;
1546 /* Perform any SATA core re-initialisation after reset post reset init
1547 * needs to be called for both ports as there's one reset for both
1548 * ports */
1549 for (n = 0; n < hd->n_ports; n++)
1550 sata_oxnas_post_reset_init(ah->ports[n]);
1551
1552
1553 return actions_required;
1554 }
1555
1556 /**
1557 * ata_qc_new - Request an available ATA command, for queueing
1558 * @ap: Port associated with device @dev
1559 * @return non zero will refuse a new command, zero will may grant on subject
1560 * to conditions elsewhere.
1561 *
1562 */
1563 static int sata_oxnas_qc_new(struct ata_port *ap)
1564 {
1565 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1566
1567 DPRINTK("port %d\n", ap->port_no);
1568 smp_rmb();
1569 if (hd->port_frozen || hd->port_in_eh)
1570 return 1;
1571 else
1572 return !sata_oxnas_acquire_hw(ap, 0, 0);
1573 }
1574
1575 /**
1576 * releases the lock on the port the command used
1577 */
1578 static void sata_oxnas_qc_free(struct ata_queued_cmd *qc)
1579 {
1580 DPRINTK("\n");
1581 sata_oxnas_release_hw(qc->ap);
1582 }
1583
1584 static void sata_oxnas_freeze(struct ata_port *ap)
1585 {
1586 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1587
1588 DPRINTK("\n");
1589 hd->port_frozen |= BIT(ap->port_no);
1590 smp_wmb();
1591 }
1592
1593 static void sata_oxnas_thaw(struct ata_port *ap)
1594 {
1595 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1596
1597 DPRINTK("\n");
1598 hd->port_frozen &= ~BIT(ap->port_no);
1599 smp_wmb();
1600 }
1601
1602 void sata_oxnas_freeze_host(struct ata_port *ap)
1603 {
1604 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1605
1606 DPRINTK("ENTER\n");
1607 hd->port_in_eh |= BIT(ap->port_no);
1608 smp_wmb();
1609 }
1610
1611 void sata_oxnas_thaw_host(struct ata_port *ap)
1612 {
1613 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1614
1615 DPRINTK("ENTER\n");
1616 hd->port_in_eh &= ~BIT(ap->port_no);
1617 smp_wmb();
1618 }
1619
1620 static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)
1621 {
1622 DPRINTK("ENTER\n");
1623 /* If the core is busy here, make it idle */
1624 if (qc->flags & ATA_QCFLAG_FAILED)
1625 sata_oxnas_cleanup(qc->ap->host);
1626 }
1627
1628
1629 /**
1630 * turn on the interrupts
1631 *
1632 * @param ap Hardware with the registers in
1633 */
1634 static void sata_oxnas_irq_on(struct ata_port *ap)
1635 {
1636 struct sata_oxnas_port_priv *pd = ap->private_data;
1637 u32 mask = (COREINT_END << ap->port_no);
1638
1639 /* Clear pending interrupts */
1640 iowrite32(~0, pd->port_base + INT_CLEAR);
1641 iowrite32(mask, pd->core_base + CORE_INT_STATUS);
1642 wmb();
1643
1644 /* enable End of command interrupt */
1645 iowrite32(INT_WANT, pd->port_base + INT_ENABLE);
1646 iowrite32(mask, pd->core_base + CORE_INT_ENABLE);
1647 }
1648
1649
1650 /** @return true if the port has a cable connected */
1651 int sata_oxnas_check_link(struct ata_port *ap)
1652 {
1653 int reg;
1654
1655 sata_oxnas_scr_read_port(ap, SCR_STATUS, &reg);
1656 /* Check for the cable present indicated by SCR status bit-0 set */
1657 return reg & 0x1;
1658 }
1659
1660 /**
1661 * ata_std_postreset - standard postreset callback
1662 * @link: the target ata_link
1663 * @classes: classes of attached devices
1664 *
1665 * This function is invoked after a successful reset. Note that
1666 * the device might have been reset more than once using
1667 * different reset methods before postreset is invoked.
1668 *
1669 * LOCKING:
1670 * Kernel thread context (may sleep)
1671 */
1672 static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)
1673 {
1674 struct ata_port *ap = link->ap;
1675 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1676
1677 unsigned int dev;
1678
1679 DPRINTK("ENTER\n");
1680 ata_std_postreset(link, classes);
1681
1682 /* turn on phy error detection by removing the masks */
1683 sata_oxnas_link_write(ap->host->ports[0], 0x0c, 0x30003);
1684 if (hd->n_ports > 1)
1685 sata_oxnas_link_write(ap->host->ports[1], 0x0c, 0x30003);
1686
1687 /* bail out if no device is present */
1688 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1689 DPRINTK("EXIT, no device\n");
1690 return;
1691 }
1692
1693 /* go through all the devices and configure them */
1694 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1695 if (ap->link.device[dev].class == ATA_DEV_ATA)
1696 sata_oxnas_dev_config(&(ap->link.device[dev]));
1697 }
1698
1699 DPRINTK("EXIT\n");
1700 }
1701
1702 /**
1703 * Called to read the hardware registers / DMA buffers, to
1704 * obtain the current set of taskfile register values.
1705 * @param ap hardware with the registers in
1706 * @param tf taskfile to read the registers into
1707 */
1708 static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1709 {
1710 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1711 void __iomem *port_base = port_priv->port_base;
1712 /* read the orb registers */
1713 u32 Orb1 = ioread32(port_base + ORB1);
1714 u32 Orb2 = ioread32(port_base + ORB2);
1715 u32 Orb3 = ioread32(port_base + ORB3);
1716 u32 Orb4 = ioread32(port_base + ORB4);
1717
1718 /* read common 28/48 bit tf parameters */
1719 tf->device = (Orb1 >> 24);
1720 tf->nsect = (Orb2 >> 0);
1721 tf->feature = (Orb2 >> 16);
1722 tf->command = sata_oxnas_check_status(ap);
1723
1724 /* read 48 or 28 bit tf parameters */
1725 if (tf->flags & ATA_TFLAG_LBA48) {
1726 tf->hob_nsect = (Orb2 >> 8);
1727 tf->lbal = (Orb3 >> 0);
1728 tf->lbam = (Orb3 >> 8);
1729 tf->lbah = (Orb3 >> 16);
1730 tf->hob_lbal = (Orb3 >> 24);
1731 tf->hob_lbam = (Orb4 >> 0);
1732 tf->hob_lbah = (Orb4 >> 8);
1733 /* feature ext and control are write only */
1734 } else {
1735 /* read 28-bit lba */
1736 tf->lbal = (Orb3 >> 0);
1737 tf->lbam = (Orb3 >> 8);
1738 tf->lbah = (Orb3 >> 16);
1739 }
1740 }
1741
1742 /**
1743 * Read a result task-file from the sata core registers.
1744 */
1745 static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)
1746 {
1747 /* Read the most recently received FIS from the SATA core ORB registers
1748 and convert to an ATA taskfile */
1749 sata_oxnas_tf_read(qc->ap, &qc->result_tf);
1750 return true;
1751 }
1752
1753 /**
1754 * Reads the Status ATA shadow register from hardware.
1755 *
1756 * @return The status register
1757 */
1758 static u8 sata_oxnas_check_status(struct ata_port *ap)
1759 {
1760 u32 Reg;
1761 u8 status;
1762 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1763 void __iomem *port_base = port_priv->port_base;
1764
1765 /* read byte 3 of Orb2 register */
1766 status = ioread32(port_base + ORB2) >> 24;
1767
1768 /* check for the drive going missing indicated by SCR status bits
1769 * 0-3 = 0 */
1770 sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);
1771
1772 if (!(Reg & 0x1)) {
1773 status |= ATA_DF;
1774 status |= ATA_ERR;
1775 }
1776
1777 return status;
1778 }
1779
1780 static inline void sata_oxnas_reset_ucode(struct ata_host *ah, int force,
1781 int no_microcode)
1782 {
1783 struct sata_oxnas_host_priv *hd = ah->private_data;
1784
1785 DPRINTK("ENTER\n");
1786 if (no_microcode) {
1787 u32 reg;
1788
1789 sata_oxnas_set_mode(ah, UNKNOWN_MODE, force);
1790 reg = ioread32(hd->core_base + DEVICE_CONTROL);
1791 reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;
1792 iowrite32(reg, hd->core_base + DEVICE_CONTROL);
1793 } else {
1794 /* JBOD uCode */
1795 sata_oxnas_set_mode(ah, OXNASSATA_NOTRAID, force);
1796 /* Turn the work around off as it may have been left on by any
1797 * HW-RAID code that we've been working with */
1798 iowrite32(0x0, hd->core_base + PORT_ERROR_MASK);
1799 }
1800 }
1801
1802 /**
1803 * Prepare as much as possible for a command without involving anything that is
1804 * shared between ports.
1805 */
1806 static enum ata_completion_errors sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
1807 {
1808 struct sata_oxnas_port_priv *pd;
1809 int port_no = qc->ap->port_no;
1810
1811 /* if the port's not connected, complete now with an error */
1812 if (!sata_oxnas_check_link(qc->ap)) {
1813 ata_port_err(qc->ap,
1814 "port %d not connected completing with error\n",
1815 port_no);
1816 qc->err_mask |= AC_ERR_ATA_BUS;
1817 ata_qc_complete(qc);
1818 }
1819
1820 sata_oxnas_reset_ucode(qc->ap->host, 0, 0);
1821
1822 /* both pio and dma commands use dma */
1823 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
1824
1825 /* program the scatterlist into the prd table */
1826 ata_bmdma_qc_prep(qc);
1827
1828 /* point the sgdma controller at the dma request structure */
1829 pd = qc->ap->private_data;
1830
1831 iowrite32(pd->sgdma_request_pa,
1832 pd->sgdma_base + SGDMA_REQUESTPTR);
1833
1834 /* setup the request table */
1835 if (port_no == 0) {
1836 pd->sgdma_request->control =
1837 (qc->dma_dir == DMA_FROM_DEVICE) ?
1838 SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;
1839 } else {
1840 pd->sgdma_request->control =
1841 (qc->dma_dir == DMA_FROM_DEVICE) ?
1842 SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;
1843 }
1844 pd->sgdma_request->qualifier = SGDMA_REQQUAL;
1845 pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;
1846 pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;
1847 smp_wmb();
1848
1849 /* tell it to wait */
1850 iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
1851 }
1852
1853 return AC_ERR_OK;
1854 }
1855
1856 static int sata_oxnas_port_start(struct ata_port *ap)
1857 {
1858 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1859 struct device *dev = ap->host->dev;
1860 struct sata_oxnas_port_priv *pp;
1861 void *mem;
1862 dma_addr_t mem_dma;
1863
1864 DPRINTK("ENTER\n");
1865
1866 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
1867 if (!pp)
1868 return -ENOMEM;
1869
1870 pp->port_base = host_priv->port_base +
1871 (ap->port_no ? PORT_SIZE : 0);
1872 pp->dmactl_base = host_priv->dmactl_base +
1873 (ap->port_no ? DMA_CORESIZE : 0);
1874 pp->sgdma_base = host_priv->sgdma_base +
1875 (ap->port_no ? SGDMA_CORESIZE : 0);
1876 pp->core_base = host_priv->core_base;
1877
1878 /* preallocated */
1879 if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * host_priv->n_ports) {
1880 DPRINTK("using preallocated DMA\n");
1881 mem_dma = host_priv->dma_base +
1882 (ap->port_no ? SATA_OXNAS_DMA_SIZE : 0);
1883 mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);
1884 } else {
1885 mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,
1886 GFP_KERNEL);
1887 }
1888 if (!mem)
1889 goto err_ret;
1890
1891 pp->sgdma_request_pa = mem_dma;
1892 pp->sgdma_request = mem;
1893
1894 ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);
1895 ap->bmdma_prd = mem + sizeof(struct sgdma_request);
1896
1897 ap->private_data = pp;
1898
1899 sata_oxnas_post_reset_init(ap);
1900
1901 return 0;
1902
1903 err_ret:
1904 kfree(pp);
1905 return -ENOMEM;
1906
1907 }
1908
1909 static void sata_oxnas_port_stop(struct ata_port *ap)
1910 {
1911 struct device *dev = ap->host->dev;
1912 struct sata_oxnas_port_priv *pp = ap->private_data;
1913 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1914
1915 DPRINTK("ENTER\n");
1916 ap->private_data = NULL;
1917 if (host_priv->dma_size) {
1918 iounmap(pp->sgdma_request);
1919 } else {
1920 dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,
1921 pp->sgdma_request, pp->sgdma_request_pa);
1922 }
1923
1924 kfree(pp);
1925 }
1926
1927
1928 static void sata_oxnas_post_reset_init(struct ata_port *ap)
1929 {
1930 uint dev;
1931
1932 /* force to load u-code only once after reset */
1933 sata_oxnas_reset_ucode(ap->host, !ap->port_no, 0);
1934
1935 /* turn on phy error detection by removing the masks */
1936 sata_oxnas_link_write(ap, 0x0C, 0x30003);
1937
1938 /* enable hotplug event detection */
1939 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1940 sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);
1941 sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));
1942
1943 /* enable interrupts for ports */
1944 sata_oxnas_irq_on(ap);
1945
1946 /* go through all the devices and configure them */
1947 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1948 if (ap->link.device[dev].class == ATA_DEV_ATA) {
1949 sata_std_hardreset(&ap->link, NULL, jiffies + HZ);
1950 sata_oxnas_dev_config(&(ap->link.device[dev]));
1951 }
1952 }
1953
1954 /* clean up any remaining errors */
1955 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1956 VPRINTK("done\n");
1957 }
1958
1959 /**
1960 * host_stop() is called when the rmmod or hot unplug process begins. The
1961 * hook must stop all hardware interrupts, DMA engines, etc.
1962 *
1963 * @param ap hardware with the registers in
1964 */
1965 static void sata_oxnas_host_stop(struct ata_host *host_set)
1966 {
1967 DPRINTK("\n");
1968 }
1969
1970
1971 #define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
1972 static void sata_oxnas_error_handler(struct ata_port *ap)
1973 {
1974 DPRINTK("Enter port_no %d\n", ap->port_no);
1975 sata_oxnas_freeze_host(ap);
1976
1977 /* If the core is busy here, make it idle */
1978 sata_oxnas_cleanup(ap->host);
1979
1980 ata_std_error_handler(ap);
1981
1982 sata_oxnas_thaw_host(ap);
1983 }
1984
1985 static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
1986 unsigned long deadline)
1987 {
1988 struct ata_port *ap = link->ap;
1989 struct sata_oxnas_port_priv *pd = ap->private_data;
1990 void __iomem *port_base = pd->port_base;
1991 int rc;
1992
1993 struct ata_taskfile tf;
1994 u32 Command_Reg;
1995
1996 DPRINTK("ENTER\n");
1997
1998 port_base = pd->port_base;
1999
2000 if (ata_link_offline(link)) {
2001 DPRINTK("PHY reports no device\n");
2002 *class = ATA_DEV_NONE;
2003 goto out;
2004 }
2005
2006 /* write value to register */
2007 iowrite32(0, port_base + ORB1);
2008 iowrite32(0, port_base + ORB2);
2009 iowrite32(0, port_base + ORB3);
2010 iowrite32((ap->ctl) << 24, port_base + ORB4);
2011
2012 /* command the core to send a control FIS */
2013 Command_Reg = ioread32(port_base + SATA_COMMAND);
2014 Command_Reg &= ~SATA_OPCODE_MASK;
2015 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
2016 iowrite32(Command_Reg, port_base + SATA_COMMAND);
2017 udelay(20); /* FIXME: flush */
2018
2019 /* write value to register */
2020 iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);
2021
2022 /* command the core to send a control FIS */
2023 Command_Reg &= ~SATA_OPCODE_MASK;
2024 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
2025 iowrite32(Command_Reg, port_base + SATA_COMMAND);
2026 udelay(20); /* FIXME: flush */
2027
2028 /* write value to register */
2029 iowrite32((ap->ctl) << 24, port_base + ORB4);
2030
2031 /* command the core to send a control FIS */
2032 Command_Reg &= ~SATA_OPCODE_MASK;
2033 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
2034 iowrite32(Command_Reg, port_base + SATA_COMMAND);
2035
2036 msleep(150);
2037
2038 rc = ata_sff_wait_ready(link, deadline);
2039
2040 /* if link is occupied, -ENODEV too is an error */
2041 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2042 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
2043 return rc;
2044 }
2045
2046 /* determine by signature whether we have ATA or ATAPI devices */
2047 sata_oxnas_tf_read(ap, &tf);
2048 *class = ata_dev_classify(&tf);
2049
2050 if (*class == ATA_DEV_UNKNOWN)
2051 *class = ATA_DEV_NONE;
2052
2053 out:
2054 DPRINTK("EXIT, class=%u\n", *class);
2055 return 0;
2056 }
2057
2058
2059 int sata_oxnas_init_controller(struct ata_host *host)
2060 {
2061 return 0;
2062 }
2063
2064 /**
2065 * Ref bug-6320
2066 *
2067 * This code is a work around for a DMA hardware bug that will repeat the
2068 * penultimate 8-bytes on some reads. This code will check that the amount
2069 * of data transferred is a multiple of 512 bytes, if not the in it will
2070 * fetch the correct data from a buffer in the SATA core and copy it into
2071 * memory.
2072 *
2073 * @param port SATA port to check and if necessary, correct.
2074 */
2075 static int sata_oxnas_bug_6320_detect(struct ata_port *ap)
2076 {
2077 struct sata_oxnas_port_priv *pd = ap->private_data;
2078 void __iomem *core_base = pd->core_base;
2079 int is_read;
2080 int quads_transferred;
2081 int remainder;
2082 int sector_quads_remaining;
2083 int bug_present = 0;
2084
2085 /* Only want to apply fix to reads */
2086 is_read = !(ioread32(core_base + DM_DBG1) & (ap->port_no ?
2087 BIT(CORE_PORT1_DATA_DIR_BIT) :
2088 BIT(CORE_PORT0_DATA_DIR_BIT)));
2089
2090 /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
2091 transferred (datacount_port register counts quads transferred) */
2092 quads_transferred =
2093 ioread32(core_base + (ap->port_no ?
2094 DATACOUNT_PORT1 : DATACOUNT_PORT0));
2095
2096 remainder = quads_transferred & 0x7f;
2097 sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
2098
2099 if (is_read && (sector_quads_remaining == 2)) {
2100 bug_present = 1;
2101 } else if (sector_quads_remaining) {
2102 if (is_read) {
2103 ata_port_warn(ap, "SATA read fixup cannot deal with "
2104 "%d quads remaining\n",
2105 sector_quads_remaining);
2106 } else {
2107 ata_port_warn(ap, "SATA write fixup of %d quads "
2108 "remaining not supported\n",
2109 sector_quads_remaining);
2110 }
2111 }
2112
2113 return bug_present;
2114 }
2115
2116 /* This port done an interrupt */
2117 static void sata_oxnas_port_irq(struct ata_port *ap, int force_error)
2118 {
2119 struct ata_queued_cmd *qc;
2120 struct sata_oxnas_port_priv *pd = ap->private_data;
2121 void __iomem *port_base = pd->port_base;
2122
2123 u32 int_status;
2124 unsigned long flags = 0;
2125
2126 DPRINTK("ENTER port %d irqstatus %x\n", ap->port_no,
2127 ioread32(port_base + INT_STATUS));
2128
2129 if (ap->qc_active & (1ULL << ATA_TAG_INTERNAL)) {
2130 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
2131 DPRINTK("completing non-ncq cmd\n");
2132
2133 if (qc)
2134 ata_qc_complete(qc);
2135
2136 return;
2137 }
2138
2139 qc = ata_qc_from_tag(ap, ap->link.active_tag);
2140
2141
2142 /* record the port's interrupt */
2143 int_status = ioread32(port_base + INT_STATUS);
2144
2145 /* If there's no command associated with this IRQ, ignore it. We may get
2146 * spurious interrupts when cleaning-up after a failed command, ignore
2147 * these too. */
2148 if (likely(qc)) {
2149 /* get the status before any error cleanup */
2150 qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));
2151 if (force_error) {
2152 /* Pretend there has been a link error */
2153 qc->err_mask |= AC_ERR_ATA_BUS;
2154 DPRINTK(" ####force error####\n");
2155 }
2156 /* tell libata we're done */
2157 local_irq_save(flags);
2158 sata_oxnas_irq_clear(ap);
2159 local_irq_restore(flags);
2160 ata_qc_complete(qc);
2161 } else {
2162 VPRINTK("Ignoring interrupt, can't find the command tag="
2163 "%d %08x\n", ap->link.active_tag, ap->qc_active);
2164 }
2165
2166 /* maybe a hotplug event */
2167 if (unlikely(int_status & INT_LINK_SERROR)) {
2168 u32 serror;
2169
2170 sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);
2171 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
2172 ata_ehi_hotplugged(&ap->link.eh_info);
2173 ata_port_freeze(ap);
2174 }
2175 }
2176 }
2177
2178 /**
2179 * irq_handler is the interrupt handling routine registered with the system,
2180 * by libata.
2181 */
2182 static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)
2183 {
2184 struct ata_host *ah = dev_instance;
2185 struct sata_oxnas_host_priv *hd = ah->private_data;
2186 void __iomem *core_base = hd->core_base;
2187
2188 u32 int_status;
2189 irqreturn_t ret = IRQ_NONE;
2190 u32 port_no;
2191 u32 mask;
2192 int bug_present;
2193
2194 /* loop until there are no more interrupts */
2195 while ((int_status = (ioread32(core_base + CORE_INT_STATUS)) &
2196 (COREINT_END | (COREINT_END << 1)))) {
2197
2198 /* clear any interrupt */
2199 iowrite32(int_status, core_base + CORE_INT_CLEAR);
2200
2201 /* Only need workaround_bug_6320 for single disk systems as dual
2202 * disk will use uCode which prevents this read underrun problem
2203 * from occurring.
2204 * All single disk systems will use port 0 */
2205 for (port_no = 0; port_no < hd->n_ports; ++port_no) {
2206 /* check the raw end of command interrupt to see if the
2207 * port is done */
2208 mask = (COREINT_END << port_no);
2209 if (!(int_status & mask))
2210 continue;
2211
2212 /* this port had an interrupt, clear it */
2213 iowrite32(mask, core_base + CORE_INT_CLEAR);
2214 /* check for bug 6320 only if no microcode was loaded */
2215 bug_present = (hd->current_ucode == UNKNOWN_MODE) &&
2216 sata_oxnas_bug_6320_detect(ah->ports[port_no]);
2217
2218 sata_oxnas_port_irq(ah->ports[port_no],
2219 bug_present);
2220 ret = IRQ_HANDLED;
2221 }
2222 }
2223
2224 return ret;
2225 }
2226
2227 /*
2228 * scsi mid-layer and libata interface structures
2229 */
2230 static struct scsi_host_template sata_oxnas_sht = {
2231 ATA_NCQ_SHT("sata_oxnas"),
2232 .can_queue = SATA_OXNAS_QUEUE_DEPTH,
2233 .sg_tablesize = SATA_OXNAS_MAX_PRD,
2234 .dma_boundary = ATA_DMA_BOUNDARY,
2235 };
2236
2237
2238 static struct ata_port_operations sata_oxnas_ops = {
2239 .inherits = &sata_port_ops,
2240 .qc_prep = sata_oxnas_qc_prep,
2241 .qc_issue = sata_oxnas_qc_issue,
2242 .qc_fill_rtf = sata_oxnas_qc_fill_rtf,
2243 .qc_new = sata_oxnas_qc_new,
2244 .qc_free = sata_oxnas_qc_free,
2245
2246 .scr_read = sata_oxnas_scr_read,
2247 .scr_write = sata_oxnas_scr_write,
2248
2249 .freeze = sata_oxnas_freeze,
2250 .thaw = sata_oxnas_thaw,
2251 .softreset = sata_oxnas_softreset,
2252 /* .hardreset = sata_oxnas_hardreset, */
2253 .postreset = sata_oxnas_postreset,
2254 .error_handler = sata_oxnas_error_handler,
2255 .post_internal_cmd = sata_oxnas_post_internal_cmd,
2256
2257 .port_start = sata_oxnas_port_start,
2258 .port_stop = sata_oxnas_port_stop,
2259
2260 .host_stop = sata_oxnas_host_stop,
2261 /* .pmp_attach = sata_oxnas_pmp_attach, */
2262 /* .pmp_detach = sata_oxnas_pmp_detach, */
2263 .sff_check_status = sata_oxnas_check_status,
2264 .acquire_hw = sata_oxnas_acquire_hw,
2265 };
2266
2267 static const struct ata_port_info sata_oxnas_port_info = {
2268 .flags = SATA_OXNAS_HOST_FLAGS,
2269 .pio_mask = ATA_PIO4,
2270 .udma_mask = ATA_UDMA6,
2271 .port_ops = &sata_oxnas_ops,
2272 };
2273
2274 static int sata_oxnas_probe(struct platform_device *ofdev)
2275 {
2276 int retval = -ENXIO;
2277 int n_ports = 0;
2278 void __iomem *port_base = NULL;
2279 void __iomem *dmactl_base = NULL;
2280 void __iomem *sgdma_base = NULL;
2281 void __iomem *core_base = NULL;
2282 void __iomem *phy_base = NULL;
2283 struct reset_control *rstc;
2284
2285 struct resource res = {};
2286 struct sata_oxnas_host_priv *host_priv = NULL;
2287 int irq = 0;
2288 struct ata_host *host = NULL;
2289 struct clk *clk = NULL;
2290
2291 const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };
2292
2293 of_property_read_u32(ofdev->dev.of_node, "nr-ports", &n_ports);
2294 if (n_ports < 1 || n_ports > SATA_OXNAS_MAX_PORTS)
2295 goto error_exit_with_cleanup;
2296
2297 port_base = of_iomap(ofdev->dev.of_node, 0);
2298 if (!port_base)
2299 goto error_exit_with_cleanup;
2300
2301 dmactl_base = of_iomap(ofdev->dev.of_node, 1);
2302 if (!dmactl_base)
2303 goto error_exit_with_cleanup;
2304
2305 sgdma_base = of_iomap(ofdev->dev.of_node, 2);
2306 if (!sgdma_base)
2307 goto error_exit_with_cleanup;
2308
2309 core_base = of_iomap(ofdev->dev.of_node, 3);
2310 if (!core_base)
2311 goto error_exit_with_cleanup;
2312
2313 phy_base = of_iomap(ofdev->dev.of_node, 4);
2314 if (!phy_base)
2315 goto error_exit_with_cleanup;
2316
2317 host_priv = devm_kzalloc(&ofdev->dev,
2318 sizeof(struct sata_oxnas_host_priv),
2319 GFP_KERNEL);
2320 if (!host_priv)
2321 goto error_exit_with_cleanup;
2322
2323 host_priv->port_base = port_base;
2324 host_priv->dmactl_base = dmactl_base;
2325 host_priv->sgdma_base = sgdma_base;
2326 host_priv->core_base = core_base;
2327 host_priv->phy_base = phy_base;
2328 host_priv->n_ports = n_ports;
2329 host_priv->current_ucode = UNKNOWN_MODE;
2330
2331 if (!of_address_to_resource(ofdev->dev.of_node, 5, &res)) {
2332 host_priv->dma_base = res.start;
2333 host_priv->dma_size = resource_size(&res);
2334 }
2335
2336 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
2337 if (!irq) {
2338 dev_err(&ofdev->dev, "invalid irq from platform\n");
2339 goto error_exit_with_cleanup;
2340 }
2341 host_priv->irq = irq;
2342
2343 clk = of_clk_get(ofdev->dev.of_node, 0);
2344 if (IS_ERR(clk)) {
2345 retval = PTR_ERR(clk);
2346 clk = NULL;
2347 goto error_exit_with_cleanup;
2348 }
2349 host_priv->clk = clk;
2350
2351 rstc = devm_reset_control_get(&ofdev->dev, "sata");
2352 if (IS_ERR(rstc)) {
2353 retval = PTR_ERR(rstc);
2354 goto error_exit_with_cleanup;
2355 }
2356 host_priv->rst_sata = rstc;
2357
2358 rstc = devm_reset_control_get(&ofdev->dev, "link");
2359 if (IS_ERR(rstc)) {
2360 retval = PTR_ERR(rstc);
2361 goto error_exit_with_cleanup;
2362 }
2363 host_priv->rst_link = rstc;
2364
2365 rstc = devm_reset_control_get(&ofdev->dev, "phy");
2366 if (IS_ERR(rstc)) {
2367 retval = PTR_ERR(rstc);
2368 goto error_exit_with_cleanup;
2369 }
2370 host_priv->rst_phy = rstc;
2371
2372 /* allocate host structure */
2373 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, n_ports);
2374
2375 if (!host) {
2376 retval = -ENOMEM;
2377 goto error_exit_with_cleanup;
2378 }
2379 host->private_data = host_priv;
2380 host->iomap = port_base;
2381
2382 /* initialize core locking and queues */
2383 init_waitqueue_head(&host_priv->fast_wait_queue);
2384 init_waitqueue_head(&host_priv->scsi_wait_queue);
2385 spin_lock_init(&host_priv->phy_lock);
2386 spin_lock_init(&host_priv->core_lock);
2387 host_priv->core_locked = 0;
2388 host_priv->reentrant_port_no = -1;
2389 host_priv->hw_lock_count = 0;
2390 host_priv->direct_lock_count = 0;
2391 host_priv->locker_uid = 0;
2392 host_priv->current_locker_type = SATA_UNLOCKED;
2393 host_priv->isr_arg = NULL;
2394 host_priv->isr_callback = NULL;
2395
2396 /* initialize host controller */
2397 retval = sata_oxnas_init_controller(host);
2398 if (retval)
2399 goto error_exit_with_cleanup;
2400
2401 /*
2402 * Now, register with libATA core, this will also initiate the
2403 * device discovery process, invoking our port_start() handler &
2404 * error_handler() to execute a dummy softreset EH session
2405 */
2406 ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,
2407 &sata_oxnas_sht);
2408
2409 return 0;
2410
2411 error_exit_with_cleanup:
2412 if (irq)
2413 irq_dispose_mapping(host_priv->irq);
2414 if (clk)
2415 clk_put(clk);
2416 if (host)
2417 ata_host_detach(host);
2418 if (port_base)
2419 iounmap(port_base);
2420 if (sgdma_base)
2421 iounmap(sgdma_base);
2422 if (core_base)
2423 iounmap(core_base);
2424 if (phy_base)
2425 iounmap(phy_base);
2426 return retval;
2427 }
2428
2429
2430 static int sata_oxnas_remove(struct platform_device *ofdev)
2431 {
2432 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
2433 struct sata_oxnas_host_priv *host_priv = host->private_data;
2434
2435 ata_host_detach(host);
2436
2437 irq_dispose_mapping(host_priv->irq);
2438 iounmap(host_priv->port_base);
2439 iounmap(host_priv->sgdma_base);
2440 iounmap(host_priv->core_base);
2441
2442 /* reset Controller, Link and PHY */
2443 reset_control_assert(host_priv->rst_sata);
2444 reset_control_assert(host_priv->rst_link);
2445 reset_control_assert(host_priv->rst_phy);
2446
2447 /* Disable the clock to the SATA block */
2448 clk_disable_unprepare(host_priv->clk);
2449 clk_put(host_priv->clk);
2450
2451 return 0;
2452 }
2453
2454 #ifdef CONFIG_PM
2455 static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)
2456 {
2457 struct ata_host *host = dev_get_drvdata(&op->dev);
2458
2459 return ata_host_suspend(host, state);
2460 }
2461
2462 static int sata_oxnas_resume(struct platform_device *op)
2463 {
2464 struct ata_host *host = dev_get_drvdata(&op->dev);
2465 int ret;
2466
2467 ret = sata_oxnas_init_controller(host);
2468 if (ret) {
2469 dev_err(&op->dev, "Error initializing hardware\n");
2470 return ret;
2471 }
2472 ata_host_resume(host);
2473 return 0;
2474 }
2475 #endif
2476
2477
2478
2479 static struct of_device_id oxnas_sata_match[] = {
2480 {
2481 .compatible = "plxtech,nas782x-sata",
2482 },
2483 {},
2484 };
2485
2486 MODULE_DEVICE_TABLE(of, oxnas_sata_match);
2487
2488 static struct platform_driver oxnas_sata_driver = {
2489 .driver = {
2490 .name = "oxnas-sata",
2491 .owner = THIS_MODULE,
2492 .of_match_table = oxnas_sata_match,
2493 },
2494 .probe = sata_oxnas_probe,
2495 .remove = sata_oxnas_remove,
2496 #ifdef CONFIG_PM
2497 .suspend = sata_oxnas_suspend,
2498 .resume = sata_oxnas_resume,
2499 #endif
2500 };
2501
2502 module_platform_driver(oxnas_sata_driver);
2503
2504 MODULE_LICENSE("GPL");
2505 MODULE_VERSION("1.0");
2506 MODULE_AUTHOR("Oxford Semiconductor Ltd.");
2507 MODULE_DESCRIPTION("low-level driver for Oxford 934 SATA core");
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