target/linux/mediatek/patches-6.6/230-v6.4-dt-bindings-clock-mediatek-add-mt7981-clock-IDs.patch

   1 From a6473d0f9f07b1196f3a67099826f50a2a4e84e8 Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Thu, 26 Jan 2023 03:34:05 +0000
   4 Subject: [PATCH] dt-bindings: clock: mediatek: add mt7981 clock IDs
   5
   6 Add MT7981 clock dt-bindings, include topckgen, apmixedsys,
   7 infracfg, and ethernet subsystem clocks.
   8
   9 Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  10 Signed-off-by: Jianhui Zhao <zhaojh329@gmail.com>
  11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  12 Link: https://lore.kernel.org/r/e353d32b5a4481766519a037afe1ed44e31ece1a.1674703830.git.daniel@makrotopia.org
  13 Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
  14 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  15 ---
  16  .../dt-bindings/clock/mediatek,mt7981-clk.h   | 215 ++++++++++++++++++
  17  1 file changed, 215 insertions(+)
  18  create mode 100644 include/dt-bindings/clock/mediatek,mt7981-clk.h
  19
  20 --- /dev/null
  21 +++ b/include/dt-bindings/clock/mediatek,mt7981-clk.h
  22 @@ -0,0 +1,215 @@
  23 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  24 +/*
  25 + * Copyright (c) 2021 MediaTek Inc.
  26 + * Author: Wenzhen.Yu <wenzhen.yu@mediatek.com>
  27 + * Author: Jianhui Zhao <zhaojh329@gmail.com>
  28 + * Author: Daniel Golle <daniel@makrotopia.org>
  29 + */
  30 +
  31 +#ifndef _DT_BINDINGS_CLK_MT7981_H
  32 +#define _DT_BINDINGS_CLK_MT7981_H
  33 +
  34 +/* TOPCKGEN */
  35 +#define CLK_TOP_CB_CKSQ_40M            0
  36 +#define CLK_TOP_CB_M_416M              1
  37 +#define CLK_TOP_CB_M_D2                        2
  38 +#define CLK_TOP_CB_M_D3                        3
  39 +#define CLK_TOP_M_D3_D2                        4
  40 +#define CLK_TOP_CB_M_D4                        5
  41 +#define CLK_TOP_CB_M_D8                        6
  42 +#define CLK_TOP_M_D8_D2                        7
  43 +#define CLK_TOP_CB_MM_720M             8
  44 +#define CLK_TOP_CB_MM_D2               9
  45 +#define CLK_TOP_CB_MM_D3               10
  46 +#define CLK_TOP_CB_MM_D3_D5            11
  47 +#define CLK_TOP_CB_MM_D4               12
  48 +#define CLK_TOP_CB_MM_D6               13
  49 +#define CLK_TOP_MM_D6_D2               14
  50 +#define CLK_TOP_CB_MM_D8               15
  51 +#define CLK_TOP_CB_APLL2_196M          16
  52 +#define CLK_TOP_APLL2_D2               17
  53 +#define CLK_TOP_APLL2_D4               18
  54 +#define CLK_TOP_NET1_2500M             19
  55 +#define CLK_TOP_CB_NET1_D4             20
  56 +#define CLK_TOP_CB_NET1_D5             21
  57 +#define CLK_TOP_NET1_D5_D2             22
  58 +#define CLK_TOP_NET1_D5_D4             23
  59 +#define CLK_TOP_CB_NET1_D8             24
  60 +#define CLK_TOP_NET1_D8_D2             25
  61 +#define CLK_TOP_NET1_D8_D4             26
  62 +#define CLK_TOP_CB_NET2_800M           27
  63 +#define CLK_TOP_CB_NET2_D2             28
  64 +#define CLK_TOP_CB_NET2_D4             29
  65 +#define CLK_TOP_NET2_D4_D2             30
  66 +#define CLK_TOP_NET2_D4_D4             31
  67 +#define CLK_TOP_CB_NET2_D6             32
  68 +#define CLK_TOP_CB_WEDMCU_208M         33
  69 +#define CLK_TOP_CB_SGM_325M            34
  70 +#define CLK_TOP_CKSQ_40M_D2            35
  71 +#define CLK_TOP_CB_RTC_32K             36
  72 +#define CLK_TOP_CB_RTC_32P7K           37
  73 +#define CLK_TOP_USB_TX250M             38
  74 +#define CLK_TOP_FAUD                   39
  75 +#define CLK_TOP_NFI1X                  40
  76 +#define CLK_TOP_USB_EQ_RX250M          41
  77 +#define CLK_TOP_USB_CDR_CK             42
  78 +#define CLK_TOP_USB_LN0_CK             43
  79 +#define CLK_TOP_SPINFI_BCK             44
  80 +#define CLK_TOP_SPI                    45
  81 +#define CLK_TOP_SPIM_MST               46
  82 +#define CLK_TOP_UART_BCK               47
  83 +#define CLK_TOP_PWM_BCK                        48
  84 +#define CLK_TOP_I2C_BCK                        49
  85 +#define CLK_TOP_PEXTP_TL               50
  86 +#define CLK_TOP_EMMC_208M              51
  87 +#define CLK_TOP_EMMC_400M              52
  88 +#define CLK_TOP_DRAMC_REF              53
  89 +#define CLK_TOP_DRAMC_MD32             54
  90 +#define CLK_TOP_SYSAXI                 55
  91 +#define CLK_TOP_SYSAPB                 56
  92 +#define CLK_TOP_ARM_DB_MAIN            57
  93 +#define CLK_TOP_AP2CNN_HOST            58
  94 +#define CLK_TOP_NETSYS                 59
  95 +#define CLK_TOP_NETSYS_500M            60
  96 +#define CLK_TOP_NETSYS_WED_MCU         61
  97 +#define CLK_TOP_NETSYS_2X              62
  98 +#define CLK_TOP_SGM_325M               63
  99 +#define CLK_TOP_SGM_REG                        64
 100 +#define CLK_TOP_F26M                   65
 101 +#define CLK_TOP_EIP97B                 66
 102 +#define CLK_TOP_USB3_PHY               67
 103 +#define CLK_TOP_AUD                    68
 104 +#define CLK_TOP_A1SYS                  69
 105 +#define CLK_TOP_AUD_L                  70
 106 +#define CLK_TOP_A_TUNER                        71
 107 +#define CLK_TOP_U2U3_REF               72
 108 +#define CLK_TOP_U2U3_SYS               73
 109 +#define CLK_TOP_U2U3_XHCI              74
 110 +#define CLK_TOP_USB_FRMCNT             75
 111 +#define CLK_TOP_NFI1X_SEL              76
 112 +#define CLK_TOP_SPINFI_SEL             77
 113 +#define CLK_TOP_SPI_SEL                        78
 114 +#define CLK_TOP_SPIM_MST_SEL           79
 115 +#define CLK_TOP_UART_SEL               80
 116 +#define CLK_TOP_PWM_SEL                        81
 117 +#define CLK_TOP_I2C_SEL                        82
 118 +#define CLK_TOP_PEXTP_TL_SEL           83
 119 +#define CLK_TOP_EMMC_208M_SEL          84
 120 +#define CLK_TOP_EMMC_400M_SEL          85
 121 +#define CLK_TOP_F26M_SEL               86
 122 +#define CLK_TOP_DRAMC_SEL              87
 123 +#define CLK_TOP_DRAMC_MD32_SEL         88
 124 +#define CLK_TOP_SYSAXI_SEL             89
 125 +#define CLK_TOP_SYSAPB_SEL             90
 126 +#define CLK_TOP_ARM_DB_MAIN_SEL                91
 127 +#define CLK_TOP_AP2CNN_HOST_SEL                92
 128 +#define CLK_TOP_NETSYS_SEL             93
 129 +#define CLK_TOP_NETSYS_500M_SEL                94
 130 +#define CLK_TOP_NETSYS_MCU_SEL         95
 131 +#define CLK_TOP_NETSYS_2X_SEL          96
 132 +#define CLK_TOP_SGM_325M_SEL           97
 133 +#define CLK_TOP_SGM_REG_SEL            98
 134 +#define CLK_TOP_EIP97B_SEL             99
 135 +#define CLK_TOP_USB3_PHY_SEL           100
 136 +#define CLK_TOP_AUD_SEL                        101
 137 +#define CLK_TOP_A1SYS_SEL              102
 138 +#define CLK_TOP_AUD_L_SEL              103
 139 +#define CLK_TOP_A_TUNER_SEL            104
 140 +#define CLK_TOP_U2U3_SEL               105
 141 +#define CLK_TOP_U2U3_SYS_SEL           106
 142 +#define CLK_TOP_U2U3_XHCI_SEL          107
 143 +#define CLK_TOP_USB_FRMCNT_SEL         108
 144 +#define CLK_TOP_AUD_I2S_M              109
 145 +
 146 +/* INFRACFG */
 147 +#define CLK_INFRA_66M_MCK              0
 148 +#define CLK_INFRA_UART0_SEL            1
 149 +#define CLK_INFRA_UART1_SEL            2
 150 +#define CLK_INFRA_UART2_SEL            3
 151 +#define CLK_INFRA_SPI0_SEL             4
 152 +#define CLK_INFRA_SPI1_SEL             5
 153 +#define CLK_INFRA_SPI2_SEL             6
 154 +#define CLK_INFRA_PWM1_SEL             7
 155 +#define CLK_INFRA_PWM2_SEL             8
 156 +#define CLK_INFRA_PWM3_SEL             9
 157 +#define CLK_INFRA_PWM_BSEL             10
 158 +#define CLK_INFRA_PCIE_SEL             11
 159 +#define CLK_INFRA_GPT_STA              12
 160 +#define CLK_INFRA_PWM_HCK              13
 161 +#define CLK_INFRA_PWM_STA              14
 162 +#define CLK_INFRA_PWM1_CK              15
 163 +#define CLK_INFRA_PWM2_CK              16
 164 +#define CLK_INFRA_PWM3_CK              17
 165 +#define CLK_INFRA_CQ_DMA_CK            18
 166 +#define CLK_INFRA_AUD_BUS_CK           19
 167 +#define CLK_INFRA_AUD_26M_CK           20
 168 +#define CLK_INFRA_AUD_L_CK             21
 169 +#define CLK_INFRA_AUD_AUD_CK           22
 170 +#define CLK_INFRA_AUD_EG2_CK           23
 171 +#define CLK_INFRA_DRAMC_26M_CK         24
 172 +#define CLK_INFRA_DBG_CK               25
 173 +#define CLK_INFRA_AP_DMA_CK            26
 174 +#define CLK_INFRA_SEJ_CK               27
 175 +#define CLK_INFRA_SEJ_13M_CK           28
 176 +#define CLK_INFRA_THERM_CK             29
 177 +#define CLK_INFRA_I2C0_CK              30
 178 +#define CLK_INFRA_UART0_CK             31
 179 +#define CLK_INFRA_UART1_CK             32
 180 +#define CLK_INFRA_UART2_CK             33
 181 +#define CLK_INFRA_SPI2_CK              34
 182 +#define CLK_INFRA_SPI2_HCK_CK          35
 183 +#define CLK_INFRA_NFI1_CK              36
 184 +#define CLK_INFRA_SPINFI1_CK           37
 185 +#define CLK_INFRA_NFI_HCK_CK           38
 186 +#define CLK_INFRA_SPI0_CK              39
 187 +#define CLK_INFRA_SPI1_CK              40
 188 +#define CLK_INFRA_SPI0_HCK_CK          41
 189 +#define CLK_INFRA_SPI1_HCK_CK          42
 190 +#define CLK_INFRA_FRTC_CK              43
 191 +#define CLK_INFRA_MSDC_CK              44
 192 +#define CLK_INFRA_MSDC_HCK_CK          45
 193 +#define CLK_INFRA_MSDC_133M_CK         46
 194 +#define CLK_INFRA_MSDC_66M_CK          47
 195 +#define CLK_INFRA_ADC_26M_CK           48
 196 +#define CLK_INFRA_ADC_FRC_CK           49
 197 +#define CLK_INFRA_FBIST2FPC_CK         50
 198 +#define CLK_INFRA_I2C_MCK_CK           51
 199 +#define CLK_INFRA_I2C_PCK_CK           52
 200 +#define CLK_INFRA_IUSB_133_CK          53
 201 +#define CLK_INFRA_IUSB_66M_CK          54
 202 +#define CLK_INFRA_IUSB_SYS_CK          55
 203 +#define CLK_INFRA_IUSB_CK              56
 204 +#define CLK_INFRA_IPCIE_CK             57
 205 +#define CLK_INFRA_IPCIE_PIPE_CK                58
 206 +#define CLK_INFRA_IPCIER_CK            59
 207 +#define CLK_INFRA_IPCIEB_CK            60
 208 +
 209 +/* APMIXEDSYS */
 210 +#define CLK_APMIXED_ARMPLL             0
 211 +#define CLK_APMIXED_NET2PLL            1
 212 +#define CLK_APMIXED_MMPLL              2
 213 +#define CLK_APMIXED_SGMPLL             3
 214 +#define CLK_APMIXED_WEDMCUPLL          4
 215 +#define CLK_APMIXED_NET1PLL            5
 216 +#define CLK_APMIXED_MPLL               6
 217 +#define CLK_APMIXED_APLL2              7
 218 +
 219 +/* SGMIISYS_0 */
 220 +#define CLK_SGM0_TX_EN                 0
 221 +#define CLK_SGM0_RX_EN                 1
 222 +#define CLK_SGM0_CK0_EN                        2
 223 +#define CLK_SGM0_CDR_CK0_EN            3
 224 +
 225 +/* SGMIISYS_1 */
 226 +#define CLK_SGM1_TX_EN                 0
 227 +#define CLK_SGM1_RX_EN                 1
 228 +#define CLK_SGM1_CK1_EN                        2
 229 +#define CLK_SGM1_CDR_CK1_EN            3
 230 +
 231 +/* ETHSYS */
 232 +#define CLK_ETH_FE_EN                  0
 233 +#define CLK_ETH_GP2_EN                 1
 234 +#define CLK_ETH_GP1_EN                 2
 235 +#define CLK_ETH_WOCPU0_EN              3
 236 +
 237 +#endif /* _DT_BINDINGS_CLK_MT7981_H */