Add support for the T113 family, along with 4 boards.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
endef
+define U-Boot/mangopi_mqdual_t113
+ BUILD_SUBTARGET:=cortexa7
+ NAME:=MangoPi MQDual (T113)
+ BUILD_DEVICES:=widora_mangopi-mqdual-t113
+endef
+
+define U-Boot/myir_myd_t113x
+ BUILD_SUBTARGET:=cortexa7
+ NAME:=MYIR MYD-T113X
+ BUILD_DEVICES:=myir_myd-yt113x
+ UENV:=t113.ttyS5
+endef
+
+define U-Boot/myir_myd_t113x-spi
+ BUILD_SUBTARGET:=cortexa7
+ NAME:=MYIR MYD-T113X SPI
+ BUILD_DEVICES:=myir_myd-yt113x-spi
+ UENV:=t113.ttyS5
+endef
+
+define U-Boot/rongpin_rp_t113
+ BUILD_SUBTARGET:=cortexa7
+ NAME:=Rongpin RP-T113
+ BUILD_DEVICES:=rongpin_rp-t113
+ UENV:=t113.ttyS3
+endef
+
UBOOT_TARGETS := \
+ mangopi_mqdual_t113 \
+ myir_myd_t113x \
+ myir_myd_t113x-spi \
+ rongpin_rp_t113 \
a64-olinuxino \
a64-olinuxino-emmc \
A10-OLinuXino-Lime \
--- /dev/null
+From f26cc77a06a9efb561396adc1c02f01e5c5170c5 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Fri, 21 Jul 2023 14:45:59 +0100
+Subject: [PATCH 4000/4018] sunxi: clock: h6: prepare for PRCM less SoCs
+
+The Allwinner D1/R528/T113 SoCs have a very minimal separate
+"management" power plane, with almost no device attached to it (so
+no r_i2c or r_uart). This means we don't need to flip any clock gates in
+the PRCM block, which in fact those SoCs do not have.
+
+Prepare the code for those SoCs by making the PRCM block optional in the
+H6 SPL clock code, which we otherwise share to this new family of SoCs.
+If the memory map (cpu.h) does not define the PRCM address, we simply
+skip any attempt to program gates there.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/arm/mach-sunxi/clock_sun50i_h6.c | 22 +++++++++++++++++++---
+ 1 file changed, 19 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c
+index bea91c78bc..0d15d53936 100644
+--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
++++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
+@@ -4,14 +4,20 @@
+ #include <asm/arch/clock.h>
+ #include <asm/arch/prcm.h>
+
++#ifndef SUNXI_PRCM_BASE
++#define SUNXI_PRCM_BASE 0
++#endif
++
+ #ifdef CONFIG_SPL_BUILD
+-void clock_init_safe(void)
++
++static void clock_init_safe_prcm(void)
+ {
+- struct sunxi_ccm_reg *const ccm =
+- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
++ if (!prcm)
++ return;
++
+ if (IS_ENABLED(CONFIG_MACH_SUN50I_H616)) {
+ /* this seems to enable PLLs on H616 */
+ setbits_le32(&prcm->sys_pwroff_gating, 0x10);
+@@ -30,6 +36,14 @@ void clock_init_safe(void)
+ /* set PLL VDD LDO output to 1.14 V */
+ setbits_le32(&prcm->pll_ldo_cfg, 0x60000);
+ }
++}
++
++void clock_init_safe(void)
++{
++ struct sunxi_ccm_reg *const ccm =
++ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
++
++ clock_init_safe_prcm();
+
+ clock_set_pll1(408000000);
+
+@@ -146,6 +160,8 @@ int clock_twi_onoff(int port, int state)
+ value = BIT(GATE_SHIFT) | BIT (RESET_SHIFT);
+
+ if (port == 5) {
++ if (!prcm)
++ return -ENODEV;
+ shift = 0;
+ ptr = &prcm->twi_gate_reset;
+ } else {
+--
+2.20.1
+
--- /dev/null
+From 13339996e5ffd1cf9e276e6403aa14948f27c56a Mon Sep 17 00:00:00 2001
+From: Yegor Yefremov <yegorslists@googlemail.com>
+Date: Wed, 28 Nov 2012 11:15:18 +0100
+Subject: [PATCH 4001/4018] net: add ICPlus PHY driver
+
+The driver code was taken from Linux kernel source:
+drivers/net/phy/icplus.c
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
+---
+ drivers/net/phy/Kconfig | 3 ++
+ drivers/net/phy/Makefile | 1 +
+ drivers/net/phy/icplus.c | 87 ++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 91 insertions(+)
+ create mode 100644 drivers/net/phy/icplus.c
+
+diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
+index 3d96938eab..afcd1d09c7 100644
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -168,6 +168,9 @@ config PHY_DAVICOM
+ config PHY_ET1011C
+ bool "LSI TruePHY ET1011C support"
+
++config PHY_ICPLUS
++ bool "IC+ IP101 Ethernet PHY support"
++
+ config PHY_LXT
+ bool "LXT971 Ethernet PHY support"
+
+diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
+index 2487f366e1..ff7bc1a4f1 100644
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -18,6 +18,7 @@ obj-$(CONFIG_PHY_CORTINA) += cortina.o
+ obj-$(CONFIG_PHY_CORTINA_ACCESS) += ca_phy.o
+ obj-$(CONFIG_PHY_DAVICOM) += davicom.o
+ obj-$(CONFIG_PHY_ET1011C) += et1011c.o
++obj-$(CONFIG_PHY_ICPLUS) += icplus.o
+ obj-$(CONFIG_PHY_LXT) += lxt.o
+ obj-$(CONFIG_PHY_MARVELL) += marvell.o
+ obj-$(CONFIG_PHY_MARVELL_10G) += marvell10g.o
+diff --git a/drivers/net/phy/icplus.c b/drivers/net/phy/icplus.c
+new file mode 100644
+index 0000000000..27a8fbae50
+--- /dev/null
++++ b/drivers/net/phy/icplus.c
+@@ -0,0 +1,87 @@
++/*
++ * ICPlus PHY drivers
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ * Copyright (c) 2007 Freescale Semiconductor, Inc.
++ *
++ */
++#include <phy.h>
++
++/* IP101A/G - IP1001 */
++#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
++#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
++#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
++#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
++#define IP101A_G_APS_ON 2 /* IP101A/G APS Mode bit */
++#define IP101A_G_IRQ_CONF_STATUS 0x11 /* Conf Info IRQ & Status Reg */
++#define IP101A_G_IRQ_PIN_USED (1<<15) /* INTR pin used */
++#define IP101A_G_IRQ_DEFAULT IP101A_G_IRQ_PIN_USED
++
++static int ip1001_config(struct phy_device *phydev)
++{
++ int c;
++
++ /* Enable Auto Power Saving mode */
++ c = phy_read(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2);
++ if (c < 0)
++ return c;
++ c |= IP1001_APS_ON;
++ c = phy_write(phydev, MDIO_DEVAD_NONE, IP1001_SPEC_CTRL_STATUS_2, c);
++ if (c < 0)
++ return c;
++
++ /* INTR pin used: speed/link/duplex will cause an interrupt */
++ c = phy_write(phydev, MDIO_DEVAD_NONE, IP101A_G_IRQ_CONF_STATUS,
++ IP101A_G_IRQ_DEFAULT);
++ if (c < 0)
++ return c;
++
++ if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
++ /*
++ * Additional delay (2ns) used to adjust RX clock phase
++ * at RGMII interface
++ */
++ c = phy_read(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS);
++ if (c < 0)
++ return c;
++
++ c |= IP1001_PHASE_SEL_MASK;
++ c = phy_write(phydev, MDIO_DEVAD_NONE, IP10XX_SPEC_CTRL_STATUS,
++ c);
++ if (c < 0)
++ return c;
++ }
++
++ return 0;
++}
++
++static int ip1001_startup(struct phy_device *phydev)
++{
++ genphy_update_link(phydev);
++ genphy_parse_link(phydev);
++
++ return 0;
++}
++U_BOOT_PHY_DRIVER(lxt971) = {
++ .name = "ICPlus IP1001",
++ .uid = 0x02430d90,
++ .mask = 0x0ffffff0,
++ .features = PHY_GBIT_FEATURES,
++ .config = &ip1001_config,
++ .startup = &ip1001_startup,
++ .shutdown = &genphy_shutdown,
++};
+--
+2.20.1
+
--- /dev/null
+From 3cdcdfd064bb9a5c5082feb967e783c6e1ebf6d4 Mon Sep 17 00:00:00 2001
+From: Maxim Kiselev <bigunclemax@gmail.com>
+Date: Fri, 19 May 2023 16:40:07 +0300
+Subject: [PATCH 4002/4018] sunxi: SPL SPI: Add SPI boot support for the
+ Allwinner R528/T113 SoCs
+
+R528/T113 SoCs uses the same SPI IP as the H6, also have the same clocks
+and reset bits layout, but the CCU base is different. Another difference
+is that the new SoCs do not have a clock divider inside. Instead of this
+we should configure sample mode depending on input clock rate.
+
+The pin assignment is also different: the H6 uses PC0, the R528/T113 PC4
+instead. This makes for a change in spi0_pinmux_setup() routine.
+
+This patch extends the H6/H616 #ifdef guards to also cover the R528/T113,
+using the shared CONFIG_SUNXI_GEN_NCAT2 and CONFIG_MACH_SUN8I_R528
+symbols. Also use CONFIG_SUNXI_GEN_NCAT2 symbol for the Kconfig
+dependency.
+
+Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
+Tested-by: Sam Edwards <CFSworks@gmail.com>
+---
+ arch/arm/mach-sunxi/Kconfig | 2 +-
+ arch/arm/mach-sunxi/spl_spi_sunxi.c | 78 +++++++++++++++++++++--------
+ 2 files changed, 58 insertions(+), 22 deletions(-)
+
+diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
+index a4a8d8e944..d1acb88704 100644
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -1061,7 +1061,7 @@ config SPL_STACK_R_ADDR
+
+ config SPL_SPI_SUNXI
+ bool "Support for SPI Flash on Allwinner SoCs in SPL"
+- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV
++ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I || MACH_SUN8I_R40 || SUN50I_GEN_H6 || MACH_SUNIV || SUNXI_GEN_NCAT2
+ help
+ Enable support for SPI Flash. This option allows SPL to read from
+ sunxi SPI Flash. It uses the same method as the boot ROM, so does
+diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c
+index c2410dd7bb..3cfbf56d59 100644
+--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
++++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
+@@ -73,18 +73,27 @@
+ #define SUN6I_CTL_ENABLE BIT(0)
+ #define SUN6I_CTL_MASTER BIT(1)
+ #define SUN6I_CTL_SRST BIT(31)
++#define SUN6I_TCR_SDM BIT(13)
+ #define SUN6I_TCR_XCH BIT(31)
+
+ /*****************************************************************************/
+
+-#define CCM_AHB_GATING0 (0x01C20000 + 0x60)
+-#define CCM_H6_SPI_BGR_REG (0x03001000 + 0x96c)
+-#ifdef CONFIG_SUN50I_GEN_H6
+-#define CCM_SPI0_CLK (0x03001000 + 0x940)
++#if defined(CONFIG_SUN50I_GEN_H6)
++#define CCM_BASE 0x03001000
++#elif defined(CONFIG_SUNXI_GEN_NCAT2)
++#define CCM_BASE 0x02001000
+ #else
+-#define CCM_SPI0_CLK (0x01C20000 + 0xA0)
++#define CCM_BASE 0x01C20000
+ #endif
+-#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0)
++
++#define CCM_AHB_GATING0 (CCM_BASE + 0x60)
++#define CCM_H6_SPI_BGR_REG (CCM_BASE + 0x96c)
++#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2)
++#define CCM_SPI0_CLK (CCM_BASE + 0x940)
++#else
++#define CCM_SPI0_CLK (CCM_BASE + 0xA0)
++#endif
++#define SUN6I_BUS_SOFT_RST_REG0 (CCM_BASE + 0x2C0)
+
+ #define AHB_RESET_SPI0_SHIFT 20
+ #define AHB_GATE_OFFSET_SPI0 20
+@@ -102,17 +111,22 @@
+ */
+ static void spi0_pinmux_setup(unsigned int pin_function)
+ {
+- /* All chips use PC0 and PC2. */
+- sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
++ /* All chips use PC2. And all chips use PC0, except R528/T113 */
++ if (!IS_ENABLED(CONFIG_MACH_SUN8I_R528))
++ sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
++
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
+
+- /* All chips except H6 and H616 use PC1. */
+- if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
++ /* All chips except H6/H616/R528/T113 use PC1. */
++ if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) &&
++ !IS_ENABLED(CONFIG_MACH_SUN8I_R528))
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
+
+- if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
++ if (IS_ENABLED(CONFIG_MACH_SUN50I_H6) ||
++ IS_ENABLED(CONFIG_MACH_SUN8I_R528))
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
+- if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
++ if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) ||
++ IS_ENABLED(CONFIG_MACH_SUN8I_R528))
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(4), pin_function);
+
+ /* Older generations use PC23 for CS, newer ones use PC3. */
+@@ -126,7 +140,8 @@ static void spi0_pinmux_setup(unsigned int pin_function)
+ static bool is_sun6i_gen_spi(void)
+ {
+ return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
+- IS_ENABLED(CONFIG_SUN50I_GEN_H6);
++ IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
++ IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2);
+ }
+
+ static uintptr_t spi0_base_address(void)
+@@ -137,6 +152,9 @@ static uintptr_t spi0_base_address(void)
+ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
+ return 0x05010000;
+
++ if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
++ return 0x04025000;
++
+ if (!is_sun6i_gen_spi() ||
+ IS_ENABLED(CONFIG_MACH_SUNIV))
+ return 0x01C05000;
+@@ -152,23 +170,30 @@ static void spi0_enable_clock(void)
+ uintptr_t base = spi0_base_address();
+
+ /* Deassert SPI0 reset on SUN6I */
+- if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
++ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
++ IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
+ setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
+ else if (is_sun6i_gen_spi())
+ setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
+ (1 << AHB_RESET_SPI0_SHIFT));
+
+ /* Open the SPI0 gate */
+- if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
++ if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) &&
++ !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
+ setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
+
+ if (IS_ENABLED(CONFIG_MACH_SUNIV)) {
+ /* Divide by 32, clock source is AHB clock 200MHz */
+ writel(SPI0_CLK_DIV_BY_32, base + SUN6I_SPI0_CCTL);
+ } else {
+- /* Divide by 4 */
+- writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
+- SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
++ /* New SoCs do not have a clock divider inside */
++ if (!IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) {
++ /* Divide by 4 */
++ writel(SPI0_CLK_DIV_BY_4,
++ base + (is_sun6i_gen_spi() ? SUN6I_SPI0_CCTL :
++ SUN4I_SPI0_CCTL));
++ }
++
+ /* 24MHz from OSC24M */
+ writel((1 << 31), CCM_SPI0_CLK);
+ }
+@@ -180,6 +205,14 @@ static void spi0_enable_clock(void)
+ /* Wait for completion */
+ while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
+ ;
++
++ /*
++ * For new SoCs we should configure sample mode depending on
++ * input clock. As 24MHz from OSC24M is used, we could use
++ * normal sample mode by setting SDM bit in the TCR register
++ */
++ if (IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
++ setbits_le32(base + SUN6I_SPI0_TCR, SUN6I_TCR_SDM);
+ } else {
+ /* Enable SPI in the master mode and reset FIFO */
+ setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
+@@ -206,11 +239,13 @@ static void spi0_disable_clock(void)
+ writel(0, CCM_SPI0_CLK);
+
+ /* Close the SPI0 gate */
+- if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6))
++ if (!IS_ENABLED(CONFIG_SUN50I_GEN_H6) &&
++ !IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
+ clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
+
+ /* Assert SPI0 reset on SUN6I */
+- if (IS_ENABLED(CONFIG_SUN50I_GEN_H6))
++ if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) ||
++ IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2))
+ clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
+ else if (is_sun6i_gen_spi())
+ clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
+@@ -224,7 +259,8 @@ static void spi0_init(void)
+ if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
+ IS_ENABLED(CONFIG_SUN50I_GEN_H6))
+ pin_function = SUN50I_GPC_SPI0;
+- else if (IS_ENABLED(CONFIG_MACH_SUNIV))
++ else if (IS_ENABLED(CONFIG_MACH_SUNIV) ||
++ IS_ENABLED(CONFIG_MACH_SUN8I_R528))
+ pin_function = SUNIV_GPC_SPI0;
+
+ spi0_pinmux_setup(pin_function);
+--
+2.20.1
+
--- /dev/null
+From 8f4d23ac2094fe2153fbe82b089d1d6d5e0c02d8 Mon Sep 17 00:00:00 2001
+From: Maxim Kiselev <bigunclemax@gmail.com>
+Date: Fri, 19 May 2023 16:40:08 +0300
+Subject: [PATCH 4003/4018] spi: sunxi: Add support for R329/D1/R528/T113 SPI
+ controller
+
+These SoCs have two SPI controllers that are quite similar to the SPI
+on previous Allwinner SoCs. The main difference is that new SoCs
+don't have a clock divider (SPI_CCR register) inside SPI IP.
+
+Instead SPI sample mode should be configured depending on the input clock.
+
+For now SPI input clock source selection is not supported by this driver,
+and only HOSC@24MHz can be used as input clock. Therefore, according to
+the, manual we could change the SPI sample mode from delay half
+cycle(default) to normal.
+
+This patch adds a quirk for this kind of SPI controllers
+
+Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
+Tested-by: Sam Edwards <CFSworks@gmail.com>
+---
+ drivers/spi/spi-sunxi.c | 34 +++++++++++++++++++++++++++++++++-
+ 1 file changed, 33 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
+index c56d82d998..9ec6b359e2 100644
+--- a/drivers/spi/spi-sunxi.c
++++ b/drivers/spi/spi-sunxi.c
+@@ -117,6 +117,8 @@ enum sun4i_spi_bits {
+ SPI_TCR_XCH,
+ SPI_TCR_CS_MANUAL,
+ SPI_TCR_CS_LEVEL,
++ SPI_TCR_SDC,
++ SPI_TCR_SDM,
+ SPI_FCR_TF_RST,
+ SPI_FCR_RF_RST,
+ SPI_FSR_RF_CNT_MASK,
+@@ -128,6 +130,7 @@ struct sun4i_spi_variant {
+ u32 fifo_depth;
+ bool has_soft_reset;
+ bool has_burst_ctl;
++ bool has_clk_ctl;
+ };
+
+ struct sun4i_spi_plat {
+@@ -302,7 +305,19 @@ static int sun4i_spi_claim_bus(struct udevice *dev)
+ setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
+ SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
+
+- sun4i_spi_set_speed_mode(dev->parent);
++ if (priv->variant->has_clk_ctl) {
++ sun4i_spi_set_speed_mode(dev->parent);
++ } else {
++ /*
++ * At this moment there is no ability to change input clock.
++ * Therefore, we can only use default HOSC@24MHz clock and
++ * set SPI sampling mode to normal
++ */
++ clrsetbits_le32(SPI_REG(priv, SPI_TCR),
++ SPI_BIT(priv, SPI_TCR_SDC) |
++ SPI_BIT(priv, SPI_TCR_SDM),
++ SPI_BIT(priv, SPI_TCR_SDM));
++ }
+
+ return 0;
+ }
+@@ -516,6 +531,8 @@ static const u32 sun6i_spi_bits[] = {
+ [SPI_TCR_CS_MASK] = 0x30,
+ [SPI_TCR_CS_MANUAL] = BIT(6),
+ [SPI_TCR_CS_LEVEL] = BIT(7),
++ [SPI_TCR_SDC] = BIT(11),
++ [SPI_TCR_SDM] = BIT(13),
+ [SPI_TCR_XCH] = BIT(31),
+ [SPI_FCR_RF_RST] = BIT(15),
+ [SPI_FCR_TF_RST] = BIT(31),
+@@ -526,6 +543,7 @@ static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
+ .regs = sun4i_spi_regs,
+ .bits = sun4i_spi_bits,
+ .fifo_depth = 64,
++ .has_clk_ctl = true,
+ };
+
+ static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
+@@ -534,6 +552,7 @@ static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
+ .fifo_depth = 128,
+ .has_soft_reset = true,
+ .has_burst_ctl = true,
++ .has_clk_ctl = true,
+ };
+
+ static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
+@@ -542,6 +561,15 @@ static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
+ .fifo_depth = 64,
+ .has_soft_reset = true,
+ .has_burst_ctl = true,
++ .has_clk_ctl = true,
++};
++
++static const struct sun4i_spi_variant sun50i_r329_spi_variant = {
++ .regs = sun6i_spi_regs,
++ .bits = sun6i_spi_bits,
++ .fifo_depth = 64,
++ .has_soft_reset = true,
++ .has_burst_ctl = true,
+ };
+
+ static const struct udevice_id sun4i_spi_ids[] = {
+@@ -557,6 +585,10 @@ static const struct udevice_id sun4i_spi_ids[] = {
+ .compatible = "allwinner,sun8i-h3-spi",
+ .data = (ulong)&sun8i_h3_spi_variant,
+ },
++ {
++ .compatible = "allwinner,sun50i-r329-spi",
++ .data = (ulong)&sun50i_r329_spi_variant,
++ },
+ { /* sentinel */ }
+ };
+
+--
+2.20.1
+
--- /dev/null
+From 94db257f9fd0b36e612dd6ea2ce3f695da0d8fc2 Mon Sep 17 00:00:00 2001
+From: Sam Edwards <cfsworks@gmail.com>
+Date: Wed, 16 Aug 2023 10:34:20 -0700
+Subject: [PATCH 4004/4018] HACK: sunxi: psci: be compatible with v1 of R528
+ patchset
+
+This is a hack for reviewer QoL. It is not being submitted for mainline
+inclusion.
+---
+ arch/arm/cpu/armv7/sunxi/psci.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
+index 5cb8cfa6cf..c8a9218d45 100644
+--- a/arch/arm/cpu/armv7/sunxi/psci.c
++++ b/arch/arm/cpu/armv7/sunxi/psci.c
+@@ -65,6 +65,18 @@
+ #define SUNXI_R_CPUCFG_BASE 0
+ #endif
+
++/* 3 hacks for compatibility across v1/v2 of Andre's R528 support series */
++#ifndef SUNXI_R_CPUCFG_BASE
++#define SUNXI_R_CPUCFG_BASE 0
++#endif
++#ifndef SUNXI_PRCM_BASE
++#define SUNXI_PRCM_BASE 0
++#endif
++#if defined(SUNXI_CPUX_BASE) && defined(SUNXI_CPUCFG_BASE)
++#undef SUNXI_CPUCFG_BASE
++#define SUNXI_CPUCFG_BASE SUNXI_CPUX_BASE
++#endif
++
+ static void __secure cp15_write_cntp_tval(u32 tval)
+ {
+ asm volatile ("mcr p15, 0, %0, c14, c2, 0" : : "r" (tval));
+--
+2.20.1
+
--- /dev/null
+From 1be7791f220325b0d6f42c3f2c383d8423936942 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sat, 3 Jun 2023 00:52:04 +0200
+Subject: [PATCH 4005/4018] sunxi: add uart0_pins on Port E PE2/PE3 on D1s/T133
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/riscv/dts/sunxi-d1s-t113.dtsi | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi
+index 822f022eec..e32112972d 100644
+--- a/arch/riscv/dts/sunxi-d1s-t113.dtsi
++++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi
+@@ -143,6 +143,12 @@
+ pins = "PB6", "PB7";
+ function = "uart3";
+ };
++
++ /omit-if-no-ref/
++ uart0_pins: uart0-pins {
++ pins = "PE2", "PE3";
++ function = "uart0";
++ };
+ };
+
+ ccu: clock-controller@2001000 {
+--
+2.20.1
+
--- /dev/null
+From 92c2cd5838666718cc55ee21f02e6959ab40e463 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sat, 3 Jun 2023 00:52:40 +0200
+Subject: [PATCH 4006/4018] sunxi: add support for MangoPI MQDual T113 variant
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/dts/Makefile | 3 +-
+ .../dts/sun8i-t113s-mangopi-mqdual-t113.dts | 50 +++++++++++++++++++
+ configs/mangopi_mqdual_t113_defconfig | 17 +++++++
+ 3 files changed, 69 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/dts/sun8i-t113s-mangopi-mqdual-t113.dts
+ create mode 100644 configs/mangopi_mqdual_t113_defconfig
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 9d28a485be..440a6976d6 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -810,7 +810,8 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
+ sun8i-v3-sl631-imx179.dtb \
+ sun8i-v3s-licheepi-zero.dtb
+ dtb-$(CONFIG_MACH_SUN8I_R528) += \
+- sun8i-t113s-mangopi-mq-r-t113.dtb
++ sun8i-t113s-mangopi-mq-r-t113.dtb \
++ sun8i-t113s-mangopi-mqdual-t113.dtb
+ dtb-$(CONFIG_MACH_SUN50I_H5) += \
+ sun50i-h5-bananapi-m2-plus.dtb \
+ sun50i-h5-emlid-neutis-n5-devboard.dtb \
+diff --git a/arch/arm/dts/sun8i-t113s-mangopi-mqdual-t113.dts b/arch/arm/dts/sun8i-t113s-mangopi-mqdual-t113.dts
+new file mode 100644
+index 0000000000..7de3ddb92f
+--- /dev/null
++++ b/arch/arm/dts/sun8i-t113s-mangopi-mqdual-t113.dts
+@@ -0,0 +1,50 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Arm Ltd.
++
++#include <dt-bindings/interrupt-controller/irq.h>
++
++/dts-v1/;
++
++#include "sun8i-t113s.dtsi"
++#include "sunxi-d1s-t113-mangopi-mq-r.dtsi"
++
++/ {
++ model = "MangoPi MQDual T113";
++ compatible = "widora,mangopi-mqdual-t113", "allwinner,sun8i-t113s";
++
++ aliases {
++ serial0 = &uart0;
++ ethernet0 = &rtl8189ftv;
++ };
++
++ chosen {
++ stdout-path = "serial0:115200n8";
++ };
++};
++
++&cpu0 {
++ cpu-supply = <®_vcc_core>;
++};
++
++&cpu1 {
++ cpu-supply = <®_vcc_core>;
++};
++
++&mmc1 {
++ rtl8189ftv: wifi@1 {
++ reg = <1>;
++ interrupt-parent = <&pio>;
++ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */
++ interrupt-names = "host-wake";
++ };
++};
++
++&uart0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart0_pins>;
++ status = "okay";
++};
++
++&uart3 {
++ status = "disabled";
++};
+diff --git a/configs/mangopi_mqdual_t113_defconfig b/configs/mangopi_mqdual_t113_defconfig
+new file mode 100644
+index 0000000000..98b90c55f4
+--- /dev/null
++++ b/configs/mangopi_mqdual_t113_defconfig
+@@ -0,0 +1,17 @@
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-mangopi-mqdual-t113"
++CONFIG_SUNXI_MINIMUM_DRAM_MB=128
++CONFIG_SPL=y
++CONFIG_MACH_SUN8I_R528=y
++CONFIG_CONS_INDEX=1
++CONFIG_MMC0_CD_PIN="PF6"
++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
++CONFIG_SYS_MONITOR_LEN=786432
++CONFIG_DRAM_CLK=792
++CONFIG_DRAM_ZQ=8092667
++CONFIG_DRAM_SUNXI_ODT_EN=0
++CONFIG_DRAM_SUNXI_TPR0=0x004a2195
++CONFIG_DRAM_SUNXI_TPR11=0x340000
++CONFIG_DRAM_SUNXI_TPR12=0x46
++CONFIG_DRAM_SUNXI_TPR13=0x34000100
+--
+2.20.1
+
--- /dev/null
+From 41ee73b7621cd4b689ad9c9f107aff2e8c30ef2f Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sat, 3 Jun 2023 23:41:31 +0200
+Subject: [PATCH 4007/4018] sunxi: add support for UART5 in Port E group on
+ T133
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/include/asm/arch-sunxi/serial.h | 1 +
+ arch/arm/mach-sunxi/board.c | 4 ++++
+ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 +
+ include/configs/sunxi-common.h | 3 +++
+ 4 files changed, 9 insertions(+)
+
+diff --git a/arch/arm/include/asm/arch-sunxi/serial.h b/arch/arm/include/asm/arch-sunxi/serial.h
+index 9386287b65..48d0f42a3b 100644
+--- a/arch/arm/include/asm/arch-sunxi/serial.h
++++ b/arch/arm/include/asm/arch-sunxi/serial.h
+@@ -20,6 +20,7 @@
+ #elif defined(CONFIG_SUNXI_GEN_NCAT2)
+ #define SUNXI_UART0_BASE 0x02500000
+ #define SUNXI_R_UART_BASE 0 // 0x07080000 (?>
++#define SUNXI_UART5_BASE (SUNXI_UART0_BASE + 0x1400)
+ #else
+ #define SUNXI_UART0_BASE 0x01c28000
+ #define SUNXI_R_UART_BASE 0x01f02800
+diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
+index 11a4941822..91de9b6c39 100644
+--- a/arch/arm/mach-sunxi/board.c
++++ b/arch/arm/mach-sunxi/board.c
+@@ -175,6 +175,10 @@ static int gpio_init(void)
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
+ sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
++#elif CONFIG_CONS_INDEX == 6 && defined(CONFIG_MACH_SUN8I_R528)
++ sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 9);
++ sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 9);
++ sunxi_gpio_set_pull(SUNXI_GPE(7), SUNXI_GPIO_PULL_UP);
+ #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
+ !defined(CONFIG_MACH_SUN8I_R40)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN8I_GPG_UART1);
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+index 37ea93715d..281d6a4249 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+@@ -615,6 +615,7 @@ static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
+ { "uart1", 2 }, /* PG6-PG7 */
+ { "uart2", 7 }, /* PB0-PB1 */
+ { "uart3", 7 }, /* PB6-PB7 */
++ { "uart5", 3 }, /* PE6-PE7 */
+ };
+
+ static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = {
+diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
+index b8ca77d031..bdb568af4b 100644
+--- a/include/configs/sunxi-common.h
++++ b/include/configs/sunxi-common.h
+@@ -29,6 +29,9 @@
+ # define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE
+ # define CFG_SYS_NS16550_COM4 SUNXI_UART3_BASE
+ # define CFG_SYS_NS16550_COM5 SUNXI_R_UART_BASE
++#if defined(CONFIG_SUNXI_GEN_NCAT2)
++# define CFG_SYS_NS16550_COM6 SUNXI_UART5_BASE
++#endif
+ #endif
+
+ /* CPU */
+--
+2.20.1
+
--- /dev/null
+From ed5dca10146a654e7861cfb5bce95e2bb216dab5 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sun, 4 Jun 2023 00:13:45 +0200
+Subject: [PATCH 4008/4018] sunxi: add MYIR MYD-YT113X board
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/dts/Makefile | 3 +-
+ arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dts | 68 ++++++++++++++++++++
+ configs/myir_myd_t113x_defconfig | 20 ++++++
+ 3 files changed, 90 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dts
+ create mode 100644 configs/myir_myd_t113x_defconfig
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 440a6976d6..b282d2efd4 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -811,7 +811,8 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
+ sun8i-v3s-licheepi-zero.dtb
+ dtb-$(CONFIG_MACH_SUN8I_R528) += \
+ sun8i-t113s-mangopi-mq-r-t113.dtb \
+- sun8i-t113s-mangopi-mqdual-t113.dtb
++ sun8i-t113s-mangopi-mqdual-t113.dtb \
++ sun8i-t113s-myir-myd-yt113x.dtb
+ dtb-$(CONFIG_MACH_SUN50I_H5) += \
+ sun50i-h5-bananapi-m2-plus.dtb \
+ sun50i-h5-emlid-neutis-n5-devboard.dtb \
+diff --git a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dts b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dts
+new file mode 100644
+index 0000000000..afd0d8f532
+--- /dev/null
++++ b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x.dts
+@@ -0,0 +1,68 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Arm Ltd.
++
++#include <dt-bindings/interrupt-controller/irq.h>
++
++/dts-v1/;
++
++#include "sun8i-t113s.dtsi"
++#include "sunxi-d1s-t113-mangopi-mq-r.dtsi"
++
++/ {
++ model = "MYIR MYD-YT113X";
++ compatible = "myir,myd-yt113x", "myir,myc-yt113x", "allwinner,sun8i-t113s";
++
++ aliases {
++ serial5 = &uart5;
++ };
++
++ chosen {
++ stdout-path = "serial5:115200n8";
++ };
++};
++
++&cpu0 {
++ cpu-supply = <®_vcc_core>;
++};
++
++&cpu1 {
++ cpu-supply = <®_vcc_core>;
++};
++
++&mmc2_pins {
++ bias-pull-up;
++ drive-strength = <40>;
++};
++
++&mmc2 {
++ pinctrl-0 = <&mmc2_pins>;
++ pinctrl-names = "default";
++ vmmc-supply = <®_3v3>;
++ non-removable;
++ bus-width = <4>;
++ status = "okay";
++
++ emmc: emmc@0 {
++ reg = <0>;
++ compatible = "mmc-card";
++ broken-hpi;
++ };
++};
++
++&pio {
++ /omit-if-no-ref/
++ uart5_pins: uart5-pins {
++ pins = "PE6", "PE7";
++ function = "uart5";
++ };
++};
++
++&uart5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart5_pins>;
++ status = "okay";
++};
++
++&uart3 {
++ status = "disabled";
++};
+diff --git a/configs/myir_myd_t113x_defconfig b/configs/myir_myd_t113x_defconfig
+new file mode 100644
+index 0000000000..2ae442c3ca
+--- /dev/null
++++ b/configs/myir_myd_t113x_defconfig
+@@ -0,0 +1,20 @@
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-myir-myd-yt113x"
++CONFIG_SUNXI_MINIMUM_DRAM_MB=128
++CONFIG_SPL=y
++CONFIG_MACH_SUN8I_R528=y
++CONFIG_CONS_INDEX=6
++CONFIG_MMC0_CD_PIN="PF6"
++CONFIG_MMC_SUNXI_SLOT_EXTRA=2
++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
++CONFIG_SYS_MONITOR_LEN=786432
++CONFIG_DRAM_CLK=792
++CONFIG_DRAM_ZQ=8092667
++CONFIG_DRAM_SUNXI_ODT_EN=0
++CONFIG_DRAM_SUNXI_TPR0=0x004a2195
++CONFIG_DRAM_SUNXI_TPR11=0x340000
++CONFIG_DRAM_SUNXI_TPR12=0x46
++CONFIG_DRAM_SUNXI_TPR13=0x34000100
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_OHCI_HCD=y
+--
+2.20.1
+
--- /dev/null
+From e50a38fcd689bb3bc1e6cf191f482dbc179420b3 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sat, 3 Jun 2023 23:57:46 +0200
+Subject: [PATCH 4009/4018] sunxi: add support for UART3 on PE pins
+
+Some boards use Port E pins for muxing the UART3 as console. Add a new
+Kconfig option allowing to select this (mimicking MMC_PINS_PH).
+
+Pinmux taken from https://bbs.aw-ol.com/assets/uploads/files/1648883311844-t113-s3_datasheet_v1.2.pdf
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/mach-sunxi/Kconfig | 6 ++++++
+ arch/arm/mach-sunxi/board.c | 10 ++++++++--
+ arch/riscv/dts/sunxi-d1s-t113.dtsi | 6 ++++++
+ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 4 ++++
+ 4 files changed, 24 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
+index d1acb88704..cd45dde191 100644
+--- a/arch/arm/mach-sunxi/Kconfig
++++ b/arch/arm/mach-sunxi/Kconfig
+@@ -729,6 +729,12 @@ config UART0_PORT_F
+ at the same time, the system can be only booted in the FEL mode.
+ Only enable this if you really know what you are doing.
+
++config UART3_PINS_PE
++ bool "Pins for uart3 are on Port E"
++ ---help---
++ Select this option for boards where uart3 uses the Port E pinmux.
++ (Some T113-S3 boards use uart3 as console.)
++
+ config OLD_SUNXI_KERNEL_COMPAT
+ bool "Enable workarounds for booting old kernels"
+ ---help---
+diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
+index 91de9b6c39..d18880ea5a 100644
+--- a/arch/arm/mach-sunxi/board.c
++++ b/arch/arm/mach-sunxi/board.c
+@@ -168,16 +168,22 @@ static int gpio_init(void)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
+ sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
+ #elif CONFIG_CONS_INDEX == 4 && defined(CONFIG_MACH_SUN8I_R528)
++#if defined(CONFIG_UART3_PINS_PE)
++ sunxi_gpio_set_cfgpin(SUNXI_GPE(8), 5);
++ sunxi_gpio_set_cfgpin(SUNXI_GPE(9), 5);
++ sunxi_gpio_set_pull(SUNXI_GPE(9), SUNXI_GPIO_PULL_UP);
++#else
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(6), 7);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(7), 7);
+ sunxi_gpio_set_pull(SUNXI_GPB(7), SUNXI_GPIO_PULL_UP);
++#endif
+ #elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
+ sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
+ #elif CONFIG_CONS_INDEX == 6 && defined(CONFIG_MACH_SUN8I_R528)
+- sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 9);
+- sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 9);
++ sunxi_gpio_set_cfgpin(SUNXI_GPE(6), 3);
++ sunxi_gpio_set_cfgpin(SUNXI_GPE(7), 3);
+ sunxi_gpio_set_pull(SUNXI_GPE(7), SUNXI_GPIO_PULL_UP);
+ #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN8I) && \
+ !defined(CONFIG_MACH_SUN8I_R40)
+diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi
+index e32112972d..ff8c8d766f 100644
+--- a/arch/riscv/dts/sunxi-d1s-t113.dtsi
++++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi
+@@ -144,6 +144,12 @@
+ function = "uart3";
+ };
+
++ /omit-if-no-ref/
++ uart3_pe_pins: uart3-pe-pins {
++ pins = "PE8", "PE9";
++ function = "uart3";
++ };
++
+ /omit-if-no-ref/
+ uart0_pins: uart0-pins {
+ pins = "PE2", "PE3";
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+index 281d6a4249..3710757608 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c
+@@ -614,7 +614,11 @@ static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = {
+ #endif
+ { "uart1", 2 }, /* PG6-PG7 */
+ { "uart2", 7 }, /* PB0-PB1 */
++#if IS_ENABLED(CONFIG_UART3_PINS_E)
++ { "uart3", 5 }, /* PE8-PE9 */
++#else
+ { "uart3", 7 }, /* PB6-PB7 */
++#endif
+ { "uart5", 3 }, /* PE6-PE7 */
+ };
+
+--
+2.20.1
+
--- /dev/null
+From b1e6908b53c410fafe54a1b0c07f2bfbebcacf5d Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sat, 3 Jun 2023 23:42:33 +0200
+Subject: [PATCH 4010/4018] sunxi: add support for Rongpin RP-T113 board
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/dts/Makefile | 3 +-
+ arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts | 99 ++++++++++++++++++++
+ configs/rongpin_rp_t113_defconfig | 18 ++++
+ 3 files changed, 119 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts
+ create mode 100644 configs/rongpin_rp_t113_defconfig
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index b282d2efd4..418c6a5f6e 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -812,7 +812,8 @@ dtb-$(CONFIG_MACH_SUN8I_V3S) += \
+ dtb-$(CONFIG_MACH_SUN8I_R528) += \
+ sun8i-t113s-mangopi-mq-r-t113.dtb \
+ sun8i-t113s-mangopi-mqdual-t113.dtb \
+- sun8i-t113s-myir-myd-yt113x.dtb
++ sun8i-t113s-myir-myd-yt113x.dtb \
++ sun8i-t113s-rongpin-rp-t113.dtb
+ dtb-$(CONFIG_MACH_SUN50I_H5) += \
+ sun50i-h5-bananapi-m2-plus.dtb \
+ sun50i-h5-emlid-neutis-n5-devboard.dtb \
+diff --git a/arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts b/arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts
+new file mode 100644
+index 0000000000..3f7633210b
+--- /dev/null
++++ b/arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts
+@@ -0,0 +1,99 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Arm Ltd.
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/gpio/gpio.h>
++
++/dts-v1/;
++
++#include "sun8i-t113s.dtsi"
++
++/ {
++ model = "Rongpin RP-T113";
++ compatible = "rongpin,rp-t113", "allwinner,sun8i-t113s";
++
++ aliases {
++ serial3 = &uart3;
++ };
++
++ chosen {
++ stdout-path = "serial3:115200n8";
++ };
++
++ /* board wide 5V supply directly from the USB-C socket */
++ reg_vcc5v: regulator-5v {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc-5v";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ };
++
++ /* SY8008 DC/DC regulator on the board */
++ reg_3v3: regulator-3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc-3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <®_vcc5v>;
++ };
++
++ /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */
++ reg_vcc_core: regulator-core {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc-core";
++ regulator-min-microvolt = <880000>;
++ regulator-max-microvolt = <880000>;
++ vin-supply = <®_vcc5v>;
++ };
++
++ /* XC6206 LDO on the board */
++ reg_avdd2v8: regulator-avdd {
++ compatible = "regulator-fixed";
++ regulator-name = "avdd2v8";
++ regulator-min-microvolt = <2800000>;
++ regulator-max-microvolt = <2800000>;
++ vin-supply = <®_3v3>;
++ };
++};
++
++&cpu0 {
++ cpu-supply = <®_vcc_core>;
++};
++
++&cpu1 {
++ cpu-supply = <®_vcc_core>;
++};
++
++&pio {
++ vcc-pb-supply = <®_3v3>;
++ vcc-pd-supply = <®_3v3>;
++ vcc-pe-supply = <®_avdd2v8>;
++ vcc-pf-supply = <®_3v3>;
++ vcc-pg-supply = <®_3v3>;
++};
++
++&uart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart3_pe_pins>;
++ status = "okay";
++};
++
++&mmc0 {
++ pinctrl-0 = <&mmc0_pins>;
++ pinctrl-names = "default";
++ vmmc-supply = <®_3v3>;
++ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
++ disable-wp;
++ bus-width = <4>;
++ status = "okay";
++};
++
++&mmc2 {
++ pinctrl-0 = <&mmc2_pins>;
++ pinctrl-names = "default";
++ vmmc-supply = <®_3v3>;
++ non-removable;
++ bus-width = <4>;
++ status = "okay";
++};
+diff --git a/configs/rongpin_rp_t113_defconfig b/configs/rongpin_rp_t113_defconfig
+new file mode 100644
+index 0000000000..9b5a5bcd65
+--- /dev/null
++++ b/configs/rongpin_rp_t113_defconfig
+@@ -0,0 +1,18 @@
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-rongpin-rp-t113"
++CONFIG_SUNXI_MINIMUM_DRAM_MB=128
++CONFIG_SPL=y
++CONFIG_MACH_SUN8I_R528=y
++CONFIG_CONS_INDEX=4
++CONFIG_MMC0_CD_PIN="PF6"
++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
++CONFIG_SYS_MONITOR_LEN=786432
++CONFIG_DRAM_CLK=792
++CONFIG_DRAM_ZQ=8092667
++CONFIG_DRAM_SUNXI_ODT_EN=0
++CONFIG_DRAM_SUNXI_TPR0=0x004a2195
++CONFIG_DRAM_SUNXI_TPR11=0x340000
++CONFIG_DRAM_SUNXI_TPR12=0x46
++CONFIG_DRAM_SUNXI_TPR13=0x34000100
++CONFIG_UART3_PINS_PE=y
+--
+2.20.1
+
--- /dev/null
+From d39d26e888a4a4bc3333faed7308598b2cb7c3f8 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sat, 29 Jul 2023 11:23:47 +0200
+Subject: [PATCH 4011/4018] sunxi: add MYIR MYD-YT113X-SPI board
+
+Instead of eMMC, this board sports a 256Mb SPI NAND flash.
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/dts/Makefile | 1 +
+ .../dts/sun8i-t113s-myir-myd-yt113x-spi.dts | 59 +++++++++++++++++++
+ configs/myir_myd_t113x-spi_defconfig | 38 ++++++++++++
+ 3 files changed, 98 insertions(+)
+ create mode 100644 arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts
+ create mode 100644 configs/myir_myd_t113x-spi_defconfig
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 418c6a5f6e..0572f4b8a6 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -813,6 +813,7 @@ dtb-$(CONFIG_MACH_SUN8I_R528) += \
+ sun8i-t113s-mangopi-mq-r-t113.dtb \
+ sun8i-t113s-mangopi-mqdual-t113.dtb \
+ sun8i-t113s-myir-myd-yt113x.dtb \
++ sun8i-t113s-myir-myd-yt113x-spi.dtb \
+ sun8i-t113s-rongpin-rp-t113.dtb
+ dtb-$(CONFIG_MACH_SUN50I_H5) += \
+ sun50i-h5-bananapi-m2-plus.dtb \
+diff --git a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts
+new file mode 100644
+index 0000000000..f72bab29a6
+--- /dev/null
++++ b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts
+@@ -0,0 +1,59 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++// Copyright (C) 2022 Arm Ltd.
++
++#include <dt-bindings/interrupt-controller/irq.h>
++
++/dts-v1/;
++
++#include "sun8i-t113s.dtsi"
++#include "sunxi-d1s-t113-mangopi-mq-r.dtsi"
++
++/ {
++ model = "MYIR MYD-YT113X (SPI)";
++ compatible = "myir,myd-yt113x", "myir,myc-yt113x", "allwinner,sun8i-t113s";
++
++ aliases {
++ serial5 = &uart5;
++ };
++
++ chosen {
++ stdout-path = "serial5:115200n8";
++ };
++};
++
++&cpu0 {
++ cpu-supply = <®_vcc_core>;
++};
++
++&cpu1 {
++ cpu-supply = <®_vcc_core>;
++};
++
++&pio {
++ /omit-if-no-ref/
++ uart5_pins: uart5-pins {
++ pins = "PE6", "PE7";
++ function = "uart5";
++ };
++};
++
++&uart5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart5_pins>;
++ status = "okay";
++};
++
++&uart3 {
++ status = "disabled";
++};
++
++&spi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi0_pins>;
++ status = "okay";
++ spi_nand@0 {
++ compatible = "spi-nand";
++ reg = <0>;
++ spi-max-frequency = <52000000>;
++ };
++};
+diff --git a/configs/myir_myd_t113x-spi_defconfig b/configs/myir_myd_t113x-spi_defconfig
+new file mode 100644
+index 0000000000..a433fe0449
+--- /dev/null
++++ b/configs/myir_myd_t113x-spi_defconfig
+@@ -0,0 +1,38 @@
++CONFIG_ARM=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_DEFAULT_DEVICE_TREE="sun8i-t113s-myir-myd-yt113x-spi"
++CONFIG_SUNXI_MINIMUM_DRAM_MB=128
++CONFIG_SPL=y
++CONFIG_SPL_SPI_SUNXI=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_MACH_SUN8I_R528=y
++CONFIG_CONS_INDEX=6
++CONFIG_MMC0_CD_PIN="PF6"
++# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
++CONFIG_SYS_MONITOR_LEN=786432
++CONFIG_DRAM_CLK=792
++CONFIG_DRAM_ZQ=8092667
++CONFIG_DRAM_SUNXI_ODT_EN=0
++CONFIG_DRAM_SUNXI_TPR0=0x004a2195
++CONFIG_DRAM_SUNXI_TPR11=0x340000
++CONFIG_DRAM_SUNXI_TPR12=0x46
++CONFIG_DRAM_SUNXI_TPR13=0x34000100
++CONFIG_CLK_SUN20I_D1=y
++CONFIG_PHY_MOTORCOMM=y
++CONFIG_SUN8I_EMAC=y
++CONFIG_RGMII=y
++CONFIG_RMII=y
++CONFIG_MTD=y
++CONFIG_DM_MTD=y
++CONFIG_SYS_MTDPARTS_RUNTIME=y
++CONFIG_NAND_STM32_FMC2=y
++CONFIG_SYS_NAND_ONFI_DETECTION=y
++CONFIG_MTD_SPI_NAND=y
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH_MACRONIX=y
++CONFIG_SPI_FLASH_SPANSION=y
++CONFIG_SPI_FLASH_STMICRO=y
++CONFIG_SPI_FLASH_WINBOND=y
++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
++CONFIG_SPI_FLASH_MTD=y
++CONFIG_SPI=y
+--
+2.20.1
+
--- /dev/null
+From b843c0563d331c591a5dfd18c17c76b4dff12695 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sat, 29 Jul 2023 11:29:26 +0200
+Subject: [PATCH 4012/4018] sunxi: add support for emac on PG pins
+
+Some boards use Port G pins for muxing EMAC.
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/riscv/dts/sunxi-d1s-t113.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi
+index ff8c8d766f..44d3523059 100644
+--- a/arch/riscv/dts/sunxi-d1s-t113.dtsi
++++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi
+@@ -113,6 +113,14 @@
+ function = "emac";
+ };
+
++ /omit-if-no-ref/
++ rgmii_pg_pins: rgmii-pg-pins {
++ pins = "PG0", "PG1", "PG2", "PG3", "PG4",
++ "PG5", "PG6", "PG7", "PG8", "PG9",
++ "PG11", "PG12", "PG13", "PG14", "PG15";
++ function = "emac";
++ };
++
+ /omit-if-no-ref/
+ rmii_pe_pins: rmii-pe-pins {
+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
+--
+2.20.1
+
--- /dev/null
+From d000fc9c1837dd627e01950dc8a60008ce5edbdf Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sat, 29 Jul 2023 11:34:19 +0200
+Subject: [PATCH 4013/4018] sunxi: add ethernet support on MYIR MYD-YT113X-SPI
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ .../dts/sun8i-t113s-myir-myd-yt113x-spi.dts | 34 +++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+diff --git a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts
+index f72bab29a6..431d5593d6 100644
+--- a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts
++++ b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts
+@@ -19,6 +19,23 @@
+ chosen {
+ stdout-path = "serial5:115200n8";
+ };
++
++ reg_vcc5v: regulator-5v {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc-5v";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ };
++
++ /* SY8008 DC/DC regulator on the board */
++ reg_3v3: regulator-3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc-3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <®_vcc5v>;
++ };
+ };
+
+ &cpu0 {
+@@ -57,3 +74,20 @@
+ spi-max-frequency = <52000000>;
+ };
+ };
++
++&emac {
++ pinctrl-names = "default";
++ pinctrl-0 = <&rgmii_pg_pins>;
++ phy-supply = <®_3v3>;
++ phy-handle = <&ext_rgmii_phy>;
++ phy-mode = "rgmii-id";
++
++ status = "okay";
++};
++
++&mdio {
++ ext_rgmii_phy: ethernet-phy@4 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <4>;
++ };
++};
+--
+2.20.1
+
--- /dev/null
+From d771b39a2439f29ce4d6e0031cfc57abf54d0e4e Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sun, 4 Jun 2023 15:40:42 +0200
+Subject: [PATCH 4014/4018] sunxi: enable emac on Rongpin RP-T113
+
+The emac is connected to an IC+ IP101 PHY, for which the driver
+has been re-added (it was removed in 2014).
+
+Currently the driver init fails with the below, so further tweaking
+will be required.
+
+CPU: Allwinner R528 (SUN8I)
+Model: Rongpin RP-T113
+DRAM: 128 MiB
+Core: 36 devices, 15 uclasses, devicetree: separate
+MMC: mmc@4020000: 0, mmc@4022000: 1
+Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
+In: serial@2500c00
+Out: serial@2500c00
+Err: serial@2500c00
+Net: eth_sun8i_emac ethernet@4500000: failed to get TX clock
+No ethernet found.
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts | 28 ++++++++++++++++++++
+ configs/rongpin_rp_t113_defconfig | 3 +++
+ 2 files changed, 31 insertions(+)
+
+diff --git a/arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts b/arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts
+index 3f7633210b..348ae5eec6 100644
+--- a/arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts
++++ b/arch/arm/dts/sun8i-t113s-rongpin-rp-t113.dts
+@@ -55,6 +55,16 @@
+ regulator-max-microvolt = <2800000>;
+ vin-supply = <®_3v3>;
+ };
++
++ reg_gmac_3v3: gmac-3v3 {
++ compatible = "regulator-fixed";
++ regulator-name = "gmac-3v3";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ startup-delay-us = <100000>;
++ enable-active-high;
++ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++ };
+ };
+
+ &cpu0 {
+@@ -79,6 +89,17 @@
+ status = "okay";
+ };
+
++&emac {
++ pinctrl-names = "default";
++ pinctrl-0 = <&rmii_pe_pins>;
++
++ phy-supply = <®_3v3>;
++ phy-handle = <&ext_rgmii_phy>;
++ phy-mode = "rmii";
++
++ status = "okay";
++};
++
+ &mmc0 {
+ pinctrl-0 = <&mmc0_pins>;
+ pinctrl-names = "default";
+@@ -97,3 +118,10 @@
+ bus-width = <4>;
+ status = "okay";
+ };
++
++&mdio {
++ ext_rgmii_phy: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <1>;
++ };
++};
+diff --git a/configs/rongpin_rp_t113_defconfig b/configs/rongpin_rp_t113_defconfig
+index 9b5a5bcd65..e234934f50 100644
+--- a/configs/rongpin_rp_t113_defconfig
++++ b/configs/rongpin_rp_t113_defconfig
+@@ -16,3 +16,6 @@ CONFIG_DRAM_SUNXI_TPR11=0x340000
+ CONFIG_DRAM_SUNXI_TPR12=0x46
+ CONFIG_DRAM_SUNXI_TPR13=0x34000100
+ CONFIG_UART3_PINS_PE=y
++CONFIG_SUN8I_EMAC=y
++CONFIG_PHY_ICPLUS=y
++CONFIG_RMII=y
+--
+2.20.1
+
--- /dev/null
+From 17b7430b6b1b2e4b50369cb688fbfe3b1472aaef Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Mon, 5 Jun 2023 17:57:15 +0200
+Subject: [PATCH 4015/4018] sunxi: enable gmac on MYIR MYD-YT113X with the
+ YT8531 PHY
+
+The gmac is connected to a Motorcomm YT8531, for which the driver
+has been picked from Starfive and ported over.
+
+Support is not yet added in DTS, only for compile testing.
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ configs/myir_myd_t113x_defconfig | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/configs/myir_myd_t113x_defconfig b/configs/myir_myd_t113x_defconfig
+index 2ae442c3ca..8bffcb7acd 100644
+--- a/configs/myir_myd_t113x_defconfig
++++ b/configs/myir_myd_t113x_defconfig
+@@ -18,3 +18,12 @@ CONFIG_DRAM_SUNXI_TPR12=0x46
+ CONFIG_DRAM_SUNXI_TPR13=0x34000100
+ CONFIG_USB_EHCI_HCD=y
+ CONFIG_USB_OHCI_HCD=y
++CONFIG_PHY_MOTORCOMM=y
++CONFIG_SUN8I_EMAC=y
++CONFIG_RGMII=y
++CONFIG_RMII=y
++CONFIG_SUPPORT_EMMC_BOOT=y
++CONFIG_MMC_IO_VOLTAGE=y
++CONFIG_SPL_MMC_IO_VOLTAGE=y
++CONFIG_MMC_HS200_SUPPORT=y
++CONFIG_SPL_MMC_HS200_SUPPORT=y
+--
+2.20.1
+
--- /dev/null
+From 765140fa293f719cb11346a8b0474f78310a785f Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sat, 26 Aug 2023 17:45:03 +0200
+Subject: [PATCH 4016/4018] arm: dts: add partition table for MYIR
+ MYD-YT113X-SPI
+
+The original bootloader reports the following as the partition table:
+
+device nand0 <nand>, # parts = 4
+ #: name size offset mask_flags
+ 0: boot0 0x00100000 0x00000000 1
+ 1: uboot 0x00300000 0x00100000 1
+ 2: secure_storage 0x00100000 0x00400000 1
+ 3: sys 0x0fb00000 0x00500000 0
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ .../dts/sun8i-t113s-myir-myd-yt113x-spi.dts | 26 +++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts
+index 431d5593d6..a5fd8c6bea 100644
+--- a/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts
++++ b/arch/arm/dts/sun8i-t113s-myir-myd-yt113x-spi.dts
+@@ -72,6 +72,32 @@
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "boot0";
++ reg = <0x0 0x100000>;
++ };
++
++ partition@100000 {
++ label = "uboot";
++ reg = <0x0 0x300000>;
++ };
++
++ partition@400000 {
++ label = "secure_storage";
++ reg = <0x0 0x400000>;
++ };
++
++ partition@500000 {
++ label = "sys";
++ reg = <0x0 0xfb00000>;
++ };
++ };
+ };
+ };
+
+--
+2.20.1
+
--- /dev/null
+From 0922f4d0e26eb573bd3214391993883937d2de93 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sat, 26 Aug 2023 17:46:22 +0200
+Subject: [PATCH 4017/4018] configs: enable UBI support for MYIR MYD-YT113X-SPI
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ configs/myir_myd_t113x-spi_defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/configs/myir_myd_t113x-spi_defconfig b/configs/myir_myd_t113x-spi_defconfig
+index a433fe0449..a1c2a82c87 100644
+--- a/configs/myir_myd_t113x-spi_defconfig
++++ b/configs/myir_myd_t113x-spi_defconfig
+@@ -36,3 +36,4 @@ CONFIG_SPI_FLASH_WINBOND=y
+ # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+ CONFIG_SPI_FLASH_MTD=y
+ CONFIG_SPI=y
++CONFIG_MTD_UBI_FASTMAP=y
+--
+2.20.1
+
--- /dev/null
+From e01de46856ec0d86a0e193dae2a9e2e0c6fa28b1 Mon Sep 17 00:00:00 2001
+From: Zoltan HERPAI <wigyori@uid0.hu>
+Date: Sat, 26 Aug 2023 21:09:17 +0200
+Subject: [PATCH 4018/4018] sunxi: r528/d1/t113: add SDC2 pinmux on PC2-7 pins
+
+Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
+---
+ board/sunxi/board.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/board/sunxi/board.c b/board/sunxi/board.c
+index 8c12c8dead..f23908ed13 100644
+--- a/board/sunxi/board.c
++++ b/board/sunxi/board.c
+@@ -422,6 +422,13 @@ static void mmc_pinmux_setup(int sdc)
+ sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
+ sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
++#elif defined(CONFIG_MACH_SUN8I_R528)
++ /* SDC2: PC2-PC7 */
++ for (pin = SUNXI_GPC(2); pin <= SUNXI_GPC(7); pin++) {
++ sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
++ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
++ sunxi_gpio_set_drv(pin, 2);
++ }
+ #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
+ /* SDC2: PC5-PC6, PC8-PC16 */
+ for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
+--
+2.20.1
+
--- /dev/null
+setenv fdt_high ffffffff
+setenv mmc_rootpart 2
+part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid
+setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage
+setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb
+setenv bootargs console=ttyS3,115200 earlyprintk root=PARTUUID=${uuid} rootwait
+setenv uenvcmd run loadkernel \&\& run loaddtb \&\& bootm \$kernel_addr_r - \$fdt_addr_r
+run uenvcmd
--- /dev/null
+setenv fdt_high ffffffff
+setenv mmc_rootpart 2
+part uuid mmc ${mmc_bootdev}:${mmc_rootpart} uuid
+setenv loadkernel fatload mmc \$mmc_bootdev \$kernel_addr_r uImage
+setenv loaddtb fatload mmc \$mmc_bootdev \$fdt_addr_r dtb
+setenv bootargs console=ttyS5,115200 earlyprintk root=PARTUUID=${uuid} rootwait
+setenv uenvcmd run loadkernel \&\& run loaddtb \&\& bootm \$kernel_addr_r - \$fdt_addr_r
+run uenvcmd
projects / openwrt / staging / wigyori.git / commitdiff