ARM: dts: uniphier: sync with Linux 4.17-rc6
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Tue, 22 May 2018 15:30:54 +0000 (00:30 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Tue, 22 May 2018 15:32:39 +0000 (00:32 +0900)
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
arch/arm/dts/uniphier-ld11.dtsi
arch/arm/dts/uniphier-ld20-ref.dts
arch/arm/dts/uniphier-ld20.dtsi
arch/arm/dts/uniphier-pxs3.dtsi

index 577803bd62db679cec7b2738360810166a9e2633..e7514f01fa0788fe5af31d86e04badf481f6d804 100644 (file)
                        mmc-ddr-1_8v;
                        mmc-hs200-1_8v;
                        mmc-pwrseq = <&emmc_pwrseq>;
-                       cdns,phy-input-delay-legacy = <4>;
+                       cdns,phy-input-delay-legacy = <9>;
                        cdns,phy-input-delay-mmc-highspeed = <2>;
                        cdns,phy-input-delay-mmc-ddr = <3>;
                        cdns,phy-dll-delay-sdclk = <21>;
index 2c1a92fafbfbe053808b00e4b8b66804f6744e4d..440c2e6a638b998c163b3f8aea91f94e115f516b 100644 (file)
                reg = <0>;
        };
 };
+
+&pinctrl_ether_rgmii {
+       tx {
+               pins = "RGMII_TXCLK", "RGMII_TXD0", "RGMII_TXD1",
+                      "RGMII_TXD2", "RGMII_TXD3", "RGMII_TXCTL";
+               drive-strength = <9>;
+       };
+};
index b36adb9ef8ab8238757b5efda9b6290486ebf4ff..31bc124dfca7f98e79a39e40de4ca595ec831284 100644 (file)
                        mmc-ddr-1_8v;
                        mmc-hs200-1_8v;
                        mmc-pwrseq = <&emmc_pwrseq>;
-                       cdns,phy-input-delay-legacy = <4>;
+                       cdns,phy-input-delay-legacy = <9>;
                        cdns,phy-input-delay-mmc-highspeed = <2>;
                        cdns,phy-input-delay-mmc-ddr = <3>;
                        cdns,phy-dll-delay-sdclk = <21>;
index 7b511656b2f4877c10e03ef0e03773c1dd1b25ca..ae867cbb0acbe09bd9a56f7490e393701ed468d7 100644 (file)
                        mmc-ddr-1_8v;
                        mmc-hs200-1_8v;
                        mmc-pwrseq = <&emmc_pwrseq>;
-                       cdns,phy-input-delay-legacy = <4>;
+                       cdns,phy-input-delay-legacy = <9>;
                        cdns,phy-input-delay-mmc-highspeed = <2>;
                        cdns,phy-input-delay-mmc-ddr = <3>;
                        cdns,phy-dll-delay-sdclk = <21>;