/*.patch
/llvm-bpf*
key-build*
+private-key.pem
+public-key.pem
*.orig
*.rej
*~
bool "Enable TLS certificate verification during package download"
default y
+ config USE_APK
+ bool "Use APK instead of OPKG to build distribution (EXPERIMENTAL)"
+
comment "General build options"
config TESTING_KERNEL
config STRIP_KERNEL_EXPORTS
bool "Strip unnecessary exports from the kernel image"
+ depends on !LINUX_6_6
help
Reduces kernel size by stripping unused kernel exports from the kernel
image. Note that this might make the kernel incompatible with any kernel
This will compile your kernel and modules with debug information.
config KERNEL_DEBUG_INFO_BTF
-
bool "Enable additional BTF type information"
depends on !HOST_OS_MACOS
depends on KERNEL_DEBUG_INFO && !KERNEL_DEBUG_INFO_REDUCED
Required to run BPF CO-RE applications.
+config KERNEL_DEBUG_INFO_BTF_MODULES
+ def_bool y
+ depends on KERNEL_DEBUG_INFO_BTF
+
config KERNEL_MODULE_ALLOW_BTF_MISMATCH
bool "Allow loading modules with non-matching BTF type info"
- depends on KERNEL_DEBUG_INFO_BTF
+ depends on KERNEL_DEBUG_INFO_BTF_MODULES
help
For modules whose split BTF does not match vmlinux, load without
BTF rather than refusing to load. The default behavior with
$(foreach dir,$(PACKAGE_SUBDIRS), \
$(foreach pkg,$(1), $(dir)/$(pkg)_*.ipk)))
+apk_package_files = $(wildcard \
+ $(foreach dir,$(PACKAGE_SUBDIRS), \
+ $(foreach pkg,$(1), $(dir)/$(pkg)_*.apk)))
+
# 1: package name
define FeedPackageDir
$(strip $(if $(CONFIG_PER_FEED_REPO), \
endef
# 1: destination file
-define FeedSourcesAppend
+define FeedSourcesAppendOPKG
( \
echo 'src/gz %d_core %U/targets/%S/packages'; \
$(strip $(if $(CONFIG_PER_FEED_REPO), \
) >> $(1)
endef
+# 1: destination file
+define FeedSourcesAppendAPK
+( \
+ echo '%U/targets/%S/packages/packages.adb'; \
+ $(strip $(if $(CONFIG_PER_FEED_REPO), \
+ echo '%U/packages/%A/base/packages.adb'; \
+ $(if $(filter %SNAPSHOT-y,$(VERSION_NUMBER)-$(CONFIG_BUILDBOT)), \
+ echo '%U/targets/%S/kmods/$(LINUX_VERSION)-$(LINUX_RELEASE)-$(LINUX_VERMAGIC)/packages.adb';) \
+ $(foreach feed,$(FEEDS_AVAILABLE), \
+ $(if $(CONFIG_FEED_$(feed)), \
+ echo '$(if $(filter m,$(CONFIG_FEED_$(feed))),# )%U/packages/%A/$(feed)/packages.adb';)))) \
+) >> $(1)
+endef
+
# 1: package name
define GetABISuffix
$(if $(ABIV_$(1)),$(ABIV_$(1)),$(call FormatABISuffix,$(1),$(foreach v,$(wildcard $(STAGING_DIR)/pkginfo/$(1).version),$(shell cat $(v)))))
_host_target:=$(if $(HOST_QUILT),,.)
Host/Patch:=$(Host/Patch/Default)
-ifneq ($(strip $(HOST_UNPACK)),)
- define Host/Prepare/Default
- $(HOST_UNPACK)
+define Host/Prepare/Default
+ $(if $(strip $(HOST_UNPACK)),$(HOST_UNPACK))
[ ! -d ./src/ ] || $(CP) ./src/* $(HOST_BUILD_DIR)
$(Host/Patch)
- endef
-endif
+endef
define Host/Prepare
$(call Host/Prepare/Default)
endef
define Image/Manifest
- $(call opkg,$(TARGET_DIR_ORIG)) list-installed > \
- $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).manifest
+ $(if $(CONFIG_USE_APK), \
+ $(call apk,$(TARGET_DIR_ORIG)) list --quiet --manifest --no-network | sort | sed 's/ / - /' > \
+ $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).manifest, \
+ $(call opkg,$(TARGET_DIR_ORIG)) list-installed > \
+ $(BIN_DIR)/$(IMG_PREFIX)$(if $(PROFILE_SANITIZED),-$(PROFILE_SANITIZED)).manifest \
+ )
ifneq ($(CONFIG_JSON_CYCLONEDX_SBOM),)
$(SCRIPT_DIR)/package-metadata.pl imgcyclonedxsbom \
$(if $(IB),$(TOPDIR)/.packageinfo, $(TMP_DIR)/.packageinfo) \
$(call opkg,$(mkfs_cur_target_dir)) \
-f $(mkfs_cur_target_dir).conf
+apk_target = $(call apk,$(mkfs_cur_target_dir)) --no-scripts
+
+
target-dir-%: FORCE
+ifneq ($(CONFIG_USE_APK),)
+ rm -rf $(mkfs_cur_target_dir)
+ $(CP) $(TARGET_DIR_ORIG) $(mkfs_cur_target_dir)
+ mv $(mkfs_cur_target_dir)/etc/apk/repositories $(mkfs_cur_target_dir).repositories
+ $(if $(mkfs_packages_remove), \
+ $(apk_target) del $(mkfs_packages_remove))
+ $(if $(mkfs_packages_add), \
+ $(apk_target) add $(mkfs_packages_add))
+ mv $(mkfs_cur_target_dir).repositories $(mkfs_cur_target_dir)/etc/apk/repositories
+else
rm -rf $(mkfs_cur_target_dir) $(mkfs_cur_target_dir).opkg
$(CP) $(TARGET_DIR_ORIG) $(mkfs_cur_target_dir)
-mv $(mkfs_cur_target_dir)/etc/opkg $(mkfs_cur_target_dir).opkg
$(call opkg_package_files,$(mkfs_packages_add)))
-$(CP) -T $(mkfs_cur_target_dir).opkg/ $(mkfs_cur_target_dir)/etc/opkg/
rm -rf $(mkfs_cur_target_dir).opkg $(mkfs_cur_target_dir).conf
+endif
$(call prepare_rootfs,$(mkfs_cur_target_dir),$(TOPDIR)/files)
$(KDIR)/root.%: kernel_prepare
-LINUX_VERSION-6.6 = .30
-LINUX_KERNEL_HASH-6.6.30 = b66a5b863b0f8669448b74ca83bd641a856f164b29956e539bbcb5fdeeab9cc6
+LINUX_VERSION-6.6 = .32
+LINUX_KERNEL_HASH-6.6.32 = aaa824eaf07f61911d22b75ff090a403c3dd0bd73e23933e0bba8b5971436ce1
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Copyright (C) 2006-2020 OpenWrt.org
-
-ifndef DUMP
- include $(INCLUDE_DIR)/feeds.mk
-endif
-
-IPKG_REMOVE:= \
- $(SCRIPT_DIR)/ipkg-remove
-
-IPKG_STATE_DIR:=$(TARGET_DIR)/usr/lib/opkg
-
-# Generates a make statement to return a wildcard for candidate ipkg files
-# 1: package name
-define gen_ipkg_wildcard
- $(1)$$(if $$(filter -%,$$(ABIV_$(1))),,[^a-z-])*
-endef
-
-# 1: package name
-# 2: candidate ipk files
-define remove_ipkg_files
- $(if $(strip $(2)),$(IPKG_REMOVE) $(1) $(2))
-endef
-
-# 1: package name
-# 2: variable name
-# 3: variable suffix
-# 4: file is a script
-define BuildIPKGVariable
-ifdef Package/$(1)/$(2)
- $$(IPKG_$(1)) : VAR_$(2)$(3)=$$(Package/$(1)/$(2))
- $(call shexport,Package/$(1)/$(2))
- $(1)_COMMANDS += echo "$$$$$$$$$(call shvar,Package/$(1)/$(2))" > $(2)$(3); $(if $(4),chmod 0755 $(2)$(3);)
-endif
-endef
-
-PARENL :=(
-PARENR :=)
-
-dep_split=$(subst :,$(space),$(1))
-dep_rem=$(subst !,,$(subst $(strip $(PARENL)),,$(subst $(strip $(PARENR)),,$(word 1,$(call dep_split,$(1))))))
-dep_and=dep_and_res:=$$(and $(subst $(space),$(comma),$(foreach cond,$(subst &&, ,$(1)),$$(CONFIG_$(cond)))))
-dep_confvar=$(strip $(foreach cond,$(subst ||, ,$(call dep_rem,$(1))),$(eval $(call dep_and,$(cond)))$(dep_and_res)))
-dep_pos=$(if $(call dep_confvar,$(1)),$(call dep_val,$(1)))
-dep_neg=$(if $(call dep_confvar,$(1)),,$(call dep_val,$(1)))
-dep_if=$(if $(findstring !,$(1)),$(call dep_neg,$(1)),$(call dep_pos,$(1)))
-dep_val=$(word 2,$(call dep_split,$(1)))
-strip_deps=$(strip $(subst +,,$(filter-out @%,$(1))))
-filter_deps=$(foreach dep,$(call strip_deps,$(1)),$(if $(findstring :,$(dep)),$(call dep_if,$(dep)),$(dep)))
-
-define AddDependency
- $$(if $(1),$$(if $(2),$$(foreach pkg,$(1),$$(IPKG_$$(pkg))): $$(foreach pkg,$(2),$$(IPKG_$$(pkg)))))
-endef
-
-define FixupReverseDependencies
- DEPS := $$(filter %:$(1),$$(IDEPEND))
- DEPS := $$(patsubst %:$(1),%,$$(DEPS))
- DEPS := $$(filter $$(DEPS),$$(IPKGS))
- $(call AddDependency,$$(DEPS),$(1))
-endef
-
-define FixupDependencies
- DEPS := $$(filter $(1):%,$$(IDEPEND))
- DEPS := $$(patsubst $(1):%,%,$$(DEPS))
- DEPS := $$(filter $$(DEPS),$$(IPKGS))
- $(call AddDependency,$(1),$$(DEPS))
-endef
-
-ifneq ($(PKG_NAME),toolchain)
- define CheckDependencies
- @( \
- rm -f $(PKG_INFO_DIR)/$(1).missing; \
- ( \
- export \
- READELF=$(TARGET_CROSS)readelf \
- OBJCOPY=$(TARGET_CROSS)objcopy \
- XARGS="$(XARGS)"; \
- $(SCRIPT_DIR)/gen-dependencies.sh "$$(IDIR_$(1))"; \
- ) | while read FILE; do \
- grep -qxF "$$$$FILE" $(PKG_INFO_DIR)/$(1).provides || \
- echo "$$$$FILE" >> $(PKG_INFO_DIR)/$(1).missing; \
- done; \
- if [ -f "$(PKG_INFO_DIR)/$(1).missing" ]; then \
- echo "Package $(1) is missing dependencies for the following libraries:" >&2; \
- cat "$(PKG_INFO_DIR)/$(1).missing" >&2; \
- false; \
- fi; \
- )
- endef
-endif
-
-_addsep=$(word 1,$(1))$(foreach w,$(wordlist 2,$(words $(1)),$(1)),$(strip $(2) $(w)))
-_cleansep=$(subst $(space)$(2)$(space),$(2)$(space),$(1))
-mergelist=$(call _cleansep,$(call _addsep,$(1),$(comma)),$(comma))
-addfield=$(if $(strip $(2)),$(1): $(2))
-_define=define
-_endef=endef
-
-ifeq ($(DUMP),)
- define BuildTarget/ipkg
- ABIV_$(1):=$(call FormatABISuffix,$(1),$(ABI_VERSION))
- PDIR_$(1):=$(call FeedPackageDir,$(1))
- IPKG_$(1):=$$(PDIR_$(1))/$(1)$$(ABIV_$(1))_$(VERSION)_$(PKGARCH).ipk
- IDIR_$(1):=$(PKG_BUILD_DIR)/ipkg-$(PKGARCH)/$(1)
- KEEP_$(1):=$(strip $(call Package/$(1)/conffiles))
-
- TARGET_VARIANT:=$$(if $(ALL_VARIANTS),$$(if $$(VARIANT),$$(filter-out *,$$(VARIANT)),$(firstword $(ALL_VARIANTS))))
- ifeq ($(BUILD_VARIANT),$$(if $$(TARGET_VARIANT),$$(TARGET_VARIANT),$(BUILD_VARIANT)))
- do_install=
- ifdef Package/$(1)/install
- do_install=yes
- endif
- ifdef Package/$(1)/install-overlay
- do_install=yes
- endif
- ifdef do_install
- ifneq ($(CONFIG_PACKAGE_$(1))$(DEVELOPER),)
- IPKGS += $(1)
- $(_pkg_target)compile: $$(IPKG_$(1)) $(PKG_INFO_DIR)/$(1).provides $(PKG_BUILD_DIR)/.pkgdir/$(1).installed
- prepare-package-install: $$(IPKG_$(1))
- compile: $(STAGING_DIR_ROOT)/stamp/.$(1)_installed
- else
- $(if $(CONFIG_PACKAGE_$(1)),$$(info WARNING: skipping $(1) -- package not selected))
- endif
-
- .PHONY: $(PKG_INSTALL_STAMP).$(1)
- ifeq ($(CONFIG_PACKAGE_$(1)),y)
- compile: $(PKG_INSTALL_STAMP).$(1)
- endif
- $(PKG_INSTALL_STAMP).$(1): prepare-package-install
- echo "$(1)" >> $(PKG_INSTALL_STAMP)
- else
- $(if $(CONFIG_PACKAGE_$(1)),$$(warning WARNING: skipping $(1) -- package has no install section))
- endif
- endif
-
- DEPENDS:=$(call PKG_FIXUP_DEPENDS,$(1),$(DEPENDS))
- IDEPEND_$(1):=$$(call filter_deps,$$(DEPENDS))
- IDEPEND += $$(patsubst %,$(1):%,$$(IDEPEND_$(1)))
- $(FixupDependencies)
- $(FixupReverseDependencies)
-
- $(eval $(call BuildIPKGVariable,$(1),conffiles))
- $(eval $(call BuildIPKGVariable,$(1),preinst,,1))
- $(eval $(call BuildIPKGVariable,$(1),postinst,-pkg,1))
- $(eval $(call BuildIPKGVariable,$(1),prerm,-pkg,1))
- $(eval $(call BuildIPKGVariable,$(1),postrm,,1))
-
- $(PKG_BUILD_DIR)/.pkgdir/$(1).installed : export PATH=$$(TARGET_PATH_PKG)
- $(PKG_BUILD_DIR)/.pkgdir/$(1).installed: $(STAMP_BUILT)
- rm -rf $$@ $(PKG_BUILD_DIR)/.pkgdir/$(1)
- mkdir -p $(PKG_BUILD_DIR)/.pkgdir/$(1)
- $(call Package/$(1)/install,$(PKG_BUILD_DIR)/.pkgdir/$(1))
- $(call Package/$(1)/install_lib,$(PKG_BUILD_DIR)/.pkgdir/$(1))
- touch $$@
-
- $(STAGING_DIR_ROOT)/stamp/.$(1)_installed: $(PKG_BUILD_DIR)/.pkgdir/$(1).installed
- mkdir -p $(STAGING_DIR_ROOT)/stamp
- $(if $(ABI_VERSION),echo '$(ABI_VERSION)' | cmp -s - $(PKG_INFO_DIR)/$(1).version || { \
- echo '$(ABI_VERSION)' > $(PKG_INFO_DIR)/$(1).version; \
- $(foreach pkg,$(filter-out $(1),$(PROVIDES)), \
- cp $(PKG_INFO_DIR)/$(1).version $(PKG_INFO_DIR)/$(pkg).version; \
- ) \
- } )
- $(call locked,$(CP) $(PKG_BUILD_DIR)/.pkgdir/$(1)/. $(STAGING_DIR_ROOT)/,root-copy)
- touch $$@
-
- Package/$(1)/DEPENDS := $$(call mergelist,$$(foreach dep,$$(filter-out @%,$$(IDEPEND_$(1))),$$(dep)$$(call GetABISuffix,$$(dep))))
- ifneq ($$(EXTRA_DEPENDS),)
- Package/$(1)/DEPENDS := $$(EXTRA_DEPENDS)$$(if $$(Package/$(1)/DEPENDS),$$(comma) $$(Package/$(1)/DEPENDS))
- endif
-
-$(_define) Package/$(1)/CONTROL
-Package: $(1)$$(ABIV_$(1))
-Version: $(VERSION)
-$$(call addfield,Depends,$$(Package/$(1)/DEPENDS)
-)$$(call addfield,Conflicts,$$(call mergelist,$(CONFLICTS))
-)$$(call addfield,Provides,$$(call mergelist,$$(filter-out $(1)$$(ABIV_$(1)),$(PROVIDES)$$(if $$(ABIV_$(1)), $(1) $(foreach provide,$(PROVIDES),$(provide)$$(ABIV_$(1))))))
-)$$(call addfield,Alternatives,$$(call mergelist,$(ALTERNATIVES))
-)$$(call addfield,Source,$(SOURCE)
-)$$(call addfield,SourceName,$(PKG_NAME)
-)$$(call addfield,License,$(LICENSE)
-)$$(call addfield,LicenseFiles,$(LICENSE_FILES)
-)$$(call addfield,Section,$(SECTION)
-)$$(call addfield,Require-User,$(USERID)
-)$$(call addfield,SourceDateEpoch,$(PKG_SOURCE_DATE_EPOCH)
-)$$(call addfield,URL,$(URL)
-)$$(if $$(ABIV_$(1)),ABIVersion: $$(ABIV_$(1))
-)$(if $(PKG_CPE_ID),CPE-ID: $(PKG_CPE_ID)
-)$(if $(filter hold,$(PKG_FLAGS)),Status: unknown hold not-installed
-)$(if $(filter essential,$(PKG_FLAGS)),Essential: yes
-)$(if $(MAINTAINER),Maintainer: $(MAINTAINER)
-)Architecture: $(PKGARCH)
-Installed-Size: 0
-$(_endef)
-
- $$(IPKG_$(1)) : export CONTROL=$$(Package/$(1)/CONTROL)
- $$(IPKG_$(1)) : export DESCRIPTION=$$(Package/$(1)/description)
- $$(IPKG_$(1)) : export PATH=$$(TARGET_PATH_PKG)
- $$(IPKG_$(1)) : export PKG_SOURCE_DATE_EPOCH:=$(PKG_SOURCE_DATE_EPOCH)
- $(PKG_INFO_DIR)/$(1).provides $$(IPKG_$(1)): $(STAMP_BUILT) $(INCLUDE_DIR)/package-ipkg.mk
- @rm -rf $$(IDIR_$(1)); \
- $$(call remove_ipkg_files,$(1),$$(call opkg_package_files,$(call gen_ipkg_wildcard,$(1))))
- mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1))/CONTROL $(PKG_INFO_DIR)
- $(call Package/$(1)/install,$$(IDIR_$(1)))
- $(if $(Package/$(1)/install-overlay),mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1))/rootfs-overlay)
- $(call Package/$(1)/install-overlay,$$(IDIR_$(1))/rootfs-overlay)
- -find $$(IDIR_$(1)) -name 'CVS' -o -name '.svn' -o -name '.#*' -o -name '*~'| $(XARGS) rm -rf
- @( \
- find $$(IDIR_$(1)) -name lib\*.so\* -or -name \*.ko | awk -F/ '{ print $$$$NF }'; \
- for file in $$(patsubst %,$(PKG_INFO_DIR)/%.provides,$$(IDEPEND_$(1))); do \
- if [ -f "$$$$file" ]; then \
- cat $$$$file; \
- fi; \
- done; $(Package/$(1)/extra_provides) \
- ) | sort -u > $(PKG_INFO_DIR)/$(1).provides
- $(if $(PROVIDES),@for pkg in $(filter-out $(1),$(PROVIDES)); do cp $(PKG_INFO_DIR)/$(1).provides $(PKG_INFO_DIR)/$$$$pkg.provides; done)
- $(CheckDependencies)
-
- $(RSTRIP) $$(IDIR_$(1))
-
- ifneq ($$(CONFIG_IPK_FILES_CHECKSUMS),)
- (cd $$(IDIR_$(1)); \
- ( \
- find . -type f \! -path ./CONTROL/\* -exec $(MKHASH) sha256 -n \{\} \; 2> /dev/null | \
- sed 's|\([[:blank:]]\)\./| \1/|' > $$(IDIR_$(1))/CONTROL/files-sha256sum \
- ) || true \
- )
- endif
- (cd $$(IDIR_$(1))/CONTROL; \
- ( \
- echo "$$$$CONTROL"; \
- printf "Description: "; echo "$$$$DESCRIPTION" | sed -e 's,^[[:space:]]*, ,g'; \
- ) > control; \
- chmod 644 control; \
- ( \
- echo "#!/bin/sh"; \
- echo "[ \"\$$$${IPKG_NO_SCRIPT}\" = \"1\" ] && exit 0"; \
- echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
- echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
- echo "default_postinst \$$$$0 \$$$$@"; \
- ) > postinst; \
- ( \
- echo "#!/bin/sh"; \
- echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
- echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
- echo "default_prerm \$$$$0 \$$$$@"; \
- ) > prerm; \
- chmod 0755 postinst prerm; \
- $($(1)_COMMANDS) \
- )
-
- ifneq ($$(KEEP_$(1)),)
- @( \
- keepfiles=""; \
- for x in $$(KEEP_$(1)); do \
- [ -f "$$(IDIR_$(1))/$$$$x" ] || keepfiles="$$$${keepfiles:+$$$$keepfiles }$$$$x"; \
- done; \
- [ -z "$$$$keepfiles" ] || { \
- mkdir -p $$(IDIR_$(1))/lib/upgrade/keep.d; \
- for x in $$$$keepfiles; do echo $$$$x >> $$(IDIR_$(1))/lib/upgrade/keep.d/$(1); done; \
- }; \
- )
- endif
-
- $(INSTALL_DIR) $$(PDIR_$(1))
- $(FAKEROOT) $(STAGING_DIR_HOST)/bin/bash $(SCRIPT_DIR)/ipkg-build -m "$(FILE_MODES)" $$(IDIR_$(1)) $$(PDIR_$(1))
- @[ -f $$(IPKG_$(1)) ]
-
- $(1)-clean:
- $$(call remove_ipkg_files,$(1),$$(call opkg_package_files,$(call gen_ipkg_wildcard,$(1))))
-
- clean: $(1)-clean
-
- endef
-endif
--- /dev/null
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Copyright (C) 2006-2022 OpenWrt.org
+
+ifndef DUMP
+ include $(INCLUDE_DIR)/feeds.mk
+endif
+
+IPKG_STATE_DIR:=$(TARGET_DIR)/usr/lib/opkg
+
+# Generates a make statement to return a wildcard for candidate ipkg files
+# 1: package name
+define gen_package_wildcard
+ $(1)$$(if $$(filter -%,$$(ABIV_$(1))),,[^a-z-])*
+endef
+
+# 1: package name
+# 2: candidate ipk files
+define remove_ipkg_files
+ $(if $(strip $(2)),$(SCRIPT_DIR)/ipkg-remove $(1) $(2))
+endef
+
+# 1: package name
+# 2: variable name
+# 3: variable suffix
+# 4: file is a script
+define BuildPackVariable
+ifdef Package/$(1)/$(2)
+ $$(PACK_$(1)) : VAR_$(2)$(3)=$$(Package/$(1)/$(2))
+ $(call shexport,Package/$(1)/$(2))
+ $(1)_COMMANDS += echo "$$$$$$$$$(call shvar,Package/$(1)/$(2))" > $(2)$(3); $(if $(4),chmod 0755 $(2)$(3);)
+endif
+endef
+
+PARENL :=(
+PARENR :=)
+
+dep_split=$(subst :,$(space),$(1))
+dep_rem=$(subst !,,$(subst $(strip $(PARENL)),,$(subst $(strip $(PARENR)),,$(word 1,$(call dep_split,$(1))))))
+dep_and=dep_and_res:=$$(and $(subst $(space),$(comma),$(foreach cond,$(subst &&, ,$(1)),$$(CONFIG_$(cond)))))
+dep_confvar=$(strip $(foreach cond,$(subst ||, ,$(call dep_rem,$(1))),$(eval $(call dep_and,$(cond)))$(dep_and_res)))
+dep_pos=$(if $(call dep_confvar,$(1)),$(call dep_val,$(1)))
+dep_neg=$(if $(call dep_confvar,$(1)),,$(call dep_val,$(1)))
+dep_if=$(if $(findstring !,$(1)),$(call dep_neg,$(1)),$(call dep_pos,$(1)))
+dep_val=$(word 2,$(call dep_split,$(1)))
+strip_deps=$(strip $(subst +,,$(filter-out @%,$(1))))
+filter_deps=$(foreach dep,$(call strip_deps,$(1)),$(if $(findstring :,$(dep)),$(call dep_if,$(dep)),$(dep)))
+
+define AddDependency
+ $$(if $(1),$$(if $(2),$$(foreach pkg,$(1),$$(PACK_$$(pkg))): $$(foreach pkg,$(2),$$(PACK_$$(pkg)))))
+endef
+
+define FixupReverseDependencies
+ DEPS := $$(filter %:$(1),$$(IDEPEND))
+ DEPS := $$(patsubst %:$(1),%,$$(DEPS))
+ DEPS := $$(filter $$(DEPS),$$(IPKGS))
+ $(call AddDependency,$$(DEPS),$(1))
+endef
+
+define FixupDependencies
+ DEPS := $$(filter $(1):%,$$(IDEPEND))
+ DEPS := $$(patsubst $(1):%,%,$$(DEPS))
+ DEPS := $$(filter $$(DEPS),$$(IPKGS))
+ $(call AddDependency,$(1),$$(DEPS))
+endef
+
+ifneq ($(PKG_NAME),toolchain)
+ define CheckDependencies
+ @( \
+ rm -f $(PKG_INFO_DIR)/$(1).missing; \
+ ( \
+ export \
+ READELF=$(TARGET_CROSS)readelf \
+ OBJCOPY=$(TARGET_CROSS)objcopy \
+ XARGS="$(XARGS)"; \
+ $(SCRIPT_DIR)/gen-dependencies.sh "$$(IDIR_$(1))"; \
+ ) | while read FILE; do \
+ grep -qxF "$$$$FILE" $(PKG_INFO_DIR)/$(1).provides || \
+ echo "$$$$FILE" >> $(PKG_INFO_DIR)/$(1).missing; \
+ done; \
+ if [ -f "$(PKG_INFO_DIR)/$(1).missing" ]; then \
+ echo "Package $(1) is missing dependencies for the following libraries:" >&2; \
+ cat "$(PKG_INFO_DIR)/$(1).missing" >&2; \
+ false; \
+ fi; \
+ )
+ endef
+endif
+
+_addsep=$(word 1,$(1))$(foreach w,$(wordlist 2,$(words $(1)),$(1)),$(strip $(2) $(w)))
+_cleansep=$(subst $(space)$(2)$(space),$(2)$(space),$(1))
+mergelist=$(call _cleansep,$(call _addsep,$(1),$(comma)),$(comma))
+addfield=$(if $(strip $(2)),$(1): $(2))
+_define=define
+_endef=endef
+
+ifeq ($(DUMP),)
+ define BuildTarget/ipkg
+ ABIV_$(1):=$(call FormatABISuffix,$(1),$(ABI_VERSION))
+ PDIR_$(1):=$(call FeedPackageDir,$(1))
+ifeq ($(CONFIG_USE_APK),)
+ PACK_$(1):=$$(PDIR_$(1))/$(1)$$(ABIV_$(1))_$(VERSION)_$(PKGARCH).ipk
+else
+ PACK_$(1):=$$(PDIR_$(1))/$(1)$$(ABIV_$(1))-$(VERSION).apk
+endif
+ IDIR_$(1):=$(PKG_BUILD_DIR)/ipkg-$(PKGARCH)/$(1)
+ ADIR_$(1):=$(PKG_BUILD_DIR)/apk-$(PKGARCH)/$(1)
+ KEEP_$(1):=$(strip $(call Package/$(1)/conffiles))
+
+ TARGET_VARIANT:=$$(if $(ALL_VARIANTS),$$(if $$(VARIANT),$$(filter-out *,$$(VARIANT)),$(firstword $(ALL_VARIANTS))))
+ ifeq ($(BUILD_VARIANT),$$(if $$(TARGET_VARIANT),$$(TARGET_VARIANT),$(BUILD_VARIANT)))
+ do_install=
+ ifdef Package/$(1)/install
+ do_install=yes
+ endif
+ ifdef Package/$(1)/install-overlay
+ do_install=yes
+ endif
+ ifdef do_install
+ ifneq ($(CONFIG_PACKAGE_$(1))$(DEVELOPER),)
+ IPKGS += $(1)
+ $(_pkg_target)compile: $$(PACK_$(1)) $(PKG_INFO_DIR)/$(1).provides $(PKG_BUILD_DIR)/.pkgdir/$(1).installed
+ prepare-package-install: $$(PACK_$(1))
+ compile: $(STAGING_DIR_ROOT)/stamp/.$(1)_installed
+ else
+ $(if $(CONFIG_PACKAGE_$(1)),$$(info WARNING: skipping $(1) -- package not selected))
+ endif
+
+ .PHONY: $(PKG_INSTALL_STAMP).$(1)
+ ifeq ($(CONFIG_PACKAGE_$(1)),y)
+ compile: $(PKG_INSTALL_STAMP).$(1)
+ endif
+ $(PKG_INSTALL_STAMP).$(1): prepare-package-install
+ echo "$(1)" >> $(PKG_INSTALL_STAMP)
+ else
+ $(if $(CONFIG_PACKAGE_$(1)),$$(warning WARNING: skipping $(1) -- package has no install section))
+ endif
+ endif
+
+ DEPENDS:=$(call PKG_FIXUP_DEPENDS,$(1),$(DEPENDS))
+ IDEPEND_$(1):=$$(call filter_deps,$$(DEPENDS))
+ IDEPEND += $$(patsubst %,$(1):%,$$(IDEPEND_$(1)))
+ $(FixupDependencies)
+ $(FixupReverseDependencies)
+
+ $(eval $(call BuildPackVariable,$(1),conffiles))
+ $(eval $(call BuildPackVariable,$(1),preinst,,1))
+ $(eval $(call BuildPackVariable,$(1),postinst,-pkg,1))
+ $(eval $(call BuildPackVariable,$(1),prerm,-pkg,1))
+ $(eval $(call BuildPackVariable,$(1),postrm,,1))
+
+ $(PKG_BUILD_DIR)/.pkgdir/$(1).installed : export PATH=$$(TARGET_PATH_PKG)
+ $(PKG_BUILD_DIR)/.pkgdir/$(1).installed: $(STAMP_BUILT)
+ rm -rf $$@ $(PKG_BUILD_DIR)/.pkgdir/$(1)
+ mkdir -p $(PKG_BUILD_DIR)/.pkgdir/$(1)
+ $(call Package/$(1)/install,$(PKG_BUILD_DIR)/.pkgdir/$(1))
+ $(call Package/$(1)/install_lib,$(PKG_BUILD_DIR)/.pkgdir/$(1))
+ touch $$@
+
+ $(STAGING_DIR_ROOT)/stamp/.$(1)_installed: $(PKG_BUILD_DIR)/.pkgdir/$(1).installed
+ mkdir -p $(STAGING_DIR_ROOT)/stamp
+ $(if $(ABI_VERSION),echo '$(ABI_VERSION)' | cmp -s - $(PKG_INFO_DIR)/$(1).version || { \
+ echo '$(ABI_VERSION)' > $(PKG_INFO_DIR)/$(1).version; \
+ $(foreach pkg,$(filter-out $(1),$(PROVIDES)), \
+ cp $(PKG_INFO_DIR)/$(1).version $(PKG_INFO_DIR)/$(pkg).version; \
+ ) \
+ } )
+ $(call locked,$(CP) $(PKG_BUILD_DIR)/.pkgdir/$(1)/. $(STAGING_DIR_ROOT)/,root-copy)
+ touch $$@
+
+ Package/$(1)/DEPENDS := $$(call mergelist,$$(foreach dep,$$(filter-out @%,$$(IDEPEND_$(1))),$$(dep)$$(call GetABISuffix,$$(dep))))
+ ifneq ($$(EXTRA_DEPENDS),)
+ Package/$(1)/DEPENDS := $$(EXTRA_DEPENDS)$$(if $$(Package/$(1)/DEPENDS),$$(comma) $$(Package/$(1)/DEPENDS))
+ endif
+
+$(_define) Package/$(1)/CONTROL
+Package: $(1)$$(ABIV_$(1))
+Version: $(VERSION)
+$$(call addfield,Depends,$$(Package/$(1)/DEPENDS)
+)$$(call addfield,Conflicts,$$(call mergelist,$(CONFLICTS))
+)$$(call addfield,Provides,$$(call mergelist,$$(filter-out $(1)$$(ABIV_$(1)),$(PROVIDES)$$(if $$(ABIV_$(1)), $(1) $(foreach provide,$(PROVIDES),$(provide)$$(ABIV_$(1))))))
+)$$(call addfield,Alternatives,$$(call mergelist,$(ALTERNATIVES))
+)$$(call addfield,Source,$(SOURCE)
+)$$(call addfield,SourceName,$(PKG_NAME)
+)$$(call addfield,License,$(LICENSE)
+)$$(call addfield,LicenseFiles,$(LICENSE_FILES)
+)$$(call addfield,Section,$(SECTION)
+)$$(call addfield,Require-User,$(USERID)
+)$$(call addfield,SourceDateEpoch,$(PKG_SOURCE_DATE_EPOCH)
+)$$(call addfield,URL,$(URL)
+)$$(if $$(ABIV_$(1)),ABIVersion: $$(ABIV_$(1))
+)$(if $(PKG_CPE_ID),CPE-ID: $(PKG_CPE_ID)
+)$(if $(filter hold,$(PKG_FLAGS)),Status: unknown hold not-installed
+)$(if $(filter essential,$(PKG_FLAGS)),Essential: yes
+)$(if $(MAINTAINER),Maintainer: $(MAINTAINER)
+)Architecture: $(PKGARCH)
+Installed-Size: 0
+$(_endef)
+
+ $$(PACK_$(1)) : export CONTROL=$$(Package/$(1)/CONTROL)
+ $$(PACK_$(1)) : export DESCRIPTION=$$(Package/$(1)/description)
+ $$(PACK_$(1)) : export PATH=$$(TARGET_PATH_PKG)
+ $$(PACK_$(1)) : export PKG_SOURCE_DATE_EPOCH:=$(PKG_SOURCE_DATE_EPOCH)
+ $(PKG_INFO_DIR)/$(1).provides $$(PACK_$(1)): $(STAMP_BUILT) $(INCLUDE_DIR)/package-pack.mk
+ rm -rf $$(IDIR_$(1))
+ifeq ($$(CONFIG_USE_APK),)
+ $$(call remove_ipkg_files,$(1),$$(call opkg_package_files,$(call gen_package_wildcard,$(1))))
+endif
+ mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1)) $(PKG_INFO_DIR)
+ $(call Package/$(1)/install,$$(IDIR_$(1)))
+ $(if $(Package/$(1)/install-overlay),mkdir -p $(PACKAGE_DIR) $$(IDIR_$(1))/rootfs-overlay)
+ $(call Package/$(1)/install-overlay,$$(IDIR_$(1))/rootfs-overlay)
+ -find $$(IDIR_$(1)) -name 'CVS' -o -name '.svn' -o -name '.#*' -o -name '*~'| $(XARGS) rm -rf
+ @( \
+ find $$(IDIR_$(1)) -name lib\*.so\* -or -name \*.ko | awk -F/ '{ print $$$$NF }'; \
+ for file in $$(patsubst %,$(PKG_INFO_DIR)/%.provides,$$(IDEPEND_$(1))); do \
+ if [ -f "$$$$file" ]; then \
+ cat $$$$file; \
+ fi; \
+ done; $(Package/$(1)/extra_provides) \
+ ) | sort -u > $(PKG_INFO_DIR)/$(1).provides
+ $(if $(PROVIDES),@for pkg in $(filter-out $(1),$(PROVIDES)); do cp $(PKG_INFO_DIR)/$(1).provides $(PKG_INFO_DIR)/$$$$pkg.provides; done)
+ $(CheckDependencies)
+
+ $(RSTRIP) $$(IDIR_$(1))
+
+ ifneq ($$(CONFIG_IPK_FILES_CHECKSUMS),)
+ (cd $$(IDIR_$(1)); \
+ ( \
+ find . -type f \! -path ./CONTROL/\* -exec $(MKHASH) sha256 -n \{\} \; 2> /dev/null | \
+ sed 's|\([[:blank:]]\)\./| \1/|' > $$(IDIR_$(1))/CONTROL/files-sha256sum \
+ ) || true \
+ )
+ endif
+
+ ifneq ($$(KEEP_$(1)),)
+ @( \
+ keepfiles=""; \
+ for x in $$(KEEP_$(1)); do \
+ [ -f "$$(IDIR_$(1))/$$$$x" ] || keepfiles="$$$${keepfiles:+$$$$keepfiles }$$$$x"; \
+ done; \
+ [ -z "$$$$keepfiles" ] || { \
+ mkdir -p $$(IDIR_$(1))/lib/upgrade/keep.d; \
+ for x in $$$$keepfiles; do echo $$$$x >> $$(IDIR_$(1))/lib/upgrade/keep.d/$(1); done; \
+ }; \
+ )
+ endif
+
+ $(INSTALL_DIR) $$(PDIR_$(1))/tmp
+
+ifeq ($(CONFIG_USE_APK),)
+ mkdir -p $$(IDIR_$(1))/CONTROL
+ (cd $$(IDIR_$(1))/CONTROL; \
+ ( \
+ echo "$$$$CONTROL"; \
+ printf "Description: "; echo "$$$$DESCRIPTION" | sed -e 's,^[[:space:]]*, ,g'; \
+ ) > control; \
+ chmod 644 control; \
+ ( \
+ echo "#!/bin/sh"; \
+ echo "[ \"\$$$${IPKG_NO_SCRIPT}\" = \"1\" ] && exit 0"; \
+ echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
+ echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
+ echo "default_postinst \$$$$0 \$$$$@"; \
+ ) > postinst; \
+ ( \
+ echo "#!/bin/sh"; \
+ echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
+ echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
+ echo "default_prerm \$$$$0 \$$$$@"; \
+ ) > prerm; \
+ chmod 0755 postinst prerm; \
+ $($(1)_COMMANDS) \
+ )
+
+ $(FAKEROOT) $(STAGING_DIR_HOST)/bin/bash $(SCRIPT_DIR)/ipkg-build -m "$(FILE_MODES)" $$(IDIR_$(1)) $$(PDIR_$(1))
+else
+ mkdir -p $$(ADIR_$(1))/
+ mkdir -p $$(IDIR_$(1))/lib/apk/packages/
+
+ (cd $$(ADIR_$(1)); $($(1)_COMMANDS))
+
+ ( \
+ echo "#!/bin/sh"; \
+ echo "[ \"\$$$${IPKG_NO_SCRIPT}\" = \"1\" ] && exit 0"; \
+ echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
+ echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
+ echo 'export root="$$$${IPKG_INSTROOT}"'; \
+ echo 'export pkgname="$(1)"'; \
+ echo "add_group_and_user"; \
+ [ ! -f $$(ADIR_$(1))/postinst-pkg ] || cat "$$(ADIR_$(1))/postinst-pkg"; \
+ echo "default_postinst"; \
+ ) > $$(ADIR_$(1))/post-install;
+
+ ( \
+ echo "#!/bin/sh"; \
+ echo "[ -s "\$$$${IPKG_INSTROOT}/lib/functions.sh" ] || exit 0"; \
+ echo ". \$$$${IPKG_INSTROOT}/lib/functions.sh"; \
+ echo 'export root="$$$${IPKG_INSTROOT}"'; \
+ echo 'export pkgname="$(1)"'; \
+ [ ! -f $$(ADIR_$(1))/prerm-pkg ] || cat "$$(ADIR_$(1))/prerm-pkg"; \
+ echo "default_prerm"; \
+ ) > $$(ADIR_$(1))/pre-deinstall;
+
+ if [ -n "$(USERID)" ]; then echo $(USERID) > $$(IDIR_$(1))/lib/apk/packages/$(1).rusers; fi;
+ if [ -n "$(ALTERNATIVES)" ]; then echo $(ALTERNATIVES) > $$(IDIR_$(1))/lib/apk/packages/$(1).alternatives; fi;
+ (cd $$(IDIR_$(1)) && find . -type f,l -printf "/%P\n" > $$(IDIR_$(1))/lib/apk/packages/$(1).list)
+ if [ -f $$(ADIR_$(1))/conffiles ]; then mv $$(ADIR_$(1))/conffiles $$(IDIR_$(1))/lib/apk/packages/$(1).conffiles; fi;
+
+ $(FAKEROOT) $(STAGING_DIR_HOST)/bin/apk mkpkg \
+ --info "name:$(1)$$(ABIV_$(1))" \
+ --info "version:$(VERSION)" \
+ --info "description:" \
+ --info "arch:$(PKGARCH)" \
+ --info "license:$(LICENSE)" \
+ --info "origin:$(SOURCE)" \
+ --info "provides:$$(foreach prov,$$(filter-out $(1)$$(ABIV_$(1)),$(PROVIDES)$$(if $$(ABIV_$(1)), \
+ $(1) $(foreach provide,$(PROVIDES),$(provide)$$(ABIV_$(1))))),$$(prov)=$(VERSION) )" \
+ --script "post-install:$$(ADIR_$(1))/post-install" \
+ --script "pre-deinstall:$$(ADIR_$(1))/pre-deinstall" \
+ --info "depends:$$(foreach depends,$$(subst $$(comma),$$(space),$$(subst $$(space),,$$(subst $$(paren_right),,$$(subst $$(paren_left),,$$(Package/$(1)/DEPENDS))))),$$(depends))" \
+ --files "$$(IDIR_$(1))" \
+ --output "$$(PACK_$(1))" \
+ --sign "$(BUILD_KEY_APK_SEC)"
+endif
+
+ @[ -f $$(PACK_$(1)) ]
+
+ $(1)-clean:
+ifeq ($(CONFIG_USE_APK),)
+ $$(call remove_ipkg_files,$(1),$$(call opkg_package_files,$(call gen_package_wildcard,$(1))))
+else
+ $$(call remove_ipkg_files,$(1),$$(call apk_package_files,$(call gen_package_wildcard,$(1))))
+endif
+
+
+ clean: $(1)-clean
+
+ endef
+endif
include $(INCLUDE_DIR)/package-defaults.mk
include $(INCLUDE_DIR)/package-dumpinfo.mk
-include $(INCLUDE_DIR)/package-ipkg.mk
+include $(INCLUDE_DIR)/package-pack.mk
include $(INCLUDE_DIR)/package-bin.mk
include $(INCLUDE_DIR)/autotools.mk
--add-arch all:100 \
--add-arch $(if $(ARCH_PACKAGES),$(ARCH_PACKAGES),$(BOARD)):200
+apk = \
+ IPKG_INSTROOT=$(1) \
+ $(FAKEROOT) $(STAGING_DIR_HOST)/bin/apk \
+ --root $(1) \
+ --repositories-file /dev/zero \
+ --keys-dir $(TOPDIR) \
+ --no-cache \
+ --no-logfile \
+ --preserve-env \
+ --repository file://$(PACKAGE_DIR_ALL)/packages.adb
+
TARGET_DIR_ORIG := $(TARGET_ROOTFS_DIR)/root.orig-$(BOARD)
ifdef CONFIG_CLEAN_IPKG
@mkdir -p $(1)/var/lock
@( \
cd $(1); \
+ if [ -n "$(CONFIG_USE_APK)" ]; then \
+ $(STAGING_DIR_HOST)/bin/tar -xf ./lib/apk/db/scripts.tar --wildcards "*.post-install" -O > script.sh; \
+ chmod +x script.sh; \
+ IPKG_INSTROOT=$(1) $$(command -v bash) script.sh; \
+ else \
for script in ./usr/lib/opkg/info/*.postinst; do \
IPKG_INSTROOT=$(1) $$(command -v bash) $$script; \
ret=$$?; \
exit 1; \
fi; \
done; \
+ $(if $(IB),,awk -i inplace \
+ '/^Status:/ { \
+ if ($$3 == "user") { $$3 = "ok" } \
+ else { sub(/,\<user\>|\<user\>,/, "", $$3) } \
+ }1' $(1)/usr/lib/opkg/status) ; \
+ $(if $(SOURCE_DATE_EPOCH),sed -i "s/Installed-Time: .*/Installed-Time: $(SOURCE_DATE_EPOCH)/" $(1)/usr/lib/opkg/status ;) \
+ fi; \
for script in ./etc/init.d/*; do \
grep '#!/bin/sh /etc/rc.common' $$script >/dev/null || continue; \
if ! echo " $(3) " | grep -q " $$(basename $$script) "; then \
fi; \
done || true \
)
- awk -i inplace \
- '/^Status:/ { \
- if ($$3 == "user") { $$3 = "ok" } \
- else { sub(/,\<user\>|\<user\>,/, "", $$3) } \
- }1' $(1)/usr/lib/opkg/status
- $(if $(SOURCE_DATE_EPOCH),sed -i "s/Installed-Time: .*/Installed-Time: $(SOURCE_DATE_EPOCH)/" $(1)/usr/lib/opkg/status)
+
@-find $(1) -name CVS -o -name .svn -o -name .git -o -name '.#*' | $(XARGS) rm -rf
rm -rf \
$(1)/boot \
logd \
mtd \
netifd \
- opkg \
uci \
uclient-fetch \
urandom-seed \
urngd
+ifdef CONFIG_USE_APK
+DEFAULT_PACKAGES+=apk
+else
+DEFAULT_PACKAGES+=opkg
+endif
+
ifneq ($(CONFIG_SELINUX),)
DEFAULT_PACKAGES+=busybox-selinux procd-selinux
else
$(curdir)/merge:
rm -rf $(PACKAGE_DIR_ALL)
mkdir -p $(PACKAGE_DIR_ALL)
+ifneq ($(CONFIG_USE_APK),)
+ -$(foreach pdir,$(PACKAGE_SUBDIRS),$(if $(wildcard $(pdir)/*.apk),ln -s $(pdir)/*.apk $(PACKAGE_DIR_ALL);))
+else
-$(foreach pdir,$(PACKAGE_SUBDIRS),$(if $(wildcard $(pdir)/*.ipk),ln -s $(pdir)/*.ipk $(PACKAGE_DIR_ALL);))
+endif
+
+$(BUILD_KEY_APK_SEC):
+ $(STAGING_DIR_HOST)/bin/openssl ecparam -name prime256v1 -genkey -noout -out $(BUILD_KEY_APK_SEC)
+
+$(BUILD_KEY_APK_PUB): $(BUILD_KEY_APK_SEC)
+ $(STAGING_DIR_HOST)/bin/openssl ec -in $(BUILD_KEY_APK_SEC) -pubout > $(BUILD_KEY_APK_PUB)
$(curdir)/merge-index: $(curdir)/merge
+ifneq ($(CONFIG_USE_APK),)
+ (cd $(PACKAGE_DIR_ALL) && $(STAGING_DIR_HOST)/bin/apk mkndx \
+ --root $(TOPDIR) \
+ --keys-dir $(TOPDIR) \
+ --sign $(BUILD_KEY_APK_SEC) \
+ --output packages.adb \
+ *.apk; \
+ )
+else
(cd $(PACKAGE_DIR_ALL) && $(SCRIPT_DIR)/ipkg-make-index.sh . 2>&1 > Packages; )
+endif
ifndef SDK
$(curdir)//compile = $(STAGING_DIR)/.prepared $(BIN_DIR)
+ifneq ($(CONFIG_USE_APK),)
+ $(curdir)/compile: $(curdir)/system/apk/host/compile $(BUILD_KEY_APK_SEC) $(BUILD_KEY_APK_PUB)
+else
$(curdir)/compile: $(curdir)/system/opkg/host/compile
endif
+endif
-$(curdir)/install: $(TMP_DIR)/.build $(curdir)/merge $(if $(CONFIG_TARGET_PER_DEVICE_ROOTFS),$(curdir)/merge-index)
+$(curdir)/install: $(TMP_DIR)/.build $(curdir)/merge $(curdir)/merge-index
- find $(STAGING_DIR_ROOT) -type d | $(XARGS) chmod 0755
rm -rf $(TARGET_DIR) $(TARGET_DIR_ORIG)
mkdir -p $(TARGET_DIR)/tmp
+ifneq ($(CONFIG_USE_APK),)
+ $(file >$(TMP_DIR)/apk_install_list,\
+ $(foreach pkg,$(shell cat $(PACKAGE_INSTALL_FILES) 2>/dev/null),$(pkg)$(call GetABISuffix,$(pkg))))
+ $(call apk,$(TARGET_DIR)) add --initdb --no-scripts --arch $(ARCH_PACKAGES) $$(cat $(TMP_DIR)/apk_install_list)
+else
$(file >$(TMP_DIR)/opkg_install_list,\
$(call opkg_package_files,\
$(foreach pkg,$(shell cat $(PACKAGE_INSTALL_FILES) 2>/dev/null),$(pkg)$(call GetABISuffix,$(pkg)))))
$(call opkg,$(TARGET_DIR)) flag $$flag `cat $$file`; \
done; \
done || true
+endif
$(CP) $(TARGET_DIR) $(TARGET_DIR_ORIG)
$(curdir)/index: FORCE
@echo Generating package index...
+ifneq ($(CONFIG_USE_APK),)
+ @for d in $(PACKAGE_SUBDIRS); do \
+ mkdir -p $$d; \
+ cd $$d || continue; \
+ ls *.apk >/dev/null 2>&1 || continue; \
+ $(STAGING_DIR_HOST)/bin/apk mkndx \
+ --root $(TOPDIR) \
+ --keys-dir $(TOPDIR) \
+ --sign $(BUILD_KEY_APK_SEC) \
+ --output packages.adb \
+ *.apk; \
+ done
+else
@for d in $(PACKAGE_SUBDIRS); do ( \
mkdir -p $$d; \
cd $$d || continue; \
$(SCRIPT_DIR)/package-metadata.pl pkgcyclonedxsbom Packages.manifest > Packages.bom.cdx.json || true; \
); done
endif
+endif
$(curdir)/flags-install:= -j1
endef
Build/Compile = $(Build/Compile/Default)
+ifneq ($(CONFIG_USE_APK),)
+ifndef CONFIG_BUILDBOT
+ define Package/base-files/install-key
+ mkdir -p $(1)/etc/apk/keys
+ $(CP) $(BUILD_KEY_APK_PUB) $(1)/etc/apk/keys/
+ endef
+endif
+else
ifdef CONFIG_SIGNED_PACKAGES
define Build/Configure
[ -s $(BUILD_KEY) -a -s $(BUILD_KEY).pub ] || \
define Package/base-files/install-key
mkdir -p $(1)/etc/opkg/keys
$(CP) $(BUILD_KEY).pub $(1)/etc/opkg/keys/`$(STAGING_DIR_HOST)/bin/usign -F -p $(BUILD_KEY).pub`
-
endef
endif
endif
+endif
ifeq ($(CONFIG_NAND_SUPPORT),)
define Package/base-files/nand-support
cat $(BIN_DIR)/feeds.buildinfo >>$(1)/etc/build.feeds; \
cat $(BIN_DIR)/version.buildinfo >>$(1)/etc/build.version)
+ $(if $(CONFIG_TARGET_PREINIT_DISABLE_FAILSAFE), \
+ rm -f $(1)/etc/banner.failsafe,)
+
+ifneq ($(CONFIG_USE_APK),)
+ mkdir -p $(1)/etc/apk/
+ $(call FeedSourcesAppendAPK,$(1)/etc/apk/repositories)
+ $(VERSION_SED_SCRIPT) $(1)/etc/apk/repositories
+else
$(if $(CONFIG_CLEAN_IPKG),, \
mkdir -p $(1)/etc/opkg; \
- $(call FeedSourcesAppend,$(1)/etc/opkg/distfeeds.conf); \
+ $(call FeedSourcesAppendOPKG,$(1)/etc/opkg/distfeeds.conf); \
$(VERSION_SED_SCRIPT) $(1)/etc/opkg/distfeeds.conf)
$(if $(CONFIG_IPK_FILES_CHECKSUMS),, \
rm -f $(1)/sbin/pkg_check)
-
- $(if $(CONFIG_TARGET_PREINIT_DISABLE_FAILSAFE), \
- rm -f $(1)/etc/banner.failsafe,)
+endif
endef
ifneq ($(DUMP),1)
default_prerm() {
local root="${IPKG_INSTROOT}"
- local pkgname="$(basename ${1%.*})"
+ [ -z "$pkgname" ] && local pkgname="$(basename ${1%.*})"
local ret=0
+ local filelist="${root}/usr/lib/opkg/info/${pkgname}.list"
+ [ -f "$root/lib/apk/packages/${pkgname}.list" ] && filelist="$root/lib/apk/packages/${pkgname}.list"
if [ -f "$root/usr/lib/opkg/info/${pkgname}.prerm-pkg" ]; then
( . "$root/usr/lib/opkg/info/${pkgname}.prerm-pkg" )
fi
local shell="$(command -v bash)"
- for i in $(grep -s "^/etc/init.d/" "$root/usr/lib/opkg/info/${pkgname}.list"); do
+ for i in $(grep -s "^/etc/init.d/" "$filelist"); do
if [ -n "$root" ]; then
${shell:-/bin/sh} "$root/etc/rc.common" "$root$i" disable
else
}
add_group_and_user() {
- local pkgname="$1"
+ [ -z "$pkgname" ] && local pkgname="$(basename ${1%.*})"
local rusers="$(sed -ne 's/^Require-User: *//p' $root/usr/lib/opkg/info/${pkgname}.control 2>/dev/null)"
+ if [ -f "$root/lib/apk/packages/${pkgname}.rusers" ]; then
+ local rusers="$(cat $root/lib/apk/packages/${pkgname}.rusers)"
+ fi
if [ -n "$rusers" ]; then
local tuple oIFS="$IFS"
fi
}
+update_alternatives() {
+ local root="${IPKG_INSTROOT}"
+ local action="$1"
+ local pkgname="$2"
+
+ if [ -f "$root/lib/apk/packages/${pkgname}.alternatives" ]; then
+ for pkg_alt in $(cat $root/lib/apk/packages/${pkgname}.alternatives); do
+ local best_prio=0;
+ local best_src="/bin/busybox";
+ pkg_prio=${pkg_alt%%:*};
+ pkg_target=${pkg_alt#*:};
+ pkg_target=${pkg_target%:*};
+ pkg_src=${pkg_alt##*:};
+
+ if [ -e "$root/$target" ]; then
+ for alts in $root/lib/apk/packages/*.alternatives; do
+ for alt in $(cat $alts); do
+ prio=${alt%%:*};
+ target=${alt#*:};
+ target=${target%:*};
+ src=${alt##*:};
+
+ if [ "$target" = "$pkg_target" ] &&
+ [ "$src" != "$pkg_src" ] &&
+ [ "$best_prio" -lt "$prio" ]; then
+ best_prio=$prio;
+ best_src=$src;
+ fi
+ done
+ done
+ fi
+ case "$action" in
+ install)
+ if [ "$best_prio" -lt "$pkg_prio" ]; then
+ ln -sf "$pkg_src" "$root/$pkg_target"
+ echo "add alternative: $pkg_target -> $pkg_src"
+ fi
+ ;;
+ remove)
+ if [ "$best_prio" -lt "$pkg_prio" ]; then
+ ln -sf "$best_src" "$root/$pkg_target"
+ echo "add alternative: $pkg_target -> $best_src"
+ fi
+ ;;
+ esac
+ done
+ fi
+}
+
default_postinst() {
local root="${IPKG_INSTROOT}"
- local pkgname="$(basename ${1%.*})"
- local filelist="/usr/lib/opkg/info/${pkgname}.list"
+ [ -z "$pkgname" ] && local pkgname="$(basename ${1%.*})"
+ local filelist="${root}/usr/lib/opkg/info/${pkgname}.list"
+ [ -f "$root/lib/apk/packages/${pkgname}.list" ] && filelist="$root/lib/apk/packages/${pkgname}.list"
local ret=0
- add_group_and_user "${pkgname}"
+ if [ -e "${root}/usr/lib/opkg/info/${pkgname}.list" ]; then
+ filelist="${root}/usr/lib/opkg/info/${pkgname}.list"
+ add_group_and_user "${pkgname}"
+ fi
+
+ if [ -e "${root}/lib/apk/packages/${pkgname}.list" ]; then
+ filelist="${root}/lib/apk/packages/${pkgname}.list"
+ update_alternatives install "${pkgname}"
+ fi
if [ -d "$root/rootfs-overlay" ]; then
cp -R $root/rootfs-overlay/. $root/
fi
local shell="$(command -v bash)"
- for i in $(grep -s "^/etc/init.d/" "$root$filelist"); do
+ for i in $(grep -s "^/etc/init.d/" "$filelist"); do
if [ -n "$root" ]; then
${shell:-/bin/sh} "$root/etc/rc.common" "$root$i" enable
else
DEFAULT:=TARGET_mediatek_filogic
endef
+define Trusted-Firmware-A/mt7981-nor-ddr4
+ NAME:=MediaTek MT7981 (SPI-NOR, DDR4)
+ BOOT_DEVICE:=nor
+ BUILD_SUBTARGET:=filogic
+ PLAT:=mt7981
+ DDR_TYPE:=ddr4
+endef
+
define Trusted-Firmware-A/mt7981-emmc-ddr3
NAME:=MediaTek MT7981 (eMMC, DDR3)
BOOT_DEVICE:=emmc
DEFAULT:=TARGET_mediatek_filogic
endef
+define Trusted-Firmware-A/mt7981-spim-nand-ubi-ddr4
+ NAME:=MediaTek MT7981 (SPI-NAND via SPIM, DDR4)
+ BOOT_DEVICE:=spim-nand
+ BUILD_SUBTARGET:=filogic
+ PLAT:=mt7981
+ DDR_TYPE:=ddr4
+ USE_UBI:=1
+endef
+
define Trusted-Firmware-A/mt7986-nor-ddr4
NAME:=MediaTek MT7986 (SPI-NOR, DDR4)
BOOT_DEVICE:=nor
mt7981-ram-ddr3 \
mt7981-emmc-ddr3 \
mt7981-nor-ddr3 \
+ mt7981-nor-ddr4 \
mt7981-sdmmc-ddr3 \
mt7981-snand-ddr3 \
mt7981-spim-nand-ddr3 \
+ mt7981-spim-nand-ubi-ddr4 \
mt7981-ram-ddr4 \
mt7981-emmc-ddr4 \
mt7981-spim-nand-ddr4 \
$(if $(DRAM_USE_COMB),DRAM_USE_COMB=1) \
$(if $(RAM_BOOT_UART_DL),RAM_BOOT_UART_DL=1) \
$(if $(USE_UBI),UBI=1 $(if $(findstring mt7622,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x80000)) \
+ $(if $(USE_UBI),UBI=1 $(if $(findstring mt7981,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x100000)) \
all
define Package/trusted-firmware-a-ram/install
include $(TOPDIR)/rules.mk
PKG_NAME:=tfa-layerscape
-PKG_VERSION:=lf-6.1.1-1.0.0
+PKG_VERSION:=6.6.3.1.0.0
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/nxp-qoriq/atf
-PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0
-PKG_MIRROR_HASH:=e109ca87a0f432529ab4d1fcd019adc0cd0d3684c96cdf770aac113f9bbe4bd6
+PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0
+PKG_MIRROR_HASH:=28b731c1c4cc3226ccaef2142c61127f213c03cbd219df556c1d191e95f8470c
PKG_BUILD_DEPENDS:=tfa-layerscape/host
include $(INCLUDE_DIR)/host-build.mk
--- a/Makefile
+++ b/Makefile
-@@ -914,10 +914,6 @@ CRTTOOL ?= ${CRTTOOLPATH}/cert_create$
+@@ -953,10 +953,6 @@ CRTTOOL ?= ${CRTTOOLPATH}/cert_create$
ENCTOOLPATH ?= tools/encrypt_fw
ENCTOOL ?= ${ENCTOOLPATH}/encrypt_fw${BIN_EXT}
-
# Variables for use with sptool
SPTOOLPATH ?= tools/sptool
- SPTOOL ?= ${SPTOOLPATH}/sptool${BIN_EXT}
-@@ -1322,13 +1318,6 @@ endif
+ SPTOOL ?= ${SPTOOLPATH}/sptool.py
+@@ -1409,13 +1405,6 @@ endif
clean:
@echo " CLEAN"
$(call SHELL_REMOVE_DIR,${BUILD_PLAT})
${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean
${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} clean
${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
-@@ -1337,13 +1326,6 @@ realclean distclean:
+@@ -1424,13 +1413,6 @@ realclean distclean:
@echo " REALCLEAN"
$(call SHELL_REMOVE_DIR,${BUILD_BASE})
$(call SHELL_DELETE_ALL, ${CURDIR}/cscope.*)
-# to pass the gnumake flags to nmake.
- ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL)) realclean
-endif
- ${Q}${MAKE} --no-print-directory -C ${SPTOOLPATH} clean
- ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} clean
+ ${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${CRTTOOLPATH} realclean
${Q}${MAKE} PLAT=${PLAT} --no-print-directory -C ${ENCTOOLPATH} realclean
-@@ -1400,7 +1382,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL}
+ ${Q}${MAKE} --no-print-directory -C ${ROMLIBPATH} clean
+@@ -1486,7 +1468,7 @@ certificates: ${CRT_DEPS} ${CRTTOOL}
@${ECHO_BLANK_LINE}
endif
-${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS} ${FIPTOOL}
+${BUILD_PLAT}/${FIP_NAME}: ${FIP_DEPS}
- $(eval ${CHECK_FIP_CMD})
- ${Q}${FIPTOOL} create ${FIP_ARGS} $@
- ${Q}${FIPTOOL} info $@
-@@ -1417,7 +1399,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT
+ $(eval ${CHECK_FIP_CMD})
+ ${Q}${FIPTOOL} create ${FIP_ARGS} $@
+ ${Q}${FIPTOOL} info $@
+@@ -1503,7 +1485,7 @@ fwu_certificates: ${FWU_CRT_DEPS} ${CRTT
@${ECHO_BLANK_LINE}
endif
-${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS} ${FIPTOOL}
+${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP_DEPS}
- $(eval ${CHECK_FWU_FIP_CMD})
- ${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@
- ${Q}${FIPTOOL} info $@
-@@ -1425,19 +1407,9 @@ ${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP
+ $(eval ${CHECK_FWU_FIP_CMD})
+ ${Q}${FIPTOOL} create ${FWU_FIP_ARGS} $@
+ ${Q}${FIPTOOL} info $@
+@@ -1511,19 +1493,9 @@ ${BUILD_PLAT}/${FWU_FIP_NAME}: ${FWU_FIP
@echo "Built $@ successfully"
@${ECHO_BLANK_LINE}
-${FIPTOOL}: FORCE
-ifdef UNIX_MK
-- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} --no-print-directory -C ${FIPTOOLPATH}
+- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" FIPTOOL=${FIPTOOL} OPENSSL_DIR=${OPENSSL_DIR} DEBUG=${DEBUG} V=${V} --no-print-directory -C ${FIPTOOLPATH} all
-else
-# Clear the MAKEFLAGS as we do not want
-# to pass the gnumake flags to nmake.
- ${Q}set MAKEFLAGS= && ${MSVC_NMAKE} /nologo /f ${FIPTOOLPATH}/Makefile.msvc FIPTOOLPATH=$(subst /,\,$(FIPTOOLPATH)) FIPTOOL=$(subst /,\,$(FIPTOOL))
-endif
-
- sptool: ${SPTOOL}
- ${SPTOOL}: FORCE
- ${Q}${MAKE} CPPFLAGS="-DVERSION='\"${VERSION_STRING}\"'" SPTOOL=${SPTOOL} --no-print-directory -C ${SPTOOLPATH}
+ romlib.bin: libraries FORCE
+ ${Q}${MAKE} PLAT_DIR=${PLAT_DIR} BUILD_PLAT=${BUILD_PLAT} ENABLE_BTI=${ENABLE_BTI} ARM_ARCH_MINOR=${ARM_ARCH_MINOR} INCLUDES='${INCLUDES}' DEFINES='${DEFINES}' --no-print-directory -C ${ROMLIBPATH} all
+
--- a/tools/fiptool/Makefile
+++ b/tools/fiptool/Makefile
-@@ -48,7 +48,7 @@ all: ${PROJECT}
+@@ -67,7 +67,7 @@ all: ${PROJECT}
- ${PROJECT}: ${OBJECTS} Makefile
+ ${PROJECT}: --openssl ${OBJECTS} Makefile
@echo " HOSTLD $@"
- ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS}
+ ${Q}${HOSTCC} ${OBJECTS} -o $@ ${LDLIBS} $(LDFLAGS)
@${ECHO_BLANK_LINE}
@echo "Built $@ successfully"
@${ECHO_BLANK_LINE}
---- a/tools/nxp/plat_fiptool/plat_fiptool.mk 2023-05-20 22:28:28.079945619 +0200
-+++ b/tools/nxp/plat_fiptool/plat_fiptool.mk 2023-05-20 22:26:59.443307771 +0200
+--- a/tools/nxp/plat_fiptool/plat_fiptool.mk
++++ b/tools/nxp/plat_fiptool/plat_fiptool.mk
@@ -22,11 +22,11 @@ INCLUDE_PATHS += -I${PLAT_DEF_UUID_OID_C
$(shell rm ${PLAT_DEF_UUID_CONFIG_FILE_PATH}/${PLAT_DEF_UUID_CONFIG_FILE_NAME}.o)
Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@protonmail.ch>
---
plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c | 34 +++++++
- plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h | 92 +++++++++++++++++++
+ plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h | 83 +++++++++++++++++++
plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk | 25 +++++
.../soc-ls1012a/ls1012afrdm/platform_def.h | 13 +++
plat/nxp/soc-ls1012a/ls1012afrdm/policy.h | 16 ++++
create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h
create mode 100644 plat/nxp/soc-ls1012a/ls1012afrdm/policy.h
-diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c b/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c
-new file mode 100644
-index 000000000..8cb518540
--- /dev/null
+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/ddr_init.c
@@ -0,0 +1,34 @@
+
+ return NXP_DRAM0_SIZE;
+}
-diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h b/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h
-new file mode 100644
-index 000000000..eb745a0a3
--- /dev/null
+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/plat_def.h
-@@ -0,0 +1,92 @@
+@@ -0,0 +1,83 @@
+/*
+ * Copyright 2022 NXP
+ *
+#define MAX_FIP_DEVICES 1
+#endif
+
-+#ifdef PLAT_FIP_OFFSET
-+#undef PLAT_FIP_OFFSET
-+#endif
-+#ifdef PLAT_FIP_MAX_SIZE
-+#undef PLAT_FIP_MAX_SIZE
-+#endif
-+#define PLAT_FIP_OFFSET 0x60000
-+#define PLAT_FIP_MAX_SIZE 0x170000
-+
+/*
+ * ID of the secure physical generic timer interrupt used by the BL32.
+ */
+#define PLAT_LS_G0_IRQ_PROPS(grp)
+
+#endif
-diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk b/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk
-new file mode 100644
-index 000000000..270e92420
--- /dev/null
+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/platform.mk
@@ -0,0 +1,25 @@
+
+# Adding SoC build info
+include plat/nxp/soc-ls1012a/soc.mk
-diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h b/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h
-new file mode 100644
-index 000000000..7daf1c02c
--- /dev/null
+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/platform_def.h
@@ -0,0 +1,13 @@
+#include <plat_default_def.h>
+
+#endif /* PLATFORM_DEF_H */
-diff --git a/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h b/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h
-new file mode 100644
-index 000000000..a782d01c7
--- /dev/null
+++ b/plat/nxp/soc-ls1012a/ls1012afrdm/policy.h
@@ -0,0 +1,16 @@
+#define POLICY_SMMU_PAGESZ_64K 0x0
+
+#endif /* POLICY_H */
---
-2.34.1
-
--- a/scripts/check-config.sh
+++ b/scripts/check-config.sh
-@@ -50,14 +50,13 @@ cat `find ${srctree} -name "Kconfig*"` |sed -n \
+@@ -50,14 +50,13 @@ cat `find ${srctree} -name "Kconfig*"` |
|sort |uniq > ${ok}
comm -23 ${suspects} ${ok} >${new_adhoc}
if [ -s ${new_adhoc} ]; then
PKG_NAME:=uboot-envtools
PKG_DISTNAME:=u-boot
PKG_VERSION:=2024.01
-PKG_RELEASE:=2
+PKG_RELEASE:=3
PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:= \
linksys,ea4500-v3)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000"
;;
+dell,apl26-0ae)
+ ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x40000" "0x10000"
+ ;;
domywifi,dw33d)
ubootenv_add_uci_config "/dev/mtd4" "0x0" "0x10000" "0x10000"
;;
checkpoint,l-50|\
cloudengines,pogoe02|\
cloudengines,pogoplugv4|\
+dlink,dns320l|\
globalscale,sheevaplug|\
iom,ix2-200|\
iom,ix4-200d|\
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x80000"
ubootenv_add_uci_sys_config "/dev/mtd3" "0x0" "0x100000" "0x100000"
;;
+smartrg,sdg-8733|\
+smartrg,sdg-8734)
+ local envdev=$(find_mmc_part "u-boot-env" "mmcblk0")
+ ubootenv_add_uci_config "$envdev" "0x0" "0x8000" "0x8000"
+ ;;
ubnt,unifi-6-plus)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x10000"
;;
;;
linksys,mx4200v1|\
linksys,mx4200v2|\
-linksys,mx5300)
+linksys,mx5300|\
+linksys,mx8500)
idx="$(find_mtd_index u_env)"
[ -n "$idx" ] && \
ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000" "2"
;;
+netgear,sxr80|\
+netgear,sxs80)
+ idx="$(find_mtd_index 0:appsblenv)"
+ [ -n "$idx" ] && \
+ ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x40000" "0x20000"
+ ;;
redmi,ax6|\
xiaomi,ax3600|\
xiaomi,ax9000)
asus,rt-ax53u|\
asus,rt-ax54|\
belkin,rt1800|\
+elecom,wrc-x1800gs|\
h3c,tx1800-plus|\
h3c,tx1801-plus|\
h3c,tx1806|\
include $(TOPDIR)/rules.mk
PKG_VERSION:=2020.04
-PKG_RELEASE:=9
+PKG_RELEASE:=10
PKG_HASH:=fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372
BUILD_SUBTARGET:=generic
endef
+define U-Boot/dns320l
+ NAME:=D-Link DNS-320L
+ BUILD_DEVICES:=dlink_dns320l
+endef
+
define U-Boot/dockstar
NAME:=Seagate DockStar
BUILD_DEVICES:=seagate_dockstar
endef
UBOOT_TARGETS := \
+ dns320l \
dockstar dockstar_second_stage \
goflexhome \
ib62x0 ib62x0_second_stage \
-diff -ruN u-boot-2020.04.old/arch/arm/mach-kirkwood/Kconfig u-boot-2020.04/arch/arm/mach-kirkwood/Kconfig
---- u-boot-2020.04.old/arch/arm/mach-kirkwood/Kconfig 2020-07-09 00:46:15.000000000 +0200
-+++ u-boot-2020.04/arch/arm/mach-kirkwood/Kconfig 2020-07-09 01:07:00.309219477 +0200
-@@ -44,6 +44,9 @@
+--- a/arch/arm/mach-kirkwood/Kconfig
++++ b/arch/arm/mach-kirkwood/Kconfig
+@@ -44,6 +44,9 @@ config TARGET_NET2BIG_V2
config TARGET_NETSPACE_V2
bool "LaCie netspace_v2 Board"
config TARGET_IB62X0
bool "ib62x0 Board"
-@@ -92,6 +95,7 @@
+@@ -95,6 +98,7 @@ source "board/iomega/iconnect/Kconfig"
source "board/keymile/Kconfig"
source "board/LaCie/net2big_v2/Kconfig"
source "board/LaCie/netspace_v2/Kconfig"
source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
-diff -ruN u-boot-2020.04.old/board/Marvell/netgear_ms2110/Kconfig u-boot-2020.04/board/Marvell/netgear_ms2110/Kconfig
---- u-boot-2020.04.old/board/Marvell/netgear_ms2110/Kconfig 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-2020.04/board/Marvell/netgear_ms2110/Kconfig 2020-07-09 00:59:29.000000000 +0200
+--- /dev/null
++++ b/board/Marvell/netgear_ms2110/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NETGEAR_MS2110
+
+ default "netgear_ms2110"
+
+endif
-diff -ruN u-boot-2020.04.old/board/Marvell/netgear_ms2110/kwbimage.cfg u-boot-2020.04/board/Marvell/netgear_ms2110/kwbimage.cfg
---- u-boot-2020.04.old/board/Marvell/netgear_ms2110/kwbimage.cfg 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-2020.04/board/Marvell/netgear_ms2110/kwbimage.cfg 2020-07-09 00:59:29.000000000 +0200
+--- /dev/null
++++ b/board/Marvell/netgear_ms2110/kwbimage.cfg
@@ -0,0 +1,167 @@
+#
+# (C) Copyright 2009
+
+# End of Header extension
+DATA 0x0 0x0
-diff -ruN u-boot-2020.04.old/board/Marvell/netgear_ms2110/MAINTAINERS u-boot-2020.04/board/Marvell/netgear_ms2110/MAINTAINERS
---- u-boot-2020.04.old/board/Marvell/netgear_ms2110/MAINTAINERS 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-2020.04/board/Marvell/netgear_ms2110/MAINTAINERS 2020-07-09 00:59:29.000000000 +0200
+--- /dev/null
++++ b/board/Marvell/netgear_ms2110/MAINTAINERS
@@ -0,0 +1,6 @@
+NETGEAR_MS2110 BOARD
+M: bodhi <mibodhi@gmail.com>
+F: board/Marvell/netgear_ms2110
+F: include/configs/netgear_ms2110.h
+F: configs/netgear_ms2110_defconfig
-diff -ruN u-boot-2020.04.old/board/Marvell/netgear_ms2110/Makefile u-boot-2020.04/board/Marvell/netgear_ms2110/Makefile
---- u-boot-2020.04.old/board/Marvell/netgear_ms2110/Makefile 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-2020.04/board/Marvell/netgear_ms2110/Makefile 2020-07-09 00:59:29.000000000 +0200
+--- /dev/null
++++ b/board/Marvell/netgear_ms2110/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2014 bodhi <mibodhi@gmail.com>
+
+obj-y := netgear_ms2110.o
+
-diff -ruN u-boot-2020.04.old/board/Marvell/netgear_ms2110/netgear_ms2110.c u-boot-2020.04/board/Marvell/netgear_ms2110/netgear_ms2110.c
---- u-boot-2020.04.old/board/Marvell/netgear_ms2110/netgear_ms2110.c 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-2020.04/board/Marvell/netgear_ms2110/netgear_ms2110.c 2020-07-09 00:59:29.000000000 +0200
+--- /dev/null
++++ b/board/Marvell/netgear_ms2110/netgear_ms2110.c
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2014-2017 bodhi <mibodhi@gmail.com>
+}
+#endif /* CONFIG_RESET_PHY_R */
+
-diff -ruN u-boot-2020.04.old/board/Marvell/netgear_ms2110/netgear_ms2110.h u-boot-2020.04/board/Marvell/netgear_ms2110/netgear_ms2110.h
---- u-boot-2020.04.old/board/Marvell/netgear_ms2110/netgear_ms2110.h 1970-01-01 01:00:00.000000000 +0100
-+++ u-boot-2020.04/board/Marvell/netgear_ms2110/netgear_ms2110.h 2020-07-09 00:59:29.000000000 +0200
+--- /dev/null
++++ b/board/Marvell/netgear_ms2110/netgear_ms2110.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
+
+#endif /* __NETGEAR_MS2110_H */
-diff -ruN a/configs/netgear_ms2110_defconfig b/configs/netgear_ms2110_defconfig
---- a/configs/netgear_ms2110_defconfig 1970-01-01 01:00:00.000000000 +0100
-+++ b/configs/netgear_ms2110_defconfig 2020-07-14 17:59:18.000000000 +0200
+--- /dev/null
++++ b/configs/netgear_ms2110_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_KIRKWOOD=y
+CONFIG_MVSATA_IDE=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_MV=y
-diff -ruN a/include/configs/netgear_ms2110.h b/include/configs/netgear_ms2110.h
---- a/include/configs/netgear_ms2110.h 1970-01-01 01:00:00.000000000 +0100
-+++ b/include/configs/netgear_ms2110.h 2020-07-14 17:49:15.000000000 +0200
+--- /dev/null
++++ b/include/configs/netgear_ms2110.h
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2014-2017 bodhi <mibodhi@gmail.com>
--- /dev/null
+--- a/arch/arm/mach-kirkwood/Kconfig
++++ b/arch/arm/mach-kirkwood/Kconfig
+@@ -28,6 +28,9 @@ config TARGET_POGO_E02
+ config TARGET_POGOPLUGV4
+ bool "Pogoplug V4 Board"
+
++config TARGET_DNS320L
++ bool "dns320l Board"
++
+ config TARGET_DNS325
+ bool "dns325 Board"
+
+@@ -93,6 +96,7 @@ source "board/Marvell/sheevaplug/Kconfig
+ source "board/buffalo/lsxl/Kconfig"
+ source "board/cloudengines/pogo_e02/Kconfig"
+ source "board/cloudengines/pogoplugv4/Kconfig"
++source "board/d-link/dns320l/Kconfig"
+ source "board/d-link/dns325/Kconfig"
+ source "board/iomega/iconnect/Kconfig"
+ source "board/keymile/Kconfig"
+--- /dev/null
++++ b/board/d-link/dns320l/dns320l.c
+@@ -0,0 +1,113 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright (C) 2015
++ * Gerald Kerma <dreagle@doukki.net>
++ * Tony Dinh <mibodhi@gmail.com>
++ */
++
++#include <common.h>
++#include <miiphy.h>
++#include <net.h>
++#include <asm/arch/cpu.h>
++#include <asm/arch/soc.h>
++#include <asm/arch/mpp.h>
++#include <asm/arch/gpio.h>
++#include <asm/io.h>
++#include "dns320l.h"
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int board_early_init_f(void)
++{
++ /*
++ * default gpio configuration
++ * There are maximum 64 gpios controlled through 2 sets of registers
++ * the below configuration configures mainly initial LED status
++ */
++ mvebu_config_gpio(DNS320L_OE_VAL_LOW, DNS320L_OE_VAL_HIGH,
++ DNS320L_OE_LOW, DNS320L_OE_HIGH);
++
++ /* (all LEDs & power off active high) */
++ /* Multi-Purpose Pins Functionality configuration */
++ static const u32 kwmpp_config[] = {
++ MPP0_NF_IO2,
++ MPP1_NF_IO3,
++ MPP2_NF_IO4,
++ MPP3_NF_IO5,
++ MPP4_NF_IO6,
++ MPP5_NF_IO7,
++ MPP6_SYSRST_OUTn,
++ MPP7_GPO,
++ MPP8_TW_SDA,
++ MPP9_TW_SCK,
++ MPP10_UART0_TXD,
++ MPP11_UART0_RXD,
++ MPP12_GPO,
++ MPP13_GPIO,
++ MPP14_GPIO,
++ MPP15_GPIO,
++ MPP16_GPIO,
++ MPP17_GPIO,
++ MPP18_NF_IO0,
++ MPP19_NF_IO1,
++ MPP20_SATA1_ACTn, /* sata1(left) status led */
++ MPP21_SATA0_ACTn, /* sata0(right) status led */
++ MPP22_GPIO,
++ MPP23_GPIO,
++ MPP24_GPIO,
++ MPP25_GPIO,
++ MPP26_GPIO,
++ MPP27_GPIO,
++ MPP28_GPIO,
++ MPP29_GPIO,
++ MPP30_GPIO,
++ MPP31_GPIO,
++ MPP32_GPIO,
++ 0
++ };
++ kirkwood_mpp_conf(kwmpp_config, NULL);
++
++ kw_gpio_set_value(DNS320L_GPIO_SATA_EN , 1);
++
++ return 0;
++}
++
++int board_init(void)
++{
++ /* address of boot parameters */
++ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
++
++ return 0;
++}
++
++#ifdef CONFIG_RESET_PHY_R
++/* Configure and initialize PHY */
++void reset_phy(void)
++{
++ u16 reg;
++ u16 phyaddr;
++ char *name = "egiga0";
++
++ if (miiphy_set_current_dev(name))
++ return;
++
++ /* read PHY dev address */
++ if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) {
++ printf("could not read PHY dev address\n");
++ return;
++ }
++
++ /* set RGMII delay */
++ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, MV88E1318_MAC_CTRL_PG);
++ miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, ®);
++ reg |= (MV88E1318_RGMII_RX_CTRL | MV88E1318_RGMII_TX_CTRL);
++ miiphy_write(name, phyaddr, MV88E1318_MAC_CTRL_REG, reg);
++ miiphy_write(name, phyaddr, MV88E1318_PGADR_REG, 0);
++
++ /* reset PHY */
++ if (miiphy_reset(name, phyaddr))
++ return;
++
++ printf("MV88E1318 PHY initialized on %s\n", name);
++}
++#endif /* CONFIG_RESET_PHY_R */
+--- /dev/null
++++ b/board/d-link/dns320l/dns320l.h
+@@ -0,0 +1,39 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright (C) 2011
++ * Stefan Herbrechtsmeier <stefan@herbrechtsmeier.net>
++ *
++ * Based on Kirkwood support:
++ * (C) Copyright 2009
++ * Marvell Semiconductor <www.marvell.com>
++ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
++ */
++
++#ifndef __DNS320L_H
++#define __DNS320L_H
++
++/* GPIO configuration */
++#define DNS320L_GPIO_SATA_EN 24
++#define HDD_L_GREEN_LED (1 << 22)
++#define HDD_R_GREEN_LED (1 << 23)
++#define USB_BLUE_LED (1 << 25)
++#define USB_ORANGE_LED (1 << 26)
++
++#define DNS320L_OE_LOW (~(HDD_L_GREEN_LED | HDD_R_GREEN_LED | \
++ USB_BLUE_LED | USB_ORANGE_LED))
++#define DNS320L_OE_VAL_LOW (0)
++
++/* high GPIO's */
++#define WATCHDOG_SIGNAL (1 << 14)
++
++#define DNS320L_OE_HIGH (~(WATCHDOG_SIGNAL))
++#define DNS320L_OE_VAL_HIGH ((WATCHDOG_SIGNAL))
++
++/* PHY related */
++#define MV88E1318_PGADR_REG 22
++#define MV88E1318_MAC_CTRL_PG 2
++#define MV88E1318_MAC_CTRL_REG 21
++#define MV88E1318_RGMII_TX_CTRL (1 << 4)
++#define MV88E1318_RGMII_RX_CTRL (1 << 5)
++
++#endif /* __DNS320L_H */
+--- /dev/null
++++ b/board/d-link/dns320l/Kconfig
+@@ -0,0 +1,18 @@
++# SPDX-License-Identifier: GPL-2.0+
++#
++# Copyright (C) 2015
++# Gerald Kerma <dreagle@doukki.net>
++# Tony Dinh <mibodhi@gmail.com>
++
++if TARGET_DNS320L
++
++config SYS_BOARD
++ default "dns320l"
++
++config SYS_VENDOR
++ default "d-link"
++
++config SYS_CONFIG_NAME
++ default "dns320l"
++
++endif
+--- /dev/null
++++ b/board/d-link/dns320l/kwbimage.cfg
+@@ -0,0 +1,41 @@
++# SPDX-License-Identifier: GPL-2.0+
++#
++# Copyright (C) 2015
++# Gerald Kerma <dreagle@doukki.net>
++# Tony Dinh <mibodhi@gmail.com>
++# Refer to doc/README.kwbimage for more details about how-to
++# configure and create kirkwood boot images.
++#
++
++# Boot Media configurations
++BOOT_FROM nand
++NAND_ECC_MODE default
++NAND_PAGE_SIZE 0x0800
++
++# Configure RGMII-0 interface pad voltage to 1.8V
++DATA 0xFFD100e0 0x1b1b1b9b
++
++DATA 0xFFD01400 0x43010c30
++DATA 0xFFD01404 0x39543000
++DATA 0xFFD01408 0x22125451
++DATA 0xFFD0140C 0x00000833
++DATA 0xFFD01410 0x0000000C
++DATA 0xFFD01414 0x00000000
++DATA 0xFFD01418 0x00000000
++DATA 0xFFD0141C 0x00000652
++DATA 0xFFD01420 0x00000004
++DATA 0xFFD01424 0x0000F17F
++DATA 0xFFD01428 0x00085520
++DATA 0xFFD0147c 0x00008552
++DATA 0xFFD01504 0x0FFFFFF1
++DATA 0xFFD01508 0x10000000
++DATA 0xFFD0150C 0x00000000
++DATA 0xFFD01514 0x00000000
++DATA 0xFFD0151C 0x00000000
++DATA 0xFFD01494 0x00010000
++DATA 0xFFD01498 0x00000000
++DATA 0xFFD0149C 0x0000E403
++DATA 0xFFD01480 0x00000001
++DATA 0xFFD20134 0x66666666
++DATA 0xFFD20138 0x66666666
++DATA 0x0 0x0
+--- /dev/null
++++ b/board/d-link/dns320l/MAINTAINERS
+@@ -0,0 +1,8 @@
++NSA310S BOARD
++M: Gerald Kerma <dreagle@doukki.net>
++M: Tony Dinh <mibodhi@gmail.com>
++M: Luka Perkov <luka.perkov@sartura.hr>
++S: Maintained
++F: board/d-link/dns320l/
++F: include/configs/dns320l.h
++F: configs/dns320l_defconfig
+--- /dev/null
++++ b/board/d-link/dns320l/Makefile
+@@ -0,0 +1,7 @@
++# SPDX-License-Identifier: GPL-2.0+
++#
++# Copyright (C) 2015
++# Gerald Kerma <dreagle@doukki.net>
++# Tony Dinh <mibodhi@gmail.com>
++
++obj-y := dns320l.o
+--- /dev/null
++++ b/configs/dns320l_defconfig
+@@ -0,0 +1,48 @@
++CONFIG_ARM=y
++CONFIG_SYS_DCACHE_OFF=y
++CONFIG_ARCH_CPU_INIT=y
++CONFIG_KIRKWOOD=y
++CONFIG_SYS_TEXT_BASE=0x600000
++CONFIG_TARGET_DNS320L=y
++CONFIG_ENV_SIZE=0x20000
++CONFIG_ENV_OFFSET=0x100000
++CONFIG_NR_DRAM_BANKS=2
++CONFIG_BOOTDELAY=3
++CONFIG_USE_PREBOOT=y
++# CONFIG_DISPLAY_BOARDINFO is not set
++CONFIG_HUSH_PARSER=y
++CONFIG_SYS_PROMPT="dns320l => "
++CONFIG_CMD_BOOTZ=y
++# CONFIG_CMD_FLASH is not set
++CONFIG_CMD_IDE=y
++CONFIG_CMD_NAND=y
++CONFIG_CMD_USB=y
++# CONFIG_CMD_SETEXPR is not set
++CONFIG_CMD_DHCP=y
++CONFIG_CMD_MII=y
++CONFIG_CMD_PING=y
++CONFIG_CMD_EXT2=y
++CONFIG_CMD_FAT=y
++CONFIG_CMD_JFFS2=y
++CONFIG_CMD_MTDPARTS=y
++CONFIG_MTDPARTS_DEFAULT="mtdparts=orion_nand:0x100000@0x0(uboot),0x20000@0x100000(ubootenv),0x6de0000@0x120000(ubi),0xa00000@0x6f00000(mini),0x500000@0x7900000(config),0x200000@0x7e00000(my-dlink)"
++CONFIG_CMD_UBI=y
++CONFIG_ISO_PARTITION=y
++CONFIG_ENV_IS_IN_NAND=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_MVSATA_IDE=y
++# CONFIG_MMC is not set
++CONFIG_MTD=y
++CONFIG_MTD_RAW_NAND=y
++CONFIG_MVGBE=y
++CONFIG_MII=y
++CONFIG_SYS_NS16550=y
++CONFIG_USB=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_STORAGE=y
++CONFIG_FIT=y
++CONFIG_FIT_VERBOSE=y
++CONFIG_LZMA=y
++CONFIG_LZO=y
++CONFIG_OF_LIBFDT=y
++CONFIG_NET_RANDOM_ETHADDR=y
+--- /dev/null
++++ b/include/configs/dns320l.h
+@@ -0,0 +1,69 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright (C) 2015
++ * Gerald Kerma <dreagle@doukki.net>
++ * Tony Dinh <mibodhi@gmail.com>
++ * Luka Perkov <luka.perkov@sartura.hr>
++ */
++
++#ifndef _CONFIG_DNS320L_H
++#define _CONFIG_DNS320L_H
++
++/* high level configuration options */
++#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */
++#define CONFIG_KW88F6192 1 /* SOC Name */
++#define CONFIG_KW88F6702 1 /* SOC Name */
++#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
++
++/* compression configuration */
++#define CONFIG_BZIP2
++
++/* commands configuration */
++
++/*
++ * mv-common.h should be defined after CMD configs since it used them
++ * to enable certain macros
++ */
++#include "mv-common.h"
++
++/* environment variables configuration */
++
++/* default environment variables */
++#define CONFIG_BOOTCOMMAND \
++ "ubi part ubi; " \
++ "ubi read 0x800000 kernel; " \
++ "bootm 0x800000"
++
++#define CONFIG_EXTRA_ENV_SETTINGS \
++ "console=console=ttyS0,115200\0" \
++ "mtdids=nand0=orion_nand\0" \
++ "mtdparts="CONFIG_MTDPARTS_DEFAULT "\0" \
++ "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
++
++/* Ethernet driver configuration */
++#ifdef CONFIG_CMD_NET
++#define CONFIG_NETCONSOLE
++#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
++#define CONFIG_PHY_BASE_ADR 1
++#define CONFIG_RESET_PHY_R
++#endif /* CONFIG_CMD_NET */
++
++/* SATA driver configuration */
++#ifdef CONFIG_IDE
++#define __io
++#define CONFIG_IDE_PREINIT
++#define CONFIG_MVSATA_IDE_USE_PORT0
++#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
++#endif /* CONFIG_IDE */
++
++/*
++ * Enable GPI0 support
++*/
++#define CONFIG_KIRKWOOD_GPIO
++
++/* RTC driver configuration */
++#ifdef CONFIG_CMD_DATE
++#define CONFIG_RTC_MV
++#endif /* CONFIG_CMD_DATE */
++
++#endif /* _CONFIG_DNS320L_H */
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
-@@ -107,4 +107,7 @@ source "board/alliedtelesis/SBx81LIFXCAT
+@@ -111,4 +111,7 @@ source "board/alliedtelesis/SBx81LIFXCAT
source "board/Marvell/db-88f6281-bp/Kconfig"
source "board/checkpoint/l-50/Kconfig"
endif
--- a/arch/mips/include/asm/arch-vrx200/config.h
+++ b/arch/mips/include/asm/arch-vrx200/config.h
-@@ -167,7 +167,7 @@
+@@ -168,7 +168,7 @@
#define CONFIG_SYS_TEXT_BASE 0xB0000000
#endif
delete mode 100644 include/linux/compiler-gcc4.h
create mode 100644 include/linux/compiler-intel.h
-diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
-index 9896e54..22ab246 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -5,11 +5,28 @@
*/
-#ifndef __pure
-# define __pure __attribute__((pure))
--#endif
--#ifndef __aligned
--# define __aligned(x) __attribute__((aligned(x)))
--#endif
--#define __printf(a,b) __attribute__((format(printf,a,b)))
--#define noinline __attribute__((noinline))
--#define __attribute_const__ __attribute__((__const__))
--#define __maybe_unused __attribute__((unused))
--#define __always_unused __attribute__((unused))
--
--#define __gcc_header(x) #x
--#define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h)
--#define gcc_header(x) _gcc_header(x)
--#include gcc_header(__GNUC__)
+#define __pure __attribute__((pure))
+#define __aligned(x) __attribute__((aligned(x)))
+#define __printf(a, b) __attribute__((format(printf, a, b)))
+
+#if GCC_VERSION >= 30400
+#define __must_check __attribute__((warn_unused_result))
-+#endif
+ #endif
+-#ifndef __aligned
+-# define __aligned(x) __attribute__((aligned(x)))
+
+#if GCC_VERSION >= 40000
+
+
+#if GCC_VERSION >= 40100 && GCC_VERSION < 40600
+# define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
-+#endif
+ #endif
+-#define __printf(a,b) __attribute__((format(printf,a,b)))
+-#define noinline __attribute__((noinline))
+-#define __attribute_const__ __attribute__((__const__))
+-#define __maybe_unused __attribute__((unused))
+-#define __always_unused __attribute__((unused))
+-
+-#define __gcc_header(x) #x
+-#define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h)
+-#define gcc_header(x) _gcc_header(x)
+-#include gcc_header(__GNUC__)
+
+#if GCC_VERSION >= 40300
+/* Mark functions as cold. gcc will assume any path leading to a call
+ * code
+ */
+#define uninitialized_var(x) x = x
-diff --git a/include/linux/compiler-gcc3.h b/include/linux/compiler-gcc3.h
-deleted file mode 100644
-index 2befe65..0000000
--- a/include/linux/compiler-gcc3.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#define uninitialized_var(x) x = x
-
-#define __always_inline inline __attribute__((always_inline))
-diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h
-deleted file mode 100644
-index 27d11ca..0000000
--- a/include/linux/compiler-gcc4.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#define __compiletime_warning(message) __attribute__((warning(message)))
-#define __compiletime_error(message) __attribute__((error(message)))
-#endif
-diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h
-new file mode 100644
-index 0000000..d4c7113
--- /dev/null
+++ b/include/linux/compiler-intel.h
@@ -0,0 +1,45 @@
+#define __builtin_bswap16 _bswap16
+#endif
+
-diff --git a/include/linux/compiler.h b/include/linux/compiler.h
-index 5be3dab..020ad16 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -5,16 +5,24 @@
extern void __chk_user_ptr(const volatile void __user *);
extern void __chk_io_ptr(const volatile void __iomem *);
#else
-@@ -27,20 +35,32 @@ extern void __chk_io_ptr(const volatile void __iomem *);
+@@ -27,20 +35,32 @@ extern void __chk_io_ptr(const volatile
# define __chk_user_ptr(x) (void)0
# define __chk_io_ptr(x) (void)0
# define __builtin_warning(x, y...) (1)
/* Intel compiler defines __GNUC__. So we will overwrite implementations
* coming from above header files here
-@@ -49,6 +69,13 @@ extern void __chk_io_ptr(const volatile void __iomem *);
+@@ -49,6 +69,13 @@ extern void __chk_io_ptr(const volatile
# include <linux/compiler-intel.h>
#endif
/*
* Generic compiler-dependent macros required for kernel
* build go below this comment. Actual compiler/compiler version
-@@ -117,7 +144,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+@@ -117,7 +144,7 @@ void ftrace_likely_update(struct ftrace_
*/
#define if(cond, ...) __trace_if( (cond , ## __VA_ARGS__) )
#define __trace_if(cond) \
({ \
int ______r; \
static struct ftrace_branch_data \
-@@ -144,6 +171,10 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+@@ -144,6 +171,10 @@ void ftrace_likely_update(struct ftrace_
# define barrier() __memory_barrier()
#endif
/* Unreachable code */
#ifndef unreachable
# define unreachable() do { } while (1)
-@@ -156,6 +187,135 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+@@ -156,6 +187,135 @@ void ftrace_likely_update(struct ftrace_
(typeof(ptr)) (__ptr + (off)); })
#endif
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
-@@ -228,7 +388,7 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+@@ -228,7 +388,7 @@ void ftrace_likely_update(struct ftrace_
/*
* Rather then using noinline to prevent stack consumption, use
*/
#define noinline_for_stack noinline
-@@ -270,11 +430,28 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+@@ -270,11 +430,28 @@ void ftrace_likely_update(struct ftrace_
# define __section(S) __attribute__ ((__section__(#S)))
#endif
/* Compile time object size, -1 for unknown */
#ifndef __compiletime_object_size
# define __compiletime_object_size(obj) -1
-@@ -284,7 +461,48 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+@@ -284,8 +461,49 @@ void ftrace_likely_update(struct ftrace_
#endif
#ifndef __compiletime_error
# define __compiletime_error(message)
+# define __compiletime_error_fallback(condition) \
+ do { ((void)sizeof(char[1 - 2 * condition])); } while (0)
+# endif
- #endif
++#endif
+#ifndef __compiletime_error_fallback
+# define __compiletime_error_fallback(condition) do { } while (0)
-+#endif
-+
+ #endif
+
+#define __compiletime_assert(condition, msg, prefix, suffix) \
+ do { \
+ bool __cond = !(condition); \
+#define compiletime_assert_atomic_type(t) \
+ compiletime_assert(__native_word(t), \
+ "Need native word sized stores/loads for atomicity.")
-
++
/*
* Prevent the compiler from merging or refetching accesses. The compiler
-@@ -293,11 +511,45 @@ void ftrace_likely_update(struct ftrace_branch_data *f, int val, int expect);
+ * is also forbidden from reordering successive instances of ACCESS_ONCE(),
+@@ -293,11 +511,45 @@ void ftrace_likely_update(struct ftrace_
* to make the compiler aware of ordering is to put the two invocations of
* ACCESS_ONCE() in different C statements.
*
+# define nokprobe_inline inline
+#endif
#endif /* __LINUX_COMPILER_H */
---
-2.7.4
-
include $(TOPDIR)/rules.mk
PKG_NAME:=uboot-layerscape
-PKG_VERSION:=lf-6.1.1-1.0.0
+PKG_VERSION:=6.6.3.1.0.0
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/nxp-qoriq/u-boot
-PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0
-PKG_MIRROR_HASH:=6cb3cd569f11f582375eb3af475a2a0d77fe602813337b64883ef01344be7bf6
+PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0
+PKG_MIRROR_HASH:=dec5b6e4fe328b930f201fbf06a0a7b71a9dd72f38f16c9570188c0a7fea916a
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/fsl_ls1012a-frdm
NAME:=NXP LS1012AFRDM
UBOOT_CONFIG:=ls1012afrdm_tfa
- ENV_SIZE:=0x40000
endef
define U-Boot/fsl_ls1012a-rdb
NAME:=NXP LS1012ARDB
UBOOT_CONFIG:=ls1012ardb_tfa
- ENV_SIZE:=0x40000
endef
define U-Boot/fsl_ls1012a-frwy-sdboot
NAME:=NXP LS1012AFRWY
UBOOT_CONFIG:=ls1012afrwy_tfa
- ENV_SIZE:=0x10000
endef
define U-Boot/fsl_ls1028a-rdb
+++ /dev/null
-From 089b90b11008ec95a56da12e31d11e3f31a9bb26 Mon Sep 17 00:00:00 2001
-From: Martin Schiller <ms@dev.tdt.de>
-Date: Wed, 17 Nov 2021 07:29:55 +0100
-Subject: [PATCH] board: ls1046ardb: force PCI device enumeration
-
-Commit 045ecf899252 ("configs: enable DM_ETH support for LS1046ARDB")
-resulted in the PCI bus no longer being implicitly enumerated.
-
-However, this is necessary for the fdt pcie fixups to work.
-
-Therefore, similar to commit 8b6558bd4187 ("board: ls1088ardb:
-transition to DM_ETH"), pci_init() is now called in the board_init()
-routine when CONFIG_DM_ETH is active.
-
-Signed-off-by: Martin Schiller <ms@dev.tdt.de>
-CC: Priyanka Jain <priyanka.jain@nxp.com>
----
- board/freescale/ls1046ardb/ls1046ardb.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/board/freescale/ls1046ardb/ls1046ardb.c
-+++ b/board/freescale/ls1046ardb/ls1046ardb.c
-@@ -88,6 +88,10 @@ int board_init(void)
- ppa_init();
- #endif
-
-+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
-+ pci_init();
-+#endif
-+
- /* invert AQR105 IRQ pins polarity */
- out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
-
+++ /dev/null
-From 64d2dffa8b51c1beb7e472690dcac965ac0f7ac4 Mon Sep 17 00:00:00 2001
-From: Martin Schiller <ms@dev.tdt.de>
-Date: Tue, 23 Nov 2021 07:24:19 +0100
-Subject: [PATCH] board: ls1043ardb: force PCI device enumeration
-
-Commit eb1986804d1d ("configs: enable DM_ETH support for LS1043ARDB")
-resulted in the PCI bus no longer being implicitly enumerated.
-
-However, this is necessary for the fdt pcie fixups to work.
-
-Therefore, similar to commit 8b6558bd4187 ("board: ls1088ardb:
-transition to DM_ETH"), pci_init() is now called in the board_init()
-routine when CONFIG_DM_ETH is active.
-
-Signed-off-by: Martin Schiller <ms@dev.tdt.de>
-CC: Priyanka Jain <priyanka.jain@nxp.com>
-CC: Camelia Groza <camelia.groza@nxp.com>
----
- board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/board/freescale/ls1043ardb/ls1043ardb.c
-+++ b/board/freescale/ls1043ardb/ls1043ardb.c
-@@ -214,6 +214,10 @@ int board_init(void)
- ppa_init();
- #endif
-
-+#if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
-+ pci_init();
-+#endif
-+
- #ifdef CONFIG_U_QE
- u_qe_init();
- #endif
-From b382eeafe01df21da3518b2f1dd7d22ee114efb0 Mon Sep 17 00:00:00 2001
+From 54a19a8c97608c71b440639c878f2f57b5add95d Mon Sep 17 00:00:00 2001
From: Pawel Dembicki <paweldembicki@gmail.com>
Date: Mon, 24 Oct 2022 14:19:38 +0200
Subject: [PATCH] layerscape: adjust LS1021A-IOT config for OpenWrt
Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
---
- configs/ls1021aiot_sdcard_defconfig | 3 +++
- include/configs/ls1021aiot.h | 4 ++--
- 2 files changed, 5 insertions(+), 2 deletions(-)
+ configs/ls1021aiot_sdcard_defconfig | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
-@@ -27,8 +27,11 @@ CONFIG_CMD_MII=y
+@@ -24,7 +24,7 @@ CONFIG_AHCI=y
+ CONFIG_LAYERSCAPE_NS_ACCESS=y
+ CONFIG_PCIE1=y
+ CONFIG_PCIE2=y
+-CONFIG_SYS_MONITOR_LEN=524288
++CONFIG_SYS_MONITOR_LEN=786432
+ CONFIG_OF_BOARD_SETUP=y
+ CONFIG_OF_STDOUT_VIA_ALIAS=y
+ CONFIG_RAMBOOT_PBL=y
+@@ -40,7 +40,7 @@ CONFIG_SPL_MAX_SIZE=0x1a000
+ CONFIG_SPL_PAD_TO=0x1c000
+ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+ CONFIG_SPL_BSS_START_ADDR=0x80100000
+-CONFIG_SPL_BSS_MAX_SIZE=0x80000
++CONFIG_SPL_BSS_MAX_SIZE=0xc0000
+ CONFIG_SPL_FSL_PBL=y
+ # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+ CONFIG_SYS_SPL_MALLOC=y
+@@ -66,8 +66,11 @@ CONFIG_CMD_MII=y
# CONFIG_CMD_MDIO is not set
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
---- a/include/configs/ls1021aiot.h
-+++ b/include/configs/ls1021aiot.h
-@@ -78,8 +78,8 @@
- CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
- #define CONFIG_SPL_BSS_START_ADDR 0x80100000
--#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
--#define CONFIG_SYS_MONITOR_LEN 0x80000
-+#define CONFIG_SPL_BSS_MAX_SIZE 0xc0000
-+#define CONFIG_SYS_MONITOR_LEN 0xc0000
- #endif
-
- #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3
endef
+define U-Boot/mt7981_openwrt_one-snand
+ NAME:=OpenWrt One NAND
+ BUILD_SUBTARGET:=filogic
+ BUILD_DEVICES:=openwrt_one
+ UBOOT_CONFIG:=mt7981_openwrt-one-spi-nand
+ UBOOT_IMAGE:=u-boot.fip
+ BL2_BOOTDEV:=spim-nand-ubi
+ BL2_SOC:=mt7981
+ BL2_DDRTYPE:=ddr4
+ DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ubi-ddr4
+endef
+
+define U-Boot/mt7981_openwrt_one-nor
+ NAME:=OpenWrt One NOR
+ BUILD_SUBTARGET:=filogic
+ BUILD_DEVICES:=openwrt_one
+ UBOOT_CONFIG:=mt7981_openwrt-one-nor
+ UBOOT_IMAGE:=u-boot.fip
+ BL2_BOOTDEV:=nor
+ BL2_SOC:=mt7981
+ BL2_DDRTYPE:=ddr4
+ FIP_COMPRESS:=1
+ DEPENDS:=+trusted-firmware-a-mt7981-nor-ddr4
+endef
+
define U-Boot/mt7981_rfb-spim-nand
NAME:=MT7981 Reference Board
BUILD_SUBTARGET:=filogic
mt7622_ubnt_unifi-6-lr-v1 \
mt7622_ubnt_unifi-6-lr-v2 \
mt7622_ubnt_unifi-6-lr-v3 \
- mt7622_xiaomi_redmi-router-ax6s-ubi-loader \
+ mt7622_xiaomi_redmi-router-ax6s-ubi-loader \
mt7623n_bpir2 \
mt7623a_unielec_u7623 \
mt7628_rfb \
mt7981_cmcc_rax3000m-nand \
mt7981_h3c_magic-nx30-pro \
mt7981_jcg_q30-pro \
+ mt7981_openwrt_one-snand \
+ mt7981_openwrt_one-nor \
mt7981_rfb-spim-nand \
mt7981_rfb-emmc \
mt7981_rfb-nor \
CONFIG_MTD=y
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
-@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
+@@ -11,7 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x46000000
CONFIG_DEBUG_UART=y
+-# CONFIG_AUTOBOOT is not set
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_NAND_BOOT=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
- # CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
CONFIG_LOGLEVEL=7
-@@ -22,15 +40,118 @@ CONFIG_SYS_PBSIZE=1049
+ CONFIG_LOG=y
+@@ -22,15 +39,120 @@ CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_EMBED=y
++CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_ENV_OVERWRITE=y
-+CONFIG_ENV_IS_IN_MMC=y
-+CONFIG_ENV_OFFSET=0x400000
-+CONFIG_ENV_OFFSET_REDUND=0x440000
-+CONFIG_ENV_SIZE=0x40000
-+CONFIG_ENV_SIZE_REDUND=0x40000
++CONFIG_ENV_IS_IN_UBI=y
++CONFIG_ENV_UBI_PART="ubi"
++CONFIG_ENV_SIZE=0x1f000
++CONFIG_ENV_SIZE_REDUND=0x1f000
++CONFIG_ENV_UBI_VOLUME="ubootenv"
++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
CONFIG_DOS_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
-@@ -46,6 +167,9 @@ CONFIG_PROT_TCP=y
+@@ -46,6 +168,9 @@ CONFIG_PROT_TCP=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
+--- a/arch/arm/dts/mt7988-rfb.dts
++++ b/arch/arm/dts/mt7988-rfb.dts
+@@ -144,6 +144,23 @@
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "bl2";
++ reg = <0x0 0x200000>;
++ };
++
++ partition@200000 {
++ label = "ubi";
++ reg = <0x200000 0x7e00000>;
++ compatible = "linux,ubi";
++ };
++ };
+ };
+ };
+
--- /dev/null
+From cca5775031e4890f195246772e00f7f4ae7438f6 Mon Sep 17 00:00:00 2001
+From: John Crispin <john@phrozen.org>
+Date: Mon, 19 Feb 2024 05:52:24 +0100
+Subject: [PATCH 1/2] mt7981.dtsi: add USB nodes
+
+Signed-off-by: John Crispin <john@phrozen.org>
+---
+ arch/arm/dts/mt7981.dtsi | 47 ++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/arm/dts/mt7981.dtsi
++++ b/arch/arm/dts/mt7981.dtsi
+@@ -6,6 +6,7 @@
+
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/clock/mt7981-clk.h>
+ #include <dt-bindings/reset/mt7629-reset.h>
+ #include <dt-bindings/pinctrl/mt65xx.h>
+@@ -342,4 +343,50 @@
+ status = "disabled";
+ };
+
++ xhci: xhci@11200000 {
++ compatible = "mediatek,mt7981-xhci",
++ "mediatek,mtk-xhci";
++ reg = <0x11200000 0x2e00>,
++ <0x11203e00 0x0100>;
++ reg-names = "mac", "ippc";
++ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
++ phys = <&u2port0 PHY_TYPE_USB2>,
++ <&u3port0 PHY_TYPE_USB3>;
++ clocks = <&infracfg_ao CK_INFRA_IUSB_SYS_CK>,
++ <&infracfg_ao CK_INFRA_IUSB_CK>,
++ <&infracfg_ao CK_INFRA_IUSB_133_CK>,
++ <&infracfg_ao CK_INFRA_IUSB_66M_CK>,
++ <&topckgen CK_TOP_U2U3_XHCI_SEL>;
++ clock-names = "sys_ck",
++ "ref_ck",
++ "mcu_ck",
++ "dma_ck",
++ "xhci_ck";
++ mediatek,u3p-dis-msk = <0x1>;
++ status = "okay";
++ };
++
++ usbtphy: usb-phy@11e10000 {
++ compatible = "mediatek,mt7981",
++ "mediatek,generic-tphy-v2";
++ #address-cells = <1>;
++ #size-cells = <1>;
++ status = "okay";
++
++ u2port0: usb-phy@11e10000 {
++ reg = <0x11e10000 0x700>;
++ clocks = <&topckgen CK_TOP_USB_FRMCNT_SEL>;
++ clock-names = "ref";
++ #phy-cells = <1>;
++ status = "okay";
++ };
++
++ u3port0: usb-phy@11e10700 {
++ reg = <0x11e10700 0x900>;
++ clocks = <&topckgen CK_TOP_USB3_PHY_SEL>;
++ clock-names = "ref";
++ #phy-cells = <1>;
++ status = "okay";
++ };
++ };
+ };
--- /dev/null
+--- /dev/null
++++ b/arch/arm/dts/openwrt-one.dts
+@@ -0,0 +1,203 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2024 John Crispin <john@phrozen.org>
++ */
++
++/dts-v1/;
++#include "mt7981.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++
++/ {
++ #address-cells = <1>;
++ #size-cells = <1>;
++ model = "OpenWrt One";
++ compatible = "openwrt,one", "mediatek,mt7981";
++ chosen {
++ stdout-path = &uart0;
++ tick-timer = &timer0;
++ };
++
++ memory@40000000 {
++ device_type = "memory";
++ reg = <0x40000000 0x10000000>;
++ };
++
++ keys {
++ compatible = "gpio-keys";
++
++ user {
++ label = "front";
++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
++ linux,code = <BTN_0>;
++ };
++
++ reset {
++ label = "back";
++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
++ linux,code = <BTN_1>;
++ };
++ };
++
++ leds {
++ compatible = "gpio-leds";
++
++ red {
++ label = "red";
++ gpios = <&gpio 9 GPIO_ACTIVE_HIGH>;
++ };
++
++ white {
++ label = "white";
++ gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
++ };
++
++ green {
++ label = "green";
++ gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
++ };
++ };
++};
++
++&uart0 {
++ status = "okay";
++};
++
++ð {
++ status = "okay";
++ mediatek,gmac-id = <1>;
++ phy-mode = "gmii";
++ phy-handle = <&phy0>;
++
++ phy0: eth-phy@0 {
++ compatible = "ethernet-phy-ieee802.3-c22";
++ reg = <0>;
++ };
++};
++
++&pinctrl {
++ spi_flash_pins: spi0-pins-func-1 {
++ mux {
++ function = "flash";
++ groups = "spi0", "spi0_wp_hold";
++ };
++
++ conf-pu {
++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
++ drive-strength = <MTK_DRIVE_8mA>;
++ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
++ };
++
++ conf-pd {
++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
++ drive-strength = <MTK_DRIVE_8mA>;
++ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
++ };
++ };
++
++ spi2_flash_pins: spi2-spi2-pins {
++ mux {
++ function = "spi";
++ groups = "spi2", "spi2_wp_hold";
++ };
++
++ conf-pu {
++ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
++ drive-strength = <MTK_DRIVE_8mA>;
++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
++ };
++
++ conf-pd {
++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
++ drive-strength = <MTK_DRIVE_8mA>;
++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
++ };
++ };
++};
++
++&spi0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi_flash_pins>;
++ status = "okay";
++ must_tx;
++ enhance_timing;
++ dma_ext;
++ ipm_design;
++ support_quad;
++ tick_dly = <2>;
++ sample_sel = <0>;
++
++ spi_nand@0 {
++ compatible = "spi-nand";
++ reg = <0>;
++ spi-max-frequency = <52000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@0 {
++ label = "bl2";
++ reg = <0x0 0x100000>;
++ };
++
++ partition@200000 {
++ label = "ubi";
++ reg = <0x100000 0x7f00000>;
++ };
++ };
++ };
++};
++
++&spi2 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi2_flash_pins>;
++ status = "okay";
++ must_tx;
++ enhance_timing;
++ dma_ext;
++ ipm_design;
++ tick_dly = <2>;
++ sample_sel = <0>;
++
++ spi_nor@0 {
++ compatible = "jedec,spi-nor";
++ reg = <0>;
++ spi-max-frequency = <5000000>;
++
++ partitions {
++ compatible = "fixed-partitions";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ partition@00000 {
++ label = "bl2-nor";
++ reg = <0x00000 0x0040000>;
++ };
++
++ partition@40000 {
++ label = "factory";
++ reg = <0x40000 0x00C0000>;
++ };
++
++ partition@100000 {
++ label = "fip-nor";
++ reg = <0x100000 0x0080000>;
++ };
++
++ partition@180000 {
++ label = "recovery";
++ reg = <0x180000 0xc80000>;
++ };
++ };
++ };
++};
++
++&watchdog {
++ status = "disabled";
++};
+--- /dev/null
++++ b/configs/mt7981_openwrt-one-nor_defconfig
+@@ -0,0 +1,1811 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# U-Boot 2024.01 Configuration
++#
++
++#
++# Compiler: aarch64-openwrt-linux-musl-gcc (OpenWrt GCC 13.2.0 r26144+12-219018185e) 13.2.0
++#
++CONFIG_CREATE_ARCH_SYMLINK=y
++CONFIG_SYS_CACHE_SHIFT_6=y
++CONFIG_SYS_CACHELINE_SIZE=64
++CONFIG_LINKER_LIST_ALIGN=8
++# CONFIG_ARC is not set
++CONFIG_ARM=y
++# CONFIG_M68K is not set
++# CONFIG_MICROBLAZE is not set
++# CONFIG_MIPS is not set
++# CONFIG_NIOS2 is not set
++# CONFIG_PPC is not set
++# CONFIG_RISCV is not set
++# CONFIG_SANDBOX is not set
++# CONFIG_SH is not set
++# CONFIG_X86 is not set
++# CONFIG_XTENSA is not set
++CONFIG_SYS_ARCH="arm"
++CONFIG_SYS_CPU="armv8"
++CONFIG_SYS_SOC="mediatek"
++CONFIG_SYS_VENDOR="mediatek"
++CONFIG_SYS_BOARD="mt7981"
++CONFIG_SYS_CONFIG_NAME="mt7981"
++
++#
++# Skipping low level initialization functions
++#
++# CONFIG_SKIP_LOWLEVEL_INIT is not set
++# CONFIG_SKIP_LOWLEVEL_INIT_ONLY is not set
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_SYS_NONCACHED_MEMORY=0x100000
++# CONFIG_SYS_ICACHE_OFF is not set
++# CONFIG_SYS_DCACHE_OFF is not set
++
++#
++# ARM architecture
++#
++CONFIG_ARM64=y
++CONFIG_ARM64_CRC32=y
++CONFIG_COUNTER_FREQUENCY=0
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_INIT_SP_RELATIVE=y
++CONFIG_SYS_INIT_SP_BSS_OFFSET=524288
++# CONFIG_GIC_V3_ITS is not set
++CONFIG_STATIC_RELA=y
++CONFIG_DMA_ADDR_T_64BIT=y
++CONFIG_GPIO_EXTRA_HEADER=y
++CONFIG_ARM_ASM_UNIFIED=y
++# CONFIG_SYS_ARM_CACHE_CP15 is not set
++# CONFIG_SYS_ARM_MMU is not set
++# CONFIG_SYS_ARM_MPU is not set
++CONFIG_SYS_ARM_ARCH=8
++CONFIG_SYS_ARM_CACHE_WRITEBACK=y
++# CONFIG_SYS_ARM_CACHE_WRITETHROUGH is not set
++# CONFIG_SYS_ARM_CACHE_WRITEALLOC is not set
++# CONFIG_ARCH_CPU_INIT is not set
++CONFIG_SYS_ARCH_TIMER=y
++CONFIG_ARM_SMCCC=y
++# CONFIG_SYS_L2_PL310 is not set
++# CONFIG_SPL_SYS_L2_PL310 is not set
++# CONFIG_SYS_L2CACHE_OFF is not set
++# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
++# CONFIG_USE_ARCH_MEMCPY is not set
++# CONFIG_USE_ARCH_MEMSET is not set
++CONFIG_ARM64_SUPPORT_AARCH32=y
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_HISTB is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_TARGET_STV0991 is not set
++# CONFIG_ARCH_BCM283X is not set
++# CONFIG_ARCH_BCMSTB is not set
++# CONFIG_ARCH_BCMBCA is not set
++# CONFIG_TARGET_VEXPRESS_CA9X4 is not set
++# CONFIG_TARGET_BCMNS is not set
++# CONFIG_TARGET_BCMNS2 is not set
++# CONFIG_TARGET_BCMNS3 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_S5PC1XX is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_IPQ40XX is not set
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_K3 is not set
++# CONFIG_ARCH_OMAP2PLUS is not set
++# CONFIG_ARCH_MESON is not set
++CONFIG_ARCH_MEDIATEK=y
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_IMX8 is not set
++# CONFIG_ARCH_IMX8M is not set
++# CONFIG_ARCH_IMX8ULP is not set
++# CONFIG_ARCH_IMX9 is not set
++# CONFIG_ARCH_IMXRT is not set
++# CONFIG_ARCH_MX23 is not set
++# CONFIG_ARCH_MX28 is not set
++# CONFIG_ARCH_MX31 is not set
++# CONFIG_ARCH_MX7ULP is not set
++# CONFIG_ARCH_MX7 is not set
++# CONFIG_ARCH_MX6 is not set
++# CONFIG_ARCH_MX5 is not set
++# CONFIG_ARCH_NEXELL is not set
++# CONFIG_ARCH_NPCM is not set
++# CONFIG_ARCH_APPLE is not set
++# CONFIG_ARCH_OWL is not set
++# CONFIG_ARCH_QEMU is not set
++# CONFIG_ARCH_RMOBILE is not set
++# CONFIG_ARCH_SNAPDRAGON is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VERSAL is not set
++# CONFIG_ARCH_VERSAL_NET is not set
++# CONFIG_ARCH_VF610 is not set
++# CONFIG_ARCH_ZYNQ is not set
++# CONFIG_ARCH_ZYNQMP_R5 is not set
++# CONFIG_ARCH_ZYNQMP is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_VEXPRESS64 is not set
++# CONFIG_TARGET_CORSTONE1000 is not set
++# CONFIG_TARGET_TOTAL_COMPUTE is not set
++# CONFIG_TARGET_LS2080A_EMU is not set
++# CONFIG_TARGET_LS1088AQDS is not set
++# CONFIG_TARGET_LS2080AQDS is not set
++# CONFIG_TARGET_LS2080ARDB is not set
++# CONFIG_TARGET_LS2081ARDB is not set
++# CONFIG_TARGET_LX2160ARDB is not set
++# CONFIG_TARGET_LX2160AQDS is not set
++# CONFIG_TARGET_LX2162AQDS is not set
++# CONFIG_TARGET_HIKEY is not set
++# CONFIG_TARGET_HIKEY960 is not set
++# CONFIG_TARGET_POPLAR is not set
++# CONFIG_TARGET_LS1012AQDS is not set
++# CONFIG_TARGET_LS1012ARDB is not set
++# CONFIG_TARGET_LS1012A2G5RDB is not set
++# CONFIG_TARGET_LS1012AFRWY is not set
++# CONFIG_TARGET_LS1012AFRDM is not set
++# CONFIG_TARGET_LS1028AQDS is not set
++# CONFIG_TARGET_LS1028ARDB is not set
++# CONFIG_TARGET_LS1088ARDB is not set
++# CONFIG_TARGET_LS1021AQDS is not set
++# CONFIG_TARGET_LS1021ATWR is not set
++# CONFIG_TARGET_PG_WCOM_SELI8 is not set
++# CONFIG_TARGET_PG_WCOM_EXPU1 is not set
++# CONFIG_TARGET_LS1021ATSN is not set
++# CONFIG_TARGET_LS1021AIOT is not set
++# CONFIG_TARGET_LS1043AQDS is not set
++# CONFIG_TARGET_LS1043ARDB is not set
++# CONFIG_TARGET_LS1046AQDS is not set
++# CONFIG_TARGET_LS1046ARDB is not set
++# CONFIG_TARGET_LS1046AFRWY is not set
++# CONFIG_TARGET_SL28 is not set
++# CONFIG_TARGET_TEN64 is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_SYNQUACER is not set
++# CONFIG_ARCH_STM32 is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_STM32MP is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_OCTEONTX is not set
++# CONFIG_ARCH_OCTEONTX2 is not set
++# CONFIG_TARGET_THUNDERX_88XX is not set
++# CONFIG_ARCH_ASPEED is not set
++# CONFIG_TARGET_DURIAN is not set
++# CONFIG_TARGET_POMELO is not set
++# CONFIG_TARGET_PRESIDIO_ASIC is not set
++# CONFIG_TARGET_XENGUEST_ARM64 is not set
++# CONFIG_ARCH_GXP is not set
++# CONFIG_STATIC_MACH_TYPE is not set
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_LEN=0x400000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_ENV_SOURCE_FILE=""
++CONFIG_SF_DEFAULT_SPEED=1000000
++CONFIG_SF_DEFAULT_MODE=0x0
++CONFIG_ENV_SIZE=0x8000
++CONFIG_DM_GPIO=y
++CONFIG_DEFAULT_DEVICE_TREE="openwrt-one"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x8000
++CONFIG_DM_RESET=y
++CONFIG_SYS_MONITOR_LEN=0
++# CONFIG_MT8512 is not set
++# CONFIG_TARGET_MT7622 is not set
++# CONFIG_TARGET_MT7623 is not set
++# CONFIG_TARGET_MT7629 is not set
++CONFIG_TARGET_MT7981=y
++# CONFIG_TARGET_MT7986 is not set
++# CONFIG_TARGET_MT7988 is not set
++# CONFIG_TARGET_MT8183 is not set
++# CONFIG_TARGET_MT8512 is not set
++# CONFIG_TARGET_MT8516 is not set
++# CONFIG_TARGET_MT8518 is not set
++CONFIG_MTK_BROM_HEADER_INFO="media=snand;nandinfo=2k+64"
++CONFIG_RESET_BUTTON_LABEL="back"
++CONFIG_RESET_BUTTON_SETTLE_DELAY=0
++CONFIG_ERR_PTR_OFFSET=0x0
++# CONFIG_SPL is not set
++CONFIG_BOOTSTAGE_STASH_ADDR=0x0
++CONFIG_DEBUG_UART_BASE=0x11002000
++CONFIG_DEBUG_UART_CLOCK=40000000
++# CONFIG_DEBUG_UART_BOARD_INIT is not set
++CONFIG_IDENT_STRING=""
++CONFIG_SYS_CLK_FREQ=0
++# CONFIG_CHIP_DIP_SCAN is not set
++# CONFIG_CMO_BY_VA_ONLY is not set
++# CONFIG_ARMV8_MULTIENTRY is not set
++# CONFIG_ARMV8_SET_SMPEN is not set
++# CONFIG_ARMV8_SWITCH_TO_EL1 is not set
++
++#
++# ARMv8 secure monitor firmware
++#
++# CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT is not set
++CONFIG_PSCI_RESET=y
++# CONFIG_ARMV8_PSCI is not set
++# CONFIG_ARMV8_EA_EL3_FIRST is not set
++# CONFIG_ARMV8_CRYPTO is not set
++# CONFIG_CMD_DEKBLOB is not set
++# CONFIG_IMX_CAAM_DEK_ENCAP is not set
++# CONFIG_IMX_OPTEE_DEK_ENCAP is not set
++# CONFIG_IMX_SECO_DEK_ENCAP is not set
++# CONFIG_IMX_ELE_DEK_ENCAP is not set
++# CONFIG_CMD_HDMIDETECT is not set
++CONFIG_IMX_DCD_ADDR=0x00910000
++CONFIG_SYS_MEM_TOP_HIDE=0x0
++CONFIG_SYS_LOAD_ADDR=0x46000000
++
++#
++# ARM debug
++#
++CONFIG_BUILD_TARGET=""
++# CONFIG_PCI is not set
++CONFIG_FWU_NUM_BANKS=2
++CONFIG_FWU_NUM_IMAGES_PER_BANK=2
++CONFIG_DEBUG_UART=y
++# CONFIG_AHCI is not set
++# CONFIG_OF_BOARD_FIXUP is not set
++
++#
++# Functionality shared between NXP SoCs
++#
++# CONFIG_NXP_ESBC is not set
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_CC_IS_GCC=y
++CONFIG_GCC_VERSION=130200
++CONFIG_CLANG_VERSION=0
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++# CONFIG_CC_OPTIMIZE_FOR_SPEED is not set
++# CONFIG_CC_OPTIMIZE_FOR_DEBUG is not set
++# CONFIG_OPTIMIZE_INLINING is not set
++CONFIG_ARCH_SUPPORTS_LTO=y
++# CONFIG_LTO is not set
++CONFIG_CC_HAS_ASM_INLINE=y
++# CONFIG_XEN is not set
++# CONFIG_ENV_VARS_UBOOT_CONFIG is not set
++# CONFIG_SYS_BOOT_GET_CMDLINE is not set
++# CONFIG_SYS_BOOT_GET_KBD is not set
++CONFIG_SYS_MALLOC_F=y
++# CONFIG_VALGRIND is not set
++CONFIG_EXPERT=y
++CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
++# CONFIG_SYS_MALLOC_DEFAULT_TO_INIT is not set
++# CONFIG_TOOLS_DEBUG is not set
++CONFIG_PHYS_64BIT=y
++CONFIG_FDT_64BIT=y
++# CONFIG_REMAKE_ELF is not set
++# CONFIG_HAS_BOARD_SIZE_LIMIT is not set
++# CONFIG_SYS_CUSTOM_LDSCRIPT is not set
++CONFIG_PLATFORM_ELFENTRY="_start"
++CONFIG_STACK_SIZE=0x1000000
++CONFIG_SYS_SRAM_BASE=0x0
++CONFIG_SYS_SRAM_SIZE=0x0
++# CONFIG_MP is not set
++CONFIG_HAVE_TEXT_BASE=y
++# CONFIG_HAVE_SYS_UBOOT_START is not set
++CONFIG_SYS_UBOOT_START=0x41e00000
++# CONFIG_DYNAMIC_SYS_CLK_FREQ is not set
++# CONFIG_API is not set
++
++#
++# Boot options
++#
++
++#
++# Boot images
++#
++# CONFIG_ANDROID_BOOT_IMAGE is not set
++# CONFIG_TIMESTAMP is not set
++CONFIG_FIT=y
++CONFIG_FIT_EXTERNAL_OFFSET=0x0
++CONFIG_FIT_FULL_CHECK=y
++# CONFIG_FIT_SIGNATURE is not set
++# CONFIG_FIT_CIPHER is not set
++# CONFIG_FIT_VERBOSE is not set
++# CONFIG_FIT_BEST_MATCH is not set
++CONFIG_FIT_PRINT=y
++# CONFIG_SPL_LOAD_FIT_FULL is not set
++CONFIG_PXE_UTILS=y
++CONFIG_BOOTSTD=y
++# CONFIG_BOOTSTD_FULL is not set
++# CONFIG_BOOTSTD_DEFAULTS is not set
++CONFIG_BOOTSTD_BOOTCOMMAND=y
++CONFIG_BOOTMETH_GLOBAL=y
++# CONFIG_BOOTMETH_CROS is not set
++CONFIG_BOOTMETH_EXTLINUX=y
++CONFIG_BOOTMETH_EXTLINUX_PXE=y
++CONFIG_BOOTMETH_EFILOADER=y
++CONFIG_BOOTMETH_VBE=y
++CONFIG_BOOTMETH_VBE_REQUEST=y
++CONFIG_BOOTMETH_VBE_SIMPLE=y
++CONFIG_BOOTMETH_VBE_SIMPLE_OS=y
++# CONFIG_BOOTMETH_SCRIPT is not set
++CONFIG_LEGACY_IMAGE_FORMAT=y
++# CONFIG_SUPPORT_RAW_INITRD is not set
++# CONFIG_CHROMEOS is not set
++# CONFIG_CHROMEOS_VBOOT is not set
++# CONFIG_RAMBOOT_PBL is not set
++CONFIG_SYS_BOOT_RAMDISK_HIGH=y
++# CONFIG_DISTRO_DEFAULTS is not set
++
++#
++# Boot timing
++#
++# CONFIG_BOOTSTAGE is not set
++CONFIG_BOOTSTAGE_STASH_SIZE=0x1000
++# CONFIG_SHOW_BOOT_PROGRESS is not set
++
++#
++# Boot media
++#
++CONFIG_NAND_BOOT=y
++# CONFIG_ONENAND_BOOT is not set
++# CONFIG_QSPI_BOOT is not set
++# CONFIG_SATA_BOOT is not set
++# CONFIG_SD_BOOT is not set
++# CONFIG_SD_BOOT_QSPI is not set
++CONFIG_SPI_BOOT=y
++
++#
++# Autoboot options
++#
++CONFIG_AUTOBOOT=y
++CONFIG_BOOTDELAY=2
++# CONFIG_AUTOBOOT_KEYED is not set
++# CONFIG_AUTOBOOT_USE_MENUKEY is not set
++CONFIG_AUTOBOOT_MENU_SHOW=y
++# CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE is not set
++# CONFIG_BOOT_RETRY is not set
++
++#
++# Image support
++#
++# CONFIG_IMAGE_PRE_LOAD is not set
++
++#
++# Devicetree fixup
++#
++# CONFIG_OF_BOARD_SETUP is not set
++# CONFIG_OF_SYSTEM_SETUP is not set
++# CONFIG_OF_STDOUT_VIA_ALIAS is not set
++# CONFIG_FDT_FIXUP_PARTITIONS is not set
++# CONFIG_FDT_SIMPLEFB is not set
++CONFIG_ARCH_FIXUP_FDT_MEMORY=y
++# CONFIG_USE_BOOTARGS is not set
++# CONFIG_BOOTARGS_SUBST is not set
++# CONFIG_USE_BOOTCOMMAND is not set
++CONFIG_USE_PREBOOT=y
++CONFIG_DEFAULT_FDT_FILE="openwrt-one"
++# CONFIG_SAVE_PREV_BL_FDT_ADDR is not set
++# CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR is not set
++
++#
++# Configuration editor
++#
++# CONFIG_CEDIT is not set
++
++#
++# Console
++#
++CONFIG_MENU=y
++# CONFIG_CONSOLE_RECORD is not set
++# CONFIG_DISABLE_CONSOLE is not set
++CONFIG_LOGLEVEL=7
++# CONFIG_SILENT_CONSOLE is not set
++# CONFIG_SPL_SILENT_CONSOLE is not set
++# CONFIG_TPL_SILENT_CONSOLE is not set
++# CONFIG_PRE_CONSOLE_BUFFER is not set
++CONFIG_CONSOLE_FLUSH_SUPPORT=y
++# CONFIG_CONSOLE_FLUSH_ON_NEWLINE is not set
++# CONFIG_CONSOLE_MUX is not set
++# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set
++# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set
++# CONFIG_SYS_CONSOLE_INFO_QUIET is not set
++# CONFIG_SYS_STDIO_DEREGISTER is not set
++# CONFIG_SPL_SYS_STDIO_DEREGISTER is not set
++# CONFIG_SYS_DEVICE_NULLDEV is not set
++
++#
++# Logging
++#
++CONFIG_LOG=y
++CONFIG_LOG_MAX_LEVEL=6
++CONFIG_LOG_DEFAULT_LEVEL=6
++CONFIG_LOG_CONSOLE=y
++# CONFIG_LOGF_FILE is not set
++# CONFIG_LOGF_LINE is not set
++# CONFIG_LOGF_FUNC is not set
++CONFIG_LOGF_FUNC_PAD=20
++# CONFIG_LOG_SYSLOG is not set
++# CONFIG_LOG_ERROR_RETURN is not set
++
++#
++# Init options
++#
++# CONFIG_BOARD_TYPES is not set
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DISPLAY_BOARDINFO=y
++# CONFIG_DISPLAY_BOARDINFO_LATE is not set
++
++#
++# Start-up hooks
++#
++# CONFIG_CYCLIC is not set
++CONFIG_EVENT=y
++CONFIG_EVENT_DYNAMIC=y
++# CONFIG_EVENT_DEBUG is not set
++# CONFIG_ARCH_MISC_INIT is not set
++# CONFIG_BOARD_EARLY_INIT_F is not set
++# CONFIG_BOARD_EARLY_INIT_R is not set
++# CONFIG_BOARD_POSTCLK_INIT is not set
++CONFIG_BOARD_LATE_INIT=y
++# CONFIG_CLOCKS is not set
++# CONFIG_HWCONFIG is not set
++CONFIG_LAST_STAGE_INIT=y
++# CONFIG_MISC_INIT_R is not set
++# CONFIG_SYS_MALLOC_BOOTPARAMS is not set
++# CONFIG_ID_EEPROM is not set
++# CONFIG_RESET_PHY_R is not set
++
++#
++# Security support
++#
++CONFIG_HASH=y
++# CONFIG_STACKPROTECTOR is not set
++# CONFIG_BOARD_RNG_SEED is not set
++
++#
++# Update support
++#
++# CONFIG_UPDATE_TFTP is not set
++# CONFIG_ANDROID_AB is not set
++
++#
++# Blob list
++#
++# CONFIG_BLOBLIST is not set
++CONFIG_SUPPORT_SPL=y
++# CONFIG_VPL is not set
++
++#
++# Command line interface
++#
++CONFIG_CMDLINE=y
++CONFIG_HUSH_PARSER=y
++CONFIG_CMDLINE_EDITING=y
++# CONFIG_CMDLINE_PS_SUPPORT is not set
++CONFIG_AUTO_COMPLETE=y
++CONFIG_SYS_LONGHELP=y
++CONFIG_SYS_PROMPT="OpenWrt One> "
++CONFIG_SYS_PROMPT_HUSH_PS2="> "
++CONFIG_SYS_MAXARGS=16
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_SYS_XTRACE=y
++CONFIG_BUILD_BIN2C=y
++
++#
++# Commands
++#
++
++#
++# Info commands
++#
++CONFIG_CMD_BDI=y
++# CONFIG_CMD_BDINFO_EXTRA is not set
++# CONFIG_CMD_CONFIG is not set
++CONFIG_CMD_CONSOLE=y
++CONFIG_CMD_CPU=y
++# CONFIG_CMD_HISTORY is not set
++CONFIG_CMD_LICENSE=y
++# CONFIG_CMD_PMC is not set
++
++#
++# Boot commands
++#
++CONFIG_CMD_BOOTD=y
++CONFIG_CMD_BOOTM=y
++# CONFIG_CMD_BOOTDEV is not set
++CONFIG_CMD_BOOTFLOW=y
++# CONFIG_CMD_BOOTMETH is not set
++CONFIG_BOOTM_EFI=y
++# CONFIG_CMD_BOOTZ is not set
++CONFIG_CMD_BOOTI=y
++CONFIG_BOOTM_LINUX=y
++# CONFIG_BOOTM_NETBSD is not set
++# CONFIG_BOOTM_OPENRTOS is not set
++# CONFIG_BOOTM_OSE is not set
++# CONFIG_BOOTM_PLAN9 is not set
++# CONFIG_BOOTM_RTEMS is not set
++# CONFIG_CMD_VBE is not set
++# CONFIG_BOOTM_VXWORKS is not set
++CONFIG_SYS_BOOTM_LEN=0x4000000
++CONFIG_CMD_BOOTEFI=y
++CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
++# CONFIG_CMD_BOOTEFI_HELLO is not set
++# CONFIG_CMD_BOOTEFI_SELFTEST is not set
++CONFIG_CMD_BOOTMENU=y
++# CONFIG_CMD_ADTIMG is not set
++CONFIG_CMD_ELF=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_GO=y
++CONFIG_CMD_RUN=y
++CONFIG_CMD_IMI=y
++# CONFIG_CMD_IMLS is not set
++CONFIG_CMD_XIMG=y
++# CONFIG_CMD_ZBOOT is not set
++
++#
++# Environment commands
++#
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_EXPORTENV=y
++CONFIG_CMD_IMPORTENV=y
++CONFIG_CMD_EDITENV=y
++# CONFIG_CMD_GREPENV is not set
++CONFIG_CMD_SAVEENV=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_ENV_EXISTS=y
++CONFIG_CMD_ENV_READMEM=y
++# CONFIG_CMD_ENV_CALLBACK is not set
++CONFIG_CMD_ENV_FLAGS=y
++# CONFIG_CMD_NVEDIT_EFI is not set
++# CONFIG_CMD_NVEDIT_INDIRECT is not set
++# CONFIG_CMD_NVEDIT_INFO is not set
++# CONFIG_CMD_NVEDIT_LOAD is not set
++# CONFIG_CMD_NVEDIT_SELECT is not set
++
++#
++# Memory commands
++#
++# CONFIG_CMD_BINOP is not set
++# CONFIG_CMD_BLOBLIST is not set
++CONFIG_CMD_CRC32=y
++# CONFIG_CRC32_VERIFY is not set
++# CONFIG_CMD_EEPROM is not set
++# CONFIG_LOOPW is not set
++# CONFIG_CMD_MD5SUM is not set
++# CONFIG_CMD_MEMINFO is not set
++CONFIG_CMD_MEMORY=y
++# CONFIG_CMD_MEM_SEARCH is not set
++# CONFIG_CMD_MX_CYCLIC is not set
++CONFIG_CMD_RANDOM=y
++# CONFIG_CMD_MEMTEST is not set
++# CONFIG_CMD_SHA1SUM is not set
++CONFIG_CMD_STRINGS=y
++
++#
++# Compression commands
++#
++CONFIG_CMD_LZMADEC=y
++# CONFIG_CMD_UNLZ4 is not set
++# CONFIG_CMD_UNZIP is not set
++# CONFIG_CMD_ZIP is not set
++
++#
++# Device access commands
++#
++# CONFIG_CMD_ARMFLASH is not set
++# CONFIG_CMD_BIND is not set
++# CONFIG_CMD_CLK is not set
++# CONFIG_CMD_DEMO is not set
++# CONFIG_CMD_DFU is not set
++CONFIG_CMD_DM=y
++CONFIG_CMD_FLASH=y
++# CONFIG_CMD_FPGAD is not set
++# CONFIG_CMD_FUSE is not set
++CONFIG_CMD_GPIO=y
++# CONFIG_CMD_GPIO_READ is not set
++CONFIG_CMD_PWM=y
++# CONFIG_CMD_GPT is not set
++# CONFIG_RANDOM_UUID is not set
++# CONFIG_CMD_IDE is not set
++# CONFIG_CMD_IO is not set
++# CONFIG_CMD_IOTRACE is not set
++# CONFIG_CMD_I2C is not set
++CONFIG_CMD_LOADB=y
++# CONFIG_CMD_LOADM is not set
++CONFIG_CMD_LOADS=y
++# CONFIG_LOADS_ECHO is not set
++# CONFIG_CMD_SAVES is not set
++# CONFIG_SYS_LOADS_BAUD_CHANGE is not set
++CONFIG_CMD_LOADXY_TIMEOUT=90
++# CONFIG_CMD_LSBLK is not set
++# CONFIG_CMD_MBR is not set
++# CONFIG_CMD_CLONE is not set
++CONFIG_CMD_MTD=y
++CONFIG_CMD_NAND_EXT=y
++# CONFIG_CMD_ONENAND is not set
++# CONFIG_CMD_OSD is not set
++# CONFIG_CMD_PART is not set
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PINMUX=y
++# CONFIG_CMD_POWEROFF is not set
++# CONFIG_CMD_READ is not set
++# CONFIG_CMD_SATA is not set
++# CONFIG_CMD_SDRAM is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_SF_TEST=y
++# CONFIG_CMD_SPI is not set
++# CONFIG_CMD_TSI148 is not set
++# CONFIG_CMD_UNIVERSE is not set
++CONFIG_CMD_USB=y
++# CONFIG_CMD_USB_SDP is not set
++# CONFIG_CMD_RKMTD is not set
++# CONFIG_CMD_WRITE is not set
++
++#
++# Shell scripting commands
++#
++# CONFIG_CMD_CAT is not set
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_SETEXPR=y
++# CONFIG_CMD_SETEXPR_FMT is not set
++# CONFIG_CMD_XXD is not set
++
++#
++# Android support commands
++#
++CONFIG_CMD_NET=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_DHCP=y
++# CONFIG_BOOTP_MAY_FAIL is not set
++CONFIG_BOOTP_BOOTPATH=y
++# CONFIG_BOOTP_VENDOREX is not set
++# CONFIG_BOOTP_BOOTFILESIZE is not set
++CONFIG_BOOTP_DNS=y
++# CONFIG_BOOTP_DNS2 is not set
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_HOSTNAME=y
++# CONFIG_BOOTP_PREFER_SERVERIP is not set
++CONFIG_BOOTP_SUBNETMASK=y
++# CONFIG_BOOTP_NISDOMAIN is not set
++# CONFIG_BOOTP_NTPSERVER is not set
++# CONFIG_BOOTP_TIMEOFFSET is not set
++# CONFIG_CMD_PCAP is not set
++CONFIG_BOOTP_PXE=y
++CONFIG_BOOTP_PXE_CLIENTARCH=0x16
++# CONFIG_BOOTP_PXE_DHCP_OPTION is not set
++CONFIG_BOOTP_VCI_STRING="U-Boot.armv8"
++CONFIG_CMD_TFTPBOOT=y
++# CONFIG_CMD_TFTPPUT is not set
++CONFIG_CMD_TFTPSRV=y
++CONFIG_NET_TFTP_VARS=y
++CONFIG_CMD_RARP=y
++# CONFIG_CMD_NFS is not set
++# CONFIG_SYS_DISABLE_AUTOLOAD is not set
++# CONFIG_CMD_WGET is not set
++# CONFIG_CMD_MII is not set
++# CONFIG_CMD_MDIO is not set
++CONFIG_CMD_PING=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_ETHSW is not set
++CONFIG_CMD_PXE=y
++# CONFIG_CMD_WOL is not set
++
++#
++# Misc commands
++#
++# CONFIG_CMD_2048 is not set
++# CONFIG_CMD_BSP is not set
++CONFIG_CMD_BLOCK_CACHE=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++# CONFIG_CMD_CONITRACE is not set
++# CONFIG_CMD_CLS is not set
++# CONFIG_CMD_EFIDEBUG is not set
++CONFIG_CMD_EFICONFIG=y
++# CONFIG_CMD_EXCEPTION is not set
++CONFIG_CMD_LED=y
++# CONFIG_CMD_INI is not set
++# CONFIG_CMD_DATE is not set
++# CONFIG_CMD_TIME is not set
++# CONFIG_CMD_GETTIME is not set
++# CONFIG_CMD_PAUSE is not set
++CONFIG_CMD_SLEEP=y
++# CONFIG_CMD_TIMER is not set
++# CONFIG_CMD_SYSBOOT is not set
++# CONFIG_CMD_QFW is not set
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_PSTORE_MEM_SIZE=0x10000
++CONFIG_CMD_PSTORE_RECORD_SIZE=0x1000
++CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x1000
++CONFIG_CMD_PSTORE_FTRACE_SIZE=0x1000
++CONFIG_CMD_PSTORE_PMSG_SIZE=0x1000
++CONFIG_CMD_PSTORE_ECC_SIZE=0
++# CONFIG_CMD_TERMINAL is not set
++CONFIG_CMD_UUID=y
++
++#
++# TI specific command line interface
++#
++
++#
++# Power commands
++#
++
++#
++# Security commands
++#
++# CONFIG_CMD_AES is not set
++# CONFIG_CMD_BLOB is not set
++CONFIG_CMD_HASH=y
++# CONFIG_CMD_HVC is not set
++CONFIG_CMD_SMC=y
++# CONFIG_HASH_VERIFY is not set
++
++#
++# Firmware commands
++#
++
++#
++# Filesystem commands
++#
++# CONFIG_CMD_BTRFS is not set
++# CONFIG_CMD_EROFS is not set
++# CONFIG_CMD_EXT2 is not set
++# CONFIG_CMD_EXT4 is not set
++CONFIG_CMD_FAT=y
++# CONFIG_CMD_SQUASHFS is not set
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++# CONFIG_CMD_JFFS2 is not set
++# CONFIG_CMD_MTDPARTS is not set
++CONFIG_MTDIDS_DEFAULT=""
++CONFIG_MTDPARTS_DEFAULT=""
++# CONFIG_CMD_REISER is not set
++# CONFIG_CMD_ZFS is not set
++
++#
++# Debug commands
++#
++# CONFIG_CMD_DIAG is not set
++# CONFIG_CMD_EVENT is not set
++# CONFIG_CMD_LOG is not set
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITIONS=y
++# CONFIG_MAC_PARTITION is not set
++CONFIG_DOS_PARTITION=y
++# CONFIG_ISO_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++CONFIG_PARTITION_UUIDS=y
++CONFIG_SUPPORT_OF_CONTROL=y
++
++#
++# Device Tree Control
++#
++CONFIG_OF_CONTROL=y
++CONFIG_OF_REAL=y
++# CONFIG_OF_LIVE is not set
++CONFIG_OF_SEPARATE=y
++# CONFIG_OF_EMBED is not set
++# CONFIG_OF_BOARD is not set
++# CONFIG_OF_OMIT_DTB is not set
++CONFIG_DEVICE_TREE_INCLUDES=""
++CONFIG_OF_LIST="openwrt-one"
++# CONFIG_MULTI_DTB_FIT is not set
++CONFIG_OF_TAG_MIGRATE=y
++# CONFIG_OF_DTB_PROPS_REMOVE is not set
++
++#
++# Environment
++#
++CONFIG_ENV_SUPPORT=y
++CONFIG_SAVEENV=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_MIN_ENTRIES=64
++CONFIG_ENV_MAX_ENTRIES=512
++CONFIG_ENV_IS_DEFAULT=y
++CONFIG_ENV_IS_NOWHERE=y
++# CONFIG_ENV_IS_IN_EEPROM is not set
++# CONFIG_ENV_IS_IN_FAT is not set
++# CONFIG_ENV_IS_IN_EXT4 is not set
++# CONFIG_ENV_IS_IN_FLASH is not set
++# CONFIG_ENV_IS_IN_MTD is not set
++# CONFIG_ENV_IS_IN_NAND is not set
++# CONFIG_ENV_IS_IN_NVRAM is not set
++# CONFIG_ENV_IS_IN_ONENAND is not set
++# CONFIG_ENV_IS_IN_REMOTE is not set
++# CONFIG_ENV_IS_IN_SPI_FLASH is not set
++# CONFIG_ENV_IS_IN_UBI is not set
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_DEFAULT_ENV_FILE="openwrt-one-nor_env"
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++# CONFIG_ENV_IMPORT_FDT is not set
++# CONFIG_ENV_APPEND is not set
++# CONFIG_ENV_WRITEABLE_LIST is not set
++# CONFIG_ENV_ACCESS_IGNORE_FORCE is not set
++# CONFIG_USE_BOOTFILE is not set
++# CONFIG_USE_ETHPRIME is not set
++# CONFIG_USE_HOSTNAME is not set
++# CONFIG_VERSION_VARIABLE is not set
++CONFIG_NET=y
++CONFIG_ARP_TIMEOUT=5000
++CONFIG_NET_RETRY_COUNT=5
++CONFIG_PROT_UDP=y
++CONFIG_BOOTDEV_ETH=y
++# CONFIG_BOOTP_SEND_HOSTNAME is not set
++CONFIG_NET_RANDOM_ETHADDR=y
++# CONFIG_NETCONSOLE is not set
++# CONFIG_IP_DEFRAG is not set
++# CONFIG_SYS_FAULT_ECHO_LINK_DOWN is not set
++CONFIG_TFTP_BLOCKSIZE=1468
++# CONFIG_TFTP_PORT is not set
++CONFIG_TFTP_WINDOWSIZE=1
++# CONFIG_TFTP_TSIZE is not set
++# CONFIG_SERVERIP_FROM_PROXYDHCP is not set
++CONFIG_SERVERIP_FROM_PROXYDHCP_DELAY_MS=100
++# CONFIG_KEEP_SERVERADDR is not set
++# CONFIG_UDP_CHECKSUM is not set
++# CONFIG_BOOTP_SERVERIP is not set
++CONFIG_BOOTP_MAX_ROOT_PATH_LEN=64
++# CONFIG_USE_GATEWAYIP is not set
++# CONFIG_USE_IPADDR is not set
++# CONFIG_USE_NETMASK is not set
++# CONFIG_USE_ROOTPATH is not set
++# CONFIG_USE_SERVERIP is not set
++# CONFIG_PROT_TCP is not set
++# CONFIG_IPV6 is not set
++CONFIG_SYS_RX_ETH_BUFFER=4
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_DM=y
++# CONFIG_DM_WARN is not set
++# CONFIG_DM_DEBUG is not set
++# CONFIG_DM_STATS is not set
++CONFIG_DM_DEVICE_REMOVE=y
++CONFIG_DM_EVENT=y
++CONFIG_DM_STDIO=y
++CONFIG_DM_SEQ_ALIAS=y
++# CONFIG_DM_DMA is not set
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++# CONFIG_DEVRES is not set
++CONFIG_SIMPLE_BUS=y
++# CONFIG_SIMPLE_BUS_CORRECT_RANGE is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++CONFIG_OF_TRANSLATE=y
++# CONFIG_TRANSLATION_OFFSET is not set
++CONFIG_DM_DEV_READ_INLINE=y
++# CONFIG_OFNODE_MULTI_TREE is not set
++# CONFIG_BOUNCE_BUFFER is not set
++# CONFIG_ADC is not set
++# CONFIG_ADC_EXYNOS is not set
++# CONFIG_ADC_SANDBOX is not set
++# CONFIG_SARADC_MESON is not set
++# CONFIG_SARADC_ROCKCHIP is not set
++# CONFIG_SATA is not set
++# CONFIG_SCSI_AHCI is not set
++
++#
++# SATA/SCSI device support
++#
++# CONFIG_AXI is not set
++
++#
++# Bus devices
++#
++CONFIG_BLK=y
++CONFIG_BLOCK_CACHE=y
++# CONFIG_BLKMAP is not set
++# CONFIG_EFI_MEDIA is not set
++# CONFIG_IDE is not set
++# CONFIG_LBA48 is not set
++# CONFIG_SYS_64BIT_LBA is not set
++# CONFIG_RKMTD is not set
++# CONFIG_BOOTCOUNT_LIMIT is not set
++
++#
++# Button Support
++#
++CONFIG_BUTTON=y
++# CONFIG_BUTTON_ADC is not set
++CONFIG_BUTTON_GPIO=y
++
++#
++# Cache Controller drivers
++#
++# CONFIG_CACHE is not set
++# CONFIG_L2X0_CACHE is not set
++# CONFIG_V5L2_CACHE is not set
++# CONFIG_NCORE_CACHE is not set
++# CONFIG_SIFIVE_CCACHE is not set
++
++#
++# Clock
++#
++CONFIG_CLK=y
++# CONFIG_CLK_CCF is not set
++# CONFIG_CLK_GPIO is not set
++# CONFIG_CLK_CDCE9XX is not set
++# CONFIG_CLK_ICS8N3QV01 is not set
++# CONFIG_CLK_K210 is not set
++# CONFIG_CLK_MPC83XX is not set
++# CONFIG_CLK_XLNX_CLKWZRD is not set
++# CONFIG_CLK_AT91 is not set
++# CONFIG_CLK_RCAR is not set
++# CONFIG_CLK_RCAR_CPG_LIB is not set
++# CONFIG_CLK_SIFIVE is not set
++# CONFIG_CLK_TI_AM3_DPLL is not set
++# CONFIG_CLK_TI_CTRL is not set
++# CONFIG_CLK_TI_GATE is not set
++# CONFIG_CLK_K3 is not set
++CONFIG_CPU=y
++# CONFIG_CPU_IMX is not set
++
++#
++# Hardware crypto devices
++#
++# CONFIG_DM_HASH is not set
++# CONFIG_FSL_CAAM is not set
++CONFIG_CAAM_64BIT=y
++# CONFIG_SYS_FSL_SEC_BE is not set
++# CONFIG_SYS_FSL_SEC_LE is not set
++# CONFIG_NPCM_AES is not set
++# CONFIG_NPCM_SHA is not set
++# CONFIG_DDR_SPD is not set
++# CONFIG_IMX_SNPS_DDR_PHY is not set
++
++#
++# Demo for driver model
++#
++# CONFIG_DM_DEMO is not set
++
++#
++# DFU support
++#
++
++#
++# DMA Support
++#
++# CONFIG_DMA is not set
++# CONFIG_DMA_LPC32XX is not set
++# CONFIG_TI_EDMA3 is not set
++# CONFIG_DMA_LEGACY is not set
++
++#
++# Extcon Support
++#
++# CONFIG_EXTCON is not set
++
++#
++# Fastboot support
++#
++# CONFIG_UDP_FUNCTION_FASTBOOT is not set
++# CONFIG_TCP_FUNCTION_FASTBOOT is not set
++CONFIG_FIRMWARE=y
++CONFIG_ARM_PSCI_FW=y
++# CONFIG_ZYNQMP_FIRMWARE is not set
++# CONFIG_ARM_SMCCC_FEATURES is not set
++# CONFIG_ARM_FFA_TRANSPORT is not set
++# CONFIG_SCMI_FIRMWARE is not set
++# CONFIG_DM_FUZZING_ENGINE is not set
++
++#
++# FPGA support
++#
++# CONFIG_FPGA_ALTERA is not set
++# CONFIG_FPGA_SOCFPGA is not set
++# CONFIG_FPGA_LATTICE is not set
++# CONFIG_FPGA_XILINX is not set
++# CONFIG_DM_FPGA is not set
++# CONFIG_FWU_MDATA is not set
++CONFIG_GPIO=y
++CONFIG_GPIO_HOG=y
++# CONFIG_DM_GPIO_LOOKUP_LABEL is not set
++# CONFIG_ALTERA_PIO is not set
++# CONFIG_BCM2835_GPIO is not set
++# CONFIG_DWAPB_GPIO is not set
++# CONFIG_AT91_GPIO is not set
++# CONFIG_ATMEL_PIO4 is not set
++# CONFIG_ASPEED_GPIO is not set
++# CONFIG_DA8XX_GPIO is not set
++# CONFIG_HIKEY_GPIO is not set
++# CONFIG_INTEL_BROADWELL_GPIO is not set
++# CONFIG_INTEL_GPIO is not set
++# CONFIG_INTEL_ICH6_GPIO is not set
++# CONFIG_IMX_RGPIO2P is not set
++# CONFIG_IPROC_GPIO is not set
++# CONFIG_HSDK_CREG_GPIO is not set
++# CONFIG_KIRKWOOD_GPIO is not set
++# CONFIG_LPC32XX_GPIO is not set
++# CONFIG_MCP230XX_GPIO is not set
++# CONFIG_MSM_GPIO is not set
++# CONFIG_MXC_GPIO is not set
++# CONFIG_MXS_GPIO is not set
++# CONFIG_NPCM_GPIO is not set
++# CONFIG_CMD_PCA953X is not set
++# CONFIG_ROCKCHIP_GPIO is not set
++# CONFIG_XILINX_GPIO is not set
++# CONFIG_TCA642X is not set
++# CONFIG_TEGRA_GPIO is not set
++# CONFIG_TEGRA186_GPIO is not set
++# CONFIG_VYBRID_GPIO is not set
++# CONFIG_SIFIVE_GPIO is not set
++# CONFIG_ZYNQ_GPIO is not set
++# CONFIG_DM_74X164 is not set
++# CONFIG_PCA953X is not set
++# CONFIG_MPC8XXX_GPIO is not set
++# CONFIG_MPC8XX_GPIO is not set
++# CONFIG_NX_GPIO is not set
++# CONFIG_NOMADIK_GPIO is not set
++# CONFIG_ZYNQMP_GPIO_MODEPIN is not set
++# CONFIG_SLG7XL45106_I2C_GPO is not set
++# CONFIG_TURRIS_OMNIA_MCU is not set
++# CONFIG_FTGPIO010 is not set
++
++#
++# Hardware Spinlock Support
++#
++# CONFIG_DM_HWSPINLOCK is not set
++CONFIG_I2C=y
++# CONFIG_DM_I2C is not set
++# CONFIG_SYS_I2C_LEGACY is not set
++# CONFIG_SPL_SYS_I2C_LEGACY is not set
++# CONFIG_SYS_I2C_FSL is not set
++# CONFIG_SYS_I2C_DW is not set
++# CONFIG_SYS_I2C_IMX_LPI2C is not set
++# CONFIG_SYS_I2C_MTK is not set
++# CONFIG_SYS_I2C_MICROCHIP is not set
++# CONFIG_SYS_I2C_MXC is not set
++# CONFIG_SYS_I2C_NPCM is not set
++# CONFIG_SYS_I2C_SOFT is not set
++# CONFIG_SYS_I2C_MV is not set
++# CONFIG_SYS_I2C_MVTWSI is not set
++CONFIG_INPUT=y
++# CONFIG_DM_KEYBOARD is not set
++# CONFIG_CROS_EC_KEYB is not set
++# CONFIG_TEGRA_KEYBOARD is not set
++# CONFIG_TWL4030_INPUT is not set
++
++#
++# IOMMU device drivers
++#
++# CONFIG_IOMMU is not set
++
++#
++# LED Support
++#
++CONFIG_LED=y
++# CONFIG_LED_PWM is not set
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++# CONFIG_LED_STATUS is not set
++
++#
++# Mailbox Controller Support
++#
++# CONFIG_DM_MAILBOX is not set
++
++#
++# Memory Controller drivers
++#
++# CONFIG_MEMORY is not set
++# CONFIG_ATMEL_EBI is not set
++# CONFIG_MFD_ATMEL_SMC is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MISC is not set
++# CONFIG_NVMEM is not set
++# CONFIG_SPL_NVMEM is not set
++# CONFIG_SMSC_LPC47M is not set
++# CONFIG_SMSC_SIO1007 is not set
++# CONFIG_CROS_EC is not set
++# CONFIG_DS4510 is not set
++# CONFIG_FSL_SEC_MON is not set
++# CONFIG_IRQ is not set
++# CONFIG_NPCM_HOST is not set
++# CONFIG_NUVOTON_NCT6102D is not set
++# CONFIG_PWRSEQ is not set
++# CONFIG_PCA9551_LED is not set
++# CONFIG_TEST_DRV is not set
++# CONFIG_USB_HUB_USB251XB is not set
++# CONFIG_TWL4030_LED is not set
++# CONFIG_WINBOND_W83627 is not set
++# CONFIG_FS_LOADER is not set
++
++#
++# MMC Host controller Support
++#
++# CONFIG_MMC is not set
++# CONFIG_MMC_BROKEN_CD is not set
++# CONFIG_DM_MMC is not set
++# CONFIG_FSL_ESDHC is not set
++# CONFIG_FSL_ESDHC_IMX is not set
++
++#
++# MTD Support
++#
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD=y
++CONFIG_DM_MTD=y
++# CONFIG_MTD_NOR_FLASH is not set
++# CONFIG_MTD_CONCAT is not set
++# CONFIG_SYS_MTDPARTS_RUNTIME is not set
++# CONFIG_FLASH_CFI_DRIVER is not set
++# CONFIG_CFI_FLASH is not set
++# CONFIG_ALTERA_QSPI is not set
++# CONFIG_HBMC_AM654 is not set
++# CONFIG_SAMSUNG_ONENAND is not set
++# CONFIG_USE_SYS_MAX_FLASH_BANKS is not set
++CONFIG_MTD_NAND_CORE=y
++# CONFIG_MTD_RAW_NAND is not set
++CONFIG_MTD_SPI_NAND=y
++
++#
++# SPI Flash Support
++#
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH=y
++CONFIG_SF_DEFAULT_BUS=0
++CONFIG_SF_DEFAULT_CS=0
++# CONFIG_BOOTDEV_SPI_FLASH is not set
++CONFIG_SPI_FLASH_SFDP_SUPPORT=y
++CONFIG_SPI_FLASH_SMART_HWCAPS=y
++# CONFIG_SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT is not set
++# CONFIG_SPI_FLASH_SOFT_RESET is not set
++# CONFIG_SPI_FLASH_BAR is not set
++CONFIG_SPI_FLASH_LOCK=y
++CONFIG_SPI_FLASH_UNLOCK_ALL=y
++# CONFIG_SPI_FLASH_ATMEL is not set
++CONFIG_SPI_FLASH_EON=y
++CONFIG_SPI_FLASH_GIGADEVICE=y
++CONFIG_SPI_FLASH_ISSI=y
++CONFIG_SPI_FLASH_MACRONIX=y
++CONFIG_SPI_FLASH_SPANSION=y
++# CONFIG_SPI_FLASH_S28HX_T is not set
++CONFIG_SPI_FLASH_STMICRO=y
++# CONFIG_SPI_FLASH_MT35XU is not set
++# CONFIG_SPI_FLASH_SST is not set
++CONFIG_SPI_FLASH_WINBOND=y
++CONFIG_SPI_FLASH_XMC=y
++CONFIG_SPI_FLASH_XTX=y
++# CONFIG_SPI_FLASH_ZBIT is not set
++CONFIG_SPI_FLASH_USE_4K_SECTORS=y
++# CONFIG_SPI_FLASH_DATAFLASH is not set
++CONFIG_SPI_FLASH_MTD=y
++
++#
++# UBI support
++#
++CONFIG_UBI_SILENCE_MSG=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_MODULE=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++# CONFIG_NVMXIP is not set
++# CONFIG_NVMXIP_QSPI is not set
++# CONFIG_NMBM is not set
++
++#
++# Multiplexer drivers
++#
++# CONFIG_MULTIPLEXER is not set
++# CONFIG_BITBANGMII is not set
++# CONFIG_MV88E6352_SWITCH is not set
++CONFIG_PHYLIB=y
++# CONFIG_PHY_ADDR_ENABLE is not set
++# CONFIG_B53_SWITCH is not set
++# CONFIG_MV88E61XX_SWITCH is not set
++# CONFIG_PHYLIB_10G is not set
++# CONFIG_PHY_ADIN is not set
++# CONFIG_PHY_AIROHA is not set
++# CONFIG_PHY_AQUANTIA is not set
++# CONFIG_PHY_ATHEROS is not set
++# CONFIG_SPL_PHY_ATHEROS is not set
++# CONFIG_PHY_BROADCOM is not set
++# CONFIG_PHY_CORTINA is not set
++# CONFIG_PHY_DAVICOM is not set
++# CONFIG_PHY_ET1011C is not set
++# CONFIG_PHY_LXT is not set
++# CONFIG_PHY_MARVELL is not set
++# CONFIG_PHY_MARVELL_10G is not set
++# CONFIG_PHY_MESON_GXL is not set
++# CONFIG_PHY_MICREL is not set
++# CONFIG_PHY_MOTORCOMM is not set
++# CONFIG_PHY_MSCC is not set
++# CONFIG_PHY_NATSEMI is not set
++# CONFIG_PHY_NXP_C45_TJA11XX is not set
++# CONFIG_PHY_NXP_TJA11XX is not set
++# CONFIG_PHY_REALTEK is not set
++# CONFIG_PHY_SMSC is not set
++# CONFIG_PHY_TERANETICS is not set
++# CONFIG_PHY_TI is not set
++# CONFIG_PHY_TI_DP83867 is not set
++# CONFIG_PHY_TI_DP83869 is not set
++# CONFIG_PHY_TI_GENERIC is not set
++# CONFIG_PHY_VITESSE is not set
++# CONFIG_PHY_XILINX is not set
++# CONFIG_PHY_XILINX_GMII2RGMII is not set
++# CONFIG_PHY_XWAY is not set
++# CONFIG_PHY_ETHERNET_ID is not set
++CONFIG_PHY_FIXED=y
++# CONFIG_PHY_NCSI is not set
++# CONFIG_FSL_MEMAC is not set
++CONFIG_PHY_RESET_DELAY=0
++# CONFIG_FSL_PFE is not set
++CONFIG_ETH=y
++CONFIG_DM_ETH=y
++# CONFIG_DM_MDIO is not set
++# CONFIG_DM_ETH_PHY is not set
++CONFIG_NETDEVICES=y
++# CONFIG_PHY_GIGE is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_BCM_SF2_ETH is not set
++# CONFIG_BCMGENET is not set
++# CONFIG_BNXT_ETH is not set
++# CONFIG_CALXEDA_XGMAC is not set
++# CONFIG_DRIVER_DM9000 is not set
++# CONFIG_DWC_ETH_QOS is not set
++# CONFIG_EEPRO100 is not set
++# CONFIG_ETH_DESIGNWARE is not set
++# CONFIG_ETH_DESIGNWARE_MESON8B is not set
++# CONFIG_ETHOC is not set
++# CONFIG_FMAN_ENET is not set
++# CONFIG_FTMAC100 is not set
++# CONFIG_FTGMAC100 is not set
++# CONFIG_MCFFEC is not set
++# CONFIG_FSLDMAFEC is not set
++# CONFIG_KS8851_MLL is not set
++# CONFIG_LITEETH is not set
++# CONFIG_MACB is not set
++# CONFIG_NET_NPCM750 is not set
++# CONFIG_PCH_GBE is not set
++# CONFIG_RGMII is not set
++# CONFIG_MII is not set
++# CONFIG_RMII is not set
++# CONFIG_PCNET is not set
++# CONFIG_QE_UEC is not set
++# CONFIG_RTL8139 is not set
++# CONFIG_SMC911X is not set
++# CONFIG_SUN7I_GMAC is not set
++# CONFIG_SUN4I_EMAC is not set
++# CONFIG_SUN8I_EMAC is not set
++# CONFIG_SH_ETHER is not set
++# CONFIG_DRIVER_TI_CPSW is not set
++# CONFIG_DRIVER_TI_EMAC is not set
++# CONFIG_DRIVER_TI_KEYSTONE_NET is not set
++# CONFIG_TULIP is not set
++# CONFIG_XILINX_AXIEMAC is not set
++# CONFIG_VSC7385_ENET is not set
++# CONFIG_XILINX_EMACLITE is not set
++# CONFIG_ZYNQ_GEM is not set
++# CONFIG_SYS_DPAA_QBMAN is not set
++# CONFIG_TSEC_ENET is not set
++CONFIG_MEDIATEK_ETH=y
++# CONFIG_HIFEMAC_ETH is not set
++# CONFIG_HIGMACV300_ETH is not set
++# CONFIG_NVME is not set
++# CONFIG_NVME_APPLE is not set
++
++#
++# PCI Endpoint
++#
++# CONFIG_PCI_ENDPOINT is not set
++# CONFIG_X86_PCH7 is not set
++# CONFIG_X86_PCH9 is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_PHY=y
++# CONFIG_NOP_PHY is not set
++# CONFIG_MIPI_DPHY_HELPERS is not set
++# CONFIG_BCM_SR_PCIE_PHY is not set
++# CONFIG_OMAP_USB2_PHY is not set
++CONFIG_PHY_MTK_TPHY=y
++
++#
++# Rockchip PHY driver
++#
++# CONFIG_PHY_CADENCE_SIERRA is not set
++# CONFIG_PHY_CADENCE_TORRENT is not set
++# CONFIG_MSM8916_USB_PHY is not set
++# CONFIG_MVEBU_COMPHY_SUPPORT is not set
++
++#
++# Pin controllers
++#
++CONFIG_PINCTRL=y
++CONFIG_PINCTRL_FULL=y
++CONFIG_PINCTRL_GENERIC=y
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_PINCONF_RECURSIVE=y
++# CONFIG_PINCTRL_AT91 is not set
++# CONFIG_PINCTRL_AT91PIO4 is not set
++# CONFIG_PINCTRL_INTEL is not set
++# CONFIG_PINCTRL_QE is not set
++# CONFIG_PINCTRL_ROCKCHIP_RV1108 is not set
++# CONFIG_PINCTRL_SINGLE is not set
++# CONFIG_PINCTRL_STM32 is not set
++# CONFIG_PINCTRL_STMFX is not set
++# CONFIG_PINCTRL_K210 is not set
++CONFIG_PINCTRL_MTK=y
++# CONFIG_PINCTRL_MT7622 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT7629 is not set
++CONFIG_PINCTRL_MT7981=y
++# CONFIG_PINCTRL_MT7986 is not set
++# CONFIG_PINCTRL_MT7988 is not set
++# CONFIG_PINCTRL_MT8512 is not set
++# CONFIG_PINCTRL_MT8516 is not set
++# CONFIG_PINCTRL_MT8518 is not set
++CONFIG_POWER=y
++# CONFIG_POWER_LEGACY is not set
++# CONFIG_ACPI_PMC is not set
++
++#
++# Power Domain Support
++#
++CONFIG_POWER_DOMAIN=y
++# CONFIG_APPLE_PMGR_POWER_DOMAIN is not set
++CONFIG_MTK_POWER_DOMAIN=y
++# CONFIG_DM_PMIC is not set
++# CONFIG_PMIC_TPS65217 is not set
++# CONFIG_POWER_TPS65218 is not set
++# CONFIG_POWER_TPS62362 is not set
++# CONFIG_DM_REGULATOR is not set
++# CONFIG_TPS6586X_POWER is not set
++# CONFIG_POWER_MT6323 is not set
++CONFIG_DM_PWM=y
++# CONFIG_PWM_ASPEED is not set
++# CONFIG_PWM_CADENCE_TTC is not set
++# CONFIG_PWM_CROS_EC is not set
++# CONFIG_PWM_EXYNOS is not set
++# CONFIG_PWM_IMX is not set
++# CONFIG_PWM_MESON is not set
++CONFIG_PWM_MTK=y
++# CONFIG_PWM_ROCKCHIP is not set
++# CONFIG_PWM_SANDBOX is not set
++# CONFIG_PWM_SIFIVE is not set
++# CONFIG_PWM_TEGRA is not set
++# CONFIG_PWM_SUNXI is not set
++# CONFIG_U_QE is not set
++# CONFIG_RAM is not set
++
++#
++# Reboot Mode Support
++#
++# CONFIG_DM_REBOOT_MODE is not set
++
++#
++# Remote Processor drivers
++#
++
++#
++# Reset Controller Support
++#
++# CONFIG_RESET_AST2500 is not set
++# CONFIG_RESET_AST2600 is not set
++CONFIG_RESET_MEDIATEK=y
++# CONFIG_RESET_HISILICON is not set
++# CONFIG_RESET_SYSCON is not set
++# CONFIG_RESET_SCMI is not set
++# CONFIG_RESET_DRA7 is not set
++# CONFIG_DM_RNG is not set
++
++#
++# Real Time Clock
++#
++# CONFIG_DM_RTC is not set
++# CONFIG_RTC_ENABLE_32KHZ_OUTPUT is not set
++# CONFIG_RTC_DS1337 is not set
++# CONFIG_RTC_DS1338 is not set
++# CONFIG_RTC_DS1374 is not set
++# CONFIG_RTC_DS3231 is not set
++# CONFIG_RTC_PCF8563 is not set
++# CONFIG_RTC_PT7C4338 is not set
++# CONFIG_RTC_PL031 is not set
++# CONFIG_RTC_S35392A is not set
++# CONFIG_RTC_MC13XXX is not set
++# CONFIG_RTC_MC146818 is not set
++# CONFIG_RTC_M41T62 is not set
++# CONFIG_SCSI is not set
++# CONFIG_DM_SCSI is not set
++CONFIG_SERIAL=y
++CONFIG_BAUDRATE=115200
++# CONFIG_DEFAULT_ENV_IS_RW is not set
++CONFIG_REQUIRE_SERIAL_CONSOLE=y
++# CONFIG_SPECIFY_CONSOLE_INDEX is not set
++CONFIG_SERIAL_PRESENT=y
++CONFIG_DM_SERIAL=y
++# CONFIG_SERIAL_RX_BUFFER is not set
++# CONFIG_SERIAL_PUTS is not set
++# CONFIG_SERIAL_SEARCH_ALL is not set
++# CONFIG_SERIAL_PROBE_ALL is not set
++# CONFIG_VPL_DM_SERIAL is not set
++CONFIG_DEBUG_UART_MTK=y
++CONFIG_DEBUG_UART_SHIFT=0
++# CONFIG_DEBUG_UART_ANNOUNCE is not set
++# CONFIG_DEBUG_UART_SKIP_INIT is not set
++# CONFIG_ALTERA_JTAG_UART is not set
++# CONFIG_ALTERA_UART is not set
++# CONFIG_ARC_SERIAL is not set
++# CONFIG_ARM_DCC is not set
++# CONFIG_ATMEL_USART is not set
++# CONFIG_BCM6345_SERIAL is not set
++# CONFIG_COREBOOT_SERIAL is not set
++# CONFIG_CORTINA_UART is not set
++# CONFIG_FSL_LINFLEXUART is not set
++# CONFIG_FSL_LPUART is not set
++# CONFIG_MVEBU_A3700_UART is not set
++# CONFIG_MCFUART is not set
++# CONFIG_NULLDEV_SERIAL is not set
++# CONFIG_SYS_NS16550 is not set
++# CONFIG_PL01X_SERIAL is not set
++# CONFIG_ROCKCHIP_SERIAL is not set
++# CONFIG_XILINX_UARTLITE is not set
++# CONFIG_MSM_SERIAL is not set
++# CONFIG_MSM_GENI_SERIAL is not set
++# CONFIG_MXS_AUART_SERIAL is not set
++# CONFIG_OMAP_SERIAL is not set
++# CONFIG_SIFIVE_SERIAL is not set
++# CONFIG_ZYNQ_SERIAL is not set
++CONFIG_MTK_SERIAL=y
++# CONFIG_MT7620_SERIAL is not set
++# CONFIG_NPCM_SERIAL is not set
++# CONFIG_SM is not set
++# CONFIG_MESON_SM is not set
++# CONFIG_SMEM is not set
++
++#
++# Sound support
++#
++# CONFIG_SOUND is not set
++
++#
++# SOC (System On Chip) specific Drivers
++#
++# CONFIG_SOC_DEVICE is not set
++# CONFIG_SOC_TI is not set
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_SPI_MEM=y
++# CONFIG_SPI_DIRMAP is not set
++# CONFIG_ALTERA_SPI is not set
++# CONFIG_APPLE_SPI is not set
++# CONFIG_ATCSPI200_SPI is not set
++# CONFIG_ATMEL_SPI is not set
++# CONFIG_BCMSTB_SPI is not set
++# CONFIG_CORTINA_SFLASH is not set
++# CONFIG_CADENCE_QSPI is not set
++# CONFIG_CF_SPI is not set
++# CONFIG_DESIGNWARE_SPI is not set
++# CONFIG_EXYNOS_SPI is not set
++# CONFIG_FSL_DSPI is not set
++# CONFIG_FSL_QSPI is not set
++# CONFIG_GXP_SPI is not set
++# CONFIG_ICH_SPI is not set
++# CONFIG_IPROC_QSPI is not set
++# CONFIG_KIRKWOOD_SPI is not set
++# CONFIG_MICROCHIP_COREQSPI is not set
++# CONFIG_MPC8XXX_SPI is not set
++# CONFIG_MTK_SNOR is not set
++# CONFIG_MTK_SNFI_SPI is not set
++CONFIG_MTK_SPIM=y
++# CONFIG_MVEBU_A3700_SPI is not set
++# CONFIG_MXS_SPI is not set
++# CONFIG_SPI_MXIC is not set
++# CONFIG_NPCM_FIU_SPI is not set
++# CONFIG_NPCM_PSPI is not set
++# CONFIG_NXP_FSPI is not set
++# CONFIG_OMAP3_SPI is not set
++# CONFIG_PL022_SPI is not set
++# CONFIG_ROCKCHIP_SFC is not set
++# CONFIG_ROCKCHIP_SPI is not set
++# CONFIG_SPI_ASPEED_SMC is not set
++# CONFIG_SPI_SIFIVE is not set
++# CONFIG_SOFT_SPI is not set
++# CONFIG_SPI_SN_F_OSPI is not set
++# CONFIG_SPI_SUNXI is not set
++# CONFIG_TEGRA114_SPI is not set
++# CONFIG_TEGRA20_SFLASH is not set
++# CONFIG_TEGRA20_SLINK is not set
++# CONFIG_TEGRA210_QSPI is not set
++# CONFIG_TI_QSPI is not set
++# CONFIG_XILINX_SPI is not set
++# CONFIG_ZYNQ_SPI is not set
++# CONFIG_ZYNQ_QSPI is not set
++# CONFIG_ZYNQMP_GQSPI is not set
++# CONFIG_SH_QSPI is not set
++# CONFIG_MXC_SPI is not set
++
++#
++# SPMI support
++#
++# CONFIG_SPMI is not set
++# CONFIG_SYSINFO is not set
++
++#
++# System reset device drivers
++#
++# CONFIG_SYSRESET is not set
++# CONFIG_TEE is not set
++# CONFIG_DM_THERMAL is not set
++
++#
++# Timer Support
++#
++# CONFIG_TIMER is not set
++
++#
++# TPM support
++#
++CONFIG_USB=y
++CONFIG_DM_USB=y
++# CONFIG_DM_USB_GADGET is not set
++
++#
++# USB Host Controller Drivers
++#
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++# CONFIG_USB_XHCI_DWC3 is not set
++# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set
++CONFIG_USB_XHCI_MTK=y
++# CONFIG_USB_XHCI_FSL is not set
++# CONFIG_USB_XHCI_BRCM is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_ISP1760 is not set
++# CONFIG_USB_CDNS3 is not set
++# CONFIG_USB_DWC3 is not set
++# CONFIG_USB_MTU3 is not set
++
++#
++# Legacy MUSB Support
++#
++# CONFIG_USB_MUSB_HCD is not set
++# CONFIG_USB_MUSB_UDC is not set
++
++#
++# MUSB Controller Driver
++#
++# CONFIG_USB_MUSB_HOST is not set
++# CONFIG_USB_MUSB_PIO_ONLY is not set
++
++#
++# USB Phy
++#
++# CONFIG_TWL4030_USB is not set
++# CONFIG_ROCKCHIP_USB2_PHY is not set
++
++#
++# ULPI drivers
++#
++
++#
++# USB peripherals
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_KEYBOARD is not set
++# CONFIG_USB_ONBOARD_HUB is not set
++CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=1000
++# CONFIG_USB_HOST_ETHER is not set
++# CONFIG_USB_GADGET is not set
++# CONFIG_SPL_USB_GADGET is not set
++
++#
++# UFS Host Controller Support
++#
++# CONFIG_TI_J721E_UFS is not set
++
++#
++# Graphics support
++#
++# CONFIG_VIDEO is not set
++
++#
++# VirtIO Drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# 1-Wire support
++#
++# CONFIG_W1 is not set
++
++#
++# 1-wire EEPROM support
++#
++# CONFIG_W1_EEPROM is not set
++
++#
++# Watchdog Timer Support
++#
++# CONFIG_WATCHDOG is not set
++CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
++# CONFIG_IMX_WATCHDOG is not set
++# CONFIG_ULP_WATCHDOG is not set
++# CONFIG_WDT is not set
++# CONFIG_PHYS_TO_BUS is not set
++
++#
++# File systems
++#
++# CONFIG_FS_BTRFS is not set
++# CONFIG_FS_CBFS is not set
++# CONFIG_FS_EXT4 is not set
++CONFIG_FS_FAT=y
++CONFIG_FAT_WRITE=y
++CONFIG_FS_FAT_MAX_CLUSTSIZE=65536
++# CONFIG_FS_JFFS2 is not set
++CONFIG_UBIFS_SILENCE_MSG=y
++CONFIG_UBIFS_SILENCE_DEBUG_DUMP=y
++# CONFIG_FS_CRAMFS is not set
++# CONFIG_YAFFS2 is not set
++# CONFIG_FS_SQUASHFS is not set
++# CONFIG_FS_EROFS is not set
++
++#
++# Library routines
++#
++# CONFIG_ADDR_MAP is not set
++# CONFIG_SYS_TIMER_COUNTS_DOWN is not set
++# CONFIG_PHYSMEM is not set
++# CONFIG_BCH is not set
++# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
++CONFIG_CHARSET=y
++# CONFIG_DYNAMIC_CRC_TABLE is not set
++CONFIG_LIB_UUID=y
++# CONFIG_SEMIHOSTING is not set
++CONFIG_PRINTF=y
++CONFIG_SPRINTF=y
++CONFIG_STRTO=y
++CONFIG_SYS_HZ=1000
++# CONFIG_PANIC_HANG is not set
++CONFIG_REGEX=y
++CONFIG_LIB_RAND=y
++# CONFIG_LIB_HW_RAND is not set
++CONFIG_SUPPORT_ACPI=y
++# CONFIG_ACPI is not set
++CONFIG_RBTREE=y
++# CONFIG_BITREVERSE is not set
++# CONFIG_TRACE is not set
++# CONFIG_CIRCBUF is not set
++# CONFIG_CMD_DHRYSTONE is not set
++
++#
++# Security support
++#
++# CONFIG_AES is not set
++# CONFIG_ECDSA is not set
++# CONFIG_RSA is not set
++# CONFIG_TPM is not set
++
++#
++# Android Verified Boot
++#
++
++#
++# Hashing Support
++#
++# CONFIG_BLAKE2 is not set
++CONFIG_SHA1=y
++CONFIG_SHA256=y
++# CONFIG_SHA512 is not set
++# CONFIG_SHA384 is not set
++# CONFIG_SHA_HW_ACCEL is not set
++CONFIG_MD5=y
++CONFIG_CRC8=y
++CONFIG_CRC32=y
++
++#
++# Compression Support
++#
++# CONFIG_LZ4 is not set
++CONFIG_LZMA=y
++CONFIG_LZO=y
++CONFIG_GZIP=y
++# CONFIG_ZLIB_UNCOMPRESS is not set
++# CONFIG_BZIP2 is not set
++CONFIG_ZLIB=y
++# CONFIG_ZSTD is not set
++CONFIG_VPL_LZMA=y
++# CONFIG_SPL_GZIP is not set
++# CONFIG_ERRNO_STR is not set
++CONFIG_HEXDUMP=y
++# CONFIG_GETOPT is not set
++CONFIG_OF_LIBFDT=y
++CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
++CONFIG_SYS_FDT_PAD=0x3000
++
++#
++# System tables
++#
++CONFIG_GENERATE_SMBIOS_TABLE=y
++# CONFIG_LIB_RATIONAL is not set
++CONFIG_SMBIOS=y
++# CONFIG_SMBIOS_PARSER is not set
++CONFIG_EFI_LOADER=y
++CONFIG_CMD_BOOTEFI_BOOTMGR=y
++CONFIG_EFI_VARIABLE_FILE_STORE=y
++# CONFIG_EFI_VARIABLE_NO_STORE is not set
++# CONFIG_EFI_VARIABLES_PRESEED is not set
++CONFIG_EFI_VAR_BUF_SIZE=131072
++# CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN is not set
++# CONFIG_EFI_RUNTIME_UPDATE_CAPSULE is not set
++CONFIG_EFI_CAPSULE_MAX=15
++CONFIG_EFI_DEVICE_PATH_TO_TEXT=y
++CONFIG_EFI_DEVICE_PATH_UTIL=y
++CONFIG_EFI_DT_FIXUP=y
++CONFIG_EFI_LOADER_HII=y
++CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y
++CONFIG_EFI_UNICODE_CAPITALIZATION=y
++# CONFIG_EFI_LOADER_BOUNCE_BUFFER is not set
++CONFIG_EFI_PLATFORM_LANG_CODES="en-US"
++CONFIG_EFI_HAVE_RUNTIME_RESET=y
++CONFIG_EFI_LOAD_FILE2_INITRD=y
++CONFIG_EFI_ECPT=y
++CONFIG_EFI_EBBR_2_1_CONFORMANCE=y
++# CONFIG_OPTEE_LIB is not set
++# CONFIG_OPTEE_IMAGE is not set
++# CONFIG_BOOTM_OPTEE is not set
++# CONFIG_TEST_FDTDEC is not set
++CONFIG_LIB_ELF=y
++CONFIG_LMB=y
++CONFIG_LMB_USE_MAX_REGIONS=y
++CONFIG_LMB_MAX_REGIONS=64
++# CONFIG_PHANDLE_CHECK_SEQ is not set
++
++#
++# Testing
++#
++# CONFIG_UNIT_TEST is not set
++# CONFIG_POST is not set
++
++#
++# Tools options
++#
++CONFIG_MKIMAGE_DTC_PATH="dtc"
++CONFIG_TOOLS_CRC32=y
++# CONFIG_TOOLS_LIBCRYPTO is not set
++CONFIG_TOOLS_FIT=y
++CONFIG_TOOLS_FIT_FULL_CHECK=y
++CONFIG_TOOLS_FIT_PRINT=y
++CONFIG_TOOLS_FIT_RSASSA_PSS=y
++CONFIG_TOOLS_FIT_SIGNATURE=y
++CONFIG_TOOLS_FIT_SIGNATURE_MAX_SIZE=0x10000000
++CONFIG_TOOLS_FIT_VERBOSE=y
++CONFIG_TOOLS_MD5=y
++CONFIG_TOOLS_OF_LIBFDT=y
++CONFIG_TOOLS_SHA1=y
++CONFIG_TOOLS_SHA256=y
++CONFIG_TOOLS_SHA384=y
++CONFIG_TOOLS_SHA512=y
++# CONFIG_TOOLS_MKEFICAPSULE is not set
++# CONFIG_FSPI_CONF_HEADER is not set
++# CONFIG_TOOLS_MKFWUMDATA is not set
+--- /dev/null
++++ b/configs/mt7981_openwrt-one-spi-nand_defconfig
+@@ -0,0 +1,1815 @@
++#
++# Automatically generated file; DO NOT EDIT.
++# U-Boot 2024.01 Configuration
++#
++
++#
++# Compiler: aarch64-openwrt-linux-musl-gcc (OpenWrt GCC 12.3.0 r25206+8-d5e2177a6b) 12.3.0
++#
++CONFIG_CREATE_ARCH_SYMLINK=y
++CONFIG_SYS_CACHE_SHIFT_6=y
++CONFIG_SYS_CACHELINE_SIZE=64
++CONFIG_LINKER_LIST_ALIGN=8
++# CONFIG_ARC is not set
++CONFIG_ARM=y
++# CONFIG_M68K is not set
++# CONFIG_MICROBLAZE is not set
++# CONFIG_MIPS is not set
++# CONFIG_NIOS2 is not set
++# CONFIG_PPC is not set
++# CONFIG_RISCV is not set
++# CONFIG_SANDBOX is not set
++# CONFIG_SH is not set
++# CONFIG_X86 is not set
++# CONFIG_XTENSA is not set
++CONFIG_SYS_ARCH="arm"
++CONFIG_SYS_CPU="armv8"
++CONFIG_SYS_SOC="mediatek"
++CONFIG_SYS_VENDOR="mediatek"
++CONFIG_SYS_BOARD="mt7981"
++CONFIG_SYS_CONFIG_NAME="mt7981"
++
++#
++# Skipping low level initialization functions
++#
++# CONFIG_SKIP_LOWLEVEL_INIT is not set
++# CONFIG_SKIP_LOWLEVEL_INIT_ONLY is not set
++CONFIG_SYS_HAS_NONCACHED_MEMORY=y
++CONFIG_SYS_NONCACHED_MEMORY=0x100000
++# CONFIG_SYS_ICACHE_OFF is not set
++# CONFIG_SYS_DCACHE_OFF is not set
++
++#
++# ARM architecture
++#
++CONFIG_ARM64=y
++CONFIG_ARM64_CRC32=y
++CONFIG_COUNTER_FREQUENCY=0
++CONFIG_POSITION_INDEPENDENT=y
++CONFIG_INIT_SP_RELATIVE=y
++CONFIG_SYS_INIT_SP_BSS_OFFSET=524288
++# CONFIG_GIC_V3_ITS is not set
++CONFIG_STATIC_RELA=y
++CONFIG_DMA_ADDR_T_64BIT=y
++CONFIG_GPIO_EXTRA_HEADER=y
++CONFIG_ARM_ASM_UNIFIED=y
++# CONFIG_SYS_ARM_CACHE_CP15 is not set
++# CONFIG_SYS_ARM_MMU is not set
++# CONFIG_SYS_ARM_MPU is not set
++CONFIG_SYS_ARM_ARCH=8
++CONFIG_SYS_ARM_CACHE_WRITEBACK=y
++# CONFIG_SYS_ARM_CACHE_WRITETHROUGH is not set
++# CONFIG_SYS_ARM_CACHE_WRITEALLOC is not set
++# CONFIG_ARCH_CPU_INIT is not set
++CONFIG_SYS_ARCH_TIMER=y
++CONFIG_ARM_SMCCC=y
++# CONFIG_SYS_L2_PL310 is not set
++# CONFIG_SPL_SYS_L2_PL310 is not set
++# CONFIG_SYS_L2CACHE_OFF is not set
++# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
++# CONFIG_USE_ARCH_MEMCPY is not set
++# CONFIG_USE_ARCH_MEMSET is not set
++CONFIG_ARM64_SUPPORT_AARCH32=y
++# CONFIG_ARCH_AT91 is not set
++# CONFIG_ARCH_DAVINCI is not set
++# CONFIG_ARCH_HISTB is not set
++# CONFIG_ARCH_KIRKWOOD is not set
++# CONFIG_ARCH_MVEBU is not set
++# CONFIG_ARCH_ORION5X is not set
++# CONFIG_TARGET_STV0991 is not set
++# CONFIG_ARCH_BCM283X is not set
++# CONFIG_ARCH_BCMSTB is not set
++# CONFIG_ARCH_BCMBCA is not set
++# CONFIG_TARGET_VEXPRESS_CA9X4 is not set
++# CONFIG_TARGET_BCMNS is not set
++# CONFIG_TARGET_BCMNS2 is not set
++# CONFIG_TARGET_BCMNS3 is not set
++# CONFIG_ARCH_EXYNOS is not set
++# CONFIG_ARCH_S5PC1XX is not set
++# CONFIG_ARCH_HIGHBANK is not set
++# CONFIG_ARCH_INTEGRATOR is not set
++# CONFIG_ARCH_IPQ40XX is not set
++# CONFIG_ARCH_KEYSTONE is not set
++# CONFIG_ARCH_K3 is not set
++# CONFIG_ARCH_OMAP2PLUS is not set
++# CONFIG_ARCH_MESON is not set
++CONFIG_ARCH_MEDIATEK=y
++# CONFIG_ARCH_LPC32XX is not set
++# CONFIG_ARCH_IMX8 is not set
++# CONFIG_ARCH_IMX8M is not set
++# CONFIG_ARCH_IMX8ULP is not set
++# CONFIG_ARCH_IMX9 is not set
++# CONFIG_ARCH_IMXRT is not set
++# CONFIG_ARCH_MX23 is not set
++# CONFIG_ARCH_MX28 is not set
++# CONFIG_ARCH_MX31 is not set
++# CONFIG_ARCH_MX7ULP is not set
++# CONFIG_ARCH_MX7 is not set
++# CONFIG_ARCH_MX6 is not set
++# CONFIG_ARCH_MX5 is not set
++# CONFIG_ARCH_NEXELL is not set
++# CONFIG_ARCH_NPCM is not set
++# CONFIG_ARCH_APPLE is not set
++# CONFIG_ARCH_OWL is not set
++# CONFIG_ARCH_QEMU is not set
++# CONFIG_ARCH_RMOBILE is not set
++# CONFIG_ARCH_SNAPDRAGON is not set
++# CONFIG_ARCH_SOCFPGA is not set
++# CONFIG_ARCH_SUNXI is not set
++# CONFIG_ARCH_U8500 is not set
++# CONFIG_ARCH_VERSAL is not set
++# CONFIG_ARCH_VERSAL_NET is not set
++# CONFIG_ARCH_VF610 is not set
++# CONFIG_ARCH_ZYNQ is not set
++# CONFIG_ARCH_ZYNQMP_R5 is not set
++# CONFIG_ARCH_ZYNQMP is not set
++# CONFIG_ARCH_TEGRA is not set
++# CONFIG_ARCH_VEXPRESS64 is not set
++# CONFIG_TARGET_CORSTONE1000 is not set
++# CONFIG_TARGET_TOTAL_COMPUTE is not set
++# CONFIG_TARGET_LS2080A_EMU is not set
++# CONFIG_TARGET_LS1088AQDS is not set
++# CONFIG_TARGET_LS2080AQDS is not set
++# CONFIG_TARGET_LS2080ARDB is not set
++# CONFIG_TARGET_LS2081ARDB is not set
++# CONFIG_TARGET_LX2160ARDB is not set
++# CONFIG_TARGET_LX2160AQDS is not set
++# CONFIG_TARGET_LX2162AQDS is not set
++# CONFIG_TARGET_HIKEY is not set
++# CONFIG_TARGET_HIKEY960 is not set
++# CONFIG_TARGET_POPLAR is not set
++# CONFIG_TARGET_LS1012AQDS is not set
++# CONFIG_TARGET_LS1012ARDB is not set
++# CONFIG_TARGET_LS1012A2G5RDB is not set
++# CONFIG_TARGET_LS1012AFRWY is not set
++# CONFIG_TARGET_LS1012AFRDM is not set
++# CONFIG_TARGET_LS1028AQDS is not set
++# CONFIG_TARGET_LS1028ARDB is not set
++# CONFIG_TARGET_LS1088ARDB is not set
++# CONFIG_TARGET_LS1021AQDS is not set
++# CONFIG_TARGET_LS1021ATWR is not set
++# CONFIG_TARGET_PG_WCOM_SELI8 is not set
++# CONFIG_TARGET_PG_WCOM_EXPU1 is not set
++# CONFIG_TARGET_LS1021ATSN is not set
++# CONFIG_TARGET_LS1021AIOT is not set
++# CONFIG_TARGET_LS1043AQDS is not set
++# CONFIG_TARGET_LS1043ARDB is not set
++# CONFIG_TARGET_LS1046AQDS is not set
++# CONFIG_TARGET_LS1046ARDB is not set
++# CONFIG_TARGET_LS1046AFRWY is not set
++# CONFIG_TARGET_SL28 is not set
++# CONFIG_TARGET_TEN64 is not set
++# CONFIG_ARCH_UNIPHIER is not set
++# CONFIG_ARCH_SYNQUACER is not set
++# CONFIG_ARCH_STM32 is not set
++# CONFIG_ARCH_STI is not set
++# CONFIG_ARCH_STM32MP is not set
++# CONFIG_ARCH_ROCKCHIP is not set
++# CONFIG_ARCH_OCTEONTX is not set
++# CONFIG_ARCH_OCTEONTX2 is not set
++# CONFIG_TARGET_THUNDERX_88XX is not set
++# CONFIG_ARCH_ASPEED is not set
++# CONFIG_TARGET_DURIAN is not set
++# CONFIG_TARGET_POMELO is not set
++# CONFIG_TARGET_PRESIDIO_ASIC is not set
++# CONFIG_TARGET_XENGUEST_ARM64 is not set
++# CONFIG_ARCH_GXP is not set
++# CONFIG_STATIC_MACH_TYPE is not set
++CONFIG_TEXT_BASE=0x41e00000
++CONFIG_SYS_MALLOC_LEN=0x400000
++CONFIG_SYS_MALLOC_F_LEN=0x4000
++CONFIG_NR_DRAM_BANKS=1
++CONFIG_ENV_SOURCE_FILE=""
++CONFIG_SF_DEFAULT_SPEED=1000000
++CONFIG_SF_DEFAULT_MODE=0x0
++CONFIG_ENV_SIZE=0x1f000
++CONFIG_DM_GPIO=y
++CONFIG_DEFAULT_DEVICE_TREE="openwrt-one"
++CONFIG_OF_LIBFDT_OVERLAY=y
++CONFIG_MULTI_DTB_FIT_UNCOMPRESS_SZ=0x8000
++CONFIG_DM_RESET=y
++CONFIG_SYS_MONITOR_LEN=0
++# CONFIG_MT8512 is not set
++# CONFIG_TARGET_MT7622 is not set
++# CONFIG_TARGET_MT7623 is not set
++# CONFIG_TARGET_MT7629 is not set
++CONFIG_TARGET_MT7981=y
++# CONFIG_TARGET_MT7986 is not set
++# CONFIG_TARGET_MT7988 is not set
++# CONFIG_TARGET_MT8183 is not set
++# CONFIG_TARGET_MT8512 is not set
++# CONFIG_TARGET_MT8516 is not set
++# CONFIG_TARGET_MT8518 is not set
++CONFIG_MTK_BROM_HEADER_INFO="media=snand;nandinfo=2k+64"
++CONFIG_RESET_BUTTON_LABEL="back"
++CONFIG_RESET_BUTTON_SETTLE_DELAY=0
++CONFIG_ERR_PTR_OFFSET=0x0
++# CONFIG_SPL is not set
++CONFIG_BOOTSTAGE_STASH_ADDR=0x0
++CONFIG_DEBUG_UART_BASE=0x11002000
++CONFIG_DEBUG_UART_CLOCK=40000000
++# CONFIG_DEBUG_UART_BOARD_INIT is not set
++CONFIG_IDENT_STRING=""
++CONFIG_SYS_CLK_FREQ=0
++# CONFIG_CHIP_DIP_SCAN is not set
++# CONFIG_CMO_BY_VA_ONLY is not set
++# CONFIG_ARMV8_MULTIENTRY is not set
++# CONFIG_ARMV8_SET_SMPEN is not set
++# CONFIG_ARMV8_SWITCH_TO_EL1 is not set
++
++#
++# ARMv8 secure monitor firmware
++#
++# CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT is not set
++CONFIG_PSCI_RESET=y
++# CONFIG_ARMV8_PSCI is not set
++# CONFIG_ARMV8_EA_EL3_FIRST is not set
++# CONFIG_ARMV8_CRYPTO is not set
++# CONFIG_CMD_DEKBLOB is not set
++# CONFIG_IMX_CAAM_DEK_ENCAP is not set
++# CONFIG_IMX_OPTEE_DEK_ENCAP is not set
++# CONFIG_IMX_SECO_DEK_ENCAP is not set
++# CONFIG_IMX_ELE_DEK_ENCAP is not set
++# CONFIG_CMD_HDMIDETECT is not set
++CONFIG_IMX_DCD_ADDR=0x00910000
++CONFIG_SYS_MEM_TOP_HIDE=0x0
++CONFIG_SYS_LOAD_ADDR=0x46000000
++
++#
++# ARM debug
++#
++CONFIG_BUILD_TARGET=""
++# CONFIG_PCI is not set
++CONFIG_FWU_NUM_BANKS=2
++CONFIG_FWU_NUM_IMAGES_PER_BANK=2
++CONFIG_DEBUG_UART=y
++# CONFIG_AHCI is not set
++# CONFIG_OF_BOARD_FIXUP is not set
++
++#
++# Functionality shared between NXP SoCs
++#
++# CONFIG_NXP_ESBC is not set
++
++#
++# General setup
++#
++CONFIG_LOCALVERSION=""
++CONFIG_LOCALVERSION_AUTO=y
++CONFIG_CC_IS_GCC=y
++CONFIG_GCC_VERSION=120300
++CONFIG_CLANG_VERSION=0
++CONFIG_CC_OPTIMIZE_FOR_SIZE=y
++# CONFIG_CC_OPTIMIZE_FOR_SPEED is not set
++# CONFIG_CC_OPTIMIZE_FOR_DEBUG is not set
++# CONFIG_OPTIMIZE_INLINING is not set
++CONFIG_ARCH_SUPPORTS_LTO=y
++# CONFIG_LTO is not set
++CONFIG_CC_HAS_ASM_INLINE=y
++# CONFIG_XEN is not set
++# CONFIG_ENV_VARS_UBOOT_CONFIG is not set
++# CONFIG_SYS_BOOT_GET_CMDLINE is not set
++# CONFIG_SYS_BOOT_GET_KBD is not set
++CONFIG_SYS_MALLOC_F=y
++# CONFIG_VALGRIND is not set
++CONFIG_EXPERT=y
++CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
++# CONFIG_SYS_MALLOC_DEFAULT_TO_INIT is not set
++# CONFIG_TOOLS_DEBUG is not set
++CONFIG_PHYS_64BIT=y
++CONFIG_FDT_64BIT=y
++# CONFIG_REMAKE_ELF is not set
++# CONFIG_HAS_BOARD_SIZE_LIMIT is not set
++# CONFIG_SYS_CUSTOM_LDSCRIPT is not set
++CONFIG_PLATFORM_ELFENTRY="_start"
++CONFIG_STACK_SIZE=0x1000000
++CONFIG_SYS_SRAM_BASE=0x0
++CONFIG_SYS_SRAM_SIZE=0x0
++# CONFIG_MP is not set
++CONFIG_HAVE_TEXT_BASE=y
++# CONFIG_HAVE_SYS_UBOOT_START is not set
++CONFIG_SYS_UBOOT_START=0x41e00000
++# CONFIG_DYNAMIC_SYS_CLK_FREQ is not set
++# CONFIG_API is not set
++
++#
++# Boot options
++#
++
++#
++# Boot images
++#
++# CONFIG_ANDROID_BOOT_IMAGE is not set
++# CONFIG_TIMESTAMP is not set
++CONFIG_FIT=y
++CONFIG_FIT_EXTERNAL_OFFSET=0x0
++CONFIG_FIT_FULL_CHECK=y
++# CONFIG_FIT_SIGNATURE is not set
++# CONFIG_FIT_CIPHER is not set
++# CONFIG_FIT_VERBOSE is not set
++# CONFIG_FIT_BEST_MATCH is not set
++CONFIG_FIT_PRINT=y
++# CONFIG_SPL_LOAD_FIT_FULL is not set
++CONFIG_PXE_UTILS=y
++CONFIG_BOOTSTD=y
++# CONFIG_BOOTSTD_FULL is not set
++# CONFIG_BOOTSTD_DEFAULTS is not set
++CONFIG_BOOTSTD_BOOTCOMMAND=y
++CONFIG_BOOTMETH_GLOBAL=y
++# CONFIG_BOOTMETH_CROS is not set
++CONFIG_BOOTMETH_EXTLINUX=y
++CONFIG_BOOTMETH_EXTLINUX_PXE=y
++CONFIG_BOOTMETH_EFILOADER=y
++CONFIG_BOOTMETH_VBE=y
++CONFIG_BOOTMETH_VBE_REQUEST=y
++CONFIG_BOOTMETH_VBE_SIMPLE=y
++CONFIG_BOOTMETH_VBE_SIMPLE_OS=y
++# CONFIG_BOOTMETH_SCRIPT is not set
++CONFIG_LEGACY_IMAGE_FORMAT=y
++# CONFIG_SUPPORT_RAW_INITRD is not set
++# CONFIG_CHROMEOS is not set
++# CONFIG_CHROMEOS_VBOOT is not set
++# CONFIG_RAMBOOT_PBL is not set
++CONFIG_SYS_BOOT_RAMDISK_HIGH=y
++# CONFIG_DISTRO_DEFAULTS is not set
++
++#
++# Boot timing
++#
++# CONFIG_BOOTSTAGE is not set
++CONFIG_BOOTSTAGE_STASH_SIZE=0x1000
++# CONFIG_SHOW_BOOT_PROGRESS is not set
++
++#
++# Boot media
++#
++CONFIG_NAND_BOOT=y
++# CONFIG_ONENAND_BOOT is not set
++# CONFIG_QSPI_BOOT is not set
++# CONFIG_SATA_BOOT is not set
++# CONFIG_SD_BOOT is not set
++# CONFIG_SD_BOOT_QSPI is not set
++CONFIG_SPI_BOOT=y
++
++#
++# Autoboot options
++#
++CONFIG_AUTOBOOT=y
++CONFIG_BOOTDELAY=2
++# CONFIG_AUTOBOOT_KEYED is not set
++# CONFIG_AUTOBOOT_USE_MENUKEY is not set
++CONFIG_AUTOBOOT_MENU_SHOW=y
++# CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE is not set
++# CONFIG_BOOT_RETRY is not set
++
++#
++# Image support
++#
++# CONFIG_IMAGE_PRE_LOAD is not set
++
++#
++# Devicetree fixup
++#
++# CONFIG_OF_BOARD_SETUP is not set
++# CONFIG_OF_SYSTEM_SETUP is not set
++# CONFIG_OF_STDOUT_VIA_ALIAS is not set
++# CONFIG_FDT_FIXUP_PARTITIONS is not set
++# CONFIG_FDT_SIMPLEFB is not set
++CONFIG_ARCH_FIXUP_FDT_MEMORY=y
++# CONFIG_USE_BOOTARGS is not set
++# CONFIG_BOOTARGS_SUBST is not set
++# CONFIG_USE_BOOTCOMMAND is not set
++CONFIG_USE_PREBOOT=y
++CONFIG_DEFAULT_FDT_FILE="openwrt-one"
++# CONFIG_SAVE_PREV_BL_FDT_ADDR is not set
++# CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR is not set
++
++#
++# Configuration editor
++#
++# CONFIG_CEDIT is not set
++
++#
++# Console
++#
++CONFIG_MENU=y
++# CONFIG_CONSOLE_RECORD is not set
++# CONFIG_DISABLE_CONSOLE is not set
++CONFIG_LOGLEVEL=7
++# CONFIG_SILENT_CONSOLE is not set
++# CONFIG_SPL_SILENT_CONSOLE is not set
++# CONFIG_TPL_SILENT_CONSOLE is not set
++# CONFIG_PRE_CONSOLE_BUFFER is not set
++CONFIG_CONSOLE_FLUSH_SUPPORT=y
++# CONFIG_CONSOLE_FLUSH_ON_NEWLINE is not set
++# CONFIG_CONSOLE_MUX is not set
++# CONFIG_SYS_CONSOLE_IS_IN_ENV is not set
++# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set
++# CONFIG_SYS_CONSOLE_INFO_QUIET is not set
++# CONFIG_SYS_STDIO_DEREGISTER is not set
++# CONFIG_SPL_SYS_STDIO_DEREGISTER is not set
++# CONFIG_SYS_DEVICE_NULLDEV is not set
++
++#
++# Logging
++#
++CONFIG_LOG=y
++CONFIG_LOG_MAX_LEVEL=6
++CONFIG_LOG_DEFAULT_LEVEL=6
++CONFIG_LOG_CONSOLE=y
++# CONFIG_LOGF_FILE is not set
++# CONFIG_LOGF_LINE is not set
++# CONFIG_LOGF_FUNC is not set
++CONFIG_LOGF_FUNC_PAD=20
++# CONFIG_LOG_SYSLOG is not set
++# CONFIG_LOG_ERROR_RETURN is not set
++
++#
++# Init options
++#
++# CONFIG_BOARD_TYPES is not set
++CONFIG_DISPLAY_CPUINFO=y
++CONFIG_DISPLAY_BOARDINFO=y
++# CONFIG_DISPLAY_BOARDINFO_LATE is not set
++
++#
++# Start-up hooks
++#
++# CONFIG_CYCLIC is not set
++CONFIG_EVENT=y
++CONFIG_EVENT_DYNAMIC=y
++# CONFIG_EVENT_DEBUG is not set
++# CONFIG_ARCH_MISC_INIT is not set
++# CONFIG_BOARD_EARLY_INIT_F is not set
++# CONFIG_BOARD_EARLY_INIT_R is not set
++# CONFIG_BOARD_POSTCLK_INIT is not set
++CONFIG_BOARD_LATE_INIT=y
++# CONFIG_CLOCKS is not set
++# CONFIG_HWCONFIG is not set
++CONFIG_LAST_STAGE_INIT=y
++# CONFIG_MISC_INIT_R is not set
++# CONFIG_SYS_MALLOC_BOOTPARAMS is not set
++# CONFIG_ID_EEPROM is not set
++# CONFIG_RESET_PHY_R is not set
++
++#
++# Security support
++#
++CONFIG_HASH=y
++# CONFIG_STACKPROTECTOR is not set
++# CONFIG_BOARD_RNG_SEED is not set
++
++#
++# Update support
++#
++# CONFIG_UPDATE_TFTP is not set
++# CONFIG_ANDROID_AB is not set
++
++#
++# Blob list
++#
++# CONFIG_BLOBLIST is not set
++CONFIG_SUPPORT_SPL=y
++# CONFIG_VPL is not set
++
++#
++# Command line interface
++#
++CONFIG_CMDLINE=y
++CONFIG_HUSH_PARSER=y
++CONFIG_CMDLINE_EDITING=y
++# CONFIG_CMDLINE_PS_SUPPORT is not set
++CONFIG_AUTO_COMPLETE=y
++CONFIG_SYS_LONGHELP=y
++CONFIG_SYS_PROMPT="OpenWrt One> "
++CONFIG_SYS_PROMPT_HUSH_PS2="> "
++CONFIG_SYS_MAXARGS=16
++CONFIG_SYS_CBSIZE=512
++CONFIG_SYS_PBSIZE=1049
++CONFIG_SYS_XTRACE=y
++CONFIG_BUILD_BIN2C=y
++
++#
++# Commands
++#
++
++#
++# Info commands
++#
++CONFIG_CMD_BDI=y
++# CONFIG_CMD_BDINFO_EXTRA is not set
++# CONFIG_CMD_CONFIG is not set
++CONFIG_CMD_CONSOLE=y
++CONFIG_CMD_CPU=y
++# CONFIG_CMD_HISTORY is not set
++CONFIG_CMD_LICENSE=y
++# CONFIG_CMD_PMC is not set
++
++#
++# Boot commands
++#
++CONFIG_CMD_BOOTD=y
++CONFIG_CMD_BOOTM=y
++# CONFIG_CMD_BOOTDEV is not set
++CONFIG_CMD_BOOTFLOW=y
++# CONFIG_CMD_BOOTMETH is not set
++CONFIG_BOOTM_EFI=y
++# CONFIG_CMD_BOOTZ is not set
++CONFIG_CMD_BOOTI=y
++CONFIG_BOOTM_LINUX=y
++# CONFIG_BOOTM_NETBSD is not set
++# CONFIG_BOOTM_OPENRTOS is not set
++# CONFIG_BOOTM_OSE is not set
++# CONFIG_BOOTM_PLAN9 is not set
++# CONFIG_BOOTM_RTEMS is not set
++# CONFIG_CMD_VBE is not set
++# CONFIG_BOOTM_VXWORKS is not set
++CONFIG_SYS_BOOTM_LEN=0x4000000
++CONFIG_CMD_BOOTEFI=y
++CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
++# CONFIG_CMD_BOOTEFI_HELLO is not set
++# CONFIG_CMD_BOOTEFI_SELFTEST is not set
++CONFIG_CMD_BOOTMENU=y
++# CONFIG_CMD_ADTIMG is not set
++CONFIG_CMD_ELF=y
++CONFIG_CMD_FDT=y
++CONFIG_CMD_GO=y
++CONFIG_CMD_RUN=y
++CONFIG_CMD_IMI=y
++# CONFIG_CMD_IMLS is not set
++CONFIG_CMD_XIMG=y
++# CONFIG_CMD_ZBOOT is not set
++
++#
++# Environment commands
++#
++CONFIG_CMD_ASKENV=y
++CONFIG_CMD_EXPORTENV=y
++CONFIG_CMD_IMPORTENV=y
++CONFIG_CMD_EDITENV=y
++# CONFIG_CMD_GREPENV is not set
++CONFIG_CMD_SAVEENV=y
++CONFIG_CMD_ERASEENV=y
++CONFIG_CMD_ENV_EXISTS=y
++CONFIG_CMD_ENV_READMEM=y
++# CONFIG_CMD_ENV_CALLBACK is not set
++CONFIG_CMD_ENV_FLAGS=y
++# CONFIG_CMD_NVEDIT_EFI is not set
++# CONFIG_CMD_NVEDIT_INDIRECT is not set
++# CONFIG_CMD_NVEDIT_INFO is not set
++# CONFIG_CMD_NVEDIT_LOAD is not set
++# CONFIG_CMD_NVEDIT_SELECT is not set
++
++#
++# Memory commands
++#
++# CONFIG_CMD_BINOP is not set
++# CONFIG_CMD_BLOBLIST is not set
++CONFIG_CMD_CRC32=y
++# CONFIG_CRC32_VERIFY is not set
++# CONFIG_CMD_EEPROM is not set
++# CONFIG_LOOPW is not set
++# CONFIG_CMD_MD5SUM is not set
++# CONFIG_CMD_MEMINFO is not set
++CONFIG_CMD_MEMORY=y
++# CONFIG_CMD_MEM_SEARCH is not set
++# CONFIG_CMD_MX_CYCLIC is not set
++CONFIG_CMD_RANDOM=y
++# CONFIG_CMD_MEMTEST is not set
++# CONFIG_CMD_SHA1SUM is not set
++CONFIG_CMD_STRINGS=y
++
++#
++# Compression commands
++#
++CONFIG_CMD_LZMADEC=y
++# CONFIG_CMD_UNLZ4 is not set
++# CONFIG_CMD_UNZIP is not set
++# CONFIG_CMD_ZIP is not set
++
++#
++# Device access commands
++#
++# CONFIG_CMD_ARMFLASH is not set
++# CONFIG_CMD_BIND is not set
++# CONFIG_CMD_CLK is not set
++# CONFIG_CMD_DEMO is not set
++# CONFIG_CMD_DFU is not set
++CONFIG_CMD_DM=y
++CONFIG_CMD_FLASH=y
++# CONFIG_CMD_FPGAD is not set
++# CONFIG_CMD_FUSE is not set
++CONFIG_CMD_GPIO=y
++# CONFIG_CMD_GPIO_READ is not set
++CONFIG_CMD_PWM=y
++# CONFIG_CMD_GPT is not set
++# CONFIG_RANDOM_UUID is not set
++# CONFIG_CMD_IDE is not set
++# CONFIG_CMD_IO is not set
++# CONFIG_CMD_IOTRACE is not set
++# CONFIG_CMD_I2C is not set
++CONFIG_CMD_LOADB=y
++# CONFIG_CMD_LOADM is not set
++CONFIG_CMD_LOADS=y
++# CONFIG_LOADS_ECHO is not set
++# CONFIG_CMD_SAVES is not set
++# CONFIG_SYS_LOADS_BAUD_CHANGE is not set
++CONFIG_CMD_LOADXY_TIMEOUT=90
++# CONFIG_CMD_LSBLK is not set
++# CONFIG_CMD_MBR is not set
++# CONFIG_CMD_CLONE is not set
++CONFIG_CMD_MTD=y
++CONFIG_CMD_NAND_EXT=y
++# CONFIG_CMD_ONENAND is not set
++# CONFIG_CMD_OSD is not set
++# CONFIG_CMD_PART is not set
++CONFIG_CMD_PCI=y
++CONFIG_CMD_PINMUX=y
++# CONFIG_CMD_POWEROFF is not set
++# CONFIG_CMD_READ is not set
++# CONFIG_CMD_SATA is not set
++# CONFIG_CMD_SDRAM is not set
++CONFIG_CMD_SF=y
++CONFIG_CMD_SF_TEST=y
++# CONFIG_CMD_SPI is not set
++# CONFIG_CMD_TSI148 is not set
++# CONFIG_CMD_UNIVERSE is not set
++CONFIG_CMD_USB=y
++# CONFIG_CMD_USB_SDP is not set
++# CONFIG_CMD_RKMTD is not set
++# CONFIG_CMD_WRITE is not set
++
++#
++# Shell scripting commands
++#
++# CONFIG_CMD_CAT is not set
++CONFIG_CMD_ECHO=y
++CONFIG_CMD_ITEST=y
++CONFIG_CMD_SOURCE=y
++CONFIG_CMD_SETEXPR=y
++# CONFIG_CMD_SETEXPR_FMT is not set
++# CONFIG_CMD_XXD is not set
++
++#
++# Android support commands
++#
++CONFIG_CMD_NET=y
++CONFIG_CMD_BOOTP=y
++CONFIG_CMD_DHCP=y
++# CONFIG_BOOTP_MAY_FAIL is not set
++CONFIG_BOOTP_BOOTPATH=y
++# CONFIG_BOOTP_VENDOREX is not set
++# CONFIG_BOOTP_BOOTFILESIZE is not set
++CONFIG_BOOTP_DNS=y
++# CONFIG_BOOTP_DNS2 is not set
++CONFIG_BOOTP_GATEWAY=y
++CONFIG_BOOTP_HOSTNAME=y
++# CONFIG_BOOTP_PREFER_SERVERIP is not set
++CONFIG_BOOTP_SUBNETMASK=y
++# CONFIG_BOOTP_NISDOMAIN is not set
++# CONFIG_BOOTP_NTPSERVER is not set
++# CONFIG_BOOTP_TIMEOFFSET is not set
++# CONFIG_CMD_PCAP is not set
++CONFIG_BOOTP_PXE=y
++CONFIG_BOOTP_PXE_CLIENTARCH=0x16
++# CONFIG_BOOTP_PXE_DHCP_OPTION is not set
++CONFIG_BOOTP_VCI_STRING="U-Boot.armv8"
++CONFIG_CMD_TFTPBOOT=y
++# CONFIG_CMD_TFTPPUT is not set
++CONFIG_CMD_TFTPSRV=y
++CONFIG_NET_TFTP_VARS=y
++CONFIG_CMD_RARP=y
++# CONFIG_CMD_NFS is not set
++# CONFIG_SYS_DISABLE_AUTOLOAD is not set
++# CONFIG_CMD_WGET is not set
++# CONFIG_CMD_MII is not set
++# CONFIG_CMD_MDIO is not set
++CONFIG_CMD_PING=y
++CONFIG_CMD_CDP=y
++CONFIG_CMD_SNTP=y
++CONFIG_CMD_DNS=y
++CONFIG_CMD_LINK_LOCAL=y
++# CONFIG_CMD_ETHSW is not set
++CONFIG_CMD_PXE=y
++# CONFIG_CMD_WOL is not set
++
++#
++# Misc commands
++#
++# CONFIG_CMD_2048 is not set
++# CONFIG_CMD_BSP is not set
++CONFIG_CMD_BLOCK_CACHE=y
++CONFIG_CMD_BUTTON=y
++CONFIG_CMD_CACHE=y
++# CONFIG_CMD_CONITRACE is not set
++# CONFIG_CMD_CLS is not set
++# CONFIG_CMD_EFIDEBUG is not set
++CONFIG_CMD_EFICONFIG=y
++# CONFIG_CMD_EXCEPTION is not set
++CONFIG_CMD_LED=y
++# CONFIG_CMD_INI is not set
++# CONFIG_CMD_DATE is not set
++# CONFIG_CMD_TIME is not set
++# CONFIG_CMD_GETTIME is not set
++# CONFIG_CMD_PAUSE is not set
++CONFIG_CMD_SLEEP=y
++# CONFIG_CMD_TIMER is not set
++# CONFIG_CMD_SYSBOOT is not set
++# CONFIG_CMD_QFW is not set
++CONFIG_CMD_PSTORE=y
++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
++CONFIG_CMD_PSTORE_MEM_SIZE=0x10000
++CONFIG_CMD_PSTORE_RECORD_SIZE=0x1000
++CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x1000
++CONFIG_CMD_PSTORE_FTRACE_SIZE=0x1000
++CONFIG_CMD_PSTORE_PMSG_SIZE=0x1000
++CONFIG_CMD_PSTORE_ECC_SIZE=0
++# CONFIG_CMD_TERMINAL is not set
++CONFIG_CMD_UUID=y
++
++#
++# TI specific command line interface
++#
++
++#
++# Power commands
++#
++
++#
++# Security commands
++#
++# CONFIG_CMD_AES is not set
++# CONFIG_CMD_BLOB is not set
++CONFIG_CMD_HASH=y
++# CONFIG_CMD_HVC is not set
++CONFIG_CMD_SMC=y
++# CONFIG_HASH_VERIFY is not set
++
++#
++# Firmware commands
++#
++
++#
++# Filesystem commands
++#
++# CONFIG_CMD_BTRFS is not set
++# CONFIG_CMD_EROFS is not set
++# CONFIG_CMD_EXT2 is not set
++# CONFIG_CMD_EXT4 is not set
++CONFIG_CMD_FAT=y
++# CONFIG_CMD_SQUASHFS is not set
++CONFIG_CMD_FS_GENERIC=y
++CONFIG_CMD_FS_UUID=y
++# CONFIG_CMD_JFFS2 is not set
++# CONFIG_CMD_MTDPARTS is not set
++CONFIG_MTDIDS_DEFAULT=""
++CONFIG_MTDPARTS_DEFAULT=""
++# CONFIG_CMD_REISER is not set
++# CONFIG_CMD_ZFS is not set
++
++#
++# Debug commands
++#
++# CONFIG_CMD_DIAG is not set
++# CONFIG_CMD_EVENT is not set
++# CONFIG_CMD_LOG is not set
++CONFIG_CMD_UBI=y
++CONFIG_CMD_UBI_RENAME=y
++CONFIG_CMD_UBIFS=y
++
++#
++# Partition Types
++#
++CONFIG_PARTITIONS=y
++# CONFIG_MAC_PARTITION is not set
++CONFIG_DOS_PARTITION=y
++# CONFIG_ISO_PARTITION is not set
++# CONFIG_AMIGA_PARTITION is not set
++# CONFIG_EFI_PARTITION is not set
++CONFIG_PARTITION_UUIDS=y
++CONFIG_SUPPORT_OF_CONTROL=y
++
++#
++# Device Tree Control
++#
++CONFIG_OF_CONTROL=y
++CONFIG_OF_REAL=y
++# CONFIG_OF_LIVE is not set
++CONFIG_OF_SEPARATE=y
++# CONFIG_OF_EMBED is not set
++# CONFIG_OF_BOARD is not set
++# CONFIG_OF_OMIT_DTB is not set
++CONFIG_DEVICE_TREE_INCLUDES=""
++CONFIG_OF_LIST="openwrt-one"
++# CONFIG_MULTI_DTB_FIT is not set
++CONFIG_OF_TAG_MIGRATE=y
++# CONFIG_OF_DTB_PROPS_REMOVE is not set
++
++#
++# Environment
++#
++CONFIG_ENV_SUPPORT=y
++CONFIG_SAVEENV=y
++CONFIG_ENV_OVERWRITE=y
++CONFIG_ENV_MIN_ENTRIES=64
++CONFIG_ENV_MAX_ENTRIES=512
++# CONFIG_ENV_IS_NOWHERE is not set
++# CONFIG_ENV_IS_IN_EEPROM is not set
++# CONFIG_ENV_IS_IN_FAT is not set
++# CONFIG_ENV_IS_IN_EXT4 is not set
++# CONFIG_ENV_IS_IN_FLASH is not set
++# CONFIG_ENV_IS_IN_MTD is not set
++# CONFIG_ENV_IS_IN_NAND is not set
++# CONFIG_ENV_IS_IN_NVRAM is not set
++# CONFIG_ENV_IS_IN_ONENAND is not set
++# CONFIG_ENV_IS_IN_REMOTE is not set
++# CONFIG_ENV_IS_IN_SPI_FLASH is not set
++CONFIG_ENV_IS_IN_UBI=y
++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
++CONFIG_ENV_UBI_PART="ubi"
++CONFIG_ENV_UBI_VOLUME="ubootenv"
++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2"
++# CONFIG_ENV_UBI_VOLUME_CREATE is not set
++CONFIG_ENV_UBI_VID_OFFSET=0
++CONFIG_SYS_RELOC_GD_ENV_ADDR=y
++CONFIG_USE_DEFAULT_ENV_FILE=y
++CONFIG_DEFAULT_ENV_FILE="openwrt-one-spi-nand_env"
++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
++# CONFIG_ENV_IMPORT_FDT is not set
++# CONFIG_ENV_APPEND is not set
++# CONFIG_ENV_WRITEABLE_LIST is not set
++# CONFIG_ENV_ACCESS_IGNORE_FORCE is not set
++# CONFIG_USE_BOOTFILE is not set
++# CONFIG_USE_ETHPRIME is not set
++# CONFIG_USE_HOSTNAME is not set
++# CONFIG_VERSION_VARIABLE is not set
++CONFIG_NET=y
++CONFIG_ARP_TIMEOUT=5000
++CONFIG_NET_RETRY_COUNT=5
++CONFIG_PROT_UDP=y
++CONFIG_BOOTDEV_ETH=y
++# CONFIG_BOOTP_SEND_HOSTNAME is not set
++CONFIG_NET_RANDOM_ETHADDR=y
++# CONFIG_NETCONSOLE is not set
++# CONFIG_IP_DEFRAG is not set
++# CONFIG_SYS_FAULT_ECHO_LINK_DOWN is not set
++CONFIG_TFTP_BLOCKSIZE=1468
++# CONFIG_TFTP_PORT is not set
++CONFIG_TFTP_WINDOWSIZE=1
++# CONFIG_TFTP_TSIZE is not set
++# CONFIG_SERVERIP_FROM_PROXYDHCP is not set
++CONFIG_SERVERIP_FROM_PROXYDHCP_DELAY_MS=100
++# CONFIG_KEEP_SERVERADDR is not set
++# CONFIG_UDP_CHECKSUM is not set
++# CONFIG_BOOTP_SERVERIP is not set
++CONFIG_BOOTP_MAX_ROOT_PATH_LEN=64
++# CONFIG_USE_GATEWAYIP is not set
++# CONFIG_USE_IPADDR is not set
++# CONFIG_USE_NETMASK is not set
++# CONFIG_USE_ROOTPATH is not set
++# CONFIG_USE_SERVERIP is not set
++# CONFIG_PROT_TCP is not set
++# CONFIG_IPV6 is not set
++CONFIG_SYS_RX_ETH_BUFFER=4
++
++#
++# Device Drivers
++#
++
++#
++# Generic Driver Options
++#
++CONFIG_DM=y
++# CONFIG_DM_WARN is not set
++# CONFIG_DM_DEBUG is not set
++# CONFIG_DM_STATS is not set
++CONFIG_DM_DEVICE_REMOVE=y
++CONFIG_DM_EVENT=y
++CONFIG_DM_STDIO=y
++CONFIG_DM_SEQ_ALIAS=y
++# CONFIG_DM_DMA is not set
++CONFIG_REGMAP=y
++CONFIG_SYSCON=y
++# CONFIG_DEVRES is not set
++CONFIG_SIMPLE_BUS=y
++# CONFIG_SIMPLE_BUS_CORRECT_RANGE is not set
++# CONFIG_SIMPLE_PM_BUS is not set
++CONFIG_OF_TRANSLATE=y
++# CONFIG_TRANSLATION_OFFSET is not set
++CONFIG_DM_DEV_READ_INLINE=y
++# CONFIG_OFNODE_MULTI_TREE is not set
++# CONFIG_BOUNCE_BUFFER is not set
++# CONFIG_ADC is not set
++# CONFIG_ADC_EXYNOS is not set
++# CONFIG_ADC_SANDBOX is not set
++# CONFIG_SARADC_MESON is not set
++# CONFIG_SARADC_ROCKCHIP is not set
++# CONFIG_SATA is not set
++# CONFIG_SCSI_AHCI is not set
++
++#
++# SATA/SCSI device support
++#
++# CONFIG_AXI is not set
++
++#
++# Bus devices
++#
++CONFIG_BLK=y
++CONFIG_BLOCK_CACHE=y
++# CONFIG_BLKMAP is not set
++# CONFIG_EFI_MEDIA is not set
++# CONFIG_IDE is not set
++# CONFIG_LBA48 is not set
++# CONFIG_SYS_64BIT_LBA is not set
++# CONFIG_RKMTD is not set
++# CONFIG_BOOTCOUNT_LIMIT is not set
++
++#
++# Button Support
++#
++CONFIG_BUTTON=y
++# CONFIG_BUTTON_ADC is not set
++CONFIG_BUTTON_GPIO=y
++
++#
++# Cache Controller drivers
++#
++# CONFIG_CACHE is not set
++# CONFIG_L2X0_CACHE is not set
++# CONFIG_V5L2_CACHE is not set
++# CONFIG_NCORE_CACHE is not set
++# CONFIG_SIFIVE_CCACHE is not set
++
++#
++# Clock
++#
++CONFIG_CLK=y
++# CONFIG_CLK_CCF is not set
++# CONFIG_CLK_GPIO is not set
++# CONFIG_CLK_CDCE9XX is not set
++# CONFIG_CLK_ICS8N3QV01 is not set
++# CONFIG_CLK_K210 is not set
++# CONFIG_CLK_MPC83XX is not set
++# CONFIG_CLK_XLNX_CLKWZRD is not set
++# CONFIG_CLK_AT91 is not set
++# CONFIG_CLK_RCAR is not set
++# CONFIG_CLK_RCAR_CPG_LIB is not set
++# CONFIG_CLK_SIFIVE is not set
++# CONFIG_CLK_TI_AM3_DPLL is not set
++# CONFIG_CLK_TI_CTRL is not set
++# CONFIG_CLK_TI_GATE is not set
++# CONFIG_CLK_K3 is not set
++CONFIG_CPU=y
++# CONFIG_CPU_IMX is not set
++
++#
++# Hardware crypto devices
++#
++# CONFIG_DM_HASH is not set
++# CONFIG_FSL_CAAM is not set
++CONFIG_CAAM_64BIT=y
++# CONFIG_SYS_FSL_SEC_BE is not set
++# CONFIG_SYS_FSL_SEC_LE is not set
++# CONFIG_NPCM_AES is not set
++# CONFIG_NPCM_SHA is not set
++# CONFIG_DDR_SPD is not set
++# CONFIG_IMX_SNPS_DDR_PHY is not set
++
++#
++# Demo for driver model
++#
++# CONFIG_DM_DEMO is not set
++
++#
++# DFU support
++#
++
++#
++# DMA Support
++#
++# CONFIG_DMA is not set
++# CONFIG_DMA_LPC32XX is not set
++# CONFIG_TI_EDMA3 is not set
++# CONFIG_DMA_LEGACY is not set
++
++#
++# Extcon Support
++#
++# CONFIG_EXTCON is not set
++
++#
++# Fastboot support
++#
++# CONFIG_UDP_FUNCTION_FASTBOOT is not set
++# CONFIG_TCP_FUNCTION_FASTBOOT is not set
++CONFIG_FIRMWARE=y
++CONFIG_ARM_PSCI_FW=y
++# CONFIG_ZYNQMP_FIRMWARE is not set
++# CONFIG_ARM_SMCCC_FEATURES is not set
++# CONFIG_ARM_FFA_TRANSPORT is not set
++# CONFIG_SCMI_FIRMWARE is not set
++# CONFIG_DM_FUZZING_ENGINE is not set
++
++#
++# FPGA support
++#
++# CONFIG_FPGA_ALTERA is not set
++# CONFIG_FPGA_SOCFPGA is not set
++# CONFIG_FPGA_LATTICE is not set
++# CONFIG_FPGA_XILINX is not set
++# CONFIG_DM_FPGA is not set
++# CONFIG_FWU_MDATA is not set
++CONFIG_GPIO=y
++CONFIG_GPIO_HOG=y
++# CONFIG_DM_GPIO_LOOKUP_LABEL is not set
++# CONFIG_ALTERA_PIO is not set
++# CONFIG_BCM2835_GPIO is not set
++# CONFIG_DWAPB_GPIO is not set
++# CONFIG_AT91_GPIO is not set
++# CONFIG_ATMEL_PIO4 is not set
++# CONFIG_ASPEED_GPIO is not set
++# CONFIG_DA8XX_GPIO is not set
++# CONFIG_HIKEY_GPIO is not set
++# CONFIG_INTEL_BROADWELL_GPIO is not set
++# CONFIG_INTEL_GPIO is not set
++# CONFIG_INTEL_ICH6_GPIO is not set
++# CONFIG_IMX_RGPIO2P is not set
++# CONFIG_IPROC_GPIO is not set
++# CONFIG_HSDK_CREG_GPIO is not set
++# CONFIG_KIRKWOOD_GPIO is not set
++# CONFIG_LPC32XX_GPIO is not set
++# CONFIG_MCP230XX_GPIO is not set
++# CONFIG_MSM_GPIO is not set
++# CONFIG_MXC_GPIO is not set
++# CONFIG_MXS_GPIO is not set
++# CONFIG_NPCM_GPIO is not set
++# CONFIG_CMD_PCA953X is not set
++# CONFIG_ROCKCHIP_GPIO is not set
++# CONFIG_XILINX_GPIO is not set
++# CONFIG_TCA642X is not set
++# CONFIG_TEGRA_GPIO is not set
++# CONFIG_TEGRA186_GPIO is not set
++# CONFIG_VYBRID_GPIO is not set
++# CONFIG_SIFIVE_GPIO is not set
++# CONFIG_ZYNQ_GPIO is not set
++# CONFIG_DM_74X164 is not set
++# CONFIG_PCA953X is not set
++# CONFIG_MPC8XXX_GPIO is not set
++# CONFIG_MPC8XX_GPIO is not set
++# CONFIG_NX_GPIO is not set
++# CONFIG_NOMADIK_GPIO is not set
++# CONFIG_ZYNQMP_GPIO_MODEPIN is not set
++# CONFIG_SLG7XL45106_I2C_GPO is not set
++# CONFIG_TURRIS_OMNIA_MCU is not set
++# CONFIG_FTGPIO010 is not set
++
++#
++# Hardware Spinlock Support
++#
++# CONFIG_DM_HWSPINLOCK is not set
++CONFIG_I2C=y
++# CONFIG_DM_I2C is not set
++# CONFIG_SYS_I2C_LEGACY is not set
++# CONFIG_SPL_SYS_I2C_LEGACY is not set
++# CONFIG_SYS_I2C_FSL is not set
++# CONFIG_SYS_I2C_DW is not set
++# CONFIG_SYS_I2C_IMX_LPI2C is not set
++# CONFIG_SYS_I2C_MTK is not set
++# CONFIG_SYS_I2C_MICROCHIP is not set
++# CONFIG_SYS_I2C_MXC is not set
++# CONFIG_SYS_I2C_NPCM is not set
++# CONFIG_SYS_I2C_SOFT is not set
++# CONFIG_SYS_I2C_MV is not set
++# CONFIG_SYS_I2C_MVTWSI is not set
++CONFIG_INPUT=y
++# CONFIG_DM_KEYBOARD is not set
++# CONFIG_CROS_EC_KEYB is not set
++# CONFIG_TEGRA_KEYBOARD is not set
++# CONFIG_TWL4030_INPUT is not set
++
++#
++# IOMMU device drivers
++#
++# CONFIG_IOMMU is not set
++
++#
++# LED Support
++#
++CONFIG_LED=y
++# CONFIG_LED_PWM is not set
++CONFIG_LED_BLINK=y
++CONFIG_LED_GPIO=y
++# CONFIG_LED_STATUS is not set
++
++#
++# Mailbox Controller Support
++#
++# CONFIG_DM_MAILBOX is not set
++
++#
++# Memory Controller drivers
++#
++# CONFIG_MEMORY is not set
++# CONFIG_ATMEL_EBI is not set
++# CONFIG_MFD_ATMEL_SMC is not set
++
++#
++# Multifunction device drivers
++#
++# CONFIG_MISC is not set
++# CONFIG_NVMEM is not set
++# CONFIG_SPL_NVMEM is not set
++# CONFIG_SMSC_LPC47M is not set
++# CONFIG_SMSC_SIO1007 is not set
++# CONFIG_CROS_EC is not set
++# CONFIG_DS4510 is not set
++# CONFIG_FSL_SEC_MON is not set
++# CONFIG_IRQ is not set
++# CONFIG_NPCM_HOST is not set
++# CONFIG_NUVOTON_NCT6102D is not set
++# CONFIG_PWRSEQ is not set
++# CONFIG_PCA9551_LED is not set
++# CONFIG_TEST_DRV is not set
++# CONFIG_USB_HUB_USB251XB is not set
++# CONFIG_TWL4030_LED is not set
++# CONFIG_WINBOND_W83627 is not set
++# CONFIG_FS_LOADER is not set
++
++#
++# MMC Host controller Support
++#
++# CONFIG_MMC is not set
++# CONFIG_MMC_BROKEN_CD is not set
++# CONFIG_DM_MMC is not set
++# CONFIG_FSL_ESDHC is not set
++# CONFIG_FSL_ESDHC_IMX is not set
++
++#
++# MTD Support
++#
++CONFIG_MTD_PARTITIONS=y
++CONFIG_MTD=y
++CONFIG_DM_MTD=y
++# CONFIG_MTD_NOR_FLASH is not set
++# CONFIG_MTD_CONCAT is not set
++# CONFIG_SYS_MTDPARTS_RUNTIME is not set
++# CONFIG_FLASH_CFI_DRIVER is not set
++# CONFIG_CFI_FLASH is not set
++# CONFIG_ALTERA_QSPI is not set
++# CONFIG_HBMC_AM654 is not set
++# CONFIG_SAMSUNG_ONENAND is not set
++# CONFIG_USE_SYS_MAX_FLASH_BANKS is not set
++CONFIG_MTD_NAND_CORE=y
++# CONFIG_MTD_RAW_NAND is not set
++CONFIG_MTD_SPI_NAND=y
++
++#
++# SPI Flash Support
++#
++CONFIG_DM_SPI_FLASH=y
++CONFIG_SPI_FLASH=y
++CONFIG_SF_DEFAULT_BUS=0
++CONFIG_SF_DEFAULT_CS=0
++# CONFIG_BOOTDEV_SPI_FLASH is not set
++CONFIG_SPI_FLASH_SFDP_SUPPORT=y
++CONFIG_SPI_FLASH_SMART_HWCAPS=y
++# CONFIG_SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT is not set
++# CONFIG_SPI_FLASH_SOFT_RESET is not set
++# CONFIG_SPI_FLASH_BAR is not set
++CONFIG_SPI_FLASH_LOCK=y
++CONFIG_SPI_FLASH_UNLOCK_ALL=y
++# CONFIG_SPI_FLASH_ATMEL is not set
++CONFIG_SPI_FLASH_EON=y
++CONFIG_SPI_FLASH_GIGADEVICE=y
++CONFIG_SPI_FLASH_ISSI=y
++CONFIG_SPI_FLASH_MACRONIX=y
++CONFIG_SPI_FLASH_SPANSION=y
++# CONFIG_SPI_FLASH_S28HX_T is not set
++CONFIG_SPI_FLASH_STMICRO=y
++# CONFIG_SPI_FLASH_MT35XU is not set
++# CONFIG_SPI_FLASH_SST is not set
++CONFIG_SPI_FLASH_WINBOND=y
++CONFIG_SPI_FLASH_XMC=y
++CONFIG_SPI_FLASH_XTX=y
++# CONFIG_SPI_FLASH_ZBIT is not set
++CONFIG_SPI_FLASH_USE_4K_SECTORS=y
++# CONFIG_SPI_FLASH_DATAFLASH is not set
++CONFIG_SPI_FLASH_MTD=y
++
++#
++# UBI support
++#
++CONFIG_UBI_SILENCE_MSG=y
++CONFIG_MTD_UBI=y
++CONFIG_MTD_UBI_MODULE=y
++CONFIG_MTD_UBI_WL_THRESHOLD=4096
++CONFIG_MTD_UBI_BEB_LIMIT=20
++# CONFIG_MTD_UBI_FASTMAP is not set
++# CONFIG_NVMXIP is not set
++# CONFIG_NVMXIP_QSPI is not set
++# CONFIG_NMBM is not set
++
++#
++# Multiplexer drivers
++#
++# CONFIG_MULTIPLEXER is not set
++# CONFIG_BITBANGMII is not set
++# CONFIG_MV88E6352_SWITCH is not set
++CONFIG_PHYLIB=y
++# CONFIG_PHY_ADDR_ENABLE is not set
++# CONFIG_B53_SWITCH is not set
++# CONFIG_MV88E61XX_SWITCH is not set
++# CONFIG_PHYLIB_10G is not set
++# CONFIG_PHY_ADIN is not set
++# CONFIG_PHY_AIROHA is not set
++# CONFIG_PHY_AQUANTIA is not set
++# CONFIG_PHY_ATHEROS is not set
++# CONFIG_SPL_PHY_ATHEROS is not set
++# CONFIG_PHY_BROADCOM is not set
++# CONFIG_PHY_CORTINA is not set
++# CONFIG_PHY_DAVICOM is not set
++# CONFIG_PHY_ET1011C is not set
++# CONFIG_PHY_LXT is not set
++# CONFIG_PHY_MARVELL is not set
++# CONFIG_PHY_MARVELL_10G is not set
++# CONFIG_PHY_MESON_GXL is not set
++# CONFIG_PHY_MICREL is not set
++# CONFIG_PHY_MOTORCOMM is not set
++# CONFIG_PHY_MSCC is not set
++# CONFIG_PHY_NATSEMI is not set
++# CONFIG_PHY_NXP_C45_TJA11XX is not set
++# CONFIG_PHY_NXP_TJA11XX is not set
++# CONFIG_PHY_REALTEK is not set
++# CONFIG_PHY_SMSC is not set
++# CONFIG_PHY_TERANETICS is not set
++# CONFIG_PHY_TI is not set
++# CONFIG_PHY_TI_DP83867 is not set
++# CONFIG_PHY_TI_DP83869 is not set
++# CONFIG_PHY_TI_GENERIC is not set
++# CONFIG_PHY_VITESSE is not set
++# CONFIG_PHY_XILINX is not set
++# CONFIG_PHY_XILINX_GMII2RGMII is not set
++# CONFIG_PHY_XWAY is not set
++# CONFIG_PHY_ETHERNET_ID is not set
++CONFIG_PHY_FIXED=y
++# CONFIG_PHY_NCSI is not set
++# CONFIG_FSL_MEMAC is not set
++CONFIG_PHY_RESET_DELAY=0
++# CONFIG_FSL_PFE is not set
++CONFIG_ETH=y
++CONFIG_DM_ETH=y
++# CONFIG_DM_MDIO is not set
++# CONFIG_DM_ETH_PHY is not set
++CONFIG_NETDEVICES=y
++# CONFIG_PHY_GIGE is not set
++# CONFIG_ALTERA_TSE is not set
++# CONFIG_BCM_SF2_ETH is not set
++# CONFIG_BCMGENET is not set
++# CONFIG_BNXT_ETH is not set
++# CONFIG_CALXEDA_XGMAC is not set
++# CONFIG_DRIVER_DM9000 is not set
++# CONFIG_DWC_ETH_QOS is not set
++# CONFIG_EEPRO100 is not set
++# CONFIG_ETH_DESIGNWARE is not set
++# CONFIG_ETH_DESIGNWARE_MESON8B is not set
++# CONFIG_ETHOC is not set
++# CONFIG_FMAN_ENET is not set
++# CONFIG_FTMAC100 is not set
++# CONFIG_FTGMAC100 is not set
++# CONFIG_MCFFEC is not set
++# CONFIG_FSLDMAFEC is not set
++# CONFIG_KS8851_MLL is not set
++# CONFIG_LITEETH is not set
++# CONFIG_MACB is not set
++# CONFIG_NET_NPCM750 is not set
++# CONFIG_PCH_GBE is not set
++# CONFIG_RGMII is not set
++# CONFIG_MII is not set
++# CONFIG_RMII is not set
++# CONFIG_PCNET is not set
++# CONFIG_QE_UEC is not set
++# CONFIG_RTL8139 is not set
++# CONFIG_SMC911X is not set
++# CONFIG_SUN7I_GMAC is not set
++# CONFIG_SUN4I_EMAC is not set
++# CONFIG_SUN8I_EMAC is not set
++# CONFIG_SH_ETHER is not set
++# CONFIG_DRIVER_TI_CPSW is not set
++# CONFIG_DRIVER_TI_EMAC is not set
++# CONFIG_DRIVER_TI_KEYSTONE_NET is not set
++# CONFIG_TULIP is not set
++# CONFIG_XILINX_AXIEMAC is not set
++# CONFIG_VSC7385_ENET is not set
++# CONFIG_XILINX_EMACLITE is not set
++# CONFIG_ZYNQ_GEM is not set
++# CONFIG_SYS_DPAA_QBMAN is not set
++# CONFIG_TSEC_ENET is not set
++CONFIG_MEDIATEK_ETH=y
++# CONFIG_HIFEMAC_ETH is not set
++# CONFIG_HIGMACV300_ETH is not set
++# CONFIG_NVME is not set
++# CONFIG_NVME_APPLE is not set
++
++#
++# PCI Endpoint
++#
++# CONFIG_PCI_ENDPOINT is not set
++# CONFIG_X86_PCH7 is not set
++# CONFIG_X86_PCH9 is not set
++
++#
++# PHY Subsystem
++#
++CONFIG_PHY=y
++# CONFIG_NOP_PHY is not set
++# CONFIG_MIPI_DPHY_HELPERS is not set
++# CONFIG_BCM_SR_PCIE_PHY is not set
++# CONFIG_OMAP_USB2_PHY is not set
++CONFIG_PHY_MTK_TPHY=y
++
++#
++# Rockchip PHY driver
++#
++# CONFIG_PHY_CADENCE_SIERRA is not set
++# CONFIG_PHY_CADENCE_TORRENT is not set
++# CONFIG_MSM8916_USB_PHY is not set
++# CONFIG_MVEBU_COMPHY_SUPPORT is not set
++
++#
++# Pin controllers
++#
++CONFIG_PINCTRL=y
++CONFIG_PINCTRL_FULL=y
++CONFIG_PINCTRL_GENERIC=y
++CONFIG_PINMUX=y
++CONFIG_PINCONF=y
++CONFIG_PINCONF_RECURSIVE=y
++# CONFIG_PINCTRL_AT91 is not set
++# CONFIG_PINCTRL_AT91PIO4 is not set
++# CONFIG_PINCTRL_INTEL is not set
++# CONFIG_PINCTRL_QE is not set
++# CONFIG_PINCTRL_ROCKCHIP_RV1108 is not set
++# CONFIG_PINCTRL_SINGLE is not set
++# CONFIG_PINCTRL_STM32 is not set
++# CONFIG_PINCTRL_STMFX is not set
++# CONFIG_PINCTRL_K210 is not set
++CONFIG_PINCTRL_MTK=y
++# CONFIG_PINCTRL_MT7622 is not set
++# CONFIG_PINCTRL_MT7623 is not set
++# CONFIG_PINCTRL_MT7629 is not set
++CONFIG_PINCTRL_MT7981=y
++# CONFIG_PINCTRL_MT7986 is not set
++# CONFIG_PINCTRL_MT7988 is not set
++# CONFIG_PINCTRL_MT8512 is not set
++# CONFIG_PINCTRL_MT8516 is not set
++# CONFIG_PINCTRL_MT8518 is not set
++CONFIG_POWER=y
++# CONFIG_POWER_LEGACY is not set
++# CONFIG_ACPI_PMC is not set
++
++#
++# Power Domain Support
++#
++CONFIG_POWER_DOMAIN=y
++# CONFIG_APPLE_PMGR_POWER_DOMAIN is not set
++CONFIG_MTK_POWER_DOMAIN=y
++# CONFIG_DM_PMIC is not set
++# CONFIG_PMIC_TPS65217 is not set
++# CONFIG_POWER_TPS65218 is not set
++# CONFIG_POWER_TPS62362 is not set
++# CONFIG_DM_REGULATOR is not set
++# CONFIG_TPS6586X_POWER is not set
++# CONFIG_POWER_MT6323 is not set
++CONFIG_DM_PWM=y
++# CONFIG_PWM_ASPEED is not set
++# CONFIG_PWM_CADENCE_TTC is not set
++# CONFIG_PWM_CROS_EC is not set
++# CONFIG_PWM_EXYNOS is not set
++# CONFIG_PWM_IMX is not set
++# CONFIG_PWM_MESON is not set
++CONFIG_PWM_MTK=y
++# CONFIG_PWM_ROCKCHIP is not set
++# CONFIG_PWM_SANDBOX is not set
++# CONFIG_PWM_SIFIVE is not set
++# CONFIG_PWM_TEGRA is not set
++# CONFIG_PWM_SUNXI is not set
++# CONFIG_U_QE is not set
++# CONFIG_RAM is not set
++
++#
++# Reboot Mode Support
++#
++# CONFIG_DM_REBOOT_MODE is not set
++
++#
++# Remote Processor drivers
++#
++
++#
++# Reset Controller Support
++#
++# CONFIG_RESET_AST2500 is not set
++# CONFIG_RESET_AST2600 is not set
++CONFIG_RESET_MEDIATEK=y
++# CONFIG_RESET_HISILICON is not set
++# CONFIG_RESET_SYSCON is not set
++# CONFIG_RESET_SCMI is not set
++# CONFIG_RESET_DRA7 is not set
++# CONFIG_DM_RNG is not set
++
++#
++# Real Time Clock
++#
++# CONFIG_DM_RTC is not set
++# CONFIG_RTC_ENABLE_32KHZ_OUTPUT is not set
++# CONFIG_RTC_DS1337 is not set
++# CONFIG_RTC_DS1338 is not set
++# CONFIG_RTC_DS1374 is not set
++# CONFIG_RTC_DS3231 is not set
++# CONFIG_RTC_PCF8563 is not set
++# CONFIG_RTC_PT7C4338 is not set
++# CONFIG_RTC_PL031 is not set
++# CONFIG_RTC_S35392A is not set
++# CONFIG_RTC_MC13XXX is not set
++# CONFIG_RTC_MC146818 is not set
++# CONFIG_RTC_M41T62 is not set
++# CONFIG_SCSI is not set
++# CONFIG_DM_SCSI is not set
++CONFIG_SERIAL=y
++CONFIG_BAUDRATE=115200
++# CONFIG_DEFAULT_ENV_IS_RW is not set
++CONFIG_REQUIRE_SERIAL_CONSOLE=y
++# CONFIG_SPECIFY_CONSOLE_INDEX is not set
++CONFIG_SERIAL_PRESENT=y
++CONFIG_DM_SERIAL=y
++# CONFIG_SERIAL_RX_BUFFER is not set
++# CONFIG_SERIAL_PUTS is not set
++# CONFIG_SERIAL_SEARCH_ALL is not set
++# CONFIG_SERIAL_PROBE_ALL is not set
++# CONFIG_VPL_DM_SERIAL is not set
++CONFIG_DEBUG_UART_MTK=y
++CONFIG_DEBUG_UART_SHIFT=0
++# CONFIG_DEBUG_UART_ANNOUNCE is not set
++# CONFIG_DEBUG_UART_SKIP_INIT is not set
++# CONFIG_ALTERA_JTAG_UART is not set
++# CONFIG_ALTERA_UART is not set
++# CONFIG_ARC_SERIAL is not set
++# CONFIG_ARM_DCC is not set
++# CONFIG_ATMEL_USART is not set
++# CONFIG_BCM6345_SERIAL is not set
++# CONFIG_COREBOOT_SERIAL is not set
++# CONFIG_CORTINA_UART is not set
++# CONFIG_FSL_LINFLEXUART is not set
++# CONFIG_FSL_LPUART is not set
++# CONFIG_MVEBU_A3700_UART is not set
++# CONFIG_MCFUART is not set
++# CONFIG_NULLDEV_SERIAL is not set
++# CONFIG_SYS_NS16550 is not set
++# CONFIG_PL01X_SERIAL is not set
++# CONFIG_ROCKCHIP_SERIAL is not set
++# CONFIG_XILINX_UARTLITE is not set
++# CONFIG_MSM_SERIAL is not set
++# CONFIG_MSM_GENI_SERIAL is not set
++# CONFIG_MXS_AUART_SERIAL is not set
++# CONFIG_OMAP_SERIAL is not set
++# CONFIG_SIFIVE_SERIAL is not set
++# CONFIG_ZYNQ_SERIAL is not set
++CONFIG_MTK_SERIAL=y
++# CONFIG_MT7620_SERIAL is not set
++# CONFIG_NPCM_SERIAL is not set
++# CONFIG_SM is not set
++# CONFIG_MESON_SM is not set
++# CONFIG_SMEM is not set
++
++#
++# Sound support
++#
++# CONFIG_SOUND is not set
++
++#
++# SOC (System On Chip) specific Drivers
++#
++# CONFIG_SOC_DEVICE is not set
++# CONFIG_SOC_TI is not set
++CONFIG_SPI=y
++CONFIG_DM_SPI=y
++CONFIG_SPI_MEM=y
++# CONFIG_SPI_DIRMAP is not set
++# CONFIG_ALTERA_SPI is not set
++# CONFIG_APPLE_SPI is not set
++# CONFIG_ATCSPI200_SPI is not set
++# CONFIG_ATMEL_SPI is not set
++# CONFIG_BCMSTB_SPI is not set
++# CONFIG_CORTINA_SFLASH is not set
++# CONFIG_CADENCE_QSPI is not set
++# CONFIG_CF_SPI is not set
++# CONFIG_DESIGNWARE_SPI is not set
++# CONFIG_EXYNOS_SPI is not set
++# CONFIG_FSL_DSPI is not set
++# CONFIG_FSL_QSPI is not set
++# CONFIG_GXP_SPI is not set
++# CONFIG_ICH_SPI is not set
++# CONFIG_IPROC_QSPI is not set
++# CONFIG_KIRKWOOD_SPI is not set
++# CONFIG_MICROCHIP_COREQSPI is not set
++# CONFIG_MPC8XXX_SPI is not set
++# CONFIG_MTK_SNOR is not set
++# CONFIG_MTK_SNFI_SPI is not set
++CONFIG_MTK_SPIM=y
++# CONFIG_MVEBU_A3700_SPI is not set
++# CONFIG_MXS_SPI is not set
++# CONFIG_SPI_MXIC is not set
++# CONFIG_NPCM_FIU_SPI is not set
++# CONFIG_NPCM_PSPI is not set
++# CONFIG_NXP_FSPI is not set
++# CONFIG_OMAP3_SPI is not set
++# CONFIG_PL022_SPI is not set
++# CONFIG_ROCKCHIP_SFC is not set
++# CONFIG_ROCKCHIP_SPI is not set
++# CONFIG_SPI_ASPEED_SMC is not set
++# CONFIG_SPI_SIFIVE is not set
++# CONFIG_SOFT_SPI is not set
++# CONFIG_SPI_SN_F_OSPI is not set
++# CONFIG_SPI_SUNXI is not set
++# CONFIG_TEGRA114_SPI is not set
++# CONFIG_TEGRA20_SFLASH is not set
++# CONFIG_TEGRA20_SLINK is not set
++# CONFIG_TEGRA210_QSPI is not set
++# CONFIG_TI_QSPI is not set
++# CONFIG_XILINX_SPI is not set
++# CONFIG_ZYNQ_SPI is not set
++# CONFIG_ZYNQ_QSPI is not set
++# CONFIG_ZYNQMP_GQSPI is not set
++# CONFIG_SH_QSPI is not set
++# CONFIG_MXC_SPI is not set
++
++#
++# SPMI support
++#
++# CONFIG_SPMI is not set
++# CONFIG_SYSINFO is not set
++
++#
++# System reset device drivers
++#
++# CONFIG_SYSRESET is not set
++# CONFIG_TEE is not set
++# CONFIG_DM_THERMAL is not set
++
++#
++# Timer Support
++#
++# CONFIG_TIMER is not set
++
++#
++# TPM support
++#
++CONFIG_USB=y
++CONFIG_DM_USB=y
++# CONFIG_DM_USB_GADGET is not set
++
++#
++# USB Host Controller Drivers
++#
++CONFIG_USB_HOST=y
++CONFIG_USB_XHCI_HCD=y
++# CONFIG_USB_XHCI_DWC3 is not set
++# CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set
++CONFIG_USB_XHCI_MTK=y
++# CONFIG_USB_XHCI_FSL is not set
++# CONFIG_USB_XHCI_BRCM is not set
++# CONFIG_USB_EHCI_HCD is not set
++# CONFIG_USB_OHCI_HCD is not set
++# CONFIG_USB_UHCI_HCD is not set
++# CONFIG_USB_DWC2 is not set
++# CONFIG_USB_R8A66597_HCD is not set
++# CONFIG_USB_ISP1760 is not set
++# CONFIG_USB_CDNS3 is not set
++# CONFIG_USB_DWC3 is not set
++# CONFIG_USB_MTU3 is not set
++
++#
++# Legacy MUSB Support
++#
++# CONFIG_USB_MUSB_HCD is not set
++# CONFIG_USB_MUSB_UDC is not set
++
++#
++# MUSB Controller Driver
++#
++# CONFIG_USB_MUSB_HOST is not set
++# CONFIG_USB_MUSB_PIO_ONLY is not set
++
++#
++# USB Phy
++#
++# CONFIG_TWL4030_USB is not set
++# CONFIG_ROCKCHIP_USB2_PHY is not set
++
++#
++# ULPI drivers
++#
++
++#
++# USB peripherals
++#
++CONFIG_USB_STORAGE=y
++# CONFIG_USB_KEYBOARD is not set
++# CONFIG_USB_ONBOARD_HUB is not set
++CONFIG_USB_HUB_DEBOUNCE_TIMEOUT=1000
++# CONFIG_USB_HOST_ETHER is not set
++# CONFIG_USB_GADGET is not set
++# CONFIG_SPL_USB_GADGET is not set
++
++#
++# UFS Host Controller Support
++#
++# CONFIG_TI_J721E_UFS is not set
++
++#
++# Graphics support
++#
++# CONFIG_VIDEO is not set
++
++#
++# VirtIO Drivers
++#
++# CONFIG_VIRTIO_MMIO is not set
++
++#
++# 1-Wire support
++#
++# CONFIG_W1 is not set
++
++#
++# 1-wire EEPROM support
++#
++# CONFIG_W1_EEPROM is not set
++
++#
++# Watchdog Timer Support
++#
++# CONFIG_WATCHDOG is not set
++CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
++# CONFIG_IMX_WATCHDOG is not set
++# CONFIG_ULP_WATCHDOG is not set
++# CONFIG_WDT is not set
++# CONFIG_PHYS_TO_BUS is not set
++
++#
++# File systems
++#
++# CONFIG_FS_BTRFS is not set
++# CONFIG_FS_CBFS is not set
++# CONFIG_FS_EXT4 is not set
++CONFIG_FS_FAT=y
++CONFIG_FAT_WRITE=y
++CONFIG_FS_FAT_MAX_CLUSTSIZE=65536
++# CONFIG_FS_JFFS2 is not set
++CONFIG_UBIFS_SILENCE_MSG=y
++CONFIG_UBIFS_SILENCE_DEBUG_DUMP=y
++# CONFIG_FS_CRAMFS is not set
++# CONFIG_YAFFS2 is not set
++# CONFIG_FS_SQUASHFS is not set
++# CONFIG_FS_EROFS is not set
++
++#
++# Library routines
++#
++# CONFIG_ADDR_MAP is not set
++# CONFIG_SYS_TIMER_COUNTS_DOWN is not set
++# CONFIG_PHYSMEM is not set
++# CONFIG_BCH is not set
++# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
++CONFIG_CHARSET=y
++# CONFIG_DYNAMIC_CRC_TABLE is not set
++CONFIG_LIB_UUID=y
++# CONFIG_SEMIHOSTING is not set
++CONFIG_PRINTF=y
++CONFIG_SPRINTF=y
++CONFIG_STRTO=y
++CONFIG_SYS_HZ=1000
++# CONFIG_PANIC_HANG is not set
++CONFIG_REGEX=y
++CONFIG_LIB_RAND=y
++# CONFIG_LIB_HW_RAND is not set
++CONFIG_SUPPORT_ACPI=y
++# CONFIG_ACPI is not set
++CONFIG_RBTREE=y
++# CONFIG_BITREVERSE is not set
++# CONFIG_TRACE is not set
++# CONFIG_CIRCBUF is not set
++# CONFIG_CMD_DHRYSTONE is not set
++
++#
++# Security support
++#
++# CONFIG_AES is not set
++# CONFIG_ECDSA is not set
++# CONFIG_RSA is not set
++# CONFIG_TPM is not set
++
++#
++# Android Verified Boot
++#
++
++#
++# Hashing Support
++#
++# CONFIG_BLAKE2 is not set
++CONFIG_SHA1=y
++CONFIG_SHA256=y
++# CONFIG_SHA512 is not set
++# CONFIG_SHA384 is not set
++# CONFIG_SHA_HW_ACCEL is not set
++CONFIG_MD5=y
++CONFIG_CRC8=y
++CONFIG_CRC32=y
++
++#
++# Compression Support
++#
++# CONFIG_LZ4 is not set
++CONFIG_LZMA=y
++CONFIG_LZO=y
++CONFIG_GZIP=y
++# CONFIG_ZLIB_UNCOMPRESS is not set
++# CONFIG_BZIP2 is not set
++CONFIG_ZLIB=y
++# CONFIG_ZSTD is not set
++CONFIG_VPL_LZMA=y
++# CONFIG_SPL_GZIP is not set
++# CONFIG_ERRNO_STR is not set
++CONFIG_HEXDUMP=y
++# CONFIG_GETOPT is not set
++CONFIG_OF_LIBFDT=y
++CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
++CONFIG_SYS_FDT_PAD=0x3000
++
++#
++# System tables
++#
++CONFIG_GENERATE_SMBIOS_TABLE=y
++# CONFIG_LIB_RATIONAL is not set
++CONFIG_SMBIOS=y
++# CONFIG_SMBIOS_PARSER is not set
++CONFIG_EFI_LOADER=y
++CONFIG_CMD_BOOTEFI_BOOTMGR=y
++CONFIG_EFI_VARIABLE_FILE_STORE=y
++# CONFIG_EFI_VARIABLE_NO_STORE is not set
++# CONFIG_EFI_VARIABLES_PRESEED is not set
++CONFIG_EFI_VAR_BUF_SIZE=131072
++# CONFIG_EFI_SCROLL_ON_CLEAR_SCREEN is not set
++# CONFIG_EFI_RUNTIME_UPDATE_CAPSULE is not set
++CONFIG_EFI_CAPSULE_MAX=15
++CONFIG_EFI_DEVICE_PATH_TO_TEXT=y
++CONFIG_EFI_DEVICE_PATH_UTIL=y
++CONFIG_EFI_DT_FIXUP=y
++CONFIG_EFI_LOADER_HII=y
++CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y
++CONFIG_EFI_UNICODE_CAPITALIZATION=y
++# CONFIG_EFI_LOADER_BOUNCE_BUFFER is not set
++CONFIG_EFI_PLATFORM_LANG_CODES="en-US"
++CONFIG_EFI_HAVE_RUNTIME_RESET=y
++CONFIG_EFI_LOAD_FILE2_INITRD=y
++CONFIG_EFI_ECPT=y
++CONFIG_EFI_EBBR_2_1_CONFORMANCE=y
++# CONFIG_OPTEE_LIB is not set
++# CONFIG_OPTEE_IMAGE is not set
++# CONFIG_BOOTM_OPTEE is not set
++# CONFIG_TEST_FDTDEC is not set
++CONFIG_LIB_ELF=y
++CONFIG_LMB=y
++CONFIG_LMB_USE_MAX_REGIONS=y
++CONFIG_LMB_MAX_REGIONS=64
++# CONFIG_PHANDLE_CHECK_SEQ is not set
++
++#
++# Testing
++#
++# CONFIG_UNIT_TEST is not set
++# CONFIG_POST is not set
++
++#
++# Tools options
++#
++CONFIG_MKIMAGE_DTC_PATH="dtc"
++CONFIG_TOOLS_CRC32=y
++CONFIG_TOOLS_LIBCRYPTO=y
++CONFIG_TOOLS_FIT=y
++CONFIG_TOOLS_FIT_FULL_CHECK=y
++CONFIG_TOOLS_FIT_PRINT=y
++CONFIG_TOOLS_FIT_RSASSA_PSS=y
++CONFIG_TOOLS_FIT_SIGNATURE=y
++CONFIG_TOOLS_FIT_SIGNATURE_MAX_SIZE=0x10000000
++CONFIG_TOOLS_FIT_VERBOSE=y
++CONFIG_TOOLS_MD5=y
++CONFIG_TOOLS_OF_LIBFDT=y
++CONFIG_TOOLS_SHA1=y
++CONFIG_TOOLS_SHA256=y
++CONFIG_TOOLS_SHA384=y
++CONFIG_TOOLS_SHA512=y
++# CONFIG_TOOLS_MKEFICAPSULE is not set
++# CONFIG_FSPI_CONF_HEADER is not set
++# CONFIG_TOOLS_MKFWUMDATA is not set
+--- /dev/null
++++ b/openwrt-one-nor_env
+@@ -0,0 +1,46 @@
++bl2_mtd_write=mtd erase bl2-nor && mtd write bl2-nor $loadaddr 0x0 0x40000
++bl2_tftp_write=tftpboot $loadaddr $bootfile_bl2_nor && run bl2_mtd_write
++bootcmd=run check_button ; run led_start ; mtd read recovery ${loadaddr} ; bootm ; run led_loop_error
++bootconf=config-1
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-openwrt_one-initramfs.itb
++bootfile_bl2_nor=openwrt-mediatek-filogic-openwrt_one-nor-preloader.bin
++bootfile_fip_nor=openwrt-mediatek-filogic-openwrt_one-nor-bl31-uboot.fip
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run bootcmd
++bootmenu_1=Boot system via TFTP.=run tftp_boot ; run bootmenu_confirm_return
++bootmenu_2=\e[31mUnlock NOR. (Make sure the NOR/WP jumper is populated)\e[0m=sf probe 1:0 && sf protect unlock 0x0 0x1000000 ; run bootmenu_confirm_return
++bootmenu_3=\e[31mLoad BL31+U-Boot FIP via TFTP then write to NOR.\e[0m=run fip_tftp_write ; run bootmenu_confirm_return
++bootmenu_4=\e[31mLoad BL2 preloader via TFTP then write to NOR.\e[0m=run bl2_tftp_write ; run bootmenu_confirm_return
++bootmenu_5=\e[31mLoad recovery system via TFTP then write to NOR.\e[0m=run tftp_write ; run bootmenu_confirm_return
++bootmenu_6=\e[31mLock NOR. (Remove jumper afterwards)\e[0m=sf probe 1:0 && sf protect lock 0x0 0x1000000 ; run bootmenu_confirm_return
++bootmenu_7=Reboot.=reset
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title= \e[0;34m( ( ( \e[1;39mOpenWrt\e[0;34m ) ) ) \e[0;36m[SPI-NOR]\e[0m
++check_button=if button front ; then run usb_recovery ; run led_loop_error ; fi
++fip_mtd_write=mtd erase fip-nor && mtd write fip-nor $loadaddr
++fip_tftp_write=tftpboot $loadaddr $bootfile_fip_nor && run fip_mtd_write
++ipaddr=192.168.11.11
++led_done=led green off ; led white on
++led_loop_done=led white off ; led green on ; echo done ; while true ; do sleep 1 ; done
++led_loop_error=led white off ; led green off ; while true ; do led red on ; sleep 1 ; led red off ; sleep 1 ; done
++led_boot=led green on ; led white on ; led red on
++led_start=led green off ; led red off; led white on
++loadaddr=0x46000000
++preboot=run led_boot
++recoverfile_bl2=openwrt-mediatek-filogic-openwrt_one-snand-preloader.bin
++recoverfile_ubi=openwrt-mediatek-filogic-openwrt_one-factory.ubi
++recovery_write_bl2=mtd erase bl2 && for offset in 0x0 0x40000 0x80000; do mtd write bl2 $loadaddr $offset 0x40000 ; done
++recovery_write_ubi=mtd erase ubi && mtd write ubi $loadaddr 0 ${filesize}
++serverip=192.168.11.23
++tftp_boot=run led_start ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++tftp_write=run led_start ; tftpboot $loadaddr $bootfile && mtd erase recovery 0x0 ${filesize} && mtd write recovery $loadaddr 0x0 ${filesize}
++usb_recovery=run led_start ; usb start && run usb_recovery_bl2 && run usb_recovery_ubi && run led_loop_done
++usb_recovery_bl2=fatload usb 0:1 ${loadaddr} ${recoverfile_bl2} && run recovery_write_bl2
++usb_recovery_ubi=fatload usb 0:1 ${loadaddr} ${recoverfile_ubi} && run recovery_write_ubi
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title \e[33m$ver\e[0m"
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; bootmenu
++_init_env=setenv _init_env ; echo Initialize Env ; run ubi_create_env ; saveenv
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
+--- /dev/null
++++ b/openwrt-one-spi-nand_env
+@@ -0,0 +1,59 @@
++ipaddr=192.168.11.11
++serverip=192.168.11.23
++loadaddr=0x46000000
++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0
++bootcmd=run check_buttons ; run led_start ; run boot_calibration ; run boot_production ; run boot_recovery
++bootconf=config-1
++bootdelay=0
++bootfile=openwrt-mediatek-filogic-openwrt_one-initramfs.itb
++bootfile_bl2=openwrt-mediatek-filogic-openwrt_one-snand-preloader.bin
++bootfile_fip=openwrt-mediatek-filogic-openwrt_one-snand-bl31-uboot.fip
++bootfile_upg=openwrt-mediatek-filogic-openwrt_one-squashfs-sysupgrade.itb
++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; run led_boot ; bootmenu 60
++bootmenu_default=0
++bootmenu_delay=0
++bootmenu_title= \e[0;34m( ( ( \e[1;39mOpenWrt\e[0;34m ) ) ) \e[0;36m[SPI-NAND]\e[0m
++bootmenu_0=Initialize environment.=run _firstboot
++bootmenu_0d=Run default boot command.=run boot_default
++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return
++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return
++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return
++bootmenu_4=Load production system via TFTP then write to NAND.=noboot=1 ; replacevol=1 ; run boot_tftp_production ; noboot= ; replacevol= ; run bootmenu_confirm_return
++bootmenu_5=Load recovery system via TFTP then write to NAND.=noboot=1 ; replacevol=1 ; run boot_tftp_recovery ; noboot= ; replacevol= ; run bootmenu_confirm_return
++bootmenu_6=\e[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.\e[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return
++bootmenu_7=\e[31mLoad BL2 preloader via TFTP then write to NAND.\e[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return
++bootmenu_8=Reboot.=reset
++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset
++boot_default=run bootcmd ; run boot_recovery ; replacevol=1 ; run boot_tftp_forever
++boot_calibration=ubi read $loadaddr calibration && bootm $loadaddr#$bootconf
++boot_production=led white on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led white off
++boot_recovery=led green on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led green off
++boot_tftp=run led_start ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++boot_tftp_forever=led green off ; led white off ; led red on ; while true ; do run boot_tftp_recovery ; led red off ; sleep 1 ; done
++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && test $replacevol = 1 && iminfo $loadaddr && run ubi_write_production ; if test $noboot = 1 ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp_recovery=tftpboot $loadaddr $bootfile && test $replacevol = 1 && iminfo $loadaddr && run ubi_write_recovery ; if test $noboot = 1 ; then else bootm $loadaddr#$bootconf ; fi
++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf
++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory
++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2
++check_buttons=if button front ; then run boot_recovery ; run boot_tftp ; run led_loop_error ; else if button back ; then ; run usb_recover ; run led_loop_error ; fi ; fi
++led_boot=led green on ; led white on ; led red on
++led_done=led green on ; led white off ; led red off
++led_loop_error=led white off ; led green off ; while true ; do led red on ; sleep 1 ; led red off ; sleep 1 ; done
++led_start=led white on ; led green off ; led red off
++preboot=run led_boot
++reset_factory=mw $loadaddr 0xff 0x1f000 ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data
++snand_write_bl2=mtd erase bl2 && for offset in 0x0 0x40000 0x80000 0xc0000 ; do mtd write bl2 $loadaddr $offset 0x40000 ; done
++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x1f000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x1f000 dynamic
++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi
++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs
++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery
++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data
++usb_recover=run led_start ; usb start && run usb_recover_production && run led_loop_done
++usb_recover_production=fatload usb 0:1 ${loadaddr} ${bootfile_upg} && iminfo $loadaddr && run ubi_write_production
++ubi_write_fip=run ubi_remove_rootfs ; ubi check fip && ubi remove fip ; ubi create fip $filesize static && ubi write $loadaddr fip $filesize
++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize
++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize
++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv
++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; bootmenu
++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title
++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title \e[33m$ver\e[0m"
create mode 100644 configs/duckbill_defconfig
create mode 100644 include/configs/duckbill.h
-diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig
-index b90d7b6e41..e7d8bc6792 100644
--- a/arch/arm/mach-imx/mxs/Kconfig
+++ b/arch/arm/mach-imx/mxs/Kconfig
@@ -50,6 +50,10 @@ config TARGET_APX4DEVKIT
source "board/liebherr/xea/Kconfig"
source "board/ppcag/bg0900/Kconfig"
source "board/schulercontrol/sc_sps_1/Kconfig"
-diff --git a/board/i2se/duckbill/Kconfig b/board/i2se/duckbill/Kconfig
-new file mode 100644
-index 0000000000..98c1e4689f
--- /dev/null
+++ b/board/i2se/duckbill/Kconfig
@@ -0,0 +1,15 @@
+ default "duckbill"
+
+endif
-diff --git a/board/i2se/duckbill/MAINTAINERS b/board/i2se/duckbill/MAINTAINERS
-new file mode 100644
-index 0000000000..5496baa330
--- /dev/null
+++ b/board/i2se/duckbill/MAINTAINERS
@@ -0,0 +1,6 @@
+F: board/i2se/duckbill/
+F: include/configs/duckbill.h
+F: configs/duckbill_defconfig
-diff --git a/board/i2se/duckbill/Makefile b/board/i2se/duckbill/Makefile
-new file mode 100644
-index 0000000000..11bac98e4c
--- /dev/null
+++ b/board/i2se/duckbill/Makefile
@@ -0,0 +1,10 @@
+else
+obj-y := iomux.o
+endif
-diff --git a/board/i2se/duckbill/duckbill.c b/board/i2se/duckbill/duckbill.c
-new file mode 100644
-index 0000000000..93defc6c28
--- /dev/null
+++ b/board/i2se/duckbill/duckbill.c
@@ -0,0 +1,189 @@
+
+ return 0;
+}
-diff --git a/board/i2se/duckbill/iomux.c b/board/i2se/duckbill/iomux.c
-new file mode 100644
-index 0000000000..c6cc211181
--- /dev/null
+++ b/board/i2se/duckbill/iomux.c
@@ -0,0 +1,157 @@
+ else
+ mxs_iomux_setup_multiple_pads(iomux_setup_v1, ARRAY_SIZE(iomux_setup_v1));
+}
-diff --git a/configs/duckbill_defconfig b/configs/duckbill_defconfig
-new file mode 100644
-index 0000000000..b2d7fbcf77
--- /dev/null
+++ b/configs/duckbill_defconfig
@@ -0,0 +1,43 @@
+CONFIG_MII=y
+CONFIG_CONS_INDEX=0
+CONFIG_OF_LIBFDT=y
-diff --git a/include/configs/duckbill.h b/include/configs/duckbill.h
-new file mode 100644
-index 0000000000..565d8c58b7
--- /dev/null
+++ b/include/configs/duckbill.h
@@ -0,0 +1,172 @@
+#include <configs/mxs.h>
+
+#endif /* __CONFIGS_DUCKBILL_H__ */
---
-2.17.1
-
3 files changed, 60 insertions(+)
create mode 100644 board/sifive/unmatched/pwm.c
-diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile
-index 1345330089..5df01982e9 100644
--- a/board/sifive/unmatched/Makefile
+++ b/board/sifive/unmatched/Makefile
@@ -9,3 +9,4 @@ obj-y += spl.o
obj-y += unmatched.o
endif
+obj-y += pwm.o
-diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c
-new file mode 100644
-index 0000000000..e1cc02310a
--- /dev/null
+++ b/board/sifive/unmatched/pwm.c
@@ -0,0 +1,57 @@
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm1->cmp3);
+ writel(PWM_CFG_INIT, (void *)&pwm1->cfg);
+}
-diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
-index 7c0beedc08..f3a661a81e 100644
--- a/board/sifive/unmatched/spl.c
+++ b/board/sifive/unmatched/spl.c
@@ -90,6 +90,8 @@ int spl_board_init_f(void)
ret = spl_gemgxl_init();
if (ret) {
debug("Gigabit ethernet PHY (VSC8541) init failed: %d\n", ret);
---
-2.27.0
-
configs/sifive_unmatched_defconfig | 1 +
3 files changed, 14 insertions(+)
-diff --git a/board/sifive/unmatched/pwm.c b/board/sifive/unmatched/pwm.c
-index e1cc02310a..bd67672c22 100644
--- a/board/sifive/unmatched/pwm.c
+++ b/board/sifive/unmatched/pwm.c
@@ -36,6 +36,7 @@ void pwm_device_init(void)
+ writel(PWM_CMP_ENABLE_VAL, (void *)&pwm0->cmp3);
+#endif
}
-diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
-index 6295deeae2..30c082d001 100644
--- a/board/sifive/unmatched/unmatched.c
+++ b/board/sifive/unmatched/unmatched.c
@@ -22,6 +22,12 @@ void *board_fdt_blob_setup(int *err)
int board_init(void)
{
/* enable all cache ways */
-diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
-index d400ed0b23..0758f8e90f 100644
--- a/configs/sifive_unmatched_defconfig
+++ b/configs/sifive_unmatched_defconfig
-@@ -51,3 +51,4 @@ CONFIG_DM_SCSI=y
+@@ -62,3 +62,4 @@ CONFIG_DM_SCSI=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
+CONFIG_BOARD_EARLY_INIT_F=y
---
-2.27.0
-
Tested-by: Christian Stewart <christian@paral.in>
Reviewed-by: Rick Chen <rick@andestech.com>
-diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
-index 0b80eb8d86..53d1194ffb 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -24,7 +24,16 @@ ifeq ($(CONFIG_CMODEL_MEDANY),y)
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
-@@ -726,9 +726,14 @@ static int fit_handle_file(struct image_
+@@ -729,9 +729,14 @@ static int fit_handle_file(struct image_
}
*cmd = '\0';
} else if (params->datafile) {
--- a/tools/image-host.c
+++ b/tools/image-host.c
-@@ -1125,6 +1125,7 @@ static int fit_config_add_verification_d
+@@ -1122,6 +1122,7 @@ static int fit_config_add_verification_d
* 2) get public key (X509_get_pubkey)
* 3) provide der format (d2i_RSAPublicKey)
*/
static int read_pub_key(const char *keydir, const void *name,
unsigned char **pubkey, int *pubkey_len)
{
-@@ -1178,6 +1179,13 @@ err_cert:
+@@ -1175,6 +1176,13 @@ err_cert:
fclose(f);
return ret;
}
#
include $(TOPDIR)/rules.mk
-PKG_VERSION := 2020.04
-PKG_RELEASE:=3
+PKG_VERSION := 2024.04
+PKG_RELEASE:=1
-PKG_HASH := fe732aaf037d9cc3c0909bad8362af366ae964bbdac6913a34081ff4ad565372
+PKG_HASH := 18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a
PKG_MAINTAINER := Tomasz Maciej Nowak <tmn505@gmail.com>
+UBOOT_USE_INTREE_DTC:=1
+
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
)
endef
-define Build/Configure
- sed '/select BINMAN/d' -i $(PKG_BUILD_DIR)/arch/arm/mach-tegra/Kconfig
- $(call Build/Configure/U-Boot)
-endef
-
define Build/Compile
$(call Build/Compile/U-Boot)
$(call Build/bct-image)
scripts/dtc/dtc-lexer.l | 1 -
1 file changed, 1 deletion(-)
-diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
-index 5c6c3fd557d7f..b3b7270300de5 100644
--- a/scripts/dtc/dtc-lexer.l
+++ b/scripts/dtc/dtc-lexer.l
@@ -38,7 +38,6 @@ LINECOMMENT "//".*\n
--- /dev/null
+#
+# Copyright (C) 2022 Ye Jiaqiang, Tony Ambardar
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=ply
+PKG_RELEASE:=1
+
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_URL:=https://github.com/iovisor/ply.git
+PKG_MIRROR_HASH:=d4f434c4d11b662b61da2de8b5a29ecdeac655aa5158f4c4127e2a91047c0c54
+PKG_SOURCE_DATE:=2023-05-16
+PKG_SOURCE_VERSION:=1b57943db56692924bccb61c271de24a8264d8df
+
+PKG_LICENSE:=GPLv2
+PKG_LICENSE_FILES:=COPYING
+PKG_MAINTAINER:=Tony Ambardar <itugrok@yahoo.com>
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/ply
+ SECTION:=devel
+ CATEGORY:=Development
+ TITLE:=Light-weight dynamic tracer for Linux
+ URL:=https://github.com/iovisor/ply.git
+ DEPENDS:= \
+ @KERNEL_BPF_EVENTS @KERNEL_DYNAMIC_FTRACE @KERNEL_DEBUG_FS \
+ @mips||mipsel||mips64||mips64el||x86_64||powerpc||arm_v7||aarch64||riscv||riscv64
+endef
+
+define Package/ply/description
+ A light-weight dynamic tracer for Linux that leverages the kernel's
+ BPF VM in concert with kprobes and tracepoints to attach probes to
+ arbitrary points in the kernel.
+endef
+
+CONFIGURE_ARGS += --enable-shared=yes --enable-static=no
+
+define Build/Prepare
+ $(call Build/Prepare/Default)
+ cd $(PKG_BUILD_DIR) && exec ./autogen.sh
+endef
+
+define Package/ply/install
+ $(INSTALL_DIR) $(1)/usr/bin $(1)/usr/lib
+ $(INSTALL_BIN) $(PKG_BUILD_DIR)/src/ply/.libs/ply $(1)/usr/bin/
+ $(CP) $(PKG_BUILD_DIR)/src/libply/.libs/libply.so* $(1)/usr/lib/
+endef
+
+$(eval $(call BuildPackage,ply))
--- /dev/null
+From 755220eb974708615b14bcdc6412319698e0485d Mon Sep 17 00:00:00 2001
+From: Tony Ambardar <Tony.Ambardar@gmail.com>
+Date: Thu, 22 Dec 2022 22:53:10 -0800
+Subject: [PATCH] Revert "ply: Use new read_kernel variants"
+
+This reverts commit 17864b9818cceca09f31a346908afe1c718c10c5.
+
+Fixes: 17864b98 ("ply: Use new read_kernel variants")
+Signed-off-by: Tony Ambardar <Tony.Ambardar@gmail.com>
+---
+ src/libply/built-in/memory.c | 10 +++++-----
+ src/libply/ir.c | 10 +++++-----
+ src/libply/provider/tracepoint.c | 2 +-
+ 3 files changed, 11 insertions(+), 11 deletions(-)
+
+--- a/src/libply/built-in/memory.c
++++ b/src/libply/built-in/memory.c
+@@ -140,7 +140,7 @@ static int str_ir_post(const struct func
+ ir_emit_ldbp(pb->ir, BPF_REG_1, n->sym->irs.stack);
+ ir_emit_insn(ir, MOV_IMM((int32_t)type_sizeof(n->sym->type)), BPF_REG_2, 0);
+ ir_emit_sym_to_reg(ir, BPF_REG_3, ptr->sym);
+- ir_emit_insn(ir, CALL(BPF_FUNC_probe_read_kernel_str), 0, 0);
++ ir_emit_insn(ir, CALL(BPF_FUNC_probe_read_str), 0, 0);
+ return 0;
+ }
+
+@@ -305,7 +305,7 @@ static int struct_dot_ir_pre(const struc
+ sou->sym->irs.hint.dot = 1;
+
+ /* this also means we need to put ourselves on the
+- * stack since data will be loaded via probe_read_kernel */
++ * stack since data will be loaded via probe_read */
+ n->sym->irs.hint.stack = 1;
+ }
+ return 0;
+@@ -334,7 +334,7 @@ static int struct_dot_ir_post(const stru
+
+ ir_emit_sym_to_reg(pb->ir, BPF_REG_3, ptr->sym);
+ ir_emit_insn(pb->ir, ALU64_IMM(BPF_ADD, offset), BPF_REG_3, 0);
+- goto probe_read_kernel;
++ goto probe_read;
+ }
+
+ offset += sou->sym->irs.stack;
+@@ -346,10 +346,10 @@ static int struct_dot_ir_post(const stru
+ }
+
+ ir_emit_insn(pb->ir, ALU_IMM(BPF_ADD, offset), BPF_REG_3, 0);
+-probe_read_kernel:
++probe_read:
+ ir_emit_insn(pb->ir, MOV_IMM((int32_t)dst->size), BPF_REG_2, 0);
+ ir_emit_ldbp(pb->ir, BPF_REG_1, dst->stack);
+- ir_emit_insn(pb->ir, CALL(BPF_FUNC_probe_read_kernel), 0, 0);
++ ir_emit_insn(pb->ir, CALL(BPF_FUNC_probe_read), 0, 0);
+ /* TODO if (r0) exit(r0); */
+ return 0;
+ }
+--- a/src/libply/ir.c
++++ b/src/libply/ir.c
+@@ -38,10 +38,10 @@ static const char *bpf_func_name(enum bp
+ return "map_update_elem";
+ case BPF_FUNC_perf_event_output:
+ return "perf_event_output";
+- case BPF_FUNC_probe_read_kernel:
+- return "probe_read_kernel";
+- case BPF_FUNC_probe_read_kernel_str:
+- return "probe_read_kernel_str";
++ case BPF_FUNC_probe_read:
++ return "probe_read";
++ case BPF_FUNC_probe_read_str:
++ return "probe_read_str";
+ case BPF_FUNC_trace_printk:
+ return "trace_printk";
+ default:
+@@ -416,7 +416,7 @@ void ir_emit_read_to_sym(struct ir *ir,
+ if (src != BPF_REG_3)
+ ir_emit_insn(ir, MOV, BPF_REG_3, src);
+
+- ir_emit_insn(ir, CALL(BPF_FUNC_probe_read_kernel), 0, 0);
++ ir_emit_insn(ir, CALL(BPF_FUNC_probe_read), 0, 0);
+ /* TODO if (r0) exit(r0); */
+ }
+
+--- a/src/libply/provider/tracepoint.c
++++ b/src/libply/provider/tracepoint.c
+@@ -68,7 +68,7 @@ static int tracepoint_dyn_ir_post(const
+ ir_emit_insn(ir, ALU_IMM(BPF_AND, 0xffff), BPF_REG_4, 0);
+ ir_emit_insn(ir, ALU64(BPF_ADD), BPF_REG_3, BPF_REG_4);
+
+- ir_emit_insn(ir, CALL(BPF_FUNC_probe_read_kernel), 0, 0);
++ ir_emit_insn(ir, CALL(BPF_FUNC_probe_read), 0, 0);
+ return 0;
+ }
+
edimax_cax1800 \
linksys_mx4200 \
linksys_mx5300 \
+ linksys_mx8500 \
netgear_lbr20 \
netgear_rax120v2 \
+ netgear_sxk80 \
netgear_wax214 \
netgear_wax218 \
netgear_wax620 \
$(eval $(call generate-ipq-wifi-package,edimax_cax1800,Edimax CAX1800))
$(eval $(call generate-ipq-wifi-package,linksys_mx4200,Linksys MX4200))
$(eval $(call generate-ipq-wifi-package,linksys_mx5300,Linksys MX5300))
+$(eval $(call generate-ipq-wifi-package,linksys_mx8500,Linksys MX8500))
$(eval $(call generate-ipq-wifi-package,netgear_lbr20,Netgear LBR20))
$(eval $(call generate-ipq-wifi-package,netgear_rax120v2,Netgear RAX120v2))
+$(eval $(call generate-ipq-wifi-package,netgear_sxk80,Netgear SXK80))
$(eval $(call generate-ipq-wifi-package,netgear_wax214,Netgear WAX214))
$(eval $(call generate-ipq-wifi-package,netgear_wax218,Netgear WAX218))
$(eval $(call generate-ipq-wifi-package,netgear_wax620,Netgear WAX620))
include $(TOPDIR)/rules.mk
PKG_NAME:=fman-ucode
-PKG_VERSION:=lf-6.1.1-1.0.0
+PKG_VERSION:=6.6.3.1.0.0
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/nxp-qoriq/qoriq-fm-ucode
-PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0
-PKG_MIRROR_HASH:=d69792e0b03f2fd00cb9d69325d9817b43fb14dd1b27e41018b3ea69b25c55a5
+PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0
+PKG_MIRROR_HASH:=6bb9dd8ae0ac7b2ba0e5bc5e0590732167844a1b2c9316fbdcdd04e600785b0c
PKG_FLAGS:=nonshared
include $(TOPDIR)/rules.mk
PKG_NAME:=ls-ddr-phy
-PKG_VERSION:=21.08
-PKG_RELEASE:=3
+PKG_VERSION:=6.6.3.1.0.0
+PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/NXP/ddr-phy-binary.git
-PKG_SOURCE_VERSION:=LSDK-21.08
-PKG_MIRROR_HASH:=2f9bf4f6b2410e436e4e606f981c71919b1896e4da4f204de483d9f7677a064d
+PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0
+PKG_MIRROR_HASH:=7a1a35b3060adba875c507be3a5c800fa0c461103aaeb8eb0eab11f1f4b8139f
PKG_BUILD_DEPENDS:=tfa-layerscape/host
PKG_LICENSE:=EULA
include $(TOPDIR)/rules.mk
PKG_NAME:=ls-rcw
-PKG_VERSION:=lf-6.1.1-1.0.0
+PKG_VERSION:=6.6.3.1.0.0
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/nxp-qoriq/rcw
-PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0
-PKG_MIRROR_HASH:=6d505c1a60046a79c91b69cd6e26a2ef3515d7cb2999bdc9defcb664a1a5aef9
+PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0
+PKG_MIRROR_HASH:=da45ce99a0ff85375673fa8c05110c3bda36dedca4ac66190809328f79878a0a
PKG_FLAGS:=nonshared
include $(TOPDIR)/rules.mk
PKG_NAME:=ppfe
-PKG_VERSION:=lf-6.1.1-1.0.0
+PKG_VERSION:=6.6.3.1.0.0
PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/nxp-qoriq/qoriq-engine-pfe-bin
-PKG_SOURCE_VERSION:=lf-6.1.1-1.0.0
-PKG_MIRROR_HASH:=59f5660f1b93314e3e073053195719eab7361f07d1a9e02896f9356b1a615873
+PKG_SOURCE_VERSION:=lf-6.6.3-1.0.0
+PKG_MIRROR_HASH:=836da0d1ace6c5896c434940b5f06ae9ddcb871959e9f5aa3df75d67e39aec41
PKG_FLAGS:=nonshared
include $(TOPDIR)/rules.mk
PKG_NAME:=linux-firmware
-PKG_VERSION:=20240220
+PKG_VERSION:=20240513
PKG_RELEASE:=1
PKG_SOURCE_URL:=@KERNEL/linux/kernel/firmware
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
-PKG_HASH:=bf0f239dc0801e9d6bf5d5fb3e2f549575632cf4688f4348184199cb02c2bcd7
+PKG_HASH:=9f05edb99668135d37cedc4fdd18aac2802dc9e4566e086e6c6c2e321f3ecc4e
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
endef
$(eval $(call BuildPackage,rtl8723au-firmware))
+Package/rtl8723be-firmware = $(call Package/firmware-default,RealTek RTL8723BE firmware,,LICENCE.rtlwifi_firmware.txt)
+define Package/rtl8723be-firmware/install
+ $(INSTALL_DIR) $(1)/lib/firmware/rtlwifi
+ $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8723befw_36.bin $(1)/lib/firmware/rtlwifi
+ $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8723befw.bin $(1)/lib/firmware/rtlwifi
+endef
+$(eval $(call BuildPackage,rtl8723be-firmware))
+
Package/rtl8723bu-firmware = $(call Package/firmware-default,RealTek RTL8723BU firmware,,LICENCE.rtlwifi_firmware.txt)
define Package/rtl8723bu-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi
Package/rtl8821ae-firmware = $(call Package/firmware-default,RealTek RTL8821AE firmware,,LICENCE.rtlwifi_firmware.txt)
define Package/rtl8821ae-firmware/install
$(INSTALL_DIR) $(1)/lib/firmware/rtlwifi
- $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8821aefw.bin $(1)/lib/firmware/rtlwifi
+ $(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8821aefw_29.bin $(1)/lib/firmware/rtlwifi
$(INSTALL_DATA) $(PKG_BUILD_DIR)/rtlwifi/rtl8821aefw_wowlan.bin $(1)/lib/firmware/rtlwifi
endef
$(eval $(call BuildPackage,rtl8821ae-firmware))
include $(TOPDIR)/rules.mk
PKG_NAME:=wireless-regdb
-PKG_VERSION:=2024.01.23
+PKG_VERSION:=2024.05.08
PKG_RELEASE:=1
PKG_LICENSE:=ISC
PKG_LICENSE_FILES:=LICENSE
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@KERNEL/software/network/wireless-regdb/
-PKG_HASH:=c8a61c9acf76fa7eb4239e89f640dee3e87098d9f69b4d3518c9c60fc6d20c55
+PKG_HASH:=9aee1d86ebebb363b714bec941b2820f31e3b7f1a485ddc9fcbd9985c7d3e7c4
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
ioctl.c | 6 ++++++
1 file changed, 6 insertions(+)
-diff --git a/ioctl.c b/ioctl.c
-index 8f241b86..4262bbd5 100644
--- a/ioctl.c
+++ b/ioctl.c
-@@ -1246,7 +1246,9 @@ static struct ctl_table verbosity_ctl_root[] = {
+@@ -1246,7 +1246,9 @@ static struct ctl_table verbosity_ctl_ro
{
.procname = "ioctl",
.mode = 0555,
zc.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
-diff --git a/zc.c b/zc.c
-index fdf7da17..6637945a 100644
--- a/zc.c
+++ b/zc.c
-@@ -80,10 +80,14 @@ int __get_userbuf(uint8_t __user *addr, uint32_t len, int write,
+@@ -80,10 +80,14 @@ int __get_userbuf(uint8_t __user *addr,
ret = get_user_pages_remote(task, mm,
(unsigned long)addr, pgcount, write ? FOLL_WRITE : 0,
pg, NULL, NULL);
zc.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
-diff --git a/ioctl.c b/ioctl.c
-index 4262bbd..e3eefe1 100644
--- a/ioctl.c
+++ b/ioctl.c
-@@ -1246,7 +1246,7 @@ static struct ctl_table verbosity_ctl_root[] = {
+@@ -1246,7 +1246,7 @@ static struct ctl_table verbosity_ctl_ro
{
.procname = "ioctl",
.mode = 0555,
verbosity_sysctl_header = register_sysctl_table(verbosity_ctl_root);
#else
verbosity_sysctl_header = register_sysctl(verbosity_ctl_root->procname, verbosity_ctl_dir);
-diff --git a/zc.c b/zc.c
-index 6637945..00e00c1 100644
--- a/zc.c
+++ b/zc.c
-@@ -80,7 +80,7 @@ int __get_userbuf(uint8_t __user *addr, uint32_t len, int write,
+@@ -80,7 +80,7 @@ int __get_userbuf(uint8_t __user *addr,
ret = get_user_pages_remote(task, mm,
(unsigned long)addr, pgcount, write ? FOLL_WRITE : 0,
pg, NULL, NULL);
cryptlib.c | 4 ++++
1 file changed, 4 insertions(+)
-diff --git a/cryptlib.c b/cryptlib.c
-index 4d739e5..0e59d4c 100644
--- a/cryptlib.c
+++ b/cryptlib.c
-@@ -381,7 +381,11 @@ int cryptodev_hash_init(struct hash_data *hdata, const char *alg_name,
+@@ -381,7 +381,11 @@ int cryptodev_hash_init(struct hash_data
}
hdata->digestsize = crypto_ahash_digestsize(hdata->async.s);
#if defined(ENABLE_FW_PROC) && ENABLE_FW_PROC
static int proc_read_genconf(char *, char **, off_t, int, int *, void *);
#endif
-@@ -889,6 +891,7 @@ static INLINE void proc_file_delete(void
+@@ -896,6 +898,7 @@ static INLINE void proc_file_delete(void
remove_proc_entry("driver/ifx_ptm", NULL);
}
static int proc_read_version(char *buf, char **start, off_t offset, int count, int *eof, void *data)
{
int len = 0;
-@@ -963,8 +966,9 @@ static int proc_write_wanmib(struct file
+@@ -970,8 +973,9 @@ static int proc_write_wanmib(struct file
return count;
}
static INLINE int strincmp(const char *, const char *, int);
#endif
static INLINE int ifx_ptm_version(char *);
-@@ -1159,8 +1159,6 @@ static int proc_write_dbg(struct file *f
+@@ -1166,8 +1166,6 @@ static int proc_write_dbg(struct file *f
return count;
}
static INLINE int stricmp(const char *p1, const char *p2)
{
int c1, c2;
-@@ -1178,7 +1176,6 @@ static INLINE int stricmp(const char *p1
+@@ -1185,7 +1183,6 @@ static INLINE int stricmp(const char *p1
return *p1 - *p2;
}
--- a/src/drv_tapi_cid.c
+++ b/src/drv_tapi_cid.c
-@@ -1424,6 +1424,8 @@ static IFX_int32_t cid_lookup_transparent(TAPI_CIDTX_DATA_t *pTxData,
+@@ -1424,6 +1424,8 @@ static IFX_int32_t cid_lookup_transparen
cidfsk_set_tx_time (pTxData, &pConfData->TapiCidFskConf);
case IFX_TAPI_CID_GEN_TYPE_DTMF:
memcpy (pTxData->cidBuf[IFX_TAPI_CID_GEN_TYPE_DTMF].pBuf,
pMessage[0].transparent.data, pMessage[0].transparent.len);
-@@ -1497,6 +1499,7 @@ static IFX_int32_t cid_prepare_data(TAPI_CHANNEL *pChannel,
+@@ -1497,6 +1499,7 @@ static IFX_int32_t cid_prepare_data(TAPI
break;
case IFX_TAPI_CID_STD_KPN_DTMF:
/*lint -fallthrough*/
case IFX_TAPI_CID_STD_KPN_DTMF_FSK:
if (IFX_TAPI_CID_HM_ONHOOK == pTxData->txHookMode)
{
-@@ -1506,6 +1509,7 @@ static IFX_int32_t cid_prepare_data(TAPI_CHANNEL *pChannel,
+@@ -1506,6 +1509,7 @@ static IFX_int32_t cid_prepare_data(TAPI
}
/* KPN CID Type 2 (off-hook) always using FSK */
/*lint -fallthrough*/
default:
pTxData->cidGenType = IFX_TAPI_CID_GEN_TYPE_FSK;
break;
-@@ -1532,6 +1536,7 @@ static IFX_int32_t cid_prepare_data(TAPI_CHANNEL *pChannel,
+@@ -1532,6 +1536,7 @@ static IFX_int32_t cid_prepare_data(TAPI
break;
/*lint -fallthrough*/
case IFX_TAPI_CID_GEN_TYPE_FSK:
if (IFX_TAPI_CID_STD_NTT == pConfData->nStandard)
-@@ -2036,6 +2041,7 @@ static FSM_STATUS_t cid_fsm_alert_exec(TAPI_CHANNEL *pChannel)
+@@ -2036,6 +2041,7 @@ static FSM_STATUS_t cid_fsm_alert_exec(T
}
pTxData->nCidSubState++;
/*lint -fallthrough*/
case 1:
if (pConfData->OSIoffhook && pConfData->nSAStone)
{
-@@ -2052,6 +2058,7 @@ static FSM_STATUS_t cid_fsm_alert_exec(TAPI_CHANNEL *pChannel)
+@@ -2052,6 +2058,7 @@ static FSM_STATUS_t cid_fsm_alert_exec(T
}
pTxData->nCidSubState++;
/*lint -fallthrough*/
case 2:
if (pConfData->nSAStone)
{
-@@ -2069,6 +2076,7 @@ static FSM_STATUS_t cid_fsm_alert_exec(TAPI_CHANNEL *pChannel)
+@@ -2069,6 +2076,7 @@ static FSM_STATUS_t cid_fsm_alert_exec(T
}
pTxData->nCidSubState++;
/*lint -fallthrough*/
default:
/* Play CAS tone on data channel, use unprotected function, protection
is done around cid_fsm_alert_exec */
-@@ -3458,6 +3466,7 @@ IFX_int32_t TAPI_Phone_CID_Stop_Tx(TAPI_CHANNEL *pChannel)
+@@ -3458,6 +3466,7 @@ IFX_int32_t TAPI_Phone_CID_Stop_Tx(TAPI_
}
/* deliberately fall through */
/*lint -fallthrough*/
case TAPI_CID_STATE_ACK:
/* deactivate the DTMF override - last two params are ignored */
if (ptr_chk(pDrvCtx->SIG.DTMFD_Override, ""))
-@@ -3469,6 +3478,7 @@ IFX_int32_t TAPI_Phone_CID_Stop_Tx(TAPI_CHANNEL *pChannel)
+@@ -3469,6 +3478,7 @@ IFX_int32_t TAPI_Phone_CID_Stop_Tx(TAPI_
}
/* deliberately fall through */
/*lint -fallthrough*/
case TAPI_CID_STATE_SENDING:
TAPI_Stop_Timer (pTxData->CidTimerID);
break;
-@@ -4066,6 +4076,7 @@ IFX_int32_t TAPI_Phone_Get_CidRxData (TAPI_CHANNEL *pChannel,
+@@ -4066,6 +4076,7 @@ IFX_int32_t TAPI_Phone_Get_CidRxData (TA
/* If the fifo is not empty take the data from the fifo first. */
/* deliberately fallthrough to default case */
/*lint -fallthrough*/
When there is no data in the fifo TAPI_statusErr is returned. */
--- a/src/drv_tapi_dial.c
+++ b/src/drv_tapi_dial.c
-@@ -319,6 +319,8 @@ static IFX_void_t ifx_tapi_dial_OnTimer(Timer_ID Timer, IFX_ulong_t nArg)
+@@ -319,6 +319,8 @@ static IFX_void_t ifx_tapi_dial_OnTimer(
/* NOTE: the "break" statement has been intentionally omitted */
/*lint -fallthrough */
certain low pulse (not noise). The next state is the overlap with
--- a/src/drv_tapi_event.c
+++ b/src/drv_tapi_event.c
-@@ -1545,6 +1545,7 @@ IFX_int32_t IFX_TAPI_Event_Dispatch_ProcessCtx(IFX_TAPI_EXT_EVENT_PARAM_t*
+@@ -1545,6 +1545,7 @@ IFX_int32_t IFX_TAPI_Event_Dispatch_Proc
/**\todo put in device fifo */
pEvent->ch = IFX_TAPI_DEVICE_CH_NUMBER;
/*lint -fallthrough */
break;
--- a/src/drv_tapi_ioctl.c
+++ b/src/drv_tapi_ioctl.c
-@@ -1552,6 +1553,7 @@ static IFX_int32_t TAPI_IoctlCh (IFX_TAPI_DRV_CTX_t* pDrvCtx,
+@@ -1552,6 +1552,7 @@ static IFX_int32_t TAPI_IoctlCh (IFX_TA
/* Dial Services */
ret = TAPI_statusNotSupported;
/*lint -fallthrough*/
--- a/src/drv_tapi_ioctl.c
+++ b/src/drv_tapi_ioctl.c
-@@ -702,7 +702,8 @@ static IFX_int32_t TAPI_IoctlDev (IFX_TAPI_DRV_CTX_t* pDrvCtx,
+@@ -702,7 +702,8 @@ static IFX_int32_t TAPI_IoctlDev (IFX_TA
if (ret == TAPI_statusOk || ret == 1)
{
#ifdef INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS
--- a/src/common/drv_dsl_cpe_api.c
+++ b/src/common/drv_dsl_cpe_api.c
-@@ -2652,6 +2652,8 @@ DSL_Error_t DSL_DRV_AutobootControlSet(
+@@ -2653,6 +2653,8 @@ DSL_Error_t DSL_DRV_AutobootControlSet(
/* no break */
/* ... pass to restart*/
+ fallthrough;
case DSL_PM_RESET_HISTORY_SHOWTIME:
#ifdef INCLUDE_DSL_CPE_PM_SHOWTIME_COUNTERS
- nErrCode = DSL_DRV_PM_HistoryDelete(pContext, EpData.pHistShowtime );
\ No newline at end of file
+ nErrCode = DSL_DRV_PM_HistoryDelete(pContext, EpData.pHistShowtime );
--- a/src/common/drv_dsl_cpe_os_linux.c
+++ b/src/common/drv_dsl_cpe_os_linux.c
-@@ -54,7 +54,7 @@ static int DSL_DRV_Release(DSL_DRV_inode_t * ino, DSL_DRV_file_t * fil);
+@@ -54,7 +54,7 @@ static int DSL_DRV_Release(DSL_DRV_inode
static DSL_uint_t DSL_DRV_Poll(DSL_DRV_file_t *pFile, DSL_DRV_Poll_Table_t *wait);
static void DSL_DRV_NlSendMsg(DSL_char_t* pMsg);
#endif
-@@ -368,10 +368,10 @@ int DSL_DRV_debug_printf(DSL_Context_t const *pContext, DSL_char_t const *fmt, .
+@@ -368,10 +368,10 @@ int DSL_DRV_debug_printf(DSL_Context_t c
{
DSL_int_t nRet = 0;
#ifndef _lint
DSL_char_t debugString[DSL_DBG_MAX_DEBUG_PRINT_CHAR + 1] = {0};
va_list ap; /* points to each unnamed arg in turn */
-@@ -406,6 +406,8 @@ int DSL_DRV_debug_printf(DSL_Context_t const *pContext, DSL_char_t const *fmt, .
+@@ -406,6 +406,8 @@ int DSL_DRV_debug_printf(DSL_Context_t c
#endif /* DSL_DEBUG_DISABLE */
return nRet;
#else
--- a/src/device/drv_dsl_cpe_msg_vrx.c
+++ b/src/device/drv_dsl_cpe_msg_vrx.c
-@@ -2456,32 +2456,32 @@ DSL_Error_t DSL_DRV_VRX_SendMsgSnrPerGroupesGet(
+@@ -2456,32 +2456,32 @@ DSL_Error_t DSL_DRV_VRX_SendMsgSnrPerGro
#endif /* defined(INCLUDE_DSL_G997_PER_TONE) || defined(INCLUDE_DSL_DELT)*/
#ifdef INCLUDE_DSL_DELT
- memcpy(pDst,pSrc,valueSize);
- }
- }
--
-- return DSL_SUCCESS;
--}
+// static DSL_Error_t DSL_DRV_VRX_SpreadArray(
+// DSL_void_t* pArray,
+// DSL_uint16_t valueSize,
+// memcpy(pDst,pSrc,valueSize);
+// }
+// }
-+
+
+- return DSL_SUCCESS;
+-}
+// return DSL_SUCCESS;
+// }
This function requests a set of up to 60 entries of the DELT data.
--- a/src/device/drv_dsl_cpe_device_vrx.c
+++ b/src/device/drv_dsl_cpe_device_vrx.c
-@@ -3356,7 +3356,9 @@ static DSL_Error_t DSL_DRV_VRX_TestParametersFeUpdate(
+@@ -3356,7 +3356,9 @@ static DSL_Error_t DSL_DRV_VRX_TestParam
DSL_Error_t nErrCode = DSL_SUCCESS;
DSL_uint16_t i = 0;
DSL_uint16_t nDataLen = 0;
DSL_DEBUG( DSL_DBG_MSG,
(pContext, SYS_DBG_MSG"DSL[%02d]: IN - DSL_DRV_VRX_TestParametersFeUpdate"
-@@ -8312,6 +8314,7 @@ DSL_Error_t DSL_DRV_DEV_AutobootHandleTraining(
+@@ -8312,6 +8314,7 @@ DSL_Error_t DSL_DRV_DEV_AutobootHandleTr
(pContext, SYS_DBG_MSG"DSL[%02d]: ORDERLY_SHUTDOWN state reached"
DSL_DRV_CRLF, DSL_DEV_NUM(pContext)));
/* do not use break here, continue handling */
--- a/src/vectoring/ifxmips_vectoring.c
+++ b/src/vectoring/ifxmips_vectoring.c
-@@ -298,7 +298,7 @@ static int proc_write_dbg(struct file *file, const char __user *buf, size_t coun
+@@ -298,7 +298,7 @@ static int proc_write_dbg(struct file *f
DBG_ENABLE_MASK_ALL
};
char *p;
int len, rlen;
-@@ -306,6 +306,10 @@ static int proc_write_dbg(struct file *file, const char __user *buf, size_t coun
+@@ -306,6 +306,10 @@ static int proc_write_dbg(struct file *f
int f_enable = 0;
int i;
len = count < sizeof(str) ? count : sizeof(str) - 1;
rlen = len - copy_from_user(str, buf, len);
while ( rlen && str[rlen - 1] <= ' ' )
-@@ -365,6 +369,8 @@ static int proc_write_dbg(struct file *file, const char __user *buf, size_t coun
+@@ -365,6 +369,8 @@ static int proc_write_dbg(struct file *f
}
}
#include "ifxmips_vectoring_stub.h"
-@@ -46,13 +47,17 @@ static int proc_write_vectoring(struct file *file, const char __user *buf, size_
+@@ -46,13 +47,17 @@ static int proc_write_vectoring(struct f
{
char *p;
int len;
len = sizeof(local_buf) < count ? sizeof(local_buf) - 1 : count;
len = len - copy_from_user(local_buf, buf, len);
local_buf[len] = 0;
-@@ -81,6 +86,8 @@ static int proc_write_vectoring(struct file *file, const char __user *buf, size_
+@@ -81,6 +86,8 @@ static int proc_write_vectoring(struct f
else
printk("echo send <size> > /proc/driver/vectoring_test\n");
define KernelPackage/can-usb-esd
TITLE:=ESD USB/2 CAN/USB interface
- KCONFIG:=CONFIG_CAN_ESD_USB2
- FILES:=$(LINUX_DIR)/drivers/net/can/usb/esd_usb2.ko
- AUTOLOAD:=$(call AutoProbe,esd_usb2)
+ KCONFIG:= \
+ CONFIG_CAN_ESD_USB2@lt6.0 \
+ CONFIG_CAN_ESD_USB@ge6.0
+ FILES:= \
+ $(LINUX_DIR)/drivers/net/can/usb/esd_usb2.ko@lt6.0 \
+ $(LINUX_DIR)/drivers/net/can/usb/esd_usb.ko@ge6.0
+ AUTOLOAD:=$(call AutoProbe,esd_usb2 esd_usb)
$(call AddDepends/can,+kmod-usb-core)
endef
KCONFIG:= \
CONFIG_CRYPTO_HW=y \
CONFIG_CRYPTO_DEV_IXP4XX
- FILES:=$(LINUX_DIR)/drivers/crypto/ixp4xx_crypto.ko
+ FILES:=$(LINUX_DIR)/drivers/crypto/intel/ixp4xx/ixp4xx_crypto.ko
AUTOLOAD:=$(call AutoProbe,ixp4xx_crypto)
$(call AddDepends/crypto)
endef
$(eval $(call KernelPackage,i2c-i801))
+I2C_MLXCPLD_MODULES:= \
+ CONFIG_I2C_MLXCPLD:drivers/i2c/busses/i2c-mlxcpld
+
+define KernelPackage/i2c-mlxcpld
+ $(call i2c_defaults,$(I2C_MLXCPLD_MODULES),59)
+ TITLE:=Mellanox I2C driver
+ DEPENDS:=@TARGET_x86_64 +kmod-regmap-core
+endef
+
+define KernelPackage/i2c-mlxcpld/description
+ This exposes the Mellanox platform I2C busses
+ to the linux I2C layer for X86 based systems.
+ Controller is implemented as CPLD logic.
+endef
+
+$(eval $(call KernelPackage,i2c-mlxcpld))
+
+
I2C_MUX_MODULES:= \
CONFIG_I2C_MUX:drivers/i2c/i2c-mux
$(eval $(call KernelPackage,i2c-mux-gpio))
+I2C_MUX_MLXCPLD_MODULES:= \
+ CONFIG_I2C_MUX_MLXCPLD:drivers/i2c/muxes/i2c-mux-mlxcpld
+
+define KernelPackage/i2c-mux-mlxcpld
+ $(call i2c_defaults,$(I2C_MUX_MLXCPLD_MODULES),51)
+ TITLE:=Mellanox CPLD based I2C multiplexer
+ DEPENDS:=+kmod-i2c-mlxcpld +kmod-i2c-mux
+endef
+
+define KernelPackage/i2c-mux-mlxcpld/description
+ This driver provides access to
+ I2C busses connected through a MUX, which is controlled
+ by a CPLD register.
+endef
+
+$(eval $(call KernelPackage,i2c-mux-mlxcpld))
+
+
I2C_MUX_REG_MODULES:= \
CONFIG_I2C_MUX_REG:drivers/i2c/muxes/i2c-mux-reg
KCONFIG:=$(KCONFIG_IPT_CLUSTERIP)
FILES:=$(foreach mod,$(IPT_CLUSTERIP-m),$(LINUX_DIR)/net/$(mod).ko)
AUTOLOAD:=$(call AutoProbe,$(notdir $(IPT_CLUSTERIP-m)))
- $(call AddDepends/ipt,+kmod-nf-conntrack)
+ $(call AddDepends/ipt,+kmod-nf-conntrack @LINUX_5_15||LINUX_6_1)
endef
define KernelPackage/ipt-clusterip/description
$(eval $(call KernelPackage,lkdtm))
+define KernelPackage/mlx_wdt
+ SUBMENU:=$(OTHER_MENU)
+ TITLE:=Mellanox Watchdog
+ DEPENDS:=@TARGET_x86 +kmod-regmap-core
+ KCONFIG:= \
+ CONFIG_MELLANOX_PLATFORM=y \
+ CONFIG_MLX_WDT
+ FILES:=$(LINUX_DIR)/drivers/watchdog/mlx_wdt.ko
+ AUTOLOAD:=$(call AutoProbe,mlx_wdt)
+endef
+
+define KernelPackage/mlx_wdt/description
+ This is the driver for the hardware watchdog on Mellanox systems.
+ This driver can be used together with the watchdog daemon.
+ It can also watch your kernel to make sure it doesn't freeze,
+ and if it does, it reboots your system after a certain amount of
+ time.
+endef
+
+$(eval $(call KernelPackage,mlx_wdt))
+
+
+define KernelPackage/mlxreg
+ SUBMENU:=$(OTHER_MENU)
+ TITLE:=Mellanox platform register access
+ DEPENDS:=@TARGET_x86 +kmod-i2c-mux-mlxcpld
+ KCONFIG:= \
+ CONFIG_MELLANOX_PLATFORM=y \
+ CONFIG_MLX_PLATFORM \
+ CONFIG_MLXREG_HOTPLUG \
+ CONFIG_MLXREG_IO \
+ CONFIG_SENSORS_MLXREG_FAN \
+ CONFIG_LEDS_MLXREG
+ FILES:= \
+ $(LINUX_DIR)/drivers/platform/x86/mlx-platform.ko \
+ $(LINUX_DIR)/drivers/platform/mellanox/mlxreg-hotplug.ko \
+ $(LINUX_DIR)/drivers/platform/mellanox/mlxreg-io.ko \
+ $(LINUX_DIR)/drivers/hwmon/mlxreg-fan.ko \
+ $(LINUX_DIR)/drivers/leds/leds-mlxreg.ko
+ AUTOLOAD:=$(call AutoProbe,mlx-platform mlxreg-hotplug mlxreg-io mlxreg-fan leds-mlxreg)
+endef
+
+define KernelPackage/mlxreg/description
+ Allows access to Mellanox programmable device register
+ space through sysfs interface. The sets of registers for sysfs access
+ are defined per system type bases and include the registers related
+ to system resets operation, system reset causes monitoring and some
+ kinds of mux selection.
+endef
+
+$(eval $(call KernelPackage,mlxreg))
+
+
+define KernelPackage/mlxreg-lc
+ SUBMENU:=$(OTHER_MENU)
+ TITLE:=Mellanox line card platform support
+ DEPENDS:=kmod-mlxreg +kmod-regmap-i2c
+ KCONFIG:=CONFIG_MLXREG_LC
+ FILES:=$(LINUX_DIR)/drivers/platform/mellanox/mlxreg-lc.ko
+ AUTOLOAD:=$(call AutoProbe,mlxreg-lc)
+endef
+
+define KernelPackage/mlxreg-lc/description
+ Provides support for the Mellanox MSN4800-XX line cards,
+ which are the part of MSN4800 Ethernet modular switch systems.
+endef
+
+$(eval $(call KernelPackage,mlxreg-lc))
+
+
+define KernelPackage/mlxreg-sn2201
+ SUBMENU:=$(OTHER_MENU)
+ TITLE:=Nvidia SN2201 platform support
+ DEPENDS:=kmod-mlxreg +kmod-regmap-i2c
+ KCONFIG:=CONFIG_NVSW_SN2201
+ FILES:=$(LINUX_DIR)/drivers/platform/mellanox/nvsw-sn2201.ko
+ AUTOLOAD:=$(call AutoProbe,nvsw-sn2201)
+endef
+
+define KernelPackage/mlxreg-sn2201/description
+ Provides support for the Nvidia SN2201 platform.
+endef
+
+$(eval $(call KernelPackage,mlxreg-sn2201))
+
+
define KernelPackage/pinctrl-mcp23s08
SUBMENU:=$(OTHER_MENU)
TITLE:=Microchip MCP23xxx I/O expander
$(eval $(call KernelPackage,bcma))
-define KernelPackage/rtc-ds1307
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Dallas/Maxim DS1307 (and compatible) RTC support
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-i2c-core +kmod-regmap-i2c +kmod-hwmon-core
- KCONFIG:=CONFIG_RTC_DRV_DS1307 \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-ds1307.ko
- AUTOLOAD:=$(call AutoProbe,rtc-ds1307)
-endef
-
-define KernelPackage/rtc-ds1307/description
- Kernel module for Dallas/Maxim DS1307/DS1337/DS1338/DS1340/DS1388/DS3231,
- Epson RX-8025 and various other compatible RTC chips connected via I2C.
-endef
-
-$(eval $(call KernelPackage,rtc-ds1307))
-
-
-define KernelPackage/rtc-ds1374
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Dallas/Maxim DS1374 RTC support
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-i2c-core
- KCONFIG:=CONFIG_RTC_DRV_DS1374 \
- CONFIG_RTC_DRV_DS1374_WDT=n \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-ds1374.ko
- AUTOLOAD:=$(call AutoProbe,rtc-ds1374)
-endef
-
-define KernelPackage/rtc-ds1374/description
- Kernel module for Dallas/Maxim DS1374.
-endef
-
-$(eval $(call KernelPackage,rtc-ds1374))
-
-
-define KernelPackage/rtc-ds1672
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Dallas/Maxim DS1672 RTC support
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-i2c-core
- KCONFIG:=CONFIG_RTC_DRV_DS1672 \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-ds1672.ko
- AUTOLOAD:=$(call AutoProbe,rtc-ds1672)
-endef
-
-define KernelPackage/rtc-ds1672/description
- Kernel module for Dallas/Maxim DS1672 RTC.
-endef
-
-$(eval $(call KernelPackage,rtc-ds1672))
-
-
-define KernelPackage/rtc-em3027
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Microelectronic EM3027 RTC support
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-i2c-core
- KCONFIG:=CONFIG_RTC_DRV_EM3027 \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-em3027.ko
- AUTOLOAD:=$(call AutoProbe,rtc-em3027)
-endef
-
-define KernelPackage/rtc-em3027/description
- Kernel module for Microelectronic EM3027 RTC.
-endef
-
-$(eval $(call KernelPackage,rtc-em3027))
-
-
-define KernelPackage/rtc-isl1208
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Intersil ISL1208 RTC support
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-i2c-core
- KCONFIG:=CONFIG_RTC_DRV_ISL1208 \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-isl1208.ko
- AUTOLOAD:=$(call AutoProbe,rtc-isl1208)
-endef
-
-define KernelPackage/rtc-isl1208/description
- Kernel module for Intersil ISL1208 RTC.
-endef
-
-$(eval $(call KernelPackage,rtc-isl1208))
-
-
-define KernelPackage/rtc-mv
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Marvell SoC RTC support
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- KCONFIG:=CONFIG_RTC_DRV_MV \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-mv.ko
- AUTOLOAD:=$(call AutoProbe,rtc-mv)
-endef
-
-define KernelPackage/rtc-mv/description
- Kernel module for Marvell SoC RTC.
-endef
-
-$(eval $(call KernelPackage,rtc-mv))
-
-
-define KernelPackage/rtc-pcf8563
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Philips PCF8563/Epson RTC8564 RTC support
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-i2c-core
- KCONFIG:=CONFIG_RTC_DRV_PCF8563 \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-pcf8563.ko
- AUTOLOAD:=$(call AutoProbe,rtc-pcf8563)
-endef
-
-define KernelPackage/rtc-pcf8563/description
- Kernel module for Philips PCF8563 RTC chip.
- The Epson RTC8564 should work as well.
-endef
-
-$(eval $(call KernelPackage,rtc-pcf8563))
-
-
-define KernelPackage/rtc-pcf2123
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Philips PCF2123 RTC support
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-regmap-spi
- KCONFIG:=CONFIG_RTC_DRV_PCF2123 \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-pcf2123.ko
- AUTOLOAD:=$(call AutoProbe,rtc-pcf2123)
-endef
-
-define KernelPackage/rtc-pcf2123/description
- Kernel module for Philips PCF2123 RTC chip
-endef
-
-$(eval $(call KernelPackage,rtc-pcf2123))
-
-define KernelPackage/rtc-pcf2127
- SUBMENU:=$(OTHER_MENU)
- TITLE:=NXP PCF2127 and PCF2129 RTC support
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-i2c-core +kmod-regmap-spi
- KCONFIG:=CONFIG_RTC_DRV_PCF2127 \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-pcf2127.ko
- AUTOLOAD:=$(call AutoProbe,rtc-pcf2127)
-endef
-
-define KernelPackage/rtc-pcf2127/description
- Kernel module for NXP PCF2127 and PCF2129 RTC chip
-endef
-
-$(eval $(call KernelPackage,rtc-pcf2127))
-
-define KernelPackage/rtc-r7301
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Epson RTC7301 support
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-regmap-mmio
- KCONFIG:=CONFIG_RTC_DRV_R7301 \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-r7301.ko
- AUTOLOAD:=$(call AutoProbe,rtc-r7301)
-endef
-
-define KernelPackage/rtc-r7301/description
- Kernel module for Epson RTC7301 RTC chip
-endef
-
-$(eval $(call KernelPackage,rtc-r7301))
-
-define KernelPackage/rtc-rs5c372a
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Ricoh R2025S/D, RS5C372A/B, RV5C386, RV5C387A
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-i2c-core
- KCONFIG:=CONFIG_RTC_DRV_RS5C372 \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-rs5c372.ko
- AUTOLOAD:=$(call AutoLoad,50,rtc-rs5c372,1)
-endef
-
-define KernelPackage/rtc-rs5c372a/description
- Kernel module for Ricoh R2025S/D, RS5C372A/B, RV5C386, RV5C387A RTC on chip module
-endef
-
-$(eval $(call KernelPackage,rtc-rs5c372a))
-
-define KernelPackage/rtc-rx8025
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Epson RX-8025 / RX-8035
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-i2c-core
- KCONFIG:=CONFIG_RTC_DRV_RX8025 \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-rx8025.ko
- AUTOLOAD:=$(call AutoLoad,50,rtc-rx8025,1)
-endef
-
-define KernelPackage/rtc-rx8025/description
- Kernel module for Epson RX-8025 and RX-8035 I2C RTC chip
-endef
-
-$(eval $(call KernelPackage,rtc-rx8025))
-
-define KernelPackage/rtc-s35390a
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Seico S-35390A
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-i2c-core
- KCONFIG:=CONFIG_RTC_DRV_S35390A \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-s35390a.ko
- AUTOLOAD:=$(call AutoLoad,50,rtc-s35390a,1)
-endef
-
-define KernelPackage/rtc-s35390a/description
- Kernel module for Seiko Instruments S-35390A I2C RTC chip
-endef
-
-$(eval $(call KernelPackage,rtc-s35390a))
-
-define KernelPackage/rtc-x1205
- SUBMENU:=$(OTHER_MENU)
- TITLE:=Xicor Intersil X1205
- DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
- DEPENDS:=+kmod-i2c-core
- KCONFIG:=CONFIG_RTC_DRV_X1205 \
- CONFIG_RTC_CLASS=y
- FILES:=$(LINUX_DIR)/drivers/rtc/rtc-x1205.ko
- AUTOLOAD:=$(call AutoProbe,rtc-x1205)
-endef
-
-define KernelPackage/rtc-x1205/description
- Kernel module for Xicor Intersil X1205 I2C RTC chip
-endef
-
-$(eval $(call KernelPackage,rtc-x1205))
-
define KernelPackage/mtdtests
SUBMENU:=$(OTHER_MENU)
TITLE:=MTD subsystem tests
--- /dev/null
+#
+# Copyright (C) 2006-2024 OpenWrt.org
+#
+# This is free software, licensed under the GNU General Public License v2.
+# See /LICENSE for more information.
+#
+
+RTC_MENU:=RTC Real-Time Clock Support
+
+define KernelPackage/rtc-ds1307
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Dallas/Maxim DS1307 (and compatible) RTC support
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-i2c-core +kmod-regmap-i2c +kmod-hwmon-core
+ KCONFIG:=CONFIG_RTC_DRV_DS1307 \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-ds1307.ko
+ AUTOLOAD:=$(call AutoProbe,rtc-ds1307)
+endef
+
+define KernelPackage/rtc-ds1307/description
+ Kernel module for Dallas/Maxim DS1307/DS1337/DS1338/DS1340/DS1388/DS3231,
+ Epson RX-8025 and various other compatible RTC chips connected via I2C.
+endef
+
+$(eval $(call KernelPackage,rtc-ds1307))
+
+
+define KernelPackage/rtc-ds1374
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Dallas/Maxim DS1374 RTC support
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-i2c-core
+ KCONFIG:=CONFIG_RTC_DRV_DS1374 \
+ CONFIG_RTC_DRV_DS1374_WDT=n \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-ds1374.ko
+ AUTOLOAD:=$(call AutoProbe,rtc-ds1374)
+endef
+
+define KernelPackage/rtc-ds1374/description
+ Kernel module for Dallas/Maxim DS1374.
+endef
+
+$(eval $(call KernelPackage,rtc-ds1374))
+
+
+define KernelPackage/rtc-ds1672
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Dallas/Maxim DS1672 RTC support
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-i2c-core
+ KCONFIG:=CONFIG_RTC_DRV_DS1672 \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-ds1672.ko
+ AUTOLOAD:=$(call AutoProbe,rtc-ds1672)
+endef
+
+define KernelPackage/rtc-ds1672/description
+ Kernel module for Dallas/Maxim DS1672 RTC.
+endef
+
+$(eval $(call KernelPackage,rtc-ds1672))
+
+
+define KernelPackage/rtc-em3027
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Microelectronic EM3027 RTC support
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-i2c-core
+ KCONFIG:=CONFIG_RTC_DRV_EM3027 \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-em3027.ko
+ AUTOLOAD:=$(call AutoProbe,rtc-em3027)
+endef
+
+define KernelPackage/rtc-em3027/description
+ Kernel module for Microelectronic EM3027 RTC.
+endef
+
+$(eval $(call KernelPackage,rtc-em3027))
+
+
+define KernelPackage/rtc-isl1208
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Intersil ISL1208 RTC support
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-i2c-core
+ KCONFIG:=CONFIG_RTC_DRV_ISL1208 \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-isl1208.ko
+ AUTOLOAD:=$(call AutoProbe,rtc-isl1208)
+endef
+
+define KernelPackage/rtc-isl1208/description
+ Kernel module for Intersil ISL1208 RTC.
+endef
+
+$(eval $(call KernelPackage,rtc-isl1208))
+
+
+define KernelPackage/rtc-mv
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Marvell SoC RTC support
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ KCONFIG:=CONFIG_RTC_DRV_MV \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-mv.ko
+ AUTOLOAD:=$(call AutoProbe,rtc-mv)
+endef
+
+define KernelPackage/rtc-mv/description
+ Kernel module for Marvell SoC RTC.
+endef
+
+$(eval $(call KernelPackage,rtc-mv))
+
+
+define KernelPackage/rtc-pcf8563
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Philips PCF8563/Epson RTC8564 RTC support
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-i2c-core
+ KCONFIG:=CONFIG_RTC_DRV_PCF8563 \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-pcf8563.ko
+ AUTOLOAD:=$(call AutoProbe,rtc-pcf8563)
+endef
+
+define KernelPackage/rtc-pcf8563/description
+ Kernel module for Philips PCF8563 RTC chip.
+ The Epson RTC8564 should work as well.
+endef
+
+$(eval $(call KernelPackage,rtc-pcf8563))
+
+
+define KernelPackage/rtc-pcf2123
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Philips PCF2123 RTC support
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-regmap-spi
+ KCONFIG:=CONFIG_RTC_DRV_PCF2123 \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-pcf2123.ko
+ AUTOLOAD:=$(call AutoProbe,rtc-pcf2123)
+endef
+
+define KernelPackage/rtc-pcf2123/description
+ Kernel module for Philips PCF2123 RTC chip
+endef
+
+$(eval $(call KernelPackage,rtc-pcf2123))
+
+define KernelPackage/rtc-pcf2127
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=NXP PCF2127 and PCF2129 RTC support
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-i2c-core +kmod-regmap-spi
+ KCONFIG:=CONFIG_RTC_DRV_PCF2127 \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-pcf2127.ko
+ AUTOLOAD:=$(call AutoProbe,rtc-pcf2127)
+endef
+
+define KernelPackage/rtc-pcf2127/description
+ Kernel module for NXP PCF2127 and PCF2129 RTC chip
+endef
+
+$(eval $(call KernelPackage,rtc-pcf2127))
+
+define KernelPackage/rtc-r7301
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Epson RTC7301 support
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-regmap-mmio
+ KCONFIG:=CONFIG_RTC_DRV_R7301 \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-r7301.ko
+ AUTOLOAD:=$(call AutoProbe,rtc-r7301)
+endef
+
+define KernelPackage/rtc-r7301/description
+ Kernel module for Epson RTC7301 RTC chip
+endef
+
+$(eval $(call KernelPackage,rtc-r7301))
+
+define KernelPackage/rtc-rs5c372a
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Ricoh R2025S/D, RS5C372A/B, RV5C386, RV5C387A
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-i2c-core
+ KCONFIG:=CONFIG_RTC_DRV_RS5C372 \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-rs5c372.ko
+ AUTOLOAD:=$(call AutoLoad,50,rtc-rs5c372,1)
+endef
+
+define KernelPackage/rtc-rs5c372a/description
+ Kernel module for Ricoh R2025S/D, RS5C372A/B, RV5C386, RV5C387A RTC on chip module
+endef
+
+$(eval $(call KernelPackage,rtc-rs5c372a))
+
+define KernelPackage/rtc-rx8025
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Epson RX-8025 / RX-8035
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-i2c-core
+ KCONFIG:=CONFIG_RTC_DRV_RX8025 \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-rx8025.ko
+ AUTOLOAD:=$(call AutoLoad,50,rtc-rx8025,1)
+endef
+
+define KernelPackage/rtc-rx8025/description
+ Kernel module for Epson RX-8025 and RX-8035 I2C RTC chip
+endef
+
+$(eval $(call KernelPackage,rtc-rx8025))
+
+define KernelPackage/rtc-s35390a
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Seico S-35390A
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-i2c-core
+ KCONFIG:=CONFIG_RTC_DRV_S35390A \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-s35390a.ko
+ AUTOLOAD:=$(call AutoLoad,50,rtc-s35390a,1)
+endef
+
+define KernelPackage/rtc-s35390a/description
+ Kernel module for Seiko Instruments S-35390A I2C RTC chip
+endef
+
+$(eval $(call KernelPackage,rtc-s35390a))
+
+define KernelPackage/rtc-x1205
+ SUBMENU:=$(RTC_MENU)
+ TITLE:=Xicor Intersil X1205
+ DEFAULT:=m if ALL_KMODS && RTC_SUPPORT
+ DEPENDS:=+kmod-i2c-core
+ KCONFIG:=CONFIG_RTC_DRV_X1205 \
+ CONFIG_RTC_CLASS=y
+ FILES:=$(LINUX_DIR)/drivers/rtc/rtc-x1205.ko
+ AUTOLOAD:=$(call AutoProbe,rtc-x1205)
+endef
+
+define KernelPackage/rtc-x1205/description
+ Kernel module for Xicor Intersil X1205 I2C RTC chip
+endef
+
+$(eval $(call KernelPackage,rtc-x1205))
DEPENDS:=@DISPLAY_SUPPORT
KCONFIG:= \
CONFIG_FB \
+ CONFIG_FB_DEVICE=y \
CONFIG_FB_MXS=n \
CONFIG_FB_SM750=n \
CONFIG_FRAMEBUFFER_CONSOLE=y \
$(eval $(call KernelPackage,video-mem2mem))
-define KernelPackage/video-dma
+define KernelPackage/video-dma-contig
SUBMENU:=$(VIDEO_MENU)
TITLE:=Video DMA support
HIDDEN:=1
DEPENDS:=+kmod-video-videobuf2
- KCONFIG:= \
- CONFIG_VIDEOBUF2_DMA_CONTIG \
- CONFIG_VIDEOBUF2_DMA_SG
- FILES:= $(LINUX_DIR)/drivers/media/common/videobuf2/videobuf2-dma-*.ko
- AUTOLOAD:=$(call AutoLoad,66,videobuf2-dma-contig videobuf2-dma-sg)
+ KCONFIG:=CONFIG_VIDEOBUF2_DMA_CONTIG
+ FILES:=$(LINUX_DIR)/drivers/media/common/videobuf2/videobuf2-dma-contig.ko
+ AUTOLOAD:=$(call AutoLoad,66,videobuf2-dma-contig)
+ $(call AddDepends/video)
+endef
+
+define KernelPackage/video-dma-contig/description
+ Video DMA support Contig
+endef
+
+
+$(eval $(call KernelPackage,video-dma-contig))
+
+define KernelPackage/video-dma-sg
+ SUBMENU:=$(VIDEO_MENU)
+ TITLE:=Video DMA support
+ HIDDEN:=1
+ DEPENDS:=+kmod-video-videobuf2
+ KCONFIG:=CONFIG_VIDEOBUF2_DMA_SG
+ FILES:=$(LINUX_DIR)/drivers/media/common/videobuf2/videobuf2-dma-sg.ko
+ AUTOLOAD:=$(call AutoLoad,66,videobuf2-dma-sg)
$(call AddDepends/video)
endef
-define KernelPackage/video-dma/description
- Video DMA support
+define KernelPackage/video-dma-sg/description
+ Video DMA support SG
endef
-$(eval $(call KernelPackage,video-dma))
+$(eval $(call KernelPackage,video-dma-sg))
define KernelPackage/video-coda
TITLE:=i.MX VPU support
- DEPENDS:=@(TARGET_imx&&TARGET_imx_cortexa9) +kmod-video-mem2mem +kmod-video-dma
+ DEPENDS:=@(TARGET_imx&&TARGET_imx_cortexa9) +kmod-video-mem2mem +kmod-video-dma-contig
KCONFIG:= \
CONFIG_VIDEO_CODA \
CONFIG_VIDEO_IMX_VDOA
define KernelPackage/video-pxp
TITLE:=i.MX PXP support
- DEPENDS:=@TARGET_imx +kmod-video-mem2mem +kmod-video-dma
+ DEPENDS:=@TARGET_imx +kmod-video-mem2mem +kmod-video-dma-contig
KCONFIG:= CONFIG_VIDEO_IMX_PXP
FILES:= $(LINUX_DIR)/drivers/media/$(V4L2_MEM2MEM_DIR)/imx-pxp.ko@lt6.1 \
$(LINUX_DIR)/drivers/media/platform/nxp/imx-pxp.ko@ge6.1
define KernelPackage/video-tw686x
TITLE:=TW686x support
- DEPENDS:=@PCIE_SUPPORT +kmod-video-dma +kmod-sound-core
+ DEPENDS:=@PCIE_SUPPORT +kmod-video-dma-contig +kmod-video-dma-sg +kmod-sound-core
KCONFIG:= CONFIG_VIDEO_TW686X
FILES:= $(LINUX_DIR)/drivers/media/pci/tw686x/tw686x.ko
AUTOLOAD:=$(call AutoProbe,tw686x)
PKG_DRIVERS += \
rtlwifi rtlwifi-pci rtlwifi-btcoexist rtlwifi-usb rtl8192c-common \
- rtl8192ce rtl8192se rtl8192de rtl8192cu rtl8723bs rtl8821ae \
+ rtl8192ce rtl8192se rtl8192de rtl8192cu rtl8723-common rtl8723be rtl8723bs rtl8821ae \
rtl8xxxu rtw88 rtw88-pci rtw88-usb rtw88-8821c rtw88-8822b rtw88-8822c \
rtw88-8723d rtw88-8821ce rtw88-8821cu rtw88-8822be rtw88-8822bu \
rtw88-8822ce rtw88-8822cu rtw88-8723de
config-$(call config_package,rtl8xxxu) += RTL8XXXU
config-y += RTL8XXXU_UNTESTED
+config-$(call config_package,rtl8723-common) += RTL8723_COMMON
+config-$(call config_package,rtl8723be) += RTL8723BE
+
config-$(call config_package,rtl8723bs) += RTL8723BS
config-y += STAGING
AUTOLOAD:=$(call AutoProbe,rtw88_8723)
endef
+define KernelPackage/rtl8723-common
+ $(call KernelPackage/mac80211/Default)
+ TITLE:=Realtek RTL8723AE/RTL8723BE common support module
+ DEPENDS+= +kmod-rtlwifi
+ FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8723com/rtl8723-common.ko
+ HIDDEN:=1
+endef
+
+define KernelPackage/rtl8723be
+ $(call KernelPackage/mac80211/Default)
+ TITLE:=Realtek RTL8723AE/RTL8723BE support
+ DEPENDS+= +kmod-rtlwifi-btcoexist +kmod-rtlwifi-pci +kmod-rtl8723-common +rtl8723be-firmware
+ FILES:= $(PKG_BUILD_DIR)/drivers/net/wireless/realtek/rtlwifi/rtl8723be/rtl8723be.ko
+ AUTOLOAD:=$(call AutoProbe,rtl8723be)
+endef
+
define KernelPackage/rtl8723bs
$(call KernelPackage/mac80211/Default)
TITLE:=Realtek RTL8723BS SDIO Wireless LAN NIC driver (staging)
PKG_SOURCE_URL:=https://github.com/openwrt/mt76
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2024-04-03
-PKG_SOURCE_VERSION:=1e336a8582dce2ef32ddd440d423e9afef961e71
-PKG_MIRROR_HASH:=276613540603dc6ece9d2474ae1899b6aaa6ca93bd27824056c9689c725f5890
+PKG_SOURCE_DATE:=2024-05-17
+PKG_SOURCE_VERSION:=513c131c6309712a51502870b041f45b4bd6a6d4
+PKG_MIRROR_HASH:=3e5d8ee6b8b122cc4e32668fdde0552a9fa23819b7ebdc758ecb63b5f761683a
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_USE_NINJA:=0
$(INSTALL_BIN) $(PKG_BUILD_DIR)/tools/mt76-test $(1)/usr/sbin
endef
+define Build/InstallDev
+ mkdir -p $(STAGING_DIR_IMAGE)
+ $(CP) $(PKG_BUILD_DIR)/firmware/mt7981_eeprom_mt7976_dbdc.bin $(STAGING_DIR_IMAGE)/
+endef
+
$(eval $(call KernelPackage,mt76-core))
$(eval $(call KernelPackage,mt76-usb))
$(eval $(call KernelPackage,mt76x02-usb))
#if defined(NSS_DP_PPE_SUPPORT)
uint32_t vsi_id;
fal_port_t port_id;
-@@ -940,22 +883,15 @@ static int32_t nss_dp_probe(struct platf
+@@ -940,22 +883,16 @@ static int32_t nss_dp_probe(struct platf
dp_priv->drv_flags |= NSS_DP_PRIV_FLAG(INIT_DONE);
+ netdev_err(netdev, "failed to connect to phy device\n");
+ goto phy_setup_fail;
+ }
++ phy_attached_info(dp_priv->phydev);
}
#if defined(NSS_DP_PPE_SUPPORT)
--- a/nss_dp_main.c
+++ b/nss_dp_main.c
-@@ -972,6 +972,10 @@ static int nss_dp_remove(struct platform
+@@ -970,6 +970,10 @@ static int nss_dp_remove(struct platform
if (!dp_priv)
continue;
--- a/nss_dp_main.c
+++ b/nss_dp_main.c
-@@ -1163,6 +1163,8 @@ int __init nss_dp_init(void)
+@@ -1161,6 +1161,8 @@ int __init nss_dp_init(void)
*/
void __exit nss_dp_exit(void)
{
/*
* TODO Move this to soc_ops
*/
-@@ -1170,8 +1172,6 @@ void __exit nss_dp_exit(void)
+@@ -1168,8 +1170,6 @@ void __exit nss_dp_exit(void)
nss_dp_hal_cleanup();
dp_global_ctx.common_init_done = false;
}
--- a/nss_dp_main.c
+++ b/nss_dp_main.c
-@@ -979,6 +979,9 @@ static int nss_dp_remove(struct platform
+@@ -977,6 +977,9 @@ static int nss_dp_remove(struct platform
dp_ops = dp_priv->data_plane_ops;
hal_ops = dp_priv->gmac_hal_ops;
if (dp_priv->phydev)
phy_disconnect(dp_priv->phydev);
-@@ -990,7 +993,6 @@ static int nss_dp_remove(struct platform
+@@ -988,7 +991,6 @@ static int nss_dp_remove(struct platform
#endif
hal_ops->exit(dp_priv->gmac_hal_ctx);
dp_ops->deinit(dp_priv->dpc);
--- a/nss_dp_main.c
+++ b/nss_dp_main.c
-@@ -983,7 +983,7 @@ static int nss_dp_remove(struct platform
+@@ -981,7 +981,7 @@ static int nss_dp_remove(struct platform
unregister_netdev(dp_priv->netdev);
if (dp_priv->phydev)
--- /dev/null
+From ab3b663842f66d0ed290696cee9edb9070a36e8f Mon Sep 17 00:00:00 2001
+From: Paweł Owoc <frut3k7@gmail.com>
+Date: Wed, 7 May 2024 10:37:44 +0100
+Subject: [PATCH] hsl_phy: add support for AQR114C-B0 PHY
+
+Add support for AQR114C-B0 PHY.
+
+Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
+---
+ include/hsl/phy/hsl_phy.h | 1 +
+ src/hsl/phy/hsl_phy.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/include/hsl/phy/hsl_phy.h
++++ b/include/hsl/phy/hsl_phy.h
+@@ -612,6 +612,7 @@ typedef struct {
+ #define AQUANTIA_PHY_113C_B0 0x31c31C12
+ #define AQUANTIA_PHY_113C_B1 0x31c31C13
+ #define AQUANTIA_PHY_112C 0x03a1b792
++#define AQUANTIA_PHY_114C_B0 0x31c31c22
+ #define MVL_PHY_X3410 0x31c31DD3
+
+ #define PHY_805XV2 0x004DD082
+--- a/src/hsl/phy/hsl_phy.c
++++ b/src/hsl/phy/hsl_phy.c
+@@ -271,6 +271,7 @@ phy_type_t hsl_phytype_get_by_phyid(a_ui
+ case AQUANTIA_PHY_113C_B0:
+ case AQUANTIA_PHY_113C_B1:
+ case AQUANTIA_PHY_112C:
++ case AQUANTIA_PHY_114C_B0:
+ case MVL_PHY_X3410:
+ phytype = AQUANTIA_PHY_CHIP;
+ break;
include $(TOPDIR)/rules.mk
PKG_NAME:=libbpf
-PKG_VERSION:=1.4.1
+PKG_VERSION:=1.4.2
PKG_RELEASE:=1
PKG_SOURCE_URL:=https://github.com/libbpf/libbpf
-PKG_MIRROR_HASH:=46469f720ed246529e46d84a6444ae1c1a1eaf2a717a5a055c9973bb52159ec3
+PKG_MIRROR_HASH:=eaf56a8d4297a1dfb477d91b4fb7c7c5ad6b6df73e0f7ac3c8fd93f2664c2e85
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_VERSION:=v1.4.1
+PKG_SOURCE_VERSION:=v1.4.2
PKG_ABI_VERSION:=$(firstword $(subst .,$(space),$(PKG_VERSION)))
PKG_MAINTAINER:=Tony Ambardar <itugrok@yahoo.com>
--- /dev/null
+--- a/library/common.h
++++ b/library/common.h
+@@ -199,7 +199,7 @@ static inline void mbedtls_xor(unsigned
+ uint8x16_t x = veorq_u8(v1, v2);
+ vst1q_u8(r + i, x);
+ }
+-#if defined(__IAR_SYSTEMS_ICC__)
++#if defined(__IAR_SYSTEMS_ICC__) || (defined(MBEDTLS_COMPILER_IS_GCC) && MBEDTLS_GCC_VERSION >= 140100)
+ /* This if statement helps some compilers (e.g., IAR) optimise out the byte-by-byte tail case
+ * where n is a constant multiple of 16.
+ * For other compilers (e.g. recent gcc and clang) it makes no difference if n is a compile-time
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/firewall4.git
-PKG_SOURCE_DATE:=2023-11-03
-PKG_SOURCE_VERSION:=698a53354fd280aae097efe08803c0c9a10c14c2
-PKG_MIRROR_HASH:=736b3d03cf0db1170242de20776b0095cc37d260108e4313f84eafb46b1be711
+PKG_SOURCE_DATE:=2024-05-21
+PKG_SOURCE_VERSION:=4c01d1ebf99e8ecfa69758a9b4f450ecef7b93cd
+PKG_MIRROR_HASH:=bbc5622bc03e3b43116fcc86e3fa2d2372bfc07b3a00d2b3a6efac4f7454a403
PKG_MAINTAINER:=Jo-Philipp Wich <jo@mein.io>
PKG_LICENSE:=ISC
---- a/src/dsl_cpe_cli_access.c 2016-05-27 12:34:43.612485449 -0700
-+++ b/src/dsl_cpe_cli_access.c 2016-05-27 12:45:37.491727862 -0700
-@@ -1142,7 +1142,7 @@
+--- a/src/dsl_cpe_cli_access.c
++++ b/src/dsl_cpe_cli_access.c
+@@ -1142,7 +1142,7 @@ DSL_CLI_LOCAL DSL_int_t DSL_CPE_CLI_Auto
if ((ret < 0) && (autobootCtrl.accessCtl.nReturn < DSL_SUCCESS))
{
}
else
{
-@@ -1213,7 +1213,7 @@
+@@ -1213,7 +1213,7 @@ DSL_CLI_LOCAL DSL_int_t DSL_CPE_CLI_Auto
if ((ret < 0) && (pData.accessCtl.nReturn < DSL_SUCCESS))
{
}
else
{
-@@ -1290,7 +1290,7 @@
+@@ -1290,7 +1290,7 @@ DSL_CLI_LOCAL DSL_int_t DSL_CPE_CLI_Line
if ((ret < 0) && (pData.accessCtl.nReturn < DSL_SUCCESS))
{
}
else
{
-@@ -1355,7 +1355,7 @@
+@@ -1355,7 +1355,7 @@ DSL_CLI_LOCAL DSL_int_t DSL_CPE_CLI_Reso
pCtx, &resourceUsageStatisticsData);
if (ret < 0)
{
}
else
{
-@@ -3084,7 +3084,7 @@
+@@ -3084,7 +3084,7 @@ DSL_CLI_LOCAL DSL_int_t DSL_CPE_CLI_G997
if ((ret < 0) && (pData->accessCtl.nReturn < DSL_SUCCESS))
{
}
else
{
-@@ -4654,7 +4654,7 @@
+@@ -4654,7 +4654,7 @@ DSL_CLI_LOCAL DSL_int_t DSL_CPE_CLI_G997
if ((ret < 0) && (pData.accessCtl.nReturn < DSL_SUCCESS))
{
}
else
{
-@@ -5714,7 +5714,7 @@
+@@ -5714,7 +5714,7 @@ DSL_CLI_LOCAL DSL_int_t DSL_CPE_CLI_G997
if ((ret < 0) && (pData.accessCtl.nReturn < DSL_SUCCESS))
{
--- a/Makefile
+++ b/Makefile
-@@ -7,7 +7,7 @@ HAVE_SSL=yes
+@@ -7,7 +7,7 @@
#CC=gcc
#CFLAGS=-g
PKG_NAME:=ebtables
PKG_SOURCE_DATE:=2018-06-27
-PKG_RELEASE:=1
+PKG_RELEASE:=2
PKG_SOURCE_URL:=https://git.netfilter.org/ebtables
PKG_SOURCE_PROTO:=git
+++ /dev/null
---- a/include/ebtables_u.h
-+++ b/include/ebtables_u.h
-@@ -23,6 +23,7 @@
-
- #ifndef EBTABLES_U_H
- #define EBTABLES_U_H
-+#define _NETINET_IF_ETHER_H
- #include <netinet/in.h>
- #include <netinet/ether.h>
- #include <linux/netfilter_bridge/ebtables.h>
include $(TOPDIR)/rules.mk
PKG_NAME:=iproute2
-PKG_VERSION:=6.7.0
+PKG_VERSION:=6.9.0
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@KERNEL/linux/utils/net/iproute2
-PKG_HASH:=ff942dd9828d7d1f867f61fe72ce433078c31e5d8e4a78e20f02cb5892e8841d
+PKG_HASH:=2f643d09ea11a4a2a043c92e2b469b5f73228cbf241ae806760296ed0ec413d0
PKG_BUILD_PARALLEL:=1
PKG_BUILD_DEPENDS:=iptables
PKG_LICENSE:=GPL-2.0
VARIANT:=tcfull
PROVIDES:=tc
ALTERNATIVES:=400:/sbin/tc:/usr/libexec/tc-full
- DEPENDS:=+kmod-sched-core +(PACKAGE_devlink||PACKAGE_rdma):libmnl +libbpf +libxtables +tc-mod-iptables
-endef
-
-define Package/tc-mod-iptables
-$(call Package/iproute2/Default)
- TITLE:=Traffic control module - iptables action
- VARIANT:=tcfull
- DEPENDS:=+libxtables +libbpf
+ DEPENDS:=+kmod-sched-core +(PACKAGE_devlink||PACKAGE_rdma):libmnl +libbpf +libxtables
endef
define Package/genl
define Package/ss
$(call Package/iproute2/Default)
TITLE:=Socket statistics utility
- DEPENDS:=+libnl-tiny +(PACKAGE_devlink||PACKAGE_rdma):libmnl +kmod-netlink-diag
+ DEPENDS:=+libnl-tiny +(PACKAGE_devlink||PACKAGE_rdma):libmnl +libbpf +kmod-netlink-diag
endef
define Package/nstat
$(INSTALL_BIN) $(PKG_BUILD_DIR)/tc/tc $(1)/usr/libexec/tc-full
endef
-define Package/tc-mod-iptables/install
- $(INSTALL_DIR) $(1)/usr/lib/tc
- $(CP) $(PKG_BUILD_DIR)/tc/m_xt.so $(1)/usr/lib/tc
-endef
-
define Package/genl/install
$(INSTALL_DIR) $(1)/usr/sbin
$(INSTALL_BIN) $(PKG_BUILD_DIR)/genl/genl $(1)/usr/sbin/
$(eval $(call BuildPackage,ip-tiny))
$(eval $(call BuildPackage,ip-full))
-# build tc-mod-iptables before its dependents, to avoid
-# spurious rebuilds when building multiple variants.
-$(eval $(call BuildPackage,tc-mod-iptables))
$(eval $(call BuildPackage,tc-tiny))
$(eval $(call BuildPackage,tc-bpf))
$(eval $(call BuildPackage,tc-full))
--- a/tc/Makefile
+++ b/tc/Makefile
-@@ -119,6 +119,9 @@ CFLAGS += -DCONFIG_GACT -DCONFIG_GACT_PR
+@@ -107,6 +107,9 @@ CFLAGS += -DCONFIG_GACT -DCONFIG_GACT_PR
ifneq ($(IPT_LIB_DIR),)
CFLAGS += -DIPT_LIB_DIR=\"$(IPT_LIB_DIR)\"
endif
--- a/Makefile
+++ b/Makefile
-@@ -68,9 +68,9 @@ WFLAGS += -Wmissing-declarations -Wold-s
+@@ -69,9 +69,9 @@ WFLAGS += -Wmissing-declarations -Wold-s
CFLAGS := $(WFLAGS) $(CCOPTS) -I../include -I../include/uapi $(DEFINES) $(CFLAGS)
YACCFLAGS = -d -t -v
--- a/configure
+++ b/configure
-@@ -391,7 +391,7 @@ check_tirpc()
+@@ -362,7 +362,7 @@ check_tirpc()
check_mnl()
{
--- a/configure
+++ b/configure
-@@ -246,7 +246,7 @@ EOF
+@@ -217,7 +217,7 @@ EOF
check_elf()
{
--- a/configure
+++ b/configure
-@@ -449,7 +449,7 @@ EOF
+@@ -421,7 +421,7 @@ EOF
check_cap()
{
--- a/configure
+++ b/configure
-@@ -378,7 +378,7 @@ check_selinux()
+@@ -349,7 +349,7 @@ check_selinux()
check_tirpc()
{
"Usage: ip [ OPTIONS ] OBJECT { COMMAND | help }\n"
" ip [ -force ] -batch filename\n"
+#ifndef IPROUTE2_TINY
- "where OBJECT := { address | addrlabel | amt | fou | help | ila | ioam | l2tp |\n"
- " link | macsec | maddress | monitor | mptcp | mroute | mrule |\n"
+ "where OBJECT := { address | addrlabel | fou | help | ila | ioam | l2tp | link |\n"
+ " macsec | maddress | monitor | mptcp | mroute | mrule |\n"
" neighbor | neighbour | netconf | netns | nexthop | ntable |\n"
- " ntbl | route | rule | sr | tap | tcpmetrics |\n"
+ " ntbl | route | rule | sr | stats | tap | tcpmetrics |\n"
" token | tunnel | tuntap | vrf | xfrm }\n"
+#else
-+ "where OBJECT := { address | link | maddress | monitor |\n"
++ "where OBJECT := { address | help | link | maddress | monitor |\n"
+ " neighbor | neighbour | netns | route |\n"
-+ " rule | token | tunnel }\n"
++ " rule | stats | token | tunnel }\n"
+#endif
" OPTIONS := { -V[ersion] | -s[tatistics] | -d[etails] | -r[esolve] |\n"
" -h[uman-readable] | -iec | -j[son] | -p[retty] |\n"
+++ /dev/null
---- a/tc/Makefile
-+++ b/tc/Makefile
-@@ -106,7 +106,7 @@ LDLIBS += -L. -lm
-
- ifeq ($(SHARED_LIBS),y)
- LDLIBS += -ldl
--LDFLAGS += -Wl,-export-dynamic
-+LDFLAGS += -Wl,--dynamic-list=dynsyms.list
- endif
-
- TCLIB := tc_core.o
-@@ -135,7 +135,7 @@ MODDESTDIR := $(DESTDIR)$(LIBDIR)/tc
- all: tc $(TCSO)
-
- tc: $(TCOBJ) $(LIBNETLINK) libtc.a
-- $(QUIET_LINK)$(CC) $^ $(LDFLAGS) $(LDLIBS) -o $@
-+ $(QUIET_LINK)$(CC) $(filter-out dynsyms.list, $^) $(LDFLAGS) $(LDLIBS) -o $@
-
- libtc.a: $(TCLIB)
- $(QUIET_AR)$(AR) rcs $@ $^
-@@ -157,6 +157,7 @@ install: all
- clean:
- rm -f $(TCOBJ) $(TCLIB) libtc.a tc *.so emp_ematch.tab.h; \
- rm -f emp_ematch.tab.*
-+ rm -f dynsyms.list
-
- m_xt.so: m_xt.c
- $(QUIET_CC)$(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) -shared -fpic -o m_xt.so m_xt.c $$($(PKG_CONFIG) xtables --cflags --libs)
-@@ -193,4 +194,16 @@ static-syms.h: $(wildcard *.c)
- sed -n '/'$$s'[^ ]* =/{s:.* \([^ ]*'$$s'[^ ]*\) .*:extern char \1[] __attribute__((weak)); if (!strcmp(sym, "\1")) return \1;:;p}' $$files ; \
- done > $@
-
-+else
-+
-+tc: dynsyms.list
-+m_xt.so: dynsyms.list
-+dynsyms.list: $(wildcard *.c)
-+ files="$(filter-out $(patsubst %.so,%.c,$(TCSO)), $^)" ; \
-+ echo "{" > $@ ; \
-+ for s in `grep -B 3 '\<dlsym' $$files | sed -n '/snprintf/{s:.*"\([^"]*\)".*:\1:;s:%s::;p}'` ; do \
-+ sed -n '/'$$s'[^ ]* =/{s:.* \([^ ]*'$$s'[^ ]*\) .*:\1;:;p}' $$files ; \
-+ done >> $@ ; \
-+ echo "show_stats; print_nl; print_tm; parse_rtattr; parse_rtattr_flags; get_u32; matches; addattr_l; addattr_nest; addattr_nest_end; };" >> $@
-+
- endif
--- a/configure
+++ b/configure
-@@ -270,7 +270,7 @@ int main(int argc, char **argv) {
+@@ -241,7 +241,7 @@ int main(int argc, char **argv) {
}
EOF
local ret=$?
rm -f $TMPDIR/libbpf_test.c $TMPDIR/libbpf_test
-@@ -288,7 +288,7 @@ int main(int argc, char **argv) {
+@@ -259,7 +259,7 @@ int main(int argc, char **argv) {
}
EOF
--- a/tc/Makefile
+++ b/tc/Makefile
-@@ -132,7 +132,7 @@ MODDESTDIR := $(DESTDIR)$(LIBDIR)/tc
+@@ -120,7 +120,7 @@ MODDESTDIR := $(DESTDIR)$(LIBDIR)/tc
$(QUIET_CC)$(CC) $(CFLAGS) $(CPPFLAGS) $(LDFLAGS) -shared -fpic $< -o $@
+all: $(findstring tc,$(BUILD_VARIANT)) $(TCSO)
tc: $(TCOBJ) $(LIBNETLINK) libtc.a
- $(QUIET_LINK)$(CC) $(filter-out dynsyms.list, $^) $(LDFLAGS) $(LDLIBS) -o $@
+ $(QUIET_LINK)$(CC) $^ $(LDFLAGS) $(LDLIBS) -o $@
--- a/configure
+++ b/configure
-@@ -435,14 +435,8 @@ EOF
+@@ -407,14 +407,8 @@ EOF
if $CC -I$INCLUDE -o $TMPDIR/strtest $TMPDIR/strtest.c >/dev/null 2>&1; then
echo "no"
else
--- a/configure
+++ b/configure
-@@ -365,7 +365,7 @@ check_libbpf()
+@@ -336,7 +336,7 @@ check_libbpf()
check_selinux()
# SELinux is a compile time option in the ss utility
{
--- /dev/null
+--- a/rdma/rdma.h
++++ b/rdma/rdma.h
+@@ -16,6 +16,7 @@
+ #include <rdma/rdma_user_cm.h>
+ #include <time.h>
+ #include <net/if_arp.h>
++#include <libgen.h>
+
+ #include "list.h"
+ #include "utils.h"
--- /dev/null
+From 53a89bfd86fff1a00cc77cabb8457a03eaa3bc7d Mon Sep 17 00:00:00 2001
+From: Gabi Falk <gabifalk@gmx.com>
+Date: Fri, 10 May 2024 14:36:12 +0000
+Subject: [PATCH] bridge/vlan.c: bridge/vlan.c: fix build with gcc 14 on musl
+ systems
+
+On glibc based systems the definition of 'struct timeval' is pulled in
+with inclusion of <stdlib.h> header, but on musl based systems it
+doesn't work this way. Missing definition triggers an
+incompatible-pointer-types error with gcc 14 (warning on previous
+versions of gcc):
+
+../include/json_print.h:80:30: warning: 'struct timeval' declared inside parameter list will not be visible outside of this definition or declaration
+ 80 | _PRINT_FUNC(tv, const struct timeval *)
+ | ^~~~~~~
+../include/json_print.h:50:37: note: in definition of macro '_PRINT_FUNC'
+ 50 | type value); \
+ | ^~~~
+../include/json_print.h:80:30: warning: 'struct timeval' declared inside parameter list will not be visible outside of this definition or declaration
+ 80 | _PRINT_FUNC(tv, const struct timeval *)
+ | ^~~~~~~
+../include/json_print.h:55:45: note: in definition of macro '_PRINT_FUNC'
+ 55 | type value) \
+ | ^~~~
+../include/json_print.h: In function 'print_tv':
+../include/json_print.h:58:48: error: passing argument 5 of 'print_color_tv' from incompatible pointer type [-Wincompatible-pointer-types]
+ 58 | value); \
+ | ^~~~~
+ | |
+ | const struct timeval *
+
+Signed-off-by: Gabi Falk <gabifalk@gmx.com>
+Signed-off-by: Stephen Hemminger <stephen@networkplumber.org>
+---
+ bridge/vlan.c | 1 +
+ bridge/vni.c | 1 +
+ vdpa/vdpa.c | 1 +
+ 3 files changed, 3 insertions(+)
+
+--- a/bridge/vlan.c
++++ b/bridge/vlan.c
+@@ -4,6 +4,7 @@
+ #include <unistd.h>
+ #include <fcntl.h>
+ #include <sys/socket.h>
++#include <sys/time.h>
+ #include <net/if.h>
+ #include <netinet/in.h>
+ #include <linux/if_bridge.h>
+--- a/bridge/vni.c
++++ b/bridge/vni.c
+@@ -10,6 +10,7 @@
+ #include <string.h>
+ #include <fcntl.h>
+ #include <sys/socket.h>
++#include <sys/time.h>
+ #include <net/if.h>
+ #include <netinet/in.h>
+ #include <linux/if_link.h>
+--- a/vdpa/vdpa.c
++++ b/vdpa/vdpa.c
+@@ -3,6 +3,7 @@
+ #include <stdio.h>
+ #include <getopt.h>
+ #include <errno.h>
++#include <sys/time.h>
+ #include <linux/genetlink.h>
+ #include <linux/if_ether.h>
+ #include <linux/vdpa.h>
PKG_NAME:=linux-atm
PKG_VERSION:=2.5.2
-PKG_RELEASE:=7
+PKG_RELEASE:=8
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
PKG_SOURCE_URL:=@SF/$(PKG_NAME)
+++ /dev/null
---- a/src/arpd/io.c
-+++ b/src/arpd/io.c
-@@ -277,7 +277,8 @@ static void accept_new(void)
- struct atm_qos qos;
- ENTRY *entry;
- VCC *vcc;
-- int fd,len,size,error;
-+ int fd,error;
-+ socklen_t len,size;
-
- len = sizeof(addr);
- if ((fd = accept(incoming,(struct sockaddr *) &addr,&len)) < 0) {
-@@ -614,7 +615,8 @@ int ip_itf_info(int number,uint32_t *ip,
-
- int get_local(int fd,struct sockaddr_atmsvc *addr)
- {
-- int length,result;
-+ int result;
-+ size_t length;
-
- length = sizeof(struct sockaddr_atmsvc);
- result = getsockname(fd,(struct sockaddr *) addr,&length);
---- a/src/arpd/table.c
-+++ b/src/arpd/table.c
-@@ -101,7 +101,8 @@ static void dump_vcc(VCC *vcc)
- char addr_buf[MAX_ATM_ADDR_LEN+1];
- char qos_buf[MAX_ATM_QOS_LEN+1];
- struct atm_qos qos;
-- int size,sndbuf;
-+ int sndbuf;
-+ socklen_t size;
-
- size = sizeof(addr);
- if (getpeername(vcc->fd,(struct sockaddr *) &addr,&size) < 0) {
---- a/src/ilmid/asn1/asn_int.c
-+++ b/src/ilmid/asn1/asn_int.c
-@@ -185,7 +185,7 @@ FILE* f _AND_
- AsnInt* v _AND_
- unsigned short int indent)
- {
-- fprintf(f,"%d", *v);
-+ fprintf(f,"%ld", *v);
- }
-
-
-@@ -370,5 +370,5 @@ FILE* f _AND_
- UAsnInt* v _AND_
- unsigned short int indent)
- {
-- fprintf(f,"%u", *v);
-+ fprintf(f,"%lu", *v);
- }
---- a/src/ilmid/asn1/asn_oid.c
-+++ b/src/ilmid/asn1/asn_oid.c
-@@ -127,7 +127,7 @@ unsigned short int indent)
- if (firstArcNum > 2)
- firstArcNum = 2;
-
-- fprintf(f,"%u %u", firstArcNum, arcNum - (firstArcNum * 40));
-+ fprintf(f,"%d %lu", firstArcNum, arcNum - (firstArcNum * 40));
-
- for (; i < v->octetLen ; )
- {
-@@ -136,7 +136,7 @@ unsigned short int indent)
-
- arcNum = (arcNum << 7) + (v->octs[i] & 0x7f);
- i++;
-- fprintf(f," %u", arcNum);
-+ fprintf(f," %lu", arcNum);
- }
- fprintf(f,"}");
-
---- a/src/lane/connect.c
-+++ b/src/lane/connect.c
-@@ -258,7 +258,8 @@ static int
- data_handler(const Event_t *event, void *funcdata)
- {
- Conn_t *tmp, *newconn;
-- int fd, nbytes;
-+ int fd;
-+ socklen_t nbytes;
- static char buffer[BUFSIZE];
- LaneControl_t *ctmp;
- struct sockaddr_atmsvc addr;
---- a/src/lane/connect_bus.c
-+++ b/src/lane/connect_bus.c
-@@ -170,7 +170,8 @@ static int
- data_handler(const Event_t *event, void *funcdata)
- {
- Conn_t *tmp, *newconn;
-- int fd, nbytes;
-+ int fd;
-+ socklen_t nbytes;
- static char buffer[BUFSIZE];
- struct sockaddr_atmsvc addr;
-
---- a/src/lane/lane_atm.c
-+++ b/src/lane/lane_atm.c
-@@ -138,7 +138,7 @@ atm_connect_back(const AtmAddr_t *our_ad
- struct atm_blli blli;
- struct atm_qos qos;
- int fd, ret;
-- int len = sizeof(address);
-+ socklen_t len = sizeof(address);
-
- fd = socket(PF_ATMSVC, SOCK_DGRAM, 0);
- if (fd <0) {
---- a/src/lane/lecs.c
-+++ b/src/lane/lecs.c
-@@ -119,7 +119,7 @@ int main(int argc, char **argv)
- int just_dump=0;
- fd_set fds;
- struct sockaddr_atmsvc client;
-- int len;
-+ socklen_t len;
- unsigned char buffer[P_SIZE];
-
- while(i!=-1) {
---- a/src/lib/ans.c
-+++ b/src/lib/ans.c
-@@ -41,7 +41,7 @@
- static int ans(const char *text,int wanted,void *result,int res_len)
- {
- unsigned char answer[MAX_ANSWER];
-- unsigned char name[MAX_NAME];
-+ char name[MAX_NAME];
- unsigned char *pos,*data,*found;
- int answer_len,name_len,data_len,found_len;
- int questions,answers;
---- a/src/lib/sdu2cell.c
-+++ b/src/lib/sdu2cell.c
-@@ -15,7 +15,8 @@ int sdu2cell(int s,int sizes,const int *
- {
- struct atm_qos qos;
- int trailer,total,cells;
-- int size,i;
-+ int i;
-+ socklen_t size;
-
- size = sizeof(qos);
- if (getsockopt(s,SOL_AAL,SO_ATMQOS,&qos,&size) < 0) return -1;
---- a/src/lib/unix.c
-+++ b/src/lib/unix.c
-@@ -63,8 +63,8 @@ int un_attach(const char *path)
- int un_recv_connect(int s,void *buf,int size)
- {
- struct sockaddr_un addr;
-- int addr_size;
- int len;
-+ socklen_t addr_size;
-
- addr_size = sizeof(addr);
- len = recvfrom(s,buf,size,0,(struct sockaddr *) &addr,&addr_size);
---- a/src/maint/atmtcp.c
-+++ b/src/maint/atmtcp.c
-@@ -817,7 +817,8 @@ int main(int argc,char **argv)
- }
- else if (!strcmp(ARG,"listen") ||
- (do_background = !strcmp(ARG,"listen-bg"))) {
-- int fd,port,addr_len;
-+ int fd,port;
-+ socklen_t addr_len;
- int *fd2 = alloc_t(int);
-
- if ((fd = socket(PF_INET,SOCK_STREAM,0)) < 0) {
---- a/src/maint/hediag.c
-+++ b/src/maint/hediag.c
-@@ -1,6 +1,7 @@
- #include <stdio.h>
- #include <stdlib.h>
- #include <unistd.h>
-+#include <string.h>
- #include <sys/ioctl.h>
- #include <sys/types.h>
- #include <sys/socket.h>
---- a/src/mpoad/io.c
-+++ b/src/mpoad/io.c
-@@ -521,7 +521,8 @@ static int msg_from_mps(int slot)
- static int accept_conn(int slot)
- {
- struct sockaddr_atmsvc sa;
-- int i, new_fd, sa_len;
-+ int i, new_fd;
-+ socklen_t sa_len;
-
- sa_len = sizeof(sa);
- new_fd = accept(fds[slot].fd, (struct sockaddr *)&sa, &sa_len);
---- a/src/sigd/io.c
-+++ b/src/sigd/io.c
-@@ -355,7 +355,7 @@ int get_pvc(int itf,int *vci)
- error = 0;
- if (bind(s,(struct sockaddr *) &addr,sizeof(addr)) < 0) error = errno;
- else {
-- int size;
-+ socklen_t size;
-
- size = sizeof(addr);
- if (getsockname(s,(struct sockaddr *) &addr,&size) < 0)
---- a/src/test/ttcp.c
-+++ b/src/test/ttcp.c
-@@ -92,7 +92,8 @@ struct sockaddr_in frominet;
- struct sockaddr_atmsvc satm;
- struct atm_qos qos;
-
--int domain, fromlen;
-+int domain;
-+socklen_t fromlen;
- int fd; /* fd of network socket */
-
- int buflen = 8 * 1024; /* length of buffer */
-@@ -466,7 +467,7 @@ int no_check = 0;
-
- {
- struct sockaddr_atmsvc peer;
-- int peerlen = sizeof(peer);
-+ socklen_t peerlen = sizeof(peer);
- if (getpeername(fd, (struct sockaddr *) &peer,
- &peerlen) < 0) {
- err("getpeername");
-@@ -498,7 +499,7 @@ int no_check = 0;
- /* set socket buffer size */
- #if defined(SO_SNDBUF) || defined(SO_RCVBUF)
- if (sockbufsize) {
-- int len;
-+ socklen_t len;
-
- if (trans) {
- /* set send socket buffer if we are transmitting */
---- a/src/mpoad/mpcd.8
-+++ b/src/mpoad/mpcd.8
-@@ -28,7 +28,7 @@ mpcd \- ATM MPOA (Multi\-Protocol Over A
- .B ]]
- .SH DESCRIPTION
- MPOA client
--.SM(MPC) is responsible for creating and receiving
-+.SM (MPC) is responsible for creating and receiving
- internetwork layer shortcuts. Using these shortcuts MPCs forward
- unicast internetwork layer packets effectively over ATM without need
- for routing protocols.
-@@ -43,7 +43,7 @@ accepts shortcuts and packets arriving o
- shortcuts is done with the help of
- .SM MPOA
- server
--.SM(MPS).
-+.SM (MPS).
- .PP
- Just as the Linux
- .SM LAN
---- a/src/led/zeppelin.8
-+++ b/src/led/zeppelin.8
-@@ -99,7 +99,7 @@ Ring and ATM parts of the ELAN, so using
- recommended. Token Ring support has received less testing than its
- Ethernet counterpart.
- .SH FILES
--.IP \fI/var/run/lec[interface number].pid\fP
-+.IP \fI/var/run/lec[interface\ number].pid\fP
- The file containing the process id of zeppelin.
- .SH BUGS
- John Bonham died 1980 and Led Zeppelin broke.
---- a/src/sigd/atmsigd.conf.4
-+++ b/src/sigd/atmsigd.conf.4
-@@ -125,7 +125,7 @@ a comment. The `#' character cannot be e
- .P
- If an option is specified in \fBatmsigd.conf\fP and on the command
- line, the command line has priority.
--.COMPATIBILITY
-+.SH COMPATIBILITY
- Certain options used by past versions of \fBatmsigd\fP but no longer documented
- on the man page are still recognized and supported, but they also yield a
- warning message. Future versions of \fBatmsigd\fP will not recognize those
--- /dev/null
+--- a/src/mpoad/mpcd.8
++++ b/src/mpoad/mpcd.8
+@@ -28,7 +28,7 @@ mpcd \- ATM MPOA (Multi\-Protocol Over A
+ .B ]]
+ .SH DESCRIPTION
+ MPOA client
+-.SM(MPC) is responsible for creating and receiving
++.SM (MPC) is responsible for creating and receiving
+ internetwork layer shortcuts. Using these shortcuts MPCs forward
+ unicast internetwork layer packets effectively over ATM without need
+ for routing protocols.
+@@ -43,7 +43,7 @@ accepts shortcuts and packets arriving o
+ shortcuts is done with the help of
+ .SM MPOA
+ server
+-.SM(MPS).
++.SM (MPS).
+ .PP
+ Just as the Linux
+ .SM LAN
+--- a/src/led/zeppelin.8
++++ b/src/led/zeppelin.8
+@@ -99,7 +99,7 @@ Ring and ATM parts of the ELAN, so using
+ recommended. Token Ring support has received less testing than its
+ Ethernet counterpart.
+ .SH FILES
+-.IP \fI/var/run/lec[interface number].pid\fP
++.IP \fI/var/run/lec[interface\ number].pid\fP
+ The file containing the process id of zeppelin.
+ .SH BUGS
+ John Bonham died 1980 and Led Zeppelin broke.
+--- a/src/sigd/atmsigd.conf.4
++++ b/src/sigd/atmsigd.conf.4
+@@ -125,7 +125,7 @@ a comment. The `#' character cannot be e
+ .P
+ If an option is specified in \fBatmsigd.conf\fP and on the command
+ line, the command line has priority.
+-.COMPATIBILITY
++.SH COMPATIBILITY
+ Certain options used by past versions of \fBatmsigd\fP but no longer documented
+ on the man page are still recognized and supported, but they also yield a
+ warning message. Future versions of \fBatmsigd\fP will not recognize those
+--- a/src/arpd/io.c
++++ b/src/arpd/io.c
+@@ -277,7 +277,8 @@ static void accept_new(void)
+ struct atm_qos qos;
+ ENTRY *entry;
+ VCC *vcc;
+- int fd,len,size,error;
++ int fd,error;
++ socklen_t len,size;
+
+ len = sizeof(addr);
+ if ((fd = accept(incoming,(struct sockaddr *) &addr,&len)) < 0) {
+@@ -614,7 +615,8 @@ int ip_itf_info(int number,uint32_t *ip,
+
+ int get_local(int fd,struct sockaddr_atmsvc *addr)
+ {
+- int length,result;
++ int result;
++ size_t length;
+
+ length = sizeof(struct sockaddr_atmsvc);
+ result = getsockname(fd,(struct sockaddr *) addr,&length);
+--- a/src/arpd/table.c
++++ b/src/arpd/table.c
+@@ -101,7 +101,8 @@ static void dump_vcc(VCC *vcc)
+ char addr_buf[MAX_ATM_ADDR_LEN+1];
+ char qos_buf[MAX_ATM_QOS_LEN+1];
+ struct atm_qos qos;
+- int size,sndbuf;
++ int sndbuf;
++ socklen_t size;
+
+ size = sizeof(addr);
+ if (getpeername(vcc->fd,(struct sockaddr *) &addr,&size) < 0) {
+--- a/src/ilmid/asn1/asn_int.c
++++ b/src/ilmid/asn1/asn_int.c
+@@ -185,7 +185,7 @@ FILE* f _AND_
+ AsnInt* v _AND_
+ unsigned short int indent)
+ {
+- fprintf(f,"%d", *v);
++ fprintf(f,"%ld", *v);
+ }
+
+
+@@ -370,5 +370,5 @@ FILE* f _AND_
+ UAsnInt* v _AND_
+ unsigned short int indent)
+ {
+- fprintf(f,"%u", *v);
++ fprintf(f,"%lu", *v);
+ }
+--- a/src/ilmid/asn1/asn_oid.c
++++ b/src/ilmid/asn1/asn_oid.c
+@@ -127,7 +127,7 @@ unsigned short int indent)
+ if (firstArcNum > 2)
+ firstArcNum = 2;
+
+- fprintf(f,"%u %u", firstArcNum, arcNum - (firstArcNum * 40));
++ fprintf(f,"%d %lu", firstArcNum, arcNum - (firstArcNum * 40));
+
+ for (; i < v->octetLen ; )
+ {
+@@ -136,7 +136,7 @@ unsigned short int indent)
+
+ arcNum = (arcNum << 7) + (v->octs[i] & 0x7f);
+ i++;
+- fprintf(f," %u", arcNum);
++ fprintf(f," %lu", arcNum);
+ }
+ fprintf(f,"}");
+
+--- a/src/lane/connect.c
++++ b/src/lane/connect.c
+@@ -258,7 +258,8 @@ static int
+ data_handler(const Event_t *event, void *funcdata)
+ {
+ Conn_t *tmp, *newconn;
+- int fd, nbytes;
++ int fd;
++ socklen_t nbytes;
+ static char buffer[BUFSIZE];
+ LaneControl_t *ctmp;
+ struct sockaddr_atmsvc addr;
+--- a/src/lane/connect_bus.c
++++ b/src/lane/connect_bus.c
+@@ -170,7 +170,8 @@ static int
+ data_handler(const Event_t *event, void *funcdata)
+ {
+ Conn_t *tmp, *newconn;
+- int fd, nbytes;
++ int fd;
++ socklen_t nbytes;
+ static char buffer[BUFSIZE];
+ struct sockaddr_atmsvc addr;
+
+--- a/src/lane/lane_atm.c
++++ b/src/lane/lane_atm.c
+@@ -138,7 +138,7 @@ atm_connect_back(const AtmAddr_t *our_ad
+ struct atm_blli blli;
+ struct atm_qos qos;
+ int fd, ret;
+- int len = sizeof(address);
++ socklen_t len = sizeof(address);
+
+ fd = socket(PF_ATMSVC, SOCK_DGRAM, 0);
+ if (fd <0) {
+--- a/src/lane/lecs.c
++++ b/src/lane/lecs.c
+@@ -119,7 +119,7 @@ int main(int argc, char **argv)
+ int just_dump=0;
+ fd_set fds;
+ struct sockaddr_atmsvc client;
+- int len;
++ socklen_t len;
+ unsigned char buffer[P_SIZE];
+
+ while(i!=-1) {
+--- a/src/lib/ans.c
++++ b/src/lib/ans.c
+@@ -41,7 +41,7 @@
+ static int ans(const char *text,int wanted,void *result,int res_len)
+ {
+ unsigned char answer[MAX_ANSWER];
+- unsigned char name[MAX_NAME];
++ char name[MAX_NAME];
+ unsigned char *pos,*data,*found;
+ int answer_len,name_len,data_len,found_len;
+ int questions,answers;
+--- a/src/lib/sdu2cell.c
++++ b/src/lib/sdu2cell.c
+@@ -15,7 +15,8 @@ int sdu2cell(int s,int sizes,const int *
+ {
+ struct atm_qos qos;
+ int trailer,total,cells;
+- int size,i;
++ int i;
++ socklen_t size;
+
+ size = sizeof(qos);
+ if (getsockopt(s,SOL_AAL,SO_ATMQOS,&qos,&size) < 0) return -1;
+--- a/src/lib/unix.c
++++ b/src/lib/unix.c
+@@ -63,8 +63,8 @@ int un_attach(const char *path)
+ int un_recv_connect(int s,void *buf,int size)
+ {
+ struct sockaddr_un addr;
+- int addr_size;
+ int len;
++ socklen_t addr_size;
+
+ addr_size = sizeof(addr);
+ len = recvfrom(s,buf,size,0,(struct sockaddr *) &addr,&addr_size);
+--- a/src/maint/atmtcp.c
++++ b/src/maint/atmtcp.c
+@@ -817,7 +817,8 @@ int main(int argc,char **argv)
+ }
+ else if (!strcmp(ARG,"listen") ||
+ (do_background = !strcmp(ARG,"listen-bg"))) {
+- int fd,port,addr_len;
++ int fd,port;
++ socklen_t addr_len;
+ int *fd2 = alloc_t(int);
+
+ if ((fd = socket(PF_INET,SOCK_STREAM,0)) < 0) {
+--- a/src/maint/hediag.c
++++ b/src/maint/hediag.c
+@@ -1,6 +1,7 @@
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <unistd.h>
++#include <string.h>
+ #include <sys/ioctl.h>
+ #include <sys/types.h>
+ #include <sys/socket.h>
+--- a/src/mpoad/io.c
++++ b/src/mpoad/io.c
+@@ -521,7 +521,8 @@ static int msg_from_mps(int slot)
+ static int accept_conn(int slot)
+ {
+ struct sockaddr_atmsvc sa;
+- int i, new_fd, sa_len;
++ int i, new_fd;
++ socklen_t sa_len;
+
+ sa_len = sizeof(sa);
+ new_fd = accept(fds[slot].fd, (struct sockaddr *)&sa, &sa_len);
+--- a/src/sigd/io.c
++++ b/src/sigd/io.c
+@@ -355,7 +355,7 @@ int get_pvc(int itf,int *vci)
+ error = 0;
+ if (bind(s,(struct sockaddr *) &addr,sizeof(addr)) < 0) error = errno;
+ else {
+- int size;
++ socklen_t size;
+
+ size = sizeof(addr);
+ if (getsockname(s,(struct sockaddr *) &addr,&size) < 0)
+--- a/src/test/ttcp.c
++++ b/src/test/ttcp.c
+@@ -92,7 +92,8 @@ struct sockaddr_in frominet;
+ struct sockaddr_atmsvc satm;
+ struct atm_qos qos;
+
+-int domain, fromlen;
++int domain;
++socklen_t fromlen;
+ int fd; /* fd of network socket */
+
+ int buflen = 8 * 1024; /* length of buffer */
+@@ -466,7 +467,7 @@ int no_check = 0;
+
+ {
+ struct sockaddr_atmsvc peer;
+- int peerlen = sizeof(peer);
++ socklen_t peerlen = sizeof(peer);
+ if (getpeername(fd, (struct sockaddr *) &peer,
+ &peerlen) < 0) {
+ err("getpeername");
+@@ -498,7 +499,7 @@ int no_check = 0;
+ /* set socket buffer size */
+ #if defined(SO_SNDBUF) || defined(SO_RCVBUF)
+ if (sockbufsize) {
+- int len;
++ socklen_t len;
+
+ if (trans) {
+ /* set send socket buffer if we are transmitting */
+@@ -663,7 +664,7 @@ int no_check = 0;
+ exit(0);
+
+ usage:
+- fprintf(stderr, Usage);
++ fprintf(stderr, "%s", Usage);
+ exit(1);
+ }
+
+--- a/src/arpd/arp.c
++++ b/src/arpd/arp.c
+@@ -17,6 +17,7 @@
+ #include <netinet/in.h> /* for ntohs, etc. */
+ #define _LINUX_NETDEVICE_H /* very crude hack for glibc2 */
+ #include <linux/types.h>
++#include <linux/if.h>
+ #include <linux/if_arp.h>
+ #include <linux/if_ether.h>
+ #include <atm.h>
+--- a/src/arpd/itf.c
++++ b/src/arpd/itf.c
+@@ -14,6 +14,7 @@
+ #include <sys/socket.h>
+ #define _LINUX_NETDEVICE_H /* glibc2 */
+ #include <linux/types.h>
++#include <linux/if.h>
+ #include <linux/if_arp.h>
+
+ #include "atmd.h"
+--- a/src/maint/atmdump.c
++++ b/src/maint/atmdump.c
+@@ -14,6 +14,7 @@
+ #include <sys/types.h>
+ #include <sys/time.h>
+ #include <sys/socket.h>
++#include <linux/sockios.h>
+ #include <netinet/in.h> /* for htonl and ntohl */
+ #include <atm.h>
+
+--- a/src/maint/saaldump.c
++++ b/src/maint/saaldump.c
+@@ -15,6 +15,7 @@
+ #include <sys/time.h>
+ #include <sys/types.h>
+ #include <sys/socket.h>
++#include <linux/sockios.h>
+ #include <atm.h>
+
+ #include "pdu.h"
#include <sys/socket.h>
-#define _LINUX_NETDEVICE_H /* glibc2 */
#include <linux/types.h>
+ #include <linux/if.h>
#include <linux/if_arp.h>
-
--- a/src/arpd/io.c
+++ b/src/arpd/io.c
@@ -21,7 +21,6 @@
#include <netinet/in.h> /* for ntohs, etc. */
-#define _LINUX_NETDEVICE_H /* very crude hack for glibc2 */
#include <linux/types.h>
+ #include <linux/if.h>
#include <linux/if_arp.h>
- #include <linux/if_ether.h>
+++ /dev/null
---- a/src/test/ttcp.c
-+++ b/src/test/ttcp.c
-@@ -664,7 +664,7 @@ int no_check = 0;
- exit(0);
-
- usage:
-- fprintf(stderr, Usage);
-+ fprintf(stderr, "%s", Usage);
- exit(1);
- }
-
--- /dev/null
+--- a/src/include/atmd.h
++++ b/src/include/atmd.h
+@@ -10,6 +10,7 @@
+
+ #include <stdint.h>
+ #include <stdio.h>
++#include <string.h>
+ #include <sys/types.h>
+ #include <sys/time.h>
+
+--- a/src/lib/unix.c
++++ b/src/lib/unix.c
+@@ -8,6 +8,7 @@
+
+ #include <stdlib.h>
+ #include <stdio.h>
++#include <string.h>
+ #include <unistd.h>
+ #include <errno.h>
+ #include <sys/types.h>
+--- a/src/sigd/kernel.c
++++ b/src/sigd/kernel.c
+@@ -8,6 +8,7 @@
+
+ #include <stdlib.h>
+ #include <stdio.h>
++#include <string.h>
+ #include <errno.h>
+ #include <assert.h>
+
--- /dev/null
+--- a/src/arpd/io.c
++++ b/src/arpd/io.c
+@@ -615,7 +615,7 @@ int ip_itf_info(int number,uint32_t *ip,
+ int get_local(int fd,struct sockaddr_atmsvc *addr)
+ {
+ int result;
+- size_t length;
++ socklen_t length;
+
+ length = sizeof(struct sockaddr_atmsvc);
+ result = getsockname(fd,(struct sockaddr *) addr,&length);
+--- a/src/led/conn.c
++++ b/src/led/conn.c
+@@ -405,7 +405,7 @@ Conn_t *accept_conn(Conn_t *conn)
+ {
+ Conn_t *new;
+ struct sockaddr_atmsvc addr;
+- size_t len;
++ socklen_t len;
+ int fd;
+ char buff[MAX_ATM_ADDR_LEN+1];
+
+@@ -538,7 +538,7 @@ static int handle_accept(Conn_t *conn)
+ */
+ static int handle_data(Conn_t *conn)
+ {
+- char buff[MAX_CTRL_FRAME];
++ unsigned char buff[MAX_CTRL_FRAME];
+ int retval;
+
+ retval = recv_frame(conn, buff, sizeof(buff));
+--- a/src/led/frames.c
++++ b/src/led/frames.c
+@@ -312,7 +312,7 @@ static void handle_ready_ind(Conn_t *con
+ * dependant handler functions.
+ * Returns < 0 for serious error
+ */
+-int handle_frame(Conn_t *conn, char *buff, int size)
++int handle_frame(Conn_t *conn, unsigned char *buff, int size)
+ {
+ struct ctrl_frame *frame;
+
+--- a/src/led/frames.h
++++ b/src/led/frames.h
+@@ -13,7 +13,7 @@ int validate_frame(unsigned char *buff,
+ void send_ready_ind(Conn_t *conn);
+ void send_register_req(void);
+
+-int handle_frame(Conn_t *conn, char *buff, int size);
++int handle_frame(Conn_t *conn, unsigned char *buff, int size);
+ uint32_t send_flush_req(Conn_t *conn);
+
+ void parse_tlvs(uint16_t opcode, unsigned char *tlvp, int numtlvs, int sizeoftlvs);
+--- a/src/led/join.c
++++ b/src/led/join.c
+@@ -43,7 +43,7 @@ static int read_join_rsp(char *buff, int
+ static int parse_join_rsp(unsigned char *buff, int size);
+
+ static int get_bus_addr(struct sockaddr_atmsvc *addr);
+-static int read_bus_arp(Conn_t *conn, struct sockaddr_atmsvc *addr, char *buff, int buffsize);
++static int read_bus_arp(Conn_t *conn, struct sockaddr_atmsvc *addr, unsigned char *buff, int buffsize);
+
+ /*
+ * 5.1, Initial state
+@@ -693,7 +693,7 @@ static int get_bus_addr(struct sockaddr_
+ fd_set rfds;
+ struct timeval tv;
+ int n = 0, retval, timeout;
+- char buff[MAX_CTRL_FRAME];
++ unsigned char buff[MAX_CTRL_FRAME];
+
+ timeout = 4; /* wait response for 4 seconds */
+ lec_params.c7c_current_timeout = 1;
+@@ -740,7 +740,7 @@ static int get_bus_addr(struct sockaddr_
+ * Tries to read BUS ATM address in *addr
+ * returns < 0 for error, 0 for not found > 0 for success
+ */
+-static int read_bus_arp(Conn_t *conn, struct sockaddr_atmsvc *addr, char *buff, int buffsize)
++static int read_bus_arp(Conn_t *conn, struct sockaddr_atmsvc *addr, unsigned char *buff, int buffsize)
+ {
+ int frame_size;
+ struct ctrl_frame *frame;
+++ /dev/null
---- a/src/include/atmd.h
-+++ b/src/include/atmd.h
-@@ -10,6 +10,7 @@
-
- #include <stdint.h>
- #include <stdio.h>
-+#include <string.h>
- #include <sys/types.h>
- #include <sys/time.h>
-
---- a/src/lib/unix.c
-+++ b/src/lib/unix.c
-@@ -8,6 +8,7 @@
-
- #include <stdlib.h>
- #include <stdio.h>
-+#include <string.h>
- #include <unistd.h>
- #include <errno.h>
- #include <sys/types.h>
---- a/src/sigd/kernel.c
-+++ b/src/sigd/kernel.c
-@@ -8,6 +8,7 @@
-
- #include <stdlib.h>
- #include <stdio.h>
-+#include <string.h>
- #include <errno.h>
- #include <assert.h>
-
+++ /dev/null
---- a/src/maint/saaldump.c 2020-03-29 22:58:01.089711789 +0200
-+++ b/src/maint/saaldump.c 2020-03-29 22:59:17.564639387 +0200
-@@ -6,6 +6,7 @@
- #include <config.h>
- #endif
-
-+#include <linux/sockios.h>
- #include <stdlib.h>
- #include <stdarg.h>
- #include <stdio.h>
---- a/src/maint/atmdump.c 2020-03-29 22:58:18.573694469 +0200
-+++ b/src/maint/atmdump.c 2020-03-29 22:58:49.956729365 +0200
-@@ -6,6 +6,7 @@
- #include <config.h>
- #endif
-
-+#include <linux/sockios.h>
- #include <stdlib.h>
- #include <stdio.h>
- #include <unistd.h>
-
PKG_SOURCE_URL=https://gitlab.alpinelinux.org/alpine/apk-tools.git
PKG_SOURCE_PROTO:=git
-PKG_SOURCE_DATE:=2024-04-16
-PKG_SOURCE_VERSION:=ba6c31a5469ef74fb85119508e55de9631ffef41
-PKG_MIRROR_HASH:=3455d5799481add9ece3db685576d58be6303f3a13140133979b965cbd3c9966
+PKG_SOURCE_DATE:=2024-05-19
+PKG_SOURCE_VERSION:=825681118d05ca5801c6b3852a70a42499e57def
+PKG_MIRROR_HASH:=adc07e3320e8d780bbbd3d95d3c6c6ce259f3dbf97ab0a4ff9dc4853af21e04f
PKG_VERSION=3.0.0_pre$(subst -,,$(PKG_SOURCE_DATE))
PKG_INSTALL:=1
HOST_BUILD_PREFIX:=$(STAGING_DIR_HOST)
-HOST_BUILD_DEPENDS:=lua/host
-PKG_BUILD_DEPENDS:=$(HOST_BUILD_DEPENDS)
+PKG_BUILD_DEPENDS:=lua/host
include $(INCLUDE_DIR)/package.mk
include $(INCLUDE_DIR)/host-build.mk
TITLE:=apk package manager
DEPENDS:=+zlib
URL:=$(PKG_SOURCE_URL)
+ PROVIDES:=apk
endef
define Package/apk-mbedtls
MESON_VARS+=VERSION=$(PKG_VERSION)
MESON_HOST_ARGS += \
- -Dlua_version=5.1 \
+ -Dhelp=disabled \
-Dcompressed-help=false \
-Ddocs=disabled \
-Dcrypto_backend=openssl \
--- a/src/database.c
+++ b/src/database.c
-@@ -1604,7 +1604,7 @@ const char *apk_db_layer_name(int layer)
+@@ -1643,7 +1643,7 @@ const char *apk_db_layer_name(int layer)
{
switch (layer) {
case APK_DB_LAYER_ROOT: return "lib/apk/db";
- case APK_DB_LAYER_UVOL: return "lib/apk/db-uvol";
+ case APK_DB_LAYER_UVOL: return "tmp/run/uvol/.meta/apk";
default:
- assert("invalid layer");
+ assert(!"invalid layer");
return 0;
+++ /dev/null
-From 74ea482102e1a7c1845b3eec19cbdb21264836d4 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Timo=20Ter=C3=A4s?= <timo.teras@iki.fi>
-Date: Fri, 5 Apr 2024 12:06:56 +0300
-Subject: [PATCH 1/4] add alternate url wget implementation
-
----
- .gitlab-ci.yml | 16 ++++-
- meson.build | 6 +-
- meson_options.txt | 1 +
- src/io_url_wget.c | 150 ++++++++++++++++++++++++++++++++++++++++++++++
- src/meson.build | 4 +-
- 5 files changed, 173 insertions(+), 4 deletions(-)
- create mode 100644 src/io_url_wget.c
-
-diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
-index 7fc86563..b7e00008 100644
---- a/.gitlab-ci.yml
-+++ b/.gitlab-ci.yml
-@@ -24,7 +24,19 @@ test:alpine:
- script:
- - apk update
- - apk add make gcc git musl-dev openssl-dev linux-headers zlib-dev zstd-dev lua5.3-dev lua5.3-lzlib meson zlib-static zstd-static openssl-libs-static
-- - meson build
-+ - meson setup build -Dstatic_apk=true
-+ - ninja -C build
-+ tags:
-+ - docker-alpine
-+ - x86_64
-+
-+test:alpine-alt-config:
-+ image: alpine
-+ stage: test
-+ script:
-+ - apk update
-+ - apk add make gcc git musl-dev openssl-dev linux-headers zlib-dev lua5.3-dev lua5.3-lzlib meson
-+ - meson setup build -Durl_backend=wget -Dzstd=false
- - ninja -C build
- tags:
- - docker-alpine
-@@ -38,7 +50,7 @@ test:debian:
- - apt-get install -y make gcc git libssl-dev zlib1g-dev libzstd-dev lua5.3-dev lua5.2 lua-zlib-dev sudo meson
- - unlink /bin/sh
- - ln -s /bin/bash /bin/sh
-- - meson build
-+ - meson setup build
- - ninja -C build
- tags:
- - docker-alpine
-diff --git a/meson.build b/meson.build
-index 1a44c11f..9a14cac0 100644
---- a/meson.build
-+++ b/meson.build
-@@ -33,6 +33,10 @@ subproject = meson.is_subproject()
-
- subdir('doc')
- subdir('portability')
--subdir('libfetch')
-+if get_option('url_backend') == 'libfetch'
-+ subdir('libfetch')
-+else
-+ libfetch_dep = dependency('', required: false)
-+endif
- subdir('src')
- subdir('tests')
-diff --git a/meson_options.txt b/meson_options.txt
-index 693f46ec..940fe9a4 100644
---- a/meson_options.txt
-+++ b/meson_options.txt
-@@ -5,5 +5,6 @@ option('help', description: 'Build help into apk binaries, needs lua', type: 'fe
- option('lua', description: 'Build luaapk (lua bindings)', type: 'feature', value: 'auto')
- option('lua_version', description: 'Lua version to build against', type: 'string', value: '5.3')
- option('static_apk', description: 'Also build apk.static', type: 'boolean', value: false)
-+option('url_backend', description: 'URL backend', type: 'combo', choices: ['libfetch', 'wget'], value: 'libfetch')
- option('uvol_db_target', description: 'Default target for uvol database layer', type: 'string')
- option('zstd', description: 'Build with zstd support', type: 'boolean', value: true)
-diff --git a/src/io_url_wget.c b/src/io_url_wget.c
-new file mode 100644
-index 00000000..9a929222
---- /dev/null
-+++ b/src/io_url_wget.c
-@@ -0,0 +1,150 @@
-+/* io_url_wget.c - Alpine Package Keeper (APK)
-+ *
-+ * Copyright (C) 2005-2008 Natanael Copa <n@tanael.org>
-+ * Copyright (C) 2008-2011 Timo Teräs <timo.teras@iki.fi>
-+ * All rights reserved.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0-only
-+ */
-+
-+#include <spawn.h>
-+#include <unistd.h>
-+#include <sys/wait.h>
-+#include "apk_io.h"
-+
-+static char wget_timeout[16];
-+static char wget_no_check_certificate;
-+
-+static int wget_translate_status(int status)
-+{
-+ if (!WIFEXITED(status)) return -EFAULT;
-+ switch (WEXITSTATUS(status)) {
-+ case 0: return 0;
-+ case 3: return -EIO;
-+ case 4: return -ENETUNREACH;
-+ case 5: return -EACCES;
-+ case 6: return -EACCES;
-+ case 7: return -EPROTO;
-+ default: return -APKE_REMOTE_IO;
-+ }
-+}
-+
-+struct apk_wget_istream {
-+ struct apk_istream is;
-+ int fd;
-+ pid_t pid;
-+};
-+
-+static int wget_spawn(const char *url, pid_t *pid, int *fd)
-+{
-+ int i = 0, r, pipefds[2];
-+ posix_spawn_file_actions_t act;
-+ char *argv[16];
-+
-+ argv[i++] = "wget";
-+ argv[i++] = "-q";
-+ argv[i++] = "-T";
-+ argv[i++] = wget_timeout;
-+ if (wget_no_check_certificate) argv[i++] = "--no-check-certificate";
-+ argv[i++] = (char *) url;
-+ argv[i++] = "-O";
-+ argv[i++] = "-";
-+ argv[i++] = 0;
-+
-+ if (pipe2(pipefds, O_CLOEXEC) != 0) return -errno;
-+
-+ posix_spawn_file_actions_init(&act);
-+ posix_spawn_file_actions_adddup2(&act, pipefds[1], STDOUT_FILENO);
-+ r = posix_spawnp(pid, "wget", &act, 0, argv, environ);
-+ posix_spawn_file_actions_destroy(&act);
-+ if (r != 0) return -r;
-+ close(pipefds[1]);
-+ *fd = pipefds[0];
-+ return 0;
-+}
-+
-+static int wget_check_exit(struct apk_wget_istream *wis)
-+{
-+ int status;
-+
-+ if (wis->pid == 0) return apk_istream_error(&wis->is, 0);
-+ if (waitpid(wis->pid, &status, 0) == wis->pid) {
-+ wis->pid = 0;
-+ return apk_istream_error(&wis->is, wget_translate_status(status));
-+ }
-+ return 0;
-+}
-+
-+static void wget_get_meta(struct apk_istream *is, struct apk_file_meta *meta)
-+{
-+}
-+
-+static ssize_t wget_read(struct apk_istream *is, void *ptr, size_t size)
-+{
-+ struct apk_wget_istream *wis = container_of(is, struct apk_wget_istream, is);
-+ ssize_t r;
-+
-+ r = read(wis->fd, ptr, size);
-+ if (r < 0) return -errno;
-+ if (r == 0) return wget_check_exit(wis);
-+ return r;
-+}
-+
-+static int wget_close(struct apk_istream *is)
-+{
-+ int r = is->err;
-+ struct apk_wget_istream *wis = container_of(is, struct apk_wget_istream, is);
-+
-+ while (wis->pid != 0)
-+ wget_check_exit(wis);
-+
-+ close(wis->fd);
-+ free(wis);
-+ return r < 0 ? r : 0;
-+}
-+
-+static const struct apk_istream_ops wget_istream_ops = {
-+ .get_meta = wget_get_meta,
-+ .read = wget_read,
-+ .close = wget_close,
-+};
-+
-+struct apk_istream *apk_io_url_istream(const char *url, time_t since)
-+{
-+ struct apk_wget_istream *wis;
-+ int r;
-+
-+ wis = malloc(sizeof(*wis) + apk_io_bufsize);
-+ if (wis == NULL) return ERR_PTR(-ENOMEM);
-+
-+ *wis = (struct apk_wget_istream) {
-+ .is.ops = &wget_istream_ops,
-+ .is.buf = (uint8_t *)(wis + 1),
-+ .is.buf_size = apk_io_bufsize,
-+ };
-+ r = wget_spawn(url, &wis->pid, &wis->fd);
-+ if (r != 0) {
-+ free(wis);
-+ return ERR_PTR(r);
-+ }
-+
-+ return &wis->is;
-+}
-+
-+void apk_io_url_no_check_certificate(void)
-+{
-+ wget_no_check_certificate = 1;
-+}
-+
-+void apk_io_url_set_timeout(int timeout)
-+{
-+ snprintf(wget_timeout, sizeof wget_timeout, "%d", timeout);
-+}
-+
-+void apk_io_url_set_redirect_callback(void (*cb)(int, const char *))
-+{
-+}
-+
-+void apk_io_url_init(void)
-+{
-+}
-diff --git a/src/meson.build b/src/meson.build
-index c1aae550..38e9d3b0 100644
---- a/src/meson.build
-+++ b/src/meson.build
-@@ -1,3 +1,5 @@
-+url_backend = get_option('url_backend')
-+
- libapk_so_version = '2.99.0'
- libapk_src = [
- 'adb.c',
-@@ -22,8 +24,8 @@ libapk_src = [
- 'fs_uvol.c',
- 'hash.c',
- 'io.c',
-- 'io_url_libfetch.c',
- 'io_gunzip.c',
-+ 'io_url_@0@.c'.format(url_backend),
- 'package.c',
- 'pathbuilder.c',
- 'print.c',
---
-GitLab
-
-
-From b9fe78fbf19bb10e1d0b8eb1cb1de123bee2ed7e Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 16 Apr 2024 17:55:15 +0200
-Subject: [PATCH 2/4] add option to configure url backend in legacy make build
- system
-
-Can be configured by setting URL_BACKEND. If not set libfetch is
-selected by default.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- src/Makefile | 20 ++++++++++++++------
- 1 file changed, 14 insertions(+), 6 deletions(-)
-
-diff --git a/src/Makefile b/src/Makefile
-index f7873cb1..efdc68df 100644
---- a/src/Makefile
-+++ b/src/Makefile
-@@ -9,8 +9,8 @@ else
- $(error Lua interpreter not found. Please specify LUA interpreter, or use LUA=no to build without help.)
- endif
-
--OPENSSL_CFLAGS := $(shell $(PKG_CONFIG) --cflags openssl)
--OPENSSL_LIBS := $(shell $(PKG_CONFIG) --libs openssl)
-+OPENSSL_CFLAGS := $(shell $(PKG_CONFIG) --cflags openssl)
-+OPENSSL_LIBS := $(shell $(PKG_CONFIG) --libs openssl)
-
- ZLIB_CFLAGS := $(shell $(PKG_CONFIG) --cflags zlib)
- ZLIB_LIBS := $(shell $(PKG_CONFIG) --libs zlib)
-@@ -21,10 +21,18 @@ libapk_so := $(obj)/libapk.so.$(libapk_soname)
- libapk.so.$(libapk_soname)-objs := \
- adb.o adb_comp.o adb_walk_adb.o adb_walk_genadb.o adb_walk_gentext.o adb_walk_text.o apk_adb.o \
- atom.o blob.o commit.o common.o context.o crypto.o crypto_openssl.o ctype.o database.o hash.o \
-- extract_v2.o extract_v3.o fs_fsys.o fs_uvol.o io.o io_gunzip.o io_url_libfetch.o \
-- tar.o package.o pathbuilder.o print.o solver.o trust.o version.o
-+ extract_v2.o extract_v3.o fs_fsys.o fs_uvol.o io.o io_gunzip.o tar.o package.o pathbuilder.o \
-+ print.o solver.o trust.o version.o
-
--libapk.so.$(libapk_soname)-libs := libfetch/libfetch.a
-+libapk.so.$(libapk_soname)-libs :=
-+
-+ifeq ($(URL_BACKEND),wget)
-+libapk.so.$(libapk_soname)-objs += io_url_wget.o
-+else
-+CFLAGS_ALL += -Ilibfetch
-+libapk.so.$(libapk_soname)-objs += io_url_libfetch.o
-+libapk.so.$(libapk_soname)-libs += libfetch/libfetch.a
-+endif
-
- # ZSTD support can be disabled
- ifneq ($(ZSTD),no)
-@@ -79,7 +87,7 @@ LIBS_apk := -lapk
- LIBS_apk-test := -lapk
- LIBS_apk.so := -L$(obj) -lapk
-
--CFLAGS_ALL += -D_ATFILE_SOURCE -Ilibfetch -Iportability
-+CFLAGS_ALL += -D_ATFILE_SOURCE -Iportability
- CFLAGS_apk.o := -DAPK_VERSION=\"$(VERSION)\"
- CFLAGS_apk-static.o := -DAPK_VERSION=\"$(VERSION)\" -DOPENSSL_NO_ENGINE
- CFLAGS_apk-test.o := -DAPK_VERSION=\"$(VERSION)\" -DOPENSSL_NO_ENGINE -DTEST_MODE
---
-GitLab
-
-
-From 0418b684898403c49905c1f0e4b7c5ca522b2d50 Mon Sep 17 00:00:00 2001
-From: Jonas Jelonek <jelonek.jonas@gmail.com>
-Date: Sun, 14 Apr 2024 00:20:14 +0200
-Subject: [PATCH 3/4] crypto: add support for mbedtls as backend
-
-backend is selected at compile-time with crypto_backend option
-
-Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
----
- libfetch/meson.build | 2 +-
- meson.build | 14 +-
- meson_options.txt | 1 +
- portability/getrandom.c | 19 +++
- portability/meson.build | 3 +-
- portability/sys/random.h | 6 +
- src/apk_crypto.h | 5 +
- src/apk_crypto_mbedtls.h | 30 +++++
- src/crypto_mbedtls.c | 285 +++++++++++++++++++++++++++++++++++++++
- src/meson.build | 21 ++-
- 10 files changed, 373 insertions(+), 13 deletions(-)
- create mode 100644 portability/getrandom.c
- create mode 100644 portability/sys/random.h
- create mode 100644 src/apk_crypto_mbedtls.h
- create mode 100644 src/crypto_mbedtls.c
-
-diff --git a/libfetch/meson.build b/libfetch/meson.build
-index 431ba197..e24f95eb 100644
---- a/libfetch/meson.build
-+++ b/libfetch/meson.build
-@@ -40,7 +40,7 @@ libfetch = static_library(
- c_args: libfetch_cargs,
- dependencies: [
- libportability_dep.partial_dependency(compile_args: true, includes: true),
-- openssl_dep.partial_dependency(compile_args: true, includes: true)
-+ crypto_dep.partial_dependency(compile_args: true, includes: true)
- ],
- )
-
-diff --git a/meson.build b/meson.build
-index 9a14cac0..3a83f4e1 100644
---- a/meson.build
-+++ b/meson.build
-@@ -13,15 +13,21 @@ apk_libdir = get_option('libdir')
- lua_bin = find_program('lua' + get_option('lua_version'), required: get_option('help'))
- lua_dep = dependency('lua' + get_option('lua_version'), required: get_option('lua'))
- scdoc_dep = dependency('scdoc', version: '>=1.10', required: get_option('docs'))
--openssl_dep = dependency('openssl')
--openssl_static_dep = dependency('openssl', static: true)
- zlib_dep = dependency('zlib')
- zlib_static_dep = dependency('zlib', static: true)
- libzstd_dep = dependency('libzstd', required: get_option('zstd'))
- libzstd_static_dep = dependency('libzstd', required: get_option('zstd'), static: true)
-
--shared_deps = [ openssl_dep, zlib_dep, libzstd_dep ]
--static_deps = [ openssl_static_dep, zlib_static_dep, libzstd_static_dep ]
-+if get_option('crypto_backend') == 'openssl'
-+ crypto_dep = dependency('openssl')
-+ crypto_static_dep = dependency('openssl', static: true)
-+elif get_option('crypto_backend') == 'mbedtls'
-+ crypto_dep = [ dependency('mbedtls'), dependency('mbedcrypto') ]
-+ crypto_static_dep = [ dependency('mbedtls', static: true), dependency('mbedcrypto', static: true) ]
-+endif
-+
-+shared_deps = [ crypto_dep, zlib_dep, libzstd_dep ]
-+static_deps = [ crypto_static_dep, zlib_static_dep, libzstd_static_dep ]
-
- add_project_arguments('-D_GNU_SOURCE', language: 'c')
-
-diff --git a/meson_options.txt b/meson_options.txt
-index 940fe9a4..df0b07dc 100644
---- a/meson_options.txt
-+++ b/meson_options.txt
-@@ -1,4 +1,5 @@
- option('arch_prefix', description: 'Define a custom arch prefix for default arch', type: 'string')
-+option('crypto_backend', description: 'Crypto backend', type: 'combo', choices: ['openssl', 'mbedtls'], value: 'openssl')
- option('compressed-help', description: 'Compress help database, needs lua-zlib', type: 'boolean', value: true)
- option('docs', description: 'Build manpages with scdoc', type: 'feature', value: 'auto')
- option('help', description: 'Build help into apk binaries, needs lua', type: 'feature', value: 'auto')
-diff --git a/portability/getrandom.c b/portability/getrandom.c
-new file mode 100644
-index 00000000..b2f4a07c
---- /dev/null
-+++ b/portability/getrandom.c
-@@ -0,0 +1,19 @@
-+#include <sys/random.h>
-+#include <sys/types.h>
-+#include <unistd.h>
-+#include <fcntl.h>
-+
-+ssize_t getrandom(void *buf, size_t buflen, unsigned int flags)
-+{
-+ int fd;
-+ ssize_t ret;
-+
-+ fd = open("/dev/urandom", O_RDONLY|O_CLOEXEC);
-+ if (fd < 0)
-+ return -1;
-+
-+ ret = read(fd, buf, buflen);
-+ close(fd);
-+ return ret;
-+}
-+
-diff --git a/portability/meson.build b/portability/meson.build
-index 89957c3c..3172044e 100644
---- a/portability/meson.build
-+++ b/portability/meson.build
-@@ -3,7 +3,8 @@ cc = meson.get_compiler('c')
- libportability_src = []
-
- check_symbols = [
-- ['memrchr', 'memrchr.c', 'NEED_MEMRCHR', 'string.h'],
-+ ['getrandom', 'getrandom.c', 'NEED_GETRANDOM', 'sys/random.h'],
-+ ['memrchr', 'memrchr.c', 'NEED_MEMRCHR', 'string.h'],
- ['mknodat', 'mknodat.c', 'NEED_MKNODAT', 'sys/stat.h'],
- ['pipe2', 'pipe2.c', 'NEED_PIPE2', 'unistd.h'],
- ['qsort_r', 'qsort_r.c', 'NEED_QSORT_R', 'stdlib.h'],
-diff --git a/portability/sys/random.h b/portability/sys/random.h
-new file mode 100644
-index 00000000..02d5b1ca
---- /dev/null
-+++ b/portability/sys/random.h
-@@ -0,0 +1,6 @@
-+#include_next <sys/random.h>
-+#include <sys/types.h>
-+
-+#ifdef NEED_GETRANDOM
-+ssize_t getrandom(void *buf, size_t buflen, unsigned int flags);
-+#endif
-diff --git a/src/apk_crypto.h b/src/apk_crypto.h
-index 7de88dfc..5cae3bfe 100644
---- a/src/apk_crypto.h
-+++ b/src/apk_crypto.h
-@@ -12,7 +12,12 @@
- #include <string.h>
- #include "apk_defines.h"
- #include "apk_blob.h"
-+
-+#if defined(CRYPTO_USE_OPENSSL)
- #include "apk_crypto_openssl.h"
-+#elif defined(CRYPTO_USE_MBEDTLS)
-+#include "apk_crypto_mbedtls.h"
-+#endif
-
- // Digest
-
-diff --git a/src/apk_crypto_mbedtls.h b/src/apk_crypto_mbedtls.h
-new file mode 100644
-index 00000000..5481d149
---- /dev/null
-+++ b/src/apk_crypto_mbedtls.h
-@@ -0,0 +1,30 @@
-+/* apk_crypto_mbedtls.h - Alpine Package Keeper (APK)
-+ *
-+ * Copyright (C) 2024
-+ * All rights reserved.
-+ *
-+ * SPDX-License-Identifier: GPL-2.0-only
-+ */
-+
-+#ifndef APK_CRYPTO_MBEDTLS_H
-+#define APK_CRYPTO_MBEDTLS_H
-+
-+#include <mbedtls/md.h>
-+#include <mbedtls/pk.h>
-+#include <mbedtls/bignum.h>
-+
-+struct apk_pkey {
-+ uint8_t id[16];
-+ mbedtls_pk_context key;
-+};
-+
-+struct apk_digest_ctx {
-+ mbedtls_md_context_t mdctx;
-+ struct apk_pkey *sigver_key;
-+ uint8_t alg;
-+};
-+
-+/* based on mbedtls' internal pkwrite.h calculations */
-+#define APK_ENC_KEY_MAX_LENGTH (38 + 2 * MBEDTLS_MPI_MAX_SIZE)
-+
-+#endif
-diff --git a/src/crypto_mbedtls.c b/src/crypto_mbedtls.c
-new file mode 100644
-index 00000000..73d60e9d
---- /dev/null
-+++ b/src/crypto_mbedtls.c
-@@ -0,0 +1,285 @@
-+#include <errno.h>
-+#include <stdio.h>
-+#include <stdlib.h>
-+#include <fcntl.h>
-+#include <sys/random.h>
-+#include <sys/stat.h>
-+#include <unistd.h>
-+
-+#include <mbedtls/platform.h>
-+#include <mbedtls/md.h>
-+#include <mbedtls/pk.h>
-+#include <mbedtls/entropy.h>
-+
-+#ifdef MBEDTLS_PSA_CRYPTO_C
-+#include <psa/crypto.h>
-+#endif
-+
-+#include "apk_crypto.h"
-+
-+static inline const mbedtls_md_type_t apk_digest_alg_to_mbedtls_type(uint8_t alg) {
-+ switch (alg) {
-+ case APK_DIGEST_NONE: return MBEDTLS_MD_NONE;
-+ case APK_DIGEST_MD5: return MBEDTLS_MD_MD5;
-+ case APK_DIGEST_SHA1: return MBEDTLS_MD_SHA1;
-+ case APK_DIGEST_SHA256_160:
-+ case APK_DIGEST_SHA256: return MBEDTLS_MD_SHA256;
-+ case APK_DIGEST_SHA512: return MBEDTLS_MD_SHA512;
-+ default:
-+ assert(alg);
-+ return MBEDTLS_MD_NONE;
-+ }
-+}
-+
-+static inline const mbedtls_md_info_t *apk_digest_alg_to_mdinfo(uint8_t alg)
-+{
-+ return mbedtls_md_info_from_type(
-+ apk_digest_alg_to_mbedtls_type(alg)
-+ );
-+}
-+
-+int apk_digest_calc(struct apk_digest *d, uint8_t alg, const void *ptr, size_t sz)
-+{
-+ if (mbedtls_md(apk_digest_alg_to_mdinfo(alg), ptr, sz, d->data))
-+ return -APKE_CRYPTO_ERROR;
-+
-+ apk_digest_set(d, alg);
-+ return 0;
-+}
-+
-+int apk_digest_ctx_init(struct apk_digest_ctx *dctx, uint8_t alg)
-+{
-+ dctx->alg = alg;
-+
-+ mbedtls_md_init(&dctx->mdctx);
-+ if (alg == APK_DIGEST_NONE) return 0;
-+ if (mbedtls_md_setup(&dctx->mdctx, apk_digest_alg_to_mdinfo(alg), 0) ||
-+ mbedtls_md_starts(&dctx->mdctx))
-+ return -APKE_CRYPTO_ERROR;
-+
-+ return 0;
-+}
-+
-+int apk_digest_ctx_reset(struct apk_digest_ctx *dctx)
-+{
-+ if (dctx->alg == APK_DIGEST_NONE) return 0;
-+ if (mbedtls_md_starts(&dctx->mdctx)) return -APKE_CRYPTO_ERROR;
-+ return 0;
-+}
-+
-+int apk_digest_ctx_reset_alg(struct apk_digest_ctx *dctx, uint8_t alg)
-+{
-+ mbedtls_md_free(&dctx->mdctx);
-+
-+ dctx->alg = alg;
-+ if (alg == APK_DIGEST_NONE) return 0;
-+ if (mbedtls_md_setup(&dctx->mdctx, apk_digest_alg_to_mdinfo(alg), 0) ||
-+ mbedtls_md_starts(&dctx->mdctx))
-+ return -APKE_CRYPTO_ERROR;
-+
-+ return 0;
-+}
-+
-+void apk_digest_ctx_free(struct apk_digest_ctx *dctx)
-+{
-+ mbedtls_md_free(&dctx->mdctx);
-+}
-+
-+int apk_digest_ctx_update(struct apk_digest_ctx *dctx, const void *ptr, size_t sz)
-+{
-+ if (dctx->alg == APK_DIGEST_NONE) return 0;
-+ return mbedtls_md_update(&dctx->mdctx, ptr, sz) == 0 ? 0 : -APKE_CRYPTO_ERROR;
-+}
-+
-+int apk_digest_ctx_final(struct apk_digest_ctx *dctx, struct apk_digest *d)
-+{
-+ if (mbedtls_md_finish(&dctx->mdctx, d->data)) {
-+ apk_digest_reset(d);
-+ return -APKE_CRYPTO_ERROR;
-+ }
-+
-+ d->alg = dctx->alg;
-+ d->len = apk_digest_alg_len(d->alg);
-+ return 0;
-+}
-+
-+static int apk_load_file_at(int dirfd, const char *fn, unsigned char **buf, size_t *n)
-+{
-+ struct stat stats;
-+ size_t size;
-+ int fd;
-+
-+ if ((fd = openat(dirfd, fn, O_RDONLY|O_CLOEXEC)) < 0)
-+ return -errno;
-+
-+ if (fstat(fd, &stats)) {
-+ close(fd);
-+ return -errno;
-+ }
-+
-+ size = (size_t)stats.st_size;
-+ *n = size;
-+
-+ if (size == 0 || (*buf = mbedtls_calloc(1, size + 1)) == NULL)
-+ return MBEDTLS_ERR_PK_ALLOC_FAILED;
-+
-+ if (read(fd, *buf, size) != size) {
-+ close(fd);
-+
-+ mbedtls_platform_zeroize(*buf, size);
-+ mbedtls_free(*buf);
-+
-+ return MBEDTLS_ERR_PK_FILE_IO_ERROR;
-+ }
-+ close(fd);
-+
-+ (*buf)[size] = '\0';
-+
-+ if (strstr((const char *) *buf, "-----BEGIN ") != NULL) {
-+ ++*n;
-+ }
-+
-+ return 0;
-+}
-+
-+static int apk_pkey_init(struct apk_pkey *pkey)
-+{
-+ unsigned char dig[APK_DIGEST_MAX_LENGTH];
-+ unsigned char pub[APK_ENC_KEY_MAX_LENGTH] = {};
-+ unsigned char *c;
-+ int len, r = -APKE_CRYPTO_ERROR;
-+
-+ c = pub + APK_ENC_KEY_MAX_LENGTH;
-+
-+ // key is written backwards into pub starting at c!
-+ if ((len = mbedtls_pk_write_pubkey(&c, pub, &pkey->key)) < 0) return -APKE_CRYPTO_ERROR;
-+ if (!mbedtls_md(apk_digest_alg_to_mdinfo(APK_DIGEST_SHA512), c, len, dig)) {
-+ memcpy(pkey->id, dig, sizeof pkey->id);
-+ r = 0;
-+ }
-+
-+ return r;
-+}
-+
-+void apk_pkey_free(struct apk_pkey *pkey)
-+{
-+ mbedtls_pk_free(&pkey->key);
-+}
-+
-+static int apk_random(void *ctx, unsigned char *out, size_t len)
-+{
-+ return (int)getrandom(out, len, 0);
-+}
-+
-+#if MBEDTLS_VERSION_NUMBER >= 0x03000000
-+static inline int apk_mbedtls_parse_privkey(struct apk_pkey *pkey, const unsigned char *buf, size_t blen)
-+{
-+ return mbedtls_pk_parse_key(&pkey->key, buf, blen, NULL, 0, apk_random, NULL);
-+}
-+static inline int apk_mbedtls_sign(struct apk_digest_ctx *dctx, struct apk_digest *dig,
-+ unsigned char *sig, size_t *sig_len)
-+{
-+ return mbedtls_pk_sign(&dctx->sigver_key->key, apk_digest_alg_to_mbedtls_type(dctx->alg),
-+ (const unsigned char *)&dig->data, dig->len, sig, sizeof *sig, sig_len,
-+ apk_random, NULL);
-+}
-+#else
-+static inline int apk_mbedtls_parse_privkey(struct apk_pkey *pkey, const unsigned char *buf, size_t blen)
-+{
-+ return mbedtls_pk_parse_key(&pkey->key, buf, blen, NULL, 0);
-+}
-+static inline int apk_mbedtls_sign(struct apk_digest_ctx *dctx, struct apk_digest *dig,
-+ unsigned char *sig, size_t *sig_len)
-+{
-+ return mbedtls_pk_sign(&dctx->sigver_key->key, apk_digest_alg_to_mbedtls_type(dctx->alg),
-+ (const unsigned char *)&dig->data, dig->len, sig, sig_len, apk_random, NULL);
-+}
-+#endif
-+
-+int apk_pkey_load(struct apk_pkey *pkey, int dirfd, const char *fn)
-+{
-+ unsigned char *buf = NULL;
-+ size_t blen = 0;
-+ int ret;
-+
-+ if (apk_load_file_at(dirfd, fn, &buf, &blen))
-+ return -APKE_CRYPTO_ERROR;
-+
-+ mbedtls_pk_init(&pkey->key);
-+ if ((ret = mbedtls_pk_parse_public_key(&pkey->key, buf, blen)) != 0)
-+ ret = apk_mbedtls_parse_privkey(pkey, buf, blen);
-+
-+ mbedtls_platform_zeroize(buf, blen);
-+ mbedtls_free(buf);
-+ if (ret != 0)
-+ return -APKE_CRYPTO_KEY_FORMAT;
-+
-+ return apk_pkey_init(pkey);
-+}
-+
-+int apk_sign_start(struct apk_digest_ctx *dctx, uint8_t alg, struct apk_pkey *pkey)
-+{
-+ if (apk_digest_ctx_reset_alg(dctx, alg))
-+ return -APKE_CRYPTO_ERROR;
-+
-+ dctx->sigver_key = pkey;
-+
-+ return 0;
-+}
-+
-+int apk_sign(struct apk_digest_ctx *dctx, void *sig, size_t *len)
-+{
-+ struct apk_digest dig;
-+ int r = 0;
-+
-+ if (apk_digest_ctx_final(dctx, &dig))
-+ return -APKE_SIGNATURE_GEN_FAILURE;
-+
-+ if (apk_mbedtls_sign(dctx, &dig, sig, len))
-+ r = -APKE_SIGNATURE_GEN_FAILURE;
-+
-+ dctx->sigver_key = NULL;
-+ return r;
-+}
-+
-+int apk_verify_start(struct apk_digest_ctx *dctx, uint8_t alg, struct apk_pkey *pkey)
-+{
-+ if (apk_digest_ctx_reset_alg(dctx, alg))
-+ return -APKE_CRYPTO_ERROR;
-+
-+ dctx->sigver_key = pkey;
-+
-+ return 0;
-+}
-+
-+int apk_verify(struct apk_digest_ctx *dctx, void *sig, size_t len)
-+{
-+ struct apk_digest dig;
-+ int r = 0;
-+
-+ if (apk_digest_ctx_final(dctx, &dig))
-+ return -APKE_SIGNATURE_GEN_FAILURE;
-+
-+ if (mbedtls_pk_verify(&dctx->sigver_key->key, apk_digest_alg_to_mbedtls_type(dctx->alg),
-+ (const unsigned char *)&dig.data, dig.len, sig, len))
-+ r = -APKE_SIGNATURE_INVALID;
-+
-+ dctx->sigver_key = NULL;
-+ return r;
-+}
-+
-+static void apk_crypto_cleanup(void)
-+{
-+#ifdef MBEDTLS_PSA_CRYPTO_C
-+ mbedtls_psa_crypto_free();
-+#endif
-+}
-+
-+void apk_crypto_init(void)
-+{
-+ atexit(apk_crypto_cleanup);
-+
-+#ifdef MBEDTLS_PSA_CRYPTO_C
-+ psa_crypto_init();
-+#endif
-+}
-diff --git a/src/meson.build b/src/meson.build
-index 38e9d3b0..e1204fc0 100644
---- a/src/meson.build
-+++ b/src/meson.build
-@@ -1,3 +1,4 @@
-+crypto_backend = get_option('crypto_backend')
- url_backend = get_option('url_backend')
-
- libapk_so_version = '2.99.0'
-@@ -15,7 +16,7 @@ libapk_src = [
- 'common.c',
- 'context.c',
- 'crypto.c',
-- 'crypto_openssl.c',
-+ 'crypto_@0@.c'.format(crypto_backend),
- 'ctype.c',
- 'database.c',
- 'extract_v2.c',
-@@ -40,7 +41,7 @@ libapk_headers = [
- 'apk_atom.h',
- 'apk_blob.h',
- 'apk_crypto.h',
-- 'apk_crypto_openssl.h',
-+ 'apk_crypto_@0@.h'.format(crypto_backend),
- 'apk_ctype.h',
- 'apk_database.h',
- 'apk_defines.h',
-@@ -89,6 +90,17 @@ apk_src = [
- 'applet.c',
- ]
-
-+apk_cargs = [
-+ '-DAPK_VERSION="' + meson.project_version() + '"',
-+ '-D_ATFILE_SOURCE',
-+]
-+
-+if crypto_backend == 'openssl'
-+ apk_cargs += [ '-DCRYPTO_USE_OPENSSL' ]
-+elif crypto_backend == 'mbedtls'
-+ apk_cargs += [ '-DCRYPTO_USE_MBEDTLS' ]
-+endif
-+
- if lua_bin.found()
- genhelp_script = files('genhelp.lua')
- genhelp_args = [lua_bin, genhelp_script, '@INPUT@']
-@@ -115,11 +127,6 @@ endif
-
- apk_src += [ generated_help ]
-
--apk_cargs = [
-- '-DAPK_VERSION="' + meson.project_version() + '"',
-- '-D_ATFILE_SOURCE',
--]
--
- apk_arch_prefix = get_option('arch_prefix')
- if apk_arch_prefix != ''
- apk_cargs += ['-DAPK_ARCH_PREFIX="@0@"'.format(apk_arch_prefix)]
---
-GitLab
-
-
-From 34bb1021284dccbf97f02b0a0bb9e751b8887cad Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Tue, 16 Apr 2024 17:56:45 +0200
-Subject: [PATCH 4/4] add option to configure crypto backend in legacy make
- build system
-
-Define CRYPTO to select mbedtls as alternative crypto backend. By
-default openssl is used.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
----
- src/Makefile | 20 +++++++++++++++-----
- 1 file changed, 15 insertions(+), 5 deletions(-)
-
-diff --git a/src/Makefile b/src/Makefile
-index efdc68df..97db0e72 100644
---- a/src/Makefile
-+++ b/src/Makefile
-@@ -20,9 +20,9 @@ libapk_soname := 2.99.0
- libapk_so := $(obj)/libapk.so.$(libapk_soname)
- libapk.so.$(libapk_soname)-objs := \
- adb.o adb_comp.o adb_walk_adb.o adb_walk_genadb.o adb_walk_gentext.o adb_walk_text.o apk_adb.o \
-- atom.o blob.o commit.o common.o context.o crypto.o crypto_openssl.o ctype.o database.o hash.o \
-- extract_v2.o extract_v3.o fs_fsys.o fs_uvol.o io.o io_gunzip.o tar.o package.o pathbuilder.o \
-- print.o solver.o trust.o version.o
-+ atom.o blob.o commit.o common.o context.o crypto.o ctype.o database.o hash.o extract_v2.o \
-+ extract_v3.o fs_fsys.o fs_uvol.o io.o io_gunzip.o tar.o package.o pathbuilder.o print.o \
-+ solver.o trust.o version.o
-
- libapk.so.$(libapk_soname)-libs :=
-
-@@ -34,6 +34,16 @@ libapk.so.$(libapk_soname)-objs += io_url_libfetch.o
- libapk.so.$(libapk_soname)-libs += libfetch/libfetch.a
- endif
-
-+ifeq ($(CRYPTO),mbedtls)
-+CRYPTO_CFLAGS := $(shell $(PKG_CONFIG) --cflags mbedtls mbedcrypto) -DCRYPTO_USE_MBEDTLS
-+CRYPTO_LIBS := $(shell $(PKG_CONFIG) --libs mbedtls mbedcrypto)
-+libapk.so.$(libapk_soname)-objs += crypto_mbedtls.o
-+else
-+CRYPTO_CFLAGS := $(shell $(PKG_CONFIG) --cflags openssl) -DCRYPTO_USE_OPENSSL
-+CRYPTO_LIBS := $(shell $(PKG_CONFIG) --libs openssl)
-+libapk.so.$(libapk_soname)-objs += crypto_openssl.o
-+endif
-+
- # ZSTD support can be disabled
- ifneq ($(ZSTD),no)
- ZSTD_CFLAGS := $(shell $(PKG_CONFIG) --cflags libzstd)
-@@ -100,9 +110,9 @@ LIBS_apk.static := -Wl,--as-needed -ldl -Wl,--no-as-needed
- LDFLAGS_apk += -L$(obj)
- LDFLAGS_apk-test += -L$(obj)
-
--CFLAGS_ALL += $(OPENSSL_CFLAGS) $(ZLIB_CFLAGS) $(ZSTD_CFLAGS)
-+CFLAGS_ALL += $(CRYPTO_CFLAGS) $(ZLIB_CFLAGS) $(ZSTD_CFLAGS)
- LIBS := -Wl,--as-needed \
-- $(OPENSSL_LIBS) $(ZLIB_LIBS) $(ZSTD_LIBS) \
-+ $(CRYPTO_LIBS) $(ZLIB_LIBS) $(ZSTD_LIBS) \
- -Wl,--no-as-needed
-
- # Help generation
---
-GitLab
iucode_tool.c | 1 +
1 file changed, 1 insertion(+)
-diff --git a/iucode_tool.c b/iucode_tool.c
-index 4bba5db..0246035 100644
--- a/iucode_tool.c
+++ b/iucode_tool.c
@@ -19,6 +19,7 @@
#include <fcntl.h>
#include <stdio.h>
#include <stdlib.h>
---
-2.37.2
-
-Index: refpolicy-2.20200229/Makefile
-===================================================================
---- refpolicy-2.20200229.orig/Makefile
-+++ refpolicy-2.20200229/Makefile
+--- a/Makefile
++++ b/Makefile
@@ -648,6 +648,6 @@ ifneq ($(generated_fc),)
endif
endif
$(eval $(call BuildPackage,rpcd))
$(eval $(call BuildPlugin,file,,Provides ubus calls for file and directory operations.))
$(eval $(call BuildPlugin,rpcsys,,Provides ubus calls for sysupgrade and password changing.))
-$(eval $(call BuildPlugin,iwinfo,+libiwinfo,Provides ubus calls for accessing iwinfo data.,libiwinfo (>= 2023-01-21)))
+$(eval $(call BuildPlugin,iwinfo,+libiwinfo,Provides ubus calls for accessing iwinfo data.,libiwinfo (>=2023.01.21)))
$(eval $(call BuildPlugin,ucode,+libucode,Allows implementing plugins using ucode scripts.))
--- /dev/null
+include $(TOPDIR)/rules.mk
+
+PKG_NAME:=dns320l-mcu
+PKG_RELEASE:=1
+
+PKG_SOURCE_PROTO:=git
+PKG_SOURCE_URL=https://github.com/wigyori/dns320l-daemon.git
+PKG_SOURCE_DATE:=2024-05-11
+PKG_SOURCE_VERSION:=c74941880e0a8d2bc0344b3256b984397512e8c3
+PKG_MIRROR_HASH:=e0f186a0c139ccfac3d311f49e2fecdbd02fa3f9fe6ced4b1ce0baa603d49fc3
+PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
+PKG_LICENSE:=GPL-3.0+
+
+include $(INCLUDE_DIR)/package.mk
+
+define Package/dns320l-mcu
+ SECTION:=utils
+ CATEGORY:=Utilities
+ TITLE:=Utility to control the MCU on DNS-320L
+ DEPENDS:=@TARGET_kirkwood
+ URL:=https://github.com/wigyori/dns320l-mcu
+endef
+
+define Build/Compile
+ $(MAKE) -C $(PKG_BUILD_DIR) \
+ CC="$(TARGET_CC)" \
+ CFLAGS="$(TARGET_CFLAGS) -Wall"
+endef
+
+define Package/dns320l-mcu/install
+ $(INSTALL_DIR) $(1)/usr/bin $(1)/etc/init.d
+ $(INSTALL_BIN) ./files/dns320l-mcu.init $(1)/etc/init.d/dns320l-mcu
+ $(INSTALL_BIN) $(PKG_BUILD_DIR)/dns320l-daemon $(1)/usr/bin/dns320l-mcu
+endef
+
+$(eval $(call BuildPackage,dns320l-mcu))
--- /dev/null
+#!/bin/sh /etc/rc.common
+# Copyright (c) 2024 OpenWrt.org
+
+START=99
+
+USE_PROCD=1
+PROG=/usr/bin/dns320l-mcu
+
+start_service() {
+ procd_open_instance
+ procd_set_param command "$PROG"
+ procd_set_param respawn
+ procd_close_instance
+}
HOST_BUILD_DEPENDS:=libsepol/host
PKG_MAINTAINER:=Dominick Grift <dominick.grift@defensec.nl>
-PKG_CPE_ID:=cpe:/a:selinuxproject:secilc
PKG_LICENSE:=BSD-2-Clause
PKG_LICENSE_FILES:=COPYING
--- /dev/null
+# Huawei E5785
+TargetVendor=0x3426
+TargetProduct=0x14db
+HuaweiNewMode=1
HOST_LDFLAGS:=-L$(STAGING_DIR_HOST)/lib $(if $(IS_PACKAGE_BUILD),-L$(STAGING_DIR_HOSTPKG)/lib -L$(STAGING_DIR)/host/lib)
BUILD_KEY=$(TOPDIR)/key-build
+BUILD_KEY_APK_SEC=$(TOPDIR)/private-key.pem
+BUILD_KEY_APK_PUB=$(TOPDIR)/public-key.pem
FAKEROOT:=$(STAGING_DIR_HOST)/bin/fakeroot
push @mirrors, "https://raw.githubusercontent.com/$1";
}
} elsif ($mirror =~ /^\@GNU\/(.+)$/) {
+ push @mirrors, "https://ftpmirror.gnu.org/$1";
push @mirrors, "https://mirror.csclub.uwaterloo.ca/gnu/$1";
push @mirrors, "https://mirror.netcologne.de/gnu/$1";
push @mirrors, "https://ftp.kddilabs.jp/GNU/gnu/$1";
push @mirrors, "https://mirrors.tuna.tsinghua.edu.cn/gnu/$1";
push @mirrors, "https://mirrors.ustc.edu.cn/gnu/$1";
} elsif ($mirror =~ /^\@SAVANNAH\/(.+)$/) {
+ push @mirrors, "https://download.savannah.nongnu.org/releases/$1";
push @mirrors, "https://mirror.netcologne.de/savannah/$1";
push @mirrors, "https://mirror.csclub.uwaterloo.ca/nongnu/$1";
push @mirrors, "https://ftp.acc.umu.se/mirror/gnu.org/savannah/$1";
printf "\t\tdepends on PER_FEED_REPO\n";
printf "\t\tdefault y\n" if $installed;
printf "\t\thelp\n";
- printf "\t\t Enable the \\\"%s\\\" feed in opkg distfeeds.conf.\n", $feed->[1];
+ printf "\t\t Enable the \\\"%s\\\" feed in opkg distfeeds.conf and apk repositories.\n", $feed->[1];
printf "\t\t Say M to add the feed commented out.\n";
printf "\n";
}
-s : List of feed names and their URL.
-r <feedname>: List packages of specified feed.
-d <delimiter>: Use specified delimiter to distinguish rows (default: spaces)
- -f : List feeds in feeds.conf compatible format (when using -s).
+ -f : List feeds in opkg feeds.conf compatible format (when using -s).
install [options] <package>: Install a package
Options:
*)
BRANCH="$(git rev-parse --abbrev-ref HEAD)"
ORIGIN="$(git rev-parse --verify --symbolic-full-name ${BRANCH}@{u} 2>/dev/null)"
- [ -n "$ORIGIN" ] || ORIGIN="$(git rev-parse --verify --symbolic-full-name master@{u} 2>/dev/null)"
+ [ -n "$ORIGIN" ] || ORIGIN="$(git rev-parse --verify --symbolic-full-name main@{u} 2>/dev/null)"
REV="$(git rev-list ${REBOOT}..$GET_REV 2>/dev/null | wc -l | awk '{print $1}')"
if [ -n "$ORIGIN" ]; then
sub gen_condition ($) {
my $condition = shift;
- # remove '!()', just as include/package-ipkg.mk does
+ # remove '!()', just as include/package-pack.mk does
$condition =~ s/[()!]//g;
return join("", map(and_condition($_), split('\|\|', $condition)));
}
if ($image_packages{$name}) {
$version = $image_packages{$name};
}
- $version =~ s/-\d+$// if $version;
+ $version =~ s/-r\d+$// if $version;
if ($name =~ /^(kernel|kmod-)/ and $version =~ /^(\d+\.\d+\.\d+)/) {
$version = $1;
}
}
my $version = $pkg->{version};
- $version =~ s/-\d+$// if $version;
+ $version =~ s/-r\d+$// if $version;
if ($name =~ /^(kernel|kmod-)/ and $version =~ /^(\d+\.\d+\.\d+)/) {
$version = $1;
}
BUNDLER_PATH := $(subst $(space),:,$(filter-out $(TOPDIR)/%,$(subst :,$(space),$(PATH))))
BUNDLER_COMMAND := PATH=$(BUNDLER_PATH) $(XARGS) $(SCRIPT_DIR)/bundle-libraries.sh $(PKG_BUILD_DIR)/staging_dir/host
+PACKAGE_SUFFIX:=$(if $(CONFIG_USE_APK),apk,ipk)
+
all: compile
$(BIN_DIR)/$(IB_NAME).tar.zst: clean
$(INCLUDE_DIR) $(SCRIPT_DIR) \
$(TOPDIR)/rules.mk \
./files/Makefile \
- ./files/repositories.conf \
$(TMP_DIR)/.targetinfo \
$(TMP_DIR)/.packageinfo \
$(PKG_BUILD_DIR)/
-ifeq ($(CONFIG_IB_STANDALONE),)
+ $(INSTALL_DIR) $(PKG_BUILD_DIR)/packages
+
+ifneq ($(CONFIG_USE_APK),)
+ ifeq ($(CONFIG_IB_STANDALONE),)
+ $(call FeedSourcesAppendAPK,$(PKG_BUILD_DIR)/repositories)
+ $(VERSION_SED_SCRIPT) $(PKG_BUILD_DIR)/repositories
+ endif
+
+ $(INSTALL_DATA) ./files/README.apk.md $(PKG_BUILD_DIR)/packages/README.md
+else
+ ifeq ($(CONFIG_IB_STANDALONE),)
echo '## Remote package repositories' >> $(PKG_BUILD_DIR)/repositories.conf
- $(call FeedSourcesAppend,$(PKG_BUILD_DIR)/repositories.conf)
+ $(call FeedSourcesAppendOPKG,$(PKG_BUILD_DIR)/repositories.conf)
$(VERSION_SED_SCRIPT) $(PKG_BUILD_DIR)/repositories.conf
-endif
- $(INSTALL_DIR) $(PKG_BUILD_DIR)/packages
+ endif
+
# create an empty package index so `opkg` doesn't report an error
touch $(PKG_BUILD_DIR)/packages/Packages
- $(INSTALL_DATA) ./files/README.md $(PKG_BUILD_DIR)/packages/
+ $(INSTALL_DATA) ./files/README.opkg.md $(PKG_BUILD_DIR)/packages/README.md
echo '' >> $(PKG_BUILD_DIR)/repositories.conf
echo '## This is the local package repository, do not remove!' >> $(PKG_BUILD_DIR)/repositories.conf
echo 'src imagebuilder file:packages' >> $(PKG_BUILD_DIR)/repositories.conf
+endif
ifeq ($(CONFIG_BUILDBOT),)
ifeq ($(CONFIG_IB_STANDALONE),)
$(FIND) $(call FeedPackageDir,libc) -type f \
- \( -name 'libc_*.ipk' -or -name 'kernel_*.ipk' -or -name 'kmod-*.ipk' \) \
+ \( -name 'libc_*.$(PACKAGE_SUFFIX)' -or -name 'kernel_*.$(PACKAGE_SUFFIX)' -or -name 'kmod-*.$(PACKAGE_SUFFIX)' \) \
-exec $(CP) -t $(PKG_BUILD_DIR)/packages {} +
else
- $(FIND) $(wildcard $(PACKAGE_SUBDIRS)) -type f -name '*.ipk' \
+ $(FIND) $(wildcard $(PACKAGE_SUBDIRS)) -type f -name '*.$(PACKAGE_SUFFIX)' \
-exec $(CP) -t $(PKG_BUILD_DIR)/packages/ {} +
endif
else
$(FIND) $(call FeedPackageDir,libc) -type f \
- \( -name 'libc_*.ipk' -or -name 'kernel_*.ipk' \) \
+ \( -name 'libc_*.$(PACKAGE_SUFFIX)' -or -name 'kernel_*.$(PACKAGE_SUFFIX)' \) \
-exec $(CP) -t $(IB_LDIR)/ {} +
endif
+ifneq ($(CONFIG_USE_APK),y)
ifneq ($(CONFIG_SIGNATURE_CHECK),)
echo '' >> $(PKG_BUILD_DIR)/repositories.conf
echo 'option check_signature' >> $(PKG_BUILD_DIR)/repositories.conf
$(INSTALL_DIR) $(PKG_BUILD_DIR)/keys
$(CP) -L $(STAGING_DIR_ROOT)/etc/opkg/keys/ $(PKG_BUILD_DIR)/
$(CP) -L $(STAGING_DIR_ROOT)/usr/sbin/opkg-key $(PKG_BUILD_DIR)/scripts/
+endif
endif
$(CP) -L $(TOPDIR)/target/linux/Makefile $(PKG_BUILD_DIR)/target/linux
# override variables from rules.mk
PACKAGE_DIR:=$(TOPDIR)/packages
LISTS_DIR:=$(subst $(space),/,$(patsubst %,..,$(subst /,$(space),$(TARGET_DIR))))$(DL_DIR)
+PACKAGE_DIR_ALL:=$(TOPDIR)/packages
+
export OPKG_KEYS:=$(TOPDIR)/keys
OPKG:=$(call opkg,$(TARGET_DIR)) \
-f $(TOPDIR)/repositories.conf \
--cache $(DL_DIR) \
--lists-dir $(LISTS_DIR)
+APK:=$(call apk,$(TARGET_DIR)) \
+ --cache-dir $(DL_DIR) \
+ --allow-untrusted
+
+
include $(INCLUDE_DIR)/target.mk
-include .profiles.mk
mkdir -p $(TARGET_DIR) $(BIN_DIR) $(TMP_DIR) $(DL_DIR)
$(MAKE) package_reload >/dev/null
$(MAKE) package_install >/dev/null
+ifeq ($(CONFIG_USE_APK),)
$(OPKG) list-installed $(if $(STRIP_ABI),--strip-abi)
+else
+ $(APK) list --quiet --manifest --no-network
+endif
package_index: FORCE
@echo >&2
@echo Building package index... >&2
@mkdir -p $(TMP_DIR) $(TARGET_DIR)/tmp
+ifeq ($(CONFIG_USE_APK),)
(cd $(PACKAGE_DIR); $(SCRIPT_DIR)/ipkg-make-index.sh . > Packages && \
gzip -9nc Packages > Packages.gz; \
$(if $(CONFIG_SIGNATURE_CHECK), \
$(STAGING_DIR_HOST)/bin/usign -S -m Packages -s $(BUILD_KEY)) \
) >/dev/null 2>/dev/null
$(OPKG) update >&2 || true
+else
+ (cd $(PACKAGE_DIR); $(APK) mkndx --output packages.adb *.apk) >&2
+endif
package_reload:
+ifeq ($(CONFIG_USE_APK),)
if [ -d "$(PACKAGE_DIR)" ] && ( \
[ ! -f "$(PACKAGE_DIR)/Packages" ] || \
[ ! -f "$(PACKAGE_DIR)/Packages.gz" ] || \
mkdir -p $(TARGET_DIR)/tmp; \
$(OPKG) update >&2 || true; \
fi
+else
+ if [ -d "$(PACKAGE_DIR)" ] && ( \
+ [ ! -f "$(PACKAGE_DIR)/packages.adb" ] || \
+ [ "`find $(PACKAGE_DIR) -cnewer $(PACKAGE_DIR)/packages.adb`" ] ); then \
+ echo "Package list missing or not up-to-date, generating it." >&2 ;\
+ $(MAKE) package_index; \
+ else \
+ mkdir -p $(TARGET_DIR)/tmp; \
+ $(APK) update >&2 || true; \
+ fi
+endif
package_list: FORCE
@$(MAKE) -s package_reload
+ifeq ($(CONFIG_USE_APK),)
@$(OPKG) list --size 2>/dev/null
+else
+ @$(APK) list --size 2>/dev/null
+endif
package_install: FORCE
@echo
@echo Installing packages...
+ifeq ($(CONFIG_USE_APK),)
$(OPKG) install $(firstword $(wildcard $(LINUX_DIR)/libc_*.ipk $(PACKAGE_DIR)/libc_*.ipk))
$(OPKG) install $(firstword $(wildcard $(LINUX_DIR)/kernel_*.ipk $(PACKAGE_DIR)/kernel_*.ipk))
$(OPKG) install $(BUILD_PACKAGES)
+else
+ $(APK) add --initdb --no-scripts $(firstword $(wildcard $(LINUX_DIR)/libc-*.apk $(PACKAGE_DIR)/libc_*.apk))
+ $(APK) add --no-scripts $(firstword $(wildcard $(LINUX_DIR)/kernel-*.apk $(PACKAGE_DIR)/kernel_*.apk))
+ $(APK) add --no-scripts $(BUILD_PACKAGES)
+endif
prepare_rootfs: FORCE
@echo
@echo Finalizing root filesystem...
$(CP) $(TARGET_DIR) $(TARGET_DIR_ORIG)
+ifeq ($(CONFIG_USE_APK),)
$(if $(CONFIG_SIGNATURE_CHECK), \
$(if $(ADD_LOCAL_KEY), \
OPKG_KEYS=$(TARGET_DIR)/etc/opkg/keys/ \
$(SCRIPT_DIR)/opkg-key add $(BUILD_KEY).pub \
) \
)
+endif
$(call prepare_rootfs,$(TARGET_DIR),$(USER_FILES),$(DISABLED_SERVICES))
build_image: FORCE
endif
_check_keys: FORCE
+ifeq ($(CONFIG_USE_APK),)
ifneq ($(CONFIG_SIGNATURE_CHECK),)
@if [ ! -s $(BUILD_KEY) -o ! -s $(BUILD_KEY).pub ]; then \
echo Generate local signing keys... >&2; \
-s $(BUILD_KEY); \
fi
endif
+else
+ # TODO
+endif
image:
$(MAKE) -s _check_profile
@exit 1
endif
@$(MAKE) -s package_reload
- @$(OPKG) whatdepends -A $(PACKAGE)
+ifeq ($(CONFIG_USE_APK),)
+ @$(OPKG) list --depends $(PACKAGE)
+else
+ @$(APK) list --depends $(PACKAGE)
+endif
package_depends: FORCE
ifeq ($(PACKAGE),)
@exit 1
endif
@$(MAKE) -s package_reload
+ifeq ($(CONFIG_USE_APK),)
@$(OPKG) depends -A $(PACKAGE)
-
+else
+ @$(OPKG) whatdepends -A $(PACKAGE)
+endif
.SILENT: help info image manifest package_whatdepends package_depends
--- /dev/null
+# ./packages folder
+
+Add `.apk` packages to this folder will allow the ImageBuilder to install them.
+
+For more complex setups consider adding a custom feed containing packages.
+
+ file:///path/to/Packages.adb
+
+Whenever the ImageBuilder builds a firmware image this folder will be reloaded
+and a new package index created.
+++ /dev/null
-# ./packages folder
-
-Add `.ipk` packages to this folder will allow the ImageBuilder to install them.
-
-For more complex setups consider adding a custom feed containing packages.
-
- src custom file:///path/to/packages
-
-Whenever the ImageBuilder builds a firmware image this folder will be reloaded
-and a new package index created. In case signature checks are enabled the
-`./packages/Packages` index will be signed with a locally generated key pair.
--- /dev/null
+# ./packages folder
+
+Add `.ipk` packages to this folder will allow the ImageBuilder to install them.
+
+For more complex setups consider adding a custom feed containing packages.
+
+ src custom file:///path/to/packages
+
+Whenever the ImageBuilder builds a firmware image this folder will be reloaded
+and a new package index created. In case signature checks are enabled the
+`./packages/Packages` index will be signed with a locally generated key pair.
FEATURES:=fpu pci pcie rtc usb boot-part rootfs-part
FEATURES+=cpiogz ext4 ramdisk squashfs targz vmdk
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_V6_V7=y
-CONFIG_ARCH_MULTI_V7=y
-CONFIG_ARCH_MMAP_RND_BITS=8
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_VIRT=y
-CONFIG_ARM=y
-CONFIG_ARM_CPU_SUSPEND=y
-CONFIG_ARM_HAS_SG_CHAIN=y
-CONFIG_ARM_HEAVY_MB=y
-# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_ARM_LPAE=y
-CONFIG_ARM_PATCH_IDIV=y
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_PSCI=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ARM_VIRT_EXT=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_CACHE_L2X0=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_SPECTRE=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_V7=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
-CONFIG_DMA_OPS=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_VDSO_32=y
-CONFIG_HARDEN_BRANCH_PREDICTOR=y
-CONFIG_HAVE_SMP=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_MIGHT_HAVE_CACHE_L2X0=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_NEON=y
-CONFIG_NR_CPUS=4
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-CONFIG_OUTER_CACHE=y
-CONFIG_OUTER_CACHE_SYNC=y
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SMP_ON_UP=y
-CONFIG_SWP_EMULATE=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USE_OF=y
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_ZBOOT_ROM_TEXT=0
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_ACPI_APEI=y
-CONFIG_ACPI_HMAT=y
-CONFIG_ACPI_PCC=y
-CONFIG_AHCI_IMX=y
-CONFIG_AHCI_MVEBU=y
-CONFIG_AHCI_QORIQ=y
-CONFIG_AMPERE_ERRATUM_AC03_CPU_38=y
-CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM2835=y
-# CONFIG_ARCH_BCMBCA is not set
-CONFIG_ARCH_BCM_IPROC=y
-CONFIG_ARCH_BRCMSTB=y
-CONFIG_ARCH_HISI=y
-CONFIG_ARCH_INTEL_SOCFPGA=y
-CONFIG_ARCH_LAYERSCAPE=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_MVEBU=y
-CONFIG_ARCH_MXC=y
-CONFIG_ARCH_NXP=y
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_R8A774A1=y
-CONFIG_ARCH_R8A774B1=y
-CONFIG_ARCH_R8A774C0=y
-CONFIG_ARCH_R8A774E1=y
-# CONFIG_ARCH_R8A77950 is not set
-# CONFIG_ARCH_R8A77951 is not set
-# CONFIG_ARCH_R8A77960 is not set
-# CONFIG_ARCH_R8A77961 is not set
-# CONFIG_ARCH_R8A77965 is not set
-# CONFIG_ARCH_R8A77970 is not set
-# CONFIG_ARCH_R8A77980 is not set
-# CONFIG_ARCH_R8A77990 is not set
-# CONFIG_ARCH_R8A77995 is not set
-# CONFIG_ARCH_R8A779A0 is not set
-# CONFIG_ARCH_R8A779F0 is not set
-# CONFIG_ARCH_R8A779G0 is not set
-CONFIG_ARCH_R9A07G043=y
-CONFIG_ARCH_R9A07G044=y
-CONFIG_ARCH_R9A07G054=y
-CONFIG_ARCH_R9A09G011=y
-CONFIG_ARCH_RENESAS=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_SYNQUACER=y
-CONFIG_ARCH_THUNDER=y
-CONFIG_ARCH_THUNDER2=y
-CONFIG_ARCH_VEXPRESS=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARCH_ZYNQMP=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-CONFIG_ARM64_AMU_EXTN=y
-CONFIG_ARM64_BTI=y
-CONFIG_ARM64_CNP=y
-CONFIG_ARM64_CRYPTO=y
-CONFIG_ARM64_E0PD=y
-CONFIG_ARM64_EPAN=y
-CONFIG_ARM64_ERRATUM_1024718=y
-CONFIG_ARM64_ERRATUM_1165522=y
-CONFIG_ARM64_ERRATUM_1286807=y
-CONFIG_ARM64_ERRATUM_1319367=y
-CONFIG_ARM64_ERRATUM_1418040=y
-CONFIG_ARM64_ERRATUM_1463225=y
-CONFIG_ARM64_ERRATUM_1508412=y
-CONFIG_ARM64_ERRATUM_1530923=y
-CONFIG_ARM64_ERRATUM_1542419=y
-CONFIG_ARM64_ERRATUM_1742098=y
-CONFIG_ARM64_ERRATUM_2051678=y
-CONFIG_ARM64_ERRATUM_2054223=y
-CONFIG_ARM64_ERRATUM_2067961=y
-CONFIG_ARM64_ERRATUM_2077057=y
-CONFIG_ARM64_ERRATUM_2441007=y
-CONFIG_ARM64_ERRATUM_2441009=y
-CONFIG_ARM64_ERRATUM_2457168=y
-CONFIG_ARM64_ERRATUM_2658417=y
-CONFIG_ARM64_ERRATUM_819472=y
-CONFIG_ARM64_ERRATUM_824069=y
-CONFIG_ARM64_ERRATUM_826319=y
-CONFIG_ARM64_ERRATUM_827319=y
-CONFIG_ARM64_ERRATUM_832075=y
-CONFIG_ARM64_ERRATUM_834220=y
-CONFIG_ARM64_ERRATUM_843419=y
-CONFIG_ARM64_ERRATUM_845719=y
-CONFIG_ARM64_HW_AFDBM=y
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_MTE=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PAN=y
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_PTR_AUTH=y
-CONFIG_ARM64_PTR_AUTH_KERNEL=y
-CONFIG_ARM64_RAS_EXTN=y
-CONFIG_ARM64_SME=y
-CONFIG_ARM64_SVE=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_TLB_RANGE=y
-CONFIG_ARM64_VA_BITS=48
-CONFIG_ARM64_VA_BITS_48=y
-CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
-CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
-CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
-CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
-# CONFIG_ARMADA_37XX_RWTM_MBOX is not set
-CONFIG_ARMADA_37XX_WATCHDOG=y
-CONFIG_ARMADA_THERMAL=y
-CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
-# CONFIG_ARM_DMC620_PMU is not set
-# CONFIG_ARM_MHU_V2 is not set
-CONFIG_ARM_PSCI_CPUIDLE=y
-CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
-CONFIG_ARM_SBSA_WATCHDOG=y
-CONFIG_ARM_SCPI_POWER_DOMAIN=y
-CONFIG_ARM_SCPI_PROTOCOL=y
-CONFIG_ARM_SMCCC_SOC_ID=y
-CONFIG_ARM_SMC_WATCHDOG=y
-CONFIG_ARM_SMMU=y
-# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
-# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
-CONFIG_ARM_SMMU_V3=y
-# CONFIG_ARM_SMMU_V3_PMU is not set
-# CONFIG_ARM_SMMU_V3_SVA is not set
-CONFIG_ATOMIC64_SELFTEST=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-# CONFIG_AXI_DMAC is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BCM2711_THERMAL is not set
-CONFIG_BCM2835_MBOX=y
-CONFIG_BCM2835_POWER=y
-# CONFIG_BCM2835_THERMAL is not set
-# CONFIG_BCM2835_VCHIQ is not set
-CONFIG_BCM2835_WDT=y
-# CONFIG_BCMGENET is not set
-# CONFIG_BCM_CYGNUS_PHY is not set
-# CONFIG_BCM_FLEXRM_MBOX is not set
-# CONFIG_BCM_NS_THERMAL is not set
-# CONFIG_BCM_PDC_MBOX is not set
-# CONFIG_BCM_SR_THERMAL is not set
-CONFIG_BCM_VIDEOCORE=y
-# CONFIG_BGMAC_PLATFORM is not set
-CONFIG_BLK_PM=y
-# CONFIG_BRCMSTB_PM is not set
-# CONFIG_BRCMSTB_THERMAL is not set
-CONFIG_BRCM_USB_PINMAP=y
-CONFIG_CAVIUM_ERRATUM_22375=y
-CONFIG_CAVIUM_ERRATUM_23144=y
-CONFIG_CAVIUM_ERRATUM_23154=y
-CONFIG_CAVIUM_ERRATUM_27456=y
-CONFIG_CAVIUM_ERRATUM_30115=y
-CONFIG_CAVIUM_TX2_ERRATUM_219=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLK_BCM2711_DVP=y
-CONFIG_CLK_BCM2835=y
-CONFIG_CLK_BCM_NS2=y
-CONFIG_CLK_BCM_SR=y
-CONFIG_CLK_IMX8MM=y
-CONFIG_CLK_IMX8MN=y
-CONFIG_CLK_IMX8MP=y
-CONFIG_CLK_IMX8MQ=y
-CONFIG_CLK_IMX8QXP=y
-CONFIG_CLK_IMX8ULP=y
-CONFIG_CLK_IMX93=y
-CONFIG_CLK_INTEL_SOCFPGA=y
-CONFIG_CLK_INTEL_SOCFPGA64=y
-CONFIG_CLK_LS1028A_PLLDIG=y
-CONFIG_CLK_PX30=y
-CONFIG_CLK_QORIQ=y
-CONFIG_CLK_RASPBERRYPI=y
-CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
-CONFIG_CLK_RENESAS=y
-CONFIG_CLK_RK3308=y
-CONFIG_CLK_RK3328=y
-CONFIG_CLK_RK3368=y
-CONFIG_CLK_RK3399=y
-CONFIG_CLK_RK3568=y
-CONFIG_CLK_SP810=y
-CONFIG_CLK_SUNXI=y
-CONFIG_CLK_SUNXI_CLOCKS=y
-# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set
-# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set
-# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
-CONFIG_CLK_VEXPRESS_OSC=y
-CONFIG_CMA=y
-CONFIG_CMA_ALIGNMENT=8
-CONFIG_CMA_AREAS=19
-# CONFIG_CMA_DEBUG is not set
-# CONFIG_CMA_DEBUGFS is not set
-CONFIG_CMA_SIZE_MBYTES=32
-# CONFIG_CMA_SIZE_SEL_MAX is not set
-CONFIG_CMA_SIZE_SEL_MBYTES=y
-# CONFIG_CMA_SIZE_SEL_MIN is not set
-# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
-# CONFIG_CMA_SYSFS is not set
-# CONFIG_COMMON_CLK_FSL_FLEXSPI is not set
-# CONFIG_COMMON_CLK_FSL_SAI is not set
-CONFIG_COMMON_CLK_HI3516CV300=y
-CONFIG_COMMON_CLK_HI3519=y
-CONFIG_COMMON_CLK_HI3559A=y
-CONFIG_COMMON_CLK_HI3660=y
-CONFIG_COMMON_CLK_HI3670=y
-CONFIG_COMMON_CLK_HI3798CV200=y
-CONFIG_COMMON_CLK_HI6220=y
-CONFIG_COMMON_CLK_HI655X=y
-CONFIG_COMMON_CLK_ROCKCHIP=y
-CONFIG_COMMON_CLK_SCPI=y
-CONFIG_COMMON_CLK_ZYNQMP=y
-CONFIG_COMMON_RESET_HI3660=y
-CONFIG_COMMON_RESET_HI6220=y
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_PM=y
-CONFIG_CRYPTO_AES_ARM64=y
-CONFIG_CRYPTO_AES_ARM64_BS=y
-CONFIG_CRYPTO_AES_ARM64_CE=y
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
-CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
-CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y
-CONFIG_CRYPTO_ARCH_HAVE_LIB_CHACHA=y
-CONFIG_CRYPTO_CHACHA20=y
-CONFIG_CRYPTO_CHACHA20_NEON=y
-CONFIG_CRYPTO_CRYPTD=y
-# CONFIG_CRYPTO_DEV_ALLWINNER is not set
-# CONFIG_CRYPTO_DEV_BCM_SPU is not set
-# CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM is not set
-# CONFIG_CRYPTO_DEV_HISI_HPRE is not set
-# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set
-# CONFIG_CRYPTO_DEV_HISI_TRNG is not set
-# CONFIG_CRYPTO_DEV_OCTEONTX2_CPT is not set
-# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
-# CONFIG_CRYPTO_DEV_ZYNQMP_AES is not set
-# CONFIG_CRYPTO_DEV_ZYNQMP_SHA3 is not set
-CONFIG_CRYPTO_GHASH_ARM64_CE=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_CHACHA_GENERIC=y
-CONFIG_CRYPTO_POLYVAL_ARM64_CE=y
-CONFIG_CRYPTO_SHA1=y
-CONFIG_CRYPTO_SHA1_ARM64_CE=y
-CONFIG_CRYPTO_SHA256_ARM64=y
-CONFIG_CRYPTO_SHA2_ARM64_CE=y
-CONFIG_CRYPTO_SHA512_ARM64=y
-CONFIG_CRYPTO_SIMD=y
-# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set
-# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set
-# CONFIG_DEV_DAX_HMEM is not set
-CONFIG_DMA_BCM2835=y
-CONFIG_DMA_CMA=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DMA_SUN6I=y
-CONFIG_DRM=y
-CONFIG_DRM_BOCHS=y
-CONFIG_DRM_BRIDGE=y
-# CONFIG_DRM_FSL_LDB is not set
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-# CONFIG_DRM_IMX8QM_LDB is not set
-# CONFIG_DRM_IMX8QXP_LDB is not set
-# CONFIG_DRM_IMX8QXP_PIXEL_COMBINER is not set
-# CONFIG_DRM_IMX8QXP_PIXEL_LINK is not set
-# CONFIG_DRM_IMX8QXP_PIXEL_LINK_TO_DPI is not set
-# CONFIG_DRM_IMX_DCSS is not set
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_QXL=y
-# CONFIG_DRM_RCAR_DU is not set
-# CONFIG_DRM_ROCKCHIP is not set
-CONFIG_DRM_TTM=y
-CONFIG_DRM_TTM_HELPER=y
-# CONFIG_DRM_V3D is not set
-CONFIG_DRM_VIRTIO_GPU=y
-CONFIG_DRM_VRAM_HELPER=y
-# CONFIG_DWMAC_SUN8I is not set
-# CONFIG_DWMAC_SUNXI is not set
-CONFIG_DW_WATCHDOG=y
-CONFIG_EFI_CAPSULE_LOADER=y
-CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y
-CONFIG_EFI_SOFT_RESERVE=y
-CONFIG_EFI_VARS_PSTORE=y
-# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set
-CONFIG_FB=y
-CONFIG_FB_ARMCLCD=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_MX3=y
-# CONFIG_FB_SH_MOBILE_LCDC is not set
-# CONFIG_FB_XILINX is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_FSL_DPAA is not set
-# CONFIG_FSL_DPAA2_QDMA is not set
-CONFIG_FSL_ERRATUM_A008585=y
-# CONFIG_FSL_IMX8_DDR_PMU is not set
-# CONFIG_FSL_PQ_MDIO is not set
-CONFIG_FUJITSU_ERRATUM_010001=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-# CONFIG_GIANFAR is not set
-CONFIG_GPIO_BCM_XGS_IPROC=y
-CONFIG_GPIO_BRCMSTB=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_MPC8XXX=y
-CONFIG_GPIO_MXC=y
-CONFIG_GPIO_RASPBERRYPI_EXP=y
-CONFIG_GPIO_ROCKCHIP=y
-CONFIG_GPIO_THUNDERX=y
-CONFIG_GPIO_XLP=y
-CONFIG_GPIO_ZYNQ=y
-CONFIG_GPIO_ZYNQMP_MODEPIN=y
-CONFIG_HDMI=y
-CONFIG_HI3660_MBOX=y
-CONFIG_HI6220_MBOX=y
-CONFIG_HISILICON_ERRATUM_161600802=y
-CONFIG_HISILICON_LPC=y
-CONFIG_HISI_PMU=y
-CONFIG_HISI_THERMAL=y
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_PCIE is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y
-# CONFIG_HW_RANDOM_HISI is not set
-CONFIG_HW_RANDOM_VIRTIO=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALTERA=y
-# CONFIG_I2C_BCM2835 is not set
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_HIX5HD2 is not set
-CONFIG_I2C_IMX=y
-CONFIG_I2C_IMX_LPI2C=y
-CONFIG_I2C_RIIC=y
-# CONFIG_I2C_RZV2M is not set
-# CONFIG_I2C_SLAVE_TESTUNIT is not set
-CONFIG_I2C_SYNQUACER=y
-CONFIG_I2C_THUNDERX=y
-# CONFIG_I2C_XLP9XX is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-# CONFIG_IMX2_WDT is not set
-# CONFIG_IMX8MM_THERMAL is not set
-# CONFIG_IMX8QXP_ADC is not set
-# CONFIG_IMX_DMA is not set
-# CONFIG_IMX_DSP is not set
-CONFIG_IMX_INTMUX=y
-CONFIG_IMX_IRQSTEER=y
-CONFIG_IMX_MBOX=y
-# CONFIG_IMX_MU_MSI is not set
-CONFIG_IMX_SCU=y
-CONFIG_IMX_SCU_PD=y
-# CONFIG_IMX_SC_THERMAL is not set
-# CONFIG_IMX_SC_WDT is not set
-# CONFIG_IMX_SDMA is not set
-# CONFIG_IMX_WEIM is not set
-# CONFIG_INPUT_HISI_POWERKEY is not set
-# CONFIG_INPUT_IBM_PANEL is not set
-# CONFIG_INTEL_STRATIX10_RSU is not set
-# CONFIG_INTEL_STRATIX10_SERVICE is not set
-CONFIG_INTERCONNECT=y
-CONFIG_INTERCONNECT_IMX=y
-CONFIG_INTERCONNECT_IMX8MM=y
-CONFIG_INTERCONNECT_IMX8MN=y
-CONFIG_INTERCONNECT_IMX8MP=y
-CONFIG_INTERCONNECT_IMX8MQ=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
-# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
-# CONFIG_IOMMU_IO_PGTABLE_DART is not set
-# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
-CONFIG_IOMMU_SUPPORT=y
-# CONFIG_IPMMU_VMSA is not set
-# CONFIG_K3_DMA is not set
-CONFIG_KCMP=y
-# CONFIG_KEYBOARD_IMX_SC_KEY is not set
-# CONFIG_KEYBOARD_SUN4I_LRADC is not set
-CONFIG_KSM=y
-CONFIG_KVM=y
-CONFIG_LCD_CLASS_DEVICE=m
-# CONFIG_LCD_PLATFORM is not set
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MARVELL_10G_PHY=y
-# CONFIG_MARVELL_CN10K_DDR_PMU is not set
-# CONFIG_MARVELL_CN10K_TAD_PMU is not set
-CONFIG_MDIO_BCM_IPROC=y
-CONFIG_MDIO_BUS_MUX_BCM_IPROC=y
-CONFIG_MDIO_SUN4I=y
-# CONFIG_MFD_ALTERA_A10SR is not set
-CONFIG_MFD_ALTERA_SYSMGR=y
-# CONFIG_MFD_AXP20X_RSB is not set
-CONFIG_MFD_CORE=y
-CONFIG_MFD_HI655X_PMIC=y
-# CONFIG_MFD_KHADAS_MCU is not set
-CONFIG_MFD_SUN4I_GPADC=y
-# CONFIG_MFD_SUN6I_PRCM is not set
-CONFIG_MFD_SYSCON=y
-CONFIG_MFD_VEXPRESS_SYSREG=y
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_MMC_BCM2835=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CAVIUM_THUNDERX=y
-CONFIG_MMC_DW=y
-# CONFIG_MMC_DW_BLUEFIELD is not set
-# CONFIG_MMC_DW_EXYNOS is not set
-# CONFIG_MMC_DW_HI3798CV200 is not set
-# CONFIG_MMC_DW_K3 is not set
-# CONFIG_MMC_DW_PCI is not set
-CONFIG_MMC_DW_PLTFM=y
-CONFIG_MMC_DW_ROCKCHIP=y
-# CONFIG_MMC_MXC is not set
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ACPI=y
-CONFIG_MMC_SDHCI_CADENCE=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_MMC_SDHCI_IPROC=y
-CONFIG_MMC_SDHCI_OF_ESDHC=y
-CONFIG_MMC_SDHCI_PCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHI=y
-CONFIG_MMC_SDHI_INTERNAL_DMAC=y
-# CONFIG_MMC_SDHI_SYS_DMAC is not set
-# CONFIG_MMC_SH_MMCIF is not set
-CONFIG_MMC_SUNXI=y
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MVNETA is not set
-# CONFIG_MVPP2 is not set
-# CONFIG_MV_XOR is not set
-# CONFIG_MX3_IPU is not set
-CONFIG_MXC_CLK=y
-CONFIG_MXC_CLK_SCU=y
-# CONFIG_MXS_DMA is not set
-CONFIG_NEED_SG_DMA_LENGTH=y
-# CONFIG_NET_VENDOR_ALLWINNER is not set
-CONFIG_NODES_SHIFT=4
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=256
-CONFIG_NUMA=y
-CONFIG_NUMA_BALANCING=y
-CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
-# CONFIG_NVHE_EL2_DEBUG is not set
-CONFIG_NVIDIA_CARMEL_CNP_ERRATUM=y
-# CONFIG_NVMEM_IMX_IIM is not set
-# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
-CONFIG_NVMEM_IMX_OCOTP_SCU=y
-# CONFIG_NVMEM_LAYERSCAPE_SFP is not set
-CONFIG_NVMEM_ROCKCHIP_EFUSE=y
-# CONFIG_NVMEM_ROCKCHIP_OTP is not set
-# CONFIG_NVMEM_SNVS_LPGPR is not set
-# CONFIG_NVMEM_SUNXI_SID is not set
-# CONFIG_NVMEM_ZYNQMP is not set
-CONFIG_PCC=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_ARMADA_8K=y
-CONFIG_PCIE_BRCMSTB=y
-CONFIG_PCIE_HISI_STB=y
-CONFIG_PCIE_IPROC_MSI=y
-CONFIG_PCIE_IPROC_PLATFORM=y
-CONFIG_PCIE_LAYERSCAPE=y
-CONFIG_PCIE_MOBIVEIL_PLAT=y
-# CONFIG_PCIE_RCAR_EP is not set
-CONFIG_PCIE_RCAR_HOST=y
-CONFIG_PCIE_ROCKCHIP=y
-# CONFIG_PCIE_ROCKCHIP_DW_HOST is not set
-CONFIG_PCIE_ROCKCHIP_HOST=y
-CONFIG_PCIE_XILINX_CPM=y
-CONFIG_PCIE_XILINX_NWL=y
-CONFIG_PCI_AARDVARK=y
-CONFIG_PCI_HISI=y
-CONFIG_PCI_HOST_THUNDER_ECAM=y
-CONFIG_PCI_HOST_THUNDER_PEM=y
-CONFIG_PCI_IMX6=y
-CONFIG_PCI_IOV=y
-CONFIG_PCI_LAYERSCAPE=y
-CONFIG_PCI_PASID=y
-# CONFIG_PCI_RCAR_GEN2 is not set
-CONFIG_PHY_BCM_SR_PCIE=y
-CONFIG_PHY_BCM_SR_USB=y
-CONFIG_PHY_BRCM_SATA=y
-CONFIG_PHY_BRCM_USB=y
-CONFIG_PHY_FSL_IMX8M_PCIE=y
-# CONFIG_PHY_FSL_LYNX_28G is not set
-CONFIG_PHY_HI3660_USB=y
-CONFIG_PHY_HI3670_PCIE=y
-CONFIG_PHY_HI3670_USB=y
-CONFIG_PHY_HI6220_USB=y
-CONFIG_PHY_HISI_INNO_USB2=y
-# CONFIG_PHY_HISTB_COMBPHY is not set
-# CONFIG_PHY_MIXEL_LVDS_PHY is not set
-CONFIG_PHY_MVEBU_A3700_COMPHY=y
-CONFIG_PHY_MVEBU_A3700_UTMI=y
-CONFIG_PHY_MVEBU_A38X_COMPHY=y
-CONFIG_PHY_MVEBU_CP110_COMPHY=y
-CONFIG_PHY_NS2_PCIE=y
-CONFIG_PHY_NS2_USB_DRD=y
-# CONFIG_PHY_RCAR_GEN2 is not set
-CONFIG_PHY_RCAR_GEN3_PCIE=y
-CONFIG_PHY_RCAR_GEN3_USB2=y
-CONFIG_PHY_RCAR_GEN3_USB3=y
-# CONFIG_PHY_ROCKCHIP_DP is not set
-# CONFIG_PHY_ROCKCHIP_DPHY_RX0 is not set
-CONFIG_PHY_ROCKCHIP_EMMC=y
-# CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY is not set
-# CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set
-# CONFIG_PHY_ROCKCHIP_INNO_HDMI is not set
-CONFIG_PHY_ROCKCHIP_INNO_USB2=y
-# CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set
-CONFIG_PHY_ROCKCHIP_PCIE=y
-CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
-CONFIG_PHY_ROCKCHIP_TYPEC=y
-# CONFIG_PHY_ROCKCHIP_USB is not set
-CONFIG_PHY_SUN4I_USB=y
-CONFIG_PHY_SUN50I_USB3=y
-# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
-CONFIG_PHY_SUN9I_USB=y
-# CONFIG_PHY_XILINX_ZYNQMP is not set
-CONFIG_PINCTRL_IMX=y
-CONFIG_PINCTRL_IMX8DXL=y
-CONFIG_PINCTRL_IMX8MM=y
-CONFIG_PINCTRL_IMX8MN=y
-CONFIG_PINCTRL_IMX8MP=y
-CONFIG_PINCTRL_IMX8MQ=y
-CONFIG_PINCTRL_IMX8QM=y
-CONFIG_PINCTRL_IMX8QXP=y
-CONFIG_PINCTRL_IMX8ULP=y
-CONFIG_PINCTRL_IMX93=y
-# CONFIG_PINCTRL_IMXRT1050 is not set
-# CONFIG_PINCTRL_IMXRT1170 is not set
-CONFIG_PINCTRL_IMX_SCU=y
-CONFIG_PINCTRL_IPROC_GPIO=y
-CONFIG_PINCTRL_NS2_MUX=y
-CONFIG_PINCTRL_ROCKCHIP=y
-# CONFIG_PINCTRL_SUN20I_D1 is not set
-CONFIG_PINCTRL_SUN4I_A10=y
-CONFIG_PINCTRL_SUN50I_A100=y
-CONFIG_PINCTRL_SUN50I_A100_R=y
-CONFIG_PINCTRL_SUN50I_A64=y
-CONFIG_PINCTRL_SUN50I_A64_R=y
-CONFIG_PINCTRL_SUN50I_H5=y
-CONFIG_PINCTRL_SUN50I_H6=y
-CONFIG_PINCTRL_SUN50I_H616=y
-CONFIG_PINCTRL_SUN50I_H616_R=y
-CONFIG_PINCTRL_SUN50I_H6_R=y
-CONFIG_PINCTRL_SUN5I=y
-# CONFIG_PINCTRL_SUN6I_A31 is not set
-# CONFIG_PINCTRL_SUN6I_A31_R is not set
-# CONFIG_PINCTRL_SUN8I_A23 is not set
-# CONFIG_PINCTRL_SUN8I_A23_R is not set
-# CONFIG_PINCTRL_SUN8I_A33 is not set
-# CONFIG_PINCTRL_SUN8I_A83T is not set
-# CONFIG_PINCTRL_SUN8I_A83T_R is not set
-# CONFIG_PINCTRL_SUN8I_H3 is not set
-# CONFIG_PINCTRL_SUN8I_H3_R is not set
-# CONFIG_PINCTRL_SUN8I_V3S is not set
-# CONFIG_PINCTRL_SUN9I_A80 is not set
-# CONFIG_PINCTRL_SUN9I_A80_R is not set
-CONFIG_PINCTRL_ZYNQMP=y
-CONFIG_PM=y
-CONFIG_PM_CLK=y
-CONFIG_PM_GENERIC_DOMAINS=y
-CONFIG_PM_GENERIC_DOMAINS_OF=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_HISI=y
-CONFIG_POWER_RESET_VEXPRESS=y
-CONFIG_POWER_SUPPLY=y
-# CONFIG_PTP_1588_CLOCK_DTE is not set
-# CONFIG_PWM_BCM2835 is not set
-CONFIG_QCOM_FALKOR_ERRATUM_1003=y
-CONFIG_QCOM_FALKOR_ERRATUM_1009=y
-CONFIG_QCOM_FALKOR_ERRATUM_E1041=y
-CONFIG_QCOM_QDF2400_ERRATUM_0065=y
-CONFIG_QORIQ_THERMAL=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RASPBERRYPI_FIRMWARE=y
-CONFIG_RASPBERRYPI_POWER=y
-CONFIG_RANDOMIZE_BASE=y
-CONFIG_RANDOMIZE_MODULE_REGION_FULL=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RELOCATABLE=y
-# CONFIG_RAVB is not set
-CONFIG_RCAR_DMAC=y
-# CONFIG_RCAR_GEN3_THERMAL is not set
-# CONFIG_RCAR_THERMAL is not set
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_ANATOP=y
-CONFIG_REGULATOR_AXP20X=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_HI655X=y
-CONFIG_REGULATOR_PFUZE100=y
-# CONFIG_REGULATOR_VEXPRESS is not set
-CONFIG_RENESAS_OSTM=y
-# CONFIG_RENESAS_RZAWDT is not set
-# CONFIG_RENESAS_RZG2LWDT is not set
-# CONFIG_RENESAS_RZN1WDT is not set
-CONFIG_RENESAS_USB_DMAC=y
-# CONFIG_RENESAS_WDT is not set
-# CONFIG_RESET_BRCMSTB is not set
-CONFIG_RESET_IMX7=y
-# CONFIG_RESET_RASPBERRYPI is not set
-CONFIG_RESET_RZG2L_USBPHY_CTRL=y
-CONFIG_ROCKCHIP_IODOMAIN=y
-CONFIG_ROCKCHIP_IOMMU=y
-# CONFIG_ROCKCHIP_MBOX is not set
-CONFIG_ROCKCHIP_PM_DOMAINS=y
-# CONFIG_ROCKCHIP_SARADC is not set
-# CONFIG_ROCKCHIP_THERMAL is not set
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-# CONFIG_RTC_DRV_BRCMSTB is not set
-# CONFIG_RTC_DRV_FSL_FTM_ALARM is not set
-# CONFIG_RTC_DRV_IMXDI is not set
-# CONFIG_RTC_DRV_IMX_SC is not set
-CONFIG_RTC_DRV_MV=y
-# CONFIG_RTC_DRV_MXC is not set
-# CONFIG_RTC_DRV_MXC_V2 is not set
-# CONFIG_RTC_DRV_SH is not set
-CONFIG_RTC_I2C_AND_SPI=y
-# CONFIG_RZG2L_ADC is not set
-# CONFIG_RZG2L_THERMAL is not set
-CONFIG_RZ_DMAC=y
-CONFIG_SATA_SIL24=y
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_SMT=y
-# CONFIG_SENSORS_ARM_SCPI is not set
-CONFIG_SERIAL_8250_BCM2835AUX=y
-CONFIG_SERIAL_8250_BCM7271=y
-# CONFIG_SERIAL_8250_EXAR is not set
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_PCI=y
-CONFIG_SERIAL_FSL_LINFLEXUART=y
-CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE=y
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-CONFIG_SERIAL_IMX_EARLYCON=y
-CONFIG_SERIAL_MVEBU_CONSOLE=y
-CONFIG_SERIAL_MVEBU_UART=y
-CONFIG_SERIAL_SAMSUNG=y
-CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-# CONFIG_SMC91X is not set
-# CONFIG_SND_SOC_RCAR is not set
-# CONFIG_SND_SOC_RZ is not set
-# CONFIG_SND_SOC_SH4_FSI is not set
-# CONFIG_SND_SUN4I_I2S is not set
-# CONFIG_SND_SUN50I_CODEC_ANALOG is not set
-# CONFIG_SND_SUN50I_DMIC is not set
-# CONFIG_SND_SUN8I_CODEC is not set
-# CONFIG_SND_SUN8I_CODEC_ANALOG is not set
-# CONFIG_SNI_NETSEC is not set
-CONFIG_SOCIONEXT_SYNQUACER_PREITS=y
-CONFIG_SOC_IMX8M=y
-CONFIG_SOC_IMX9=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPI_ARMADA_3700=y
-# CONFIG_SPI_BCM2835 is not set
-CONFIG_SPI_FSL_LPSPI=y
-# CONFIG_SPI_FSL_QUADSPI is not set
-# CONFIG_SPI_HISI_KUNPENG is not set
-# CONFIG_SPI_HISI_SFC is not set
-# CONFIG_SPI_HISI_SFC_V3XX is not set
-CONFIG_SPI_IMX=y
-# CONFIG_SPI_ROCKCHIP_SFC is not set
-# CONFIG_SPI_RSPI is not set
-# CONFIG_SPI_SH_HSPI is not set
-# CONFIG_SPI_SH_MSIOF is not set
-# CONFIG_SPI_SUN4I is not set
-# CONFIG_SPI_SUN6I is not set
-# CONFIG_SPI_SYNQUACER is not set
-CONFIG_SPI_THUNDERX=y
-# CONFIG_SPI_XLP is not set
-CONFIG_STUB_CLK_HI3660=y
-CONFIG_STUB_CLK_HI6220=y
-CONFIG_SUN50I_A100_CCU=y
-CONFIG_SUN50I_A100_R_CCU=y
-CONFIG_SUN50I_A64_CCU=y
-CONFIG_SUN50I_H616_CCU=y
-CONFIG_SUN50I_H6_CCU=y
-CONFIG_SUN50I_H6_R_CCU=y
-CONFIG_SUN50I_IOMMU=y
-CONFIG_SUN6I_MSGBOX=y
-CONFIG_SUN6I_RTC_CCU=y
-# CONFIG_SUN8I_A83T_CCU is not set
-CONFIG_SUN8I_DE2_CCU=y
-# CONFIG_SUN8I_H3_CCU is not set
-CONFIG_SUN8I_R_CCU=y
-CONFIG_SUN8I_THERMAL=y
-CONFIG_SUNXI_CCU=y
-CONFIG_SUNXI_RSB=y
-CONFIG_SUNXI_WATCHDOG=y
-CONFIG_SYNC_FILE=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_TCG_TIS_SYNQUACER is not set
-CONFIG_THREAD_INFO_IN_TASK=y
-# CONFIG_THUNDERX2_PMU is not set
-CONFIG_TRANSPARENT_HUGEPAGE=y
-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
-# CONFIG_TURRIS_MOX_RWTM is not set
-CONFIG_TYPEC=y
-# CONFIG_TYPEC_ANX7411 is not set
-# CONFIG_TYPEC_DP_ALTMODE is not set
-# CONFIG_TYPEC_FUSB302 is not set
-# CONFIG_TYPEC_HD3SS3220 is not set
-# CONFIG_TYPEC_MUX_FSA4480 is not set
-# CONFIG_TYPEC_MUX_PI3USB30532 is not set
-# CONFIG_TYPEC_RT1711H is not set
-# CONFIG_TYPEC_RT1719 is not set
-# CONFIG_TYPEC_STUSB160X is not set
-CONFIG_TYPEC_TCPCI=y
-# CONFIG_TYPEC_TCPCI_MAXIM is not set
-CONFIG_TYPEC_TCPM=y
-# CONFIG_TYPEC_TPS6598X is not set
-# CONFIG_TYPEC_WUSB3801 is not set
-# CONFIG_UACCE is not set
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-# CONFIG_USB_BRCMSTB is not set
-CONFIG_USB_CHIPIDEA=y
-CONFIG_USB_CHIPIDEA_GENERIC=y
-CONFIG_USB_CHIPIDEA_HOST=y
-CONFIG_USB_CHIPIDEA_IMX=y
-CONFIG_USB_CHIPIDEA_PCI=y
-CONFIG_USB_CHIPIDEA_UDC=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_DUAL_ROLE=y
-# CONFIG_USB_DWC3_GADGET is not set
-CONFIG_USB_DWC3_HAPS=y
-# CONFIG_USB_DWC3_HOST is not set
-CONFIG_USB_DWC3_IMX8MP=y
-# CONFIG_USB_DWC3_OF_SIMPLE is not set
-CONFIG_USB_DWC3_PCI=y
-# CONFIG_USB_DWC3_ULPI is not set
-CONFIG_USB_DWC3_XILINX=y
-CONFIG_USB_EHCI_FSL=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_ORION=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-# CONFIG_USB_EMXX is not set
-CONFIG_USB_GADGET=y
-CONFIG_USB_MXS_PHY=y
-CONFIG_USB_OHCI_EXYNOS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PCI=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_OTG=y
-CONFIG_USB_OTG_FSM=y
-CONFIG_USB_RENESAS_USB3=y
-CONFIG_USB_RENESAS_USBHS=y
-CONFIG_USB_RENESAS_USBHS_HCD=y
-CONFIG_USB_RENESAS_USBHS_UDC=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_HISTB=y
-CONFIG_USB_XHCI_MVEBU=y
-CONFIG_USB_XHCI_PLATFORM=y
-CONFIG_VEXPRESS_CONFIG=y
-CONFIG_VIDEOMODE_HELPERS=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
-# CONFIG_VIRTIO_IOMMU is not set
-CONFIG_VIRTUALIZATION=y
-CONFIG_VMAP_STACK=y
-CONFIG_WDAT_WDT=y
-# CONFIG_XILINX_AMS is not set
-# CONFIG_XILINX_INTC is not set
-CONFIG_XLNX_EVENT_MANAGER=y
-CONFIG_ZONE_DMA32=y
-CONFIG_ZYNQMP_FIRMWARE=y
-# CONFIG_ZYNQMP_FIRMWARE_DEBUG is not set
-CONFIG_ZYNQMP_PM_DOMAINS=y
-CONFIG_ZYNQMP_POWER=y
+++ /dev/null
-CONFIG_64BIT=y
-CONFIG_9P_FS=y
-# CONFIG_9P_FS_POSIX_ACL is not set
-# CONFIG_9P_FS_SECURITY is not set
-# CONFIG_A64FX_DIAG is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_AC=y
-CONFIG_ACPI_APEI=y
-CONFIG_ACPI_APEI_EINJ=y
-# CONFIG_ACPI_APEI_ERST_DEBUG is not set
-CONFIG_ACPI_APEI_GHES=y
-CONFIG_ACPI_APEI_MEMORY_FAILURE=y
-CONFIG_ACPI_APEI_PCIEAER=y
-CONFIG_ACPI_BATTERY=y
-# CONFIG_ACPI_BGRT is not set
-CONFIG_ACPI_BUTTON=y
-CONFIG_ACPI_CCA_REQUIRED=y
-CONFIG_ACPI_CONTAINER=y
-CONFIG_ACPI_CPPC_CPUFREQ=y
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_DEBUGGER is not set
-# CONFIG_ACPI_DOCK is not set
-# CONFIG_ACPI_EC_DEBUGFS is not set
-CONFIG_ACPI_FAN=y
-CONFIG_ACPI_GENERIC_GSI=y
-CONFIG_ACPI_GTDT=y
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_I2C_OPREGION=y
-CONFIG_ACPI_IORT=y
-CONFIG_ACPI_MCFG=y
-# CONFIG_ACPI_PCI_SLOT is not set
-# CONFIG_ACPI_PFRUT is not set
-CONFIG_ACPI_PPTT=y
-CONFIG_ACPI_PRMT=y
-CONFIG_ACPI_PROCESSOR=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_THERMAL=y
-# CONFIG_ACPI_TINY_POWER_BUTTON is not set
-# CONFIG_ALIBABA_UNCORE_DRW_PMU is not set
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
-CONFIG_ARCH_PROC_KCORE_TEXT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ARM64=y
-CONFIG_ARM64_4K_PAGES=y
-# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set
-CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
-CONFIG_ARM64_PAGE_SHIFT=12
-CONFIG_ARM64_PA_BITS=48
-CONFIG_ARM64_PA_BITS_48=y
-CONFIG_ARM64_TAGGED_ADDR_ABI=y
-CONFIG_ARM64_VA_BITS=39
-CONFIG_ARM64_VA_BITS_39=y
-CONFIG_ARM_AMBA=y
-CONFIG_ARM_ARCH_TIMER=y
-CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
-CONFIG_ARM_GIC=y
-CONFIG_ARM_GIC_V2M=y
-CONFIG_ARM_GIC_V3=y
-CONFIG_ARM_GIC_V3_ITS=y
-CONFIG_ARM_GIC_V3_ITS_PCI=y
-CONFIG_ARM_PSCI_FW=y
-# CONFIG_ARM_SMMU_V3_PMU is not set
-CONFIG_ATA=y
-CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_PM=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DCACHE_WORD_ACCESS=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_ACPI=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_REMAP=y
-CONFIG_DMI=y
-CONFIG_DMIID=y
-CONFIG_DMI_SYSFS=y
-CONFIG_DTC=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=y
-CONFIG_EFI_ARMSTUB_DTB_LOADER=y
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_COCO_SECRET is not set
-# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_GENERIC_STUB=y
-# CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER is not set
-CONFIG_EFI_PARAMS_FROM_FDT=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-# CONFIG_EFI_ZBOOT is not set
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FAILOVER=y
-CONFIG_FB_EFI=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIO_CDEV=y
-# CONFIG_GPIO_HISI is not set
-CONFIG_GPIO_PL061=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-CONFIG_HVC_DRIVER=y
-CONFIG_HZ_PERIODIC=y
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_HID_ACPI=y
-# CONFIG_I2C_HISI is not set
-# CONFIG_I2C_SLAVE_TESTUNIT is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISCSI_IBFT is not set
-CONFIG_JBD2=y
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MEMORY_BALLOON=y
-CONFIG_MIGRATION=y
-# CONFIG_MLXBF_GIGE is not set
-CONFIG_MMC_SDHCI_ACPI=y
-CONFIG_MODULES_USE_ELF_RELA=y
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_MVMDIO=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-CONFIG_NET_9P=y
-# CONFIG_NET_9P_DEBUG is not set
-# CONFIG_NET_9P_FD is not set
-CONFIG_NET_9P_VIRTIO=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NLS=y
-CONFIG_NR_CPUS=256
-CONFIG_NVMEM=y
-CONFIG_NVME_CORE=y
-# CONFIG_NVME_MULTIPATH is not set
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_PADATA=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_PARTITION_PERCPU=y
-CONFIG_PCI=y
-# CONFIG_PCIE_HISI_ERR is not set
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_ECAM=y
-CONFIG_PCI_HOST_COMMON=y
-CONFIG_PCI_HOST_GENERIC=y
-CONFIG_PCI_LABEL=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYS_ADDR_T_64BIT=y
-# CONFIG_PMIC_OPREGION is not set
-CONFIG_PNP=y
-CONFIG_PNPACPI=y
-CONFIG_PNP_DEBUG_MESSAGES=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RATIONAL=y
-# CONFIG_RESET_ATTACK_MITIGATION is not set
-CONFIG_RFS_ACCEL=y
-CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_EFI=y
-CONFIG_RTC_DRV_PL031=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SATA_AHCI=y
-CONFIG_SATA_AHCI_PLATFORM=y
-CONFIG_SATA_HOST=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SCSI_VIRTIO=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_FSL=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_EARLYCON=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_VMEMMAP=y
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SRCU=y
-# CONFIG_SURFACE_PLATFORMS is not set
-CONFIG_SWIOTLB=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFB=y
-# CONFIG_SYSFB_SIMPLEFB is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THERMAL_OF=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_ACPI=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UACCE is not set
-CONFIG_UCS2_STRING=y
-CONFIG_UNMAP_KERNEL_AT_EL0=y
-CONFIG_USB=y
-CONFIG_USB_HID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PCI=y
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_PCI_LIB=y
-CONFIG_VMAP_STACK=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_XPS=y
-CONFIG_ZONE_DMA32=y
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca953x.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "8dev,carambola3", "qca,qca9531";
+ model = "8devices Carambola3";
+
+ aliases {
+ label-mac-device = &wmac;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ lan {
+ label = "green:lan";
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+ };
+
+ wan {
+ label = "green:wan";
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&usb0 {
+ status = "okay";
+
+ dr_mode = "host";
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&wdt {
+ status = "okay";
+};
+
+&spi {
+ status = "okay";
+
+ /* Winbond W25Q256 SPI flash */
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <45000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x000000 0x040000>;
+ read-only;
+ };
+
+ partition@40000 {
+ label = "u-boot-env";
+ reg = <0x040000 0x040000>;
+ };
+
+ art: partition@80000 {
+ label = "art";
+ reg = <0x080000 0x040000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_art_0: macaddr@0 {
+ reg = <0x0 0x6>;
+ };
+
+ macaddr_art_6: macaddr@6 {
+ reg = <0x6 0x6>;
+ };
+ };
+ };
+
+ partition@c0000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x0c0000 0xf40000>;
+ };
+ };
+ };
+};
+
+&mdio0 {
+ status = "okay";
+};
+
+ð0 {
+ status = "okay";
+
+ phy-handle = <&swphy0>;
+
+ nvmem-cells = <&macaddr_art_6>;
+ nvmem-cell-names = "mac-address";
+
+ gmac-config {
+ device = <&gmac>;
+
+ switch-phy-addr-swap = <1>;
+ switch-phy-swap = <1>;
+ };
+};
+
+ð1 {
+ nvmem-cells = <&macaddr_art_0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&wmac {
+ status = "okay";
+
+ mtd-cal-data = <&art 0x1000>;
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "qca955x.dtsi"
+
+/ {
+ model = "Dell SonicPoint ACe (APL26-0AE)";
+ compatible = "dell,apl26-0ae", "qca,qca9550", "qca,qca9558";
+
+ aliases {
+ label-mac-device = ð0;
+ led-boot = &led_wrench;
+ led-failsafe = &led_wrench;
+ led-upgrade = &led_wrench;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ button-reset {
+ label = "reset";
+ gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ /* Accessible only after disassembling the casing */
+ button-service {
+ label = "service";
+ gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&jtag_disable_pins>;
+
+ led-lan1-amber {
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+ };
+
+ led-lan1-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <1>;
+ gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
+ };
+
+ led-lan2-amber {
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
+ };
+
+ led-lan2-green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ function-enumerator = <2>;
+ gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+ };
+
+ led-wlan2g {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_2GHZ;
+ linux,default-trigger = "phy1tpt";
+ gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
+ };
+
+ led-wlan5g {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_5GHZ;
+ linux,default-trigger = "phy0tpt";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ };
+
+ led_wrench: led-wrench {
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+ð0 {
+ status = "okay";
+
+ nvmem-cells = <&macaddr_sysinfo_50 0>;
+ nvmem-cell-names = "mac-address";
+ phy-handle = <&phy0>;
+ pll-data = <0xa6000000 0x00000101 0x00001616>;
+};
+
+ð1 {
+ status = "okay";
+
+ nvmem-cells = <&macaddr_sysinfo_50 1>;
+ nvmem-cell-names = "mac-address";
+ pll-data = <0x03000101 0x00000101 0x00001616>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&mdio0 {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+
+ qca,ar8327-initvals = <
+ 0x04 0x07680000 /* PORT0 PAD MODE CTRL */
+ 0x0c 0x00000080 /* PORT6 PAD MODE CTRL */
+ 0x10 0x40000000 /* POWER_ON_STRAP */
+ 0x50 0xffb7c405 /* LED0 CTRL */
+ 0x54 0xffb7c305 /* LED1 CTRL */
+ 0x58 0xffb7c033 /* LED2 CTRL */
+ 0x5c 0x03ffff00 /* LED3 CTRL */
+ 0x7c 0x0000007e /* PORT0_STATUS */
+ 0x94 0x0000007e /* PORT6_STATUS */
+ >;
+ };
+};
+
+&pcie0 {
+ status = "okay";
+
+ wifi@0,0 {
+ compatible = "qcom,ath10k";
+ reg = <0x0000 0 0 0 0>;
+
+ /* OEM overwrites EEPROM stored adress and so do we */
+ nvmem-cells = <&macaddr_sysinfo_50 2>;
+ nvmem-cell-names = "mac-address";
+ };
+};
+
+&spi {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ broken-flash-reset;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x0080000>;
+ read-only;
+ };
+
+ partition@80000 {
+ label = "u-boot-env";
+ reg = <0x0080000 0x0040000>;
+ };
+
+ partition@c0000 {
+ label = "sysinfo";
+ reg = <0x00c0000 0x0040000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_sysinfo_50: macaddr@50 {
+ compatible = "mac-base";
+ reg = <0x50 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ partition@100000 {
+ label = "art";
+ reg = <0x0100000 0x0010000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cal_art_1000: calibration@1000 {
+ reg = <0x1000 0x440>;
+ };
+ };
+ };
+
+ partition@110000 {
+ label = "firmware";
+ reg = <0x0110000 0x1ef0000>;
+ compatible = "denx,uimage";
+ };
+ };
+ };
+};
+
+&usb_phy0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
+
+&wmac {
+ status = "okay";
+
+ nvmem-cells = <&macaddr_sysinfo_50 10>, <&cal_art_1000>;
+ nvmem-cell-names = "mac-address", "calibration";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "qca956x.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ compatible = "ubnt,amplifi-router-hd", "qca,qca9563";
+ model = "Ubiquiti AmpliFi Router HD";
+
+ aliases {
+ label-mac-device = ð0;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "Reset button";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ debounce-interval = <60>;
+ };
+ };
+};
+
+&pcie {
+ status = "okay";
+
+ wifi@0,0 {
+ compatible = "qcom,ath10k";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cells = <&cal_art_5000>;
+ nvmem-cell-names = "calibration";
+ };
+};
+
+&spi {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x000000 0x060000>;
+ read-only;
+ };
+
+ partition@60000 {
+ compatible = "u-boot,env";
+ label = "u-boot-env";
+ reg = <0x060000 0x010000>;
+ };
+
+ partition@70000 {
+ compatible = "denx,uimage";
+ label = "firmware";
+ reg = <0x070000 0xb00000>;
+ };
+
+ partition@b70000 {
+ label = "cfg";
+ reg = <0xb70000 0x0c0000>;
+ read-only;
+ };
+
+ partition@c30000 {
+ label = "recovery";
+ reg = <0xc30000 0x3b0000>;
+ read-only;
+ };
+
+ partition@fe0000 {
+ label = "prst";
+ reg = <0xfe0000 0x010000>;
+ read-only;
+ };
+
+ partition@ff0000 {
+ /* eeprom */
+ label = "art";
+ reg = <0xff0000 0x010000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_art_0: macaddr@0 {
+ compatible = "mac-base";
+ reg = <0x0 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ cal_art_1000: calibration@1000 {
+ reg = <0x1000 0x440>;
+ };
+
+ cal_art_5000: calibration@5000 {
+ reg = <0x5000 0x844>;
+ };
+ };
+ };
+
+ partition@1000000 {
+ label = "bs1";
+ reg = <0x1000000 0x010000>;
+ };
+
+ partition@1010000 {
+ label = "bs2";
+ reg = <0x1010000 0x010000>;
+ read-only;
+ };
+
+ partition@1020000 {
+ label = "stats";
+ reg = <0x1020000 0x400000>;
+ read-only;
+ };
+
+ partition@1420000 {
+ label = "fw_inactive";
+ reg = <0x1420000 0xb00000>;
+ read-only;
+ };
+
+ partition@1f20000 {
+ label = "reserved";
+ reg = <0x1f20000 0x0e0000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&mdio0 {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ phy-mode = "sgmii";
+
+ qca,ar8327-initvals = <
+ 0x04 0x00000080 /* AR8327_REG_PAD0_MODE */
+ 0x08 0x00000000 /* PORT5 PAD MODE CTRL */
+ 0x0c 0x00000000 /* PORT6 PAD MODE CTRL */
+ 0x10 0x602613a0 /* AR8327_REG_POWER_ON_STRAP */
+ 0x50 0xcc35cc35 /* AR8327_REG_LED_CTRL0 */
+ 0x54 0xca35ca35 /* AR8327_REG_LED_CTRL1 */
+ 0x58 0xc935c935 /* AR8327_REG_LED_CTRL2 */
+ 0x5c 0x03ffff00 /* AR8327_REG_LED_CTRL3 */
+ 0x7c 0x0000007e /* AR8327_REG_PORT_STATUS(0) */
+ 0x94 0x00001080 /* AR8327_REG_PORT_STATUS(6) */
+ >;
+ };
+};
+
+ð0 {
+ status = "okay";
+
+ pll-data = <0x03000101 0x00000101 0x00001919>;
+
+ phy-mode = "sgmii";
+ phy-handle = <&phy0>;
+
+ nvmem-cells = <&macaddr_art_0 0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&wmac {
+ status = "okay";
+
+ nvmem-cells = <&macaddr_art_0 (-2)>, <&cal_art_1000>;
+ nvmem-cell-names = "mac-address", "calibration";
+};
+
+&usb_phy0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+};
ucidef_set_led_netdev "lan" "LAN" "orange:eth0" "eth0"
ucidef_set_led_switch "wan" "WAN" "orange:eth1" "switch0" "0x04"
;;
+8dev,carambola3)
+ ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0" "link"
+ ucidef_set_led_netdev "wan" "WAN" "green:wan" "eth1" "link"
+ ;;
alcatel,hh40v)
ucidef_set_led_netdev "lan_data" "LAN Data" "green:lan" "eth1" "tx rx"
ucidef_set_led_netdev "lan_link" "LAN Link" "orange:lan" "eth1" "link"
ucidef_set_led_rssi "sig3" "SIG3" "green:sig3" "wlan0" "65" "100"
ucidef_set_led_rssi "sig4" "SIG4" "green:sig4" "wlan0" "50" "100"
;;
+dell,apl26-0ae)
+ ucidef_set_led_switch "lan1" "LAN1" "amber:lan-1" "switch0" "0x04"
+ ucidef_set_led_switch "lan2" "LAN2" "amber:lan-2" "switch0" "0x08"
+ ;;
devolo,dlan-pro-1200plus-ac|\
devolo,magic-2-wifi)
ucidef_set_led_netdev "plcw" "dLAN" "white:dlan" "eth0.1" "rx"
ucidef_add_switch "switch0" \
"1:wan" "5:lan" "6@eth0"
;;
+ dell,apl26-0ae)
+ ucidef_add_switch "switch0" \
+ "0@eth0" "2:lan:1" "3:lan:2" "6@eth1"
+ ;;
devolo,dlan-pro-1200plus-ac|\
devolo,magic-2-wifi)
ucidef_add_switch "switch0" \
ucidef_add_switch "switch0" \
"0@eth0" "2:lan:1" "3:lan:3" "4:lan:2"
;;
+ ubnt,amplifi-router-hd)
+ ucidef_add_switch "switch0" \
+ "0@eth0" "2:lan:1" "3:lan:3" "4:lan:2" "5:lan:4" "1:wan"
+ ;;
ubnt,edgeswitch-5xp)
ucidef_set_interface_wan "eth1"
ucidef_add_switch "switch0" \
case "$FIRMWARE" in
"ath9k-eeprom-ahb-18100000.wmac.bin")
case $board in
+ 8dev,carambola3|\
8dev,lima)
caldata_extract "art" 0x1000 0x800
;;
endef
TARGET_DEVICES += ubnt_aircube-isp
+define Device/ubnt_amplifi-router-hd
+ IMAGE_SIZE := 11264k
+ UBNT_BOARD := AFi-R-HD
+ UBNT_TYPE := AFi-R
+ UBNT_VERSION := 3.6.3
+ SOC := qca9563
+ DEVICE_MODEL := AmpliFi Router HD
+ UBNT_CHIP := qca956x
+ DEVICE_PACKAGES += kmod-ath10k-ct-smallbuffers ath10k-firmware-qca988x-ct kmod-usb2
+endef
+TARGET_DEVICES += ubnt_amplifi-router-hd
+
define Device/ubnt_bullet-ac
$(Device/ubnt-2wa)
DEVICE_MODEL := Bullet AC
endef
TARGET_DEVICES += 8dev_carambola2
+define Device/8dev_carambola3
+ SOC := qca9531
+ DEVICE_VENDOR := 8devices
+ DEVICE_MODEL := Carambola3
+ DEVICE_PACKAGES := kmod-usb2
+ IMAGE_SIZE := 32768k
+ SUPPORTED_DEVICES += carambola3
+endef
+TARGET_DEVICES += 8dev_carambola3
+
define Device/8dev_lima
SOC := qca9531
DEVICE_VENDOR := 8devices
endef
TARGET_DEVICES += compex_wpj563
+define Device/dell_apl26-0ae
+ SOC := qca9550
+ DEVICE_VENDOR := Dell
+ DEVICE_MODEL := SonicPoint
+ DEVICE_VARIANT := ACe (APL26-0AE)
+ DEVICE_ALT0_VENDOR := SonicWall
+ DEVICE_ALT0_MODEL := SonicPoint
+ DEVICE_ALT0_VARIANT := ACe (APL26-0AE)
+ DEVICE_PACKAGES := ath10k-firmware-qca988x-ct kmod-ath10k-ct kmod-usb2
+ KERNEL_SIZE := 5952k
+ IMAGE_SIZE := 31680k
+ IMAGE/sysupgrade.bin = append-kernel | pad-to $$$$(BLOCKSIZE) | \
+ append-rootfs | pad-rootfs | check-size | append-metadata
+endef
+TARGET_DEVICES += dell_apl26-0ae
+
define Device/devolo_dlan-pro-1200plus-ac
SOC := ar9344
DEVICE_VENDOR := devolo
FILES:= \
$(LINUX_DIR)/drivers/staging/vc04_services/bcm2835-codec/bcm2835-codec.ko
AUTOLOAD:=$(call AutoLoad,67,bcm2835-codec)
- $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-dma +kmod-video-mem2mem)
+ $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-dma-contig +kmod-video-mem2mem)
endef
define KernelPackage/codec-bcm2835/description
FILES:= \
$(LINUX_DIR)/drivers/staging/vc04_services/bcm2835-isp/bcm2835-isp.ko
AUTOLOAD:=$(call AutoLoad,67,bcm2835-isp)
- $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-dma)
+ $(call AddDepends/video,@TARGET_bcm27xx +kmod-vchiq-mmal-bcm2835 +kmod-video-dma-contig)
endef
define KernelPackage/isp-bcm2835/description
FEATURES:=squashfs usb
SUBTARGETS:=generic mips74k legacy
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
define Target/Description
Build firmware images for Broadcom based BCM47xx/53xx routers with MIPS CPU, *not* ARM.
+++ /dev/null
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_BCM47XX=y
-CONFIG_BCM47XX_BCMA=y
-CONFIG_BCM47XX_NVRAM=y
-CONFIG_BCM47XX_SPROM=y
-CONFIG_BCM47XX_SSB=y
-CONFIG_BCM47XX_WDT=y
-CONFIG_BCMA=y
-CONFIG_BCMA_BLOCKIO=y
-CONFIG_BCMA_DEBUG=y
-CONFIG_BCMA_DRIVER_GMAC_CMN=y
-CONFIG_BCMA_DRIVER_GPIO=y
-CONFIG_BCMA_DRIVER_MIPS=y
-CONFIG_BCMA_DRIVER_PCI=y
-CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
-CONFIG_BCMA_HOST_PCI=y
-CONFIG_BCMA_HOST_PCI_POSSIBLE=y
-CONFIG_BCMA_HOST_SOC=y
-CONFIG_BCMA_NFLASH=y
-CONFIG_BCMA_PFLASH=y
-CONFIG_BCMA_SFLASH=y
-# CONFIG_BGMAC_BCMA is not set
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CMDLINE="noinitrd console=ttyS0,115200"
-CONFIG_CMDLINE_BOOL=y
-# CONFIG_CMDLINE_OVERRIDE is not set
-# CONFIG_COMMON_CLK is not set
-CONFIG_COMPAT_32BIT_TIME=y
-# CONFIG_CPU_BMIPS is not set
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-CONFIG_CPU_HAS_SYNC=y
-CONFIG_CPU_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-# CONFIG_CPU_MIPS32_R2 is not set
-CONFIG_CPU_MIPSR1=y
-CONFIG_CPU_MIPSR2_IRQ_VI=y
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-CONFIG_CPU_R4K_CACHE_TLB=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DMA_NONCOHERENT=y
-# CONFIG_EARLY_PRINTK is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_WDT=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_RANDOM=y
-CONFIG_HZ_PERIODIC=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_LEDS_GPIO_REGISTER=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
-CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_MIPS_EBPF_JIT=y
-CONFIG_MIPS_L1_CACHE_SHIFT=5
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_BCM47XXSFLASH=y
-CONFIG_MTD_BCM47XX_PARTS=y
-CONFIG_MTD_NAND_BCM47XXNFLASH=y
-CONFIG_MTD_NAND_BRCMNAND=y
-CONFIG_MTD_NAND_BRCMNAND_BCMA=y
-CONFIG_MTD_NAND_CORE=y
-CONFIG_MTD_NAND_ECC=y
-CONFIG_MTD_PARSER_TRX=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NO_EXCEPT_FILL=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-# CONFIG_OF is not set
-CONFIG_PCI=y
-CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SRCU=y
-CONFIG_SSB=y
-CONFIG_SSB_B43_PCI_BRIDGE=y
-CONFIG_SSB_BLOCKIO=y
-CONFIG_SSB_DRIVER_EXTIF=y
-CONFIG_SSB_DRIVER_GIGE=y
-CONFIG_SSB_DRIVER_GPIO=y
-CONFIG_SSB_DRIVER_MIPS=y
-CONFIG_SSB_DRIVER_PCICORE=y
-CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
-CONFIG_SSB_EMBEDDED=y
-CONFIG_SSB_HOST_SOC=y
-CONFIG_SSB_PCICORE_HOSTMODE=y
-CONFIG_SSB_PCIHOST=y
-CONFIG_SSB_PCIHOST_POSSIBLE=y
-CONFIG_SSB_SERIAL=y
-CONFIG_SSB_SFLASH=y
-CONFIG_SSB_SPROM=y
-CONFIG_SWCONFIG=y
-CONFIG_SWCONFIG_B53=y
-CONFIG_SWCONFIG_B53_PHY_DRIVER=y
-CONFIG_SWCONFIG_B53_PHY_FIXUP=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYS_HAS_CPU_BMIPS=y
-CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_EARLY_PRINTK=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_HIGHMEM=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=1
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y
-CONFIG_WATCHDOG_CORE=y
--- /dev/null
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MMAP_RND_BITS_MAX=15
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_BCM47XX=y
+CONFIG_BCM47XX_BCMA=y
+CONFIG_BCM47XX_NVRAM=y
+CONFIG_BCM47XX_SPROM=y
+CONFIG_BCM47XX_SSB=y
+CONFIG_BCM47XX_WDT=y
+CONFIG_BCMA=y
+CONFIG_BCMA_BLOCKIO=y
+CONFIG_BCMA_DEBUG=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_BCMA_DRIVER_MIPS=y
+CONFIG_BCMA_DRIVER_PCI=y
+CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
+CONFIG_BCMA_FALLBACK_SPROM=y
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA_NFLASH=y
+CONFIG_BCMA_PFLASH=y
+CONFIG_BCMA_SFLASH=y
+# CONFIG_BGMAC_BCMA is not set
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CEVT_R4K=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMDLINE="noinitrd console=ttyS0,115200"
+CONFIG_CMDLINE_BOOL=y
+# CONFIG_CMDLINE_OVERRIDE is not set
+# CONFIG_COMMON_CLK is not set
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+# CONFIG_CPU_BMIPS is not set
+CONFIG_CPU_GENERIC_DUMP_TLB=y
+CONFIG_CPU_HAS_PREFETCH=y
+CONFIG_CPU_HAS_SYNC=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MIPS32=y
+CONFIG_CPU_MIPS32_R1=y
+# CONFIG_CPU_MIPS32_R2 is not set
+CONFIG_CPU_MIPSR1=y
+CONFIG_CPU_MIPSR2_IRQ_VI=y
+CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
+CONFIG_CPU_R4K_CACHE_TLB=y
+CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
+CONFIG_CPU_SUPPORTS_HIGHMEM=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CSRC_R4K=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DMA_NONCOHERENT=y
+# CONFIG_EARLY_PRINTK is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_FIXED_PHY=y
+CONFIG_FS_IOMAP=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_LIB_ASHLDI3=y
+CONFIG_GENERIC_LIB_ASHRDI3=y
+CONFIG_GENERIC_LIB_CMPDI2=y
+CONFIG_GENERIC_LIB_LSHRDI3=y
+CONFIG_GENERIC_LIB_UCMPDI2=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_WDT=y
+CONFIG_HARDWARE_WATCHPOINTS=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MIPS_CPU=y
+CONFIG_IRQ_WORK=y
+CONFIG_LEDS_GPIO_REGISTER=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MIGRATION=y
+CONFIG_MIPS=y
+CONFIG_MIPS_ASID_BITS=8
+CONFIG_MIPS_ASID_SHIFT=0
+CONFIG_MIPS_CLOCK_VSYSCALL=y
+# CONFIG_MIPS_CMDLINE_BUILTIN_EXTEND is not set
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_MIPS_L1_CACHE_SHIFT=5
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_BCM47XXSFLASH=y
+CONFIG_MTD_BCM47XX_PARTS=y
+CONFIG_MTD_NAND_BCM47XXNFLASH=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_BRCMNAND_BCMA=y
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_PARSER_TRX=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NO_EXCEPT_FILL=y
+CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
+# CONFIG_OF is not set
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PCI=y
+CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DRIVERS_LEGACY=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SSB=y
+CONFIG_SSB_B43_PCI_BRIDGE=y
+CONFIG_SSB_BLOCKIO=y
+CONFIG_SSB_DRIVER_EXTIF=y
+CONFIG_SSB_DRIVER_GIGE=y
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_SSB_DRIVER_MIPS=y
+CONFIG_SSB_DRIVER_PCICORE=y
+CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y
+CONFIG_SSB_EMBEDDED=y
+CONFIG_SSB_FALLBACK_SPROM=y
+CONFIG_SSB_HOST_SOC=y
+CONFIG_SSB_PCICORE_HOSTMODE=y
+CONFIG_SSB_PCIHOST=y
+CONFIG_SSB_PCIHOST_POSSIBLE=y
+CONFIG_SSB_SERIAL=y
+CONFIG_SSB_SFLASH=y
+CONFIG_SSB_SPROM=y
+CONFIG_SWCONFIG=y
+CONFIG_SWCONFIG_B53=y
+CONFIG_SWCONFIG_B53_PHY_DRIVER=y
+CONFIG_SWCONFIG_B53_PHY_FIXUP=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYS_HAS_CPU_BMIPS=y
+CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
+CONFIG_SYS_HAS_CPU_MIPS32_R1=y
+CONFIG_SYS_HAS_CPU_MIPS32_R2=y
+CONFIG_SYS_HAS_EARLY_PRINTK=y
+CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
+CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
+CONFIG_SYS_SUPPORTS_HIGHMEM=y
+CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
+CONFIG_SYS_SUPPORTS_MIPS16=y
+CONFIG_SYS_SUPPORTS_ZBOOT=y
+CONFIG_TARGET_ISA_REV=1
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TINY_SRCU=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_ZBOOT_LOAD_ADDRESS=0xffffffff80400000
+++ /dev/null
-From eea175eedf3e2f71b9538d21e643e7a1be4923df Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 6 Jan 2022 19:51:37 -0800
-Subject: [PATCH] MIPS: BCM47XX: Define Linksys WRT310N V2 buttons
-
-Update the buttons registration code to register the two buttons (WPS,
-system rester) using the existing BCM47XX_BOARD_LINKSYS_WRT310NV2 board
-entry.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/buttons.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -277,6 +277,12 @@ bcm47xx_buttons_linksys_wrt310nv1[] __in
- };
-
- static const struct gpio_keys_button
-+bcm47xx_buttons_linksys_wrt310n_v2[] __initconst = {
-+ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
-+ BCM47XX_GPIO_KEY(6, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = {
- BCM47XX_GPIO_KEY(5, KEY_WIMAX),
- BCM47XX_GPIO_KEY(6, KEY_RESTART),
-@@ -608,6 +614,9 @@ int __init bcm47xx_buttons_register(void
- case BCM47XX_BOARD_LINKSYS_WRT310NV1:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310nv1);
- break;
-+ case BCM47XX_BOARD_LINKSYS_WRT310NV2:
-+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2);
-+ break;
- case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2);
- break;
+++ /dev/null
-From 3829e4f10a232964cc728c0479c8097922e5e073 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 6 Jan 2022 19:51:38 -0800
-Subject: [PATCH] MIPS: BCM47XX: Add board entry for Linksys WRT320N v1
-
-This router is based on a Broadcom BCM4717A1 chipset and supports
-802.11n Wi-Fi. Add a board entry for that router and register LEDs and
-buttons accordingly.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/board.c | 1 +
- arch/mips/bcm47xx/buttons.c | 9 +++++++++
- arch/mips/bcm47xx/leds.c | 10 ++++++++++
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 +
- 4 files changed, 21 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -141,6 +141,7 @@ struct bcm47xx_board_type_list2 bcm47xx_
- {{BCM47XX_BOARD_LINKSYS_WRT300NV11, "Linksys WRT300N V1.1"}, "WRT300N", "1.1"},
- {{BCM47XX_BOARD_LINKSYS_WRT310NV1, "Linksys WRT310N V1"}, "WRT310N", "1.0"},
- {{BCM47XX_BOARD_LINKSYS_WRT310NV2, "Linksys WRT310N V2"}, "WRT310N", "2.0"},
-+ {{BCM47XX_BOARD_LINKSYS_WRT320N_V1, "Linksys WRT320N V1"}, "WRT320N", "1.0"},
- {{BCM47XX_BOARD_LINKSYS_WRT54G3GV2, "Linksys WRT54G3GV2-VF"}, "WRT54G3GV2-VF", "1.0"},
- {{BCM47XX_BOARD_LINKSYS_WRT610NV1, "Linksys WRT610N V1"}, "WRT610N", "1.0"},
- {{BCM47XX_BOARD_LINKSYS_WRT610NV2, "Linksys WRT610N V2"}, "WRT610N", "2.0"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -283,6 +283,12 @@ bcm47xx_buttons_linksys_wrt310n_v2[] __i
- };
-
- static const struct gpio_keys_button
-+bcm47xx_buttons_linksys_wrt320n_v1[] __initconst = {
-+ BCM47XX_GPIO_KEY(5, KEY_WPS_BUTTON),
-+ BCM47XX_GPIO_KEY(8, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_linksys_wrt54g3gv2[] __initconst = {
- BCM47XX_GPIO_KEY(5, KEY_WIMAX),
- BCM47XX_GPIO_KEY(6, KEY_RESTART),
-@@ -617,6 +623,9 @@ int __init bcm47xx_buttons_register(void
- case BCM47XX_BOARD_LINKSYS_WRT310NV2:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt310n_v2);
- break;
-+ case BCM47XX_BOARD_LINKSYS_WRT320N_V1:
-+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt320n_v1);
-+ break;
- case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_wrt54g3gv2);
- break;
---- a/arch/mips/bcm47xx/leds.c
-+++ b/arch/mips/bcm47xx/leds.c
-@@ -314,6 +314,13 @@ bcm47xx_leds_linksys_wrt310nv1[] __initc
- };
-
- static const struct gpio_led
-+bcm47xx_leds_linksys_wrt320n_v1[] __initconst = {
-+ BCM47XX_GPIO_LED(1, "blue", "wlan", 1, LEDS_GPIO_DEFSTATE_OFF),
-+ BCM47XX_GPIO_LED(2, "blue", "power", 0, LEDS_GPIO_DEFSTATE_ON),
-+ BCM47XX_GPIO_LED(4, "amber", "wps", 1, LEDS_GPIO_DEFSTATE_OFF),
-+};
-+
-+static const struct gpio_led
- bcm47xx_leds_linksys_wrt54g_generic[] __initconst = {
- BCM47XX_GPIO_LED(0, "unk", "dmz", 1, LEDS_GPIO_DEFSTATE_OFF),
- BCM47XX_GPIO_LED(1, "unk", "power", 0, LEDS_GPIO_DEFSTATE_ON),
-@@ -689,6 +696,9 @@ void __init bcm47xx_leds_register(void)
- case BCM47XX_BOARD_LINKSYS_WRT310NV1:
- bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt310nv1);
- break;
-+ case BCM47XX_BOARD_LINKSYS_WRT320N_V1:
-+ bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt320n_v1);
-+ break;
- case BCM47XX_BOARD_LINKSYS_WRT54G3GV2:
- bcm47xx_set_pdata(bcm47xx_leds_linksys_wrt54g3gv2);
- break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -72,6 +72,7 @@ enum bcm47xx_board {
- BCM47XX_BOARD_LINKSYS_WRT300NV11,
- BCM47XX_BOARD_LINKSYS_WRT310NV1,
- BCM47XX_BOARD_LINKSYS_WRT310NV2,
-+ BCM47XX_BOARD_LINKSYS_WRT320N_V1,
- BCM47XX_BOARD_LINKSYS_WRT54G3GV2,
- BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101,
- BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467,
+++ /dev/null
-From aecf89f2f8e8a604c33085c230a1f04ea325de64 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 6 Jan 2022 19:51:39 -0800
-Subject: [PATCH] MIPS: BCM47XX: Add LEDs and buttons for Asus RTN-10U
-
-Add the definitions for the buttons and LEDs used on the Asus RTN-10U
-router.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/buttons.c | 9 +++++++++
- arch/mips/bcm47xx/leds.c | 11 +++++++++++
- 2 files changed, 20 insertions(+)
-
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -27,6 +27,12 @@
- /* Asus */
-
- static const struct gpio_keys_button
-+bcm47xx_buttons_asus_rtn10u[] __initconst = {
-+ BCM47XX_GPIO_KEY(20, KEY_WPS_BUTTON),
-+ BCM47XX_GPIO_KEY(21, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_asus_rtn12[] __initconst = {
- BCM47XX_GPIO_KEY(0, KEY_WPS_BUTTON),
- BCM47XX_GPIO_KEY(1, KEY_RESTART),
-@@ -490,6 +496,9 @@ int __init bcm47xx_buttons_register(void
- int err;
-
- switch (board) {
-+ case BCM47XX_BOARD_ASUS_RTN10U:
-+ err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn10u);
-+ break;
- case BCM47XX_BOARD_ASUS_RTN12:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_asus_rtn12);
- break;
---- a/arch/mips/bcm47xx/leds.c
-+++ b/arch/mips/bcm47xx/leds.c
-@@ -30,6 +30,14 @@
- /* Asus */
-
- static const struct gpio_led
-+bcm47xx_leds_asus_rtn10u[] __initconst = {
-+ BCM47XX_GPIO_LED(5, "green", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
-+ BCM47XX_GPIO_LED(6, "green", "power", 1, LEDS_GPIO_DEFSTATE_ON),
-+ BCM47XX_GPIO_LED(7, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
-+ BCM47XX_GPIO_LED(8, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
-+};
-+
-+static const struct gpio_led
- bcm47xx_leds_asus_rtn12[] __initconst = {
- BCM47XX_GPIO_LED(2, "unk", "power", 1, LEDS_GPIO_DEFSTATE_ON),
- BCM47XX_GPIO_LED(7, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
-@@ -563,6 +571,9 @@ void __init bcm47xx_leds_register(void)
- enum bcm47xx_board board = bcm47xx_board_get();
-
- switch (board) {
-+ case BCM47XX_BOARD_ASUS_RTN10U:
-+ bcm47xx_set_pdata(bcm47xx_leds_asus_rtn10u);
-+ break;
- case BCM47XX_BOARD_ASUS_RTN12:
- bcm47xx_set_pdata(bcm47xx_leds_asus_rtn12);
- break;
+++ /dev/null
-From 15e690af5cc3cd8f5d14ee2aa3a093f80196110e Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 6 Jan 2022 19:51:40 -0800
-Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear R6300 v1
-
-Add support for the Netgear R6300 v1 Wi-Fi router using a Broadcom
-BCM4706 chipset and supporting 802.11n and 802.11ac.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/board.c | 1 +
- arch/mips/bcm47xx/buttons.c | 8 ++++++++
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 +
- 3 files changed, 10 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -162,6 +162,7 @@ struct bcm47xx_board_type_list1 bcm47xx_
- {{BCM47XX_BOARD_LUXUL_XWR_600_V1, "Luxul XWR-600 V1"}, "luxul_xwr600_v1"},
- {{BCM47XX_BOARD_LUXUL_XWR_1750_V1, "Luxul XWR-1750 V1"}, "luxul_xwr1750_v1"},
- {{BCM47XX_BOARD_NETGEAR_R6200_V1, "Netgear R6200 V1"}, "U12H192T00_NETGEAR"},
-+ {{BCM47XX_BOARD_NETGEAR_R6300_V1, "Netgear R6300 V1"}, "U12H218T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -410,6 +410,11 @@ bcm47xx_buttons_netgear_r6200_v1[] __ini
- };
-
- static const struct gpio_keys_button
-+bcm47xx_buttons_netgear_r6300_v1[] __initconst = {
-+ BCM47XX_GPIO_KEY(6, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
- BCM47XX_GPIO_KEY(4, KEY_RESTART),
- BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
-@@ -701,6 +706,9 @@ int __init bcm47xx_buttons_register(void
- case BCM47XX_BOARD_NETGEAR_R6200_V1:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6200_v1);
- break;
-+ case BCM47XX_BOARD_NETGEAR_R6300_V1:
-+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1);
-+ break;
- case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
- break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -100,6 +100,7 @@ enum bcm47xx_board {
- BCM47XX_BOARD_MOTOROLA_WR850GV2V3,
-
- BCM47XX_BOARD_NETGEAR_R6200_V1,
-+ BCM47XX_BOARD_NETGEAR_R6300_V1,
- BCM47XX_BOARD_NETGEAR_WGR614V8,
- BCM47XX_BOARD_NETGEAR_WGR614V9,
- BCM47XX_BOARD_NETGEAR_WGR614_V10,
+++ /dev/null
-From 4da27b6d550427a0560a15df36de99cb17629216 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 6 Jan 2022 19:51:41 -0800
-Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear WN2500RP v1 & v2
-
-Add support for the Netgear WN2500 RP v1 and v2 Wi-Fi range extenders
-based on the BCM5357 chipset and supporting 802.11n and 802.11ac.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/board.c | 2 ++
- arch/mips/bcm47xx/buttons.c | 9 +++++++++
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 2 ++
- 3 files changed, 13 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -166,6 +166,8 @@ struct bcm47xx_board_type_list1 bcm47xx_
- {{BCM47XX_BOARD_NETGEAR_WGR614V8, "Netgear WGR614 V8"}, "U12H072T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WGR614V9, "Netgear WGR614 V9"}, "U12H094T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WGR614_V10, "Netgear WGR614 V10"}, "U12H139T01_NETGEAR"},
-+ {{BCM47XX_BOARD_NETGEAR_WN2500RP_V1, "Netgear WN2500RP V1"}, "U12H197T00_NETGEAR"},
-+ {{BCM47XX_BOARD_NETGEAR_WN2500RP_V2, "Netgear WN2500RP V2"}, "U12H294T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WNDR3300, "Netgear WNDR3300"}, "U12H093T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WNDR3400V1, "Netgear WNDR3400 V1"}, "U12H155T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WNDR3400V2, "Netgear WNDR3400 V2"}, "U12H187T00_NETGEAR"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -415,6 +415,12 @@ bcm47xx_buttons_netgear_r6300_v1[] __ini
- };
-
- static const struct gpio_keys_button
-+bcm47xx_buttons_netgear_wn2500rp_v1[] __initconst = {
-+ BCM47XX_GPIO_KEY(12, KEY_RESTART),
-+ BCM47XX_GPIO_KEY(31, KEY_WPS_BUTTON),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_netgear_wndr3400v1[] __initconst = {
- BCM47XX_GPIO_KEY(4, KEY_RESTART),
- BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
-@@ -709,6 +715,9 @@ int __init bcm47xx_buttons_register(void
- case BCM47XX_BOARD_NETGEAR_R6300_V1:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_r6300_v1);
- break;
-+ case BCM47XX_BOARD_NETGEAR_WN2500RP_V1:
-+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wn2500rp_v1);
-+ break;
- case BCM47XX_BOARD_NETGEAR_WNDR3400V1:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wndr3400v1);
- break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -104,6 +104,8 @@ enum bcm47xx_board {
- BCM47XX_BOARD_NETGEAR_WGR614V8,
- BCM47XX_BOARD_NETGEAR_WGR614V9,
- BCM47XX_BOARD_NETGEAR_WGR614_V10,
-+ BCM47XX_BOARD_NETGEAR_WN2500RP_V1,
-+ BCM47XX_BOARD_NETGEAR_WN2500RP_V2,
- BCM47XX_BOARD_NETGEAR_WNDR3300,
- BCM47XX_BOARD_NETGEAR_WNDR3400V1,
- BCM47XX_BOARD_NETGEAR_WNDR3400V2,
+++ /dev/null
-From c022e87162219d67d687df22c977d1c2fc95fb42 Mon Sep 17 00:00:00 2001
-From: Florian Fainelli <f.fainelli@gmail.com>
-Date: Thu, 14 Jul 2022 14:13:01 -0700
-Subject: [PATCH] MIPS: BCM47XX: Add support for Netgear WNR3500L v2
-
-Add support for the Netgear WNR3500L v2 router based on the BCM47186
-chipset and supporting 802.11n Wi-Fi.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/board.c | 2 ++
- arch/mips/bcm47xx/buttons.c | 10 ++++++++++
- arch/mips/bcm47xx/leds.c | 11 +++++++++++
- arch/mips/bcm47xx/workarounds.c | 1 +
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 +
- 5 files changed, 25 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -181,6 +181,7 @@ struct bcm47xx_board_type_list1 bcm47xx_
- {{BCM47XX_BOARD_NETGEAR_WNR1000_V3, "Netgear WNR1000 V3"}, "U12H139T50_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WNR2000, "Netgear WNR2000"}, "U12H114T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "U12H136T99_NETGEAR"},
-+ {{BCM47XX_BOARD_NETGEAR_WNR3500L_V2, "Netgear WNR3500L V2"}, "U12H172T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WNR3500U, "Netgear WNR3500U"}, "U12H136T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WNR3500V2, "Netgear WNR3500 V2"}, "U12H127T00_NETGEAR"},
- {{BCM47XX_BOARD_NETGEAR_WNR3500V2VC, "Netgear WNR3500 V2vc"}, "U12H127T70_NETGEAR"},
-@@ -195,6 +196,7 @@ struct bcm47xx_board_type_list3 bcm47xx_
- {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
- {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
- {{BCM47XX_BOARD_NETGEAR_WNR3500L, "Netgear WNR3500L"}, "0x04CF", "3500", "02"},
-+ {{BCM47XX_BOARD_NETGEAR_WNR3500L_V2, "Netgear WNR3500L V2"}, "0x052b", "3500L", "02"},
- {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0101, "Linksys WRT54G/GS/GL"}, "0x0101", "42", "0x10"},
- {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0467, "Linksys WRT54G/GS/GL"}, "0x0467", "42", "0x10"},
- {{BCM47XX_BOARD_LINKSYS_WRT54G_TYPE_0708, "Linksys WRT54G/GS/GL"}, "0x0708", "42", "0x10"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -460,6 +460,13 @@ bcm47xx_buttons_netgear_wnr3500lv1[] __i
- };
-
- static const struct gpio_keys_button
-+bcm47xx_buttons_netgear_wnr3500lv2[] __initconst = {
-+ BCM47XX_GPIO_KEY(4, KEY_RESTART),
-+ BCM47XX_GPIO_KEY(6, KEY_WPS_BUTTON),
-+ BCM47XX_GPIO_KEY(8, KEY_RFKILL),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_netgear_wnr834bv2[] __initconst = {
- BCM47XX_GPIO_KEY(6, KEY_RESTART),
- };
-@@ -736,6 +743,9 @@ int __init bcm47xx_buttons_register(void
- case BCM47XX_BOARD_NETGEAR_WNR3500L:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv1);
- break;
-+ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2:
-+ err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr3500lv2);
-+ break;
- case BCM47XX_BOARD_NETGEAR_WNR834BV2:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_netgear_wnr834bv2);
- break;
---- a/arch/mips/bcm47xx/leds.c
-+++ b/arch/mips/bcm47xx/leds.c
-@@ -528,6 +528,14 @@ bcm47xx_leds_netgear_wnr3500lv1[] __init
- };
-
- static const struct gpio_led
-+bcm47xx_leds_netgear_wnr3500lv2[] __initconst = {
-+ BCM47XX_GPIO_LED(0, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
-+ BCM47XX_GPIO_LED(1, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
-+ BCM47XX_GPIO_LED(3, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
-+ BCM47XX_GPIO_LED(7, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF),
-+};
-+
-+static const struct gpio_led
- bcm47xx_leds_netgear_wnr834bv2[] __initconst = {
- BCM47XX_GPIO_LED(2, "green", "power", 0, LEDS_GPIO_DEFSTATE_ON),
- BCM47XX_GPIO_LED(3, "amber", "power", 0, LEDS_GPIO_DEFSTATE_OFF),
-@@ -791,6 +799,9 @@ void __init bcm47xx_leds_register(void)
- case BCM47XX_BOARD_NETGEAR_WNR3500L:
- bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr3500lv1);
- break;
-+ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2:
-+ bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr3500lv2);
-+ break;
- case BCM47XX_BOARD_NETGEAR_WNR834BV2:
- bcm47xx_set_pdata(bcm47xx_leds_netgear_wnr834bv2);
- break;
---- a/arch/mips/bcm47xx/workarounds.c
-+++ b/arch/mips/bcm47xx/workarounds.c
-@@ -22,6 +22,7 @@ void __init bcm47xx_workarounds(void)
-
- switch (board) {
- case BCM47XX_BOARD_NETGEAR_WNR3500L:
-+ case BCM47XX_BOARD_NETGEAR_WNR3500L_V2:
- bcm47xx_workarounds_enable_usb_power(12);
- break;
- case BCM47XX_BOARD_NETGEAR_WNDR3400V2:
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -118,6 +118,7 @@ enum bcm47xx_board {
- BCM47XX_BOARD_NETGEAR_WNR1000_V3,
- BCM47XX_BOARD_NETGEAR_WNR2000,
- BCM47XX_BOARD_NETGEAR_WNR3500L,
-+ BCM47XX_BOARD_NETGEAR_WNR3500L_V2,
- BCM47XX_BOARD_NETGEAR_WNR3500U,
- BCM47XX_BOARD_NETGEAR_WNR3500V2,
- BCM47XX_BOARD_NETGEAR_WNR3500V2VC,
+++ /dev/null
-From fc605b914167de75432c3b5aae239fb191e84a31 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 8 Feb 2023 08:03:01 +0100
-Subject: [PATCH] MIPS: BCM47XX: Add support for Linksys E2500 V3
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-It's a BCM5358 based home WiFi router. 16 MiB flash, 64 MiB RAM, BCM5325
-switch, on-SoC 802.11n radio.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
----
- arch/mips/bcm47xx/board.c | 1 +
- arch/mips/bcm47xx/buttons.c | 9 +++++++++
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 +
- 3 files changed, 11 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -130,6 +130,7 @@ struct bcm47xx_board_type_list2 bcm47xx_
- {{BCM47XX_BOARD_LINKSYS_E1000V21, "Linksys E1000 V2.1"}, "E1000", "2.1"},
- {{BCM47XX_BOARD_LINKSYS_E1200V2, "Linksys E1200 V2"}, "E1200", "2.0"},
- {{BCM47XX_BOARD_LINKSYS_E2000V1, "Linksys E2000 V1"}, "Linksys E2000", "1.0"},
-+ {{BCM47XX_BOARD_LINKSYS_E2500V3, "Linksys E2500 V3"}, "E2500", "1.0"},
- /* like WRT610N v2.0 */
- {{BCM47XX_BOARD_LINKSYS_E3000V1, "Linksys E3000 V1"}, "E300", "1.0"},
- {{BCM47XX_BOARD_LINKSYS_E3200V1, "Linksys E3200 V1"}, "E3200", "1.0"},
---- a/arch/mips/bcm47xx/buttons.c
-+++ b/arch/mips/bcm47xx/buttons.c
-@@ -223,6 +223,12 @@ bcm47xx_buttons_linksys_e2000v1[] __init
- };
-
- static const struct gpio_keys_button
-+bcm47xx_buttons_linksys_e2500v3[] __initconst = {
-+ BCM47XX_GPIO_KEY(9, KEY_WPS_BUTTON),
-+ BCM47XX_GPIO_KEY(10, KEY_RESTART),
-+};
-+
-+static const struct gpio_keys_button
- bcm47xx_buttons_linksys_e3000v1[] __initconst = {
- BCM47XX_GPIO_KEY(4, KEY_WPS_BUTTON),
- BCM47XX_GPIO_KEY(6, KEY_RESTART),
-@@ -617,6 +623,9 @@ int __init bcm47xx_buttons_register(void
- case BCM47XX_BOARD_LINKSYS_E2000V1:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e2000v1);
- break;
-+ case BCM47XX_BOARD_LINKSYS_E2500V3:
-+ err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e2500v3);
-+ break;
- case BCM47XX_BOARD_LINKSYS_E3000V1:
- err = bcm47xx_copy_bdata(bcm47xx_buttons_linksys_e3000v1);
- break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -61,6 +61,7 @@ enum bcm47xx_board {
- BCM47XX_BOARD_LINKSYS_E1000V21,
- BCM47XX_BOARD_LINKSYS_E1200V2,
- BCM47XX_BOARD_LINKSYS_E2000V1,
-+ BCM47XX_BOARD_LINKSYS_E2500V3,
- BCM47XX_BOARD_LINKSYS_E3000V1,
- BCM47XX_BOARD_LINKSYS_E3200V1,
- BCM47XX_BOARD_LINKSYS_E4200V1,
+++ /dev/null
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 1/9] mtd: rawnand: brcmnand: Assign soc as early as possible
-Date: Fri, 07 Jan 2022 10:46:06 -0800
-Content-Type: text/plain; charset="utf-8"
-
-In order to key off the brcmnand_probe() code in subsequent changes
-depending upon ctrl->soc, assign that variable as early as possible,
-instead of much later when we have checked that it is non-NULL.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -3059,6 +3059,7 @@ int brcmnand_probe(struct platform_devic
-
- dev_set_drvdata(dev, ctrl);
- ctrl->dev = dev;
-+ ctrl->soc = soc;
-
- /* Enable the static key if the soc provides I/O operations indicating
- * that a non-memory mapped IO access path must be used
-@@ -3209,8 +3210,6 @@ int brcmnand_probe(struct platform_devic
- * interesting ways
- */
- if (soc) {
-- ctrl->soc = soc;
--
- ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
- DRV_NAME, ctrl);
-
+++ /dev/null
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 3/9] mtd: rawnand: brcmnand: Avoid pdev in brcmnand_init_cs()
-Date: Fri, 07 Jan 2022 10:46:08 -0800
-Content-Type: text/plain; charset="utf-8"
-
-In preparation for encapsulating more of what the loop calling
-brcmnand_init_cs() does, avoid using platform_device when it is the
-device behind platform_device that we are using for printing errors.
-
-No functional changes introduced.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -2814,7 +2814,7 @@ static const struct nand_controller_ops
- static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
- {
- struct brcmnand_controller *ctrl = host->ctrl;
-- struct platform_device *pdev = host->pdev;
-+ struct device *dev = ctrl->dev;
- struct mtd_info *mtd;
- struct nand_chip *chip;
- int ret;
-@@ -2822,7 +2822,7 @@ static int brcmnand_init_cs(struct brcmn
-
- ret = of_property_read_u32(dn, "reg", &host->cs);
- if (ret) {
-- dev_err(&pdev->dev, "can't get chip-select\n");
-+ dev_err(dev, "can't get chip-select\n");
- return -ENXIO;
- }
-
-@@ -2831,13 +2831,13 @@ static int brcmnand_init_cs(struct brcmn
-
- nand_set_flash_node(chip, dn);
- nand_set_controller_data(chip, host);
-- mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
-+ mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d",
- host->cs);
- if (!mtd->name)
- return -ENOMEM;
-
- mtd->owner = THIS_MODULE;
-- mtd->dev.parent = &pdev->dev;
-+ mtd->dev.parent = dev;
-
- chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl;
- chip->legacy.cmdfunc = brcmnand_cmdfunc;
+++ /dev/null
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 4/9] mtd: rawnand: brcmnand: Move OF operations out of brcmnand_init_cs()
-Date: Fri, 07 Jan 2022 10:46:09 -0800
-Content-Type: text/plain; charset="utf-8"
-
-In order to initialize a given chip select object for use by the
-brcmnand driver, move all of the Device Tree specific routines outside
-of brcmnand_init_cs() in order to make it usable in a platform data
-configuration which will be necessary for supporting BCMA chips.
-
-No functional changes introduced.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 20 +++++++++++---------
- 1 file changed, 11 insertions(+), 9 deletions(-)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -2811,7 +2811,7 @@ static const struct nand_controller_ops
- .attach_chip = brcmnand_attach_chip,
- };
-
--static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
-+static int brcmnand_init_cs(struct brcmnand_host *host)
- {
- struct brcmnand_controller *ctrl = host->ctrl;
- struct device *dev = ctrl->dev;
-@@ -2820,16 +2820,9 @@ static int brcmnand_init_cs(struct brcmn
- int ret;
- u16 cfg_offs;
-
-- ret = of_property_read_u32(dn, "reg", &host->cs);
-- if (ret) {
-- dev_err(dev, "can't get chip-select\n");
-- return -ENXIO;
-- }
--
- mtd = nand_to_mtd(&host->chip);
- chip = &host->chip;
-
-- nand_set_flash_node(chip, dn);
- nand_set_controller_data(chip, host);
- mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d",
- host->cs);
-@@ -3240,7 +3233,16 @@ int brcmnand_probe(struct platform_devic
- host->pdev = pdev;
- host->ctrl = ctrl;
-
-- ret = brcmnand_init_cs(host, child);
-+ ret = of_property_read_u32(child, "reg", &host->cs);
-+ if (ret) {
-+ dev_err(dev, "can't get chip-select\n");
-+ devm_kfree(dev, host);
-+ continue;
-+ }
-+
-+ nand_set_flash_node(&host->chip, child);
-+
-+ ret = brcmnand_init_cs(host);
- if (ret) {
- devm_kfree(dev, host);
- continue; /* Try all chip-selects */
+++ /dev/null
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 5/9] mtd: rawnand: brcmnand: Allow working without interrupts
-Date: Fri, 07 Jan 2022 10:46:10 -0800
-Content-Type: text/plain; charset="utf-8"
-
-The BCMA devices include the brcmnand controller but they do not wire up
-any interrupt line, allow the main interrupt to be optional and update
-the completion path to also check for the lack of an interrupt line.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 52 +++++++++++-------------
- 1 file changed, 24 insertions(+), 28 deletions(-)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -216,7 +216,7 @@ struct brcmnand_controller {
- void __iomem *nand_base;
- void __iomem *nand_fc; /* flash cache */
- void __iomem *flash_dma_base;
-- unsigned int irq;
-+ int irq;
- unsigned int dma_irq;
- int nand_version;
-
-@@ -1650,7 +1650,7 @@ static bool brcmstb_nand_wait_for_comple
- bool err = false;
- int sts;
-
-- if (mtd->oops_panic_write) {
-+ if (mtd->oops_panic_write || ctrl->irq < 0) {
- /* switch to interrupt polling and PIO mode */
- disable_ctrl_irqs(ctrl);
- sts = bcmnand_ctrl_poll_status(ctrl, NAND_CTRL_RDY,
-@@ -3191,33 +3191,29 @@ int brcmnand_probe(struct platform_devic
- }
-
- /* IRQ */
-- ctrl->irq = platform_get_irq(pdev, 0);
-- if ((int)ctrl->irq < 0) {
-- dev_err(dev, "no IRQ defined\n");
-- ret = -ENODEV;
-- goto err;
-- }
--
-- /*
-- * Some SoCs integrate this controller (e.g., its interrupt bits) in
-- * interesting ways
-- */
-- if (soc) {
-- ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
-- DRV_NAME, ctrl);
--
-- /* Enable interrupt */
-- ctrl->soc->ctlrdy_ack(ctrl->soc);
-- ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
-- } else {
-- /* Use standard interrupt infrastructure */
-- ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
-- DRV_NAME, ctrl);
-- }
-- if (ret < 0) {
-- dev_err(dev, "can't allocate IRQ %d: error %d\n",
-- ctrl->irq, ret);
-- goto err;
-+ ctrl->irq = platform_get_irq_optional(pdev, 0);
-+ if (ctrl->irq > 0) {
-+ /*
-+ * Some SoCs integrate this controller (e.g., its interrupt bits) in
-+ * interesting ways
-+ */
-+ if (soc) {
-+ ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
-+ DRV_NAME, ctrl);
-+
-+ /* Enable interrupt */
-+ ctrl->soc->ctlrdy_ack(ctrl->soc);
-+ ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
-+ } else {
-+ /* Use standard interrupt infrastructure */
-+ ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
-+ DRV_NAME, ctrl);
-+ }
-+ if (ret < 0) {
-+ dev_err(dev, "can't allocate IRQ %d: error %d\n",
-+ ctrl->irq, ret);
-+ goto err;
-+ }
- }
-
- for_each_available_child_of_node(dn, child) {
+++ /dev/null
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 6/9] mtd: rawnand: brcmnand: Add platform data structure for BCMA
-Date: Fri, 07 Jan 2022 10:46:11 -0800
-Content-Type: text/plain; charset="utf-8"
-
-Update the BCMA's chipcommon nand flash driver to detect which
-chip-select is used and pass that information via platform data to the
-brcmnand driver. Make sure that the brcmnand platform data structure is
-always at the beginning of the platform data of the "nflash" device
-created by BCMA to allow brcmnand to safely de-reference it.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- MAINTAINERS | 1 +
- drivers/bcma/driver_chipcommon_nflash.c | 20 +++++++++++++++++++-
- include/linux/bcma/bcma_driver_chipcommon.h | 5 +++++
- include/linux/platform_data/brcmnand.h | 12 ++++++++++++
- 4 files changed, 37 insertions(+), 1 deletion(-)
- create mode 100644 include/linux/platform_data/brcmnand.h
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -3901,6 +3901,7 @@ L: linux-mtd@lists.infradead.org
- L: bcm-kernel-feedback-list@broadcom.com
- S: Maintained
- F: drivers/mtd/nand/raw/brcmnand/
-+F: include/linux/platform_data/brcmnand.h
-
- BROADCOM STB PCIE DRIVER
- M: Jim Quinlan <jim2101024@gmail.com>
---- a/drivers/bcma/driver_chipcommon_nflash.c
-+++ b/drivers/bcma/driver_chipcommon_nflash.c
-@@ -7,18 +7,28 @@
-
- #include "bcma_private.h"
-
-+#include <linux/bitops.h>
- #include <linux/platform_device.h>
-+#include <linux/platform_data/brcmnand.h>
- #include <linux/bcma/bcma.h>
-
-+/* Alternate NAND controller driver name in order to allow both bcm47xxnflash
-+ * and bcma_brcmnand to be built into the same kernel image.
-+ */
-+static const char *bcma_nflash_alt_name = "bcma_brcmnand";
-+
- struct platform_device bcma_nflash_dev = {
- .name = "bcma_nflash",
- .num_resources = 0,
- };
-
-+static const char *probes[] = { "bcm47xxpart", NULL };
-+
- /* Initialize NAND flash access */
- int bcma_nflash_init(struct bcma_drv_cc *cc)
- {
- struct bcma_bus *bus = cc->core->bus;
-+ u32 reg;
-
- if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4706 &&
- cc->core->id.rev != 38) {
-@@ -33,8 +43,16 @@ int bcma_nflash_init(struct bcma_drv_cc
-
- cc->nflash.present = true;
- if (cc->core->id.rev == 38 &&
-- (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT))
-+ (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)) {
- cc->nflash.boot = true;
-+ /* Determine the chip select that is being used */
-+ reg = bcma_cc_read32(cc, BCMA_CC_NAND_CS_NAND_SELECT) & 0xff;
-+ cc->nflash.brcmnand_info.chip_select = ffs(reg) - 1;
-+ cc->nflash.brcmnand_info.part_probe_types = probes;
-+ cc->nflash.brcmnand_info.ecc_stepsize = 512;
-+ cc->nflash.brcmnand_info.ecc_strength = 1;
-+ bcma_nflash_dev.name = bcma_nflash_alt_name;
-+ }
-
- /* Prepare platform device, but don't register it yet. It's too early,
- * malloc (required by device_private_init) is not available yet. */
---- a/include/linux/bcma/bcma_driver_chipcommon.h
-+++ b/include/linux/bcma/bcma_driver_chipcommon.h
-@@ -3,6 +3,7 @@
- #define LINUX_BCMA_DRIVER_CC_H_
-
- #include <linux/platform_device.h>
-+#include <linux/platform_data/brcmnand.h>
- #include <linux/gpio.h>
-
- /** ChipCommon core registers. **/
-@@ -599,6 +600,10 @@ struct bcma_sflash {
-
- #ifdef CONFIG_BCMA_NFLASH
- struct bcma_nflash {
-+ /* Must be the fist member for the brcmnand driver to
-+ * de-reference that structure.
-+ */
-+ struct brcmnand_platform_data brcmnand_info;
- bool present;
- bool boot; /* This is the flash the SoC boots from */
- };
---- /dev/null
-+++ b/include/linux/platform_data/brcmnand.h
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+#ifndef BRCMNAND_PLAT_DATA_H
-+#define BRCMNAND_PLAT_DATA_H
-+
-+struct brcmnand_platform_data {
-+ int chip_select;
-+ const char * const *part_probe_types;
-+ unsigned int ecc_stepsize;
-+ unsigned int ecc_strength;
-+};
-+
-+#endif /* BRCMNAND_PLAT_DATA_H */
+++ /dev/null
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 7/9] mtd: rawnand: brcmnand: Allow platform data instantation
-Date: Fri, 07 Jan 2022 10:46:12 -0800
-Content-Type: text/plain; charset="utf-8"
-
-Make use of the recently refactored code in brcmnand_init_cs() and
-derive the chip-select from the platform data that is supplied. Update
-the various code paths to avoid relying on possibly non-existent
-resources, too.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 45 ++++++++++++++++++------
- 1 file changed, 35 insertions(+), 10 deletions(-)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -9,6 +9,7 @@
- #include <linux/delay.h>
- #include <linux/device.h>
- #include <linux/platform_device.h>
-+#include <linux/platform_data/brcmnand.h>
- #include <linux/err.h>
- #include <linux/completion.h>
- #include <linux/interrupt.h>
-@@ -2811,7 +2812,8 @@ static const struct nand_controller_ops
- .attach_chip = brcmnand_attach_chip,
- };
-
--static int brcmnand_init_cs(struct brcmnand_host *host)
-+static int brcmnand_init_cs(struct brcmnand_host *host,
-+ const char * const *part_probe_types)
- {
- struct brcmnand_controller *ctrl = host->ctrl;
- struct device *dev = ctrl->dev;
-@@ -2864,7 +2866,7 @@ static int brcmnand_init_cs(struct brcmn
- if (ret)
- return ret;
-
-- ret = mtd_device_register(mtd, NULL, 0);
-+ ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
- if (ret)
- nand_cleanup(chip);
-
-@@ -3033,17 +3035,15 @@ static int brcmnand_edu_setup(struct pla
-
- int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
- {
-+ struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev);
- struct device *dev = &pdev->dev;
- struct device_node *dn = dev->of_node, *child;
- struct brcmnand_controller *ctrl;
-+ struct brcmnand_host *host;
- struct resource *res;
- int ret;
-
-- /* We only support device-tree instantiation */
-- if (!dn)
-- return -ENODEV;
--
-- if (!of_match_node(brcmnand_of_match, dn))
-+ if (dn && !of_match_node(brcmnand_of_match, dn))
- return -ENODEV;
-
- ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
-@@ -3070,7 +3070,7 @@ int brcmnand_probe(struct platform_devic
- /* NAND register range */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- ctrl->nand_base = devm_ioremap_resource(dev, res);
-- if (IS_ERR(ctrl->nand_base))
-+ if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc))
- return PTR_ERR(ctrl->nand_base);
-
- /* Enable clock before using NAND registers */
-@@ -3218,7 +3218,6 @@ int brcmnand_probe(struct platform_devic
-
- for_each_available_child_of_node(dn, child) {
- if (of_device_is_compatible(child, "brcm,nandcs")) {
-- struct brcmnand_host *host;
-
- host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
- if (!host) {
-@@ -3238,7 +3237,7 @@ int brcmnand_probe(struct platform_devic
-
- nand_set_flash_node(&host->chip, child);
-
-- ret = brcmnand_init_cs(host);
-+ ret = brcmnand_init_cs(host, NULL);
- if (ret) {
- devm_kfree(dev, host);
- continue; /* Try all chip-selects */
-@@ -3248,6 +3247,32 @@ int brcmnand_probe(struct platform_devic
- }
- }
-
-+ if (!list_empty(&ctrl->host_list))
-+ return 0;
-+
-+ if (!pd) {
-+ ret = -ENODEV;
-+ goto err;
-+ }
-+
-+ /* If we got there we must have been probing via platform data */
-+ host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
-+ if (!host) {
-+ ret = -ENOMEM;
-+ goto err;
-+ }
-+ host->pdev = pdev;
-+ host->ctrl = ctrl;
-+ host->cs = pd->chip_select;
-+ host->chip.ecc.size = pd->ecc_stepsize;
-+ host->chip.ecc.strength = pd->ecc_strength;
-+
-+ ret = brcmnand_init_cs(host, pd->part_probe_types);
-+ if (ret)
-+ goto err;
-+
-+ list_add_tail(&host->node, &ctrl->host_list);
-+
- /* No chip-selects could initialize properly */
- if (list_empty(&ctrl->host_list)) {
- ret = -ENODEV;
+++ /dev/null
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 8/9] mtd: rawnand: brcmnand: BCMA controller uses command shift of 0
-Date: Fri, 07 Jan 2022 10:46:13 -0800
-Content-Type: text/plain; charset="utf-8"
-
-For some odd and unexplained reason the BCMA NAND controller, albeit
-revision 3.4 uses a command shift of 0 instead of 24 as it should be,
-quirk that.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -951,6 +951,12 @@ static void brcmnand_wr_corr_thresh(stru
-
- static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
- {
-+ /* Kludge for the BCMA-based NAND controller which does not actually
-+ * shift the command
-+ */
-+ if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl))
-+ return 0;
-+
- if (ctrl->nand_version < 0x0602)
- return 24;
- return 0;
+++ /dev/null
-From: Florian Fainelli <f.fainelli@gmail.com>
-Subject: [PATCH v3 9/9] mtd: rawnand: brcmnand: Add BCMA shim
-Date: Fri, 07 Jan 2022 10:46:14 -0800
-Content-Type: text/plain; charset="utf-8"
-
-Add a BCMA shim to allow us to register the brcmnand driver using the
-BCMA bus which provides indirect memory mapped access to SoC registers.
-
-There are a number of registers that need to be byte swapped because
-they are natively big endian, coming directly from the NAND chip, and
-there is no bus interface unlike the iProc or STB platforms that
-performs the byte swapping for us.
-
-Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
----
- drivers/mtd/nand/raw/Kconfig | 13 +++
- drivers/mtd/nand/raw/brcmnand/Makefile | 2 +
- drivers/mtd/nand/raw/brcmnand/bcma_nand.c | 132 ++++++++++++++++++++++
- drivers/mtd/nand/raw/brcmnand/brcmnand.c | 4 +
- 4 files changed, 151 insertions(+)
- create mode 100644 drivers/mtd/nand/raw/brcmnand/bcma_nand.c
-
---- a/drivers/mtd/nand/raw/Kconfig
-+++ b/drivers/mtd/nand/raw/Kconfig
-@@ -208,6 +208,19 @@ config MTD_NAND_BRCMNAND
- originally designed for Set-Top Box but is used on various BCM7xxx,
- BCM3xxx, BCM63xxx, iProc/Cygnus and more.
-
-+if MTD_NAND_BRCMNAND
-+
-+config MTD_NAND_BRCMNAND_BCMA
-+ tristate "Broadcom BCMA NAND controller"
-+ depends on BCMA_NFLASH
-+ depends on BCMA
-+ help
-+ Enables the BRCMNAND controller over BCMA on BCM47186/BCM5358 SoCs.
-+ The glue driver will take care of performing the low-level I/O
-+ operations to interface the BRCMNAND controller over the BCMA bus.
-+
-+endif # MTD_NAND_BRCMNAND
-+
- config MTD_NAND_BCM47XXNFLASH
- tristate "BCM4706 BCMA NAND controller"
- depends on BCMA_NFLASH
---- a/drivers/mtd/nand/raw/brcmnand/Makefile
-+++ b/drivers/mtd/nand/raw/brcmnand/Makefile
-@@ -6,3 +6,5 @@ obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm6
- obj-$(CONFIG_MTD_NAND_BRCMNAND) += bcm6368_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmstb_nand.o
- obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand.o
-+
-+obj-$(CONFIG_MTD_NAND_BRCMNAND_BCMA) += bcma_nand.o
---- /dev/null
-+++ b/drivers/mtd/nand/raw/brcmnand/bcma_nand.c
-@@ -0,0 +1,132 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright © 2021 Broadcom
-+ */
-+#include <linux/bcma/bcma.h>
-+#include <linux/bcma/bcma_driver_chipcommon.h>
-+#include <linux/device.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+
-+#include "brcmnand.h"
-+
-+struct brcmnand_bcma_soc {
-+ struct brcmnand_soc soc;
-+ struct bcma_drv_cc *cc;
-+};
-+
-+static inline bool brcmnand_bcma_needs_swapping(u32 offset)
-+{
-+ switch (offset) {
-+ case BCMA_CC_NAND_SPARE_RD0:
-+ case BCMA_CC_NAND_SPARE_RD4:
-+ case BCMA_CC_NAND_SPARE_RD8:
-+ case BCMA_CC_NAND_SPARE_RD12:
-+ case BCMA_CC_NAND_SPARE_WR0:
-+ case BCMA_CC_NAND_SPARE_WR4:
-+ case BCMA_CC_NAND_SPARE_WR8:
-+ case BCMA_CC_NAND_SPARE_WR12:
-+ case BCMA_CC_NAND_DEVID:
-+ case BCMA_CC_NAND_DEVID_X:
-+ case BCMA_CC_NAND_SPARE_RD16:
-+ case BCMA_CC_NAND_SPARE_RD20:
-+ case BCMA_CC_NAND_SPARE_RD24:
-+ case BCMA_CC_NAND_SPARE_RD28:
-+ return true;
-+ }
-+
-+ return false;
-+}
-+
-+static inline struct brcmnand_bcma_soc *to_bcma_soc(struct brcmnand_soc *soc)
-+{
-+ return container_of(soc, struct brcmnand_bcma_soc, soc);
-+}
-+
-+static u32 brcmnand_bcma_read_reg(struct brcmnand_soc *soc, u32 offset)
-+{
-+ struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
-+ u32 val;
-+
-+ /* Offset into the NAND block and deal with the flash cache separately */
-+ if (offset == BRCMNAND_NON_MMIO_FC_ADDR)
-+ offset = BCMA_CC_NAND_CACHE_DATA;
-+ else
-+ offset += BCMA_CC_NAND_REVISION;
-+
-+ val = bcma_cc_read32(sc->cc, offset);
-+
-+ /* Swap if necessary */
-+ if (brcmnand_bcma_needs_swapping(offset))
-+ val = be32_to_cpu(val);
-+ return val;
-+}
-+
-+static void brcmnand_bcma_write_reg(struct brcmnand_soc *soc, u32 val,
-+ u32 offset)
-+{
-+ struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
-+
-+ /* Offset into the NAND block */
-+ if (offset == BRCMNAND_NON_MMIO_FC_ADDR)
-+ offset = BCMA_CC_NAND_CACHE_DATA;
-+ else
-+ offset += BCMA_CC_NAND_REVISION;
-+
-+ /* Swap if necessary */
-+ if (brcmnand_bcma_needs_swapping(offset))
-+ val = cpu_to_be32(val);
-+
-+ bcma_cc_write32(sc->cc, offset, val);
-+}
-+
-+static struct brcmnand_io_ops brcmnand_bcma_io_ops = {
-+ .read_reg = brcmnand_bcma_read_reg,
-+ .write_reg = brcmnand_bcma_write_reg,
-+};
-+
-+static void brcmnand_bcma_prepare_data_bus(struct brcmnand_soc *soc, bool prepare,
-+ bool is_param)
-+{
-+ struct brcmnand_bcma_soc *sc = to_bcma_soc(soc);
-+
-+ /* Reset the cache address to ensure we are already accessing the
-+ * beginning of a sub-page.
-+ */
-+ bcma_cc_write32(sc->cc, BCMA_CC_NAND_CACHE_ADDR, 0);
-+}
-+
-+static int brcmnand_bcma_nand_probe(struct platform_device *pdev)
-+{
-+ struct bcma_nflash *nflash = dev_get_platdata(&pdev->dev);
-+ struct brcmnand_bcma_soc *soc;
-+
-+ soc = devm_kzalloc(&pdev->dev, sizeof(*soc), GFP_KERNEL);
-+ if (!soc)
-+ return -ENOMEM;
-+
-+ soc->cc = container_of(nflash, struct bcma_drv_cc, nflash);
-+ soc->soc.prepare_data_bus = brcmnand_bcma_prepare_data_bus;
-+ soc->soc.ops = &brcmnand_bcma_io_ops;
-+
-+ if (soc->cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) {
-+ dev_err(&pdev->dev, "Use bcm47xxnflash for 4706!\n");
-+ return -ENODEV;
-+ }
-+
-+ return brcmnand_probe(pdev, &soc->soc);
-+}
-+
-+static struct platform_driver brcmnand_bcma_nand_driver = {
-+ .probe = brcmnand_bcma_nand_probe,
-+ .remove = brcmnand_remove,
-+ .driver = {
-+ .name = "bcma_brcmnand",
-+ .pm = &brcmnand_pm_ops,
-+ }
-+};
-+module_platform_driver(brcmnand_bcma_nand_driver);
-+
-+MODULE_LICENSE("GPL v2");
-+MODULE_AUTHOR("Broadcom");
-+MODULE_DESCRIPTION("NAND controller driver glue for BCMA chips");
---- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-+++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
-@@ -627,7 +627,11 @@ enum {
-
- static inline bool brcmnand_non_mmio_ops(struct brcmnand_controller *ctrl)
- {
-+#if IS_ENABLED(CONFIG_MTD_NAND_BRCMNAND_BCMA)
- return static_branch_unlikely(&brcmnand_soc_has_ops_key);
-+#else
-+ return false;
-+#endif
- }
-
- static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Mon, 27 Feb 2023 07:44:38 +0100
-Subject: [PATCH] MIPS: BCM47XX: Add support for Huawei B593u-12
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-It's a BCM5358 based home router. One of very few bcm47xx devices with
-cellular modems (here: LTE).
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- arch/mips/bcm47xx/board.c | 1 +
- arch/mips/bcm47xx/leds.c | 8 ++++++++
- arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h | 1 +
- 3 files changed, 10 insertions(+)
-
---- a/arch/mips/bcm47xx/board.c
-+++ b/arch/mips/bcm47xx/board.c
-@@ -193,6 +193,7 @@ struct bcm47xx_board_type_list1 bcm47xx_
- /* boardtype, boardnum, boardrev */
- static const
- struct bcm47xx_board_type_list3 bcm47xx_board_list_board[] __initconst = {
-+ {{BCM47XX_BOARD_HUAWEI_B593U_12, "Huawei B593u-12"}, "0x053d", "1234", "0x1301"},
- {{BCM47XX_BOARD_HUAWEI_E970, "Huawei E970"}, "0x048e", "0x5347", "0x11"},
- {{BCM47XX_BOARD_PHICOMM_M1, "Phicomm M1"}, "0x0590", "80", "0x1104"},
- {{BCM47XX_BOARD_ZTE_H218N, "ZTE H218N"}, "0x053d", "1234", "0x1305"},
---- a/arch/mips/bcm47xx/leds.c
-+++ b/arch/mips/bcm47xx/leds.c
-@@ -223,6 +223,11 @@ bcm47xx_leds_dlink_dir330[] __initconst
- /* Huawei */
-
- static const struct gpio_led
-+bcm47xx_leds_huawei_b593u_12[] __initconst = {
-+ BCM47XX_GPIO_LED(5, "blue", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
-+};
-+
-+static const struct gpio_led
- bcm47xx_leds_huawei_e970[] __initconst = {
- BCM47XX_GPIO_LED(0, "unk", "wlan", 0, LEDS_GPIO_DEFSTATE_OFF),
- };
-@@ -672,6 +677,9 @@ void __init bcm47xx_leds_register(void)
- bcm47xx_set_pdata(bcm47xx_leds_dlink_dir330);
- break;
-
-+ case BCM47XX_BOARD_HUAWEI_B593U_12:
-+ bcm47xx_set_pdata(bcm47xx_leds_huawei_b593u_12);
-+ break;
- case BCM47XX_BOARD_HUAWEI_E970:
- bcm47xx_set_pdata(bcm47xx_leds_huawei_e970);
- break;
---- a/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/bcm47xx_board.h
-@@ -53,6 +53,7 @@ enum bcm47xx_board {
- BCM47XX_BOARD_DLINK_DIR130,
- BCM47XX_BOARD_DLINK_DIR330,
-
-+ BCM47XX_BOARD_HUAWEI_B593U_12,
- BCM47XX_BOARD_HUAWEI_E970,
-
- BCM47XX_BOARD_LINKSYS_E900V1,
+++ /dev/null
---- a/arch/mips/include/asm/r4kcache.h
-+++ b/arch/mips/include/asm/r4kcache.h
-@@ -27,6 +27,38 @@
- extern void (*r4k_blast_dcache)(void);
- extern void (*r4k_blast_icache)(void);
-
-+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
-+#include <asm/paccess.h>
-+#include <linux/ssb/ssb.h>
-+#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
-+
-+static inline unsigned long bcm4710_dummy_rreg(void)
-+{
-+ return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
-+}
-+
-+#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
-+
-+static inline unsigned long bcm4710_fill_tlb(void *addr)
-+{
-+ return *(unsigned long *)addr;
-+}
-+
-+#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
-+
-+static inline void bcm4710_protected_fill_tlb(void *addr)
-+{
-+ unsigned long x;
-+ get_dbe(x, (unsigned long *)addr);;
-+}
-+
-+#else
-+#define BCM4710_DUMMY_RREG()
-+
-+#define BCM4710_FILL_TLB(addr)
-+#define BCM4710_PROTECTED_FILL_TLB(addr)
-+#endif
-+
- /*
- * This macro return a properly sign-extended address suitable as base address
- * for indexed cache operations. Two issues here:
-@@ -60,6 +92,7 @@ static inline void flush_icache_line_ind
-
- static inline void flush_dcache_line_indexed(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- cache_op(Index_Writeback_Inv_D, addr);
- }
-
-@@ -83,11 +116,13 @@ static inline void flush_icache_line(uns
-
- static inline void flush_dcache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Writeback_Inv_D, addr);
- }
-
- static inline void invalidate_dcache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- cache_op(Hit_Invalidate_D, addr);
- }
-
-@@ -160,6 +195,7 @@ static inline int protected_flush_icache
- return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
-
- default:
-+ BCM4710_DUMMY_RREG();
- return protected_cache_op(Hit_Invalidate_I, addr);
- }
- }
-@@ -172,6 +208,7 @@ static inline int protected_flush_icache
- */
- static inline int protected_writeback_dcache_line(unsigned long addr)
- {
-+ BCM4710_DUMMY_RREG();
- return protected_cache_op(Hit_Writeback_Inv_D, addr);
- }
-
-@@ -193,8 +230,51 @@ static inline void invalidate_tcache_pag
- unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize))); \
- } while (0)
-
-+static inline void blast_dcache(void)
-+{
-+ unsigned long start = KSEG0;
-+ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
-+ unsigned long end = (start + dcache_size);
-+
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+
-+ BCM4710_FILL_TLB(start);
-+ do {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Hit_Writeback_Inv_D, start);
-+ start += current_cpu_data.dcache.linesz;
-+ } while(start < end);
-+}
-+
-+static inline void blast_dcache_page_indexed(unsigned long page)
-+{
-+ unsigned long start = page;
-+ unsigned long end = start + PAGE_SIZE;
-+ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
-+ unsigned long ws_end = current_cpu_data.dcache.ways <<
-+ current_cpu_data.dcache.waybit;
-+ unsigned long ws, addr;
-+ for (ws = 0; ws < ws_end; ws += ws_inc) {
-+ start = page + ws;
-+ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
-+ BCM4710_DUMMY_RREG();
-+ cache_op(Index_Writeback_Inv_D, addr);
-+ }
-+ }
-+}
-+
- /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
--#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
-+#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
- static inline void extra##blast_##pfx##cache##lsize(void) \
- { \
- unsigned long start = INDEX_BASE; \
-@@ -204,6 +284,7 @@ static inline void extra##blast_##pfx##c
- current_cpu_data.desc.waybit; \
- unsigned long ws, addr; \
- \
-+ war \
- for (ws = 0; ws < ws_end; ws += ws_inc) \
- for (addr = start; addr < end; addr += lsize * 32) \
- cache_unroll(32, kernel_cache, indexop, \
-@@ -215,6 +296,7 @@ static inline void extra##blast_##pfx##c
- unsigned long start = page; \
- unsigned long end = page + PAGE_SIZE; \
- \
-+ war \
- do { \
- cache_unroll(32, kernel_cache, hitop, start, lsize); \
- start += lsize * 32; \
-@@ -231,32 +313,33 @@ static inline void extra##blast_##pfx##c
- current_cpu_data.desc.waybit; \
- unsigned long ws, addr; \
- \
-+ war \
- for (ws = 0; ws < ws_end; ws += ws_inc) \
- for (addr = start; addr < end; addr += lsize * 32) \
- cache_unroll(32, kernel_cache, indexop, \
- addr | ws, lsize); \
- }
-
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
--__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
--__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
--__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
--
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
--__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
--__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
-+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
-+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
-+__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
-+
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
-+__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
-+__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
-
- #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
- static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
-@@ -281,65 +364,36 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
- __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
-
- /* build blast_xxx_range, protected_blast_xxx_range */
--#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
-+#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2) \
- static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
- unsigned long end) \
- { \
- unsigned long lsize = cpu_##desc##_line_size(); \
-- unsigned long lsize_2 = lsize * 2; \
-- unsigned long lsize_3 = lsize * 3; \
-- unsigned long lsize_4 = lsize * 4; \
-- unsigned long lsize_5 = lsize * 5; \
-- unsigned long lsize_6 = lsize * 6; \
-- unsigned long lsize_7 = lsize * 7; \
-- unsigned long lsize_8 = lsize * 8; \
- unsigned long addr = start & ~(lsize - 1); \
-- unsigned long aend = (end + lsize - 1) & ~(lsize - 1); \
-- int lines = (aend - addr) / lsize; \
-- \
-- while (lines >= 8) { \
-- prot##cache_op(hitop, addr); \
-- prot##cache_op(hitop, addr + lsize); \
-- prot##cache_op(hitop, addr + lsize_2); \
-- prot##cache_op(hitop, addr + lsize_3); \
-- prot##cache_op(hitop, addr + lsize_4); \
-- prot##cache_op(hitop, addr + lsize_5); \
-- prot##cache_op(hitop, addr + lsize_6); \
-- prot##cache_op(hitop, addr + lsize_7); \
-- addr += lsize_8; \
-- lines -= 8; \
-- } \
-+ unsigned long aend = (end - 1) & ~(lsize - 1); \
- \
-- if (lines & 0x4) { \
-- prot##cache_op(hitop, addr); \
-- prot##cache_op(hitop, addr + lsize); \
-- prot##cache_op(hitop, addr + lsize_2); \
-- prot##cache_op(hitop, addr + lsize_3); \
-- addr += lsize_4; \
-- } \
-- \
-- if (lines & 0x2) { \
-- prot##cache_op(hitop, addr); \
-- prot##cache_op(hitop, addr + lsize); \
-- addr += lsize_2; \
-- } \
-+ war \
- \
-- if (lines & 0x1) { \
-+ while (1) { \
-+ war2 \
- prot##cache_op(hitop, addr); \
-+ if (addr == aend) \
-+ break; \
-+ addr += lsize; \
- } \
- }
-
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
--__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
- __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
-- protected_, loongson2_)
--__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
--__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
--__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
-+ protected_, loongson2_, , )
-+__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )
-+__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
- /* blast_inv_dcache_range */
--__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
--__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
-+__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
-+__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
-
- /* Currently, this is very specific to Loongson-3 */
- #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \
---- a/arch/mips/include/asm/stackframe.h
-+++ b/arch/mips/include/asm/stackframe.h
-@@ -429,6 +429,10 @@
- #else
- .set push
- .set arch=r4000
-+#ifdef CONFIG_BCM47XX
-+ nop
-+ nop
-+#endif
- eret
- .set pop
- #endif
---- a/arch/mips/kernel/genex.S
-+++ b/arch/mips/kernel/genex.S
-@@ -22,6 +22,19 @@
- #include <asm/war.h>
- #include <asm/thread_info.h>
-
-+#ifdef CONFIG_BCM47XX
-+# ifdef eret
-+# undef eret
-+# endif
-+# define eret \
-+ .set push; \
-+ .set noreorder; \
-+ nop; \
-+ nop; \
-+ eret; \
-+ .set pop;
-+#endif
-+
- __INIT
-
- /*
-@@ -33,6 +46,9 @@
- NESTED(except_vec3_generic, 0, sp)
- .set push
- .set noat
-+#ifdef CONFIG_BCM47XX
-+ nop
-+#endif
- mfc0 k1, CP0_CAUSE
- andi k1, k1, 0x7c
- #ifdef CONFIG_64BIT
-@@ -53,6 +69,9 @@ NESTED(except_vec3_r4000, 0, sp)
- .set push
- .set arch=r4000
- .set noat
-+#ifdef CONFIG_BCM47XX
-+ nop
-+#endif
- mfc0 k1, CP0_CAUSE
- li k0, 31<<2
- andi k1, k1, 0x7c
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -38,6 +38,9 @@
- #include <asm/traps.h>
- #include <asm/mips-cps.h>
-
-+/* For enabling BCM4710 cache workarounds */
-+static int bcm4710 = 0;
-+
- /*
- * Bits describing what cache ops an SMP callback function may perform.
- *
-@@ -190,6 +193,9 @@ static void r4k_blast_dcache_user_page_s
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache_page = blast_dcache_page;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache_user_page = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -208,6 +214,9 @@ static void r4k_blast_dcache_page_indexe
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache_page_indexed = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -227,6 +236,9 @@ static void r4k_blast_dcache_setup(void)
- {
- unsigned long dc_lsize = cpu_dcache_line_size();
-
-+ if (bcm4710)
-+ r4k_blast_dcache = blast_dcache;
-+ else
- if (dc_lsize == 0)
- r4k_blast_dcache = (void *)cache_noop;
- else if (dc_lsize == 16)
-@@ -1826,6 +1838,17 @@ static void coherency_setup(void)
- * silly idea of putting something else there ...
- */
- switch (current_cpu_type()) {
-+ case CPU_BMIPS3300:
-+ {
-+ u32 cm;
-+ cm = read_c0_diag();
-+ /* Enable icache */
-+ cm |= (1 << 31);
-+ /* Enable dcache */
-+ cm |= (1 << 30);
-+ write_c0_diag(cm);
-+ }
-+ break;
- case CPU_R4000PC:
- case CPU_R4000SC:
- case CPU_R4000MC:
-@@ -1872,6 +1895,15 @@ void r4k_cache_init(void)
- extern void build_copy_page(void);
- struct cpuinfo_mips *c = ¤t_cpu_data;
-
-+ /* Check if special workarounds are required */
-+#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
-+ if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
-+ printk("Enabling BCM4710A0 cache workarounds.\n");
-+ bcm4710 = 1;
-+ } else
-+#endif
-+ bcm4710 = 0;
-+
- probe_pcache();
- probe_vcache();
- setup_scache();
-@@ -1944,7 +1976,15 @@ void r4k_cache_init(void)
- */
- local_r4k___flush_cache_all(NULL);
-
-+#ifdef CONFIG_BCM47XX
-+ {
-+ static void (*_coherency_setup)(void);
-+ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
-+ _coherency_setup();
-+ }
-+#else
- coherency_setup();
-+#endif
- board_cache_error_setup = r4k_cache_error_setup;
-
- /*
---- a/arch/mips/mm/tlbex.c
-+++ b/arch/mips/mm/tlbex.c
-@@ -985,6 +985,9 @@ void build_get_pgde32(u32 **p, unsigned
- uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
- uasm_i_addu(p, ptr, tmp, ptr);
- #else
-+#ifdef CONFIG_BCM47XX
-+ uasm_i_nop(p);
-+#endif
- UASM_i_LA_mostly(p, ptr, pgdc);
- #endif
- uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
-@@ -1347,6 +1350,9 @@ static void build_r4000_tlb_refill_handl
- #ifdef CONFIG_64BIT
- build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
- #else
-+# ifdef CONFIG_BCM47XX
-+ uasm_i_nop(&p);
-+# endif
- build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
- #endif
-
-@@ -1358,6 +1364,9 @@ static void build_r4000_tlb_refill_handl
- build_update_entries(&p, K0, K1);
- build_tlb_write_entry(&p, &l, &r, tlb_random);
- uasm_l_leave(&l, p);
-+#ifdef CONFIG_BCM47XX
-+ uasm_i_nop(&p);
-+#endif
- uasm_i_eret(&p); /* return from trap */
- }
- #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
-@@ -2059,6 +2068,9 @@ build_r4000_tlbchange_handler_head(u32 *
- #ifdef CONFIG_64BIT
- build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
- #else
-+# ifdef CONFIG_BCM47XX
-+ uasm_i_nop(p);
-+# endif
- build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
- #endif
-
-@@ -2105,6 +2117,9 @@ build_r4000_tlbchange_handler_tail(u32 *
- build_tlb_write_entry(p, l, r, tlb_indexed);
- uasm_l_leave(l, *p);
- build_restore_work_registers(p);
-+#ifdef CONFIG_BCM47XX
-+ uasm_i_nop(p);
-+#endif
- uasm_i_eret(p); /* return from trap */
-
- #ifdef CONFIG_64BIT
+++ /dev/null
-From: Jeff Hansen <jhansen@cardaccess-inc.com>
-Subject: [PATCH] kmap_coherent
-
-On ASUS WL-500gP there are some "Data bus error"s when executing simple
-commands liks "ps" or "cat /proc/1/cmdline".
-
-This fixes OpenWrt ticket #1485: https://dev.openwrt.org/ticket/1485
----
---- a/arch/mips/include/asm/cpu-features.h
-+++ b/arch/mips/include/asm/cpu-features.h
-@@ -257,6 +257,9 @@
- #ifndef cpu_has_pindexed_dcache
- #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
- #endif
-+#ifndef cpu_use_kmap_coherent
-+#define cpu_use_kmap_coherent 1
-+#endif
-
- /*
- * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
---- a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
-+++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
-@@ -80,4 +80,6 @@
- #define cpu_scache_line_size() 0
- #define cpu_has_vz 0
-
-+#define cpu_use_kmap_coherent 0
-+
- #endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
---- a/arch/mips/mm/c-r4k.c
-+++ b/arch/mips/mm/c-r4k.c
-@@ -702,7 +702,7 @@ static inline void local_r4k_flush_cache
- map_coherent = (cpu_has_dc_aliases &&
- page_mapcount(page) &&
- !Page_dcache_dirty(page));
-- if (map_coherent)
-+ if (map_coherent && cpu_use_kmap_coherent)
- vaddr = kmap_coherent(page, addr);
- else
- vaddr = kmap_atomic(page);
-@@ -729,7 +729,7 @@ static inline void local_r4k_flush_cache
- }
-
- if (vaddr) {
-- if (map_coherent)
-+ if (map_coherent && cpu_use_kmap_coherent)
- kunmap_coherent();
- else
- kunmap_atomic(vaddr);
---- a/arch/mips/mm/init.c
-+++ b/arch/mips/mm/init.c
-@@ -172,7 +172,7 @@ void copy_user_highpage(struct page *to,
- void *vfrom, *vto;
-
- vto = kmap_atomic(to);
-- if (cpu_has_dc_aliases &&
-+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- page_mapcount(from) && !Page_dcache_dirty(from)) {
- vfrom = kmap_coherent(from, vaddr);
- copy_page(vto, vfrom);
-@@ -194,7 +194,7 @@ void copy_to_user_page(struct vm_area_st
- struct page *page, unsigned long vaddr, void *dst, const void *src,
- unsigned long len)
- {
-- if (cpu_has_dc_aliases &&
-+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- page_mapcount(page) && !Page_dcache_dirty(page)) {
- void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
- memcpy(vto, src, len);
-@@ -212,7 +212,7 @@ void copy_from_user_page(struct vm_area_
- struct page *page, unsigned long vaddr, void *dst, const void *src,
- unsigned long len)
- {
-- if (cpu_has_dc_aliases &&
-+ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
- page_mapcount(page) && !Page_dcache_dirty(page)) {
- void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
- memcpy(dst, vfrom, len);
+++ /dev/null
-From b36f694256f41bc71571f467646d015dda128d14 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Sat, 9 Nov 2013 17:03:59 +0100
-Subject: [PATCH 210/210] b44: register adm switch
-
----
- drivers/net/ethernet/broadcom/b44.c | 57 +++++++++++++++++++++++++++++++++++
- drivers/net/ethernet/broadcom/b44.h | 3 ++
- 2 files changed, 60 insertions(+)
-
---- a/drivers/net/ethernet/broadcom/b44.c
-+++ b/drivers/net/ethernet/broadcom/b44.c
-@@ -31,6 +31,8 @@
- #include <linux/ssb/ssb.h>
- #include <linux/slab.h>
- #include <linux/phy.h>
-+#include <linux/platform_device.h>
-+#include <linux/platform_data/adm6996-gpio.h>
-
- #include <linux/uaccess.h>
- #include <asm/io.h>
-@@ -2247,6 +2249,69 @@ static void b44_adjust_link(struct net_d
- }
- }
-
-+#ifdef CONFIG_BCM47XX
-+static int b44_register_adm_switch(struct b44 *bp)
-+{
-+ int gpio;
-+ struct platform_device *pdev;
-+ struct adm6996_gpio_platform_data adm_data = {0};
-+ struct platform_device_info info = {0};
-+
-+ adm_data.model = ADM6996L;
-+ gpio = bcm47xx_nvram_gpio_pin("adm_eecs");
-+ if (gpio >= 0)
-+ adm_data.eecs = gpio;
-+ else
-+ adm_data.eecs = 2;
-+
-+ gpio = bcm47xx_nvram_gpio_pin("adm_eesk");
-+ if (gpio >= 0)
-+ adm_data.eesk = gpio;
-+ else
-+ adm_data.eesk = 3;
-+
-+ gpio = bcm47xx_nvram_gpio_pin("adm_eedi");
-+ if (gpio >= 0)
-+ adm_data.eedi = gpio;
-+ else
-+ adm_data.eedi = 4;
-+
-+ /*
-+ * We ignore the "adm_rc" GPIO here. The driver does not use it,
-+ * and it conflicts with the Reset button GPIO on the Linksys WRT54GSv1.
-+ */
-+
-+ info.parent = bp->sdev->dev;
-+ info.name = "adm6996_gpio";
-+ info.id = -1;
-+ info.data = &adm_data;
-+ info.size_data = sizeof(adm_data);
-+
-+ if (!bp->adm_switch) {
-+ pdev = platform_device_register_full(&info);
-+ if (IS_ERR(pdev))
-+ return PTR_ERR(pdev);
-+
-+ bp->adm_switch = pdev;
-+ }
-+ return 0;
-+}
-+static void b44_unregister_adm_switch(struct b44 *bp)
-+{
-+ if (bp->adm_switch)
-+ platform_device_unregister(bp->adm_switch);
-+}
-+#else
-+static int b44_register_adm_switch(struct b44 *bp)
-+{
-+ return 0;
-+}
-+static void b44_unregister_adm_switch(struct b44 *bp)
-+{
-+
-+}
-+#endif /* CONFIG_BCM47XX */
-+
- static int b44_register_phy_one(struct b44 *bp)
- {
- __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
-@@ -2283,6 +2348,9 @@ static int b44_register_phy_one(struct b
- if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&
- (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
-
-+ if (sprom->boardflags_lo & B44_BOARDFLAG_ADM)
-+ b44_register_adm_switch(bp);
-+
- dev_info(sdev->dev,
- "could not find PHY at %i, use fixed one\n",
- bp->phy_addr);
-@@ -2477,6 +2545,7 @@ static void b44_remove_one(struct ssb_de
- unregister_netdev(dev);
- if (bp->flags & B44_FLAG_EXTERNAL_PHY)
- b44_unregister_phy_one(bp);
-+ b44_unregister_adm_switch(bp);
- ssb_device_disable(sdev, 0);
- ssb_bus_may_powerdown(sdev->bus);
- netif_napi_del(&bp->napi);
---- a/drivers/net/ethernet/broadcom/b44.h
-+++ b/drivers/net/ethernet/broadcom/b44.h
-@@ -408,6 +408,9 @@ struct b44 {
- struct mii_bus *mii_bus;
- int old_link;
- struct mii_if_info mii_if;
-+
-+ /* platform device for associated switch */
-+ struct platform_device *adm_switch;
- };
-
- #endif /* _B44_H */
+++ /dev/null
---- a/drivers/net/ethernet/broadcom/b44.c
-+++ b/drivers/net/ethernet/broadcom/b44.c
-@@ -430,10 +430,34 @@ static void b44_wap54g10_workaround(stru
- error:
- pr_warn("PHY: cannot reset MII transceiver isolate bit\n");
- }
-+
-+static void b44_bcm47xx_workarounds(struct b44 *bp)
-+{
-+ char buf[20];
-+ struct ssb_device *sdev = bp->sdev;
-+
-+ /* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */
-+ if (sdev->bus->sprom.board_num == 100) {
-+ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
-+ } else {
-+ /* WL-HDD */
-+ if (bcm47xx_nvram_getenv("hardware_version", buf, sizeof(buf)) >= 0 &&
-+ !strncmp(buf, "WL300-", strlen("WL300-"))) {
-+ if (sdev->bus->sprom.et0phyaddr == 0 &&
-+ sdev->bus->sprom.et1phyaddr == 1)
-+ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
-+ }
-+ }
-+ return;
-+}
- #else
- static inline void b44_wap54g10_workaround(struct b44 *bp)
- {
- }
-+
-+static inline void b44_bcm47xx_workarounds(struct b44 *bp)
-+{
-+}
- #endif
-
- static int b44_setup_phy(struct b44 *bp)
-@@ -442,6 +466,7 @@ static int b44_setup_phy(struct b44 *bp)
- int err;
-
- b44_wap54g10_workaround(bp);
-+ b44_bcm47xx_workarounds(bp);
-
- if (bp->flags & B44_FLAG_EXTERNAL_PHY)
- return 0;
-@@ -2177,6 +2202,8 @@ static int b44_get_invariants(struct b44
- * valid PHY address. */
- bp->phy_addr &= 0x1F;
-
-+ b44_bcm47xx_workarounds(bp);
-+
- memcpy(bp->dev->dev_addr, addr, ETH_ALEN);
-
- if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
+++ /dev/null
-This prevents the options from being delete with make kernel_oldconfig.
----
- drivers/ssb/Kconfig | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/bcma/Kconfig
-+++ b/drivers/bcma/Kconfig
-@@ -36,6 +36,7 @@ config BCMA_HOST_PCI
- config BCMA_HOST_SOC
- bool "Support for BCMA in a SoC"
- depends on HAS_IOMEM
-+ select USB_HCD_BCMA if USB_EHCI_HCD || USB_OHCI_HCD
- help
- Host interface for a Broadcom AIX bus directly mapped into
- the memory. This only works with the Broadcom SoCs from the
---- a/drivers/ssb/Kconfig
-+++ b/drivers/ssb/Kconfig
-@@ -141,6 +141,7 @@ config SSB_SFLASH
- config SSB_EMBEDDED
- bool
- depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
-+ select USB_HCD_SSB if USB_EHCI_HCD || USB_OHCI_HCD
- default y
-
- config SSB_DRIVER_EXTIF
+++ /dev/null
-From: Wolfram Joost <dbox2@frokaschwei.de>
-Subject: [PATCH] fork_cacheflush
-
-On ASUS WL-500gP there are many unexpected "Segmentation fault"s that
-seem to be caused by a kernel. They can be avoided by:
-1) Disabling highpage
-2) Using flush_cache_mm in flush_cache_dup_mm
-
-For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035
----
---- a/arch/mips/include/asm/cacheflush.h
-+++ b/arch/mips/include/asm/cacheflush.h
-@@ -46,7 +46,7 @@
- extern void (*flush_cache_all)(void);
- extern void (*__flush_cache_all)(void);
- extern void (*flush_cache_mm)(struct mm_struct *mm);
--#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
-+#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
- extern void (*flush_cache_range)(struct vm_area_struct *vma,
- unsigned long start, unsigned long end);
- extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
+++ /dev/null
-From: Jeff Hansen <jhansen@cardaccess-inc.com>
-Subject: [PATCH] no highpage
-
-On ASUS WL-500gP there are many unexpected "Segmentation fault"s that
-seem to be caused by a kernel. They can be avoided by:
-1) Disabling highpage
-2) Using flush_cache_mm in flush_cache_dup_mm
-
-For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035
----
---- a/arch/mips/include/asm/page.h
-+++ b/arch/mips/include/asm/page.h
-@@ -71,6 +71,7 @@ static inline unsigned int page_size_ftl
- #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
-
- #include <linux/pfn.h>
-+#include <asm/cpu-features.h>
-
- extern void build_clear_page(void);
- extern void build_copy_page(void);
-@@ -110,11 +111,16 @@ static inline void clear_user_page(void
- flush_data_cache_page((unsigned long)addr);
- }
-
--struct vm_area_struct;
--extern void copy_user_highpage(struct page *to, struct page *from,
-- unsigned long vaddr, struct vm_area_struct *vma);
-+static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
-+ struct page *to)
-+{
-+ extern void (*flush_data_cache_page)(unsigned long addr);
-
--#define __HAVE_ARCH_COPY_USER_HIGHPAGE
-+ copy_page(vto, vfrom);
-+ if (!cpu_has_ic_fills_f_dc ||
-+ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
-+ flush_data_cache_page((unsigned long)vto);
-+}
-
- /*
- * These are used to make use of C type-checking..
---- a/arch/mips/mm/init.c
-+++ b/arch/mips/mm/init.c
-@@ -166,30 +166,6 @@ void kunmap_coherent(void)
- preempt_enable();
- }
-
--void copy_user_highpage(struct page *to, struct page *from,
-- unsigned long vaddr, struct vm_area_struct *vma)
--{
-- void *vfrom, *vto;
--
-- vto = kmap_atomic(to);
-- if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
-- page_mapcount(from) && !Page_dcache_dirty(from)) {
-- vfrom = kmap_coherent(from, vaddr);
-- copy_page(vto, vfrom);
-- kunmap_coherent();
-- } else {
-- vfrom = kmap_atomic(from);
-- copy_page(vto, vfrom);
-- kunmap_atomic(vfrom);
-- }
-- if ((!cpu_has_ic_fills_f_dc) ||
-- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
-- flush_data_cache_page((unsigned long)vto);
-- kunmap_atomic(vto);
-- /* Make sure this page is cleared on other CPU's too before using it */
-- smp_wmb();
--}
--
- void copy_to_user_page(struct vm_area_struct *vma,
- struct page *page, unsigned long vaddr, void *dst, const void *src,
- unsigned long len)
+++ /dev/null
---- a/drivers/mtd/parsers/bcm47xxpart.c
-+++ b/drivers/mtd/parsers/bcm47xxpart.c
-@@ -98,6 +98,7 @@ static int bcm47xxpart_parse(struct mtd_
- int trx_num = 0; /* Number of found TRX partitions */
- int possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, };
- int err;
-+ bool found_nvram = false;
-
- /*
- * Some really old flashes (like AT45DB*) had smaller erasesize-s, but
-@@ -279,12 +280,23 @@ static int bcm47xxpart_parse(struct mtd_
- if (buf[0] == NVRAM_HEADER) {
- bcm47xxpart_add_part(&parts[curr_part++], "nvram",
- master->size - blocksize, 0);
-+ found_nvram = true;
- break;
- }
- }
-
- kfree(buf);
-
-+ if (!found_nvram) {
-+ pr_err("can not find a nvram partition reserve last block\n");
-+ bcm47xxpart_add_part(&parts[curr_part++], "nvram_guess",
-+ master->size - blocksize * 2, MTD_WRITEABLE);
-+ for (i = 0; i < curr_part; i++) {
-+ if (parts[i].size + parts[i].offset == master->size)
-+ parts[i].offset -= blocksize * 2;
-+ }
-+ }
-+
- /*
- * Assume that partitions end at the beginning of the one they are
- * followed by.
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Sun, 7 Nov 2021 14:20:40 +0100
-Subject: [PATCH] net: bgmac: connect to PHY even if it is BGMAC_PHY_NOREGS
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Recent bgmac change was meant to just fix a race between "Generic PHY"
-and "bcm53xx" drivers after -EPROBE_DEFER. It modified bgmac to use
-phy_connect() only if there is a real PHY device connected.
-
-That change broke bgmac on bcm47xx. bcma_phy_connect() now registers a
-fixed PHY with the bgmac_phy_connect_direct(). That fails as another
-fixed PHY (also using address 0) is already registered - by bcm47xx arch
-code bcm47xx_register_bus_complete().
-
-This change brings origial behaviour. It connects Ethernet interface
-with pseudo-PHY (switch device) and adjusts Ethernet interface link to
-match connected switch.
-
-This fixes:
-[ 2.548098] bgmac_bcma bcma0:1: Failed to register fixed PHY device
-[ 2.554584] bgmac_bcma bcma0:1: Cannot connect to phy
-
-Fixes: b5375509184d ("net: bgmac: improve handling PHY")
-Link: https://lore.kernel.org/netdev/3639116e-9292-03ca-b9d9-d741118a4541@gmail.com/T/#u
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- drivers/net/ethernet/broadcom/bgmac-bcma.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/net/ethernet/broadcom/bgmac-bcma.c
-+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c
-@@ -94,7 +94,7 @@ static int bcma_phy_connect(struct bgmac
- return 0;
-
- /* Connect to the PHY */
-- if (bgmac->mii_bus && bgmac->phyaddr != BGMAC_PHY_NOREGS) {
-+ if (bgmac->mii_bus) {
- snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,
- bgmac->phyaddr);
- phy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link,
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Fri, 10 Jun 2022 13:10:47 +0200
-Subject: [PATCH] bgmac: reduce max frame size to support just MTU 1500
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-bgmac allocates new replacement buffer before handling each received
-frame. Allocating & DMA-preparing 9724 B each time consumes a lot of CPU
-time. Ideally bgmac should just respect currently set MTU but it isn't
-the case right now. For now just revert back to the old limited frame
-size.
-
-This change bumps NAT masquarade speed by ~95%.
-
-Ref: 8c7da63978f1 ("bgmac: configure MTU and add support for frames beyond 8192 byte size")
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- drivers/net/ethernet/broadcom/bgmac.h | 3 +--
- 1 file changed, 1 insertion(+), 2 deletions(-)
-
---- a/drivers/net/ethernet/broadcom/bgmac.h
-+++ b/drivers/net/ethernet/broadcom/bgmac.h
-@@ -328,8 +328,7 @@
- #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */
- #define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \
- BGMAC_RX_FRAME_OFFSET)
--/* Jumbo frame size with FCS */
--#define BGMAC_RX_MAX_FRAME_SIZE 9724
-+#define BGMAC_RX_MAX_FRAME_SIZE 1536
- #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE)
- #define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \
- SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
+++ /dev/null
-When the Ethernet controller is powered down and someone wants to
-access the mdio bus like the witch driver (b53) the system crashed if
-PCI_D3hot was set before. This patch deactivates this power sawing mode
-when a switch driver is in use.
-
---- a/drivers/net/ethernet/broadcom/tg3.c
-+++ b/drivers/net/ethernet/broadcom/tg3.c
-@@ -4268,7 +4268,8 @@ static int tg3_power_down_prepare(struct
- static void tg3_power_down(struct tg3 *tp)
- {
- pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
-- pci_set_power_state(tp->pdev, PCI_D3hot);
-+ if (!tg3_flag(tp, ROBOSWITCH))
-+ pci_set_power_state(tp->pdev, PCI_D3hot);
- }
-
- static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)
+++ /dev/null
-From 597715c61ae75a05ab3310a34ff3857a006f0f63 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
-Date: Thu, 20 Nov 2014 21:32:42 +0100
-Subject: [PATCH] bcma: add table of serial flashes with smaller blocks
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
----
- drivers/bcma/driver_chipcommon_sflash.c | 29 +++++++++++++++++++++++++++++
- 1 file changed, 29 insertions(+)
-
---- a/drivers/bcma/driver_chipcommon_sflash.c
-+++ b/drivers/bcma/driver_chipcommon_sflash.c
-@@ -9,6 +9,7 @@
-
- #include <linux/platform_device.h>
- #include <linux/bcma/bcma.h>
-+#include <bcm47xx_board.h>
-
- static struct resource bcma_sflash_resource = {
- .name = "bcma_sflash",
-@@ -42,6 +43,13 @@ static const struct bcma_sflash_tbl_e bc
- { NULL },
- };
-
-+/* Some devices use smaller blocks (and have more of them) */
-+static const struct bcma_sflash_tbl_e bcma_sflash_st_shrink_tbl[] = {
-+ { "M25P16", 0x14, 0x1000, 512, },
-+ { "M25P32", 0x15, 0x1000, 1024, },
-+ { NULL },
-+};
-+
- static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
- { "SST25WF512", 1, 0x1000, 16, },
- { "SST25VF512", 0x48, 0x1000, 16, },
-@@ -85,6 +93,24 @@ static void bcma_sflash_cmd(struct bcma_
- bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
- }
-
-+const struct bcma_sflash_tbl_e *bcma_sflash_shrink_flash(u32 id)
-+{
-+ enum bcm47xx_board board = bcm47xx_board_get();
-+ const struct bcma_sflash_tbl_e *e;
-+
-+ switch (board) {
-+ case BCM47XX_BOARD_NETGEAR_WGR614_V10:
-+ case BCM47XX_BOARD_NETGEAR_WNR1000_V3:
-+ for (e = bcma_sflash_st_shrink_tbl; e->name; e++) {
-+ if (e->id == id)
-+ return e;
-+ }
-+ return NULL;
-+ default:
-+ return NULL;
-+ }
-+}
-+
- /* Initialize serial flash access */
- int bcma_sflash_init(struct bcma_drv_cc *cc)
- {
-@@ -115,6 +141,10 @@ int bcma_sflash_init(struct bcma_drv_cc
- case 0x13:
- return -ENOTSUPP;
- default:
-+ e = bcma_sflash_shrink_flash(id);
-+ if (e)
-+ break;
-+
- for (e = bcma_sflash_st_tbl; e->name; e++) {
- if (e->id == id)
- break;
+++ /dev/null
-The Netgear wgt634u uses a different format for storing the
-configuration. This patch is needed to read out the correct
-configuration. The cfe_env.c file uses a different method way to read
-out the configuration than the in kernel cfe config reader.
-
---- a/drivers/firmware/broadcom/Makefile
-+++ b/drivers/firmware/broadcom/Makefile
-@@ -1,4 +1,4 @@
- # SPDX-License-Identifier: GPL-2.0-only
--obj-$(CONFIG_BCM47XX_NVRAM) += bcm47xx_nvram.o
-+obj-$(CONFIG_BCM47XX_NVRAM) += bcm47xx_nvram.o cfe_env.o
- obj-$(CONFIG_BCM47XX_SPROM) += bcm47xx_sprom.o
- obj-$(CONFIG_TEE_BNXT_FW) += tee_bnxt_fw.o
---- /dev/null
-+++ b/drivers/firmware/broadcom/cfe_env.c
-@@ -0,0 +1,228 @@
-+/*
-+ * CFE environment variable access
-+ *
-+ * Copyright 2001-2003, Broadcom Corporation
-+ * Copyright 2006, Felix Fietkau <nbd@nbd.name>
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License as published by the
-+ * Free Software Foundation; either version 2 of the License, or (at your
-+ * option) any later version.
-+ */
-+
-+#include <linux/init.h>
-+#include <linux/module.h>
-+#include <linux/kernel.h>
-+#include <linux/string.h>
-+#include <asm/io.h>
-+#include <linux/uaccess.h>
-+
-+#define NVRAM_SIZE (0x1ff0)
-+static char _nvdata[NVRAM_SIZE];
-+static char _valuestr[256];
-+
-+/*
-+ * TLV types. These codes are used in the "type-length-value"
-+ * encoding of the items stored in the NVRAM device (flash or EEPROM)
-+ *
-+ * The layout of the flash/nvram is as follows:
-+ *
-+ * <type> <length> <data ...> <type> <length> <data ...> <type_end>
-+ *
-+ * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
-+ * The "length" field marks the length of the data section, not
-+ * including the type and length fields.
-+ *
-+ * Environment variables are stored as follows:
-+ *
-+ * <type_env> <length> <flags> <name> = <value>
-+ *
-+ * If bit 0 (low bit) is set, the length is an 8-bit value.
-+ * If bit 0 (low bit) is clear, the length is a 16-bit value
-+ *
-+ * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
-+ * indicates the size of the length field.
-+ *
-+ * Flags are from the constants below:
-+ *
-+ */
-+#define ENV_LENGTH_16BITS 0x00 /* for low bit */
-+#define ENV_LENGTH_8BITS 0x01
-+
-+#define ENV_TYPE_USER 0x80
-+
-+#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
-+#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
-+
-+/*
-+ * The actual TLV types we support
-+ */
-+
-+#define ENV_TLV_TYPE_END 0x00
-+#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
-+
-+/*
-+ * Environment variable flags
-+ */
-+
-+#define ENV_FLG_NORMAL 0x00 /* normal read/write */
-+#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
-+#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
-+
-+#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
-+#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
-+
-+
-+/* *********************************************************************
-+ * _nvram_read(buffer,offset,length)
-+ *
-+ * Read data from the NVRAM device
-+ *
-+ * Input parameters:
-+ * buffer - destination buffer
-+ * offset - offset of data to read
-+ * length - number of bytes to read
-+ *
-+ * Return value:
-+ * number of bytes read, or <0 if error occured
-+ ********************************************************************* */
-+static int
-+_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
-+{
-+ int i;
-+ if (offset > NVRAM_SIZE)
-+ return -1;
-+
-+ for ( i = 0; i < length; i++) {
-+ buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
-+ }
-+ return length;
-+}
-+
-+
-+static char*
-+_strnchr(const char *dest,int c,size_t cnt)
-+{
-+ while (*dest && (cnt > 0)) {
-+ if (*dest == c) return (char *) dest;
-+ dest++;
-+ cnt--;
-+ }
-+ return NULL;
-+}
-+
-+
-+
-+/*
-+ * Core support API: Externally visible.
-+ */
-+
-+/*
-+ * Get the value of an NVRAM variable
-+ * @param name name of variable to get
-+ * @return value of variable or NULL if undefined
-+ */
-+
-+char *cfe_env_get(unsigned char *nv_buf, const char *name)
-+{
-+ int size;
-+ unsigned char *buffer;
-+ unsigned char *ptr;
-+ unsigned char *envval;
-+ unsigned int reclen;
-+ unsigned int rectype;
-+ int offset;
-+ int flg;
-+
-+ if (!strcmp(name, "nvram_type"))
-+ return "cfe";
-+
-+ size = NVRAM_SIZE;
-+ buffer = &_nvdata[0];
-+
-+ ptr = buffer;
-+ offset = 0;
-+
-+ /* Read the record type and length */
-+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
-+ goto error;
-+ }
-+
-+ while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
-+
-+ /* Adjust pointer for TLV type */
-+ rectype = *(ptr);
-+ offset++;
-+ size--;
-+
-+ /*
-+ * Read the length. It can be either 1 or 2 bytes
-+ * depending on the code
-+ */
-+ if (rectype & ENV_LENGTH_8BITS) {
-+ /* Read the record type and length - 8 bits */
-+ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
-+ goto error;
-+ }
-+ reclen = *(ptr);
-+ size--;
-+ offset++;
-+ }
-+ else {
-+ /* Read the record type and length - 16 bits, MSB first */
-+ if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
-+ goto error;
-+ }
-+ reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
-+ size -= 2;
-+ offset += 2;
-+ }
-+
-+ if (reclen > size)
-+ break; /* should not happen, bad NVRAM */
-+
-+ switch (rectype) {
-+ case ENV_TLV_TYPE_ENV:
-+ /* Read the TLV data */
-+ if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
-+ goto error;
-+ flg = *ptr++;
-+ envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
-+ if (envval) {
-+ *envval++ = '\0';
-+ memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
-+ _valuestr[(reclen-1)-(envval-ptr)] = '\0';
-+#if 0
-+ printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
-+#endif
-+ if(!strcmp(ptr, name)){
-+ return _valuestr;
-+ }
-+ if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
-+ return _valuestr;
-+ }
-+ break;
-+
-+ default:
-+ /* Unknown TLV type, skip it. */
-+ break;
-+ }
-+
-+ /*
-+ * Advance to next TLV
-+ */
-+
-+ size -= (int)reclen;
-+ offset += reclen;
-+
-+ /* Read the next record type */
-+ ptr = buffer;
-+ if (_nvram_read(nv_buf, ptr,offset,1) != 1)
-+ goto error;
-+ }
-+
-+error:
-+ return NULL;
-+
-+}
-+
---- a/drivers/firmware/broadcom/bcm47xx_nvram.c
-+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c
-@@ -33,6 +33,8 @@ struct nvram_header {
- static char nvram_buf[NVRAM_SPACE];
- static size_t nvram_len;
- static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000};
-+static int cfe_env;
-+extern char *cfe_env_get(char *nv_buf, const char *name);
-
- /**
- * bcm47xx_nvram_is_valid - check for a valid NVRAM at specified memory
-@@ -80,6 +82,26 @@ static int bcm47xx_nvram_find_and_copy(v
- return -EEXIST;
- }
-
-+ cfe_env = 0;
-+
-+ /* XXX: hack for supporting the CFE environment stuff on WGT634U */
-+ if (res_size >= 8 * 1024 * 1024) {
-+ u32 *src = (u32 *)(flash_start + 8 * 1024 * 1024 - 0x2000);
-+ u32 *dst = (u32 *)nvram_buf;
-+
-+ if ((*src & 0xff00ff) == 0x000001) {
-+ printk("early_nvram_init: WGT634U NVRAM found.\n");
-+
-+ for (i = 0; i < 0x1ff0; i++) {
-+ if (*src == 0xFFFFFFFF)
-+ break;
-+ *dst++ = *src++;
-+ }
-+ cfe_env = 1;
-+ return 0;
-+ }
-+ }
-+
- /* TODO: when nvram is on nand flash check for bad blocks first. */
-
- /* Try every possible flash size and check for NVRAM at its end */
-@@ -190,6 +212,13 @@ int bcm47xx_nvram_getenv(const char *nam
- if (!name)
- return -EINVAL;
-
-+ if (cfe_env) {
-+ value = cfe_env_get(nvram_buf, name);
-+ if (!value)
-+ return -ENOENT;
-+ return snprintf(val, val_len, "%s", value);
-+ }
-+
- if (!nvram_len) {
- err = nvram_init();
- if (err)
+++ /dev/null
---- a/arch/mips/bcm47xx/setup.c
-+++ b/arch/mips/bcm47xx/setup.c
-@@ -37,6 +37,7 @@
- #include <linux/ssb/ssb.h>
- #include <linux/ssb/ssb_embedded.h>
- #include <linux/bcma/bcma_soc.h>
-+#include <linux/old_gpio_wdt.h>
- #include <asm/bootinfo.h>
- #include <asm/idle.h>
- #include <asm/prom.h>
-@@ -254,6 +255,33 @@ static struct fixed_phy_status bcm47xx_f
- .duplex = DUPLEX_FULL,
- };
-
-+static struct gpio_wdt_platform_data gpio_wdt_data;
-+
-+static struct platform_device gpio_wdt_device = {
-+ .name = "gpio-wdt",
-+ .id = 0,
-+ .dev = {
-+ .platform_data = &gpio_wdt_data,
-+ },
-+};
-+
-+static int __init bcm47xx_register_gpio_watchdog(void)
-+{
-+ enum bcm47xx_board board = bcm47xx_board_get();
-+
-+ switch (board) {
-+ case BCM47XX_BOARD_HUAWEI_E970:
-+ pr_info("bcm47xx: detected Huawei E970 or similar, starting early gpio_wdt timer\n");
-+ gpio_wdt_data.gpio = 7;
-+ gpio_wdt_data.interval = HZ;
-+ gpio_wdt_data.first_interval = HZ / 5;
-+ return platform_device_register(&gpio_wdt_device);
-+ default:
-+ /* Nothing to do */
-+ return 0;
-+ }
-+}
-+
- static int __init bcm47xx_register_bus_complete(void)
- {
- switch (bcm47xx_bus_type) {
-@@ -275,6 +303,7 @@ static int __init bcm47xx_register_bus_c
- bcm47xx_workarounds();
-
- fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
-+ bcm47xx_register_gpio_watchdog();
- return 0;
- }
- device_initcall(bcm47xx_register_bus_complete);
---- a/arch/mips/configs/bcm47xx_defconfig
-+++ b/arch/mips/configs/bcm47xx_defconfig
-@@ -63,6 +63,7 @@ CONFIG_HW_RANDOM=y
- CONFIG_GPIO_SYSFS=y
- CONFIG_WATCHDOG=y
- CONFIG_BCM47XX_WDT=y
-+CONFIG_GPIO_WDT=y
- CONFIG_SSB_DRIVER_GIGE=y
- CONFIG_BCMA_DRIVER_GMAC_CMN=y
- CONFIG_USB=y
---- a/drivers/ssb/embedded.c
-+++ b/drivers/ssb/embedded.c
-@@ -34,11 +34,36 @@ int ssb_watchdog_timer_set(struct ssb_bu
- }
- EXPORT_SYMBOL(ssb_watchdog_timer_set);
-
-+#ifdef CONFIG_BCM47XX
-+#include <bcm47xx_board.h>
-+
-+static bool ssb_watchdog_supported(void)
-+{
-+ enum bcm47xx_board board = bcm47xx_board_get();
-+
-+ /* The Huawei E970 has a hardware watchdog using a GPIO */
-+ switch (board) {
-+ case BCM47XX_BOARD_HUAWEI_E970:
-+ return false;
-+ default:
-+ return true;
-+ }
-+}
-+#else
-+static bool ssb_watchdog_supported(void)
-+{
-+ return true;
-+}
-+#endif
-+
- int ssb_watchdog_register(struct ssb_bus *bus)
- {
- struct bcm47xx_wdt wdt = {};
- struct platform_device *pdev;
-
-+ if (!ssb_watchdog_supported())
-+ return 0;
-+
- if (ssb_chipco_available(&bus->chipco)) {
- wdt.driver_data = &bus->chipco;
- wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
+++ /dev/null
-This generic GPIO watchdog is used on Huawei E970 (bcm47xx)
-
-Signed-off-by: Mathias Adam <m.adam--openwrt@adamis.de>
-
---- a/drivers/watchdog/Kconfig
-+++ b/drivers/watchdog/Kconfig
-@@ -1664,6 +1664,15 @@ config WDT_MTX1
- Hardware driver for the MTX-1 boards. This is a watchdog timer that
- will reboot the machine after a 100 seconds timer expired.
-
-+config GPIO_WDT
-+ tristate "GPIO Hardware Watchdog"
-+ help
-+ Hardware driver for GPIO-controlled watchdogs. GPIO pin and
-+ toggle interval settings are platform-specific. The driver
-+ will stop toggling the GPIO (i.e. machine reboots) after a
-+ 100 second timer expired and no process has written to
-+ /dev/watchdog during that time.
-+
- config SIBYTE_WDOG
- tristate "Sibyte SoC hardware watchdog"
- depends on CPU_SB1
---- a/drivers/watchdog/Makefile
-+++ b/drivers/watchdog/Makefile
-@@ -159,6 +159,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt
- obj-$(CONFIG_INDYDOG) += indydog.o
- obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o
- obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
-+obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o
- obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
- obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
- obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
---- /dev/null
-+++ b/drivers/watchdog/old_gpio_wdt.c
-@@ -0,0 +1,301 @@
-+/*
-+ * Driver for GPIO-controlled Hardware Watchdogs.
-+ *
-+ * Copyright (C) 2013 Mathias Adam <m.adam--linux@adamis.de>
-+ *
-+ * Replaces mtx1_wdt (driver for the MTX-1 Watchdog):
-+ *
-+ * (C) Copyright 2005 4G Systems <info@4g-systems.biz>,
-+ * All Rights Reserved.
-+ * http://www.4g-systems.biz
-+ *
-+ * (C) Copyright 2007 OpenWrt.org, Florian Fainelli <florian@openwrt.org>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License
-+ * as published by the Free Software Foundation; either version
-+ * 2 of the License, or (at your option) any later version.
-+ *
-+ * Neither Michael Stickel nor 4G Systems admit liability nor provide
-+ * warranty for any of this software. This material is provided
-+ * "AS-IS" and at no charge.
-+ *
-+ * (c) Copyright 2005 4G Systems <info@4g-systems.biz>
-+ *
-+ * Release 0.01.
-+ * Author: Michael Stickel michael.stickel@4g-systems.biz
-+ *
-+ * Release 0.02.
-+ * Author: Florian Fainelli florian@openwrt.org
-+ * use the Linux watchdog/timer APIs
-+ *
-+ * Release 0.03.
-+ * Author: Mathias Adam <m.adam--linux@adamis.de>
-+ * make it a generic gpio watchdog driver
-+ *
-+ * The Watchdog is configured to reset the MTX-1
-+ * if it is not triggered for 100 seconds.
-+ * It should not be triggered more often than 1.6 seconds.
-+ *
-+ * A timer triggers the watchdog every 5 seconds, until
-+ * it is opened for the first time. After the first open
-+ * it MUST be triggered every 2..95 seconds.
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/moduleparam.h>
-+#include <linux/types.h>
-+#include <linux/errno.h>
-+#include <linux/miscdevice.h>
-+#include <linux/fs.h>
-+#include <linux/init.h>
-+#include <linux/ioport.h>
-+#include <linux/timer.h>
-+#include <linux/completion.h>
-+#include <linux/jiffies.h>
-+#include <linux/watchdog.h>
-+#include <linux/platform_device.h>
-+#include <linux/io.h>
-+#include <linux/uaccess.h>
-+#include <linux/gpio.h>
-+#include <linux/old_gpio_wdt.h>
-+
-+static int ticks = 100 * HZ;
-+
-+static struct {
-+ struct completion stop;
-+ spinlock_t lock;
-+ int running;
-+ struct timer_list timer;
-+ int queue;
-+ int default_ticks;
-+ unsigned long inuse;
-+ unsigned gpio;
-+ unsigned int gstate;
-+ int interval;
-+ int first_interval;
-+} gpio_wdt_device;
-+
-+static void gpio_wdt_trigger(struct timer_list *unused)
-+{
-+ spin_lock(&gpio_wdt_device.lock);
-+ if (gpio_wdt_device.running && ticks > 0)
-+ ticks -= gpio_wdt_device.interval;
-+
-+ /* toggle wdt gpio */
-+ gpio_wdt_device.gstate = !gpio_wdt_device.gstate;
-+ gpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate);
-+
-+ if (gpio_wdt_device.queue && ticks > 0)
-+ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval);
-+ else
-+ complete(&gpio_wdt_device.stop);
-+ spin_unlock(&gpio_wdt_device.lock);
-+}
-+
-+static void gpio_wdt_reset(void)
-+{
-+ ticks = gpio_wdt_device.default_ticks;
-+}
-+
-+
-+static void gpio_wdt_start(void)
-+{
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&gpio_wdt_device.lock, flags);
-+ if (!gpio_wdt_device.queue) {
-+ gpio_wdt_device.queue = 1;
-+ gpio_wdt_device.gstate = 1;
-+ gpio_set_value(gpio_wdt_device.gpio, 1);
-+ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval);
-+ }
-+ gpio_wdt_device.running++;
-+ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags);
-+}
-+
-+static int gpio_wdt_stop(void)
-+{
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&gpio_wdt_device.lock, flags);
-+ if (gpio_wdt_device.queue) {
-+ gpio_wdt_device.queue = 0;
-+ gpio_wdt_device.gstate = 0;
-+ gpio_set_value(gpio_wdt_device.gpio, 0);
-+ }
-+ ticks = gpio_wdt_device.default_ticks;
-+ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags);
-+ return 0;
-+}
-+
-+/* Filesystem functions */
-+
-+static int gpio_wdt_open(struct inode *inode, struct file *file)
-+{
-+ if (test_and_set_bit(0, &gpio_wdt_device.inuse))
-+ return -EBUSY;
-+ return nonseekable_open(inode, file);
-+}
-+
-+
-+static int gpio_wdt_release(struct inode *inode, struct file *file)
-+{
-+ clear_bit(0, &gpio_wdt_device.inuse);
-+ return 0;
-+}
-+
-+static long gpio_wdt_ioctl(struct file *file, unsigned int cmd,
-+ unsigned long arg)
-+{
-+ void __user *argp = (void __user *)arg;
-+ int __user *p = (int __user *)argp;
-+ unsigned int value;
-+ static const struct watchdog_info ident = {
-+ .options = WDIOF_CARDRESET,
-+ .identity = "GPIO WDT",
-+ };
-+
-+ switch (cmd) {
-+ case WDIOC_GETSUPPORT:
-+ if (copy_to_user(argp, &ident, sizeof(ident)))
-+ return -EFAULT;
-+ break;
-+ case WDIOC_GETSTATUS:
-+ case WDIOC_GETBOOTSTATUS:
-+ put_user(0, p);
-+ break;
-+ case WDIOC_SETOPTIONS:
-+ if (get_user(value, p))
-+ return -EFAULT;
-+ if (value & WDIOS_ENABLECARD)
-+ gpio_wdt_start();
-+ else if (value & WDIOS_DISABLECARD)
-+ gpio_wdt_stop();
-+ else
-+ return -EINVAL;
-+ return 0;
-+ case WDIOC_KEEPALIVE:
-+ gpio_wdt_reset();
-+ break;
-+ default:
-+ return -ENOTTY;
-+ }
-+ return 0;
-+}
-+
-+
-+static ssize_t gpio_wdt_write(struct file *file, const char *buf,
-+ size_t count, loff_t *ppos)
-+{
-+ if (!count)
-+ return -EIO;
-+ gpio_wdt_reset();
-+ return count;
-+}
-+
-+static const struct file_operations gpio_wdt_fops = {
-+ .owner = THIS_MODULE,
-+ .llseek = no_llseek,
-+ .unlocked_ioctl = gpio_wdt_ioctl,
-+ .open = gpio_wdt_open,
-+ .write = gpio_wdt_write,
-+ .release = gpio_wdt_release,
-+};
-+
-+
-+static struct miscdevice gpio_wdt_misc = {
-+ .minor = WATCHDOG_MINOR,
-+ .name = "watchdog",
-+ .fops = &gpio_wdt_fops,
-+};
-+
-+
-+static int gpio_wdt_probe(struct platform_device *pdev)
-+{
-+ int ret;
-+ struct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data;
-+
-+ gpio_wdt_device.gpio = gpio_wdt_data->gpio;
-+ gpio_wdt_device.interval = gpio_wdt_data->interval;
-+ gpio_wdt_device.first_interval = gpio_wdt_data->first_interval;
-+ if (gpio_wdt_device.first_interval <= 0) {
-+ gpio_wdt_device.first_interval = gpio_wdt_device.interval;
-+ }
-+
-+ ret = gpio_request(gpio_wdt_device.gpio, "gpio-wdt");
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "failed to request gpio");
-+ return ret;
-+ }
-+
-+ spin_lock_init(&gpio_wdt_device.lock);
-+ init_completion(&gpio_wdt_device.stop);
-+ gpio_wdt_device.queue = 0;
-+ clear_bit(0, &gpio_wdt_device.inuse);
-+ timer_setup(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L);
-+ gpio_wdt_device.default_ticks = ticks;
-+
-+ gpio_wdt_start();
-+ dev_info(&pdev->dev, "GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\n",
-+ gpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval);
-+ return 0;
-+}
-+
-+static int gpio_wdt_remove(struct platform_device *pdev)
-+{
-+ /* FIXME: do we need to lock this test ? */
-+ if (gpio_wdt_device.queue) {
-+ gpio_wdt_device.queue = 0;
-+ wait_for_completion(&gpio_wdt_device.stop);
-+ }
-+
-+ gpio_free(gpio_wdt_device.gpio);
-+ misc_deregister(&gpio_wdt_misc);
-+ return 0;
-+}
-+
-+static struct platform_driver gpio_wdt_driver = {
-+ .probe = gpio_wdt_probe,
-+ .remove = gpio_wdt_remove,
-+ .driver.name = "gpio-wdt",
-+ .driver.owner = THIS_MODULE,
-+};
-+
-+static int __init gpio_wdt_init(void)
-+{
-+ return platform_driver_register(&gpio_wdt_driver);
-+}
-+arch_initcall(gpio_wdt_init);
-+
-+/*
-+ * We do wdt initialization in two steps: arch_initcall probes the wdt
-+ * very early to start pinging the watchdog (misc devices are not yet
-+ * available), and later module_init() just registers the misc device.
-+ */
-+static int gpio_wdt_init_late(void)
-+{
-+ int ret;
-+
-+ ret = misc_register(&gpio_wdt_misc);
-+ if (ret < 0) {
-+ pr_err("GPIO_WDT: failed to register misc device\n");
-+ return ret;
-+ }
-+ return 0;
-+}
-+#ifndef MODULE
-+module_init(gpio_wdt_init_late);
-+#endif
-+
-+static void __exit gpio_wdt_exit(void)
-+{
-+ platform_driver_unregister(&gpio_wdt_driver);
-+}
-+module_exit(gpio_wdt_exit);
-+
-+MODULE_AUTHOR("Michael Stickel, Florian Fainelli, Mathias Adam");
-+MODULE_DESCRIPTION("Driver for GPIO hardware watchdogs");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-+MODULE_ALIAS("platform:gpio-wdt");
---- /dev/null
-+++ b/include/linux/old_gpio_wdt.h
-@@ -0,0 +1,21 @@
-+/*
-+ * Definitions for the GPIO watchdog driver
-+ *
-+ * Copyright (C) 2013 Mathias Adam <m.adam--linux@adamis.de>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ */
-+
-+#ifndef _GPIO_WDT_H_
-+#define _GPIO_WDT_H_
-+
-+struct gpio_wdt_platform_data {
-+ int gpio; /* GPIO line number */
-+ int interval; /* watchdog reset interval in system ticks */
-+ int first_interval; /* first wd reset interval in system ticks */
-+};
-+
-+#endif /* _GPIO_WDT_H_ */
+++ /dev/null
-From 5c81397a0147ea59c778d1de14ef54e2268221f6 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
-Date: Wed, 8 Apr 2015 06:58:11 +0200
-Subject: [PATCH] ssb: reject PCI writes setting CardBus bridge resources
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-If SoC has a CardBus we can set resources of device at slot 1 only. It's
-impossigle to set bridge resources as it simply overwrites device 1
-configuration and usually results in Data bus error-s.
-
-Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
----
- drivers/ssb/driver_pcicore.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -165,6 +165,10 @@ static int ssb_extpci_write_config(struc
- WARN_ON(!pc->hostmode);
- if (unlikely(len != 1 && len != 2 && len != 4))
- goto out;
-+ /* CardBus SoCs allow configuring dev 1 resources only */
-+ if (extpci_core->cardbusmode && dev != 1 &&
-+ off >= PCI_BASE_ADDRESS_0 && off <= PCI_BASE_ADDRESS_5)
-+ goto out;
- addr = get_cfgspace_addr(pc, bus, dev, func, off);
- if (unlikely(!addr))
- goto out;
+++ /dev/null
---- a/drivers/pcmcia/yenta_socket.c
-+++ b/drivers/pcmcia/yenta_socket.c
-@@ -923,6 +923,8 @@ static struct cardbus_type cardbus_type[
-
- static unsigned int yenta_probe_irq(struct yenta_socket *socket, u32 isa_irq_mask)
- {
-+/* WRT54G3G does not like this */
-+#ifndef CONFIG_BCM47XX
- int i;
- unsigned long val;
- u32 mask;
-@@ -951,6 +953,9 @@ static unsigned int yenta_probe_irq(stru
- mask = probe_irq_mask(val) & 0xffff;
-
- return mask;
-+#else
-+ return 0;
-+#endif
- }
-
-
-@@ -1031,6 +1036,10 @@ static void yenta_get_socket_capabilitie
- else
- socket->socket.irq_mask = 0;
-
-+ /* irq mask probing is broken for the WRT54G3G */
-+ if (socket->socket.irq_mask == 0)
-+ socket->socket.irq_mask = 0x6f8;
-+
- dev_info(&socket->dev->dev, "ISA IRQ mask 0x%04x, PCI irq %d\n",
- socket->socket.irq_mask, socket->cb_irq);
- }
-@@ -1262,6 +1271,15 @@ static int yenta_probe(struct pci_dev *d
- dev_info(&dev->dev, "Socket status: %08x\n",
- cb_readl(socket, CB_SOCKET_STATE));
-
-+ /* Generate an interrupt on card insert/remove */
-+ config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK);
-+
-+ /* Set up Multifunction Routing Status Register */
-+ config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */);
-+
-+ /* Switch interrupts to parallelized */
-+ config_writeb(socket, 0x92, 0x64);
-+
- yenta_fixup_parent_bridge(dev->subordinate);
-
- /* Register it with the pcmcia layer.. */
+++ /dev/null
---- a/drivers/ssb/driver_pcicore.c
-+++ b/drivers/ssb/driver_pcicore.c
-@@ -394,7 +394,7 @@ static void ssb_pcicore_init_hostmode(st
- /* Give some time to the PCI controller to configure itself with the new
- * values. Not waiting at this point causes crashes of the machine.
- */
-- mdelay(10);
-+ mdelay(300);
- register_pci_controller(&ssb_pcicore_controller);
- }
-
+++ /dev/null
---- a/drivers/firmware/broadcom/bcm47xx_nvram.c
-+++ b/drivers/firmware/broadcom/bcm47xx_nvram.c
-@@ -30,7 +30,8 @@ struct nvram_header {
- u32 config_ncdl; /* ncdl values for memc */
- };
-
--static char nvram_buf[NVRAM_SPACE];
-+char nvram_buf[NVRAM_SPACE];
-+EXPORT_SYMBOL(nvram_buf);
- static size_t nvram_len;
- static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000};
- static int cfe_env;
---- a/arch/mips/mm/cache.c
-+++ b/arch/mips/mm/cache.c
-@@ -63,6 +63,9 @@ void (*_dma_cache_wback_inv)(unsigned lo
- void (*_dma_cache_wback)(unsigned long start, unsigned long size);
- void (*_dma_cache_inv)(unsigned long start, unsigned long size);
-
-+EXPORT_SYMBOL(_dma_cache_wback_inv);
-+EXPORT_SYMBOL(_dma_cache_inv);
-+
- #endif /* CONFIG_DMA_NONCOHERENT */
-
- /*
--- /dev/null
+--- a/arch/mips/include/asm/r4kcache.h
++++ b/arch/mips/include/asm/r4kcache.h
+@@ -27,6 +27,38 @@
+ extern void (*r4k_blast_dcache)(void);
+ extern void (*r4k_blast_icache)(void);
+
++#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
++#include <asm/paccess.h>
++#include <linux/ssb/ssb.h>
++#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
++
++static inline unsigned long bcm4710_dummy_rreg(void)
++{
++ return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
++}
++
++#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
++
++static inline unsigned long bcm4710_fill_tlb(void *addr)
++{
++ return *(unsigned long *)addr;
++}
++
++#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
++
++static inline void bcm4710_protected_fill_tlb(void *addr)
++{
++ unsigned long x;
++ get_dbe(x, (unsigned long *)addr);;
++}
++
++#else
++#define BCM4710_DUMMY_RREG()
++
++#define BCM4710_FILL_TLB(addr)
++#define BCM4710_PROTECTED_FILL_TLB(addr)
++#endif
++
+ /*
+ * This macro return a properly sign-extended address suitable as base address
+ * for indexed cache operations. Two issues here:
+@@ -60,6 +92,7 @@ static inline void flush_icache_line_ind
+
+ static inline void flush_dcache_line_indexed(unsigned long addr)
+ {
++ BCM4710_DUMMY_RREG();
+ cache_op(Index_Writeback_Inv_D, addr);
+ }
+
+@@ -83,11 +116,13 @@ static inline void flush_icache_line(uns
+
+ static inline void flush_dcache_line(unsigned long addr)
+ {
++ BCM4710_DUMMY_RREG();
+ cache_op(Hit_Writeback_Inv_D, addr);
+ }
+
+ static inline void invalidate_dcache_line(unsigned long addr)
+ {
++ BCM4710_DUMMY_RREG();
+ cache_op(Hit_Invalidate_D, addr);
+ }
+
+@@ -160,6 +195,7 @@ static inline int protected_flush_icache
+ return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
+
+ default:
++ BCM4710_DUMMY_RREG();
+ return protected_cache_op(Hit_Invalidate_I, addr);
+ }
+ }
+@@ -172,6 +208,7 @@ static inline int protected_flush_icache
+ */
+ static inline int protected_writeback_dcache_line(unsigned long addr)
+ {
++ BCM4710_DUMMY_RREG();
+ return protected_cache_op(Hit_Writeback_Inv_D, addr);
+ }
+
+@@ -193,8 +230,51 @@ static inline void invalidate_tcache_pag
+ unroll(times, _cache_op, insn, op, (addr) + (i++ * (lsize))); \
+ } while (0)
+
++static inline void blast_dcache(void)
++{
++ unsigned long start = KSEG0;
++ unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
++ unsigned long end = (start + dcache_size);
++
++ do {
++ BCM4710_DUMMY_RREG();
++ cache_op(Index_Writeback_Inv_D, start);
++ start += current_cpu_data.dcache.linesz;
++ } while(start < end);
++}
++
++static inline void blast_dcache_page(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = start + PAGE_SIZE;
++
++ BCM4710_FILL_TLB(start);
++ do {
++ BCM4710_DUMMY_RREG();
++ cache_op(Hit_Writeback_Inv_D, start);
++ start += current_cpu_data.dcache.linesz;
++ } while(start < end);
++}
++
++static inline void blast_dcache_page_indexed(unsigned long page)
++{
++ unsigned long start = page;
++ unsigned long end = start + PAGE_SIZE;
++ unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
++ unsigned long ws_end = current_cpu_data.dcache.ways <<
++ current_cpu_data.dcache.waybit;
++ unsigned long ws, addr;
++ for (ws = 0; ws < ws_end; ws += ws_inc) {
++ start = page + ws;
++ for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
++ BCM4710_DUMMY_RREG();
++ cache_op(Index_Writeback_Inv_D, addr);
++ }
++ }
++}
++
+ /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
+-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
++#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
+ static inline void extra##blast_##pfx##cache##lsize(void) \
+ { \
+ unsigned long start = INDEX_BASE; \
+@@ -204,6 +284,7 @@ static inline void extra##blast_##pfx##c
+ current_cpu_data.desc.waybit; \
+ unsigned long ws, addr; \
+ \
++ war \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+ for (addr = start; addr < end; addr += lsize * 32) \
+ cache_unroll(32, kernel_cache, indexop, \
+@@ -215,6 +296,7 @@ static inline void extra##blast_##pfx##c
+ unsigned long start = page; \
+ unsigned long end = page + PAGE_SIZE; \
+ \
++ war \
+ do { \
+ cache_unroll(32, kernel_cache, hitop, start, lsize); \
+ start += lsize * 32; \
+@@ -231,32 +313,33 @@ static inline void extra##blast_##pfx##c
+ current_cpu_data.desc.waybit; \
+ unsigned long ws, addr; \
+ \
++ war \
+ for (ws = 0; ws < ws_end; ws += ws_inc) \
+ for (addr = start; addr < end; addr += lsize * 32) \
+ cache_unroll(32, kernel_cache, indexop, \
+ addr | ws, lsize); \
+ }
+
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
+-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
+-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
+-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
+-
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
+-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
+-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
++__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
++__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
++__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
++
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
++__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
++__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
+
+ #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
+ static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
+@@ -281,65 +364,36 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
+ __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
+
+ /* build blast_xxx_range, protected_blast_xxx_range */
+-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
++#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2) \
+ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
+ unsigned long end) \
+ { \
+ unsigned long lsize = cpu_##desc##_line_size(); \
+- unsigned long lsize_2 = lsize * 2; \
+- unsigned long lsize_3 = lsize * 3; \
+- unsigned long lsize_4 = lsize * 4; \
+- unsigned long lsize_5 = lsize * 5; \
+- unsigned long lsize_6 = lsize * 6; \
+- unsigned long lsize_7 = lsize * 7; \
+- unsigned long lsize_8 = lsize * 8; \
+ unsigned long addr = start & ~(lsize - 1); \
+- unsigned long aend = (end + lsize - 1) & ~(lsize - 1); \
+- int lines = (aend - addr) / lsize; \
+- \
+- while (lines >= 8) { \
+- prot##cache_op(hitop, addr); \
+- prot##cache_op(hitop, addr + lsize); \
+- prot##cache_op(hitop, addr + lsize_2); \
+- prot##cache_op(hitop, addr + lsize_3); \
+- prot##cache_op(hitop, addr + lsize_4); \
+- prot##cache_op(hitop, addr + lsize_5); \
+- prot##cache_op(hitop, addr + lsize_6); \
+- prot##cache_op(hitop, addr + lsize_7); \
+- addr += lsize_8; \
+- lines -= 8; \
+- } \
++ unsigned long aend = (end - 1) & ~(lsize - 1); \
+ \
+- if (lines & 0x4) { \
+- prot##cache_op(hitop, addr); \
+- prot##cache_op(hitop, addr + lsize); \
+- prot##cache_op(hitop, addr + lsize_2); \
+- prot##cache_op(hitop, addr + lsize_3); \
+- addr += lsize_4; \
+- } \
+- \
+- if (lines & 0x2) { \
+- prot##cache_op(hitop, addr); \
+- prot##cache_op(hitop, addr + lsize); \
+- addr += lsize_2; \
+- } \
++ war \
+ \
+- if (lines & 0x1) { \
++ while (1) { \
++ war2 \
+ prot##cache_op(hitop, addr); \
++ if (addr == aend) \
++ break; \
++ addr += lsize; \
+ } \
+ }
+
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
+-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
+ __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
+- protected_, loongson2_)
+-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
+-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
+-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
++ protected_, loongson2_, , )
++__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )
++__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
+ /* blast_inv_dcache_range */
+-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
+-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
++__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
++__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
+
+ /* Currently, this is very specific to Loongson-3 */
+ #define __BUILD_BLAST_CACHE_NODE(pfx, desc, indexop, hitop, lsize) \
+--- a/arch/mips/include/asm/stackframe.h
++++ b/arch/mips/include/asm/stackframe.h
+@@ -429,6 +429,10 @@
+ #else
+ .set push
+ .set arch=r4000
++#ifdef CONFIG_BCM47XX
++ nop
++ nop
++#endif
+ eret
+ .set pop
+ #endif
+--- a/arch/mips/kernel/genex.S
++++ b/arch/mips/kernel/genex.S
+@@ -21,6 +21,19 @@
+ #include <asm/sync.h>
+ #include <asm/thread_info.h>
+
++#ifdef CONFIG_BCM47XX
++# ifdef eret
++# undef eret
++# endif
++# define eret \
++ .set push; \
++ .set noreorder; \
++ nop; \
++ nop; \
++ eret; \
++ .set pop;
++#endif
++
+ __INIT
+
+ /*
+@@ -32,6 +45,9 @@
+ NESTED(except_vec3_generic, 0, sp)
+ .set push
+ .set noat
++#ifdef CONFIG_BCM47XX
++ nop
++#endif
+ mfc0 k1, CP0_CAUSE
+ andi k1, k1, 0x7c
+ #ifdef CONFIG_64BIT
+@@ -52,6 +68,9 @@ NESTED(except_vec3_r4000, 0, sp)
+ .set push
+ .set arch=r4000
+ .set noat
++#ifdef CONFIG_BCM47XX
++ nop
++#endif
+ mfc0 k1, CP0_CAUSE
+ li k0, 31<<2
+ andi k1, k1, 0x7c
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -37,6 +37,9 @@
+ #include <asm/traps.h>
+ #include <asm/mips-cps.h>
+
++/* For enabling BCM4710 cache workarounds */
++static int bcm4710 = 0;
++
+ /*
+ * Bits describing what cache ops an SMP callback function may perform.
+ *
+@@ -144,6 +147,9 @@ static void r4k_blast_dcache_page_setup(
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache_page = blast_dcache_page;
++ else
+ switch (dc_lsize) {
+ case 0:
+ r4k_blast_dcache_page = (void *)cache_noop;
+@@ -175,6 +181,9 @@ static void r4k_blast_dcache_user_page_s
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache_user_page = blast_dcache_user_page;
++ else
+ if (dc_lsize == 0)
+ r4k_blast_dcache_user_page = (void *)cache_noop;
+ else if (dc_lsize == 16)
+@@ -194,6 +203,9 @@ static void r4k_blast_dcache_setup(void)
+ {
+ unsigned long dc_lsize = cpu_dcache_line_size();
+
++ if (bcm4710)
++ r4k_blast_dcache = blast_dcache;
++ else
+ if (dc_lsize == 0)
+ r4k_blast_dcache = (void *)cache_noop;
+ else if (dc_lsize == 16)
+@@ -1669,6 +1681,17 @@ static void coherency_setup(void)
+ * silly idea of putting something else there ...
+ */
+ switch (current_cpu_type()) {
++ case CPU_BMIPS3300:
++ {
++ u32 cm;
++ cm = read_c0_diag();
++ /* Enable icache */
++ cm |= (1 << 31);
++ /* Enable dcache */
++ cm |= (1 << 30);
++ write_c0_diag(cm);
++ }
++ break;
+ case CPU_R4000PC:
+ case CPU_R4000SC:
+ case CPU_R4000MC:
+@@ -1715,6 +1738,15 @@ void r4k_cache_init(void)
+ extern void build_copy_page(void);
+ struct cpuinfo_mips *c = ¤t_cpu_data;
+
++ /* Check if special workarounds are required */
++#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
++ if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
++ printk("Enabling BCM4710A0 cache workarounds.\n");
++ bcm4710 = 1;
++ } else
++#endif
++ bcm4710 = 0;
++
+ probe_pcache();
+ probe_vcache();
+ setup_scache();
+@@ -1777,7 +1809,15 @@ void r4k_cache_init(void)
+ */
+ local_r4k___flush_cache_all(NULL);
+
++#ifdef CONFIG_BCM47XX
++ {
++ static void (*_coherency_setup)(void);
++ _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
++ _coherency_setup();
++ }
++#else
+ coherency_setup();
++#endif
+ board_cache_error_setup = r4k_cache_error_setup;
+
+ /*
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -958,6 +958,9 @@ void build_get_pgde32(u32 **p, unsigned
+ uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
+ uasm_i_addu(p, ptr, tmp, ptr);
+ #else
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++#endif
+ UASM_i_LA_mostly(p, ptr, pgdc);
+ #endif
+ uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
+@@ -1304,6 +1307,9 @@ static void build_r4000_tlb_refill_handl
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
+ #else
++# ifdef CONFIG_BCM47XX
++ uasm_i_nop(&p);
++# endif
+ build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
+ #endif
+
+@@ -1315,6 +1321,9 @@ static void build_r4000_tlb_refill_handl
+ build_update_entries(&p, K0, K1);
+ build_tlb_write_entry(&p, &l, &r, tlb_random);
+ uasm_l_leave(&l, p);
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(&p);
++#endif
+ uasm_i_eret(&p); /* return from trap */
+ }
+ #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
+@@ -2016,6 +2025,9 @@ build_r4000_tlbchange_handler_head(u32 *
+ #ifdef CONFIG_64BIT
+ build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
+ #else
++# ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++# endif
+ build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
+ #endif
+
+@@ -2062,6 +2074,9 @@ build_r4000_tlbchange_handler_tail(u32 *
+ build_tlb_write_entry(p, l, r, tlb_indexed);
+ uasm_l_leave(l, *p);
+ build_restore_work_registers(p);
++#ifdef CONFIG_BCM47XX
++ uasm_i_nop(p);
++#endif
+ uasm_i_eret(p); /* return from trap */
+
+ #ifdef CONFIG_64BIT
--- /dev/null
+From: Jeff Hansen <jhansen@cardaccess-inc.com>
+Subject: [PATCH] kmap_coherent
+
+On ASUS WL-500gP there are some "Data bus error"s when executing simple
+commands liks "ps" or "cat /proc/1/cmdline".
+
+This fixes OpenWrt ticket #1485: https://dev.openwrt.org/ticket/1485
+---
+--- a/arch/mips/include/asm/cpu-features.h
++++ b/arch/mips/include/asm/cpu-features.h
+@@ -257,6 +257,9 @@
+ #ifndef cpu_has_pindexed_dcache
+ #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
+ #endif
++#ifndef cpu_use_kmap_coherent
++#define cpu_use_kmap_coherent 1
++#endif
+
+ /*
+ * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors
+--- a/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
++++ b/arch/mips/include/asm/mach-bcm47xx/cpu-feature-overrides.h
+@@ -79,4 +79,6 @@
+ #define cpu_scache_line_size() 0
+ #define cpu_has_vz 0
+
++#define cpu_use_kmap_coherent 0
++
+ #endif /* __ASM_MACH_BCM47XX_CPU_FEATURE_OVERRIDES_H */
+--- a/arch/mips/mm/c-r4k.c
++++ b/arch/mips/mm/c-r4k.c
+@@ -618,7 +618,7 @@ static inline void local_r4k_flush_cache
+ }
+
+ if (vaddr) {
+- if (map_coherent)
++ if (map_coherent && cpu_use_kmap_coherent)
+ kunmap_coherent();
+ else
+ kunmap_atomic(vaddr);
+--- a/arch/mips/mm/init.c
++++ b/arch/mips/mm/init.c
+@@ -173,7 +173,7 @@ void copy_user_highpage(struct page *to,
+ void *vfrom, *vto;
+
+ vto = kmap_atomic(to);
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ folio_mapped(src) && !folio_test_dcache_dirty(src)) {
+ vfrom = kmap_coherent(from, vaddr);
+ copy_page(vto, vfrom);
+@@ -197,7 +197,7 @@ void copy_to_user_page(struct vm_area_st
+ {
+ struct folio *folio = page_folio(page);
+
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ folio_mapped(folio) && !folio_test_dcache_dirty(folio)) {
+ void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ memcpy(vto, src, len);
+@@ -217,7 +217,7 @@ void copy_from_user_page(struct vm_area_
+ {
+ struct folio *folio = page_folio(page);
+
+- if (cpu_has_dc_aliases &&
++ if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+ folio_mapped(folio) && !folio_test_dcache_dirty(folio)) {
+ void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+ memcpy(dst, vfrom, len);
--- /dev/null
+From b36f694256f41bc71571f467646d015dda128d14 Mon Sep 17 00:00:00 2001
+From: Hauke Mehrtens <hauke@hauke-m.de>
+Date: Sat, 9 Nov 2013 17:03:59 +0100
+Subject: [PATCH 210/210] b44: register adm switch
+
+---
+ drivers/net/ethernet/broadcom/b44.c | 57 +++++++++++++++++++++++++++++++++++
+ drivers/net/ethernet/broadcom/b44.h | 3 ++
+ 2 files changed, 60 insertions(+)
+
+--- a/drivers/net/ethernet/broadcom/b44.c
++++ b/drivers/net/ethernet/broadcom/b44.c
+@@ -31,6 +31,8 @@
+ #include <linux/ssb/ssb.h>
+ #include <linux/slab.h>
+ #include <linux/phy.h>
++#include <linux/platform_device.h>
++#include <linux/platform_data/adm6996-gpio.h>
+
+ #include <linux/uaccess.h>
+ #include <asm/io.h>
+@@ -2227,6 +2229,69 @@ static void b44_adjust_link(struct net_d
+ }
+ }
+
++#ifdef CONFIG_BCM47XX
++static int b44_register_adm_switch(struct b44 *bp)
++{
++ int gpio;
++ struct platform_device *pdev;
++ struct adm6996_gpio_platform_data adm_data = {0};
++ struct platform_device_info info = {0};
++
++ adm_data.model = ADM6996L;
++ gpio = bcm47xx_nvram_gpio_pin("adm_eecs");
++ if (gpio >= 0)
++ adm_data.eecs = gpio;
++ else
++ adm_data.eecs = 2;
++
++ gpio = bcm47xx_nvram_gpio_pin("adm_eesk");
++ if (gpio >= 0)
++ adm_data.eesk = gpio;
++ else
++ adm_data.eesk = 3;
++
++ gpio = bcm47xx_nvram_gpio_pin("adm_eedi");
++ if (gpio >= 0)
++ adm_data.eedi = gpio;
++ else
++ adm_data.eedi = 4;
++
++ /*
++ * We ignore the "adm_rc" GPIO here. The driver does not use it,
++ * and it conflicts with the Reset button GPIO on the Linksys WRT54GSv1.
++ */
++
++ info.parent = bp->sdev->dev;
++ info.name = "adm6996_gpio";
++ info.id = -1;
++ info.data = &adm_data;
++ info.size_data = sizeof(adm_data);
++
++ if (!bp->adm_switch) {
++ pdev = platform_device_register_full(&info);
++ if (IS_ERR(pdev))
++ return PTR_ERR(pdev);
++
++ bp->adm_switch = pdev;
++ }
++ return 0;
++}
++static void b44_unregister_adm_switch(struct b44 *bp)
++{
++ if (bp->adm_switch)
++ platform_device_unregister(bp->adm_switch);
++}
++#else
++static int b44_register_adm_switch(struct b44 *bp)
++{
++ return 0;
++}
++static void b44_unregister_adm_switch(struct b44 *bp)
++{
++
++}
++#endif /* CONFIG_BCM47XX */
++
+ static int b44_register_phy_one(struct b44 *bp)
+ {
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+@@ -2263,6 +2328,9 @@ static int b44_register_phy_one(struct b
+ if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&
+ (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
+
++ if (sprom->boardflags_lo & B44_BOARDFLAG_ADM)
++ b44_register_adm_switch(bp);
++
+ dev_info(sdev->dev,
+ "could not find PHY at %i, use fixed one\n",
+ bp->phy_addr);
+@@ -2457,6 +2525,7 @@ static void b44_remove_one(struct ssb_de
+ unregister_netdev(dev);
+ if (bp->flags & B44_FLAG_EXTERNAL_PHY)
+ b44_unregister_phy_one(bp);
++ b44_unregister_adm_switch(bp);
+ ssb_device_disable(sdev, 0);
+ ssb_bus_may_powerdown(sdev->bus);
+ netif_napi_del(&bp->napi);
+--- a/drivers/net/ethernet/broadcom/b44.h
++++ b/drivers/net/ethernet/broadcom/b44.h
+@@ -408,6 +408,9 @@ struct b44 {
+ struct mii_bus *mii_bus;
+ int old_link;
+ struct mii_if_info mii_if;
++
++ /* platform device for associated switch */
++ struct platform_device *adm_switch;
+ };
+
+ #endif /* _B44_H */
--- /dev/null
+--- a/drivers/net/ethernet/broadcom/b44.c
++++ b/drivers/net/ethernet/broadcom/b44.c
+@@ -408,10 +408,34 @@ static void b44_wap54g10_workaround(stru
+ error:
+ pr_warn("PHY: cannot reset MII transceiver isolate bit\n");
+ }
++
++static void b44_bcm47xx_workarounds(struct b44 *bp)
++{
++ char buf[20];
++ struct ssb_device *sdev = bp->sdev;
++
++ /* Toshiba WRC-1000, Siemens SE505 v1, Askey RT-210W, RT-220W */
++ if (sdev->bus->sprom.board_num == 100) {
++ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
++ } else {
++ /* WL-HDD */
++ if (bcm47xx_nvram_getenv("hardware_version", buf, sizeof(buf)) >= 0 &&
++ !strncmp(buf, "WL300-", strlen("WL300-"))) {
++ if (sdev->bus->sprom.et0phyaddr == 0 &&
++ sdev->bus->sprom.et1phyaddr == 1)
++ bp->phy_addr = B44_PHY_ADDR_NO_LOCAL_PHY;
++ }
++ }
++ return;
++}
+ #else
+ static inline void b44_wap54g10_workaround(struct b44 *bp)
+ {
+ }
++
++static inline void b44_bcm47xx_workarounds(struct b44 *bp)
++{
++}
+ #endif
+
+ static int b44_setup_phy(struct b44 *bp)
+@@ -420,6 +444,7 @@ static int b44_setup_phy(struct b44 *bp)
+ int err;
+
+ b44_wap54g10_workaround(bp);
++ b44_bcm47xx_workarounds(bp);
+
+ if (bp->flags & B44_FLAG_EXTERNAL_PHY)
+ return 0;
+@@ -2157,6 +2182,8 @@ static int b44_get_invariants(struct b44
+ * valid PHY address. */
+ bp->phy_addr &= 0x1F;
+
++ b44_bcm47xx_workarounds(bp);
++
+ eth_hw_addr_set(bp->dev, addr);
+
+ if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
--- /dev/null
+This prevents the options from being delete with make kernel_oldconfig.
+---
+ drivers/ssb/Kconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/bcma/Kconfig
++++ b/drivers/bcma/Kconfig
+@@ -36,6 +36,7 @@ config BCMA_HOST_PCI
+ config BCMA_HOST_SOC
+ bool "Support for BCMA in a SoC"
+ depends on HAS_IOMEM
++ select USB_HCD_BCMA if USB_EHCI_HCD || USB_OHCI_HCD
+ help
+ Host interface for a Broadcom AIX bus directly mapped into
+ the memory. This only works with the Broadcom SoCs from the
+--- a/drivers/ssb/Kconfig
++++ b/drivers/ssb/Kconfig
+@@ -141,6 +141,7 @@ config SSB_SFLASH
+ config SSB_EMBEDDED
+ bool
+ depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
++ select USB_HCD_SSB if USB_EHCI_HCD || USB_OHCI_HCD
+ default y
+
+ config SSB_DRIVER_EXTIF
--- /dev/null
+From: Wolfram Joost <dbox2@frokaschwei.de>
+Subject: [PATCH] fork_cacheflush
+
+On ASUS WL-500gP there are many unexpected "Segmentation fault"s that
+seem to be caused by a kernel. They can be avoided by:
+1) Disabling highpage
+2) Using flush_cache_mm in flush_cache_dup_mm
+
+For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035
+---
+--- a/arch/mips/include/asm/cacheflush.h
++++ b/arch/mips/include/asm/cacheflush.h
+@@ -46,7 +46,7 @@
+ extern void (*flush_cache_all)(void);
+ extern void (*__flush_cache_all)(void);
+ extern void (*flush_cache_mm)(struct mm_struct *mm);
+-#define flush_cache_dup_mm(mm) do { (void) (mm); } while (0)
++#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
+ extern void (*flush_cache_range)(struct vm_area_struct *vma,
+ unsigned long start, unsigned long end);
+ extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
--- /dev/null
+From: Jeff Hansen <jhansen@cardaccess-inc.com>
+Subject: [PATCH] no highpage
+
+On ASUS WL-500gP there are many unexpected "Segmentation fault"s that
+seem to be caused by a kernel. They can be avoided by:
+1) Disabling highpage
+2) Using flush_cache_mm in flush_cache_dup_mm
+
+For details see OpenWrt ticket #2035 https://dev.openwrt.org/ticket/2035
+---
+--- a/arch/mips/include/asm/page.h
++++ b/arch/mips/include/asm/page.h
+@@ -71,6 +71,7 @@ static inline unsigned int page_size_ftl
+ #endif /* CONFIG_MIPS_HUGE_TLB_SUPPORT */
+
+ #include <linux/pfn.h>
++#include <asm/cpu-features.h>
+
+ extern void build_clear_page(void);
+ extern void build_copy_page(void);
+@@ -110,11 +111,16 @@ static inline void clear_user_page(void
+ flush_data_cache_page((unsigned long)addr);
+ }
+
+-struct vm_area_struct;
+-extern void copy_user_highpage(struct page *to, struct page *from,
+- unsigned long vaddr, struct vm_area_struct *vma);
++static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
++ struct page *to)
++{
++ extern void (*flush_data_cache_page)(unsigned long addr);
+
+-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
++ copy_page(vto, vfrom);
++ if (!cpu_has_ic_fills_f_dc ||
++ pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
++ flush_data_cache_page((unsigned long)vto);
++}
+
+ /*
+ * These are used to make use of C type-checking..
+--- a/arch/mips/mm/init.c
++++ b/arch/mips/mm/init.c
+@@ -166,31 +166,6 @@ void kunmap_coherent(void)
+ preempt_enable();
+ }
+
+-void copy_user_highpage(struct page *to, struct page *from,
+- unsigned long vaddr, struct vm_area_struct *vma)
+-{
+- struct folio *src = page_folio(from);
+- void *vfrom, *vto;
+-
+- vto = kmap_atomic(to);
+- if (cpu_has_dc_aliases && cpu_use_kmap_coherent &&
+- folio_mapped(src) && !folio_test_dcache_dirty(src)) {
+- vfrom = kmap_coherent(from, vaddr);
+- copy_page(vto, vfrom);
+- kunmap_coherent();
+- } else {
+- vfrom = kmap_atomic(from);
+- copy_page(vto, vfrom);
+- kunmap_atomic(vfrom);
+- }
+- if ((!cpu_has_ic_fills_f_dc) ||
+- pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
+- flush_data_cache_page((unsigned long)vto);
+- kunmap_atomic(vto);
+- /* Make sure this page is cleared on other CPU's too before using it */
+- smp_wmb();
+-}
+-
+ void copy_to_user_page(struct vm_area_struct *vma,
+ struct page *page, unsigned long vaddr, void *dst, const void *src,
+ unsigned long len)
--- /dev/null
+--- a/drivers/mtd/parsers/bcm47xxpart.c
++++ b/drivers/mtd/parsers/bcm47xxpart.c
+@@ -98,6 +98,7 @@ static int bcm47xxpart_parse(struct mtd_
+ int trx_num = 0; /* Number of found TRX partitions */
+ int possible_nvram_sizes[] = { 0x8000, 0xF000, 0x10000, };
+ int err;
++ bool found_nvram = false;
+
+ /*
+ * Some really old flashes (like AT45DB*) had smaller erasesize-s, but
+@@ -279,12 +280,23 @@ static int bcm47xxpart_parse(struct mtd_
+ if (buf[0] == NVRAM_HEADER) {
+ bcm47xxpart_add_part(&parts[curr_part++], "nvram",
+ master->size - blocksize, 0);
++ found_nvram = true;
+ break;
+ }
+ }
+
+ kfree(buf);
+
++ if (!found_nvram) {
++ pr_err("can not find a nvram partition reserve last block\n");
++ bcm47xxpart_add_part(&parts[curr_part++], "nvram_guess",
++ master->size - blocksize * 2, MTD_WRITEABLE);
++ for (i = 0; i < curr_part; i++) {
++ if (parts[i].size + parts[i].offset == master->size)
++ parts[i].offset -= blocksize * 2;
++ }
++ }
++
+ /*
+ * Assume that partitions end at the beginning of the one they are
+ * followed by.
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Sun, 7 Nov 2021 14:20:40 +0100
+Subject: [PATCH] net: bgmac: connect to PHY even if it is BGMAC_PHY_NOREGS
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Recent bgmac change was meant to just fix a race between "Generic PHY"
+and "bcm53xx" drivers after -EPROBE_DEFER. It modified bgmac to use
+phy_connect() only if there is a real PHY device connected.
+
+That change broke bgmac on bcm47xx. bcma_phy_connect() now registers a
+fixed PHY with the bgmac_phy_connect_direct(). That fails as another
+fixed PHY (also using address 0) is already registered - by bcm47xx arch
+code bcm47xx_register_bus_complete().
+
+This change brings origial behaviour. It connects Ethernet interface
+with pseudo-PHY (switch device) and adjusts Ethernet interface link to
+match connected switch.
+
+This fixes:
+[ 2.548098] bgmac_bcma bcma0:1: Failed to register fixed PHY device
+[ 2.554584] bgmac_bcma bcma0:1: Cannot connect to phy
+
+Fixes: b5375509184d ("net: bgmac: improve handling PHY")
+Link: https://lore.kernel.org/netdev/3639116e-9292-03ca-b9d9-d741118a4541@gmail.com/T/#u
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/net/ethernet/broadcom/bgmac-bcma.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c
++++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c
+@@ -94,7 +94,7 @@ static int bcma_phy_connect(struct bgmac
+ return 0;
+
+ /* Connect to the PHY */
+- if (bgmac->mii_bus && bgmac->phyaddr != BGMAC_PHY_NOREGS) {
++ if (bgmac->mii_bus) {
+ snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,
+ bgmac->phyaddr);
+ phy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link,
--- /dev/null
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 10 Jun 2022 13:10:47 +0200
+Subject: [PATCH] bgmac: reduce max frame size to support just MTU 1500
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+bgmac allocates new replacement buffer before handling each received
+frame. Allocating & DMA-preparing 9724 B each time consumes a lot of CPU
+time. Ideally bgmac should just respect currently set MTU but it isn't
+the case right now. For now just revert back to the old limited frame
+size.
+
+This change bumps NAT masquarade speed by ~95%.
+
+Ref: 8c7da63978f1 ("bgmac: configure MTU and add support for frames beyond 8192 byte size")
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+---
+ drivers/net/ethernet/broadcom/bgmac.h | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/broadcom/bgmac.h
++++ b/drivers/net/ethernet/broadcom/bgmac.h
+@@ -328,8 +328,7 @@
+ #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */
+ #define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \
+ BGMAC_RX_FRAME_OFFSET)
+-/* Jumbo frame size with FCS */
+-#define BGMAC_RX_MAX_FRAME_SIZE 9724
++#define BGMAC_RX_MAX_FRAME_SIZE 1536
+ #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE)
+ #define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \
+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
--- /dev/null
+When the Ethernet controller is powered down and someone wants to
+access the mdio bus like the witch driver (b53) the system crashed if
+PCI_D3hot was set before. This patch deactivates this power sawing mode
+when a switch driver is in use.
+
+--- a/drivers/net/ethernet/broadcom/tg3.c
++++ b/drivers/net/ethernet/broadcom/tg3.c
+@@ -4269,7 +4269,8 @@ static int tg3_power_down_prepare(struct
+ static void tg3_power_down(struct tg3 *tp)
+ {
+ pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
+- pci_set_power_state(tp->pdev, PCI_D3hot);
++ if (!tg3_flag(tp, ROBOSWITCH))
++ pci_set_power_state(tp->pdev, PCI_D3hot);
+ }
+
+ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex)
--- /dev/null
+From 597715c61ae75a05ab3310a34ff3857a006f0f63 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Thu, 20 Nov 2014 21:32:42 +0100
+Subject: [PATCH] bcma: add table of serial flashes with smaller blocks
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+ drivers/bcma/driver_chipcommon_sflash.c | 29 +++++++++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+--- a/drivers/bcma/driver_chipcommon_sflash.c
++++ b/drivers/bcma/driver_chipcommon_sflash.c
+@@ -9,6 +9,7 @@
+
+ #include <linux/platform_device.h>
+ #include <linux/bcma/bcma.h>
++#include <bcm47xx_board.h>
+
+ static struct resource bcma_sflash_resource = {
+ .name = "bcma_sflash",
+@@ -42,6 +43,13 @@ static const struct bcma_sflash_tbl_e bc
+ { NULL },
+ };
+
++/* Some devices use smaller blocks (and have more of them) */
++static const struct bcma_sflash_tbl_e bcma_sflash_st_shrink_tbl[] = {
++ { "M25P16", 0x14, 0x1000, 512, },
++ { "M25P32", 0x15, 0x1000, 1024, },
++ { NULL },
++};
++
+ static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
+ { "SST25WF512", 1, 0x1000, 16, },
+ { "SST25VF512", 0x48, 0x1000, 16, },
+@@ -85,6 +93,24 @@ static void bcma_sflash_cmd(struct bcma_
+ bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
+ }
+
++const struct bcma_sflash_tbl_e *bcma_sflash_shrink_flash(u32 id)
++{
++ enum bcm47xx_board board = bcm47xx_board_get();
++ const struct bcma_sflash_tbl_e *e;
++
++ switch (board) {
++ case BCM47XX_BOARD_NETGEAR_WGR614_V10:
++ case BCM47XX_BOARD_NETGEAR_WNR1000_V3:
++ for (e = bcma_sflash_st_shrink_tbl; e->name; e++) {
++ if (e->id == id)
++ return e;
++ }
++ return NULL;
++ default:
++ return NULL;
++ }
++}
++
+ /* Initialize serial flash access */
+ int bcma_sflash_init(struct bcma_drv_cc *cc)
+ {
+@@ -115,6 +141,10 @@ int bcma_sflash_init(struct bcma_drv_cc
+ case 0x13:
+ return -ENOTSUPP;
+ default:
++ e = bcma_sflash_shrink_flash(id);
++ if (e)
++ break;
++
+ for (e = bcma_sflash_st_tbl; e->name; e++) {
+ if (e->id == id)
+ break;
--- /dev/null
+The Netgear wgt634u uses a different format for storing the
+configuration. This patch is needed to read out the correct
+configuration. The cfe_env.c file uses a different method way to read
+out the configuration than the in kernel cfe config reader.
+
+--- a/drivers/firmware/broadcom/Makefile
++++ b/drivers/firmware/broadcom/Makefile
+@@ -1,4 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+-obj-$(CONFIG_BCM47XX_NVRAM) += bcm47xx_nvram.o
++obj-$(CONFIG_BCM47XX_NVRAM) += bcm47xx_nvram.o cfe_env.o
+ obj-$(CONFIG_BCM47XX_SPROM) += bcm47xx_sprom.o
+ obj-$(CONFIG_TEE_BNXT_FW) += tee_bnxt_fw.o
+--- /dev/null
++++ b/drivers/firmware/broadcom/cfe_env.c
+@@ -0,0 +1,228 @@
++/*
++ * CFE environment variable access
++ *
++ * Copyright 2001-2003, Broadcom Corporation
++ * Copyright 2006, Felix Fietkau <nbd@nbd.name>
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License as published by the
++ * Free Software Foundation; either version 2 of the License, or (at your
++ * option) any later version.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <asm/io.h>
++#include <linux/uaccess.h>
++
++#define NVRAM_SIZE (0x1ff0)
++static char _nvdata[NVRAM_SIZE];
++static char _valuestr[256];
++
++/*
++ * TLV types. These codes are used in the "type-length-value"
++ * encoding of the items stored in the NVRAM device (flash or EEPROM)
++ *
++ * The layout of the flash/nvram is as follows:
++ *
++ * <type> <length> <data ...> <type> <length> <data ...> <type_end>
++ *
++ * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
++ * The "length" field marks the length of the data section, not
++ * including the type and length fields.
++ *
++ * Environment variables are stored as follows:
++ *
++ * <type_env> <length> <flags> <name> = <value>
++ *
++ * If bit 0 (low bit) is set, the length is an 8-bit value.
++ * If bit 0 (low bit) is clear, the length is a 16-bit value
++ *
++ * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
++ * indicates the size of the length field.
++ *
++ * Flags are from the constants below:
++ *
++ */
++#define ENV_LENGTH_16BITS 0x00 /* for low bit */
++#define ENV_LENGTH_8BITS 0x01
++
++#define ENV_TYPE_USER 0x80
++
++#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
++#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
++
++/*
++ * The actual TLV types we support
++ */
++
++#define ENV_TLV_TYPE_END 0x00
++#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
++
++/*
++ * Environment variable flags
++ */
++
++#define ENV_FLG_NORMAL 0x00 /* normal read/write */
++#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
++#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
++
++#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
++#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
++
++
++/* *********************************************************************
++ * _nvram_read(buffer,offset,length)
++ *
++ * Read data from the NVRAM device
++ *
++ * Input parameters:
++ * buffer - destination buffer
++ * offset - offset of data to read
++ * length - number of bytes to read
++ *
++ * Return value:
++ * number of bytes read, or <0 if error occured
++ ********************************************************************* */
++static int
++_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
++{
++ int i;
++ if (offset > NVRAM_SIZE)
++ return -1;
++
++ for ( i = 0; i < length; i++) {
++ buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
++ }
++ return length;
++}
++
++
++static char*
++_strnchr(const char *dest,int c,size_t cnt)
++{
++ while (*dest && (cnt > 0)) {
++ if (*dest == c) return (char *) dest;
++ dest++;
++ cnt--;
++ }
++ return NULL;
++}
++
++
++
++/*
++ * Core support API: Externally visible.
++ */
++
++/*
++ * Get the value of an NVRAM variable
++ * @param name name of variable to get
++ * @return value of variable or NULL if undefined
++ */
++
++char *cfe_env_get(unsigned char *nv_buf, const char *name)
++{
++ int size;
++ unsigned char *buffer;
++ unsigned char *ptr;
++ unsigned char *envval;
++ unsigned int reclen;
++ unsigned int rectype;
++ int offset;
++ int flg;
++
++ if (!strcmp(name, "nvram_type"))
++ return "cfe";
++
++ size = NVRAM_SIZE;
++ buffer = &_nvdata[0];
++
++ ptr = buffer;
++ offset = 0;
++
++ /* Read the record type and length */
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
++ goto error;
++ }
++
++ while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
++
++ /* Adjust pointer for TLV type */
++ rectype = *(ptr);
++ offset++;
++ size--;
++
++ /*
++ * Read the length. It can be either 1 or 2 bytes
++ * depending on the code
++ */
++ if (rectype & ENV_LENGTH_8BITS) {
++ /* Read the record type and length - 8 bits */
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
++ goto error;
++ }
++ reclen = *(ptr);
++ size--;
++ offset++;
++ }
++ else {
++ /* Read the record type and length - 16 bits, MSB first */
++ if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
++ goto error;
++ }
++ reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
++ size -= 2;
++ offset += 2;
++ }
++
++ if (reclen > size)
++ break; /* should not happen, bad NVRAM */
++
++ switch (rectype) {
++ case ENV_TLV_TYPE_ENV:
++ /* Read the TLV data */
++ if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
++ goto error;
++ flg = *ptr++;
++ envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
++ if (envval) {
++ *envval++ = '\0';
++ memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
++ _valuestr[(reclen-1)-(envval-ptr)] = '\0';
++#if 0
++ printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
++#endif
++ if(!strcmp(ptr, name)){
++ return _valuestr;
++ }
++ if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
++ return _valuestr;
++ }
++ break;
++
++ default:
++ /* Unknown TLV type, skip it. */
++ break;
++ }
++
++ /*
++ * Advance to next TLV
++ */
++
++ size -= (int)reclen;
++ offset += reclen;
++
++ /* Read the next record type */
++ ptr = buffer;
++ if (_nvram_read(nv_buf, ptr,offset,1) != 1)
++ goto error;
++ }
++
++error:
++ return NULL;
++
++}
++
+--- a/drivers/firmware/broadcom/bcm47xx_nvram.c
++++ b/drivers/firmware/broadcom/bcm47xx_nvram.c
+@@ -33,6 +33,8 @@ struct nvram_header {
+ static char nvram_buf[NVRAM_SPACE];
+ static size_t nvram_len;
+ static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000};
++static int cfe_env;
++extern char *cfe_env_get(char *nv_buf, const char *name);
+
+ /**
+ * bcm47xx_nvram_is_valid - check for a valid NVRAM at specified memory
+@@ -80,6 +82,26 @@ static int bcm47xx_nvram_find_and_copy(v
+ return -EEXIST;
+ }
+
++ cfe_env = 0;
++
++ /* XXX: hack for supporting the CFE environment stuff on WGT634U */
++ if (res_size >= 8 * 1024 * 1024) {
++ u32 *src = (u32 *)(flash_start + 8 * 1024 * 1024 - 0x2000);
++ u32 *dst = (u32 *)nvram_buf;
++
++ if ((*src & 0xff00ff) == 0x000001) {
++ printk("early_nvram_init: WGT634U NVRAM found.\n");
++
++ for (i = 0; i < 0x1ff0; i++) {
++ if (*src == 0xFFFFFFFF)
++ break;
++ *dst++ = *src++;
++ }
++ cfe_env = 1;
++ return 0;
++ }
++ }
++
+ /* TODO: when nvram is on nand flash check for bad blocks first. */
+
+ /* Try every possible flash size and check for NVRAM at its end */
+@@ -190,6 +212,13 @@ int bcm47xx_nvram_getenv(const char *nam
+ if (!name)
+ return -EINVAL;
+
++ if (cfe_env) {
++ value = cfe_env_get(nvram_buf, name);
++ if (!value)
++ return -ENOENT;
++ return snprintf(val, val_len, "%s", value);
++ }
++
+ if (!nvram_len) {
+ err = nvram_init();
+ if (err)
--- /dev/null
+--- a/arch/mips/bcm47xx/setup.c
++++ b/arch/mips/bcm47xx/setup.c
+@@ -37,6 +37,7 @@
+ #include <linux/ssb/ssb.h>
+ #include <linux/ssb/ssb_embedded.h>
+ #include <linux/bcma/bcma_soc.h>
++#include <linux/old_gpio_wdt.h>
+ #include <asm/bootinfo.h>
+ #include <asm/idle.h>
+ #include <asm/prom.h>
+@@ -254,6 +255,33 @@ static struct fixed_phy_status bcm47xx_f
+ .duplex = DUPLEX_FULL,
+ };
+
++static struct gpio_wdt_platform_data gpio_wdt_data;
++
++static struct platform_device gpio_wdt_device = {
++ .name = "gpio-wdt",
++ .id = 0,
++ .dev = {
++ .platform_data = &gpio_wdt_data,
++ },
++};
++
++static int __init bcm47xx_register_gpio_watchdog(void)
++{
++ enum bcm47xx_board board = bcm47xx_board_get();
++
++ switch (board) {
++ case BCM47XX_BOARD_HUAWEI_E970:
++ pr_info("bcm47xx: detected Huawei E970 or similar, starting early gpio_wdt timer\n");
++ gpio_wdt_data.gpio = 7;
++ gpio_wdt_data.interval = HZ;
++ gpio_wdt_data.first_interval = HZ / 5;
++ return platform_device_register(&gpio_wdt_device);
++ default:
++ /* Nothing to do */
++ return 0;
++ }
++}
++
+ static int __init bcm47xx_register_bus_complete(void)
+ {
+ switch (bcm47xx_bus_type) {
+@@ -275,6 +303,7 @@ static int __init bcm47xx_register_bus_c
+ bcm47xx_workarounds();
+
+ fixed_phy_add(PHY_POLL, 0, &bcm47xx_fixed_phy_status);
++ bcm47xx_register_gpio_watchdog();
+ return 0;
+ }
+ device_initcall(bcm47xx_register_bus_complete);
+--- a/arch/mips/configs/bcm47xx_defconfig
++++ b/arch/mips/configs/bcm47xx_defconfig
+@@ -62,6 +62,7 @@ CONFIG_HW_RANDOM=y
+ CONFIG_GPIO_SYSFS=y
+ CONFIG_WATCHDOG=y
+ CONFIG_BCM47XX_WDT=y
++CONFIG_GPIO_WDT=y
+ CONFIG_SSB_DRIVER_GIGE=y
+ CONFIG_BCMA_DRIVER_GMAC_CMN=y
+ CONFIG_USB=y
+--- a/drivers/ssb/embedded.c
++++ b/drivers/ssb/embedded.c
+@@ -34,11 +34,36 @@ int ssb_watchdog_timer_set(struct ssb_bu
+ }
+ EXPORT_SYMBOL(ssb_watchdog_timer_set);
+
++#ifdef CONFIG_BCM47XX
++#include <bcm47xx_board.h>
++
++static bool ssb_watchdog_supported(void)
++{
++ enum bcm47xx_board board = bcm47xx_board_get();
++
++ /* The Huawei E970 has a hardware watchdog using a GPIO */
++ switch (board) {
++ case BCM47XX_BOARD_HUAWEI_E970:
++ return false;
++ default:
++ return true;
++ }
++}
++#else
++static bool ssb_watchdog_supported(void)
++{
++ return true;
++}
++#endif
++
+ int ssb_watchdog_register(struct ssb_bus *bus)
+ {
+ struct bcm47xx_wdt wdt = {};
+ struct platform_device *pdev;
+
++ if (!ssb_watchdog_supported())
++ return 0;
++
+ if (ssb_chipco_available(&bus->chipco)) {
+ wdt.driver_data = &bus->chipco;
+ wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
--- /dev/null
+This generic GPIO watchdog is used on Huawei E970 (bcm47xx)
+
+Signed-off-by: Mathias Adam <m.adam--openwrt@adamis.de>
+
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -1755,6 +1755,15 @@ config WDT_MTX1
+ Hardware driver for the MTX-1 boards. This is a watchdog timer that
+ will reboot the machine after a 100 seconds timer expired.
+
++config GPIO_WDT
++ tristate "GPIO Hardware Watchdog"
++ help
++ Hardware driver for GPIO-controlled watchdogs. GPIO pin and
++ toggle interval settings are platform-specific. The driver
++ will stop toggling the GPIO (i.e. machine reboots) after a
++ 100 second timer expired and no process has written to
++ /dev/watchdog during that time.
++
+ config SIBYTE_WDOG
+ tristate "Sibyte SoC hardware watchdog"
+ depends on CPU_SB1
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -167,6 +167,7 @@ obj-$(CONFIG_RC32434_WDT) += rc32434_wdt
+ obj-$(CONFIG_INDYDOG) += indydog.o
+ obj-$(CONFIG_JZ4740_WDT) += jz4740_wdt.o
+ obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o
++obj-$(CONFIG_GPIO_WDT) += old_gpio_wdt.o
+ obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o
+ obj-$(CONFIG_AR7_WDT) += ar7_wdt.o
+ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
+--- /dev/null
++++ b/drivers/watchdog/old_gpio_wdt.c
+@@ -0,0 +1,301 @@
++/*
++ * Driver for GPIO-controlled Hardware Watchdogs.
++ *
++ * Copyright (C) 2013 Mathias Adam <m.adam--linux@adamis.de>
++ *
++ * Replaces mtx1_wdt (driver for the MTX-1 Watchdog):
++ *
++ * (C) Copyright 2005 4G Systems <info@4g-systems.biz>,
++ * All Rights Reserved.
++ * http://www.4g-systems.biz
++ *
++ * (C) Copyright 2007 OpenWrt.org, Florian Fainelli <florian@openwrt.org>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ *
++ * Neither Michael Stickel nor 4G Systems admit liability nor provide
++ * warranty for any of this software. This material is provided
++ * "AS-IS" and at no charge.
++ *
++ * (c) Copyright 2005 4G Systems <info@4g-systems.biz>
++ *
++ * Release 0.01.
++ * Author: Michael Stickel michael.stickel@4g-systems.biz
++ *
++ * Release 0.02.
++ * Author: Florian Fainelli florian@openwrt.org
++ * use the Linux watchdog/timer APIs
++ *
++ * Release 0.03.
++ * Author: Mathias Adam <m.adam--linux@adamis.de>
++ * make it a generic gpio watchdog driver
++ *
++ * The Watchdog is configured to reset the MTX-1
++ * if it is not triggered for 100 seconds.
++ * It should not be triggered more often than 1.6 seconds.
++ *
++ * A timer triggers the watchdog every 5 seconds, until
++ * it is opened for the first time. After the first open
++ * it MUST be triggered every 2..95 seconds.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/types.h>
++#include <linux/errno.h>
++#include <linux/miscdevice.h>
++#include <linux/fs.h>
++#include <linux/init.h>
++#include <linux/ioport.h>
++#include <linux/timer.h>
++#include <linux/completion.h>
++#include <linux/jiffies.h>
++#include <linux/watchdog.h>
++#include <linux/platform_device.h>
++#include <linux/io.h>
++#include <linux/uaccess.h>
++#include <linux/gpio.h>
++#include <linux/old_gpio_wdt.h>
++
++static int ticks = 100 * HZ;
++
++static struct {
++ struct completion stop;
++ spinlock_t lock;
++ int running;
++ struct timer_list timer;
++ int queue;
++ int default_ticks;
++ unsigned long inuse;
++ unsigned gpio;
++ unsigned int gstate;
++ int interval;
++ int first_interval;
++} gpio_wdt_device;
++
++static void gpio_wdt_trigger(struct timer_list *unused)
++{
++ spin_lock(&gpio_wdt_device.lock);
++ if (gpio_wdt_device.running && ticks > 0)
++ ticks -= gpio_wdt_device.interval;
++
++ /* toggle wdt gpio */
++ gpio_wdt_device.gstate = !gpio_wdt_device.gstate;
++ gpio_set_value(gpio_wdt_device.gpio, gpio_wdt_device.gstate);
++
++ if (gpio_wdt_device.queue && ticks > 0)
++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.interval);
++ else
++ complete(&gpio_wdt_device.stop);
++ spin_unlock(&gpio_wdt_device.lock);
++}
++
++static void gpio_wdt_reset(void)
++{
++ ticks = gpio_wdt_device.default_ticks;
++}
++
++
++static void gpio_wdt_start(void)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&gpio_wdt_device.lock, flags);
++ if (!gpio_wdt_device.queue) {
++ gpio_wdt_device.queue = 1;
++ gpio_wdt_device.gstate = 1;
++ gpio_set_value(gpio_wdt_device.gpio, 1);
++ mod_timer(&gpio_wdt_device.timer, jiffies + gpio_wdt_device.first_interval);
++ }
++ gpio_wdt_device.running++;
++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags);
++}
++
++static int gpio_wdt_stop(void)
++{
++ unsigned long flags;
++
++ spin_lock_irqsave(&gpio_wdt_device.lock, flags);
++ if (gpio_wdt_device.queue) {
++ gpio_wdt_device.queue = 0;
++ gpio_wdt_device.gstate = 0;
++ gpio_set_value(gpio_wdt_device.gpio, 0);
++ }
++ ticks = gpio_wdt_device.default_ticks;
++ spin_unlock_irqrestore(&gpio_wdt_device.lock, flags);
++ return 0;
++}
++
++/* Filesystem functions */
++
++static int gpio_wdt_open(struct inode *inode, struct file *file)
++{
++ if (test_and_set_bit(0, &gpio_wdt_device.inuse))
++ return -EBUSY;
++ return nonseekable_open(inode, file);
++}
++
++
++static int gpio_wdt_release(struct inode *inode, struct file *file)
++{
++ clear_bit(0, &gpio_wdt_device.inuse);
++ return 0;
++}
++
++static long gpio_wdt_ioctl(struct file *file, unsigned int cmd,
++ unsigned long arg)
++{
++ void __user *argp = (void __user *)arg;
++ int __user *p = (int __user *)argp;
++ unsigned int value;
++ static const struct watchdog_info ident = {
++ .options = WDIOF_CARDRESET,
++ .identity = "GPIO WDT",
++ };
++
++ switch (cmd) {
++ case WDIOC_GETSUPPORT:
++ if (copy_to_user(argp, &ident, sizeof(ident)))
++ return -EFAULT;
++ break;
++ case WDIOC_GETSTATUS:
++ case WDIOC_GETBOOTSTATUS:
++ put_user(0, p);
++ break;
++ case WDIOC_SETOPTIONS:
++ if (get_user(value, p))
++ return -EFAULT;
++ if (value & WDIOS_ENABLECARD)
++ gpio_wdt_start();
++ else if (value & WDIOS_DISABLECARD)
++ gpio_wdt_stop();
++ else
++ return -EINVAL;
++ return 0;
++ case WDIOC_KEEPALIVE:
++ gpio_wdt_reset();
++ break;
++ default:
++ return -ENOTTY;
++ }
++ return 0;
++}
++
++
++static ssize_t gpio_wdt_write(struct file *file, const char *buf,
++ size_t count, loff_t *ppos)
++{
++ if (!count)
++ return -EIO;
++ gpio_wdt_reset();
++ return count;
++}
++
++static const struct file_operations gpio_wdt_fops = {
++ .owner = THIS_MODULE,
++ .llseek = no_llseek,
++ .unlocked_ioctl = gpio_wdt_ioctl,
++ .open = gpio_wdt_open,
++ .write = gpio_wdt_write,
++ .release = gpio_wdt_release,
++};
++
++
++static struct miscdevice gpio_wdt_misc = {
++ .minor = WATCHDOG_MINOR,
++ .name = "watchdog",
++ .fops = &gpio_wdt_fops,
++};
++
++
++static int gpio_wdt_probe(struct platform_device *pdev)
++{
++ int ret;
++ struct gpio_wdt_platform_data *gpio_wdt_data = pdev->dev.platform_data;
++
++ gpio_wdt_device.gpio = gpio_wdt_data->gpio;
++ gpio_wdt_device.interval = gpio_wdt_data->interval;
++ gpio_wdt_device.first_interval = gpio_wdt_data->first_interval;
++ if (gpio_wdt_device.first_interval <= 0) {
++ gpio_wdt_device.first_interval = gpio_wdt_device.interval;
++ }
++
++ ret = gpio_request(gpio_wdt_device.gpio, "gpio-wdt");
++ if (ret < 0) {
++ dev_err(&pdev->dev, "failed to request gpio");
++ return ret;
++ }
++
++ spin_lock_init(&gpio_wdt_device.lock);
++ init_completion(&gpio_wdt_device.stop);
++ gpio_wdt_device.queue = 0;
++ clear_bit(0, &gpio_wdt_device.inuse);
++ timer_setup(&gpio_wdt_device.timer, gpio_wdt_trigger, 0L);
++ gpio_wdt_device.default_ticks = ticks;
++
++ gpio_wdt_start();
++ dev_info(&pdev->dev, "GPIO Hardware Watchdog driver (gpio=%i interval=%i/%i)\n",
++ gpio_wdt_data->gpio, gpio_wdt_data->first_interval, gpio_wdt_data->interval);
++ return 0;
++}
++
++static int gpio_wdt_remove(struct platform_device *pdev)
++{
++ /* FIXME: do we need to lock this test ? */
++ if (gpio_wdt_device.queue) {
++ gpio_wdt_device.queue = 0;
++ wait_for_completion(&gpio_wdt_device.stop);
++ }
++
++ gpio_free(gpio_wdt_device.gpio);
++ misc_deregister(&gpio_wdt_misc);
++ return 0;
++}
++
++static struct platform_driver gpio_wdt_driver = {
++ .probe = gpio_wdt_probe,
++ .remove = gpio_wdt_remove,
++ .driver.name = "gpio-wdt",
++ .driver.owner = THIS_MODULE,
++};
++
++static int __init gpio_wdt_init(void)
++{
++ return platform_driver_register(&gpio_wdt_driver);
++}
++arch_initcall(gpio_wdt_init);
++
++/*
++ * We do wdt initialization in two steps: arch_initcall probes the wdt
++ * very early to start pinging the watchdog (misc devices are not yet
++ * available), and later module_init() just registers the misc device.
++ */
++static int gpio_wdt_init_late(void)
++{
++ int ret;
++
++ ret = misc_register(&gpio_wdt_misc);
++ if (ret < 0) {
++ pr_err("GPIO_WDT: failed to register misc device\n");
++ return ret;
++ }
++ return 0;
++}
++#ifndef MODULE
++module_init(gpio_wdt_init_late);
++#endif
++
++static void __exit gpio_wdt_exit(void)
++{
++ platform_driver_unregister(&gpio_wdt_driver);
++}
++module_exit(gpio_wdt_exit);
++
++MODULE_AUTHOR("Michael Stickel, Florian Fainelli, Mathias Adam");
++MODULE_DESCRIPTION("Driver for GPIO hardware watchdogs");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
++MODULE_ALIAS("platform:gpio-wdt");
+--- /dev/null
++++ b/include/linux/old_gpio_wdt.h
+@@ -0,0 +1,21 @@
++/*
++ * Definitions for the GPIO watchdog driver
++ *
++ * Copyright (C) 2013 Mathias Adam <m.adam--linux@adamis.de>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef _GPIO_WDT_H_
++#define _GPIO_WDT_H_
++
++struct gpio_wdt_platform_data {
++ int gpio; /* GPIO line number */
++ int interval; /* watchdog reset interval in system ticks */
++ int first_interval; /* first wd reset interval in system ticks */
++};
++
++#endif /* _GPIO_WDT_H_ */
--- /dev/null
+From 5c81397a0147ea59c778d1de14ef54e2268221f6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
+Date: Wed, 8 Apr 2015 06:58:11 +0200
+Subject: [PATCH] ssb: reject PCI writes setting CardBus bridge resources
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+If SoC has a CardBus we can set resources of device at slot 1 only. It's
+impossigle to set bridge resources as it simply overwrites device 1
+configuration and usually results in Data bus error-s.
+
+Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
+---
+ drivers/ssb/driver_pcicore.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -165,6 +165,10 @@ static int ssb_extpci_write_config(struc
+ WARN_ON(!pc->hostmode);
+ if (unlikely(len != 1 && len != 2 && len != 4))
+ goto out;
++ /* CardBus SoCs allow configuring dev 1 resources only */
++ if (extpci_core->cardbusmode && dev != 1 &&
++ off >= PCI_BASE_ADDRESS_0 && off <= PCI_BASE_ADDRESS_5)
++ goto out;
+ addr = get_cfgspace_addr(pc, bus, dev, func, off);
+ if (unlikely(!addr))
+ goto out;
--- /dev/null
+--- a/drivers/pcmcia/yenta_socket.c
++++ b/drivers/pcmcia/yenta_socket.c
+@@ -925,6 +925,8 @@ static struct cardbus_type cardbus_type[
+
+ static unsigned int yenta_probe_irq(struct yenta_socket *socket, u32 isa_irq_mask)
+ {
++/* WRT54G3G does not like this */
++#ifndef CONFIG_BCM47XX
+ int i;
+ unsigned long val;
+ u32 mask;
+@@ -953,6 +955,9 @@ static unsigned int yenta_probe_irq(stru
+ mask = probe_irq_mask(val) & 0xffff;
+
+ return mask;
++#else
++ return 0;
++#endif
+ }
+
+
+@@ -1033,6 +1038,10 @@ static void yenta_get_socket_capabilitie
+ else
+ socket->socket.irq_mask = 0;
+
++ /* irq mask probing is broken for the WRT54G3G */
++ if (socket->socket.irq_mask == 0)
++ socket->socket.irq_mask = 0x6f8;
++
+ dev_info(&socket->dev->dev, "ISA IRQ mask 0x%04x, PCI irq %d\n",
+ socket->socket.irq_mask, socket->cb_irq);
+ }
+@@ -1264,6 +1273,15 @@ static int yenta_probe(struct pci_dev *d
+ dev_info(&dev->dev, "Socket status: %08x\n",
+ cb_readl(socket, CB_SOCKET_STATE));
+
++ /* Generate an interrupt on card insert/remove */
++ config_writew(socket, CB_SOCKET_MASK, CB_CSTSMASK | CB_CDMASK);
++
++ /* Set up Multifunction Routing Status Register */
++ config_writew(socket, 0x8C, 0x1000 /* MFUNC3 to GPIO3 */ | 0x2 /* MFUNC0 to INTA */);
++
++ /* Switch interrupts to parallelized */
++ config_writeb(socket, 0x92, 0x64);
++
+ yenta_fixup_parent_bridge(dev->subordinate);
+
+ /* Register it with the pcmcia layer.. */
--- /dev/null
+--- a/drivers/ssb/driver_pcicore.c
++++ b/drivers/ssb/driver_pcicore.c
+@@ -394,7 +394,7 @@ static void ssb_pcicore_init_hostmode(st
+ /* Give some time to the PCI controller to configure itself with the new
+ * values. Not waiting at this point causes crashes of the machine.
+ */
+- mdelay(10);
++ mdelay(300);
+ register_pci_controller(&ssb_pcicore_controller);
+ }
+
--- /dev/null
+--- a/drivers/firmware/broadcom/bcm47xx_nvram.c
++++ b/drivers/firmware/broadcom/bcm47xx_nvram.c
+@@ -30,7 +30,8 @@ struct nvram_header {
+ u32 config_ncdl; /* ncdl values for memc */
+ };
+
+-static char nvram_buf[NVRAM_SPACE];
++char nvram_buf[NVRAM_SPACE];
++EXPORT_SYMBOL(nvram_buf);
+ static size_t nvram_len;
+ static const u32 nvram_sizes[] = {0x6000, 0x8000, 0xF000, 0x10000};
+ static int cfe_env;
+--- a/arch/mips/mm/cache.c
++++ b/arch/mips/mm/cache.c
+@@ -80,6 +80,9 @@ void (*_dma_cache_wback_inv)(unsigned lo
+ void (*_dma_cache_wback)(unsigned long start, unsigned long size);
+ void (*_dma_cache_inv)(unsigned long start, unsigned long size);
+
++EXPORT_SYMBOL(_dma_cache_wback_inv);
++EXPORT_SYMBOL(_dma_cache_inv);
++
+ #endif /* CONFIG_DMA_NONCOHERENT */
+
+ /*
KERNELNAME:=Image dtbs
SUBTARGETS:=generic
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
+++ /dev/null
-CONFIG_64BIT=y
-# CONFIG_AHCI_SUNXI is not set
-CONFIG_ARCH_CLOCKSOURCE_INIT=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MMAP_RND_BITS=18
-CONFIG_ARCH_MMAP_RND_BITS_MAX=24
-CONFIG_ARCH_MMAP_RND_BITS_MIN=18
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
-CONFIG_ARCH_RV64I=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUNXI=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-CONFIG_ASN1=y
-CONFIG_ASSOCIATIVE_ARRAY=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_CLZ_TAB=y
-CONFIG_CMODEL_MEDANY=y
-# CONFIG_CMODEL_MEDLOW is not set
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-# CONFIG_COMPAT_32BIT_TIME is not set
-CONFIG_COMPAT_BRK=y
-CONFIG_CONTEXT_TRACKING=y
-CONFIG_CONTEXT_TRACKING_IDLE=y
-CONFIG_COREDUMP=y
-CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
-CONFIG_CPU_ISOLATION=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRC16=y
-# CONFIG_CRC32_SARWATE is not set
-CONFIG_CRC32_SLICEBY8=y
-CONFIG_CRC7=y
-CONFIG_CRC_ITU_T=y
-CONFIG_CRYPTO_DEV_ALLWINNER=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DMADEVICES=y
-CONFIG_DMA_DIRECT_REMAP=y
-CONFIG_DMA_ENGINE=y
-CONFIG_DMA_OF=y
-CONFIG_DMA_SUN6I=y
-CONFIG_DMA_VIRTUAL_CHANNELS=y
-CONFIG_DTC=y
-CONFIG_DWMAC_GENERIC=y
-CONFIG_DWMAC_SUN8I=y
-CONFIG_DWMAC_SUNXI=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=m
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_COCO_SECRET is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-CONFIG_EFI_GENERIC_STUB=y
-CONFIG_EFI_PARAMS_FROM_FDT=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-# CONFIG_EFI_ZBOOT is not set
-CONFIG_ELF_CORE=y
-# CONFIG_ERRATA_SIFIVE is not set
-CONFIG_ERRATA_THEAD=y
-CONFIG_ERRATA_THEAD_CMO=y
-CONFIG_ERRATA_THEAD_PBMT=y
-CONFIG_EXT4_FS=y
-CONFIG_EXTCON=y
-CONFIG_FAILOVER=y
-CONFIG_FHANDLE=y
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_AUTOSELECT=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FPU=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FRAME_WARN=2048
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ARCH_TOPOLOGY=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CSUM=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IOREMAP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_PHY=y
-CONFIG_GENERIC_PINCONF=y
-CONFIG_GENERIC_PINCTRL_GROUPS=y
-CONFIG_GENERIC_PINMUX_FUNCTIONS=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HID_GENERIC=y
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_RISCV_SBI=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_HELPER_AUTO=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_I2C_OCORES=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUGFS is not set
-# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
-CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IO_URING=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-# CONFIG_KEYBOARD_SUN4I_LRADC is not set
-# CONFIG_LEDS_PWM_MULTICOLOR is not set
-# CONFIG_LEDS_SUN50I_A100 is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_MAILBOX=y
-# CONFIG_MAILBOX_TEST is not set
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_BUS_MUX=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-# CONFIG_MDIO_SUN4I is not set
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_AXP20X=y
-CONFIG_MFD_AXP20X_I2C=y
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_SUN4I_GPADC is not set
-CONFIG_MFD_SUN6I_PRCM=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_SUNXI=y
-CONFIG_MMIOWB=y
-CONFIG_MTD_SPI_NOR=y
-CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
-# CONFIG_MUSB_PIO_ONLY is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_VENDOR_ALLWINNER=y
-CONFIG_NLS=y
-# CONFIG_NONPORTABLE is not set
-CONFIG_NOP_USB_XCEIV=y
-CONFIG_NR_CPUS=8
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SUNXI_SID=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_DMA_DEFAULT_COHERENT=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IOMMU=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-CONFIG_OID_REGISTRY=y
-CONFIG_PADATA=y
-CONFIG_PAGE_OFFSET=0xff60000000000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-# CONFIG_PAGE_TABLE_CHECK is not set
-CONFIG_PANIC_TIMEOUT=0
-CONFIG_PCPU_DEV_REFCNT=y
-CONFIG_PGTABLE_LEVELS=5
-CONFIG_PHYLIB=y
-CONFIG_PHYLINK=y
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PHY_SUN4I_USB=y
-CONFIG_PHY_SUN50I_USB3=y
-# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
-# CONFIG_PHY_SUN9I_USB is not set
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_SUN20I_D1=y
-# CONFIG_PINCTRL_SUN4I_A10 is not set
-# CONFIG_PINCTRL_SUN50I_A100 is not set
-# CONFIG_PINCTRL_SUN50I_A100_R is not set
-# CONFIG_PINCTRL_SUN50I_A64 is not set
-# CONFIG_PINCTRL_SUN50I_A64_R is not set
-# CONFIG_PINCTRL_SUN50I_H5 is not set
-# CONFIG_PINCTRL_SUN50I_H6 is not set
-# CONFIG_PINCTRL_SUN50I_H616 is not set
-# CONFIG_PINCTRL_SUN50I_H616_R is not set
-# CONFIG_PINCTRL_SUN50I_H6_R is not set
-# CONFIG_PINCTRL_SUN5I is not set
-# CONFIG_PINCTRL_SUN6I_A31 is not set
-# CONFIG_PINCTRL_SUN6I_A31_R is not set
-# CONFIG_PINCTRL_SUN8I_A23 is not set
-# CONFIG_PINCTRL_SUN8I_A23_R is not set
-# CONFIG_PINCTRL_SUN8I_A33 is not set
-# CONFIG_PINCTRL_SUN8I_A83T is not set
-# CONFIG_PINCTRL_SUN8I_A83T_R is not set
-# CONFIG_PINCTRL_SUN8I_H3 is not set
-# CONFIG_PINCTRL_SUN8I_H3_R is not set
-# CONFIG_PINCTRL_SUN8I_V3S is not set
-# CONFIG_PINCTRL_SUN9I_A80 is not set
-# CONFIG_PINCTRL_SUN9I_A80_R is not set
-CONFIG_PINCTRL_SUNXI=y
-CONFIG_PORTABLE=y
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_POWER_RESET_SYSCON_POWEROFF=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PRINTK_TIME=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_PWM=y
-# CONFIG_PWM_CLK is not set
-# CONFIG_PWM_SIFIVE is not set
-# CONFIG_PWM_SUN4I is not set
-# CONFIG_PWM_SUN8I_V536 is not set
-CONFIG_PWM_SYSFS=y
-# CONFIG_PWM_XILINX is not set
-CONFIG_RATIONAL=y
-CONFIG_RCU_TRACE=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_IRQ=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_AXP20X is not set
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_REGULATOR_SUN20I=y
-# CONFIG_RESET_ATTACK_MITIGATION is not set
-CONFIG_RESET_CONTROLLER=y
-CONFIG_RESET_SIMPLE=y
-CONFIG_RESET_SUNXI=y
-CONFIG_RISCV=y
-CONFIG_RISCV_ALTERNATIVE=y
-CONFIG_RISCV_ALTERNATIVE_EARLY=y
-CONFIG_RISCV_BOOT_SPINWAIT=y
-CONFIG_RISCV_DMA_NONCOHERENT=y
-CONFIG_RISCV_INTC=y
-CONFIG_RISCV_ISA_C=y
-CONFIG_RISCV_ISA_SVPBMT=y
-CONFIG_RISCV_ISA_ZICBOM=y
-CONFIG_RISCV_SBI=y
-CONFIG_RISCV_SBI_V01=y
-CONFIG_RISCV_TIMER=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_DRV_EFI is not set
-CONFIG_RTC_DRV_GOLDFISH=y
-CONFIG_RTC_DRV_SUN6I=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-CONFIG_SCHED_DEBUG=y
-CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
-CONFIG_SERIAL_8250_DW=y
-CONFIG_SERIAL_8250_DWLIB=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SIFIVE_PLIC=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_SMP=y
-# CONFIG_SND_SUN20I_CODEC is not set
-# CONFIG_SND_SUN4I_I2S is not set
-# CONFIG_SND_SUN50I_DMIC is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
-# CONFIG_SOC_SIFIVE is not set
-# CONFIG_SOC_STARFIVE is not set
-# CONFIG_SOC_VIRT is not set
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_MASTER=y
-CONFIG_SPI_MEM=y
-# CONFIG_SPI_SUN4I is not set
-CONFIG_SPI_SUN6I=y
-CONFIG_SRCU=y
-CONFIG_STACKDEPOT=y
-CONFIG_STACKTRACE=y
-CONFIG_STMMAC_ETH=y
-CONFIG_STMMAC_PLATFORM=y
-CONFIG_SUN20I_D1_CCU=y
-CONFIG_SUN20I_D1_R_CCU=y
-# CONFIG_SUN4I_EMAC is not set
-CONFIG_SUN4I_TIMER=y
-CONFIG_SUN50I_IOMMU=y
-CONFIG_SUN6I_MSGBOX=y
-CONFIG_SUN6I_RTC_CCU=y
-CONFIG_SUN8I_DE2_CCU=y
-# CONFIG_SUN8I_R_CCU is not set
-# CONFIG_SUN8I_THERMAL is not set
-CONFIG_SUNXI_CCU=y
-# CONFIG_SUNXI_RSB is not set
-CONFIG_SUNXI_SRAM=y
-CONFIG_SUNXI_WATCHDOG=y
-CONFIG_SWIOTLB=y
-CONFIG_SWPHY=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_SYSFB_SIMPLEFB is not set
-CONFIG_SYSFS_SYSCALL=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TOOLCHAIN_HAS_ZICBOM=y
-CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
-CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
-CONFIG_TRACE_CLOCK=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_TUNE_GENERIC=y
-# CONFIG_UACCE is not set
-CONFIG_UCS2_STRING=y
-CONFIG_UEVENT_HELPER_PATH=""
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_HID=y
-CONFIG_USB_MUSB_HDRC=y
-CONFIG_USB_MUSB_HOST=y
-CONFIG_USB_MUSB_SUNXI=y
-CONFIG_USB_NET_DRIVERS=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PLATFORM=y
-CONFIG_USB_PHY=y
-CONFIG_USB_SUPPORT=y
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_USB_XHCI_HCD=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-CONFIG_VGA_ARB=y
-CONFIG_VGA_ARB_MAX_GPUS=16
-# CONFIG_VHOST_MENU is not set
-# CONFIG_VIRTIO_MENU is not set
-CONFIG_VMAP_STACK=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_XPS=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZONE_DMA32=y
--- /dev/null
+CONFIG_64BIT=y
+# CONFIG_ACPI is not set
+# CONFIG_AHCI_SUNXI is not set
+CONFIG_ARCH_CLOCKSOURCE_INIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=24
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=17
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_RV64I=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUNXI=y
+# CONFIG_ARCH_THEAD is not set
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+# CONFIG_AX45MP_L2_CACHE is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMODEL_MEDANY=y
+# CONFIG_CMODEL_MEDLOW is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+# CONFIG_COMPAT_32BIT_TIME is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_ISOLATION=y
+CONFIG_CPU_RMAP=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC7=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRYPTO_DEV_ALLWINNER=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_SUN6I=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DTC=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DWMAC_SUN8I=y
+CONFIG_DWMAC_SUNXI=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=m
+# CONFIG_EFI_BOOTLOADER_CONTROL is not set
+# CONFIG_EFI_CAPSULE_LOADER is not set
+# CONFIG_EFI_COCO_SECRET is not set
+# CONFIG_EFI_DISABLE_PCI_DMA is not set
+# CONFIG_EFI_DISABLE_RUNTIME is not set
+CONFIG_EFI_EARLYCON=y
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_GENERIC_STUB=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_ZBOOT is not set
+CONFIG_ELF_CORE=y
+# CONFIG_ERRATA_ANDES is not set
+# CONFIG_ERRATA_SIFIVE is not set
+CONFIG_ERRATA_THEAD=y
+CONFIG_ERRATA_THEAD_CMO=y
+CONFIG_ERRATA_THEAD_PBMT=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_FAILOVER=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_AUTOSELECT=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FPU=y
+CONFIG_FRAME_POINTER=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_RISCV_SBI=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_MV64XXX=y
+CONFIG_I2C_OCORES=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IOMMUFD is not set
+CONFIG_IO_URING=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_STACKS=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+# CONFIG_KEYBOARD_SUN4I_LRADC is not set
+# CONFIG_LEDS_PWM_MULTICOLOR is not set
+# CONFIG_LEDS_SUN50I_A100 is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_SUN4I is not set
+CONFIG_MEMFD_CREATE=y
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_SUN4I_GPADC is not set
+CONFIG_MFD_SUN6I_PRCM=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MMIOWB=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+# CONFIG_MUSB_PIO_ONLY is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_VENDOR_ALLWINNER=y
+CONFIG_NLS=y
+# CONFIG_NONPORTABLE is not set
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_NR_CPUS=8
+CONFIG_NVMEM=y
+CONFIG_NVMEM_SUNXI_SID=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DMA_DEFAULT_COHERENT=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OID_REGISTRY=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xff60000000000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PAGE_TABLE_CHECK is not set
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PCPU_DEV_REFCNT=y
+CONFIG_PGTABLE_LEVELS=5
+CONFIG_PHYLIB=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_PHY_SUN50I_USB3=y
+# CONFIG_PHY_SUN6I_MIPI_DPHY is not set
+# CONFIG_PHY_SUN9I_USB is not set
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SUN20I_D1=y
+# CONFIG_PINCTRL_SUN4I_A10 is not set
+# CONFIG_PINCTRL_SUN50I_A100 is not set
+# CONFIG_PINCTRL_SUN50I_A100_R is not set
+# CONFIG_PINCTRL_SUN50I_A64 is not set
+# CONFIG_PINCTRL_SUN50I_A64_R is not set
+# CONFIG_PINCTRL_SUN50I_H5 is not set
+# CONFIG_PINCTRL_SUN50I_H6 is not set
+# CONFIG_PINCTRL_SUN50I_H616 is not set
+# CONFIG_PINCTRL_SUN50I_H616_R is not set
+# CONFIG_PINCTRL_SUN50I_H6_R is not set
+# CONFIG_PINCTRL_SUN5I is not set
+# CONFIG_PINCTRL_SUN6I_A31 is not set
+# CONFIG_PINCTRL_SUN6I_A31_R is not set
+# CONFIG_PINCTRL_SUN8I_A23 is not set
+# CONFIG_PINCTRL_SUN8I_A23_R is not set
+# CONFIG_PINCTRL_SUN8I_A33 is not set
+# CONFIG_PINCTRL_SUN8I_A83T is not set
+# CONFIG_PINCTRL_SUN8I_A83T_R is not set
+# CONFIG_PINCTRL_SUN8I_H3 is not set
+# CONFIG_PINCTRL_SUN8I_H3_R is not set
+# CONFIG_PINCTRL_SUN8I_V3S is not set
+# CONFIG_PINCTRL_SUN9I_A80 is not set
+# CONFIG_PINCTRL_SUN9I_A80_R is not set
+CONFIG_PINCTRL_SUNXI=y
+CONFIG_PORTABLE=y
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+# CONFIG_PWM_CLK is not set
+# CONFIG_PWM_SIFIVE is not set
+# CONFIG_PWM_SUN4I is not set
+# CONFIG_PWM_SUN8I_V536 is not set
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_XILINX is not set
+CONFIG_RATIONAL=y
+CONFIG_RCU_TRACE=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_AXP20X is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_SUN20I=y
+# CONFIG_RESET_ATTACK_MITIGATION is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_SIMPLE=y
+CONFIG_RESET_SUNXI=y
+CONFIG_RISCV=y
+CONFIG_RISCV_ALTERNATIVE=y
+CONFIG_RISCV_ALTERNATIVE_EARLY=y
+CONFIG_RISCV_BOOT_SPINWAIT=y
+CONFIG_RISCV_DMA_NONCOHERENT=y
+CONFIG_RISCV_INTC=y
+CONFIG_RISCV_ISA_C=y
+CONFIG_RISCV_ISA_FALLBACK=y
+CONFIG_RISCV_ISA_SVNAPOT=y
+CONFIG_RISCV_ISA_SVPBMT=y
+CONFIG_RISCV_ISA_V=y
+CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y
+CONFIG_RISCV_ISA_ZBB=y
+CONFIG_RISCV_ISA_ZICBOM=y
+CONFIG_RISCV_ISA_ZICBOZ=y
+CONFIG_RISCV_SBI=y
+CONFIG_RISCV_SBI_V01=y
+CONFIG_RISCV_TIMER=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_EFI is not set
+CONFIG_RTC_DRV_GOLDFISH=y
+CONFIG_RTC_DRV_SUN6I=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SIFIVE_PLIC=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SMP=y
+# CONFIG_SND_SUN20I_CODEC is not set
+# CONFIG_SND_SUN20I_D1_CODEC_ANALOG is not set
+# CONFIG_SND_SUN4I_I2S is not set
+# CONFIG_SND_SUN50I_DMIC is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+# CONFIG_SOC_MICROCHIP_POLARFIRE is not set
+# CONFIG_SOC_SIFIVE is not set
+# CONFIG_SOC_STARFIVE is not set
+# CONFIG_SOC_VIRT is not set
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_SUN4I is not set
+CONFIG_SPI_SUN6I=y
+CONFIG_SRCU=y
+CONFIG_STACKDEPOT=y
+CONFIG_STACKTRACE=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_SUN20I_D1_CCU=y
+CONFIG_SUN20I_D1_R_CCU=y
+CONFIG_SUN20I_GPADC=y
+# CONFIG_SUN4I_EMAC is not set
+CONFIG_SUN4I_TIMER=y
+CONFIG_SUN50I_IOMMU=y
+CONFIG_SUN6I_MSGBOX=y
+CONFIG_SUN6I_RTC_CCU=y
+CONFIG_SUN8I_DE2_CCU=y
+# CONFIG_SUN8I_R_CCU is not set
+CONFIG_SUN8I_THERMAL=y
+CONFIG_SUNXI_CCU=y
+# CONFIG_SUNXI_RSB is not set
+CONFIG_SUNXI_SRAM=y
+CONFIG_SUNXI_WATCHDOG=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+# CONFIG_SYSFB_SIMPLEFB is not set
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_THREAD_SIZE_ORDER=2
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TOOLCHAIN_HAS_ZICBOM=y
+CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y
+CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y
+CONFIG_TRACE_CLOCK=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_TUNE_GENERIC=y
+# CONFIG_UACCE is not set
+CONFIG_UCS2_STRING=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_HID=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_SUNXI=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_PHY=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_XHCI_HCD=y
+# CONFIG_USB_XHCI_PLATFORM is not set
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_VHOST_MENU is not set
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_XPS=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+++ /dev/null
-From e663d510ae6a81694a8e9e1ce07bb80dd6b77558 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 24 Jul 2022 17:12:07 -0500
-Subject: [PATCH 001/117] dt-bindings: net: bluetooth: realtek: Add RTL8723DS
-
-RTL8723DS is another version of the RTL8723 WiFi + Bluetooth chip. It is
-already supported by the hci_uart/btrtl driver. Document the compatible.
-
-Series-to: Marcel Holtmann <marcel@holtmann.org>
-Series-to: Johan Hedberg <johan.hedberg@gmail.com>
-Series-to: Luiz Augusto von Dentz <luiz.dentz@gmail.com>
-Series-to: David S. Miller <davem@davemloft.net>
-Series-to: Eric Dumazet <edumazet@google.com>
-Series-to: Jakub Kicinski <kuba@kernel.org>
-Series-to: Paolo Abeni <pabeni@redhat.com>
-Series-cc: linux-bluetooth@vger.kernel.org
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- Documentation/devicetree/bindings/net/realtek-bluetooth.yaml | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml
-+++ b/Documentation/devicetree/bindings/net/realtek-bluetooth.yaml
-@@ -20,6 +20,7 @@ properties:
- enum:
- - realtek,rtl8723bs-bt
- - realtek,rtl8723cs-bt
-+ - realtek,rtl8723ds-bt
- - realtek,rtl8822cs-bt
-
- device-wake-gpios:
+++ /dev/null
-From 74492b9ecd874496578693d9985649665b560308 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 20:08:49 -0500
-Subject: [PATCH 002/117] clk: sunxi-ng: mp: Avoid computing the rate twice
-
-ccu_mp_find_best() already computes a best_rate at the same time as the
-best m and p factors. Return it so the caller does not need to duplicate
-the division.
-
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/clk/sunxi-ng/ccu_mp.c | 11 ++++++-----
- 1 file changed, 6 insertions(+), 5 deletions(-)
-
---- a/drivers/clk/sunxi-ng/ccu_mp.c
-+++ b/drivers/clk/sunxi-ng/ccu_mp.c
-@@ -10,9 +10,9 @@
- #include "ccu_gate.h"
- #include "ccu_mp.h"
-
--static void ccu_mp_find_best(unsigned long parent, unsigned long rate,
-- unsigned int max_m, unsigned int max_p,
-- unsigned int *m, unsigned int *p)
-+static unsigned long ccu_mp_find_best(unsigned long parent, unsigned long rate,
-+ unsigned int max_m, unsigned int max_p,
-+ unsigned int *m, unsigned int *p)
- {
- unsigned long best_rate = 0;
- unsigned int best_m = 0, best_p = 0;
-@@ -35,6 +35,8 @@ static void ccu_mp_find_best(unsigned lo
-
- *m = best_m;
- *p = best_p;
-+
-+ return best_rate;
- }
-
- static unsigned long ccu_mp_find_best_with_parent_adj(struct clk_hw *hw,
-@@ -109,8 +111,7 @@ static unsigned long ccu_mp_round_rate(s
- max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);
-
- if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {
-- ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
-- rate = *parent_rate / p / m;
-+ rate = ccu_mp_find_best(*parent_rate, rate, max_m, max_p, &m, &p);
- } else {
- rate = ccu_mp_find_best_with_parent_adj(hw, parent_rate, rate,
- max_m, max_p);
+++ /dev/null
-From 7185f7b424dfd9082bf0859a60b98a2dbd784ed6 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Mon, 5 Sep 2022 16:45:44 -0500
-Subject: [PATCH 003/117] dt-bindings: net: sun8i-emac: Add phy-supply property
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
-+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
-@@ -40,6 +40,9 @@ properties:
- clock-names:
- const: stmmaceth
-
-+ phy-supply:
-+ description: PHY regulator
-+
- syscon:
- $ref: /schemas/types.yaml#/definitions/phandle
- description:
+++ /dev/null
-From d20bb97fac77e4d88424043627c769427fc0d35e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Mon, 5 Sep 2022 16:46:34 -0500
-Subject: [PATCH 004/117] dt-bindings: net: sun8i-emac: Add properties from
- dwmac binding
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml | 5 +++++
- 1 file changed, 5 insertions(+)
-
---- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
-+++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml
-@@ -40,6 +40,9 @@ properties:
- clock-names:
- const: stmmaceth
-
-+ resets: true
-+ reset-names: true
-+
- phy-supply:
- description: PHY regulator
-
-@@ -49,6 +52,8 @@ properties:
- Phandle to the device containing the EMAC or GMAC clock
- register
-
-+ mdio: true
-+
- required:
- - compatible
- - reg
+++ /dev/null
-From c99d1e681dc460892004054a314fa7f929f43490 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 13 Aug 2022 10:45:59 -0500
-Subject: [PATCH 005/117] dt-bindings: display: sun8i-a83t-dw-hdmi: Remove
- #phy-cells
-
-This device is not a PHY, and none of the nodes using this schema
-contain a #phy-cells property. Likely this was a copy/paste error
-introduced during the YAML conversion.
-
-Fixes: f5a98bfe7b37 ("dt-bindings: display: Convert Allwinner display pipeline to schemas")
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 3 ---
- 1 file changed, 3 deletions(-)
-
---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
-@@ -20,9 +20,6 @@ maintainers:
- - Maxime Ripard <mripard@kernel.org>
-
- properties:
-- "#phy-cells":
-- const: 0
--
- compatible:
- oneOf:
- - const: allwinner,sun8i-a83t-dw-hdmi
+++ /dev/null
-From e214b79d45cccdd0cfe839e54da2b3c82b6c6be4 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 31 Mar 2022 23:43:15 -0500
-Subject: [PATCH 006/117] dt-bindings: display: Add D1 HDMI compatibles
-
-Allwinner D1 contains a DesignWare HDMI controller with some changes in
-platform integration, and a new HDMI PHY. Add their compatibles.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml | 1 +
- .../bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
-@@ -29,6 +29,7 @@ properties:
- - enum:
- - allwinner,sun8i-h3-dw-hdmi
- - allwinner,sun8i-r40-dw-hdmi
-+ - allwinner,sun20i-d1-dw-hdmi
- - allwinner,sun50i-a64-dw-hdmi
- - const: allwinner,sun8i-a83t-dw-hdmi
-
---- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
-@@ -19,6 +19,7 @@ properties:
- - allwinner,sun8i-a83t-hdmi-phy
- - allwinner,sun8i-h3-hdmi-phy
- - allwinner,sun8i-r40-hdmi-phy
-+ - allwinner,sun20i-d1-hdmi-phy
- - allwinner,sun50i-a64-hdmi-phy
- - allwinner,sun50i-h6-hdmi-phy
-
+++ /dev/null
-From 75dc74ecc1bf5e270659c6c78877053b50e6ae19 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 30 Mar 2022 21:24:21 -0500
-Subject: [PATCH 007/117] drm/sun4i: Add support for D1 HDMI
-
-D1's HDMI controller contains some platform integration changes.
-It now has no external TMDS clock. The controller also supports HDCP
-without an external clock or reset.
-
-While the maximum HDMI frequency is not explicity stated, the BSP PHY
-driver provides PLL configurations only up to 297 MHz, so use that as
-the max frequency.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
-+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
-@@ -133,7 +133,7 @@ static int sun8i_dw_hdmi_bind(struct dev
- return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl),
- "Could not get ctrl reset control\n");
-
-- hdmi->clk_tmds = devm_clk_get(dev, "tmds");
-+ hdmi->clk_tmds = devm_clk_get_optional(dev, "tmds");
- if (IS_ERR(hdmi->clk_tmds))
- return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds),
- "Couldn't get the tmds clock\n");
-@@ -246,6 +246,11 @@ static const struct sun8i_dw_hdmi_quirks
- .mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
- };
-
-+static const struct sun8i_dw_hdmi_quirks sun20i_d1_quirks = {
-+ .mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
-+ .use_drm_infoframe = true,
-+};
-+
- static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
- .mode_valid = sun8i_dw_hdmi_mode_valid_h6,
- .use_drm_infoframe = true,
-@@ -257,6 +262,10 @@ static const struct of_device_id sun8i_d
- .data = &sun8i_a83t_quirks,
- },
- {
-+ .compatible = "allwinner,sun20i-d1-dw-hdmi",
-+ .data = &sun20i_d1_quirks,
-+ },
-+ {
- .compatible = "allwinner,sun50i-h6-dw-hdmi",
- .data = &sun50i_h6_quirks,
- },
+++ /dev/null
-From 11f9765a8e6723bcb7243f6dbc48e6deaf17b097 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 3 Apr 2022 15:15:41 -0500
-Subject: [PATCH 008/117] drm/sun4i: sun8i-hdmi-phy: Add support for D1 PHY
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 169 +++++++++++++++++++++++++
- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 32 +++++
- 2 files changed, 201 insertions(+)
-
---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
-+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
-@@ -145,6 +145,175 @@
-
- #define SUN8I_HDMI_PHY_CEC_REG 0x003c
-
-+#define SUN20I_HDMI_PHY_CTL0_REG 0x0040
-+#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE_MAN BIT(31)
-+#define SUN20I_HDMI_PHY_CTL0_PLL_LOCK_MODE BIT(30)
-+#define SUN20I_HDMI_PHY_CTL0_FIFO_WORKC_EN BIT(29)
-+#define SUN20I_HDMI_PHY_CTL0_FIFO_AUTOSYNC_DIS BIT(28)
-+#define SUN20I_HDMI_PHY_CTL0_ENTX GENMASK(27, 24)
-+#define SUN20I_HDMI_PHY_CTL0_ENBI GENMASK(23, 20)
-+#define SUN20I_HDMI_PHY_CTL0_ENLDO BIT(18)
-+#define SUN20I_HDMI_PHY_CTL0_ENLDO_FS BIT(17)
-+#define SUN20I_HDMI_PHY_CTL0_ENCK BIT(16)
-+#define SUN20I_HDMI_PHY_CTL0_REG_PLR GENMASK(15, 12)
-+#define SUN20I_HDMI_PHY_CTL0_REG_DEN GENMASK(11, 8)
-+#define SUN20I_HDMI_PHY_CTL0_REG_CSMPS GENMASK(7, 6)
-+#define SUN20I_HDMI_PHY_CTL0_REG_CK_TEST_SEL BIT(5)
-+#define SUN20I_HDMI_PHY_CTL0_REG_CK_SEL BIT(4)
-+#define SUN20I_HDMI_PHY_CTL0_HPD_EN BIT(2)
-+#define SUN20I_HDMI_PHY_CTL0_SCL_EN BIT(1)
-+#define SUN20I_HDMI_PHY_CTL0_SDA_EN BIT(0)
-+
-+#define SUN20I_HDMI_PHY_CTL1_REG 0x0044
-+#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE_MAN BIT(31)
-+#define SUN20I_HDMI_PHY_CTL1_RXSENSE_MODE BIT(30)
-+#define SUN20I_HDMI_PHY_CTL1_RES_S GENMASK(29, 28)
-+#define SUN20I_HDMI_PHY_CTL1_RES_SCKTMDS BIT(27)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SWI BIT(26)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SVR GENMASK(25, 24)
-+#define SUN20I_HDMI_PHY_CTL1_REG_BST2 GENMASK(21, 20)
-+#define SUN20I_HDMI_PHY_CTL1_REG_BST1 GENMASK(19, 18)
-+#define SUN20I_HDMI_PHY_CTL1_REG_BST0 GENMASK(17, 16)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_3 GENMASK(15, 12)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_2 GENMASK(11, 8)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_1 GENMASK(7, 4)
-+#define SUN20I_HDMI_PHY_CTL1_REG_SP2_0 GENMASK(3, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL2_REG 0x0048
-+#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE_MAN BIT(31)
-+#define SUN20I_HDMI_PHY_CTL2_HPDO_MODE BIT(30)
-+#define SUN20I_HDMI_PHY_CTL2_REG_RESDI GENMASK(29, 24)
-+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_3 GENMASK(23, 19)
-+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_2 GENMASK(18, 14)
-+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_1 GENMASK(13, 9)
-+#define SUN20I_HDMI_PHY_CTL2_REG_SP1_0 GENMASK(8, 4)
-+#define SUN20I_HDMI_PHY_CTL2_REG_P2OPT GENMASK(3, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL3_REG 0x004c
-+#define SUN20I_HDMI_PHY_CTL3_REG_P2_3 GENMASK(31, 28)
-+#define SUN20I_HDMI_PHY_CTL3_REG_P2_2 GENMASK(27, 24)
-+#define SUN20I_HDMI_PHY_CTL3_REG_P2_1 GENMASK(23, 20)
-+#define SUN20I_HDMI_PHY_CTL3_REG_P2_0 GENMASK(19, 16)
-+#define SUN20I_HDMI_PHY_CTL3_REG_MC3 GENMASK(15, 12)
-+#define SUN20I_HDMI_PHY_CTL3_REG_MC2 GENMASK(11, 8)
-+#define SUN20I_HDMI_PHY_CTL3_REG_MC1 GENMASK(7, 4)
-+#define SUN20I_HDMI_PHY_CTL3_REG_MC0 GENMASK(3, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL4_REG 0x0050
-+#define SUN20I_HDMI_PHY_CTL4_REG_SLV GENMASK(31, 29)
-+#define SUN20I_HDMI_PHY_CTL4_REG_P1_3 GENMASK(28, 24)
-+#define SUN20I_HDMI_PHY_CTL4_REG_P1_2 GENMASK(20, 16)
-+#define SUN20I_HDMI_PHY_CTL4_REG_P1_1 GENMASK(12, 8)
-+#define SUN20I_HDMI_PHY_CTL4_REG_P1_0 GENMASK(4, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL5_REG 0x0054
-+#define SUN20I_HDMI_PHY_CTL5_REG_P1OPT GENMASK(19, 16)
-+#define SUN20I_HDMI_PHY_CTL5_REG_CKPDLYOPT BIT(12)
-+#define SUN20I_HDMI_PHY_CTL5_REG_CALSW BIT(11)
-+#define SUN20I_HDMI_PHY_CTL5_ENRESCK BIT(10)
-+#define SUN20I_HDMI_PHY_CTL5_ENRES BIT(9)
-+#define SUN20I_HDMI_PHY_CTL5_ENRCAL BIT(8)
-+#define SUN20I_HDMI_PHY_CTL5_ENP2S GENMASK(7, 4)
-+#define SUN20I_HDMI_PHY_CTL5_ENIB BIT(1)
-+#define SUN20I_HDMI_PHY_CTL5_ENCALOG BIT(0)
-+
-+#define SUN20I_HDMI_PLL_CTL0_REG 0x0058
-+#define SUN20I_HDMI_PLL_CTL0_CKO_SEL GENMASK(31, 30)
-+#define SUN20I_HDMI_PLL_CTL0_BYPASS_PPLL BIT(29)
-+#define SUN20I_HDMI_PLL_CTL0_ENVBS BIT(28)
-+#define SUN20I_HDMI_PLL_CTL0_SLV GENMASK(26, 24)
-+#define SUN20I_HDMI_PLL_CTL0_BCR BIT(23)
-+#define SUN20I_HDMI_PLL_CTL0_BYPASS_CLRDPTH BIT(22)
-+#define SUN20I_HDMI_PLL_CTL0_CLR_DPTH GENMASK(21, 20)
-+#define SUN20I_HDMI_PLL_CTL0_CUTFB BIT(18)
-+#define SUN20I_HDMI_PLL_CTL0_DIV2_CKBIT BIT(17)
-+#define SUN20I_HDMI_PLL_CTL0_DIV2_CKTMDS BIT(16)
-+#define SUN20I_HDMI_PLL_CTL0_DIV_PRE GENMASK(15, 12)
-+#define SUN20I_HDMI_PLL_CTL0_DIVX1 BIT(10)
-+#define SUN20I_HDMI_PLL_CTL0_SDRVEN BIT(9)
-+#define SUN20I_HDMI_PLL_CTL0_VCORANGE BIT(8)
-+#define SUN20I_HDMI_PLL_CTL0_N_CNTRL GENMASK(7, 6)
-+#define SUN20I_HDMI_PLL_CTL0_GMP_CNTRL GENMASK(5, 4)
-+#define SUN20I_HDMI_PLL_CTL0_PROP_CNTRL GENMASK(2, 0)
-+
-+#define SUN20I_HDMI_PLL_CTL1_REG 0x005c
-+#define SUN20I_HDMI_PLL_CTL1_CTRL_MODLE_CLKSRC BIT(31)
-+#define SUN20I_HDMI_PLL_CTL1_PCNT_N GENMASK(27, 20)
-+#define SUN20I_HDMI_PLL_CTL1_PCNT_EN BIT(19)
-+#define SUN20I_HDMI_PLL_CTL1_SDM_EN BIT(18)
-+#define SUN20I_HDMI_PLL_CTL1_PIXEL_REP GENMASK(17, 16)
-+#define SUN20I_HDMI_PLL_CTL1_PWRON BIT(12)
-+#define SUN20I_HDMI_PLL_CTL1_RESET BIT(11)
-+#define SUN20I_HDMI_PLL_CTL1_SCKREF BIT(10)
-+#define SUN20I_HDMI_PLL_CTL1_SCKFB BIT(9)
-+#define SUN20I_HDMI_PLL_CTL1_DRV_ANA BIT(8)
-+#define SUN20I_HDMI_PLL_CTL1_FAST_TECH BIT(7)
-+#define SUN20I_HDMI_PLL_CTL1_GEAR_SHIFT BIT(6)
-+#define SUN20I_HDMI_PLL_CTL1_REF_CNTRL GENMASK(5, 4)
-+#define SUN20I_HDMI_PLL_CTL1_INT_CNTRL GENMASK(2, 0)
-+
-+#define SUN20I_HDMI_AFIFO_CFG_REG 0x0060
-+#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR BIT(0)
-+#define SUN20I_HDMI_AFIFO_CFG_AFIFO_ERROR_DET BIT(1)
-+
-+#define SUN20I_HDMI_MODULATOR_CFG0_REG 0x0064
-+#define SUN20I_HDMI_MODULATOR_CFG1_REG 0x0068
-+
-+#define SUN20I_HDMI_INDEB_CTRL_REG 0x006c
-+#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUGMODE BIT(29)
-+#define SUN20I_HDMI_INDEB_CTRL_HPDI_DEBUG BIT(28)
-+#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUGMODE BIT(25)
-+#define SUN20I_HDMI_INDEB_CTRL_SDAI_DEBUG BIT(24)
-+#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUGMODE BIT(21)
-+#define SUN20I_HDMI_INDEB_CTRL_SCLI_DEBUG BIT(20)
-+#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUGMODE BIT(17)
-+#define SUN20I_HDMI_INDEB_CTRL_CECI_DEBUG BIT(16)
-+#define SUN20I_HDMI_INDEB_CTRL_TXDATA_DEBUGMODE GENMASK(1, 0)
-+
-+#define SUN20I_HDMI_INDBG_TXD0_REG 0x0070
-+#define SUN20I_HDMI_INDBG_TXD1_REG 0x0074
-+#define SUN20I_HDMI_INDBG_TXD2_REG 0x0078
-+#define SUN20I_HDMI_INDBG_TXD3_REG 0x007c
-+
-+#define SUN20I_HDMI_PLL_STS_REG 0x0080
-+#define SUN20I_HDMI_PLL_STS_PHY_CDETPCK_STATUS BIT(31)
-+#define SUN20I_HDMI_PLL_STS_PHY_CDETP_STATUS GENMASK(30, 28)
-+#define SUN20I_HDMI_PLL_STS_PHY_CDETNCK_STATUS BIT(27)
-+#define SUN20I_HDMI_PLL_STS_PHY_CDETN_STATUS GENMASK(26, 24)
-+#define SUN20I_HDMI_PLL_STS_PHY_HPDO_STATUS BIT(23)
-+#define SUN20I_HDMI_PLL_STS_PHY_SCLO_STATUS BIT(22)
-+#define SUN20I_HDMI_PLL_STS_PHY_SDAO_STATUS BIT(21)
-+#define SUN20I_HDMI_PLL_STS_PHY_CECO_STATUS BIT(20)
-+#define SUN20I_HDMI_PLL_STS_PHY_COUT2D_STATUS BIT(17)
-+#define SUN20I_HDMI_PLL_STS_PHY_RCALEND2D_STS BIT(16)
-+#define SUN20I_HDMI_PLL_STS_PHY_RESDO2D_STATUS GENMASK(13, 8)
-+#define SUN20I_HDMI_PLL_STS_PLL_LOCK_STATUS BIT(4)
-+#define SUN20I_HDMI_PLL_STS_RXSENSE_DLY_STATUS BIT(1)
-+#define SUN20I_HDMI_PLL_STS_TX_READY_DLY_STATUS BIT(0)
-+
-+#define SUN20I_HDMI_PRBS_CTL_REG 0x0084
-+#define SUN20I_HDMI_PRBS_SEED_GEN_REG 0x0088
-+#define SUN20I_HDMI_PRBS_SEED_CHK_REG 0x008c
-+#define SUN20I_HDMI_PRBS_SEED_NUM_REG 0x0090
-+#define SUN20I_HDMI_PRBS_CYCLE_NUM_REG 0x0094
-+
-+#define SUN20I_HDMI_PLL_ODLY_REG 0x0098
-+#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_RESET BIT(31)
-+#define SUN20I_HDMI_PLL_ODLY_RXSENSE_DLY_COUNT GENMASK(30, 16)
-+#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_RESET BIT(15)
-+#define SUN20I_HDMI_PLL_ODLY_TX_READY_DLY_COUNT GENMASK(14, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL6_REG 0x009c
-+#define SUN20I_HDMI_PHY_CTL6_SWITCH_CLKCH_DATA BIT(31)
-+#define SUN20I_HDMI_PHY_CTL6_EN_CKDAT BIT(30)
-+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE2_340M GENMASK(29, 20)
-+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE1_340M GENMASK(19, 10)
-+#define SUN20I_HDMI_PHY_CTL6_CLK_GREATE0_340M GENMASK(9, 0)
-+
-+#define SUN20I_HDMI_PHY_CTL7_REG 0x00a0
-+#define SUN20I_HDMI_PHY_CTL7_CLK_LOW_340M GENMASK(21, 12)
-+#define SUN20I_HDMI_PHY_CTL7_CLK_GREATE3_340M GENMASK(9, 0)
-+
- struct sun8i_hdmi_phy;
-
- struct sun8i_hdmi_phy_variant {
---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
-+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
-@@ -398,6 +398,28 @@ static const struct dw_hdmi_phy_ops sun8
- .setup_hpd = dw_hdmi_phy_setup_hpd,
- };
-
-+static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
-+ const struct drm_display_info *display,
-+ const struct drm_display_mode *mode)
-+{
-+ struct sun8i_hdmi_phy *phy = data;
-+
-+ return 0;
-+}
-+
-+static void sun20i_d1_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
-+{
-+ struct sun8i_hdmi_phy *phy = data;
-+}
-+
-+static const struct dw_hdmi_phy_ops sun20i_d1_hdmi_phy_ops = {
-+ .init = sun20i_d1_hdmi_phy_config,
-+ .disable = sun20i_d1_hdmi_phy_disable,
-+ .read_hpd = dw_hdmi_phy_read_hpd,
-+ .update_hpd = dw_hdmi_phy_update_hpd,
-+ .setup_hpd = dw_hdmi_phy_setup_hpd,
-+};
-+
- static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy)
- {
- /* enable read access to HDMI controller */
-@@ -576,6 +598,7 @@ void sun8i_hdmi_phy_set_ops(struct sun8i
- const struct sun8i_hdmi_phy_variant *variant = phy->variant;
-
- if (variant->phy_ops) {
-+ plat_data->phy_force_vendor = true;
- plat_data->phy_ops = variant->phy_ops;
- plat_data->phy_name = "sun8i_dw_hdmi_phy";
- plat_data->phy_data = phy;
-@@ -612,6 +635,11 @@ static const struct sun8i_hdmi_phy_varia
- .phy_init = &sun8i_hdmi_phy_init_h3,
- };
-
-+static const struct sun8i_hdmi_phy_variant sun20i_d1_hdmi_phy = {
-+ .phy_ops = &sun20i_d1_hdmi_phy_ops,
-+ .phy_init = &sun50i_hdmi_phy_init_h6,
-+};
-+
- static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = {
- .has_phy_clk = true,
- .phy_ops = &sun8i_h3_hdmi_phy_ops,
-@@ -639,6 +667,10 @@ static const struct of_device_id sun8i_h
- .data = &sun8i_r40_hdmi_phy,
- },
- {
-+ .compatible = "allwinner,sun20i-d1-hdmi-phy",
-+ .data = &sun20i_d1_hdmi_phy,
-+ },
-+ {
- .compatible = "allwinner,sun50i-a64-hdmi-phy",
- .data = &sun50i_a64_hdmi_phy,
- },
+++ /dev/null
-From 7ea7d4abfd537230da58533803a2d0257addace8 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 30 Mar 2022 00:46:07 -0500
-Subject: [PATCH 009/117] drm/sun4i: Copy in BSP code for D1 HDMI PHY
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/aw_phy.h | 411 +++++++++++++++++++++++++
- drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 1 +
- drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 156 ++++++++++
- 3 files changed, 568 insertions(+)
- create mode 100644 drivers/gpu/drm/sun4i/aw_phy.h
-
---- /dev/null
-+++ b/drivers/gpu/drm/sun4i/aw_phy.h
-@@ -0,0 +1,411 @@
-+/*
-+ * Allwinner SoCs hdmi2.0 driver.
-+ *
-+ * Copyright (C) 2016 Allwinner.
-+ *
-+ * This file is licensed under the terms of the GNU General Public
-+ * License version 2. This program is licensed "as is" without any
-+ * warranty of any kind, whether express or implied.
-+ */
-+
-+#ifndef AW_PHY_H_
-+#define AW_PHY_H_
-+
-+#define AW_PHY_TIMEOUT 1000
-+#define LOCK_TIMEOUT 100
-+
-+/* allwinner phy register offset */
-+#define HDMI_PHY_CTL0 0x40
-+#define HDMI_PHY_CTL1 0x44
-+#define HDMI_PHY_CTL2 0x48
-+#define HDMI_PHY_CTL3 0x4C
-+#define HDMI_PHY_CTL4 0x50
-+#define HDMI_PHY_CTL5 0x54
-+#define HDMI_PLL_CTL0 0x58
-+#define HDMI_PLL_CTL1 0x5C
-+#define HDMI_AFIFO_CFG 0x60
-+#define HDMI_MODULATOR_CFG0 0x64
-+#define HDMI_MODULATOR_CFG1 0x68
-+#define HDMI_PHY_INDEB_CTRL 0x6C
-+#define HDMI_PHY_INDBG_TXD0 0x70
-+#define HDMI_PHY_INDBG_TXD1 0x74
-+#define HDMI_PHY_INDBG_TXD2 0x78
-+#define HDMI_PHY_INDBG_TXD3 0x7C
-+#define HDMI_PHY_PLL_STS 0x80
-+#define HDMI_PRBS_CTL 0x84
-+#define HDMI_PRBS_SEED_GEN 0x88
-+#define HDMI_PRBS_SEED_CHK 0x8C
-+#define HDMI_PRBS_SEED_NUM 0x90
-+#define HDMI_PRBS_CYCLE_NUM 0x94
-+#define HDMI_PHY_PLL_ODLY_CFG 0x98
-+#define HDMI_PHY_CTL6 0x9C
-+#define HDMI_PHY_CTL7 0xA0
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 sda_en :1; // Default: 0;
-+ u32 scl_en :1; // Default: 0;
-+ u32 hpd_en :1; // Default: 0;
-+ u32 res0 :1; // Default: 0;
-+ u32 reg_ck_sel :1; // Default: 1;
-+ u32 reg_ck_test_sel :1; // Default: 1;
-+ u32 reg_csmps :2; // Default: 0;
-+ u32 reg_den :4; // Default: F;
-+ u32 reg_plr :4; // Default: 0;
-+ u32 enck :1; // Default: 1;
-+ u32 enldo_fs :1; // Default: 1;
-+ u32 enldo :1; // Default: 1;
-+ u32 res1 :1; // Default: 1;
-+ u32 enbi :4; // Default: F;
-+ u32 entx :4; // Default: F;
-+ u32 async_fifo_autosync_disable :1; // Default: 0;
-+ u32 async_fifo_workc_enable :1; // Default: 1;
-+ u32 phy_pll_lock_mode :1; // Default: 1;
-+ u32 phy_pll_lock_mode_man :1; // Default: 1;
-+ } bits;
-+} HDMI_PHY_CTL0_t; //=========================== 0x0040
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 reg_sp2_0 : 4 ; // Default: 0;
-+ u32 reg_sp2_1 : 4 ; // Default: 0;
-+ u32 reg_sp2_2 : 4 ; // Default: 0;
-+ u32 reg_sp2_3 : 4 ; // Default: 0;
-+ u32 reg_bst0 : 2 ; // Default: 3;
-+ u32 reg_bst1 : 2 ; // Default: 3;
-+ u32 reg_bst2 : 2 ; // Default: 3;
-+ u32 res0 : 2 ; // Default: 0;
-+ u32 reg_svr : 2 ; // Default: 2;
-+ u32 reg_swi : 1 ; // Default: 0;
-+ u32 res_scktmds : 1 ; // Default: 0;
-+ u32 res_res_s : 2 ; // Default: 3;
-+ u32 phy_rxsense_mode : 1 ; // Default: 0;
-+ u32 res_rxsense_mode_man : 1 ; // Default: 0;
-+ } bits;
-+} HDMI_PHY_CTL1_t; //===================================================== 0x0044
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 reg_p2opt : 4 ; // Default: 0;
-+ u32 reg_sp1_0 : 5 ; // Default: 0;
-+ u32 reg_sp1_1 : 5 ; // Default: 0;
-+ u32 reg_sp1_2 : 5 ; // Default: 0;
-+ u32 reg_sp1_3 : 5 ; // Default: 0;
-+ u32 reg_resdi : 6 ; // Default: 18;
-+ u32 phy_hpdo_mode : 1 ; // Default: 0;
-+ u32 phy_hpdo_mode_man : 1 ; // Default: 0;
-+ } bits;
-+} HDMI_PHY_CTL2_t; //===================================================== 0x0048
-+
-+
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 reg_mc0 : 4 ; // Default: F;
-+ u32 reg_mc1 : 4 ; // Default: F;
-+ u32 reg_mc2 : 4 ; // Default: F;
-+ u32 reg_mc3 : 4 ; // Default: F;
-+ u32 reg_p2_0 : 4 ; // Default: F;
-+ u32 reg_p2_1 : 4 ; // Default: F;
-+ u32 reg_p2_2 : 4 ; // Default: F;
-+ u32 reg_p2_3 : 4 ; // Default: F;
-+ } bits;
-+} HDMI_PHY_CTL3_t; //===================================================== 0x004C
-+
-+
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 reg_p1_0 : 5 ; // Default: 0x10;
-+ u32 res0 : 3 ; // Default: 0;
-+ u32 reg_p1_1 : 5 ; // Default: 0x10;
-+ u32 res1 : 3 ; // Default: 0;
-+ u32 reg_p1_2 : 5 ; // Default: 0x10;
-+ u32 res2 : 3 ; // Default: 0;
-+ u32 reg_p1_3 : 5 ; // Default: 0x10;
-+ u32 reg_slv : 3 ; // Default: 0;
-+ } bits;
-+} HDMI_PHY_CTL4_t; //===================================================== 0x0050
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 encalog : 1 ; // Default: 0x1;
-+ u32 enib : 1 ; // Default: 0x1;
-+ u32 res0 : 2 ; // Default: 0;
-+ u32 enp2s : 4 ; // Default: 0xF;
-+ u32 enrcal : 1 ; // Default: 0x1;
-+ u32 enres : 1 ; // Default: 1;
-+ u32 enresck : 1 ; // Default: 1;
-+ u32 reg_calsw : 1 ; // Default: 0;
-+ u32 reg_ckpdlyopt : 1 ; // Default: 0;
-+ u32 res1 : 3 ; // Default: 0;
-+ u32 reg_p1opt : 4 ; // Default: 0;
-+ u32 res2 : 12 ; // Default: 0;
-+ } bits;
-+} HDMI_PHY_CTL5_t; //===================================================== 0x0054
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 prop_cntrl : 3 ; // Default: 0x7;
-+ u32 res0 : 1 ; // Default: 0;
-+ u32 gmp_cntrl : 2 ; // Default: 1;
-+ u32 n_cntrl : 2 ; // Default: 0;
-+ u32 vcorange : 1 ; // Default: 0;
-+ u32 sdrven : 1 ; // Default: 0;
-+ u32 divx1 : 1 ; // Default: 0;
-+ u32 res1 : 1 ; // Default: 0;
-+ u32 div_pre : 4 ; // Default: 0;
-+ u32 div2_cktmds : 1 ; // Default: 1;
-+ u32 div2_ckbit : 1 ; // Default: 1;
-+ u32 cutfb : 1 ; // Default: 0;
-+ u32 res2 : 1 ; // Default: 0;
-+ u32 clr_dpth : 2 ; // Default: 0;
-+ u32 bypass_clrdpth : 1 ; // Default: 0;
-+ u32 bcr : 1 ; // Default: 0;
-+ u32 slv : 3 ; // Default: 4;
-+ u32 res3 : 1 ; // Default: 0;
-+ u32 envbs : 1 ; // Default: 0;
-+ u32 bypass_ppll : 1 ; // Default: 0;
-+ u32 cko_sel : 2 ; // Default: 0;
-+ } bits;
-+} HDMI_PLL_CTL0_t; //===================================================== 0x0058
-+
-+
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 int_cntrl : 3 ; // Default: 0x0;
-+ u32 res0 : 1 ; // Default: 0;
-+ u32 ref_cntrl : 2 ; // Default: 3;
-+ u32 gear_shift : 1 ; // Default: 0;
-+ u32 fast_tech : 1 ; // Default: 0;
-+ u32 drv_ana : 1 ; // Default: 1;
-+ u32 sckfb : 1 ; // Default: 0;
-+ u32 sckref : 1 ; // Default: 0;
-+ u32 reset : 1 ; // Default: 0;
-+ u32 pwron : 1 ; // Default: 0;
-+ u32 res1 : 3 ; // Default: 0;
-+ u32 pixel_rep : 2 ; // Default: 0;
-+ u32 sdm_en : 1 ; // Default: 0;
-+ u32 pcnt_en : 1 ; // Default: 0;
-+ u32 pcnt_n : 8 ; // Default: 0xE;
-+ u32 res2 : 3 ; // Default: 0;
-+ u32 ctrl_modle_clksrc : 1 ; // Default: 0;
-+ } bits;
-+} HDMI_PLL_CTL1_t; //===================================================== 0x005C
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 hdmi_afifo_error : 1 ; // Default: 0x0;
-+ u32 hdmi_afifo_error_det : 1 ; // Default: 0x0;
-+ u32 res0 : 30 ; // Default: 0;
-+ } bits;
-+} HDMI_AFIFO_CFG_t; //===================================================== 0x0060
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 fnpll_mash_en : 1 ; // Default: 0x0;
-+ u32 fnpll_mash_mod : 2 ; // Default: 0x0;
-+ u32 fnpll_mash_stp : 9 ; // Default: 0x0;
-+ u32 fnpll_mash_m12 : 1 ; // Default: 0x0;
-+ u32 fnpll_mash_frq : 2 ; // Default: 0x0;
-+ u32 fnpll_mash_bot : 17 ; // Default: 0x0;
-+ } bits;
-+} HDMI_MODULATOR_CFG0_t; //===================================================== 0x0064
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 fnpll_mash_dth : 1 ; // Default: 0x0;
-+ u32 fnpll_mash_fen : 1 ; // Default: 0x0;
-+ u32 fnpll_mash_frc : 17 ; // Default: 0x0;
-+ u32 fnpll_mash_fnv : 8 ; // Default: 0x0;
-+ u32 res0 : 5 ; // Default: 0x0;
-+ } bits;
-+} HDMI_MODULATOR_CFG1_t; //===================================================== 0x0068
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 txdata_debugmode : 2 ; // Default: 0x0;
-+ u32 res0 : 14 ; // Default: 0x0;
-+ u32 ceci_debug : 1 ; // Default: 0x0;
-+ u32 ceci_debugmode : 1 ; // Default: 0x0;
-+ u32 res1 : 2 ; // Default: 0x0;
-+ u32 sdai_debug : 1 ; // Default: 0x0;
-+ u32 sdai_debugmode : 1 ; // Default: 0x0;
-+ u32 res2 : 2 ; // Default: 0x0;
-+ u32 scli_debug : 1 ; // Default: 0x0;
-+ u32 scli_debugmode : 1 ; // Default: 0x0;
-+ u32 res3 : 2 ; // Default: 0x0;
-+ u32 hpdi_debug : 1 ; // Default: 0x0;
-+ u32 hpdi_debugmode : 1 ; // Default: 0x0;
-+ u32 res4 : 2 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PHY_INDBG_CTRL_t; //================================================== 0x006C
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 txdata0_debug_data : 32 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PHY_INDBG_TXD0_t; //================================================== 0x0070
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 txdata1_debug_data : 32 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PHY_INDBG_TXD1_t; //================================================== 0x0074
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 txdata2_debug_data : 32 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PHY_INDBG_TXD2_t; //================================================== 0x0078
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 txdata3_debug_data : 32 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PHY_INDBG_TXD3_t; //================================================== 0x007C
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 tx_ready_dly_status : 1 ; // Default: 0x0;
-+ u32 rxsense_dly_status : 1 ; // Default: 0x0;
-+ u32 res0 : 2 ; // Default: 0x0;
-+ u32 pll_lock_status : 1 ; // Default: 0x0;
-+ u32 res1 : 3 ; // Default: 0x0;
-+ u32 phy_resdo2d_status : 6 ; // Default: 0x0;
-+ u32 res2 : 2 ; // Default: 0x0;
-+ u32 phy_rcalend2d_status : 1 ; // Default: 0x0;
-+ u32 phy_cout2d_status : 1 ; // Default: 0x0;
-+ u32 res3 : 2 ; // Default: 0x0;
-+ u32 phy_ceco_status : 1 ; // Default: 0x0;
-+ u32 phy_sdao_status : 1 ; // Default: 0x0;
-+ u32 phy_sclo_status : 1 ; // Default: 0x0;
-+ u32 phy_hpdo_status : 1 ; // Default: 0x0;
-+ u32 phy_cdetn_status : 3 ; // Default: 0x0;
-+ u32 phy_cdetnck_status : 1 ; // Default: 0x0;
-+ u32 phy_cdetp_status : 3 ; // Default: 0x0;
-+ u32 phy_cdetpck_status : 1 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PHY_PLL_STS_t; //===================================================== 0x0080
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 prbs_en : 1 ; // Default: 0x0;
-+ u32 prbs_start : 1 ; // Default: 0x0;
-+ u32 prbs_seq_gen : 1 ; // Default: 0x0;
-+ u32 prbs_seq_chk : 1 ; // Default: 0x0;
-+ u32 prbs_mode : 4 ; // Default: 0x0;
-+ u32 prbs_type : 2 ; // Default: 0x0;
-+ u32 prbs_clk_pol : 1 ; // Default: 0x0;
-+ u32 res0 : 21 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PRBS_CTL_t; //===================================================== 0x0084
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 prbs_seed_gen : 32 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PRBS_SEED_GEN_t; //================================================= 0x0088
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 prbs_seed_chk : 32 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PRBS_SEED_CHK_t; //================================================= 0x008C
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 prbs_seed_num : 32 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PRBS_SEED_NUM_t; //================================================= 0x0090
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 prbs_cycle_num : 32 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PRBS_CYCLE_NUM_t; //================================================= 0x0094
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 tx_ready_dly_count : 15 ; // Default: 0x0;
-+ u32 tx_ready_dly_reset : 1 ; // Default: 0x0;
-+ u32 rxsense_dly_count : 15 ; // Default: 0x0;
-+ u32 rxsense_dly_reset : 1 ; // Default: 0x0;
-+ } bits;
-+} HDMI_PHY_PLL_ODLY_CFG_t; //================================================= 0x0098
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 clk_greate0_340m : 10 ; // Default: 0x3FF;
-+ u32 clk_greate1_340m : 10 ; // Default: 0x3FF;
-+ u32 clk_greate2_340m : 10 ; // Default: 0x3FF;
-+ u32 en_ckdat : 1 ; // Default: 0x3FF;
-+ u32 switch_clkch_data_corresponding : 1 ; // Default: 0x3FF;
-+ } bits;
-+} HDMI_PHY_CTL6_t; //========================================================= 0x009C
-+
-+typedef union {
-+ u32 dwval;
-+ struct {
-+ u32 clk_greate3_340m : 10 ; // Default: 0x0;
-+ u32 res0 : 2 ; // Default: 0x3FF;
-+ u32 clk_low_340m : 10 ; // Default: 0x3FF;
-+ u32 res1 : 10 ; // Default: 0x3FF;
-+ } bits;
-+} HDMI_PHY_CTL7_t; //========================================================= 0x00A0
-+
-+struct __aw_phy_reg_t {
-+ u32 res[16]; /* 0x0 ~ 0x3c */
-+ HDMI_PHY_CTL0_t phy_ctl0; /* 0x0040 */
-+ HDMI_PHY_CTL1_t phy_ctl1; /* 0x0044 */
-+ HDMI_PHY_CTL2_t phy_ctl2; /* 0x0048 */
-+ HDMI_PHY_CTL3_t phy_ctl3; /* 0x004c */
-+ HDMI_PHY_CTL4_t phy_ctl4; /* 0x0050 */
-+ HDMI_PHY_CTL5_t phy_ctl5; /* 0x0054 */
-+ HDMI_PLL_CTL0_t pll_ctl0; /* 0x0058 */
-+ HDMI_PLL_CTL1_t pll_ctl1; /* 0x005c */
-+ HDMI_AFIFO_CFG_t afifo_cfg; /* 0x0060 */
-+ HDMI_MODULATOR_CFG0_t modulator_cfg0; /* 0x0064 */
-+ HDMI_MODULATOR_CFG1_t modulator_cfg1; /* 0x0068 */
-+ HDMI_PHY_INDBG_CTRL_t phy_indbg_ctrl; /* 0x006c */
-+ HDMI_PHY_INDBG_TXD0_t phy_indbg_txd0; /* 0x0070 */
-+ HDMI_PHY_INDBG_TXD1_t phy_indbg_txd1; /* 0x0074 */
-+ HDMI_PHY_INDBG_TXD2_t phy_indbg_txd2; /* 0x0078 */
-+ HDMI_PHY_INDBG_TXD3_t phy_indbg_txd3; /* 0x007c */
-+ HDMI_PHY_PLL_STS_t phy_pll_sts; /* 0x0080 */
-+ HDMI_PRBS_CTL_t prbs_ctl; /* 0x0084 */
-+ HDMI_PRBS_SEED_GEN_t prbs_seed_gen; /* 0x0088 */
-+ HDMI_PRBS_SEED_CHK_t prbs_seed_chk; /* 0x008c */
-+ HDMI_PRBS_SEED_NUM_t prbs_seed_num; /* 0x0090 */
-+ HDMI_PRBS_CYCLE_NUM_t prbs_cycle_num; /* 0x0094 */
-+ HDMI_PHY_PLL_ODLY_CFG_t phy_pll_odly_cfg; /* 0x0098 */
-+ HDMI_PHY_CTL6_t phy_ctl6; /* 0x009c */
-+ HDMI_PHY_CTL7_t phy_ctl7; /* 0x00A0 */
-+};
-+
-+#endif /* AW_PHY_H_ */
---- a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
-+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h
-@@ -334,6 +334,7 @@ struct sun8i_hdmi_phy {
- struct clk *clk_pll1;
- struct device *dev;
- unsigned int rcal;
-+ void __iomem *base;
- struct regmap *regs;
- struct reset_control *rst_phy;
- const struct sun8i_hdmi_phy_variant *variant;
---- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
-+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
-@@ -9,6 +9,8 @@
-
- #include "sun8i_dw_hdmi.h"
-
-+#include "aw_phy.h"
-+
- /*
- * Address can be actually any value. Here is set to same value as
- * it is set in BSP driver.
-@@ -398,11 +400,164 @@ static const struct dw_hdmi_phy_ops sun8
- .setup_hpd = dw_hdmi_phy_setup_hpd,
- };
-
-+static int sun20i_d1_hdmi_phy_enable(volatile struct __aw_phy_reg_t __iomem *phy_base)
-+{
-+ int i = 0, status = 0;
-+
-+ pr_info("enter %s\n", __func__);
-+
-+ //enib -> enldo -> enrcal -> encalog -> enbi[3:0] -> enck -> enp2s[3:0] -> enres -> enresck -> entx[3:0]
-+ phy_base->phy_ctl4.bits.reg_slv = 4; //low power voltage 1.08V, default is 3, set 4 as well as pll_ctl0 bit [24:26]
-+ phy_base->phy_ctl5.bits.enib = 1;
-+ phy_base->phy_ctl0.bits.enldo = 1;
-+ phy_base->phy_ctl0.bits.enldo_fs = 1;
-+ phy_base->phy_ctl5.bits.enrcal = 1;
-+
-+ phy_base->phy_ctl5.bits.encalog = 1;
-+
-+ for (i = 0; i < AW_PHY_TIMEOUT; i++) {
-+ udelay(5);
-+ status = phy_base->phy_pll_sts.bits.phy_rcalend2d_status;
-+ if (status & 0x1) {
-+ pr_info("[%s]:phy_rcalend2d_status\n", __func__);
-+ break;
-+ }
-+ }
-+ if ((i == AW_PHY_TIMEOUT) && !status) {
-+ pr_err("phy_rcalend2d_status Timeout !\n");
-+ return -1;
-+ }
-+
-+ phy_base->phy_ctl0.bits.enbi = 0xF;
-+ for (i = 0; i < AW_PHY_TIMEOUT; i++) {
-+ udelay(5);
-+ status = phy_base->phy_pll_sts.bits.pll_lock_status;
-+ if (status & 0x1) {
-+ pr_info("[%s]:pll_lock_status\n", __func__);
-+ break;
-+ }
-+ }
-+ if ((i == AW_PHY_TIMEOUT) && !status) {
-+ pr_err("pll_lock_status Timeout! status = 0x%x\n", status);
-+ return -1;
-+ }
-+
-+ phy_base->phy_ctl0.bits.enck = 1;
-+ phy_base->phy_ctl5.bits.enp2s = 0xF;
-+ phy_base->phy_ctl5.bits.enres = 1;
-+ phy_base->phy_ctl5.bits.enresck = 1;
-+ phy_base->phy_ctl0.bits.entx = 0xF;
-+
-+ for (i = 0; i < AW_PHY_TIMEOUT; i++) {
-+ udelay(5);
-+ status = phy_base->phy_pll_sts.bits.tx_ready_dly_status;
-+ if (status & 0x1) {
-+ pr_info("[%s]:tx_ready_status\n", __func__);
-+ break;
-+ }
-+ }
-+ if ((i == AW_PHY_TIMEOUT) && !status) {
-+ pr_err("tx_ready_status Timeout ! status = 0x%x\n", status);
-+ return -1;
-+ }
-+
-+ return 0;
-+}
-+
- static int sun20i_d1_hdmi_phy_config(struct dw_hdmi *hdmi, void *data,
- const struct drm_display_info *display,
- const struct drm_display_mode *mode)
- {
- struct sun8i_hdmi_phy *phy = data;
-+ volatile struct __aw_phy_reg_t __iomem *phy_base = phy->base;
-+ int ret;
-+
-+ pr_info("enter %s\n", __func__);
-+
-+ /* enable all channel */
-+ phy_base->phy_ctl5.bits.reg_p1opt = 0xF;
-+
-+ // phy_reset
-+ phy_base->phy_ctl0.bits.entx = 0;
-+ phy_base->phy_ctl5.bits.enresck = 0;
-+ phy_base->phy_ctl5.bits.enres = 0;
-+ phy_base->phy_ctl5.bits.enp2s = 0;
-+ phy_base->phy_ctl0.bits.enck = 0;
-+ phy_base->phy_ctl0.bits.enbi = 0;
-+ phy_base->phy_ctl5.bits.encalog = 0;
-+ phy_base->phy_ctl5.bits.enrcal = 0;
-+ phy_base->phy_ctl0.bits.enldo_fs = 0;
-+ phy_base->phy_ctl0.bits.enldo = 0;
-+ phy_base->phy_ctl5.bits.enib = 0;
-+ phy_base->pll_ctl1.bits.reset = 1;
-+ phy_base->pll_ctl1.bits.pwron = 0;
-+ phy_base->pll_ctl0.bits.envbs = 0;
-+
-+ // phy_set_mpll
-+ phy_base->pll_ctl0.bits.cko_sel = 0x3;
-+ phy_base->pll_ctl0.bits.bypass_ppll = 0x1;
-+ phy_base->pll_ctl1.bits.drv_ana = 1;
-+ phy_base->pll_ctl1.bits.ctrl_modle_clksrc = 0x0; //0: PLL_video 1: MPLL
-+ phy_base->pll_ctl1.bits.sdm_en = 0x0; //mpll sdm jitter is very large, not used for the time being
-+ phy_base->pll_ctl1.bits.sckref = 0; //default value is 1
-+ phy_base->pll_ctl0.bits.slv = 4;
-+ phy_base->pll_ctl0.bits.prop_cntrl = 7; //default value 7
-+ phy_base->pll_ctl0.bits.gmp_cntrl = 3; //default value 1
-+ phy_base->pll_ctl1.bits.ref_cntrl = 0;
-+ phy_base->pll_ctl0.bits.vcorange = 1;
-+
-+ // phy_set_div
-+ phy_base->pll_ctl0.bits.div_pre = 0; //div7 = n+1
-+ phy_base->pll_ctl1.bits.pcnt_en = 0;
-+ phy_base->pll_ctl1.bits.pcnt_n = 1; //div6 = 1 (pcnt_en=0) [div6 = n (pcnt_en = 1) note that some multiples are problematic] 4-256
-+ phy_base->pll_ctl1.bits.pixel_rep = 0; //div5 = n+1
-+ phy_base->pll_ctl0.bits.bypass_clrdpth = 0;
-+ phy_base->pll_ctl0.bits.clr_dpth = 0; //div4 = 1 (bypass_clrdpth = 0)
-+ //00: 2 01: 2.5 10: 3 11: 4
-+ phy_base->pll_ctl0.bits.n_cntrl = 1; //div
-+ phy_base->pll_ctl0.bits.div2_ckbit = 0; //div1 = n+1
-+ phy_base->pll_ctl0.bits.div2_cktmds = 0; //div2 = n+1
-+ phy_base->pll_ctl0.bits.bcr = 0; //div3 0: [1:10] 1: [1:40]
-+ phy_base->pll_ctl1.bits.pwron = 1;
-+ phy_base->pll_ctl1.bits.reset = 0;
-+
-+ // configure phy
-+ /* config values taken from table */
-+ phy_base->phy_ctl1.dwval = ((phy_base->phy_ctl1.dwval & 0xFFC0FFFF) | /* config->phy_ctl1 */ 0x0);
-+ phy_base->phy_ctl2.dwval = ((phy_base->phy_ctl2.dwval & 0xFF000000) | /* config->phy_ctl2 */ 0x0);
-+ phy_base->phy_ctl3.dwval = ((phy_base->phy_ctl3.dwval & 0xFFFF0000) | /* config->phy_ctl3 */ 0xFFFF);
-+ phy_base->phy_ctl4.dwval = ((phy_base->phy_ctl4.dwval & 0xE0000000) | /* config->phy_ctl4 */ 0xC0D0D0D);
-+ //phy_base->pll_ctl0.dwval |= config->pll_ctl0;
-+ //phy_base->pll_ctl1.dwval |= config->pll_ctl1;
-+
-+ // phy_set_clk
-+ phy_base->phy_ctl6.bits.switch_clkch_data_corresponding = 0;
-+ phy_base->phy_ctl6.bits.clk_greate0_340m = 0x3FF;
-+ phy_base->phy_ctl6.bits.clk_greate1_340m = 0x3FF;
-+ phy_base->phy_ctl6.bits.clk_greate2_340m = 0x0;
-+ phy_base->phy_ctl7.bits.clk_greate3_340m = 0x0;
-+ phy_base->phy_ctl7.bits.clk_low_340m = 0x3E0;
-+ phy_base->phy_ctl6.bits.en_ckdat = 1; //default value is 0
-+
-+ // phy_base->phy_ctl2.bits.reg_resdi = 0x18;
-+ // phy_base->phy_ctl4.bits.reg_slv = 3; //low power voltage 1.08V, default value is 3
-+
-+ phy_base->phy_ctl1.bits.res_scktmds = 0; //
-+ phy_base->phy_ctl0.bits.reg_csmps = 2;
-+ phy_base->phy_ctl0.bits.reg_ck_test_sel = 0; //?
-+ phy_base->phy_ctl0.bits.reg_ck_sel = 1;
-+ phy_base->phy_indbg_ctrl.bits.txdata_debugmode = 0;
-+
-+ // phy_enable
-+ ret = sun20i_d1_hdmi_phy_enable(phy_base);
-+ if (ret)
-+ return ret;
-+
-+ phy_base->phy_ctl0.bits.sda_en = 1;
-+ phy_base->phy_ctl0.bits.scl_en = 1;
-+ phy_base->phy_ctl0.bits.hpd_en = 1;
-+ phy_base->phy_ctl0.bits.reg_den = 0xF;
-+ phy_base->pll_ctl0.bits.envbs = 1;
-
- return 0;
- }
-@@ -720,6 +875,7 @@ static int sun8i_hdmi_phy_probe(struct p
- return dev_err_probe(dev, PTR_ERR(regs),
- "Couldn't map the HDMI PHY registers\n");
-
-+ phy->base = regs;
- phy->regs = devm_regmap_init_mmio(dev, regs,
- &sun8i_hdmi_phy_regmap_config);
- if (IS_ERR(phy->regs))
+++ /dev/null
-From 02a412de18479449c87ed7a332e3fe33d2eff3a4 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 27 Apr 2022 18:47:53 -0500
-Subject: [PATCH 010/117] riscv: mm: Use IOMMU for DMA when available
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/mm/dma-noncoherent.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/arch/riscv/mm/dma-noncoherent.c
-+++ b/arch/riscv/mm/dma-noncoherent.c
-@@ -7,6 +7,7 @@
-
- #include <linux/dma-direct.h>
- #include <linux/dma-map-ops.h>
-+#include <linux/iommu.h>
- #include <linux/mm.h>
- #include <asm/cacheflush.h>
-
-@@ -70,6 +71,9 @@ void arch_setup_dma_ops(struct device *d
- dev_driver_string(dev), dev_name(dev));
-
- dev->dma_coherent = coherent;
-+
-+ if (iommu)
-+ iommu_setup_dma_ops(dev, dma_base, dma_base + size - 1);
- }
-
- void riscv_noncoherent_supported(void)
+++ /dev/null
-From ee6459d60f24d91052f0288155f44e6a7f991050 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 7 May 2022 18:34:25 -0500
-Subject: [PATCH 011/117] genirq: Add support for oneshot-safe threaded EOIs
-
-irqchips can use the combination of flags IRQCHIP_ONESHOT_SAFE |
-IRQCHIP_EOI_THREADED to elide mask operations.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- kernel/irq/chip.c | 36 +++++++++++++++++-------------------
- kernel/irq/internals.h | 2 +-
- kernel/irq/manage.c | 12 ++++++------
- 3 files changed, 24 insertions(+), 26 deletions(-)
-
---- a/kernel/irq/chip.c
-+++ b/kernel/irq/chip.c
-@@ -439,16 +439,6 @@ void unmask_irq(struct irq_desc *desc)
- }
- }
-
--void unmask_threaded_irq(struct irq_desc *desc)
--{
-- struct irq_chip *chip = desc->irq_data.chip;
--
-- if (chip->flags & IRQCHIP_EOI_THREADED)
-- chip->irq_eoi(&desc->irq_data);
--
-- unmask_irq(desc);
--}
--
- /*
- * handle_nested_irq - Handle a nested irq from a irq thread
- * @irq: the interrupt number
-@@ -656,25 +646,33 @@ out_unlock:
- }
- EXPORT_SYMBOL_GPL(handle_level_irq);
-
--static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
-+void unmask_eoi_threaded_irq(struct irq_desc *desc)
- {
-- if (!(desc->istate & IRQS_ONESHOT)) {
-+ struct irq_chip *chip = desc->irq_data.chip;
-+
-+ if (desc->istate & IRQS_ONESHOT)
-+ unmask_irq(desc);
-+
-+ if (chip->flags & IRQCHIP_EOI_THREADED)
- chip->irq_eoi(&desc->irq_data);
-+}
-+
-+static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
-+{
-+ /* Do not send EOI if the thread will do it for us. */
-+ if ((chip->flags & IRQCHIP_EOI_THREADED) && desc->threads_oneshot)
- return;
-- }
-+
- /*
- * We need to unmask in the following cases:
- * - Oneshot irq which did not wake the thread (caused by a
- * spurious interrupt or a primary handler handling it
- * completely).
- */
-- if (!irqd_irq_disabled(&desc->irq_data) &&
-- irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
-- chip->irq_eoi(&desc->irq_data);
-+ if ((desc->istate & IRQS_ONESHOT) && !desc->threads_oneshot)
- unmask_irq(desc);
-- } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
-- chip->irq_eoi(&desc->irq_data);
-- }
-+
-+ chip->irq_eoi(&desc->irq_data);
- }
-
- /**
---- a/kernel/irq/internals.h
-+++ b/kernel/irq/internals.h
-@@ -93,7 +93,7 @@ extern void irq_percpu_enable(struct irq
- extern void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu);
- extern void mask_irq(struct irq_desc *desc);
- extern void unmask_irq(struct irq_desc *desc);
--extern void unmask_threaded_irq(struct irq_desc *desc);
-+extern void unmask_eoi_threaded_irq(struct irq_desc *desc);
-
- #ifdef CONFIG_SPARSE_IRQ
- static inline void irq_mark_irq(unsigned int irq) { }
---- a/kernel/irq/manage.c
-+++ b/kernel/irq/manage.c
-@@ -1074,9 +1074,9 @@ static int irq_wait_for_interrupt(struct
- static void irq_finalize_oneshot(struct irq_desc *desc,
- struct irqaction *action)
- {
-- if (!(desc->istate & IRQS_ONESHOT) ||
-- action->handler == irq_forced_secondary_handler)
-+ if (action->handler == irq_forced_secondary_handler)
- return;
-+
- again:
- chip_bus_lock(desc);
- raw_spin_lock_irq(&desc->lock);
-@@ -1112,9 +1112,8 @@ again:
-
- desc->threads_oneshot &= ~action->thread_mask;
-
-- if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) &&
-- irqd_irq_masked(&desc->irq_data))
-- unmask_threaded_irq(desc);
-+ if (!desc->threads_oneshot)
-+ unmask_eoi_threaded_irq(desc);
-
- out_unlock:
- raw_spin_unlock_irq(&desc->lock);
-@@ -1662,7 +1661,8 @@ __setup_irq(unsigned int irq, struct irq
- * !ONESHOT irqs the thread mask is 0 so we can avoid a
- * conditional in irq_wake_thread().
- */
-- if (new->flags & IRQF_ONESHOT) {
-+ if ((new->flags & IRQF_ONESHOT) ||
-+ (desc->irq_data.chip->flags & (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) == (IRQCHIP_ONESHOT_SAFE | IRQCHIP_EOI_THREADED)) {
- /*
- * Unlikely to have 32 resp 64 irqs sharing one line,
- * but who knows.
+++ /dev/null
-From 1fbe96ec05c41b313b4e7cc4b39b191b4a3f7540 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 7 May 2022 18:38:34 -0500
-Subject: [PATCH 012/117] irqchip/sifive-plic: Enable oneshot-safe threaded
- EOIs
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/irqchip/irq-sifive-plic.c | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
---- a/drivers/irqchip/irq-sifive-plic.c
-+++ b/drivers/irqchip/irq-sifive-plic.c
-@@ -207,7 +207,9 @@ static struct irq_chip plic_chip = {
- .irq_set_affinity = plic_set_affinity,
- #endif
- .irq_set_type = plic_irq_set_type,
-- .flags = IRQCHIP_AFFINITY_PRE_STARTUP,
-+ .flags = IRQCHIP_ONESHOT_SAFE |
-+ IRQCHIP_EOI_THREADED |
-+ IRQCHIP_AFFINITY_PRE_STARTUP,
- };
-
- static int plic_irq_set_type(struct irq_data *d, unsigned int type)
+++ /dev/null
-From d6cf6473b0aaec455e48bccefe318a98a87b789f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 28 May 2022 19:04:56 -0500
-Subject: [PATCH 013/117] irqchip/sifive-plic: Support wake IRQs
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/irqchip/irq-sifive-plic.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
---- a/drivers/irqchip/irq-sifive-plic.c
-+++ b/drivers/irqchip/irq-sifive-plic.c
-@@ -193,7 +193,8 @@ static struct irq_chip plic_edge_chip =
- .irq_set_affinity = plic_set_affinity,
- #endif
- .irq_set_type = plic_irq_set_type,
-- .flags = IRQCHIP_AFFINITY_PRE_STARTUP,
-+ .flags = IRQCHIP_SKIP_SET_WAKE |
-+ IRQCHIP_AFFINITY_PRE_STARTUP,
- };
-
- static struct irq_chip plic_chip = {
-@@ -207,7 +208,8 @@ static struct irq_chip plic_chip = {
- .irq_set_affinity = plic_set_affinity,
- #endif
- .irq_set_type = plic_irq_set_type,
-- .flags = IRQCHIP_ONESHOT_SAFE |
-+ .flags = IRQCHIP_SKIP_SET_WAKE |
-+ IRQCHIP_ONESHOT_SAFE |
- IRQCHIP_EOI_THREADED |
- IRQCHIP_AFFINITY_PRE_STARTUP,
- };
+++ /dev/null
-From 0e871e791a2530562851109346affa1c0d9987e0 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:15:56 -0500
-Subject: [PATCH 014/117] mmc: sunxi-mmc: Correct the maximum segment size
-
-According to the DMA descriptor documentation, the lowest two bits of
-the size field are ignored, so the size must be rounded up to a multiple
-of 4 bytes. Furthermore, 0 is not a valid buffer size; setting the size
-to 0 will cause that DMA descriptor to be ignored.
-
-Together, these restrictions limit the maximum DMA segment size to 4
-less than the power-of-two width of the size field.
-
-Series-to: Ulf Hansson <ulf.hansson@linaro.org>
-Series-to: linux-mmc@vger.kernel.org
-
-Fixes: 3cbcb16095f9 ("mmc: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs")
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/mmc/host/sunxi-mmc.c | 14 ++++++++------
- 1 file changed, 8 insertions(+), 6 deletions(-)
-
---- a/drivers/mmc/host/sunxi-mmc.c
-+++ b/drivers/mmc/host/sunxi-mmc.c
-@@ -214,6 +214,9 @@
- #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
- #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
-
-+/* Buffer size must be a multiple of 4 bytes. */
-+#define SDXC_IDMAC_SIZE_ALIGN 4
-+
- #define SDXC_CLK_400K 0
- #define SDXC_CLK_25M 1
- #define SDXC_CLK_50M 2
-@@ -361,17 +364,15 @@ static void sunxi_mmc_init_idma_des(stru
- {
- struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
- dma_addr_t next_desc = host->sg_dma;
-- int i, max_len = (1 << host->cfg->idma_des_size_bits);
-+ int i;
-
- for (i = 0; i < data->sg_len; i++) {
- pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH |
- SDXC_IDMAC_DES0_OWN |
- SDXC_IDMAC_DES0_DIC);
-
-- if (data->sg[i].length == max_len)
-- pdes[i].buf_size = 0; /* 0 == max_len */
-- else
-- pdes[i].buf_size = cpu_to_le32(data->sg[i].length);
-+ pdes[i].buf_size = cpu_to_le32(ALIGN(data->sg[i].length,
-+ SDXC_IDMAC_SIZE_ALIGN));
-
- next_desc += sizeof(struct sunxi_idma_des);
- pdes[i].buf_addr_ptr1 =
-@@ -1421,7 +1422,8 @@ static int sunxi_mmc_probe(struct platfo
- mmc->max_blk_count = 8192;
- mmc->max_blk_size = 4096;
- mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
-- mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits);
-+ mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits) -
-+ SDXC_IDMAC_SIZE_ALIGN;
- mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
- /* 400kHz ~ 52MHz */
- mmc->f_min = 400000;
+++ /dev/null
-From a8e905fb3fd0d26f724646275b72a7363b2f03d8 Mon Sep 17 00:00:00 2001
-From: Max Fierke <max@maxfierke.com>
-Date: Wed, 1 Jun 2022 00:17:47 -0500
-Subject: [PATCH 015/117] dt-bindings: display: Add bindings for ClockworkPi
- CWD686
-
-The CWD686 is a 6.86" IPS LCD panel used as the primary
-display in the ClockworkPi DevTerm portable (all cores)
-
-Signed-off-by: Max Fierke <max@maxfierke.com>
-Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../display/panel/clockwork,cwd686.yaml | 62 +++++++++++++++++++
- 1 file changed, 62 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/display/panel/clockwork,cwd686.yaml
-@@ -0,0 +1,62 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/display/panel/clockwork,cwd686.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Clockwork CWD686 6.86" IPS LCD panel
-+
-+maintainers:
-+ - Max Fierke <max@maxfierke.com>
-+
-+description: |
-+ The Clockwork CWD686 is a 6.86" ICNL9707-based IPS LCD panel used within the
-+ Clockwork DevTerm series of portable devices. The panel has a 480x1280
-+ resolution and uses 24 bit RGB per pixel.
-+
-+allOf:
-+ - $ref: panel-common.yaml#
-+
-+properties:
-+ compatible:
-+ const: clockwork,cwd686
-+
-+ reg:
-+ description: DSI virtual channel used by that screen
-+ maxItems: 1
-+
-+ reset-gpios: true
-+ rotation: true
-+ backlight: true
-+ iovcc-supply: true
-+ vci-supply: true
-+
-+required:
-+ - compatible
-+ - reg
-+ - backlight
-+ - reset-gpios
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ #include <dt-bindings/gpio/gpio.h>
-+
-+ backlight: backlight {
-+ compatible = "gpio-backlight";
-+ gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
-+ };
-+
-+ dsi {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ panel@0 {
-+ compatible = "clockwork,cwd686";
-+ reg = <0>;
-+ backlight = <&backlight>;
-+ reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
-+ rotation = <90>;
-+ };
-+ };
+++ /dev/null
-From d290546a88694dde6d2f64a973cd62ff2c69e27e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 12 Aug 2022 01:59:35 -0500
-Subject: [PATCH 016/117] dt-bindings: display: Add Sitronix ST7701s panel
- binding
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../display/panel/sitronix,st7701s.yaml | 32 +++++++++++++++++++
- 1 file changed, 32 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/display/panel/sitronix,st7701s.yaml
-@@ -0,0 +1,32 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/display/panel/sitronix,st7701s.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Sitronix ST7701 based LCD panels
-+
-+maintainers:
-+ - Samuel Holland <samuel@sholland.org>
-+
-+description: |
-+ Panel used on Lichee RV 86 Panel
-+
-+allOf:
-+ - $ref: panel-common.yaml#
-+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
-+
-+properties:
-+ compatible:
-+ items:
-+ - const: sitronix,st7701s
-+
-+ backlight: true
-+
-+ reset-gpios: true
-+
-+required:
-+ - compatible
-+ - reset-gpios
-+
-+unevaluatedProperties: false
+++ /dev/null
-From 9d9b8bd567c30a821c82c27035243536c5234542 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 29 Mar 2022 22:47:57 -0500
-Subject: [PATCH 017/117] drm/panel: Add driver for ST7701s DPI LCD panel
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/Kconfig | 8 +
- drivers/gpu/drm/panel/Makefile | 1 +
- .../gpu/drm/panel/panel-sitronix-st7701s.c | 444 ++++++++++++++++++
- 3 files changed, 453 insertions(+)
- create mode 100644 drivers/gpu/drm/panel/panel-sitronix-st7701s.c
-
---- a/drivers/gpu/drm/panel/Kconfig
-+++ b/drivers/gpu/drm/panel/Kconfig
-@@ -608,6 +608,14 @@ config DRM_PANEL_SITRONIX_ST7701
- ST7701 controller for 480X864 LCD panels with MIPI/RGB/SPI
- system interfaces.
-
-+config DRM_PANEL_SITRONIX_ST7701S
-+ tristate "Sitronix ST7701s panel driver"
-+ depends on OF
-+ depends on BACKLIGHT_CLASS_DEVICE
-+ help
-+ Say Y here if you want to enable support for the Sitronix
-+ ST7701s controller with a SPI interface.
-+
- config DRM_PANEL_SITRONIX_ST7703
- tristate "Sitronix ST7703 based MIPI touchscreen panels"
- depends on OF
---- a/drivers/gpu/drm/panel/Makefile
-+++ b/drivers/gpu/drm/panel/Makefile
-@@ -61,6 +61,7 @@ obj-$(CONFIG_DRM_PANEL_SHARP_LS037V7DW01
- obj-$(CONFIG_DRM_PANEL_SHARP_LS043T1LE01) += panel-sharp-ls043t1le01.o
- obj-$(CONFIG_DRM_PANEL_SHARP_LS060T1SX01) += panel-sharp-ls060t1sx01.o
- obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701) += panel-sitronix-st7701.o
-+obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7701S) += panel-sitronix-st7701s.o
- obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7703) += panel-sitronix-st7703.o
- obj-$(CONFIG_DRM_PANEL_SITRONIX_ST7789V) += panel-sitronix-st7789v.o
- obj-$(CONFIG_DRM_PANEL_SONY_ACX565AKM) += panel-sony-acx565akm.o
---- /dev/null
-+++ b/drivers/gpu/drm/panel/panel-sitronix-st7701s.c
-@@ -0,0 +1,444 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Copyright (C) 2017 Free Electrons
-+ */
-+
-+#include <linux/delay.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/module.h>
-+#include <linux/spi/spi.h>
-+
-+#include <video/mipi_display.h>
-+
-+#include <drm/drm_device.h>
-+#include <drm/drm_modes.h>
-+#include <drm/drm_panel.h>
-+
-+struct st7701s {
-+ struct drm_panel panel;
-+ struct gpio_desc *reset;
-+ struct spi_device *spi;
-+};
-+
-+enum {
-+ ST7789V_COMMAND = 0 << 8,
-+ ST7789V_DATA = 1 << 8,
-+};
-+
-+#define LCD_WRITE_COMMAND(x) (ST7789V_COMMAND | (x))
-+#define LCD_WRITE_DATA(x) (ST7789V_DATA | (x))
-+
-+static const u16 st7701s_init_sequence_1[] = {
-+ LCD_WRITE_COMMAND(0xFF),
-+ LCD_WRITE_DATA(0x77),
-+ LCD_WRITE_DATA(0x01),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x10),
-+
-+ LCD_WRITE_COMMAND(0xC0),
-+ LCD_WRITE_DATA(0x3B),
-+ LCD_WRITE_DATA(0x00),
-+
-+ LCD_WRITE_COMMAND(0xC1),
-+ LCD_WRITE_DATA(0x0D),
-+ LCD_WRITE_DATA(0x02),
-+
-+ LCD_WRITE_COMMAND(0xC2),
-+ LCD_WRITE_DATA(0x21),
-+ LCD_WRITE_DATA(0x08),
-+
-+ // RGB Interface Setting
-+ // LCD_WRITE_COMMAND(0xC3),
-+ // LCD_WRITE_DATA(0x02),
-+
-+ LCD_WRITE_COMMAND(0xCD),
-+ LCD_WRITE_DATA(0x18),//0F 08-OK D0-D18
-+
-+ LCD_WRITE_COMMAND(0xB0),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x11),
-+ LCD_WRITE_DATA(0x18),
-+ LCD_WRITE_DATA(0x0E),
-+ LCD_WRITE_DATA(0x11),
-+ LCD_WRITE_DATA(0x06),
-+ LCD_WRITE_DATA(0x07),
-+ LCD_WRITE_DATA(0x08),
-+ LCD_WRITE_DATA(0x07),
-+ LCD_WRITE_DATA(0x22),
-+ LCD_WRITE_DATA(0x04),
-+ LCD_WRITE_DATA(0x12),
-+ LCD_WRITE_DATA(0x0F),
-+ LCD_WRITE_DATA(0xAA),
-+ LCD_WRITE_DATA(0x31),
-+ LCD_WRITE_DATA(0x18),
-+
-+ LCD_WRITE_COMMAND(0xB1),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x11),
-+ LCD_WRITE_DATA(0x19),
-+ LCD_WRITE_DATA(0x0E),
-+ LCD_WRITE_DATA(0x12),
-+ LCD_WRITE_DATA(0x07),
-+ LCD_WRITE_DATA(0x08),
-+ LCD_WRITE_DATA(0x08),
-+ LCD_WRITE_DATA(0x08),
-+ LCD_WRITE_DATA(0x22),
-+ LCD_WRITE_DATA(0x04),
-+ LCD_WRITE_DATA(0x11),
-+ LCD_WRITE_DATA(0x11),
-+ LCD_WRITE_DATA(0xA9),
-+ LCD_WRITE_DATA(0x32),
-+ LCD_WRITE_DATA(0x18),
-+
-+ LCD_WRITE_COMMAND(0xFF),
-+ LCD_WRITE_DATA(0x77),
-+ LCD_WRITE_DATA(0x01),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x11),
-+
-+ LCD_WRITE_COMMAND(0xB0),
-+ LCD_WRITE_DATA(0x60),
-+
-+ LCD_WRITE_COMMAND(0xB1),
-+ LCD_WRITE_DATA(0x30),
-+
-+ LCD_WRITE_COMMAND(0xB2),
-+ LCD_WRITE_DATA(0x87),
-+
-+ LCD_WRITE_COMMAND(0xB3),
-+ LCD_WRITE_DATA(0x80),
-+
-+ LCD_WRITE_COMMAND(0xB5),
-+ LCD_WRITE_DATA(0x49),
-+
-+ LCD_WRITE_COMMAND(0xB7),
-+ LCD_WRITE_DATA(0x85),
-+
-+ LCD_WRITE_COMMAND(0xB8),
-+ LCD_WRITE_DATA(0x21),
-+
-+ LCD_WRITE_COMMAND(0xC1),
-+ LCD_WRITE_DATA(0x78),
-+
-+ LCD_WRITE_COMMAND(0xC2),
-+ LCD_WRITE_DATA(0x78),
-+};
-+
-+static const u16 st7701s_init_sequence_2[] = {
-+ LCD_WRITE_COMMAND(0xE0),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x1B),
-+ LCD_WRITE_DATA(0x02),
-+
-+ LCD_WRITE_COMMAND(0xE1),
-+ LCD_WRITE_DATA(0x08),
-+ LCD_WRITE_DATA(0xA0),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x07),
-+ LCD_WRITE_DATA(0xA0),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x44),
-+ LCD_WRITE_DATA(0x44),
-+
-+ LCD_WRITE_COMMAND(0xE2),
-+ LCD_WRITE_DATA(0x11),
-+ LCD_WRITE_DATA(0x11),
-+ LCD_WRITE_DATA(0x44),
-+ LCD_WRITE_DATA(0x44),
-+ LCD_WRITE_DATA(0xED),
-+ LCD_WRITE_DATA(0xA0),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0xEC),
-+ LCD_WRITE_DATA(0xA0),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x00),
-+
-+ LCD_WRITE_COMMAND(0xE3),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x11),
-+ LCD_WRITE_DATA(0x11),
-+
-+ LCD_WRITE_COMMAND(0xE4),
-+ LCD_WRITE_DATA(0x44),
-+ LCD_WRITE_DATA(0x44),
-+
-+ LCD_WRITE_COMMAND(0xE5),
-+ LCD_WRITE_DATA(0x0A),
-+ LCD_WRITE_DATA(0xE9),
-+ LCD_WRITE_DATA(0xD8),
-+ LCD_WRITE_DATA(0xA0),
-+ LCD_WRITE_DATA(0x0C),
-+ LCD_WRITE_DATA(0xEB),
-+ LCD_WRITE_DATA(0xD8),
-+ LCD_WRITE_DATA(0xA0),
-+ LCD_WRITE_DATA(0x0E),
-+ LCD_WRITE_DATA(0xED),
-+ LCD_WRITE_DATA(0xD8),
-+ LCD_WRITE_DATA(0xA0),
-+ LCD_WRITE_DATA(0x10),
-+ LCD_WRITE_DATA(0xEF),
-+ LCD_WRITE_DATA(0xD8),
-+ LCD_WRITE_DATA(0xA0),
-+
-+ LCD_WRITE_COMMAND(0xE6),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x11),
-+ LCD_WRITE_DATA(0x11),
-+
-+ LCD_WRITE_COMMAND(0xE7),
-+ LCD_WRITE_DATA(0x44),
-+ LCD_WRITE_DATA(0x44),
-+
-+ LCD_WRITE_COMMAND(0xE8),
-+ LCD_WRITE_DATA(0x09),
-+ LCD_WRITE_DATA(0xE8),
-+ LCD_WRITE_DATA(0xD8),
-+ LCD_WRITE_DATA(0xA0),
-+ LCD_WRITE_DATA(0x0B),
-+ LCD_WRITE_DATA(0xEA),
-+ LCD_WRITE_DATA(0xD8),
-+ LCD_WRITE_DATA(0xA0),
-+ LCD_WRITE_DATA(0x0D),
-+ LCD_WRITE_DATA(0xEC),
-+ LCD_WRITE_DATA(0xD8),
-+ LCD_WRITE_DATA(0xA0),
-+ LCD_WRITE_DATA(0x0F),
-+ LCD_WRITE_DATA(0xEE),
-+ LCD_WRITE_DATA(0xD8),
-+ LCD_WRITE_DATA(0xA0),
-+
-+ LCD_WRITE_COMMAND(0xEB),
-+ LCD_WRITE_DATA(0x02),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0xE4),
-+ LCD_WRITE_DATA(0xE4),
-+ LCD_WRITE_DATA(0x88),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x40),
-+
-+ LCD_WRITE_COMMAND(0xEC),
-+ LCD_WRITE_DATA(0x3C),
-+ LCD_WRITE_DATA(0x00),
-+
-+ LCD_WRITE_COMMAND(0xED),
-+ LCD_WRITE_DATA(0xAB),
-+ LCD_WRITE_DATA(0x89),
-+ LCD_WRITE_DATA(0x76),
-+ LCD_WRITE_DATA(0x54),
-+ LCD_WRITE_DATA(0x02),
-+ LCD_WRITE_DATA(0xFF),
-+ LCD_WRITE_DATA(0xFF),
-+ LCD_WRITE_DATA(0xFF),
-+ LCD_WRITE_DATA(0xFF),
-+ LCD_WRITE_DATA(0xFF),
-+ LCD_WRITE_DATA(0xFF),
-+ LCD_WRITE_DATA(0x20),
-+ LCD_WRITE_DATA(0x45),
-+ LCD_WRITE_DATA(0x67),
-+ LCD_WRITE_DATA(0x98),
-+ LCD_WRITE_DATA(0xBA),
-+
-+ LCD_WRITE_COMMAND(0xFF),
-+ LCD_WRITE_DATA(0x77),
-+ LCD_WRITE_DATA(0x01),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x00),
-+ LCD_WRITE_DATA(0x00),
-+
-+ LCD_WRITE_COMMAND(MIPI_DCS_SET_PIXEL_FORMAT),
-+ LCD_WRITE_DATA(0x66),
-+
-+ LCD_WRITE_COMMAND(MIPI_DCS_SET_ADDRESS_MODE),
-+ LCD_WRITE_DATA(0x00),
-+
-+ LCD_WRITE_COMMAND(MIPI_DCS_ENTER_INVERT_MODE),
-+
-+ LCD_WRITE_COMMAND(MIPI_DCS_EXIT_SLEEP_MODE),
-+};
-+
-+static const u16 st7701s_enable_sequence[] = {
-+ LCD_WRITE_COMMAND(MIPI_DCS_SET_DISPLAY_ON),
-+};
-+
-+static const u16 st7701s_disable_sequence[] = {
-+ LCD_WRITE_COMMAND(MIPI_DCS_SET_DISPLAY_OFF),
-+};
-+
-+static inline struct st7701s *panel_to_st7701s(struct drm_panel *panel)
-+{
-+ return container_of(panel, struct st7701s, panel);
-+}
-+
-+static int st7701s_spi_write(struct st7701s *ctx, const u16 *data, size_t size)
-+{
-+ struct spi_transfer xfer = { };
-+ struct spi_message msg;
-+
-+ spi_message_init(&msg);
-+
-+ xfer.tx_buf = data;
-+ xfer.bits_per_word = 9;
-+ xfer.len = size;
-+
-+ spi_message_add_tail(&xfer, &msg);
-+ return spi_sync(ctx->spi, &msg);
-+}
-+
-+static const struct drm_display_mode default_mode = {
-+ .clock = 19800,
-+ .hdisplay = 480,
-+ .hsync_start = 480 + 60,
-+ .hsync_end = 480 + 60 + 12,
-+ .htotal = 480 + 60 + 12 + 60,
-+ .vdisplay = 480,
-+ .vsync_start = 480 + 18,
-+ .vsync_end = 480 + 18 + 4,
-+ .vtotal = 480 + 18 + 4 + 18,
-+};
-+
-+static int st7701s_get_modes(struct drm_panel *panel,
-+ struct drm_connector *connector)
-+{
-+ struct drm_display_mode *mode;
-+
-+ mode = drm_mode_duplicate(connector->dev, &default_mode);
-+ if (!mode)
-+ return -ENOMEM;
-+
-+ drm_mode_set_name(mode);
-+
-+ mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-+ drm_mode_probed_add(connector, mode);
-+
-+ connector->display_info.width_mm = 70;
-+ connector->display_info.height_mm = 72;
-+
-+ return 1;
-+}
-+
-+static int st7701s_prepare(struct drm_panel *panel)
-+{
-+ struct st7701s *ctx = panel_to_st7701s(panel);
-+
-+ gpiod_set_value_cansleep(ctx->reset, 1);
-+ msleep(20);
-+
-+ gpiod_set_value_cansleep(ctx->reset, 0);
-+ msleep(20);
-+
-+ st7701s_spi_write(ctx, st7701s_init_sequence_1,
-+ sizeof(st7701s_init_sequence_1));
-+ msleep(20);
-+
-+ st7701s_spi_write(ctx, st7701s_init_sequence_2,
-+ sizeof(st7701s_init_sequence_2));
-+ msleep(120);
-+
-+ return 0;
-+}
-+
-+static int st7701s_enable(struct drm_panel *panel)
-+{
-+ struct st7701s *ctx = panel_to_st7701s(panel);
-+
-+ st7701s_spi_write(ctx, st7701s_enable_sequence,
-+ sizeof(st7701s_enable_sequence));
-+ msleep(20);
-+
-+ return 0;
-+}
-+
-+static int st7701s_disable(struct drm_panel *panel)
-+{
-+ struct st7701s *ctx = panel_to_st7701s(panel);
-+
-+ st7701s_spi_write(ctx, st7701s_disable_sequence,
-+ sizeof(st7701s_disable_sequence));
-+
-+ return 0;
-+}
-+
-+static int st7701s_unprepare(struct drm_panel *panel)
-+{
-+ return 0;
-+}
-+
-+static const struct drm_panel_funcs st7701s_drm_funcs = {
-+ .disable = st7701s_disable,
-+ .enable = st7701s_enable,
-+ .get_modes = st7701s_get_modes,
-+ .prepare = st7701s_prepare,
-+ .unprepare = st7701s_unprepare,
-+};
-+
-+static int st7701s_probe(struct spi_device *spi)
-+{
-+ struct device *dev = &spi->dev;
-+ struct st7701s *ctx;
-+ int ret;
-+
-+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
-+ if (!ctx)
-+ return -ENOMEM;
-+
-+ spi_set_drvdata(spi, ctx);
-+ ctx->spi = spi;
-+
-+ ctx->reset = devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_LOW);
-+ if (IS_ERR(ctx->reset)) {
-+ dev_err(&spi->dev, "Couldn't get our reset line\n");
-+ return PTR_ERR(ctx->reset);
-+ }
-+
-+ drm_panel_init(&ctx->panel, dev, &st7701s_drm_funcs,
-+ DRM_MODE_CONNECTOR_DPI);
-+
-+ ret = drm_panel_of_backlight(&ctx->panel);
-+ if (ret)
-+ return ret;
-+
-+ drm_panel_add(&ctx->panel);
-+
-+ return 0;
-+}
-+
-+static void st7701s_remove(struct spi_device *spi)
-+{
-+ struct st7701s *ctx = spi_get_drvdata(spi);
-+
-+ drm_panel_remove(&ctx->panel);
-+}
-+
-+static const struct of_device_id st7701s_of_match[] = {
-+ { .compatible = "sitronix,st7701s" },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, st7701s_of_match);
-+
-+static const struct spi_device_id st7701s_ids[] = {
-+ { "st7701s" },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(spi, st7701s_ids);
-+
-+static struct spi_driver st7701s_driver = {
-+ .probe = st7701s_probe,
-+ .remove = st7701s_remove,
-+ .driver = {
-+ .name = "st7701s",
-+ .of_match_table = st7701s_of_match,
-+ },
-+};
-+module_spi_driver(st7701s_driver);
-+
-+MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
-+MODULE_DESCRIPTION("Sitronix ST7701s LCD Driver");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From db71abf941d25b92b2117780d3771197417d1c81 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 31 Jul 2022 20:34:20 -0500
-Subject: [PATCH 018/117] nvmem: sunxi_sid: Drop the workaround on A64
-
-Now that the SRAM readout code is fixed by using 32-bit accesses, it
-always returns the same values as register readout, so the A64 variant
-no longer needs the workaround. This makes the D1 variant structure
-redundant, so remove it.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/nvmem/sunxi_sid.c | 8 +-------
- 1 file changed, 1 insertion(+), 7 deletions(-)
-
---- a/drivers/nvmem/sunxi_sid.c
-+++ b/drivers/nvmem/sunxi_sid.c
-@@ -196,15 +196,9 @@ static const struct sunxi_sid_cfg sun8i_
- .need_register_readout = true,
- };
-
--static const struct sunxi_sid_cfg sun20i_d1_cfg = {
-- .value_offset = 0x200,
-- .size = 0x100,
--};
--
- static const struct sunxi_sid_cfg sun50i_a64_cfg = {
- .value_offset = 0x200,
- .size = 0x100,
-- .need_register_readout = true,
- };
-
- static const struct sunxi_sid_cfg sun50i_h6_cfg = {
-@@ -217,7 +211,7 @@ static const struct of_device_id sunxi_s
- { .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg },
- { .compatible = "allwinner,sun8i-a83t-sid", .data = &sun50i_a64_cfg },
- { .compatible = "allwinner,sun8i-h3-sid", .data = &sun8i_h3_cfg },
-- { .compatible = "allwinner,sun20i-d1-sid", .data = &sun20i_d1_cfg },
-+ { .compatible = "allwinner,sun20i-d1-sid", .data = &sun50i_a64_cfg },
- { .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg },
- { .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg },
- { .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg },
+++ /dev/null
-From d03341ef7acb64803ade6b173d24f49ffa6149a3 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 2 Aug 2022 00:29:32 -0500
-Subject: [PATCH 019/117] dt-bindings: nvmem: Allow bit offsets greater than a
- byte
-
-Some NVMEM devices contain cells which do not start at a multiple of the
-device's stride. However, the "reg" property of a cell must be aligned
-to its provider device's stride.
-
-These cells can be represented in the DT using the "bits" property if
-that property allows offsets up to the full stride. 63 is chosen
-assuming that NVMEM devices will not have strides larger than 8 bytes.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- Documentation/devicetree/bindings/nvmem/nvmem.yaml | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/nvmem/nvmem.yaml
-+++ b/Documentation/devicetree/bindings/nvmem/nvmem.yaml
-@@ -53,7 +53,7 @@ patternProperties:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- items:
- - minimum: 0
-- maximum: 7
-+ maximum: 63
- description:
- Offset in bit within the address range specified by reg.
- - minimum: 1
+++ /dev/null
-From f666d95c1443854555044d3d4b52c463cf845ccc Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 17 Jul 2022 20:33:40 -0500
-Subject: [PATCH 020/117] regulator: dt-bindings: Add Allwinner D1 LDOs
-
-The Allwinner D1 SoC contains two pairs of in-package LDOs. One pair is
-for general purpose use. LDOA generally powers the board's 1.8 V rail.
-LDOB generally powers the in-package DRAM, where applicable.
-
-The other pair of LDOs powers the analog power domains inside the SoC,
-including the audio codec, thermal sensor, and ADCs. These LDOs require
-a 0.9 V bandgap voltage reference. The calibration value for the voltage
-reference is stored in an eFuse, accessed via an NVMEM cell.
-
-Neither LDO control register is in its own MMIO range; instead, each
-regulator device relies on a regmap/syscon exported by its parent.
-
-Series-changes: 2
- - Remove syscon property from bindings
- - Update binding examples to fix warnings and provide context
-
-Series-changes: 3
- - Add "reg" property to bindings
- - Add "unevaluatedProperties: true" to regulator nodes
- - Minor changes to regulator node name patterns
- - Remove system-ldos example (now added in patch 3)
-
-Series-changes: 4
- - Fix the order of the maintainer/description sections
- - Replace unevaluatedProperties with "additionalProperties: false"
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../allwinner,sun20i-d1-analog-ldos.yaml | 74 +++++++++++++++++++
- .../allwinner,sun20i-d1-system-ldos.yaml | 37 ++++++++++
- 2 files changed, 111 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-analog-ldos.yaml
- create mode 100644 Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-system-ldos.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-analog-ldos.yaml
-@@ -0,0 +1,74 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/regulator/allwinner,sun20i-d1-analog-ldos.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Allwinner D1 Analog LDOs
-+
-+maintainers:
-+ - Samuel Holland <samuel@sholland.org>
-+
-+description:
-+ Allwinner D1 contains a set of LDOs which are designed to supply analog power
-+ inside and outside the SoC. They are controlled by a register within the audio
-+ codec MMIO space, but which is not part of the audio codec clock/reset domain.
-+
-+properties:
-+ compatible:
-+ enum:
-+ - allwinner,sun20i-d1-analog-ldos
-+
-+ reg:
-+ maxItems: 1
-+
-+ nvmem-cells:
-+ items:
-+ - description: NVMEM cell for the calibrated bandgap reference trim value
-+
-+ nvmem-cell-names:
-+ items:
-+ - const: bg_trim
-+
-+patternProperties:
-+ "^(a|hp)ldo$":
-+ type: object
-+ $ref: regulator.yaml#
-+ unevaluatedProperties: false
-+
-+required:
-+ - compatible
-+ - reg
-+ - nvmem-cells
-+ - nvmem-cell-names
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ audio-codec@2030000 {
-+ compatible = "simple-mfd", "syscon";
-+ reg = <0x2030000 0x1000>;
-+ ranges;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ regulators@2030348 {
-+ compatible = "allwinner,sun20i-d1-analog-ldos";
-+ reg = <0x2030348 0x4>;
-+ nvmem-cells = <&bg_trim>;
-+ nvmem-cell-names = "bg_trim";
-+
-+ reg_aldo: aldo {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ };
-+
-+ reg_hpldo: hpldo {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ };
-+ };
-+ };
-+
-+...
---- /dev/null
-+++ b/Documentation/devicetree/bindings/regulator/allwinner,sun20i-d1-system-ldos.yaml
-@@ -0,0 +1,37 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/regulator/allwinner,sun20i-d1-system-ldos.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Allwinner D1 System LDOs
-+
-+maintainers:
-+ - Samuel Holland <samuel@sholland.org>
-+
-+description:
-+ Allwinner D1 contains a pair of general-purpose LDOs which are designed to
-+ supply power inside and outside the SoC. They are controlled by a register
-+ within the system control MMIO space.
-+
-+properties:
-+ compatible:
-+ enum:
-+ - allwinner,sun20i-d1-system-ldos
-+
-+ reg:
-+ maxItems: 1
-+
-+patternProperties:
-+ "^ldo[ab]$":
-+ type: object
-+ $ref: regulator.yaml#
-+ unevaluatedProperties: false
-+
-+required:
-+ - compatible
-+ - reg
-+
-+additionalProperties: false
-+
-+...
+++ /dev/null
-From ad842bfb2eb10a75050dd69145ca59de982eb0e9 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 17 Jul 2022 11:46:52 -0500
-Subject: [PATCH 021/117] regulator: sun20i: Add support for Allwinner D1 LDOs
-
-D1 contains two pairs of LDOs. Since they have similar bindings, and
-they always exist together, put them in a single driver.
-
-The analog LDOs are relatively boring, with a single linear range. Their
-one quirk is that a bandgap reference must be calibrated for them to
-produce the correct voltage.
-
-The system LDOs have the complication that their voltage step is not an
-integer, so a custom .list_voltage is needed to get the rounding right.
-
-Series-changes: 2
- - Use decimal numbers for .n_voltages instead of field widths
- - Get the regmap from the parent device instead of a property/phandle
-
-Series-changes: 3
- - Adjust control flow in sun20i_regulator_get_regmap() for clarity
-
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/regulator/Kconfig | 8 +
- drivers/regulator/Makefile | 1 +
- drivers/regulator/sun20i-regulator.c | 232 +++++++++++++++++++++++++++
- 3 files changed, 241 insertions(+)
- create mode 100644 drivers/regulator/sun20i-regulator.c
-
---- a/drivers/regulator/Kconfig
-+++ b/drivers/regulator/Kconfig
-@@ -1280,6 +1280,14 @@ config REGULATOR_STW481X_VMMC
- This driver supports the internal VMMC regulator in the STw481x
- PMIC chips.
-
-+config REGULATOR_SUN20I
-+ tristate "Allwinner D1 internal LDOs"
-+ depends on ARCH_SUNXI || COMPILE_TEST
-+ depends on MFD_SYSCON && NVMEM
-+ default ARCH_SUNXI
-+ help
-+ This driver supports the internal LDOs in the Allwinner D1 SoC.
-+
- config REGULATOR_SY7636A
- tristate "Silergy SY7636A voltage regulator"
- depends on MFD_SY7636A
---- a/drivers/regulator/Makefile
-+++ b/drivers/regulator/Makefile
-@@ -150,6 +150,7 @@ obj-$(CONFIG_REGULATOR_STM32_VREFBUF) +=
- obj-$(CONFIG_REGULATOR_STM32_PWR) += stm32-pwr.o
- obj-$(CONFIG_REGULATOR_STPMIC1) += stpmic1_regulator.o
- obj-$(CONFIG_REGULATOR_STW481X_VMMC) += stw481x-vmmc.o
-+obj-$(CONFIG_REGULATOR_SUN20I) += sun20i-regulator.o
- obj-$(CONFIG_REGULATOR_SY7636A) += sy7636a-regulator.o
- obj-$(CONFIG_REGULATOR_SY8106A) += sy8106a-regulator.o
- obj-$(CONFIG_REGULATOR_SY8824X) += sy8824x.o
---- /dev/null
-+++ b/drivers/regulator/sun20i-regulator.c
-@@ -0,0 +1,232 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+//
-+// Copyright (c) 2021-2022 Samuel Holland <samuel@sholland.org>
-+//
-+
-+#include <linux/mfd/syscon.h>
-+#include <linux/module.h>
-+#include <linux/nvmem-consumer.h>
-+#include <linux/of_device.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/regulator/driver.h>
-+
-+#define SUN20I_POWER_REG 0x348
-+
-+#define SUN20I_SYS_LDO_CTRL_REG 0x150
-+
-+struct sun20i_regulator_data {
-+ int (*init)(struct device *dev,
-+ struct regmap *regmap);
-+ const struct regulator_desc *descs;
-+ unsigned int ndescs;
-+};
-+
-+static int sun20i_d1_analog_ldos_init(struct device *dev, struct regmap *regmap)
-+{
-+ u8 bg_trim;
-+ int ret;
-+
-+ ret = nvmem_cell_read_u8(dev, "bg_trim", &bg_trim);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Failed to get bg_trim value\n");
-+
-+ /* The default value corresponds to 900 mV. */
-+ if (!bg_trim)
-+ bg_trim = 0x19;
-+
-+ return regmap_update_bits(regmap, SUN20I_POWER_REG,
-+ GENMASK(7, 0), bg_trim);
-+}
-+
-+static const struct regulator_ops sun20i_d1_analog_ldo_ops = {
-+ .list_voltage = regulator_list_voltage_linear,
-+ .map_voltage = regulator_map_voltage_linear,
-+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
-+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
-+ .enable = regulator_enable_regmap,
-+ .disable = regulator_disable_regmap,
-+ .is_enabled = regulator_is_enabled_regmap,
-+};
-+
-+static const struct regulator_desc sun20i_d1_analog_ldo_descs[] = {
-+ {
-+ .name = "aldo",
-+ .supply_name = "vdd33",
-+ .of_match = "aldo",
-+ .ops = &sun20i_d1_analog_ldo_ops,
-+ .type = REGULATOR_VOLTAGE,
-+ .owner = THIS_MODULE,
-+ .n_voltages = 8,
-+ .min_uV = 1650000,
-+ .uV_step = 50000,
-+ .vsel_reg = SUN20I_POWER_REG,
-+ .vsel_mask = GENMASK(14, 12),
-+ .enable_reg = SUN20I_POWER_REG,
-+ .enable_mask = BIT(31),
-+ },
-+ {
-+ .name = "hpldo",
-+ .supply_name = "hpldoin",
-+ .of_match = "hpldo",
-+ .ops = &sun20i_d1_analog_ldo_ops,
-+ .type = REGULATOR_VOLTAGE,
-+ .owner = THIS_MODULE,
-+ .n_voltages = 8,
-+ .min_uV = 1650000,
-+ .uV_step = 50000,
-+ .vsel_reg = SUN20I_POWER_REG,
-+ .vsel_mask = GENMASK(10, 8),
-+ .enable_reg = SUN20I_POWER_REG,
-+ .enable_mask = BIT(30),
-+ },
-+};
-+
-+static const struct sun20i_regulator_data sun20i_d1_analog_ldos = {
-+ .init = sun20i_d1_analog_ldos_init,
-+ .descs = sun20i_d1_analog_ldo_descs,
-+ .ndescs = ARRAY_SIZE(sun20i_d1_analog_ldo_descs),
-+};
-+
-+/* regulator_list_voltage_linear() modified for the non-integral uV_step. */
-+static int sun20i_d1_system_ldo_list_voltage(struct regulator_dev *rdev,
-+ unsigned int selector)
-+{
-+ const struct regulator_desc *desc = rdev->desc;
-+ unsigned int uV;
-+
-+ if (selector >= desc->n_voltages)
-+ return -EINVAL;
-+
-+ uV = desc->min_uV + (desc->uV_step * selector);
-+
-+ /* Produce correctly-rounded absolute voltages. */
-+ return uV + ((selector + 1 + (desc->min_uV % 4)) / 3);
-+}
-+
-+static const struct regulator_ops sun20i_d1_system_ldo_ops = {
-+ .list_voltage = sun20i_d1_system_ldo_list_voltage,
-+ .map_voltage = regulator_map_voltage_ascend,
-+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
-+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
-+};
-+
-+static const struct regulator_desc sun20i_d1_system_ldo_descs[] = {
-+ {
-+ .name = "ldoa",
-+ .supply_name = "ldo-in",
-+ .of_match = "ldoa",
-+ .ops = &sun20i_d1_system_ldo_ops,
-+ .type = REGULATOR_VOLTAGE,
-+ .owner = THIS_MODULE,
-+ .n_voltages = 32,
-+ .min_uV = 1600000,
-+ .uV_step = 13333, /* repeating */
-+ .vsel_reg = SUN20I_SYS_LDO_CTRL_REG,
-+ .vsel_mask = GENMASK(7, 0),
-+ },
-+ {
-+ .name = "ldob",
-+ .supply_name = "ldo-in",
-+ .of_match = "ldob",
-+ .ops = &sun20i_d1_system_ldo_ops,
-+ .type = REGULATOR_VOLTAGE,
-+ .owner = THIS_MODULE,
-+ .n_voltages = 64,
-+ .min_uV = 1166666,
-+ .uV_step = 13333, /* repeating */
-+ .vsel_reg = SUN20I_SYS_LDO_CTRL_REG,
-+ .vsel_mask = GENMASK(15, 8),
-+ },
-+};
-+
-+static const struct sun20i_regulator_data sun20i_d1_system_ldos = {
-+ .descs = sun20i_d1_system_ldo_descs,
-+ .ndescs = ARRAY_SIZE(sun20i_d1_system_ldo_descs),
-+};
-+
-+static const struct of_device_id sun20i_regulator_of_match[] = {
-+ {
-+ .compatible = "allwinner,sun20i-d1-analog-ldos",
-+ .data = &sun20i_d1_analog_ldos,
-+ },
-+ {
-+ .compatible = "allwinner,sun20i-d1-system-ldos",
-+ .data = &sun20i_d1_system_ldos,
-+ },
-+ { },
-+};
-+MODULE_DEVICE_TABLE(of, sun20i_regulator_of_match);
-+
-+static struct regmap *sun20i_regulator_get_regmap(struct device *dev)
-+{
-+ struct regmap *regmap;
-+
-+ /*
-+ * First try the syscon interface. The system control device is not
-+ * compatible with "syscon", so fall back to getting the regmap from
-+ * its platform device. This is ugly, but required for devicetree
-+ * backward compatibility.
-+ */
-+ regmap = syscon_node_to_regmap(dev->parent->of_node);
-+ if (!IS_ERR(regmap))
-+ return regmap;
-+
-+ regmap = dev_get_regmap(dev->parent, NULL);
-+ if (regmap)
-+ return regmap;
-+
-+ return ERR_PTR(-EPROBE_DEFER);
-+}
-+
-+static int sun20i_regulator_probe(struct platform_device *pdev)
-+{
-+ const struct sun20i_regulator_data *data;
-+ struct device *dev = &pdev->dev;
-+ struct regulator_config config;
-+ struct regmap *regmap;
-+ int ret;
-+
-+ data = of_device_get_match_data(dev);
-+ if (!data)
-+ return -EINVAL;
-+
-+ regmap = sun20i_regulator_get_regmap(dev);
-+ if (IS_ERR(regmap))
-+ return dev_err_probe(dev, PTR_ERR(regmap), "Failed to get regmap\n");
-+
-+ if (data->init) {
-+ ret = data->init(dev, regmap);
-+ if (ret)
-+ return ret;
-+ }
-+
-+ config = (struct regulator_config) {
-+ .dev = dev,
-+ .regmap = regmap,
-+ };
-+
-+ for (unsigned int i = 0; i < data->ndescs; ++i) {
-+ const struct regulator_desc *desc = &data->descs[i];
-+ struct regulator_dev *rdev;
-+
-+ rdev = devm_regulator_register(dev, desc, &config);
-+ if (IS_ERR(rdev))
-+ return PTR_ERR(rdev);
-+ }
-+
-+ return 0;
-+}
-+
-+static struct platform_driver sun20i_regulator_driver = {
-+ .probe = sun20i_regulator_probe,
-+ .driver = {
-+ .name = "sun20i-regulator",
-+ .of_match_table = sun20i_regulator_of_match,
-+ },
-+};
-+module_platform_driver(sun20i_regulator_driver);
-+
-+MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
-+MODULE_DESCRIPTION("Allwinner D1 internal LDO driver");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 52c6979628d596018e9259767bff4def25e449dc Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Mon, 1 Aug 2022 23:57:19 -0500
-Subject: [PATCH 022/117] dt-bindings: sram: sunxi-sram: Add optional
- regulators child
-
-Some sunxi SoCs have in-package regulators controlled by a register in
-the system control MMIO block. Allow a child node for these regulators
-in addition to SRAM child nodes.
-
-Commit-changes: 2
- - New patch for v2
-
-Series-changes: 3
- - Require the regulators node to have a unit address
- - Reference the regulator schema from the SRAM controller schema
- - Move the system LDOs example to the SRAM controller schema
- - Reorder the patches so the example passes validation
-
-Series-changes: 4
- - Remove unevaluatedProperties from regulators schema reference
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../allwinner,sun4i-a10-system-control.yaml | 28 +++++++++++++++++++
- 1 file changed, 28 insertions(+)
-
---- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
-+++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
-@@ -56,6 +56,9 @@ properties:
- ranges: true
-
- patternProperties:
-+ "^regulators@[0-9a-f]+$":
-+ $ref: /schemas/regulator/allwinner,sun20i-d1-system-ldos.yaml#
-+
- "^sram@[a-z0-9]+":
- type: object
-
-@@ -130,3 +133,28 @@ examples:
- };
- };
- };
-+
-+ - |
-+ syscon@3000000 {
-+ compatible = "allwinner,sun20i-d1-system-control";
-+ reg = <0x3000000 0x1000>;
-+ ranges;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ regulators@3000150 {
-+ compatible = "allwinner,sun20i-d1-system-ldos";
-+ reg = <0x3000150 0x4>;
-+
-+ reg_ldoa: ldoa {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ };
-+
-+ reg_ldob: ldob {
-+ regulator-name = "vcc-dram";
-+ regulator-min-microvolt = <1500000>;
-+ regulator-max-microvolt = <1500000>;
-+ };
-+ };
-+ };
+++ /dev/null
-From 1946ff7ee38c994ae3eb9968c5b51695c0df2cf7 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 2 Aug 2022 00:01:21 -0500
-Subject: [PATCH 023/117] soc: sunxi: sram: Only iterate over SRAM children
-
-Now that a "regulators" child is accepted by the controller binding, the
-debugfs show routine must be explicitly limited to "sram" children.
-
-Series-to: Liam Girdwood <lgirdwood@gmail.com>
-Series-to: Mark Brown <broonie@kernel.org>
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-Series-to: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
-Series-to: Rob Herring <robh+dt@kernel.org>
-
-Commit-changes: 2
- - New patch for v2
-
-Series-version: 4
-
-Cover-letter:
-regulator: Add support for Allwinner D1 LDOs
-This series adds bindings and a driver for the two pairs of LDOs
-inside the Allwinner D1 SoC.
-
-A binding and driver change is required for the SRAM controller, to
-accept the regulators device as its child node. The new example in the
-SRAM controller binding uses the compatible string added in this series:
-https://lore.kernel.org/lkml/20220815041248.53268-1-samuel@sholland.org/
-END
-
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/soc/sunxi/sunxi_sram.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/drivers/soc/sunxi/sunxi_sram.c
-+++ b/drivers/soc/sunxi/sunxi_sram.c
-@@ -120,6 +120,9 @@ static int sunxi_sram_show(struct seq_fi
- seq_puts(s, "--------------------\n\n");
-
- for_each_child_of_node(sram_dev->of_node, sram_node) {
-+ if (!of_node_name_eq(sram_node, "sram"))
-+ continue;
-+
- sram_addr_p = of_get_address(sram_node, 0, NULL, NULL);
-
- seq_printf(s, "sram@%08x\n",
+++ /dev/null
-From 25727569379b42593b55cfb743b7eff4cfa1cce2 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Aug 2022 23:45:50 -0500
-Subject: [PATCH 024/117] MAINTAINERS: Match the sun20i family of Allwinner
- SoCs
-
-Allwinner sunxi SoCs with a RISC-V CPU use the sun20i designator. Match
-that pattern in addition to the designators for 32 and 64-bit ARM SoCs.
-
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- MAINTAINERS | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -1828,7 +1828,7 @@ F: drivers/pinctrl/sunxi/
- F: drivers/soc/sunxi/
- N: allwinner
- N: sun[x456789]i
--N: sun50i
-+N: sun[25]0i
-
- ARM/Amlogic Meson SoC CLOCK FRAMEWORK
- M: Neil Armstrong <neil.armstrong@linaro.org>
+++ /dev/null
-From 4ae663dbc373f5690581cee16d3667693eb9d73e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 16 May 2021 14:05:17 -0500
-Subject: [PATCH 025/117] dt-bindings: riscv: Add T-HEAD C906 and C910
- compatibles
-
-The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
-Notably, the C906 core is used in the Allwinner D1 SoC.
-
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/Documentation/devicetree/bindings/riscv/cpus.yaml
-+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
-@@ -39,6 +39,8 @@ properties:
- - sifive,u5
- - sifive,u7
- - canaan,k210
-+ - thead,c906
-+ - thead,c910
- - const: riscv
- - items:
- - enum:
+++ /dev/null
-From d0c24deb787a95515d355eea68e0402bfec77f75 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 17 Jul 2022 14:42:05 -0500
-Subject: [PATCH 026/117] dt-bindings: vendor-prefixes: Add Allwinner D1 board
- vendors
-
-Some boards using the Allwinner D1 SoC are made by vendors not
-previously documented.
-
-Clockwork Tech LLC (https://www.clockworkpi.com/) manufactures the
-ClockworkPi and DevTerm boards.
-
-Beijing Widora Technology Co., Ltd. (https://mangopi.cc/) manufactures
-the MangoPi family of boards.
-
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
-+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
-@@ -260,6 +260,8 @@ patternProperties:
- description: Cirrus Logic, Inc.
- "^cisco,.*":
- description: Cisco Systems, Inc.
-+ "^clockwork,.*":
-+ description: Clockwork Tech LLC
- "^cloudengines,.*":
- description: Cloud Engines, Inc.
- "^cnm,.*":
-@@ -1424,6 +1426,8 @@ patternProperties:
- description: Shenzhen whwave Electronics, Inc.
- "^wi2wi,.*":
- description: Wi2Wi, Inc.
-+ "^widora,.*":
-+ description: Beijing Widora Technology Co., Ltd.
- "^wiligear,.*":
- description: Wiligear, Ltd.
- "^willsemi,.*":
+++ /dev/null
-From 4d7c04f210dd401f3560a7f53c78d6e058d182e2 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 29 Jun 2022 00:26:39 -0500
-Subject: [PATCH 027/117] dt-bindings: riscv: Add Allwinner D1 board
- compatibles
-
-Several SoMs and boards are available that feature the Allwinner D1 SoC.
-Document their compatible strings.
-
-Acked-by: Rob Herring <robh@kernel.org>
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../devicetree/bindings/riscv/sunxi.yaml | 64 +++++++++++++++++++
- 1 file changed, 64 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/riscv/sunxi.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml
-@@ -0,0 +1,64 @@
-+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/riscv/sunxi.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Allwinner RISC-V SoC-based boards
-+
-+maintainers:
-+ - Chen-Yu Tsai <wens@csie.org>
-+ - Jernej Skrabec <jernej.skrabec@gmail.com>
-+ - Samuel Holland <samuel@sholland.org>
-+
-+description:
-+ Allwinner RISC-V SoC-based boards
-+
-+properties:
-+ $nodename:
-+ const: '/'
-+ compatible:
-+ oneOf:
-+ - description: Dongshan Nezha STU SoM
-+ items:
-+ - const: 100ask,dongshan-nezha-stu
-+ - const: allwinner,sun20i-d1
-+
-+ - description: D1 Nezha board
-+ items:
-+ - const: allwinner,d1-nezha
-+ - const: allwinner,sun20i-d1
-+
-+ - description: ClockworkPi R-01 SoM and v3.14 board
-+ items:
-+ - const: clockwork,r-01-clockworkpi-v3.14
-+ - const: allwinner,sun20i-d1
-+
-+ - description: ClockworkPi R-01 SoM, v3.14 board, and DevTerm expansion
-+ items:
-+ - const: clockwork,r-01-devterm-v3.14
-+ - const: clockwork,r-01-clockworkpi-v3.14
-+ - const: allwinner,sun20i-d1
-+
-+ - description: Lichee RV SoM
-+ items:
-+ - const: sipeed,lichee-rv
-+ - const: allwinner,sun20i-d1
-+
-+ - description: Carrier boards for the Lichee RV SoM
-+ items:
-+ - enum:
-+ - sipeed,lichee-rv-86-panel-480p
-+ - sipeed,lichee-rv-86-panel-720p
-+ - sipeed,lichee-rv-dock
-+ - const: sipeed,lichee-rv
-+ - const: allwinner,sun20i-d1
-+
-+ - description: MangoPi MQ Pro board
-+ items:
-+ - const: widora,mangopi-mq-pro
-+ - const: allwinner,sun20i-d1
-+
-+additionalProperties: true
-+
-+...
+++ /dev/null
-From 20d565fb9324b0d2791d10cb65560eddd2ef526e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 28 Jun 2022 23:20:33 -0500
-Subject: [PATCH 028/117] riscv: dts: allwinner: Add the D1 SoC base devicetree
-
-D1 is a SoC containing a single-core T-HEAD Xuantie C906 CPU, as well as
-one HiFi 4 DSP. The SoC is based on a design that additionally contained
-a pair of Cortex A7's. For that reason, some peripherals are duplicated.
-
-This devicetree includes all of the peripherals that already have a
-documented binding.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/Makefile | 1 +
- arch/riscv/boot/dts/allwinner/Makefile | 1 +
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 900 +++++++++++++++++++
- 3 files changed, 902 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/Makefile
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-
---- a/arch/riscv/boot/dts/Makefile
-+++ b/arch/riscv/boot/dts/Makefile
-@@ -1,4 +1,5 @@
- # SPDX-License-Identifier: GPL-2.0
-+subdir-y += allwinner
- subdir-y += sifive
- subdir-y += starfive
- subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -0,0 +1 @@
-+# SPDX-License-Identifier: GPL-2.0
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -0,0 +1,900 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
-+
-+#include <dt-bindings/clock/sun6i-rtc.h>
-+#include <dt-bindings/clock/sun8i-de2.h>
-+#include <dt-bindings/clock/sun8i-tcon-top.h>
-+#include <dt-bindings/clock/sun20i-d1-ccu.h>
-+#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
-+#include <dt-bindings/interrupt-controller/irq.h>
-+#include <dt-bindings/reset/sun8i-de2.h>
-+#include <dt-bindings/reset/sun20i-d1-ccu.h>
-+#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
-+#include <dt-bindings/thermal/thermal.h>
-+
-+/ {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ cpus {
-+ timebase-frequency = <24000000>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ cpu0: cpu@0 {
-+ compatible = "thead,c906", "riscv";
-+ device_type = "cpu";
-+ reg = <0>;
-+ clocks = <&ccu CLK_RISCV>;
-+ clock-frequency = <24000000>;
-+ d-cache-block-size = <64>;
-+ d-cache-sets = <256>;
-+ d-cache-size = <32768>;
-+ i-cache-block-size = <64>;
-+ i-cache-sets = <128>;
-+ i-cache-size = <32768>;
-+ mmu-type = "riscv,sv39";
-+ riscv,isa = "rv64imafdc";
-+ #cooling-cells = <2>;
-+
-+ cpu0_intc: interrupt-controller {
-+ compatible = "riscv,cpu-intc";
-+ interrupt-controller;
-+ #address-cells = <0>;
-+ #interrupt-cells = <1>;
-+ };
-+ };
-+ };
-+
-+ de: display-engine {
-+ compatible = "allwinner,sun20i-d1-display-engine";
-+ allwinner,pipelines = <&mixer0>, <&mixer1>;
-+ status = "disabled";
-+ };
-+
-+ osc24M: osc24M-clk {
-+ compatible = "fixed-clock";
-+ clock-frequency = <24000000>;
-+ clock-output-names = "osc24M";
-+ #clock-cells = <0>;
-+ };
-+
-+ soc {
-+ compatible = "simple-bus";
-+ ranges;
-+ interrupt-parent = <&plic>;
-+ dma-noncoherent;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ dsp_wdt: watchdog@1700400 {
-+ compatible = "allwinner,sun20i-d1-wdt";
-+ reg = <0x1700400 0x20>;
-+ interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
-+ clock-names = "hosc", "losc";
-+ status = "reserved";
-+ };
-+
-+ pio: pinctrl@2000000 {
-+ compatible = "allwinner,sun20i-d1-pinctrl";
-+ reg = <0x2000000 0x800>;
-+ interrupts = <85 IRQ_TYPE_LEVEL_HIGH>,
-+ <87 IRQ_TYPE_LEVEL_HIGH>,
-+ <89 IRQ_TYPE_LEVEL_HIGH>,
-+ <91 IRQ_TYPE_LEVEL_HIGH>,
-+ <93 IRQ_TYPE_LEVEL_HIGH>,
-+ <95 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_APB0>,
-+ <&osc24M>,
-+ <&rtc CLK_OSC32K>;
-+ clock-names = "apb", "hosc", "losc";
-+ gpio-controller;
-+ interrupt-controller;
-+ #gpio-cells = <3>;
-+ #interrupt-cells = <3>;
-+
-+ /omit-if-no-ref/
-+ i2c0_pb10_pins: i2c0-pb10-pins {
-+ pins = "PB10", "PB11";
-+ function = "i2c0";
-+ };
-+
-+ /omit-if-no-ref/
-+ i2c2_pb0_pins: i2c2-pb0-pins {
-+ pins = "PB0", "PB1";
-+ function = "i2c2";
-+ };
-+
-+ /omit-if-no-ref/
-+ lcd_rgb666_pins: lcd-rgb666-pins {
-+ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
-+ "PD6", "PD7", "PD8", "PD9", "PD10", "PD11",
-+ "PD12", "PD13", "PD14", "PD15", "PD16", "PD17",
-+ "PD18", "PD19", "PD20", "PD21";
-+ function = "lcd0";
-+ };
-+
-+ /omit-if-no-ref/
-+ mmc0_pins: mmc0-pins {
-+ pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
-+ function = "mmc0";
-+ };
-+
-+ /omit-if-no-ref/
-+ mmc1_pins: mmc1-pins {
-+ pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5";
-+ function = "mmc1";
-+ };
-+
-+ /omit-if-no-ref/
-+ mmc2_pins: mmc2-pins {
-+ pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
-+ function = "mmc2";
-+ };
-+
-+ /omit-if-no-ref/
-+ rgmii_pe_pins: rgmii-pe-pins {
-+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
-+ "PE5", "PE6", "PE7", "PE8", "PE9",
-+ "PE11", "PE12", "PE13", "PE14", "PE15";
-+ function = "emac";
-+ };
-+
-+ /omit-if-no-ref/
-+ rmii_pe_pins: rmii-pe-pins {
-+ pins = "PE0", "PE1", "PE2", "PE3", "PE4",
-+ "PE5", "PE6", "PE7", "PE8", "PE9";
-+ function = "emac";
-+ };
-+
-+ /omit-if-no-ref/
-+ uart0_pb8_pins: uart0-pb8-pins {
-+ pins = "PB8", "PB9";
-+ function = "uart0";
-+ };
-+
-+ /omit-if-no-ref/
-+ uart1_pg6_pins: uart1-pg6-pins {
-+ pins = "PG6", "PG7";
-+ function = "uart1";
-+ };
-+
-+ /omit-if-no-ref/
-+ uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins {
-+ pins = "PG8", "PG9";
-+ function = "uart1";
-+ };
-+ };
-+
-+ ccu: clock-controller@2001000 {
-+ compatible = "allwinner,sun20i-d1-ccu";
-+ reg = <0x2001000 0x1000>;
-+ clocks = <&osc24M>,
-+ <&rtc CLK_OSC32K>,
-+ <&rtc CLK_IOSC>;
-+ clock-names = "hosc", "losc", "iosc";
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ };
-+
-+ lradc: keys@2009800 {
-+ compatible = "allwinner,sun20i-d1-lradc",
-+ "allwinner,sun50i-r329-lradc";
-+ reg = <0x2009800 0x400>;
-+ interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_LRADC>;
-+ resets = <&ccu RST_BUS_LRADC>;
-+ status = "disabled";
-+ };
-+
-+ codec: audio-codec@2030000 {
-+ compatible = "simple-mfd", "syscon";
-+ reg = <0x2030000 0x1000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ regulators@2030348 {
-+ compatible = "allwinner,sun20i-d1-analog-ldos";
-+ reg = <0x2030348 0x4>;
-+ nvmem-cells = <&bg_trim>;
-+ nvmem-cell-names = "bg_trim";
-+
-+ reg_aldo: aldo {
-+ };
-+
-+ reg_hpldo: hpldo {
-+ };
-+ };
-+ };
-+
-+ i2s0: i2s@2032000 {
-+ compatible = "allwinner,sun20i-d1-i2s",
-+ "allwinner,sun50i-r329-i2s";
-+ reg = <0x2032000 0x1000>;
-+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_I2S0>,
-+ <&ccu CLK_I2S0>;
-+ clock-names = "apb", "mod";
-+ resets = <&ccu RST_BUS_I2S0>;
-+ dmas = <&dma 3>, <&dma 3>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ #sound-dai-cells = <0>;
-+ };
-+
-+ i2s1: i2s@2033000 {
-+ compatible = "allwinner,sun20i-d1-i2s",
-+ "allwinner,sun50i-r329-i2s";
-+ reg = <0x2033000 0x1000>;
-+ interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_I2S1>,
-+ <&ccu CLK_I2S1>;
-+ clock-names = "apb", "mod";
-+ resets = <&ccu RST_BUS_I2S1>;
-+ dmas = <&dma 4>, <&dma 4>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ #sound-dai-cells = <0>;
-+ };
-+
-+ i2s2: i2s@2034000 {
-+ compatible = "allwinner,sun20i-d1-i2s",
-+ "allwinner,sun50i-r329-i2s";
-+ reg = <0x2034000 0x1000>;
-+ interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_I2S2>,
-+ <&ccu CLK_I2S2>;
-+ clock-names = "apb", "mod";
-+ resets = <&ccu RST_BUS_I2S2>;
-+ dmas = <&dma 5>, <&dma 5>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ #sound-dai-cells = <0>;
-+ };
-+
-+ timer: timer@2050000 {
-+ compatible = "allwinner,sun20i-d1-timer",
-+ "allwinner,sun8i-a23-timer";
-+ reg = <0x2050000 0xa0>;
-+ interrupts = <75 IRQ_TYPE_LEVEL_HIGH>,
-+ <76 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&osc24M>;
-+ };
-+
-+ wdt: watchdog@20500a0 {
-+ compatible = "allwinner,sun20i-d1-wdt-reset",
-+ "allwinner,sun20i-d1-wdt";
-+ reg = <0x20500a0 0x20>;
-+ interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
-+ clock-names = "hosc", "losc";
-+ status = "reserved";
-+ };
-+
-+ uart0: serial@2500000 {
-+ compatible = "snps,dw-apb-uart";
-+ reg = <0x2500000 0x400>;
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_UART0>;
-+ resets = <&ccu RST_BUS_UART0>;
-+ dmas = <&dma 14>, <&dma 14>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ uart1: serial@2500400 {
-+ compatible = "snps,dw-apb-uart";
-+ reg = <0x2500400 0x400>;
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_UART1>;
-+ resets = <&ccu RST_BUS_UART1>;
-+ dmas = <&dma 15>, <&dma 15>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ uart2: serial@2500800 {
-+ compatible = "snps,dw-apb-uart";
-+ reg = <0x2500800 0x400>;
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_UART2>;
-+ resets = <&ccu RST_BUS_UART2>;
-+ dmas = <&dma 16>, <&dma 16>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ uart3: serial@2500c00 {
-+ compatible = "snps,dw-apb-uart";
-+ reg = <0x2500c00 0x400>;
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_UART3>;
-+ resets = <&ccu RST_BUS_UART3>;
-+ dmas = <&dma 17>, <&dma 17>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ uart4: serial@2501000 {
-+ compatible = "snps,dw-apb-uart";
-+ reg = <0x2501000 0x400>;
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_UART4>;
-+ resets = <&ccu RST_BUS_UART4>;
-+ dmas = <&dma 18>, <&dma 18>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ uart5: serial@2501400 {
-+ compatible = "snps,dw-apb-uart";
-+ reg = <0x2501400 0x400>;
-+ reg-io-width = <4>;
-+ reg-shift = <2>;
-+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_UART5>;
-+ resets = <&ccu RST_BUS_UART5>;
-+ dmas = <&dma 19>, <&dma 19>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ };
-+
-+ i2c0: i2c@2502000 {
-+ compatible = "allwinner,sun20i-d1-i2c",
-+ "allwinner,sun8i-v536-i2c",
-+ "allwinner,sun6i-a31-i2c";
-+ reg = <0x2502000 0x400>;
-+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_I2C0>;
-+ resets = <&ccu RST_BUS_I2C0>;
-+ dmas = <&dma 43>, <&dma 43>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ i2c1: i2c@2502400 {
-+ compatible = "allwinner,sun20i-d1-i2c",
-+ "allwinner,sun8i-v536-i2c",
-+ "allwinner,sun6i-a31-i2c";
-+ reg = <0x2502400 0x400>;
-+ interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_I2C1>;
-+ resets = <&ccu RST_BUS_I2C1>;
-+ dmas = <&dma 44>, <&dma 44>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ i2c2: i2c@2502800 {
-+ compatible = "allwinner,sun20i-d1-i2c",
-+ "allwinner,sun8i-v536-i2c",
-+ "allwinner,sun6i-a31-i2c";
-+ reg = <0x2502800 0x400>;
-+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_I2C2>;
-+ resets = <&ccu RST_BUS_I2C2>;
-+ dmas = <&dma 45>, <&dma 45>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ i2c3: i2c@2502c00 {
-+ compatible = "allwinner,sun20i-d1-i2c",
-+ "allwinner,sun8i-v536-i2c",
-+ "allwinner,sun6i-a31-i2c";
-+ reg = <0x2502c00 0x400>;
-+ interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_I2C3>;
-+ resets = <&ccu RST_BUS_I2C3>;
-+ dmas = <&dma 46>, <&dma 46>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ syscon: syscon@3000000 {
-+ compatible = "allwinner,sun20i-d1-system-control";
-+ reg = <0x3000000 0x1000>;
-+ ranges;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ regulators@3000150 {
-+ compatible = "allwinner,sun20i-d1-system-ldos";
-+ reg = <0x3000150 0x4>;
-+
-+ reg_ldoa: ldoa {
-+ };
-+
-+ reg_ldob: ldob {
-+ };
-+ };
-+ };
-+
-+ dma: dma-controller@3002000 {
-+ compatible = "allwinner,sun20i-d1-dma";
-+ reg = <0x3002000 0x1000>;
-+ interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
-+ clock-names = "bus", "mbus";
-+ resets = <&ccu RST_BUS_DMA>;
-+ dma-channels = <16>;
-+ dma-requests = <48>;
-+ #dma-cells = <1>;
-+ };
-+
-+ sid: efuse@3006000 {
-+ compatible = "allwinner,sun20i-d1-sid";
-+ reg = <0x3006000 0x1000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ ths_calib: ths-calib@14 {
-+ reg = <0x14 0x4>;
-+ };
-+
-+ bg_trim: bg-trim@28 {
-+ reg = <0x28 0x4>;
-+ bits = <16 8>;
-+ };
-+ };
-+
-+ mbus: dram-controller@3102000 {
-+ compatible = "allwinner,sun20i-d1-mbus";
-+ reg = <0x3102000 0x1000>,
-+ <0x3103000 0x1000>;
-+ reg-names = "mbus", "dram";
-+ interrupts = <59 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_MBUS>,
-+ <&ccu CLK_DRAM>,
-+ <&ccu CLK_BUS_DRAM>;
-+ clock-names = "mbus", "dram", "bus";
-+ dma-ranges = <0 0x40000000 0x80000000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ #interconnect-cells = <1>;
-+ };
-+
-+ mmc0: mmc@4020000 {
-+ compatible = "allwinner,sun20i-d1-mmc";
-+ reg = <0x4020000 0x1000>;
-+ interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
-+ clock-names = "ahb", "mmc";
-+ resets = <&ccu RST_BUS_MMC0>;
-+ reset-names = "ahb";
-+ cap-sd-highspeed;
-+ max-frequency = <150000000>;
-+ no-mmc;
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mmc1: mmc@4021000 {
-+ compatible = "allwinner,sun20i-d1-mmc";
-+ reg = <0x4021000 0x1000>;
-+ interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
-+ clock-names = "ahb", "mmc";
-+ resets = <&ccu RST_BUS_MMC1>;
-+ reset-names = "ahb";
-+ cap-sd-highspeed;
-+ max-frequency = <150000000>;
-+ no-mmc;
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ mmc2: mmc@4022000 {
-+ compatible = "allwinner,sun20i-d1-emmc",
-+ "allwinner,sun50i-a100-emmc";
-+ reg = <0x4022000 0x1000>;
-+ interrupts = <58 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
-+ clock-names = "ahb", "mmc";
-+ resets = <&ccu RST_BUS_MMC2>;
-+ reset-names = "ahb";
-+ cap-mmc-highspeed;
-+ max-frequency = <150000000>;
-+ mmc-ddr-1_8v;
-+ mmc-ddr-3_3v;
-+ no-sd;
-+ no-sdio;
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ usb_otg: usb@4100000 {
-+ compatible = "allwinner,sun20i-d1-musb",
-+ "allwinner,sun8i-a33-musb";
-+ reg = <0x4100000 0x400>;
-+ interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "mc";
-+ clocks = <&ccu CLK_BUS_OTG>;
-+ resets = <&ccu RST_BUS_OTG>;
-+ extcon = <&usbphy 0>;
-+ phys = <&usbphy 0>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ usbphy: phy@4100400 {
-+ compatible = "allwinner,sun20i-d1-usb-phy";
-+ reg = <0x4100400 0x100>,
-+ <0x4101800 0x100>,
-+ <0x4200800 0x100>;
-+ reg-names = "phy_ctrl",
-+ "pmu0",
-+ "pmu1";
-+ clocks = <&osc24M>,
-+ <&osc24M>;
-+ clock-names = "usb0_phy",
-+ "usb1_phy";
-+ resets = <&ccu RST_USB_PHY0>,
-+ <&ccu RST_USB_PHY1>;
-+ reset-names = "usb0_reset",
-+ "usb1_reset";
-+ status = "disabled";
-+ #phy-cells = <1>;
-+ };
-+
-+ ehci0: usb@4101000 {
-+ compatible = "allwinner,sun20i-d1-ehci",
-+ "generic-ehci";
-+ reg = <0x4101000 0x100>;
-+ interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI0>,
-+ <&ccu CLK_BUS_EHCI0>,
-+ <&ccu CLK_USB_OHCI0>;
-+ resets = <&ccu RST_BUS_OHCI0>,
-+ <&ccu RST_BUS_EHCI0>;
-+ phys = <&usbphy 0>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci0: usb@4101400 {
-+ compatible = "allwinner,sun20i-d1-ohci",
-+ "generic-ohci";
-+ reg = <0x4101400 0x100>;
-+ interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI0>,
-+ <&ccu CLK_USB_OHCI0>;
-+ resets = <&ccu RST_BUS_OHCI0>;
-+ phys = <&usbphy 0>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ehci1: usb@4200000 {
-+ compatible = "allwinner,sun20i-d1-ehci",
-+ "generic-ehci";
-+ reg = <0x4200000 0x100>;
-+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI1>,
-+ <&ccu CLK_BUS_EHCI1>,
-+ <&ccu CLK_USB_OHCI1>;
-+ resets = <&ccu RST_BUS_OHCI1>,
-+ <&ccu RST_BUS_EHCI1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ ohci1: usb@4200400 {
-+ compatible = "allwinner,sun20i-d1-ohci",
-+ "generic-ohci";
-+ reg = <0x4200400 0x100>;
-+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_OHCI1>,
-+ <&ccu CLK_USB_OHCI1>;
-+ resets = <&ccu RST_BUS_OHCI1>;
-+ phys = <&usbphy 1>;
-+ phy-names = "usb";
-+ status = "disabled";
-+ };
-+
-+ emac: ethernet@4500000 {
-+ compatible = "allwinner,sun20i-d1-emac",
-+ "allwinner,sun50i-a64-emac";
-+ reg = <0x4500000 0x10000>;
-+ interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
-+ interrupt-names = "macirq";
-+ clocks = <&ccu CLK_BUS_EMAC>;
-+ clock-names = "stmmaceth";
-+ resets = <&ccu RST_BUS_EMAC>;
-+ reset-names = "stmmaceth";
-+ syscon = <&syscon>;
-+ status = "disabled";
-+
-+ mdio: mdio {
-+ compatible = "snps,dwmac-mdio";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+ };
-+
-+ display_clocks: clock-controller@5000000 {
-+ compatible = "allwinner,sun20i-d1-de2-clk",
-+ "allwinner,sun50i-h5-de2-clk";
-+ reg = <0x5000000 0x10000>;
-+ clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
-+ clock-names = "bus", "mod";
-+ resets = <&ccu RST_BUS_DE>;
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ };
-+
-+ mixer0: mixer@5100000 {
-+ compatible = "allwinner,sun20i-d1-de2-mixer-0";
-+ reg = <0x5100000 0x100000>;
-+ clocks = <&display_clocks CLK_BUS_MIXER0>,
-+ <&display_clocks CLK_MIXER0>;
-+ clock-names = "bus", "mod";
-+ resets = <&display_clocks RST_MIXER0>;
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ mixer0_out: port@1 {
-+ reg = <1>;
-+
-+ mixer0_out_tcon_top_mixer0: endpoint {
-+ remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
-+ };
-+ };
-+ };
-+ };
-+
-+ mixer1: mixer@5200000 {
-+ compatible = "allwinner,sun20i-d1-de2-mixer-1";
-+ reg = <0x5200000 0x100000>;
-+ clocks = <&display_clocks CLK_BUS_MIXER1>,
-+ <&display_clocks CLK_MIXER1>;
-+ clock-names = "bus", "mod";
-+ resets = <&display_clocks RST_MIXER1>;
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ mixer1_out: port@1 {
-+ reg = <1>;
-+
-+ mixer1_out_tcon_top_mixer1: endpoint {
-+ remote-endpoint = <&tcon_top_mixer1_in_mixer1>;
-+ };
-+ };
-+ };
-+ };
-+
-+ tcon_top: tcon-top@5460000 {
-+ compatible = "allwinner,sun20i-d1-tcon-top";
-+ reg = <0x5460000 0x1000>;
-+ clocks = <&ccu CLK_BUS_DPSS_TOP>,
-+ <&ccu CLK_TCON_TV>,
-+ <&ccu CLK_TVE>,
-+ <&ccu CLK_TCON_LCD0>;
-+ clock-names = "bus", "tcon-tv0", "tve0", "dsi";
-+ clock-output-names = "tcon-top-tv0", "tcon-top-dsi";
-+ resets = <&ccu RST_BUS_DPSS_TOP>;
-+ #clock-cells = <1>;
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ tcon_top_mixer0_in: port@0 {
-+ reg = <0>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ tcon_top_mixer0_in_mixer0: endpoint@0 {
-+ reg = <0>;
-+ remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
-+ };
-+ };
-+
-+ tcon_top_mixer0_out: port@1 {
-+ reg = <1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ tcon_top_mixer0_out_tcon_lcd0: endpoint@0 {
-+ reg = <0>;
-+ remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>;
-+ };
-+
-+ tcon_top_mixer0_out_tcon_tv0: endpoint@2 {
-+ reg = <2>;
-+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>;
-+ };
-+ };
-+
-+ tcon_top_mixer1_in: port@2 {
-+ reg = <2>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ tcon_top_mixer1_in_mixer1: endpoint@1 {
-+ reg = <1>;
-+ remote-endpoint = <&mixer1_out_tcon_top_mixer1>;
-+ };
-+ };
-+
-+ tcon_top_mixer1_out: port@3 {
-+ reg = <3>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ tcon_top_mixer1_out_tcon_lcd0: endpoint@0 {
-+ reg = <0>;
-+ remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>;
-+ };
-+
-+ tcon_top_mixer1_out_tcon_tv0: endpoint@2 {
-+ reg = <2>;
-+ remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>;
-+ };
-+ };
-+
-+ tcon_top_hdmi_in: port@4 {
-+ reg = <4>;
-+
-+ tcon_top_hdmi_in_tcon_tv0: endpoint {
-+ remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>;
-+ };
-+ };
-+
-+ tcon_top_hdmi_out: port@5 {
-+ reg = <5>;
-+ };
-+ };
-+ };
-+
-+ tcon_lcd0: lcd-controller@5461000 {
-+ compatible = "allwinner,sun20i-d1-tcon-lcd";
-+ reg = <0x5461000 0x1000>;
-+ interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_TCON_LCD0>,
-+ <&ccu CLK_TCON_LCD0>;
-+ clock-names = "ahb", "tcon-ch0";
-+ clock-output-names = "tcon-pixel-clock";
-+ resets = <&ccu RST_BUS_TCON_LCD0>,
-+ <&ccu RST_BUS_LVDS0>;
-+ reset-names = "lcd", "lvds";
-+ #clock-cells = <0>;
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ tcon_lcd0_in: port@0 {
-+ reg = <0>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ tcon_lcd0_in_tcon_top_mixer0: endpoint@0 {
-+ reg = <0>;
-+ remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>;
-+ };
-+
-+ tcon_lcd0_in_tcon_top_mixer1: endpoint@1 {
-+ reg = <1>;
-+ remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>;
-+ };
-+ };
-+
-+ tcon_lcd0_out: port@1 {
-+ reg = <1>;
-+ };
-+ };
-+ };
-+
-+ tcon_tv0: lcd-controller@5470000 {
-+ compatible = "allwinner,sun20i-d1-tcon-tv";
-+ reg = <0x5470000 0x1000>;
-+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_TCON_TV>,
-+ <&tcon_top CLK_TCON_TOP_TV0>;
-+ clock-names = "ahb", "tcon-ch1";
-+ resets = <&ccu RST_BUS_TCON_TV>;
-+ reset-names = "lcd";
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ tcon_tv0_in: port@0 {
-+ reg = <0>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ tcon_tv0_in_tcon_top_mixer0: endpoint@0 {
-+ reg = <0>;
-+ remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>;
-+ };
-+
-+ tcon_tv0_in_tcon_top_mixer1: endpoint@1 {
-+ reg = <1>;
-+ remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>;
-+ };
-+ };
-+
-+ tcon_tv0_out: port@1 {
-+ reg = <1>;
-+
-+ tcon_tv0_out_tcon_top_hdmi: endpoint {
-+ remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>;
-+ };
-+ };
-+ };
-+ };
-+
-+ riscv_wdt: watchdog@6011000 {
-+ compatible = "allwinner,sun20i-d1-wdt";
-+ reg = <0x6011000 0x20>;
-+ interrupts = <147 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&osc24M>, <&rtc CLK_OSC32K>;
-+ clock-names = "hosc", "losc";
-+ };
-+
-+ r_ccu: clock-controller@7010000 {
-+ compatible = "allwinner,sun20i-d1-r-ccu";
-+ reg = <0x7010000 0x400>;
-+ clocks = <&osc24M>,
-+ <&rtc CLK_OSC32K>,
-+ <&rtc CLK_IOSC>,
-+ <&ccu CLK_PLL_PERIPH0_DIV3>;
-+ clock-names = "hosc", "losc", "iosc", "pll-periph";
-+ #clock-cells = <1>;
-+ #reset-cells = <1>;
-+ };
-+
-+ rtc: rtc@7090000 {
-+ compatible = "allwinner,sun20i-d1-rtc",
-+ "allwinner,sun50i-r329-rtc";
-+ reg = <0x7090000 0x400>;
-+ interrupts = <160 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&r_ccu CLK_BUS_R_RTC>,
-+ <&osc24M>,
-+ <&r_ccu CLK_R_AHB>;
-+ clock-names = "bus", "hosc", "ahb";
-+ #clock-cells = <1>;
-+ };
-+
-+ plic: interrupt-controller@10000000 {
-+ compatible = "allwinner,sun20i-d1-plic",
-+ "thead,c900-plic";
-+ reg = <0x10000000 0x4000000>;
-+ interrupts-extended = <&cpu0_intc 11>,
-+ <&cpu0_intc 9>;
-+ interrupt-controller;
-+ riscv,ndev = <176>;
-+ #address-cells = <0>;
-+ #interrupt-cells = <2>;
-+ };
-+ };
-+};
+++ /dev/null
-From 5da27190c54b7a51062786eb01246f6f4cf2ba98 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 28 Jun 2022 23:31:16 -0500
-Subject: [PATCH 029/117] riscv: dts: allwinner: Add Allwinner D1 Nezha
- devicetree
-
-"D1 Nezha" is Allwinner's first-party development board for the D1 SoC.
-It was shipped with 512M, 1G, or 2G of DDR3. It supports onboard audio,
-HDMI, gigabit Ethernet, WiFi and Bluetooth, USB 2.0 host and OTG ports,
-plus low-speed I/O from the SoC and a GPIO expander chip.
-
-Most other D1 boards copied the Nezha's power tree, with the 1.8V rail
-powered by the SoCs internal LDOA, analog domains powered by ALDO, and
-the rest of the board powered by always-on fixed regulators. Some (but
-not all) boards also copied the PWM CPU regulator. To avoid duplication,
-factor out the out the regulator references that are common across all
-known boards.
-
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Tested-by: Conor Dooley <conor.dooley@microchip.com>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/Makefile | 1 +
- .../sun20i-d1-common-regulators.dtsi | 51 ++++++
- .../boot/dts/allwinner/sun20i-d1-nezha.dts | 171 ++++++++++++++++++
- 3 files changed, 223 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-
---- a/arch/riscv/boot/dts/allwinner/Makefile
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -1 +1,2 @@
- # SPDX-License-Identifier: GPL-2.0
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
-@@ -0,0 +1,51 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
-+
-+/ {
-+ reg_vcc: vcc {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ };
-+
-+ reg_vcc_3v3: vcc-3v3 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vcc-3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ vin-supply = <®_vcc>;
-+ };
-+};
-+
-+&lradc {
-+ vref-supply = <®_aldo>;
-+};
-+
-+&pio {
-+ vcc-pb-supply = <®_vcc_3v3>;
-+ vcc-pc-supply = <®_vcc_3v3>;
-+ vcc-pd-supply = <®_vcc_3v3>;
-+ vcc-pe-supply = <®_vcc_3v3>;
-+ vcc-pf-supply = <®_vcc_3v3>;
-+ vcc-pg-supply = <®_vcc_3v3>;
-+};
-+
-+®_aldo {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ vdd33-supply = <®_vcc_3v3>;
-+};
-+
-+®_hpldo {
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ hpldoin-supply = <®_vcc_3v3>;
-+};
-+
-+®_ldoa {
-+ regulator-always-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ ldo-in-supply = <®_vcc_3v3>;
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-@@ -0,0 +1,171 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/input/input.h>
-+
-+#include "sun20i-d1.dtsi"
-+#include "sun20i-d1-common-regulators.dtsi"
-+
-+/ {
-+ model = "Allwinner D1 Nezha";
-+ compatible = "allwinner,d1-nezha", "allwinner,sun20i-d1";
-+
-+ aliases {
-+ ethernet0 = &emac;
-+ ethernet1 = &xr829;
-+ mmc0 = &mmc0;
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ reg_usbvbus: usbvbus {
-+ compatible = "regulator-fixed";
-+ regulator-name = "usbvbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
-+ enable-active-high;
-+ vin-supply = <®_vcc>;
-+ };
-+
-+ /*
-+ * This regulator is PWM-controlled, but the PWM controller is not
-+ * yet supported, so fix the regulator to its default voltage.
-+ */
-+ reg_vdd_cpu: vdd-cpu {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vdd-cpu";
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1100000>;
-+ vin-supply = <®_vcc>;
-+ };
-+
-+ wifi_pwrseq: wifi-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <®_vdd_cpu>;
-+};
-+
-+&ehci0 {
-+ status = "okay";
-+};
-+
-+&ehci1 {
-+ status = "okay";
-+};
-+
-+&emac {
-+ pinctrl-0 = <&rgmii_pe_pins>;
-+ pinctrl-names = "default";
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii-id";
-+ phy-supply = <®_vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&i2c2 {
-+ pinctrl-0 = <&i2c2_pb0_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ pcf8574a: gpio@38 {
-+ compatible = "nxp,pcf8574a";
-+ reg = <0x38>;
-+ interrupt-parent = <&pio>;
-+ interrupts = <1 2 IRQ_TYPE_LEVEL_LOW>; /* PB2 */
-+ interrupt-controller;
-+ gpio-controller;
-+ #gpio-cells = <2>;
-+ #interrupt-cells = <2>;
-+ };
-+};
-+
-+&lradc {
-+ status = "okay";
-+
-+ button-160 {
-+ label = "OK";
-+ linux,code = <KEY_OK>;
-+ channel = <0>;
-+ voltage = <160000>;
-+ };
-+};
-+
-+&mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ };
-+};
-+
-+&mmc0 {
-+ bus-width = <4>;
-+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-+ disable-wp;
-+ vmmc-supply = <®_vcc_3v3>;
-+ vqmmc-supply = <®_vcc_3v3>;
-+ pinctrl-0 = <&mmc0_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&mmc1 {
-+ bus-width = <4>;
-+ mmc-pwrseq = <&wifi_pwrseq>;
-+ non-removable;
-+ vmmc-supply = <®_vcc_3v3>;
-+ vqmmc-supply = <®_vcc_3v3>;
-+ pinctrl-0 = <&mmc1_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ xr829: wifi@1 {
-+ reg = <1>;
-+ };
-+};
-+
-+&ohci0 {
-+ status = "okay";
-+};
-+
-+&ohci1 {
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ pinctrl-0 = <&uart0_pb8_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&uart1 {
-+ uart-has-rtscts;
-+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ /* XR829 bluetooth is connected here */
-+};
-+
-+&usb_otg {
-+ dr_mode = "otg";
-+ status = "okay";
-+};
-+
-+&usbphy {
-+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
-+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
-+ usb0_vbus-supply = <®_usbvbus>;
-+ usb1_vbus-supply = <®_vcc>;
-+ status = "okay";
-+};
+++ /dev/null
-From 3bf76e93011425ed64a69c462b9959ed2a8ccf46 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 29 Jun 2022 00:13:50 -0500
-Subject: [PATCH 030/117] riscv: dts: allwinner: Add Sipeed Lichee RV
- devicetrees
-
-Sipeed manufactures a "Lichee RV" system-on-module, which provides a
-minimal working system on its own, as well as a few carrier boards. The
-"Dock" board provides audio, USB, and WiFi. The "86 Panel" additionally
-provides 100M Ethernet and a built-in display panel.
-
-The 86 Panel repurposes the USB ID and VBUS detection GPIOs for its RGB
-panel interface, since the USB OTG port is inaccessible inside the case.
-
-Co-developed-by: Jisheng Zhang <jszhang@kernel.org>
-Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/Makefile | 4 +
- .../sun20i-d1-lichee-rv-86-panel-480p.dts | 29 ++++++
- .../sun20i-d1-lichee-rv-86-panel-720p.dts | 10 ++
- .../sun20i-d1-lichee-rv-86-panel.dtsi | 92 +++++++++++++++++++
- .../allwinner/sun20i-d1-lichee-rv-dock.dts | 74 +++++++++++++++
- .../dts/allwinner/sun20i-d1-lichee-rv.dts | 84 +++++++++++++++++
- 6 files changed, 293 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
-
---- a/arch/riscv/boot/dts/allwinner/Makefile
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -1,2 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
-@@ -0,0 +1,29 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+#include "sun20i-d1-lichee-rv-86-panel.dtsi"
-+
-+/ {
-+ model = "Sipeed Lichee RV 86 Panel (480p)";
-+ compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
-+ "allwinner,sun20i-d1";
-+};
-+
-+&i2c2 {
-+ pinctrl-0 = <&i2c2_pb0_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ touchscreen@48 {
-+ compatible = "focaltech,ft6236";
-+ reg = <0x48>;
-+ interrupt-parent = <&pio>;
-+ interrupts = <6 14 IRQ_TYPE_LEVEL_LOW>; /* PG14 */
-+ iovcc-supply = <®_vcc_3v3>;
-+ reset-gpios = <&pio 6 15 GPIO_ACTIVE_LOW>; /* PG15 */
-+ touchscreen-size-x = <480>;
-+ touchscreen-size-y = <480>;
-+ vcc-supply = <®_vcc_3v3>;
-+ wakeup-source;
-+ };
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-720p.dts
-@@ -0,0 +1,10 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+#include "sun20i-d1-lichee-rv-86-panel.dtsi"
-+
-+/ {
-+ model = "Sipeed Lichee RV 86 Panel (720p)";
-+ compatible = "sipeed,lichee-rv-86-panel-720p", "sipeed,lichee-rv",
-+ "allwinner,sun20i-d1";
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
-@@ -0,0 +1,92 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+#include "sun20i-d1-lichee-rv.dts"
-+
-+/ {
-+ aliases {
-+ ethernet0 = &emac;
-+ ethernet1 = &xr829;
-+ };
-+
-+ /* PC1 is repurposed as BT_WAKE_AP */
-+ /delete-node/ leds;
-+
-+ wifi_pwrseq: wifi-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ clocks = <&ccu CLK_FANOUT1>;
-+ clock-names = "ext_clock";
-+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
-+ assigned-clocks = <&ccu CLK_FANOUT1>;
-+ assigned-clock-rates = <32768>;
-+ pinctrl-0 = <&clk_pg11_pin>;
-+ pinctrl-names = "default";
-+ };
-+};
-+
-+&ehci1 {
-+ status = "okay";
-+};
-+
-+&emac {
-+ pinctrl-0 = <&rmii_pe_pins>;
-+ pinctrl-names = "default";
-+ phy-handle = <&ext_rmii_phy>;
-+ phy-mode = "rmii";
-+ phy-supply = <®_vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&mdio {
-+ ext_rmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
-+ };
-+};
-+
-+&mmc1 {
-+ bus-width = <4>;
-+ mmc-pwrseq = <&wifi_pwrseq>;
-+ non-removable;
-+ vmmc-supply = <®_vcc_3v3>;
-+ vqmmc-supply = <®_vcc_3v3>;
-+ pinctrl-0 = <&mmc1_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ xr829: wifi@1 {
-+ reg = <1>;
-+ };
-+};
-+
-+&ohci1 {
-+ status = "okay";
-+};
-+
-+&pio {
-+ clk_pg11_pin: clk-pg11-pin {
-+ pins = "PG11";
-+ function = "clk";
-+ };
-+};
-+
-+&uart1 {
-+ uart-has-rtscts;
-+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ /* XR829 bluetooth is connected here */
-+};
-+
-+&usb_otg {
-+ status = "disabled";
-+};
-+
-+&usbphy {
-+ /* PD20 and PD21 are repurposed for the LCD panel */
-+ /delete-property/ usb0_id_det-gpios;
-+ /delete-property/ usb0_vbus_det-gpios;
-+ usb1_vbus-supply = <®_vcc>;
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-@@ -0,0 +1,74 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+#include <dt-bindings/input/input.h>
-+
-+#include "sun20i-d1-lichee-rv.dts"
-+
-+/ {
-+ model = "Sipeed Lichee RV Dock";
-+ compatible = "sipeed,lichee-rv-dock", "sipeed,lichee-rv",
-+ "allwinner,sun20i-d1";
-+
-+ aliases {
-+ ethernet1 = &rtl8723ds;
-+ };
-+
-+ wifi_pwrseq: wifi-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
-+ };
-+};
-+
-+&ehci1 {
-+ status = "okay";
-+};
-+
-+&lradc {
-+ status = "okay";
-+
-+ button-220 {
-+ label = "OK";
-+ linux,code = <KEY_OK>;
-+ channel = <0>;
-+ voltage = <220000>;
-+ };
-+};
-+
-+&mmc1 {
-+ bus-width = <4>;
-+ mmc-pwrseq = <&wifi_pwrseq>;
-+ non-removable;
-+ vmmc-supply = <®_vcc_3v3>;
-+ vqmmc-supply = <®_vcc_3v3>;
-+ pinctrl-0 = <&mmc1_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ rtl8723ds: wifi@1 {
-+ reg = <1>;
-+ };
-+};
-+
-+&ohci1 {
-+ status = "okay";
-+};
-+
-+&uart1 {
-+ uart-has-rtscts;
-+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ bluetooth {
-+ compatible = "realtek,rtl8723ds-bt";
-+ device-wake-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG16 */
-+ enable-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
-+ host-wake-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>; /* PG17 */
-+ };
-+};
-+
-+&usbphy {
-+ usb1_vbus-supply = <®_vcc>;
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
-@@ -0,0 +1,84 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org>
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+
-+#include "sun20i-d1.dtsi"
-+#include "sun20i-d1-common-regulators.dtsi"
-+
-+/ {
-+ model = "Sipeed Lichee RV";
-+ compatible = "sipeed,lichee-rv", "allwinner,sun20i-d1";
-+
-+ aliases {
-+ mmc0 = &mmc0;
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ led-0 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_STATUS;
-+ gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
-+ };
-+ };
-+
-+ reg_vdd_cpu: vdd-cpu {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vdd-cpu";
-+ regulator-min-microvolt = <900000>;
-+ regulator-max-microvolt = <900000>;
-+ vin-supply = <®_vcc>;
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <®_vdd_cpu>;
-+};
-+
-+&ehci0 {
-+ status = "okay";
-+};
-+
-+&mmc0 {
-+ broken-cd;
-+ bus-width = <4>;
-+ disable-wp;
-+ vmmc-supply = <®_vcc_3v3>;
-+ vqmmc-supply = <®_vcc_3v3>;
-+ pinctrl-0 = <&mmc0_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&ohci0 {
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ pinctrl-0 = <&uart0_pb8_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&usb_otg {
-+ dr_mode = "otg";
-+ status = "okay";
-+};
-+
-+&usbphy {
-+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
-+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
-+ usb0_vbus-supply = <®_vcc>;
-+ status = "okay";
-+};
+++ /dev/null
-From 3cf55c25453517960d72b56d1ba8f12840b1990e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 9 Jul 2022 17:43:17 -0500
-Subject: [PATCH 031/117] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree
-
-The MangoPi MQ Pro is a tiny SBC with a layout compatible to the
-Raspberry Pi Zero. It includes the Allwinner D1 SoC, 512M or 1G of DDR3,
-and an RTL8723DS-based WiFi/Bluetooth module.
-
-The board also exposes GPIO Port E via a connector on the end of the
-board, which can support either a camera or an RMII Ethernet PHY. The
-additional regulators supply that connector.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/Makefile | 1 +
- .../allwinner/sun20i-d1-mangopi-mq-pro.dts | 128 ++++++++++++++++++
- 2 files changed, 129 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
-
---- a/arch/riscv/boot/dts/allwinner/Makefile
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -3,4 +3,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-li
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-mangopi-mq-pro.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-nezha.dtb
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
-@@ -0,0 +1,128 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+#include "sun20i-d1.dtsi"
-+#include "sun20i-d1-common-regulators.dtsi"
-+
-+/ {
-+ model = "MangoPi MQ Pro";
-+ compatible = "widora,mangopi-mq-pro", "allwinner,sun20i-d1";
-+
-+ aliases {
-+ ethernet0 = &rtl8723ds;
-+ mmc0 = &mmc0;
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ reg_avdd2v8: avdd2v8 {
-+ compatible = "regulator-fixed";
-+ regulator-name = "avdd2v8";
-+ regulator-min-microvolt = <2800000>;
-+ regulator-max-microvolt = <2800000>;
-+ vin-supply = <®_vcc_3v3>;
-+ };
-+
-+ reg_dvdd: dvdd {
-+ compatible = "regulator-fixed";
-+ regulator-name = "dvdd";
-+ regulator-min-microvolt = <1200000>;
-+ regulator-max-microvolt = <1200000>;
-+ vin-supply = <®_vcc_3v3>;
-+ };
-+
-+ reg_vdd_cpu: vdd-cpu {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vdd-cpu";
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1100000>;
-+ vin-supply = <®_vcc>;
-+ };
-+
-+ wifi_pwrseq: wifi-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ reset-gpios = <&pio 6 17 GPIO_ACTIVE_LOW>; /* PG17 */
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <®_vdd_cpu>;
-+};
-+
-+&ehci1 {
-+ status = "okay";
-+};
-+
-+&mmc0 {
-+ bus-width = <4>;
-+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
-+ disable-wp;
-+ vmmc-supply = <®_vcc_3v3>;
-+ vqmmc-supply = <®_vcc_3v3>;
-+ pinctrl-0 = <&mmc0_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&mmc1 {
-+ bus-width = <4>;
-+ mmc-pwrseq = <&wifi_pwrseq>;
-+ non-removable;
-+ vmmc-supply = <®_vcc_3v3>;
-+ vqmmc-supply = <®_vcc_3v3>;
-+ pinctrl-0 = <&mmc1_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ rtl8723ds: wifi@1 {
-+ reg = <1>;
-+ interrupt-parent = <&pio>;
-+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
-+ interrupt-names = "host-wake";
-+ };
-+};
-+
-+&ohci1 {
-+ status = "okay";
-+};
-+
-+&pio {
-+ vcc-pe-supply = <®_avdd2v8>;
-+};
-+
-+&uart0 {
-+ pinctrl-0 = <&uart0_pb8_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&uart1 {
-+ uart-has-rtscts;
-+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ bluetooth {
-+ compatible = "realtek,rtl8723ds-bt";
-+ device-wake-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */
-+ enable-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
-+ host-wake-gpios = <&pio 6 14 GPIO_ACTIVE_HIGH>; /* PG14 */
-+ };
-+};
-+
-+&usb_otg {
-+ dr_mode = "peripheral";
-+ status = "okay";
-+};
-+
-+&usbphy {
-+ usb0_vbus-supply = <®_vcc>;
-+ status = "okay";
-+};
+++ /dev/null
-From 1f26c90ac9cbb60ff315c552368a3bca16562e51 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 10 Jul 2022 11:24:42 -0500
-Subject: [PATCH 032/117] riscv: dts: allwinner: Add Dongshan Nezha STU
- devicetree
-
-The 100ask Dongshan Nezha STU is a system-on-module that can be used
-standalone or with a carrier board. The SoM provides gigabit Ethernet,
-HDMI, a USB peripheral port, and WiFi/Bluetooth via an RTL8723DS chip.
-
-The "DIY" carrier board exposes almost every pin from the D1 SoC to 0.1"
-headers, but contains no digital circuitry, so it does not have its own
-devicetree.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/Makefile | 1 +
- .../sun20i-d1-dongshan-nezha-stu.dts | 114 ++++++++++++++++++
- 2 files changed, 115 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
-
---- a/arch/riscv/boot/dts/allwinner/Makefile
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -1,4 +1,5 @@
- # SPDX-License-Identifier: GPL-2.0
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
-@@ -0,0 +1,114 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+
-+#include "sun20i-d1.dtsi"
-+#include "sun20i-d1-common-regulators.dtsi"
-+
-+/ {
-+ model = "Dongshan Nezha STU";
-+ compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
-+
-+ aliases {
-+ ethernet0 = &emac;
-+ mmc0 = &mmc0;
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+
-+ led-0 {
-+ color = <LED_COLOR_ID_GREEN>;
-+ function = LED_FUNCTION_STATUS;
-+ gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
-+ };
-+ };
-+
-+ reg_usbvbus: usbvbus {
-+ compatible = "regulator-fixed";
-+ regulator-name = "usbvbus";
-+ regulator-min-microvolt = <5000000>;
-+ regulator-max-microvolt = <5000000>;
-+ gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
-+ enable-active-high;
-+ vin-supply = <®_vcc>;
-+ };
-+
-+ /*
-+ * This regulator is PWM-controlled, but the PWM controller is not
-+ * yet supported, so fix the regulator to its default voltage.
-+ */
-+ reg_vdd_cpu: vdd-cpu {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vdd-cpu";
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1100000>;
-+ vin-supply = <®_vcc>;
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <®_vdd_cpu>;
-+};
-+
-+&ehci0 {
-+ status = "okay";
-+};
-+
-+&emac {
-+ pinctrl-0 = <&rgmii_pe_pins>;
-+ pinctrl-names = "default";
-+ phy-handle = <&ext_rgmii_phy>;
-+ phy-mode = "rgmii-id";
-+ phy-supply = <®_vcc_3v3>;
-+ status = "okay";
-+};
-+
-+&mdio {
-+ ext_rgmii_phy: ethernet-phy@1 {
-+ compatible = "ethernet-phy-ieee802.3-c22";
-+ reg = <1>;
-+ };
-+};
-+
-+&mmc0 {
-+ broken-cd;
-+ bus-width = <4>;
-+ disable-wp;
-+ vmmc-supply = <®_vcc_3v3>;
-+ vqmmc-supply = <®_vcc_3v3>;
-+ pinctrl-0 = <&mmc0_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&ohci0 {
-+ status = "okay";
-+};
-+
-+&uart0 {
-+ pinctrl-0 = <&uart0_pb8_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&usb_otg {
-+ dr_mode = "otg";
-+ status = "okay";
-+};
-+
-+&usbphy {
-+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
-+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
-+ usb0_vbus-supply = <®_usbvbus>;
-+ status = "okay";
-+};
+++ /dev/null
-From 11f692c6b009f36b9a91d5ceb5998ae15e57f18c Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 10 Jul 2022 23:43:49 -0500
-Subject: [PATCH 033/117] riscv: dts: allwinner: Add ClockworkPi and DevTerm
- devicetrees
-
-Clockwork Tech manufactures several SoMs for their RasPi CM3-compatible
-"ClockworkPi" mainboard. Their R-01 SoM features the Allwinner D1 SoC.
-The R-01 contains only the CPU, DRAM, and always-on voltage regulation;
-it does not merit a separate devicetree.
-
-The ClockworkPi mainboard features analog audio, a MIPI-DSI panel, USB
-host and peripheral ports, an Ampak AP6256 WiFi/Bluetooth module, and an
-X-Powers AXP228 PMIC for managing a Li-ion battery.
-
-The DevTerm is a complete system which extends the ClockworkPi mainboard
-with a pair of expansion boards. These expansion boards provide a fan, a
-keyboard, speakers, and a thermal printer.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/Makefile | 2 +
- .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 242 ++++++++++++++++++
- .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 37 +++
- 3 files changed, 281 insertions(+)
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
- create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
-
---- a/arch/riscv/boot/dts/allwinner/Makefile
-+++ b/arch/riscv/boot/dts/allwinner/Makefile
-@@ -1,4 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-clockworkpi-v3.14.dtb
-+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-devterm-v3.14.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
- dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-@@ -0,0 +1,242 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include <dt-bindings/gpio/gpio.h>
-+
-+#include "sun20i-d1.dtsi"
-+#include "sun20i-d1-common-regulators.dtsi"
-+
-+/ {
-+ model = "ClockworkPi v3.14 (R-01)";
-+ compatible = "clockwork,r-01-clockworkpi-v3.14", "allwinner,sun20i-d1";
-+
-+ aliases {
-+ ethernet0 = &ap6256;
-+ mmc0 = &mmc0;
-+ serial0 = &uart0;
-+ };
-+
-+ chosen {
-+ stdout-path = "serial0:115200n8";
-+ };
-+
-+ /*
-+ * This regulator is PWM-controlled, but the PWM controller is not
-+ * yet supported, so fix the regulator to its default voltage.
-+ */
-+ reg_vdd_cpu: vdd-cpu {
-+ compatible = "regulator-fixed";
-+ regulator-name = "vdd-cpu";
-+ regulator-min-microvolt = <1100000>;
-+ regulator-max-microvolt = <1100000>;
-+ vin-supply = <®_vcc>;
-+ };
-+
-+ wifi_pwrseq: wifi-pwrseq {
-+ compatible = "mmc-pwrseq-simple";
-+ reset-gpios = <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11/GPIO3 */
-+ };
-+};
-+
-+&cpu0 {
-+ cpu-supply = <®_vdd_cpu>;
-+};
-+
-+&ehci1 {
-+ status = "okay";
-+};
-+
-+&i2c0 {
-+ pinctrl-0 = <&i2c0_pb10_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ axp221: pmic@34 {
-+ compatible = "x-powers,axp228", "x-powers,axp221";
-+ reg = <0x34>;
-+ interrupt-parent = <&pio>;
-+ interrupts = <4 9 IRQ_TYPE_LEVEL_LOW>; /* PE9/GPIO2 */
-+ interrupt-controller;
-+ #interrupt-cells = <1>;
-+
-+ ac_power_supply: ac-power {
-+ compatible = "x-powers,axp221-ac-power-supply";
-+ };
-+
-+ axp_adc: adc {
-+ compatible = "x-powers,axp221-adc";
-+ #io-channel-cells = <1>;
-+ };
-+
-+ battery_power_supply: battery-power {
-+ compatible = "x-powers,axp221-battery-power-supply";
-+ };
-+
-+ regulators {
-+ x-powers,dcdc-freq = <3000>;
-+
-+ reg_dcdc1: dcdc1 {
-+ regulator-name = "sys-3v3";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ reg_dcdc3: dcdc3 {
-+ regulator-name = "sys-1v8";
-+ regulator-always-on;
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ };
-+
-+ reg_aldo1: aldo1 {
-+ regulator-name = "aud-3v3";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ reg_aldo2: aldo2 {
-+ regulator-name = "disp-3v3";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ reg_aldo3: aldo3 {
-+ regulator-name = "vdd-wifi";
-+ regulator-min-microvolt = <1800000>;
-+ regulator-max-microvolt = <1800000>;
-+ };
-+
-+ /* DLDO1 and ELDO1-3 are connected in parallel. */
-+ reg_dldo1: dldo1 {
-+ regulator-name = "vbat-wifi-a";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ /* DLDO2-DLDO4 are connected in parallel. */
-+ reg_dldo2: dldo2 {
-+ regulator-name = "vcc-3v3-ext-a";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ reg_dldo3: dldo3 {
-+ regulator-name = "vcc-3v3-ext-b";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ reg_dldo4: dldo4 {
-+ regulator-name = "vcc-3v3-ext-c";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ reg_eldo1: eldo1 {
-+ regulator-name = "vbat-wifi-b";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ reg_eldo2: eldo2 {
-+ regulator-name = "vbat-wifi-c";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+
-+ reg_eldo3: eldo3 {
-+ regulator-name = "vbat-wifi-d";
-+ regulator-always-on;
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ };
-+ };
-+
-+ usb_power_supply: usb-power {
-+ compatible = "x-powers,axp221-usb-power-supply";
-+ status = "disabled";
-+ };
-+ };
-+};
-+
-+&mmc0 {
-+ broken-cd;
-+ bus-width = <4>;
-+ disable-wp;
-+ vmmc-supply = <®_dcdc1>;
-+ vqmmc-supply = <®_vcc_3v3>;
-+ pinctrl-0 = <&mmc0_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&mmc1 {
-+ bus-width = <4>;
-+ mmc-pwrseq = <&wifi_pwrseq>;
-+ non-removable;
-+ vmmc-supply = <®_dldo1>;
-+ vqmmc-supply = <®_aldo3>;
-+ pinctrl-0 = <&mmc1_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ ap6256: wifi@1 {
-+ compatible = "brcm,bcm43456-fmac", "brcm,bcm4329-fmac";
-+ reg = <1>;
-+ interrupt-parent = <&pio>;
-+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10/GPIO4 */
-+ interrupt-names = "host-wake";
-+ };
-+};
-+
-+&ohci1 {
-+ status = "okay";
-+};
-+
-+&pio {
-+ vcc-pg-supply = <®_ldoa>;
-+};
-+
-+&uart0 {
-+ pinctrl-0 = <&uart0_pb8_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&uart1 {
-+ uart-has-rtscts;
-+ pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ bluetooth {
-+ compatible = "brcm,bcm4345c5";
-+ interrupt-parent = <&pio>;
-+ interrupts = <6 17 IRQ_TYPE_LEVEL_HIGH>; /* PG17/GPIO6 */
-+ device-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>; /* PG16/GPIO7 */
-+ shutdown-gpios = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18/GPIO5 */
-+ max-speed = <1500000>;
-+ vbat-supply = <®_dldo1>;
-+ vddio-supply = <®_aldo3>;
-+ };
-+};
-+
-+&usb_otg {
-+ dr_mode = "peripheral";
-+ status = "okay";
-+};
-+
-+&usbphy {
-+ usb0_vbus_power-supply = <&ac_power_supply>;
-+ status = "okay";
-+};
---- /dev/null
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
-@@ -0,0 +1,37 @@
-+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
-+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
-+
-+/dts-v1/;
-+
-+#include "sun20i-d1-clockworkpi-v3.14.dts"
-+
-+/ {
-+ model = "Clockwork DevTerm (R-01)";
-+ compatible = "clockwork,r-01-devterm-v3.14",
-+ "clockwork,r-01-clockworkpi-v3.14",
-+ "allwinner,sun20i-d1";
-+
-+ fan {
-+ compatible = "gpio-fan";
-+ gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10/GPIO41 */
-+ gpio-fan,speed-map = <0 0>,
-+ <6000 1>;
-+ #cooling-cells = <2>;
-+ };
-+
-+ i2c-gpio-0 {
-+ compatible = "i2c-gpio";
-+ sda-gpios = <&pio 3 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD14/GPIO44 */
-+ scl-gpios = <&pio 3 15 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PD15/GPIO45 */
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ adc@54 {
-+ compatible = "ti,adc101c";
-+ reg = <0x54>;
-+ interrupt-parent = <&pio>;
-+ interrupts = <4 12 IRQ_TYPE_LEVEL_LOW>; /* PE12/GPIO35 */
-+ vref-supply = <®_dldo2>;
-+ };
-+ };
-+};
+++ /dev/null
-From f648ec2a040efde432876ee04240cb71e4c24d6e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 16 May 2021 14:17:45 -0500
-Subject: [PATCH 034/117] riscv: Add the Allwinner SoC family Kconfig option
-
-Allwinner manufactures the sunxi family of application processors. This
-includes the "sun8i" series of ARMv7 SoCs, the "sun50i" series of ARMv8
-SoCs, and now the "sun20i" series of 64-bit RISC-V SoCs.
-
-The first SoC in the sun20i series is D1, containing a single T-HEAD
-C906 core. D1s is a low-pin-count variant of D1 with co-packaged DRAM.
-
-Most peripherals are shared across the entire chip family. In fact, the
-ARMv7 T113 SoC is pin-compatible and almost entirely register-compatible
-with the D1s.
-
-This means many existing device drivers can be reused. To facilitate
-this reuse, name the symbol ARCH_SUNXI, since that is what the existing
-drivers have as their dependency.
-
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Tested-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/Kconfig.socs | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
---- a/arch/riscv/Kconfig.socs
-+++ b/arch/riscv/Kconfig.socs
-@@ -1,5 +1,14 @@
- menu "SoC selection"
-
-+config ARCH_SUNXI
-+ bool "Allwinner sun20i SoCs"
-+ select ERRATA_THEAD if MMU && !XIP_KERNEL
-+ select SIFIVE_PLIC
-+ select SUN4I_TIMER
-+ help
-+ This enables support for Allwinner sun20i platform hardware,
-+ including boards based on the D1 and D1s SoCs.
-+
- config SOC_MICROCHIP_POLARFIRE
- bool "Microchip PolarFire SoCs"
- select MCHP_CLK_MPFS
+++ /dev/null
-From 73f9cc8568b6b821107d5194fa868e922b159091 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Mon, 27 Jun 2022 01:33:05 -0500
-Subject: [PATCH 035/117] riscv: defconfig: Enable the Allwinner D1 platform
- and drivers
-
-Now that several D1-based boards are supported, enable the platform in
-our defconfig. Build in the drivers which are necessary to boot, such as
-the pinctrl, MMC, RTC (which provides critical clocks), SPI (for flash),
-and watchdog (which may be left enabled by the bootloader). Other common
-onboard peripherals are enabled as modules.
-
-Cover-letter:
-riscv: Allwinner D1 platform support
-This series adds the Kconfig/defconfig plumbing and devicetrees for a
-range of Allwinner D1-based boards. Many features are already enabled,
-including USB, Ethernet, and WiFi.
-
-The SoC devicetree uses bindings from the following series which have
-not yet been merged:
-- SRAM controller:
- https://lore.kernel.org/lkml/20220815041248.53268-1-samuel@sholland.org/
-- NVMEM cell bits property change:
- https://lore.kernel.org/lkml/20220814173656.11856-1-samuel@sholland.org/
-- In-package LDO regulators:
- https://lore.kernel.org/lkml/20220815043436.20170-1-samuel@sholland.org/
-
-All three of these are required to set the correct I/O domain voltages
-in the pin controller, which I would consider important to have in the
-initial version of the devicetree.
-
-The SoC devicetree does contain one small hack to avoid a dependency on
-the audio codec binding, since that is not ready yet: the codec node
-uses a bare "simple-mfd", "syscon" compatible.
-END
-
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-Series-to: linux-sunxi@lists.linux.dev
-Series-to: Palmer Dabbelt <palmer@dabbelt.com>
-Series-to: Paul Walmsley <paul.walmsley@sifive.com>
-Series-to: Albert Ou <aou@eecs.berkeley.edu>
-Series-to: linux-riscv@lists.infradead.org
-Series-cc: Rob Herring <robh+dt@kernel.org>
-Series-cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
-Series-cc: devicetree@vger.kernel.org
-Series-cc: linux-kernel@vger.kernel.org
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/configs/defconfig | 23 ++++++++++++++++++++++-
- 1 file changed, 22 insertions(+), 1 deletion(-)
-
---- a/arch/riscv/configs/defconfig
-+++ b/arch/riscv/configs/defconfig
-@@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=y
- CONFIG_EXPERT=y
- # CONFIG_SYSFS_SYSCALL is not set
- CONFIG_PROFILING=y
-+CONFIG_ARCH_SUNXI=y
- CONFIG_SOC_MICROCHIP_POLARFIRE=y
- CONFIG_SOC_SIFIVE=y
- CONFIG_SOC_STARFIVE=y
-@@ -118,22 +119,31 @@ CONFIG_VIRTIO_NET=y
- CONFIG_MACB=y
- CONFIG_E1000E=y
- CONFIG_R8169=y
-+CONFIG_STMMAC_ETH=m
- CONFIG_MICROSEMI_PHY=y
- CONFIG_INPUT_MOUSEDEV=y
-+CONFIG_KEYBOARD_SUN4I_LRADC=m
- CONFIG_SERIAL_8250=y
- CONFIG_SERIAL_8250_CONSOLE=y
-+CONFIG_SERIAL_8250_DW=y
- CONFIG_SERIAL_OF_PLATFORM=y
- CONFIG_VIRTIO_CONSOLE=y
- CONFIG_HW_RANDOM=y
- CONFIG_HW_RANDOM_VIRTIO=y
-+CONFIG_I2C_MV64XXX=m
- CONFIG_SPI=y
- CONFIG_SPI_SIFIVE=y
-+CONFIG_SPI_SUN6I=y
- # CONFIG_PTP_1588_CLOCK is not set
--CONFIG_GPIOLIB=y
- CONFIG_GPIO_SIFIVE=y
-+CONFIG_WATCHDOG=y
-+CONFIG_SUNXI_WATCHDOG=y
-+CONFIG_REGULATOR=y
-+CONFIG_REGULATOR_FIXED_VOLTAGE=y
- CONFIG_DRM=m
- CONFIG_DRM_RADEON=m
- CONFIG_DRM_NOUVEAU=m
-+CONFIG_DRM_SUN4I=m
- CONFIG_DRM_VIRTIO_GPU=m
- CONFIG_FB=y
- CONFIG_FRAMEBUFFER_CONSOLE=y
-@@ -146,19 +156,30 @@ CONFIG_USB_OHCI_HCD=y
- CONFIG_USB_OHCI_HCD_PLATFORM=y
- CONFIG_USB_STORAGE=y
- CONFIG_USB_UAS=y
-+CONFIG_USB_MUSB_HDRC=m
-+CONFIG_USB_MUSB_SUNXI=m
-+CONFIG_NOP_USB_XCEIV=m
- CONFIG_MMC=y
- CONFIG_MMC_SDHCI=y
- CONFIG_MMC_SDHCI_PLTFM=y
- CONFIG_MMC_SDHCI_CADENCE=y
- CONFIG_MMC_SPI=y
-+CONFIG_MMC_SUNXI=y
- CONFIG_RTC_CLASS=y
-+CONFIG_RTC_DRV_SUN6I=y
-+CONFIG_DMADEVICES=y
-+CONFIG_DMA_SUN6I=m
- CONFIG_VIRTIO_PCI=y
- CONFIG_VIRTIO_BALLOON=y
- CONFIG_VIRTIO_INPUT=y
- CONFIG_VIRTIO_MMIO=y
-+CONFIG_SUN8I_DE2_CCU=m
-+CONFIG_SUN50I_IOMMU=y
- CONFIG_RPMSG_CHAR=y
- CONFIG_RPMSG_CTRL=y
- CONFIG_RPMSG_VIRTIO=y
-+CONFIG_PHY_SUN4I_USB=m
-+CONFIG_NVMEM_SUNXI_SID=y
- CONFIG_EXT4_FS=y
- CONFIG_EXT4_FS_POSIX_ACL=y
- CONFIG_EXT4_FS_SECURITY=y
+++ /dev/null
-From bf83f1dc034111aac1f23b98d7205d08c7c83208 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 02:33:25 -0500
-Subject: [PATCH 036/117] riscv: dts: allwinner: Add Bluetooth PCM audio
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 47 +++++++++++++++++++
- 1 file changed, 47 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-@@ -22,6 +22,32 @@
- stdout-path = "serial0:115200n8";
- };
-
-+ bt_sco_codec: bt-sco-codec {
-+ #sound-dai-cells = <0>;
-+ compatible = "linux,bt-sco";
-+ };
-+
-+ bt-sound {
-+ compatible = "simple-audio-card";
-+ simple-audio-card,name = "Bluetooth";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ simple-audio-card,dai-link@0 {
-+ format = "dsp_a";
-+ frame-master = <&bt_sound_cpu>;
-+ bitclock-master = <&bt_sound_cpu>;
-+
-+ bt_sound_cpu: cpu {
-+ sound-dai = <&i2s1>;
-+ };
-+
-+ codec {
-+ sound-dai = <&bt_sco_codec>;
-+ };
-+ };
-+ };
-+
- /*
- * This regulator is PWM-controlled, but the PWM controller is not
- * yet supported, so fix the regulator to its default voltage.
-@@ -169,6 +195,12 @@
- };
- };
-
-+&i2s1 {
-+ pinctrl-0 = <&i2s1_clk_pins>, <&i2s1_din_pin>, <&i2s1_dout_pin>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
- &mmc0 {
- broken-cd;
- bus-width = <4>;
-@@ -205,6 +237,21 @@
-
- &pio {
- vcc-pg-supply = <®_ldoa>;
-+
-+ i2s1_clk_pins: i2s1-clk-pins {
-+ pins = "PG12", "PG13";
-+ function = "i2s1";
-+ };
-+
-+ i2s1_din_pin: i2s1-din-pin {
-+ pins = "PG14";
-+ function = "i2s1_din";
-+ };
-+
-+ i2s1_dout_pin: i2s1-dout-pin {
-+ pins = "PG15";
-+ function = "i2s1_dout";
-+ };
- };
-
- &uart0 {
+++ /dev/null
-From 690b8d708e0193d50522f70359bcab62a2f99742 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Nov 2021 09:04:29 -0600
-Subject: [PATCH 037/117] dt-bindings: crypto: sun8i-ce: Add compatible for D1
-
-D1 has a crypto engine similar to the one in other Allwinner SoCs.
-Like H6, it has a separate MBUS clock gate.
-
-It also requires the internal RC oscillator to be enabled for the TRNG
-to return data. This is likely the case for earlier variants as well,
-but the clock drivers for earlier SoCs did not allow disabling the RC
-oscillator.
-
-Series-changes: 2
- - Add TRNG clock
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/crypto/allwinner,sun8i-ce.yaml | 31 ++++++++++++++-----
- 1 file changed, 23 insertions(+), 8 deletions(-)
-
---- a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
-+++ b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
-@@ -14,6 +14,7 @@ properties:
- enum:
- - allwinner,sun8i-h3-crypto
- - allwinner,sun8i-r40-crypto
-+ - allwinner,sun20i-d1-crypto
- - allwinner,sun50i-a64-crypto
- - allwinner,sun50i-h5-crypto
- - allwinner,sun50i-h6-crypto
-@@ -29,6 +30,7 @@ properties:
- - description: Bus clock
- - description: Module clock
- - description: MBus clock
-+ - description: TRNG clock (RC oscillator)
- minItems: 2
-
- clock-names:
-@@ -36,6 +38,7 @@ properties:
- - const: bus
- - const: mod
- - const: ram
-+ - const: trng
- minItems: 2
-
- resets:
-@@ -44,19 +47,31 @@ properties:
- if:
- properties:
- compatible:
-- const: allwinner,sun50i-h6-crypto
-+ enum:
-+ - allwinner,sun20i-d1-crypto
- then:
- properties:
- clocks:
-- minItems: 3
-+ minItems: 4
- clock-names:
-- minItems: 3
-+ minItems: 4
- else:
-- properties:
-- clocks:
-- maxItems: 2
-- clock-names:
-- maxItems: 2
-+ if:
-+ properties:
-+ compatible:
-+ const: allwinner,sun50i-h6-crypto
-+ then:
-+ properties:
-+ clocks:
-+ minItems: 3
-+ clock-names:
-+ minItems: 3
-+ else:
-+ properties:
-+ clocks:
-+ maxItems: 2
-+ clock-names:
-+ maxItems: 2
-
- required:
- - compatible
+++ /dev/null
-From d09357656ae3985095f562cf005fa94fd61ebfe6 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 1 Feb 2022 21:50:16 -0600
-Subject: [PATCH 038/117] crypto: sun8i-ce - Add TRNG clock to D1 variant
-
-At least the D1 variant requires a separate clock for the TRNG.
-Without this clock enabled, reading from /dev/hwrng reports:
-
- sun8i-ce 3040000.crypto: DMA timeout for TRNG (tm=96) on flow 3
-
-Experimentation shows that the necessary clock is the SoC's internal
-RC oscillator. This makes sense, as the oscillator's frequency
-variations can be used as a source of randomness.
-
-Since D1 does not yet have a device tree, we can update this variant
-without breaking anything.
-
-Series-changes: 2
- - New patch
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 1 +
- drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 2 +-
- 2 files changed, 2 insertions(+), 1 deletion(-)
-
---- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
-+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
-@@ -118,6 +118,7 @@ static const struct ce_variant ce_d1_var
- { "bus", 0, 200000000 },
- { "mod", 300000000, 0 },
- { "ram", 0, 400000000 },
-+ { "trng", 0, 0 },
- },
- .esr = ESR_D1,
- .prng = CE_ALG_PRNG,
---- a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
-+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
-@@ -105,7 +105,7 @@
-
- #define MAX_SG 8
-
--#define CE_MAX_CLOCKS 3
-+#define CE_MAX_CLOCKS 4
-
- #define MAXFLOW 4
-
+++ /dev/null
-From 5dae72bf0e0fabb3164dbc4b5eee310c63f1975c Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:20:31 -0500
-Subject: [PATCH 039/117] riscv: dts: allwinner: d1: Add crypto engine support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -457,6 +457,18 @@
- };
- };
-
-+ crypto: crypto@3040000 {
-+ compatible = "allwinner,sun20i-d1-crypto";
-+ reg = <0x3040000 0x800>;
-+ interrupts = <68 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_CE>,
-+ <&ccu CLK_CE>,
-+ <&ccu CLK_MBUS_CE>,
-+ <&rtc CLK_IOSC>;
-+ clock-names = "bus", "mod", "ram", "trng";
-+ resets = <&ccu RST_BUS_CE>;
-+ };
-+
- mbus: dram-controller@3102000 {
- compatible = "allwinner,sun20i-d1-mbus";
- reg = <0x3102000 0x1000>,
+++ /dev/null
-From 7a24e5ee94e0163801c8ab4c131ae1d530a420ea Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 02:08:36 -0500
-Subject: [PATCH 040/117] ASoC: sun50i-dmic: dt-bindings: Add D1 compatible
- string
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/sound/allwinner,sun50i-h6-dmic.yaml | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/sound/allwinner,sun50i-h6-dmic.yaml
-+++ b/Documentation/devicetree/bindings/sound/allwinner,sun50i-h6-dmic.yaml
-@@ -11,7 +11,12 @@ maintainers:
-
- properties:
- compatible:
-- const: allwinner,sun50i-h6-dmic
-+ oneOf:
-+ - items:
-+ - enum:
-+ - allwinner,sun20i-d1-dmic
-+ - const: allwinner,sun50i-h6-dmic
-+ - const: allwinner,sun50i-h6-dmic
-
- "#sound-dai-cells":
- const: 0
+++ /dev/null
-From d73f2176958e405e55c4e782c6d0f888e20080e5 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 02:08:58 -0500
-Subject: [PATCH 041/117] riscv: dts: allwinner: d1: Add DMIC node
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 15 +++++++++++++++
- 1 file changed, 15 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -208,6 +208,21 @@
- };
- };
-
-+ dmic: dmic@2031000 {
-+ compatible = "allwinner,sun20i-d1-dmic",
-+ "allwinner,sun50i-h6-dmic";
-+ reg = <0x2031000 0x400>;
-+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_DMIC>,
-+ <&ccu CLK_DMIC>;
-+ clock-names = "bus", "mod";
-+ resets = <&ccu RST_BUS_DMIC>;
-+ dmas = <&dma 8>;
-+ dma-names = "rx";
-+ status = "disabled";
-+ #sound-dai-cells = <0>;
-+ };
-+
- i2s0: i2s@2032000 {
- compatible = "allwinner,sun20i-d1-i2s",
- "allwinner,sun50i-r329-i2s";
+++ /dev/null
-From 500a3fc1ce1b216ef4f4df73e4e048170764189e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 02:20:49 -0500
-Subject: [PATCH 042/117] riscv: dts: allwinner: Add DMIC sound cards
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../sun20i-d1-lichee-rv-86-panel.dtsi | 43 ++++++++++++++++++
- .../allwinner/sun20i-d1-lichee-rv-dock.dts | 45 +++++++++++++++++++
- 2 files changed, 88 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
-@@ -9,6 +9,33 @@
- ethernet1 = &xr829;
- };
-
-+ dmic_codec: dmic-codec {
-+ compatible = "dmic-codec";
-+ num-channels = <2>;
-+ #sound-dai-cells = <0>;
-+ };
-+
-+ dmic-sound {
-+ compatible = "simple-audio-card";
-+ simple-audio-card,name = "DMIC";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ simple-audio-card,dai-link@0 {
-+ format = "pdm";
-+ frame-master = <&link0_cpu>;
-+ bitclock-master = <&link0_cpu>;
-+
-+ link0_cpu: cpu {
-+ sound-dai = <&dmic>;
-+ };
-+
-+ link0_codec: codec {
-+ sound-dai = <&dmic_codec>;
-+ };
-+ };
-+ };
-+
- /* PC1 is repurposed as BT_WAKE_AP */
- /delete-node/ leds;
-
-@@ -24,6 +51,12 @@
- };
- };
-
-+&dmic {
-+ pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
- &ehci1 {
- status = "okay";
- };
-@@ -69,6 +102,16 @@
- pins = "PG11";
- function = "clk";
- };
-+
-+ dmic_pb11_d0_pin: dmic-pb11-d0-pin {
-+ pins = "PB11";
-+ function = "dmic";
-+ };
-+
-+ dmic_pe17_clk_pin: dmic-pe17-clk-pin {
-+ pins = "PE17";
-+ function = "dmic";
-+ };
- };
-
- &uart1 {
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-@@ -15,12 +15,45 @@
- ethernet1 = &rtl8723ds;
- };
-
-+ dmic_codec: dmic-codec {
-+ compatible = "dmic-codec";
-+ num-channels = <2>;
-+ #sound-dai-cells = <0>;
-+ };
-+
-+ dmic-sound {
-+ compatible = "simple-audio-card";
-+ simple-audio-card,name = "DMIC";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ simple-audio-card,dai-link@0 {
-+ format = "pdm";
-+ frame-master = <&link0_cpu>;
-+ bitclock-master = <&link0_cpu>;
-+
-+ link0_cpu: cpu {
-+ sound-dai = <&dmic>;
-+ };
-+
-+ link0_codec: codec {
-+ sound-dai = <&dmic_codec>;
-+ };
-+ };
-+ };
-+
- wifi_pwrseq: wifi-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */
- };
- };
-
-+&dmic {
-+ pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
- &ehci1 {
- status = "okay";
- };
-@@ -55,6 +88,18 @@
- status = "okay";
- };
-
-+&pio {
-+ dmic_pb11_d0_pin: dmic-pb11-d0-pin {
-+ pins = "PB11";
-+ function = "dmic";
-+ };
-+
-+ dmic_pe17_clk_pin: dmic-pe17-clk-pin {
-+ pins = "PE17";
-+ function = "dmic";
-+ };
-+};
-+
- &uart1 {
- uart-has-rtscts;
- pinctrl-0 = <&uart1_pg6_pins>, <&uart1_pg8_rts_cts_pins>;
+++ /dev/null
-From 7708f7471ab45039e08237b42121d0372f9216a7 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:42:19 -0500
-Subject: [PATCH 043/117] hwspinlock: sun6i: Clarify bank counting logic
-
-In some of the most recent datasheets, the register definition was
-updated in a way that resolves the conflict here: the field is only two
-bits wide, and a value of "4" really means a bit pattern of "0". Correct
-the code to reflect this, but leave an updated comment because some
-datasheets still have incorrect information in them.
-
-Fixes: 3c881e05c814 ("hwspinlock: add sun6i hardware spinlock support")
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/hwspinlock/sun6i_hwspinlock.c | 36 +++++++++++----------------
- 1 file changed, 14 insertions(+), 22 deletions(-)
-
---- a/drivers/hwspinlock/sun6i_hwspinlock.c
-+++ b/drivers/hwspinlock/sun6i_hwspinlock.c
-@@ -129,30 +129,22 @@ static int sun6i_hwspinlock_probe(struct
- }
-
- /*
-- * bit 28 and 29 represents the hwspinlock setup
-+ * Bits 28 and 29 represent the number of available locks.
- *
-- * every datasheet (A64, A80, A83T, H3, H5, H6 ...) says the default value is 0x1 and 0x1
-- * to 0x4 represent 32, 64, 128 and 256 locks
-- * but later datasheets (H5, H6) say 00, 01, 10, 11 represent 32, 64, 128 and 256 locks,
-- * but that would mean H5 and H6 have 64 locks, while their datasheets talk about 32 locks
-- * all the time, not a single mentioning of 64 locks
-- * the 0x4 value is also not representable by 2 bits alone, so some datasheets are not
-- * correct
-- * one thing have all in common, default value of the sysstatus register is 0x10000000,
-- * which results in bit 28 being set
-- * this is the reason 0x1 is considered being 32 locks and bit 30 is taken into account
-- * verified on H2+ (datasheet 0x1 = 32 locks) and H5 (datasheet 01 = 64 locks)
-+ * The datasheets have two conflicting interpretations for these bits:
-+ * | 00 | 01 | 10 | 11 |
-+ * +-----+----+-----+-----+
-+ * | 256 | 32 | 64 | 128 | A80, A83T, H3, A64, A50, D1
-+ * | 32 | 64 | 128 | 256 | H5, H6, R329
-+ * where some datasheets use "4" instead of "0" for the first column.
-+ *
-+ * Experiments shows that the first interpretation is correct, as all
-+ * known implementations report the value "1" and have 32 spinlocks.
- */
-- num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28;
-- switch (num_banks) {
-- case 1 ... 4:
-- priv->nlocks = 1 << (4 + num_banks);
-- break;
-- default:
-- err = -EINVAL;
-- dev_err(&pdev->dev, "unsupported hwspinlock setup (%d)\n", num_banks);
-- goto bank_fail;
-- }
-+ num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28 & 0x3;
-+ if (!num_banks)
-+ num_banks = 4;
-+ priv->nlocks = 1 << (4 + num_banks);
-
- priv->bank = devm_kzalloc(&pdev->dev, struct_size(priv->bank, lock, priv->nlocks),
- GFP_KERNEL);
+++ /dev/null
-From a19b55088945ce86051ea4eab22df27805a30c71 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:41:44 -0500
-Subject: [PATCH 044/117] hwspinlock: sun6i: Fix driver to match binding
-
-The binding for this device does not allow using the clock-names and
-reset-names properties, so the driver should not reference the clock or
-reset by name.
-
-Fixes: 3c881e05c814 ("hwspinlock: add sun6i hardware spinlock support")
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/hwspinlock/sun6i_hwspinlock.c | 12 +++++-------
- 1 file changed, 5 insertions(+), 7 deletions(-)
-
---- a/drivers/hwspinlock/sun6i_hwspinlock.c
-+++ b/drivers/hwspinlock/sun6i_hwspinlock.c
-@@ -104,14 +104,12 @@ static int sun6i_hwspinlock_probe(struct
- if (!priv)
- return -ENOMEM;
-
-- priv->ahb_clk = devm_clk_get(&pdev->dev, "ahb");
-- if (IS_ERR(priv->ahb_clk)) {
-- err = PTR_ERR(priv->ahb_clk);
-- dev_err(&pdev->dev, "unable to get AHB clock (%d)\n", err);
-- return err;
-- }
-+ priv->ahb_clk = devm_clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(priv->ahb_clk))
-+ return dev_err_probe(&pdev->dev, PTR_ERR(priv->ahb_clk),
-+ "unable to get AHB clock\n");
-
-- priv->reset = devm_reset_control_get(&pdev->dev, "ahb");
-+ priv->reset = devm_reset_control_get(&pdev->dev, NULL);
- if (IS_ERR(priv->reset))
- return dev_err_probe(&pdev->dev, PTR_ERR(priv->reset),
- "unable to get reset control\n");
+++ /dev/null
-From f0c29c5d370507ca2106689e7e17b81e8b58f236 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Nov 2021 11:37:34 -0600
-Subject: [PATCH 045/117] dt-bindings: hwlock: sun6i: Add interrupts property
-
-While it was not officially documented until recently (e.g. A50), the
-hwspinlock block can trigger an interrupt when a lock is unlocked. This
-capability is used by Allwinner's ARISC firmware, it has been verified
-to work on A64, and the IRQ numbers are reserved as far back as A31.
-So most likely this feature has always been available.
-
-Even though the Linux hwspinlock framework cannot make use of the IRQ,
-the capability should still be documented in the device tree.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
-+++ b/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
-@@ -26,17 +26,22 @@ properties:
- resets:
- maxItems: 1
-
-+ interrupts:
-+ maxItems: 1
-+
- required:
- - compatible
- - reg
- - clocks
- - resets
-+ - interrupts
-
- additionalProperties: false
-
- examples:
- - |
- #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
-+ #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
-
- hwlock@1c18000 {
-@@ -44,5 +49,6 @@ examples:
- reg = <0x01c18000 0x1000>;
- clocks = <&ccu CLK_BUS_SPINLOCK>;
- resets = <&ccu RST_BUS_SPINLOCK>;
-+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- };
- ...
+++ /dev/null
-From e7b8c42c6bf02f4c2e24b015a12cd9edad094644 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Nov 2021 12:36:52 -0600
-Subject: [PATCH 046/117] dt-bindings: hwlock: sun6i: Add per-SoC compatibles
-
-While all implementations of this hardware appear to be indentical, it
-is possible that some difference exists. To be safe, add a compatible
-for each SoC integration, using the A31 compatible only as a fallback.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../hwlock/allwinner,sun6i-a31-hwspinlock.yaml | 16 +++++++++++++++-
- 1 file changed, 15 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
-+++ b/Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
-@@ -15,7 +15,21 @@ description:
-
- properties:
- compatible:
-- const: allwinner,sun6i-a31-hwspinlock
-+ oneOf:
-+ - items:
-+ - enum:
-+ - allwinner,sun8i-a23-hwspinlock
-+ - allwinner,sun8i-a33-hwspinlock
-+ - allwinner,sun8i-a50-hwspinlock
-+ - allwinner,sun8i-a83t-hwspinlock
-+ - allwinner,sun8i-h3-hwspinlock
-+ - allwinner,sun9i-a80-hwspinlock
-+ - allwinner,sun20i-d1-hwspinlock
-+ - allwinner,sun50i-a64-hwspinlock
-+ - allwinner,sun50i-h6-hwspinlock
-+ - allwinner,sun50i-r329-hwspinlock
-+ - const: allwinner,sun6i-a31-hwspinlock
-+ - const: allwinner,sun6i-a31-hwspinlock
-
- reg:
- maxItems: 1
+++ /dev/null
-From 419b337ac3e60126f9de0bc98892e54a8ffe3b6e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:50:57 -0500
-Subject: [PATCH 047/117] ASoC: sun4i-i2s: Also set capture DMA width
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-i2s.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/sound/soc/sunxi/sun4i-i2s.c
-+++ b/sound/soc/sunxi/sun4i-i2s.c
-@@ -633,6 +633,7 @@ static int sun4i_i2s_hw_params(struct sn
- params_physical_width(params));
- return -EINVAL;
- }
-+ i2s->capture_dma_data.addr_width = width;
- i2s->playback_dma_data.addr_width = width;
-
- sr = i2s->variant->get_sr(word_size);
+++ /dev/null
-From dbad9a1f280b3c3e34cc133407ae057293b8aadf Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 02:34:08 -0500
-Subject: [PATCH 048/117] todo
-
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -253,6 +253,7 @@
- #sound-dai-cells = <0>;
- };
-
-+ // TODO: how to integrate ASRC? same or separate node?
- i2s2: i2s@2034000 {
- compatible = "allwinner,sun20i-d1-i2s",
- "allwinner,sun50i-r329-i2s";
+++ /dev/null
-From 031deed1d755fc9f1e4908ef70969e1458203421 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 6 Jun 2021 10:20:38 -0500
-Subject: [PATCH 049/117] dt-bindings: iommu: sun50i: Add compatible for
- Allwinner D1
-
-D1 contains an IOMMU similar to the one in the H6 SoC, but the D1
-variant has no external reset signal.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../iommu/allwinner,sun50i-h6-iommu.yaml | 16 ++++++++++++++--
- 1 file changed, 14 insertions(+), 2 deletions(-)
-
---- a/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml
-+++ b/Documentation/devicetree/bindings/iommu/allwinner,sun50i-h6-iommu.yaml
-@@ -17,7 +17,9 @@ properties:
- The content of the cell is the master ID.
-
- compatible:
-- const: allwinner,sun50i-h6-iommu
-+ enum:
-+ - allwinner,sun20i-d1-iommu
-+ - allwinner,sun50i-h6-iommu
-
- reg:
- maxItems: 1
-@@ -37,7 +39,17 @@ required:
- - reg
- - interrupts
- - clocks
-- - resets
-+
-+if:
-+ properties:
-+ compatible:
-+ contains:
-+ enum:
-+ - allwinner,sun50i-h6-iommu
-+
-+then:
-+ required:
-+ - resets
-
- additionalProperties: false
-
+++ /dev/null
-From 15a0487680cf506bb4b9bfee2c41b2c3176d4efa Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 27 Apr 2022 19:01:57 -0500
-Subject: [PATCH 050/117] iommu/sun50i: Support variants without an external
- reset
-
-The IOMMU in the Allwinner D1 SoC does not have an external reset line.
-
-Only attempt to get the reset on hardware variants which should have one
-according to the binding. And switch from the deprecated function to the
-explicit "exclusive" variant.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/iommu/sun50i-iommu.c | 18 ++++++++++++++++--
- 1 file changed, 16 insertions(+), 2 deletions(-)
-
---- a/drivers/iommu/sun50i-iommu.c
-+++ b/drivers/iommu/sun50i-iommu.c
-@@ -95,6 +95,10 @@
-
- #define SPAGE_SIZE 4096
-
-+struct sun50i_iommu_variant {
-+ bool has_reset;
-+};
-+
- struct sun50i_iommu {
- struct iommu_device iommu;
-
-@@ -979,9 +983,14 @@ static irqreturn_t sun50i_iommu_irq(int
-
- static int sun50i_iommu_probe(struct platform_device *pdev)
- {
-+ const struct sun50i_iommu_variant *variant;
- struct sun50i_iommu *iommu;
- int ret, irq;
-
-+ variant = of_device_get_match_data(&pdev->dev);
-+ if (!variant)
-+ return -EINVAL;
-+
- iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
- if (!iommu)
- return -ENOMEM;
-@@ -1021,7 +1030,8 @@ static int sun50i_iommu_probe(struct pla
- goto err_free_group;
- }
-
-- iommu->reset = devm_reset_control_get(&pdev->dev, NULL);
-+ if (variant->has_reset)
-+ iommu->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
- if (IS_ERR(iommu->reset)) {
- dev_err(&pdev->dev, "Couldn't get our reset line.\n");
- ret = PTR_ERR(iommu->reset);
-@@ -1059,8 +1069,12 @@ err_free_cache:
- return ret;
- }
-
-+static const struct sun50i_iommu_variant sun50i_h6_iommu = {
-+ .has_reset = true,
-+};
-+
- static const struct of_device_id sun50i_iommu_dt[] = {
-- { .compatible = "allwinner,sun50i-h6-iommu", },
-+ { .compatible = "allwinner,sun50i-h6-iommu", .data = &sun50i_h6_iommu },
- { /* sentinel */ },
- };
- MODULE_DEVICE_TABLE(of, sun50i_iommu_dt);
+++ /dev/null
-From 384e2ca3c049fe36f4e679fc76fcc8dfdc9297f9 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 27 Apr 2022 19:06:28 -0500
-Subject: [PATCH 051/117] iommu/sun50i: Ensure bypass is disabled
-
-The H6 variant of the hardware disables bypass by default. The D1
-variant of the hardware enables bypass for all masters by default.
-
-Since the driver expects bypass to be disabled, ensure that is the case.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/iommu/sun50i-iommu.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/iommu/sun50i-iommu.c
-+++ b/drivers/iommu/sun50i-iommu.c
-@@ -445,6 +445,8 @@ static int sun50i_iommu_enable(struct su
-
- spin_lock_irqsave(&iommu->iommu_lock, flags);
-
-+ iommu_write(iommu, IOMMU_BYPASS_REG, 0);
-+
- iommu_write(iommu, IOMMU_TTB_REG, sun50i_domain->dt_dma);
- iommu_write(iommu, IOMMU_TLB_PREFETCH_REG,
- IOMMU_TLB_PREFETCH_MASTER_ENABLE(0) |
+++ /dev/null
-From 5fdd5231c56d58f16a6cefa2bed4b8f331da2c92 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 27 Apr 2022 19:20:58 -0500
-Subject: [PATCH 052/117] iommu/sun50i: Add support for the D1 variant
-
-D1 contains an IOMMU similar to the one in the H6 SoC, but the D1
-variant has no external reset signal. It also has some register
-definition changes, but none that affect the current driver.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/iommu/sun50i-iommu.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/iommu/sun50i-iommu.c
-+++ b/drivers/iommu/sun50i-iommu.c
-@@ -1071,11 +1071,15 @@ err_free_cache:
- return ret;
- }
-
-+static const struct sun50i_iommu_variant sun20i_d1_iommu = {
-+};
-+
- static const struct sun50i_iommu_variant sun50i_h6_iommu = {
- .has_reset = true,
- };
-
- static const struct of_device_id sun50i_iommu_dt[] = {
-+ { .compatible = "allwinner,sun20i-d1-iommu", .data = &sun20i_d1_iommu },
- { .compatible = "allwinner,sun50i-h6-iommu", .data = &sun50i_h6_iommu },
- { /* sentinel */ },
- };
+++ /dev/null
-From 4c37ac95ee354857c8c662b6b7b4bc50eea23206 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Aug 2022 11:20:37 -0500
-Subject: [PATCH 053/117] riscv: dts: allwinner: d1: Add IOMMU node
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -188,6 +188,14 @@
- status = "disabled";
- };
-
-+ iommu: iommu@2010000 {
-+ compatible = "allwinner,sun20i-d1-iommu";
-+ reg = <0x2010000 0x10000>;
-+ interrupts = <80 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_IOMMU>;
-+ #iommu-cells = <1>;
-+ };
-+
- codec: audio-codec@2030000 {
- compatible = "simple-mfd", "syscon";
- reg = <0x2030000 0x1000>;
-@@ -681,6 +689,7 @@
- <&display_clocks CLK_MIXER0>;
- clock-names = "bus", "mod";
- resets = <&display_clocks RST_MIXER0>;
-+ iommus = <&iommu 2>;
-
- ports {
- #address-cells = <1>;
-@@ -703,6 +712,7 @@
- <&display_clocks CLK_MIXER1>;
- clock-names = "bus", "mod";
- resets = <&display_clocks RST_MIXER1>;
-+ iommus = <&iommu 2>;
-
- ports {
- #address-cells = <1>;
+++ /dev/null
-From 31857adcc9db7244a047a3a3550219f7559d8846 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 4 Aug 2021 21:36:26 -0500
-Subject: [PATCH 054/117] dt-bindings: leds: Add Allwinner A100 LED controller
-
-The Allwinner A100, R329, and D1 SoCs contain an LED controller designed
-to drive a series of RGB LED pixels. It supports PIO and DMA transfers,
-and has configurable timing and pixel format. All three implementations
-appear to be identical, so use the oldest as the fallback compatible.
-
-Series-changes: 2
- - Fixed typo leading to duplicate t1h-ns property
- - Removed "items" layer in definition of dmas/dma-names
- - Replaced uint32 type reference with maxItems in timing properties
-
-Series-changes: 3
- - Removed quotes from enumeration values
- - Added vendor prefix to timing/format properties
- - Renamed "format" property to "pixel-format" for clarity
- - Dropped "vled-supply" as it is unrelated to the controller hardware
-
-Series-changes: 4
- - Use "default" instead of "maxItems" for timing properties
-
-Series-changes: 5
- - A100 contains the original implementation, so use that as the base
- compatible string, and rename the binding to match
- - Add "unevaluatedProperties: false" to the child multi-led binding
-
-Acked-by: Maxime Ripard <maxime@cerno.tech>
-Reviewed-by: Rob Herring <robh@kernel.org>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../leds/allwinner,sun50i-a100-ledc.yaml | 139 ++++++++++++++++++
- 1 file changed, 139 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml
-@@ -0,0 +1,139 @@
-+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
-+%YAML 1.2
-+---
-+$id: http://devicetree.org/schemas/leds/allwinner,sun50i-a100-ledc.yaml#
-+$schema: http://devicetree.org/meta-schemas/core.yaml#
-+
-+title: Allwinner A100 LED Controller Bindings
-+
-+maintainers:
-+ - Samuel Holland <samuel@sholland.org>
-+
-+description:
-+ The LED controller found in Allwinner sunxi SoCs uses a one-wire serial
-+ interface to drive up to 1024 RGB LEDs.
-+
-+properties:
-+ compatible:
-+ oneOf:
-+ - const: allwinner,sun50i-a100-ledc
-+ - items:
-+ - enum:
-+ - allwinner,sun20i-d1-ledc
-+ - allwinner,sun50i-r329-ledc
-+ - const: allwinner,sun50i-a100-ledc
-+
-+ reg:
-+ maxItems: 1
-+
-+ "#address-cells":
-+ const: 1
-+
-+ "#size-cells":
-+ const: 0
-+
-+ interrupts:
-+ maxItems: 1
-+
-+ clocks:
-+ items:
-+ - description: Bus clock
-+ - description: Module clock
-+
-+ clock-names:
-+ items:
-+ - const: bus
-+ - const: mod
-+
-+ resets:
-+ maxItems: 1
-+
-+ dmas:
-+ maxItems: 1
-+ description: TX DMA channel
-+
-+ dma-names:
-+ const: tx
-+
-+ allwinner,pixel-format:
-+ description: Pixel format (subpixel transmission order), default is "grb"
-+ enum:
-+ - bgr
-+ - brg
-+ - gbr
-+ - grb
-+ - rbg
-+ - rgb
-+
-+ allwinner,t0h-ns:
-+ default: 336
-+ description: Length of high pulse when transmitting a "0" bit
-+
-+ allwinner,t0l-ns:
-+ default: 840
-+ description: Length of low pulse when transmitting a "0" bit
-+
-+ allwinner,t1h-ns:
-+ default: 882
-+ description: Length of high pulse when transmitting a "1" bit
-+
-+ allwinner,t1l-ns:
-+ default: 294
-+ description: Length of low pulse when transmitting a "1" bit
-+
-+ allwinner,treset-ns:
-+ default: 300000
-+ description: Minimum delay between transmission frames
-+
-+patternProperties:
-+ "^multi-led@[0-9a-f]+$":
-+ type: object
-+ $ref: leds-class-multicolor.yaml#
-+ unevaluatedProperties: false
-+ properties:
-+ reg:
-+ minimum: 0
-+ maximum: 1023
-+ description: Index of the LED in the series (must be contiguous)
-+
-+ required:
-+ - reg
-+
-+required:
-+ - compatible
-+ - reg
-+ - interrupts
-+ - clocks
-+ - clock-names
-+ - resets
-+ - dmas
-+ - dma-names
-+
-+additionalProperties: false
-+
-+examples:
-+ - |
-+ #include <dt-bindings/interrupt-controller/irq.h>
-+ #include <dt-bindings/leds/common.h>
-+
-+ ledc: led-controller@2008000 {
-+ compatible = "allwinner,sun20i-d1-ledc",
-+ "allwinner,sun50i-a100-ledc";
-+ reg = <0x2008000 0x400>;
-+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu 12>, <&ccu 34>;
-+ clock-names = "bus", "mod";
-+ resets = <&ccu 12>;
-+ dmas = <&dma 42>;
-+ dma-names = "tx";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ multi-led@0 {
-+ reg = <0x0>;
-+ color = <LED_COLOR_ID_RGB>;
-+ function = LED_FUNCTION_INDICATOR;
-+ };
-+ };
-+
-+...
+++ /dev/null
-From 352b296d30df06b880d2c7620910cd759dc2609d Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 26 Jun 2021 11:02:49 -0500
-Subject: [PATCH 055/117] leds: sun50i-a100: New driver for the A100 LED
- controller
-
-Some Allwinner sunxi SoCs, starting with the A100, contain an LED
-controller designed to drive RGB LED pixels. Add a driver for it using
-the multicolor LED framework, and with LEDs defined in the device tree.
-
-Series-changes: 2
- - Renamed from sunxi-ledc to sun50i-r329-ledc
- - Added missing "static" to functions/globals as reported by 0day bot
-
-Series-changes: 3
- - Added vendor prefix to timing/format properties
- - Renamed "format" property to "pixel-format" for clarity
- - Dropped "vled-supply" as it is unrelated to the controller hardware
- - Changed "writesl" to "iowrite32_rep" so the driver builds on hppa
-
-Series-changes: 4
- - Depend on LEDS_CLASS_MULTICOLOR
-
-Series-changes: 5
- - Rename the driver R329 -> A100, since that is the actual original
- implementation
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/leds/Kconfig | 9 +
- drivers/leds/Makefile | 1 +
- drivers/leds/leds-sun50i-a100.c | 554 ++++++++++++++++++++++++++++++++
- 3 files changed, 564 insertions(+)
- create mode 100644 drivers/leds/leds-sun50i-a100.c
-
---- a/drivers/leds/Kconfig
-+++ b/drivers/leds/Kconfig
-@@ -283,6 +283,15 @@ config LEDS_COBALT_RAQ
- help
- This option enables support for the Cobalt Raq series LEDs.
-
-+config LEDS_SUN50I_A100
-+ tristate "LED support for Allwinner A100 RGB LED controller"
-+ depends on LEDS_CLASS_MULTICOLOR && OF
-+ depends on ARCH_SUNXI || COMPILE_TEST
-+ help
-+ This option enables support for the RGB LED controller found
-+ in some Allwinner sunxi SoCs, includeing A100, R329, and D1.
-+ It uses a one-wire interface to control up to 1024 LEDs.
-+
- config LEDS_SUNFIRE
- tristate "LED support for SunFire servers."
- depends on LEDS_CLASS
---- a/drivers/leds/Makefile
-+++ b/drivers/leds/Makefile
-@@ -76,6 +76,7 @@ obj-$(CONFIG_LEDS_PWM) += leds-pwm.o
- obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o
- obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o
- obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o
-+obj-$(CONFIG_LEDS_SUN50I_A100) += leds-sun50i-a100.o
- obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o
- obj-$(CONFIG_LEDS_SYSCON) += leds-syscon.o
- obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o
---- /dev/null
-+++ b/drivers/leds/leds-sun50i-a100.c
-@@ -0,0 +1,554 @@
-+// SPDX-License-Identifier: GPL-2.0
-+//
-+// Copyright (c) 2021-2022 Samuel Holland <samuel@sholland.org>
-+//
-+// Partly based on drivers/leds/leds-turris-omnia.c, which is:
-+// Copyright (c) 2020 by Marek Behún <kabel@kernel.org>
-+//
-+
-+#include <linux/clk.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/dmaengine.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/led-class-multicolor.h>
-+#include <linux/leds.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/pm.h>
-+#include <linux/reset.h>
-+#include <linux/spinlock.h>
-+
-+#define LEDC_CTRL_REG 0x0000
-+#define LEDC_CTRL_REG_DATA_LENGTH (0x1fff << 16)
-+#define LEDC_CTRL_REG_RGB_MODE (0x7 << 6)
-+#define LEDC_CTRL_REG_LEDC_EN BIT(0)
-+#define LEDC_T01_TIMING_CTRL_REG 0x0004
-+#define LEDC_T01_TIMING_CTRL_REG_T1H (0x3f << 21)
-+#define LEDC_T01_TIMING_CTRL_REG_T1L (0x1f << 16)
-+#define LEDC_T01_TIMING_CTRL_REG_T0H (0x1f << 6)
-+#define LEDC_T01_TIMING_CTRL_REG_T0L (0x3f << 0)
-+#define LEDC_RESET_TIMING_CTRL_REG 0x000c
-+#define LEDC_RESET_TIMING_CTRL_REG_LED_NUM (0x3ff << 0)
-+#define LEDC_DATA_REG 0x0014
-+#define LEDC_DMA_CTRL_REG 0x0018
-+#define LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL (0x1f << 0)
-+#define LEDC_INT_CTRL_REG 0x001c
-+#define LEDC_INT_CTRL_REG_GLOBAL_INT_EN BIT(5)
-+#define LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN BIT(1)
-+#define LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN BIT(0)
-+#define LEDC_INT_STS_REG 0x0020
-+#define LEDC_INT_STS_REG_FIFO_CPUREQ_INT BIT(1)
-+#define LEDC_INT_STS_REG_TRANS_FINISH_INT BIT(0)
-+
-+#define LEDC_FIFO_DEPTH 32
-+#define LEDC_MAX_LEDS 1024
-+
-+#define LEDS_TO_BYTES(n) ((n) * sizeof(u32))
-+
-+struct sun50i_a100_ledc_led {
-+ struct led_classdev_mc mc_cdev;
-+ struct mc_subled subled_info[3];
-+};
-+
-+#define to_ledc_led(mc) container_of(mc, struct sun50i_a100_ledc_led, mc_cdev)
-+
-+struct sun50i_a100_ledc_timing {
-+ u32 t0h_ns;
-+ u32 t0l_ns;
-+ u32 t1h_ns;
-+ u32 t1l_ns;
-+ u32 treset_ns;
-+};
-+
-+struct sun50i_a100_ledc {
-+ struct device *dev;
-+ void __iomem *base;
-+ struct clk *bus_clk;
-+ struct clk *mod_clk;
-+ struct reset_control *reset;
-+
-+ u32 *buffer;
-+ struct dma_chan *dma_chan;
-+ dma_addr_t dma_handle;
-+ int pio_length;
-+ int pio_offset;
-+
-+ spinlock_t lock;
-+ int next_length;
-+ bool xfer_active;
-+
-+ u32 format;
-+ struct sun50i_a100_ledc_timing timing;
-+
-+ int num_leds;
-+ struct sun50i_a100_ledc_led leds[];
-+};
-+
-+static int sun50i_a100_ledc_dma_xfer(struct sun50i_a100_ledc *priv, int length)
-+{
-+ struct dma_async_tx_descriptor *desc;
-+ dma_cookie_t cookie;
-+
-+ desc = dmaengine_prep_slave_single(priv->dma_chan, priv->dma_handle,
-+ LEDS_TO_BYTES(length),
-+ DMA_MEM_TO_DEV, 0);
-+ if (!desc)
-+ return -ENOMEM;
-+
-+ cookie = dmaengine_submit(desc);
-+ if (dma_submit_error(cookie))
-+ return -EIO;
-+
-+ dma_async_issue_pending(priv->dma_chan);
-+
-+ return 0;
-+}
-+
-+static void sun50i_a100_ledc_pio_xfer(struct sun50i_a100_ledc *priv, int length)
-+{
-+ u32 burst, offset, val;
-+
-+ if (length) {
-+ /* New transfer (FIFO is empty). */
-+ offset = 0;
-+ burst = min(length, LEDC_FIFO_DEPTH);
-+ } else {
-+ /* Existing transfer (FIFO is half-full). */
-+ length = priv->pio_length;
-+ offset = priv->pio_offset;
-+ burst = min(length, LEDC_FIFO_DEPTH / 2);
-+ }
-+
-+ iowrite32_rep(priv->base + LEDC_DATA_REG, priv->buffer + offset, burst);
-+
-+ if (burst < length) {
-+ priv->pio_length = length - burst;
-+ priv->pio_offset = offset + burst;
-+
-+ if (!offset) {
-+ val = readl(priv->base + LEDC_INT_CTRL_REG);
-+ val |= LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;
-+ writel(val, priv->base + LEDC_INT_CTRL_REG);
-+ }
-+ } else {
-+ /* Disable the request IRQ once all data is written. */
-+ val = readl(priv->base + LEDC_INT_CTRL_REG);
-+ val &= ~LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN;
-+ writel(val, priv->base + LEDC_INT_CTRL_REG);
-+ }
-+}
-+
-+static void sun50i_a100_ledc_start_xfer(struct sun50i_a100_ledc *priv,
-+ int length)
-+{
-+ u32 val;
-+
-+ dev_dbg(priv->dev, "Updating %d LEDs\n", length);
-+
-+ val = readl(priv->base + LEDC_CTRL_REG);
-+ val &= ~LEDC_CTRL_REG_DATA_LENGTH;
-+ val |= length << 16 | LEDC_CTRL_REG_LEDC_EN;
-+ writel(val, priv->base + LEDC_CTRL_REG);
-+
-+ if (length > LEDC_FIFO_DEPTH) {
-+ int ret = sun50i_a100_ledc_dma_xfer(priv, length);
-+
-+ if (!ret)
-+ return;
-+
-+ dev_warn(priv->dev, "Failed to set up DMA: %d\n", ret);
-+ }
-+
-+ sun50i_a100_ledc_pio_xfer(priv, length);
-+}
-+
-+static irqreturn_t sun50i_a100_ledc_irq(int irq, void *dev_id)
-+{
-+ struct sun50i_a100_ledc *priv = dev_id;
-+ u32 val;
-+
-+ val = readl(priv->base + LEDC_INT_STS_REG);
-+
-+ if (val & LEDC_INT_STS_REG_TRANS_FINISH_INT) {
-+ int next_length;
-+
-+ /* Start the next transfer if needed. */
-+ spin_lock(&priv->lock);
-+ next_length = priv->next_length;
-+ if (next_length)
-+ priv->next_length = 0;
-+ else
-+ priv->xfer_active = false;
-+ spin_unlock(&priv->lock);
-+
-+ if (next_length)
-+ sun50i_a100_ledc_start_xfer(priv, next_length);
-+ } else if (val & LEDC_INT_STS_REG_FIFO_CPUREQ_INT) {
-+ /* Continue the current transfer. */
-+ sun50i_a100_ledc_pio_xfer(priv, 0);
-+ }
-+
-+ writel(val, priv->base + LEDC_INT_STS_REG);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static void sun50i_a100_ledc_brightness_set(struct led_classdev *cdev,
-+ enum led_brightness brightness)
-+{
-+ struct sun50i_a100_ledc *priv = dev_get_drvdata(cdev->dev->parent);
-+ struct led_classdev_mc *mc_cdev = lcdev_to_mccdev(cdev);
-+ struct sun50i_a100_ledc_led *led = to_ledc_led(mc_cdev);
-+ int addr = led - priv->leds;
-+ unsigned long flags;
-+ bool xfer_active;
-+ int next_length;
-+
-+ led_mc_calc_color_components(mc_cdev, brightness);
-+
-+ priv->buffer[addr] = led->subled_info[0].brightness << 16 |
-+ led->subled_info[1].brightness << 8 |
-+ led->subled_info[2].brightness;
-+
-+ dev_dbg(priv->dev, "LED %d -> #%06x\n", addr, priv->buffer[addr]);
-+
-+ spin_lock_irqsave(&priv->lock, flags);
-+ next_length = max(priv->next_length, addr + 1);
-+ xfer_active = priv->xfer_active;
-+ if (xfer_active)
-+ priv->next_length = next_length;
-+ else
-+ priv->xfer_active = true;
-+ spin_unlock_irqrestore(&priv->lock, flags);
-+
-+ if (!xfer_active)
-+ sun50i_a100_ledc_start_xfer(priv, next_length);
-+}
-+
-+static const char *const sun50i_a100_ledc_formats[] = {
-+ "rgb",
-+ "rbg",
-+ "grb",
-+ "gbr",
-+ "brg",
-+ "bgr",
-+};
-+
-+static int sun50i_a100_ledc_parse_format(const struct device_node *np,
-+ struct sun50i_a100_ledc *priv)
-+{
-+ const char *format = "grb";
-+ u32 i;
-+
-+ of_property_read_string(np, "allwinner,pixel-format", &format);
-+
-+ for (i = 0; i < ARRAY_SIZE(sun50i_a100_ledc_formats); ++i) {
-+ if (!strcmp(format, sun50i_a100_ledc_formats[i])) {
-+ priv->format = i;
-+ return 0;
-+ }
-+ }
-+
-+ dev_err(priv->dev, "Bad pixel format '%s'\n", format);
-+
-+ return -EINVAL;
-+}
-+
-+static void sun50i_a100_ledc_set_format(struct sun50i_a100_ledc *priv)
-+{
-+ u32 val;
-+
-+ val = readl(priv->base + LEDC_CTRL_REG);
-+ val &= ~LEDC_CTRL_REG_RGB_MODE;
-+ val |= priv->format << 6;
-+ writel(val, priv->base + LEDC_CTRL_REG);
-+}
-+
-+static const struct sun50i_a100_ledc_timing sun50i_a100_ledc_default_timing = {
-+ .t0h_ns = 336,
-+ .t0l_ns = 840,
-+ .t1h_ns = 882,
-+ .t1l_ns = 294,
-+ .treset_ns = 300000,
-+};
-+
-+static int sun50i_a100_ledc_parse_timing(const struct device_node *np,
-+ struct sun50i_a100_ledc *priv)
-+{
-+ struct sun50i_a100_ledc_timing *timing = &priv->timing;
-+
-+ *timing = sun50i_a100_ledc_default_timing;
-+
-+ of_property_read_u32(np, "allwinner,t0h-ns", &timing->t0h_ns);
-+ of_property_read_u32(np, "allwinner,t0l-ns", &timing->t0l_ns);
-+ of_property_read_u32(np, "allwinner,t1h-ns", &timing->t1h_ns);
-+ of_property_read_u32(np, "allwinner,t1l-ns", &timing->t1l_ns);
-+ of_property_read_u32(np, "allwinner,treset-ns", &timing->treset_ns);
-+
-+ return 0;
-+}
-+
-+static void sun50i_a100_ledc_set_timing(struct sun50i_a100_ledc *priv)
-+{
-+ const struct sun50i_a100_ledc_timing *timing = &priv->timing;
-+ unsigned long mod_freq = clk_get_rate(priv->mod_clk);
-+ u32 cycle_ns = NSEC_PER_SEC / mod_freq;
-+ u32 val;
-+
-+ val = (timing->t1h_ns / cycle_ns) << 21 |
-+ (timing->t1l_ns / cycle_ns) << 16 |
-+ (timing->t0h_ns / cycle_ns) << 6 |
-+ (timing->t0l_ns / cycle_ns);
-+ writel(val, priv->base + LEDC_T01_TIMING_CTRL_REG);
-+
-+ val = (timing->treset_ns / cycle_ns) << 16 |
-+ (priv->num_leds - 1);
-+ writel(val, priv->base + LEDC_RESET_TIMING_CTRL_REG);
-+}
-+
-+static int sun50i_a100_ledc_resume(struct device *dev)
-+{
-+ struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);
-+ u32 val;
-+ int ret;
-+
-+ ret = reset_control_deassert(priv->reset);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(priv->bus_clk);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ ret = clk_prepare_enable(priv->mod_clk);
-+ if (ret)
-+ goto err_disable_bus_clk;
-+
-+ sun50i_a100_ledc_set_format(priv);
-+ sun50i_a100_ledc_set_timing(priv);
-+
-+ /* The trigger level must be at least the burst length. */
-+ val = readl(priv->base + LEDC_DMA_CTRL_REG);
-+ val &= ~LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL;
-+ val |= LEDC_FIFO_DEPTH / 2;
-+ writel(val, priv->base + LEDC_DMA_CTRL_REG);
-+
-+ val = LEDC_INT_CTRL_REG_GLOBAL_INT_EN |
-+ LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN;
-+ writel(val, priv->base + LEDC_INT_CTRL_REG);
-+
-+ return 0;
-+
-+err_disable_bus_clk:
-+ clk_disable_unprepare(priv->bus_clk);
-+err_assert_reset:
-+ reset_control_assert(priv->reset);
-+
-+ return ret;
-+}
-+
-+static int sun50i_a100_ledc_suspend(struct device *dev)
-+{
-+ struct sun50i_a100_ledc *priv = dev_get_drvdata(dev);
-+
-+ clk_disable_unprepare(priv->mod_clk);
-+ clk_disable_unprepare(priv->bus_clk);
-+ reset_control_assert(priv->reset);
-+
-+ return 0;
-+}
-+
-+static void sun50i_a100_ledc_dma_cleanup(void *data)
-+{
-+ struct sun50i_a100_ledc *priv = data;
-+ struct device *dma_dev = dmaengine_get_dma_device(priv->dma_chan);
-+
-+ if (priv->buffer)
-+ dma_free_wc(dma_dev, LEDS_TO_BYTES(priv->num_leds),
-+ priv->buffer, priv->dma_handle);
-+ dma_release_channel(priv->dma_chan);
-+}
-+
-+static int sun50i_a100_ledc_probe(struct platform_device *pdev)
-+{
-+ const struct device_node *np = pdev->dev.of_node;
-+ struct dma_slave_config dma_cfg = {};
-+ struct led_init_data init_data = {};
-+ struct device *dev = &pdev->dev;
-+ struct device_node *child;
-+ struct sun50i_a100_ledc *priv;
-+ struct resource *mem;
-+ int count, irq, ret;
-+
-+ count = of_get_available_child_count(np);
-+ if (!count)
-+ return -ENODEV;
-+ if (count > LEDC_MAX_LEDS) {
-+ dev_err(dev, "Too many LEDs! (max is %d)\n", LEDC_MAX_LEDS);
-+ return -EINVAL;
-+ }
-+
-+ priv = devm_kzalloc(dev, struct_size(priv, leds, count), GFP_KERNEL);
-+ if (!priv)
-+ return -ENOMEM;
-+
-+ priv->dev = dev;
-+ priv->num_leds = count;
-+ spin_lock_init(&priv->lock);
-+ dev_set_drvdata(dev, priv);
-+
-+ ret = sun50i_a100_ledc_parse_format(np, priv);
-+ if (ret)
-+ return ret;
-+
-+ ret = sun50i_a100_ledc_parse_timing(np, priv);
-+ if (ret)
-+ return ret;
-+
-+ priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
-+ if (IS_ERR(priv->base))
-+ return PTR_ERR(priv->base);
-+
-+ priv->bus_clk = devm_clk_get(dev, "bus");
-+ if (IS_ERR(priv->bus_clk))
-+ return PTR_ERR(priv->bus_clk);
-+
-+ priv->mod_clk = devm_clk_get(dev, "mod");
-+ if (IS_ERR(priv->mod_clk))
-+ return PTR_ERR(priv->mod_clk);
-+
-+ priv->reset = devm_reset_control_get_exclusive(dev, NULL);
-+ if (IS_ERR(priv->reset))
-+ return PTR_ERR(priv->reset);
-+
-+ priv->dma_chan = dma_request_chan(dev, "tx");
-+ if (IS_ERR(priv->dma_chan))
-+ return PTR_ERR(priv->dma_chan);
-+
-+ ret = devm_add_action_or_reset(dev, sun50i_a100_ledc_dma_cleanup, priv);
-+ if (ret)
-+ return ret;
-+
-+ dma_cfg.dst_addr = mem->start + LEDC_DATA_REG;
-+ dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ dma_cfg.dst_maxburst = LEDC_FIFO_DEPTH / 2;
-+ ret = dmaengine_slave_config(priv->dma_chan, &dma_cfg);
-+ if (ret)
-+ return ret;
-+
-+ priv->buffer = dma_alloc_wc(dmaengine_get_dma_device(priv->dma_chan),
-+ LEDS_TO_BYTES(priv->num_leds),
-+ &priv->dma_handle, GFP_KERNEL);
-+ if (!priv->buffer)
-+ return -ENOMEM;
-+
-+ irq = platform_get_irq(pdev, 0);
-+ if (irq < 0)
-+ return irq;
-+
-+ ret = devm_request_irq(dev, irq, sun50i_a100_ledc_irq,
-+ 0, dev_name(dev), priv);
-+ if (ret)
-+ return ret;
-+
-+ ret = sun50i_a100_ledc_resume(dev);
-+ if (ret)
-+ return ret;
-+
-+ for_each_available_child_of_node(np, child) {
-+ struct sun50i_a100_ledc_led *led;
-+ struct led_classdev *cdev;
-+ u32 addr, color;
-+
-+ ret = of_property_read_u32(child, "reg", &addr);
-+ if (ret || addr >= count) {
-+ dev_err(dev, "LED 'reg' values must be from 0 to %d\n",
-+ priv->num_leds - 1);
-+ ret = -EINVAL;
-+ goto err_put_child;
-+ }
-+
-+ ret = of_property_read_u32(child, "color", &color);
-+ if (ret || color != LED_COLOR_ID_RGB) {
-+ dev_err(dev, "LED 'color' must be LED_COLOR_ID_RGB\n");
-+ ret = -EINVAL;
-+ goto err_put_child;
-+ }
-+
-+ led = &priv->leds[addr];
-+
-+ led->subled_info[0].color_index = LED_COLOR_ID_RED;
-+ led->subled_info[0].channel = 0;
-+ led->subled_info[1].color_index = LED_COLOR_ID_GREEN;
-+ led->subled_info[1].channel = 1;
-+ led->subled_info[2].color_index = LED_COLOR_ID_BLUE;
-+ led->subled_info[2].channel = 2;
-+
-+ led->mc_cdev.num_colors = ARRAY_SIZE(led->subled_info);
-+ led->mc_cdev.subled_info = led->subled_info;
-+
-+ cdev = &led->mc_cdev.led_cdev;
-+ cdev->max_brightness = U8_MAX;
-+ cdev->brightness_set = sun50i_a100_ledc_brightness_set;
-+
-+ init_data.fwnode = of_fwnode_handle(child);
-+
-+ ret = devm_led_classdev_multicolor_register_ext(dev,
-+ &led->mc_cdev,
-+ &init_data);
-+ if (ret) {
-+ dev_err(dev, "Failed to register LED %u: %d\n",
-+ addr, ret);
-+ goto err_put_child;
-+ }
-+ }
-+
-+ dev_info(dev, "Registered %d LEDs\n", priv->num_leds);
-+
-+ return 0;
-+
-+err_put_child:
-+ of_node_put(child);
-+ sun50i_a100_ledc_suspend(&pdev->dev);
-+
-+ return ret;
-+}
-+
-+static int sun50i_a100_ledc_remove(struct platform_device *pdev)
-+{
-+ sun50i_a100_ledc_suspend(&pdev->dev);
-+
-+ return 0;
-+}
-+
-+static void sun50i_a100_ledc_shutdown(struct platform_device *pdev)
-+{
-+ sun50i_a100_ledc_suspend(&pdev->dev);
-+}
-+
-+static const struct of_device_id sun50i_a100_ledc_of_match[] = {
-+ { .compatible = "allwinner,sun50i-a100-ledc" },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, sun50i_a100_ledc_of_match);
-+
-+static SIMPLE_DEV_PM_OPS(sun50i_a100_ledc_pm,
-+ sun50i_a100_ledc_suspend, sun50i_a100_ledc_resume);
-+
-+static struct platform_driver sun50i_a100_ledc_driver = {
-+ .probe = sun50i_a100_ledc_probe,
-+ .remove = sun50i_a100_ledc_remove,
-+ .shutdown = sun50i_a100_ledc_shutdown,
-+ .driver = {
-+ .name = "sun50i-a100-ledc",
-+ .of_match_table = sun50i_a100_ledc_of_match,
-+ .pm = pm_ptr(&sun50i_a100_ledc_pm),
-+ },
-+};
-+module_platform_driver(sun50i_a100_ledc_driver);
-+
-+MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
-+MODULE_DESCRIPTION("Allwinner A100 LED controller driver");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 0040f071ab45d3098b2aad7e28e07593a5740782 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 25 Aug 2022 23:19:40 -0500
-Subject: [PATCH 056/117] arm64: dts: allwinner: a100: Add LED controller node
-
-Allwinner A100 contains an LED controller. Add it to the devicetree.
-
-Commit-changes: 5
- - New patch for v5
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 14 ++++++++++++++
- 1 file changed, 14 insertions(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
-@@ -273,6 +273,20 @@
- #size-cells = <0>;
- };
-
-+ ledc: led-controller@5018000 {
-+ compatible = "allwinner,sun50i-a100-ledc";
-+ reg = <0x5018000 0x400>;
-+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
-+ clock-names = "bus", "mod";
-+ resets = <&ccu RST_BUS_LEDC>;
-+ dmas = <&dma 42>;
-+ dma-names = "tx";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- ths: thermal-sensor@5070400 {
- compatible = "allwinner,sun50i-a100-ths";
- reg = <0x05070400 0x100>;
+++ /dev/null
-From 595f76548e1d51a76b1ab201293ef441233921cf Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 23:02:43 -0500
-Subject: [PATCH 057/117] riscv: dts: allwinner: d1: Add LED controller node
-
-Allwinner D1 contains an LED controller. Add its devicetree node, as
-well as the pinmux used by the reference board design.
-
-Commit-changes: 5
- - New patch for v5
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 21 ++++++++++++++++++++
- 1 file changed, 21 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -116,6 +116,12 @@
- };
-
- /omit-if-no-ref/
-+ ledc_pc0_pin: ledc-pc0-pin {
-+ pins = "PC0";
-+ function = "ledc";
-+ };
-+
-+ /omit-if-no-ref/
- mmc0_pins: mmc0-pins {
- pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
- function = "mmc0";
-@@ -178,6 +184,21 @@
- #reset-cells = <1>;
- };
-
-+ ledc: led-controller@2008000 {
-+ compatible = "allwinner,sun20i-d1-ledc",
-+ "allwinner,sun50i-a100-ledc";
-+ reg = <0x2008000 0x400>;
-+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>;
-+ clock-names = "bus", "mod";
-+ resets = <&ccu RST_BUS_LEDC>;
-+ dmas = <&dma 42>;
-+ dma-names = "tx";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
- lradc: keys@2009800 {
- compatible = "allwinner,sun20i-d1-lradc",
- "allwinner,sun50i-r329-lradc";
+++ /dev/null
-From e6eb041b2099ec3d07a4ec391a06e86d7697c9d1 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 23:03:01 -0500
-Subject: [PATCH 058/117] riscv: dts: allwinner: d1: Add RGB LEDs to boards
-
-Some D1-based boards feature an onboard RGB LED. Enable them.
-
-Commit-changes: 5
- - New patch for v5
-
-Series-version: 5
-
-Series-to: Pavel Machek <pavel@ucw.cz>
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-Series-to: linux-leds@vger.kernel.org
-Series-cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
-Series-cc: Rob Herring <robh+dt@kernel.org>
-Series-cc: devicetree@vger.kernel.org
-Series-cc: linux-arm-kernel@lists.infradead.org
-Series-cc: linux-kernel@vger.kernel.org
-Series-cc: linux-riscv@lists.infradead.org
-Series-cc: linux-sunxi@lists.linux.dev
-
-Cover-letter:
-leds: Allwinner A100 LED controller support
-This series adds bindings and a driver for the RGB LED controller found
-in some Allwinner SoCs, starting with A100. The hardware in the R329 and
-D1 SoCs appears to be identical.
-
-Patch 3 is included because the LED controller binding requires the DMA
-properties. That patch was sent previously[1], but never got merged.
-
-Patches 5-6 depend on the D1 devicetree series[2], but the rest of this
-series can be merged without them.
-
-This driver was tested on the D1 Nezha board.
-
-[1]: https://lore.kernel.org/linux-arm-kernel/20201110040553.1381-7-frank@allwinnertech.com/
-[2]: https://lore.kernel.org/linux-riscv/20220815050815.22340-1-samuel@sholland.org/
-END
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts | 12 ++++++++++++
- arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts | 13 +++++++++++++
- 2 files changed, 25 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-@@ -58,6 +58,18 @@
- status = "okay";
- };
-
-+&ledc {
-+ pinctrl-0 = <&ledc_pc0_pin>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ multi-led@0 {
-+ reg = <0x0>;
-+ color = <LED_COLOR_ID_RGB>;
-+ function = LED_FUNCTION_STATUS;
-+ };
-+};
-+
- &lradc {
- status = "okay";
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-@@ -5,6 +5,7 @@
-
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/input/input.h>
-+#include <dt-bindings/leds/common.h>
-
- #include "sun20i-d1.dtsi"
- #include "sun20i-d1-common-regulators.dtsi"
-@@ -90,6 +91,18 @@
- };
- };
-
-+&ledc {
-+ pinctrl-0 = <&ledc_pc0_pin>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ multi-led@0 {
-+ reg = <0x0>;
-+ color = <LED_COLOR_ID_RGB>;
-+ function = LED_FUNCTION_STATUS;
-+ };
-+};
-+
- &lradc {
- status = "okay";
-
+++ /dev/null
-From effa2ef8717b0390e8fb0648e16df1b43610af53 Mon Sep 17 00:00:00 2001
-From: Ban Tao <fengzheng923@gmail.com>
-Date: Tue, 2 Mar 2021 20:40:23 +0800
-Subject: [PATCH 059/117] pwm: sun8i-v536: document device tree bindings
-
-This adds binding documentation for sun8i-v536 SoC PWM driver.
-
-Signed-off-by: Ban Tao <fengzheng923@gmail.com>
----
- .../bindings/pwm/pwm-sun8i-v536.txt | 24 +++++++++++++++++++
- 1 file changed, 24 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pwm/pwm-sun8i-v536.txt
-@@ -0,0 +1,24 @@
-+Allwinner sun8i-v536 SoC PWM controller
-+
-+Required properties:
-+ - compatible: should be "allwinner,<name>-pwm"
-+ "allwinner,sun8i-v833-pwm"
-+ "allwinner,sun8i-v536-pwm"
-+ "allwinner,sun50i-r818-pwm"
-+ "allwinner,sun50i-a133-pwm"
-+ "allwinner,sun50i-r329-pwm"
-+ - reg: physical base address and length of the controller's registers
-+ - #pwm-cells: should be 3. See pwm.txt in this directory for a description of
-+ the cells format.
-+ - clocks: From common clock binding, handle to the parent clock.
-+ - resets: From reset clock binding, handle to the parent clock.
-+
-+Example:
-+
-+ pwm: pwm@300a0000 {
-+ compatible = "allwinner,sun50i-r818-pwm";
-+ reg = <0x0300a000 0x3ff>;
-+ clocks = <&ccu CLK_BUS_PWM>;
-+ resets = <&ccu RST_BUS_PWM>;
-+ #pwm-cells = <3>;
-+ };
+++ /dev/null
-From 4919e67557eaebb9f155950e7cac547a507b59e5 Mon Sep 17 00:00:00 2001
-From: Ban Tao <fengzheng923@gmail.com>
-Date: Tue, 2 Mar 2021 20:37:37 +0800
-Subject: [PATCH 060/117] pwm: sunxi: Add Allwinner SoC PWM controller driver
-
-The Allwinner R818, A133, R329, V536 and V833 has a new PWM controller
-IP compared to the older Allwinner SoCs.
-
-Signed-off-by: Ban Tao <fengzheng923@gmail.com>
----
- MAINTAINERS | 6 +
- drivers/pwm/Kconfig | 11 +
- drivers/pwm/Makefile | 1 +
- drivers/pwm/pwm-sun8i-v536.c | 401 +++++++++++++++++++++++++++++++++++
- 4 files changed, 419 insertions(+)
- create mode 100644 drivers/pwm/pwm-sun8i-v536.c
-
---- a/MAINTAINERS
-+++ b/MAINTAINERS
-@@ -802,6 +802,12 @@ S: Maintained
- F: Documentation/devicetree/bindings/hwlock/allwinner,sun6i-a31-hwspinlock.yaml
- F: drivers/hwspinlock/sun6i_hwspinlock.c
-
-+ALLWINNER PWM DRIVER
-+M: Ban Tao <fengzheng923@gmail.com>
-+L: linux-pwm@vger.kernel.org
-+S: Maintained
-+F: drivers/pwm/pwm-sun8i-v536.c
-+
- ALLWINNER THERMAL DRIVER
- M: Vasily Khoruzhick <anarsoul@gmail.com>
- M: Yangtao Li <tiny.windzz@gmail.com>
---- a/drivers/pwm/Kconfig
-+++ b/drivers/pwm/Kconfig
-@@ -582,6 +582,17 @@ config PWM_SUN4I
- To compile this driver as a module, choose M here: the module
- will be called pwm-sun4i.
-
-+config PWM_SUN8I_V536
-+ tristate "Allwinner SUN8I_V536 PWM support"
-+ depends on ARCH_SUNXI || COMPILE_TEST
-+ depends on HAS_IOMEM && COMMON_CLK
-+ help
-+ Enhanced PWM framework driver for Allwinner R818, A133, R329,
-+ V536 and V833 SoCs.
-+
-+ To compile this driver as a module, choose M here: the module
-+ will be called pwm-sun8i-v536.
-+
- config PWM_SUNPLUS
- tristate "Sunplus PWM support"
- depends on ARCH_SUNPLUS || COMPILE_TEST
---- a/drivers/pwm/Makefile
-+++ b/drivers/pwm/Makefile
-@@ -54,6 +54,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
- obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
- obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o
- obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o
-+obj-$(CONFIG_PWM_SUN8I_V536) += pwm-sun8i-v536.o
- obj-$(CONFIG_PWM_SUNPLUS) += pwm-sunplus.o
- obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o
- obj-$(CONFIG_PWM_TIECAP) += pwm-tiecap.o
---- /dev/null
-+++ b/drivers/pwm/pwm-sun8i-v536.c
-@@ -0,0 +1,401 @@
-+// SPDX-License-Identifier: GPL-2.0-only
-+/*
-+ * Driver for Allwinner sun8i-v536 Pulse Width Modulation Controller
-+ *
-+ * Copyright (C) 2021 Ban Tao <fengzheng923@gmail.com>
-+ *
-+ *
-+ * Limitations:
-+ * - When PWM is disabled, the output is driven to inactive.
-+ * - If the register is reconfigured while PWM is running,
-+ * it does not complete the currently running period.
-+ * - If the user input duty is beyond acceptible limits,
-+ * -EINVAL is returned.
-+ */
-+
-+#include <linux/err.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of_device.h>
-+#include <linux/pwm.h>
-+#include <linux/clk.h>
-+#include <linux/reset.h>
-+
-+#define PWM_GET_CLK_OFFSET(chan) (0x20 + ((chan >> 1) * 0x4))
-+#define PWM_CLK_APB_SCR BIT(7)
-+#define PWM_DIV_M 0
-+#define PWM_DIV_M_MASK GENMASK(3, PWM_DIV_M)
-+
-+#define PWM_CLK_REG 0x40
-+#define PWM_CLK_GATING BIT(0)
-+
-+#define PWM_ENABLE_REG 0x80
-+#define PWM_EN BIT(0)
-+
-+#define PWM_CTL_REG(chan) (0x100 + 0x20 * chan)
-+#define PWM_ACT_STA BIT(8)
-+#define PWM_PRESCAL_K 0
-+#define PWM_PRESCAL_K_MASK GENMASK(7, PWM_PRESCAL_K)
-+
-+#define PWM_PERIOD_REG(chan) (0x104 + 0x20 * chan)
-+#define PWM_ENTIRE_CYCLE 16
-+#define PWM_ENTIRE_CYCLE_MASK GENMASK(31, PWM_ENTIRE_CYCLE)
-+#define PWM_ACT_CYCLE 0
-+#define PWM_ACT_CYCLE_MASK GENMASK(15, PWM_ACT_CYCLE)
-+
-+#define BIT_CH(bit, chan) ((bit) << (chan))
-+#define SET_BITS(shift, mask, reg, val) \
-+ (((reg) & ~mask) | (val << (shift)))
-+
-+#define PWM_OSC_CLK 24000000
-+#define PWM_PRESCALER_MAX 256
-+#define PWM_CLK_DIV_M__MAX 9
-+#define PWM_ENTIRE_CYCLE_MAX 65536
-+
-+struct sun8i_pwm_data {
-+ unsigned int npwm;
-+};
-+
-+struct sun8i_pwm_chip {
-+ struct pwm_chip chip;
-+ struct clk *clk;
-+ struct reset_control *rst_clk;
-+ void __iomem *base;
-+ const struct sun8i_pwm_data *data;
-+};
-+
-+static inline struct sun8i_pwm_chip *to_sun8i_pwm_chip(struct pwm_chip *chip)
-+{
-+ return container_of(chip, struct sun8i_pwm_chip, chip);
-+}
-+
-+static inline u32 sun8i_pwm_readl(struct sun8i_pwm_chip *chip,
-+ unsigned long offset)
-+{
-+ return readl(chip->base + offset);
-+}
-+
-+static inline void sun8i_pwm_writel(struct sun8i_pwm_chip *chip,
-+ u32 val, unsigned long offset)
-+{
-+ writel(val, chip->base + offset);
-+}
-+
-+static void sun8i_pwm_get_state(struct pwm_chip *chip,
-+ struct pwm_device *pwm,
-+ struct pwm_state *state)
-+{
-+ struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
-+ u64 clk_rate;
-+ u32 tmp, entire_cycles, active_cycles;
-+ unsigned int prescaler, div_m;
-+
-+ tmp = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+ if (tmp & PWM_CLK_APB_SCR)
-+ clk_rate = clk_get_rate(pc->clk);
-+ else
-+ clk_rate = PWM_OSC_CLK;
-+
-+ tmp = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+ div_m = 0x1 << (tmp & PWM_DIV_M_MASK);
-+
-+ tmp = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
-+ prescaler = (tmp & PWM_PRESCAL_K_MASK) + 1;
-+
-+ tmp = sun8i_pwm_readl(pc, PWM_PERIOD_REG(pwm->hwpwm));
-+ entire_cycles = (tmp >> PWM_ENTIRE_CYCLE) + 1;
-+ active_cycles = (tmp & PWM_ACT_CYCLE_MASK);
-+
-+ /* (clk / div_m / prescaler) / entire_cycles = NSEC_PER_SEC / period_ns. */
-+ state->period = DIV_ROUND_CLOSEST_ULL(entire_cycles * NSEC_PER_SEC,
-+ clk_rate) * div_m * prescaler;
-+ /* duty_ns / period_ns = active_cycles / entire_cycles. */
-+ state->duty_cycle = DIV_ROUND_CLOSEST_ULL(active_cycles * state->period,
-+ entire_cycles);
-+
-+ /* parsing polarity */
-+ tmp = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
-+ if (tmp & PWM_ACT_STA)
-+ state->polarity = PWM_POLARITY_NORMAL;
-+ else
-+ state->polarity = PWM_POLARITY_INVERSED;
-+
-+ /* parsing enabled */
-+ tmp = sun8i_pwm_readl(pc, PWM_ENABLE_REG);
-+ if (tmp & BIT_CH(PWM_EN, pwm->hwpwm))
-+ state->enabled = true;
-+ else
-+ state->enabled = false;
-+
-+ dev_dbg(chip->dev, "duty_ns=%lld period_ns=%lld polarity=%s enabled=%s.\n",
-+ state->duty_cycle, state->period,
-+ state->polarity ? "inversed":"normal",
-+ state->enabled ? "true":"false");
-+}
-+
-+static void sun8i_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
-+ enum pwm_polarity polarity)
-+{
-+ struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
-+ u32 temp;
-+
-+ temp = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
-+
-+ if (polarity == PWM_POLARITY_NORMAL)
-+ temp |= PWM_ACT_STA;
-+ else
-+ temp &= ~PWM_ACT_STA;
-+
-+ sun8i_pwm_writel(pc, temp, PWM_CTL_REG(pwm->hwpwm));
-+}
-+
-+static int sun8i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
-+ const struct pwm_state *state)
-+{
-+ struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
-+ unsigned long long c;
-+ unsigned long entire_cycles, active_cycles;
-+ unsigned int div_m, prescaler;
-+ u64 duty_ns = state->duty_cycle, period_ns = state->period;
-+ u32 config;
-+ int ret = 0;
-+
-+ if (period_ns > 334) {
-+ /* if freq < 3M, then select 24M clock */
-+ c = PWM_OSC_CLK;
-+ config = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+ config &= ~PWM_CLK_APB_SCR;
-+ sun8i_pwm_writel(pc, config, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+ } else {
-+ /* if freq > 3M, then select APB as clock */
-+ c = clk_get_rate(pc->clk);
-+ config = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+ config |= PWM_CLK_APB_SCR;
-+ sun8i_pwm_writel(pc, config, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+ }
-+
-+ dev_dbg(chip->dev, "duty_ns=%lld period_ns=%lld c =%llu.\n",
-+ duty_ns, period_ns, c);
-+
-+ /*
-+ * (clk / div_m / prescaler) / entire_cycles = NSEC_PER_SEC / period_ns.
-+ * So, entire_cycles = clk * period_ns / NSEC_PER_SEC / div_m / prescaler.
-+ */
-+ c = c * period_ns;
-+ c = DIV_ROUND_CLOSEST_ULL(c, NSEC_PER_SEC);
-+ for (div_m = 0; div_m < PWM_CLK_DIV_M__MAX; div_m++) {
-+ for (prescaler = 0; prescaler < PWM_PRESCALER_MAX; prescaler++) {
-+ /*
-+ * actual prescaler = prescaler(reg value) + 1.
-+ * actual div_m = 0x1 << div_m(reg value).
-+ */
-+ entire_cycles = ((unsigned long)c >> div_m)/(prescaler + 1);
-+ if (entire_cycles <= PWM_ENTIRE_CYCLE_MAX)
-+ goto calc_end;
-+ }
-+ }
-+ ret = -EINVAL;
-+ goto exit;
-+
-+calc_end:
-+ /*
-+ * duty_ns / period_ns = active_cycles / entire_cycles.
-+ * So, active_cycles = entire_cycles * duty_ns / period_ns.
-+ */
-+ c = (unsigned long long)entire_cycles * duty_ns;
-+ c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
-+ active_cycles = c;
-+ if (entire_cycles == 0)
-+ entire_cycles++;
-+
-+ /* config clk div_m*/
-+ config = sun8i_pwm_readl(pc, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+ config = SET_BITS(PWM_DIV_M, PWM_DIV_M_MASK, config, div_m);
-+ sun8i_pwm_writel(pc, config, PWM_GET_CLK_OFFSET(pwm->hwpwm));
-+
-+ /* config prescaler */
-+ config = sun8i_pwm_readl(pc, PWM_CTL_REG(pwm->hwpwm));
-+ config = SET_BITS(PWM_PRESCAL_K, PWM_PRESCAL_K_MASK, config, prescaler);
-+ sun8i_pwm_writel(pc, config, PWM_CTL_REG(pwm->hwpwm));
-+
-+ /* config active and period cycles */
-+ config = sun8i_pwm_readl(pc, PWM_PERIOD_REG(pwm->hwpwm));
-+ config = SET_BITS(PWM_ACT_CYCLE, PWM_ACT_CYCLE_MASK, config, active_cycles);
-+ config = SET_BITS(PWM_ENTIRE_CYCLE, PWM_ENTIRE_CYCLE_MASK,
-+ config, (entire_cycles - 1));
-+ sun8i_pwm_writel(pc, config, PWM_PERIOD_REG(pwm->hwpwm));
-+
-+ dev_dbg(chip->dev, "active_cycles=%lu entire_cycles=%lu prescaler=%u div_m=%u\n",
-+ active_cycles, entire_cycles, prescaler, div_m);
-+
-+exit:
-+ return ret;
-+}
-+
-+static void sun8i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm,
-+ bool enable)
-+{
-+ struct sun8i_pwm_chip *pc = to_sun8i_pwm_chip(chip);
-+ u32 clk, pwm_en;
-+
-+ clk = sun8i_pwm_readl(pc, PWM_CLK_REG);
-+ pwm_en = sun8i_pwm_readl(pc, PWM_ENABLE_REG);
-+
-+ if (enable) {
-+ clk |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
-+ sun8i_pwm_writel(pc, clk, PWM_CLK_REG);
-+
-+ pwm_en |= BIT_CH(PWM_EN, pwm->hwpwm);
-+ sun8i_pwm_writel(pc, pwm_en, PWM_ENABLE_REG);
-+ } else {
-+ pwm_en &= ~BIT_CH(PWM_EN, pwm->hwpwm);
-+ sun8i_pwm_writel(pc, pwm_en, PWM_ENABLE_REG);
-+
-+ clk &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
-+ sun8i_pwm_writel(pc, clk, PWM_CLK_REG);
-+ }
-+}
-+
-+static int sun8i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
-+ const struct pwm_state *state)
-+{
-+ struct pwm_state curstate;
-+ int ret;
-+
-+ pwm_get_state(pwm, &curstate);
-+
-+ ret = sun8i_pwm_config(chip, pwm, state);
-+
-+ if (state->polarity != curstate.polarity)
-+ sun8i_pwm_set_polarity(chip, pwm, state->polarity);
-+
-+ if (state->enabled != curstate.enabled)
-+ sun8i_pwm_enable(chip, pwm, state->enabled);
-+
-+ return ret;
-+}
-+
-+static const struct pwm_ops sun8i_pwm_ops = {
-+ .get_state = sun8i_pwm_get_state,
-+ .apply = sun8i_pwm_apply,
-+ .owner = THIS_MODULE,
-+};
-+
-+static const struct sun8i_pwm_data sun8i_pwm_data_c9 = {
-+ .npwm = 9,
-+};
-+
-+static const struct sun8i_pwm_data sun50i_pwm_data_c16 = {
-+ .npwm = 16,
-+};
-+
-+static const struct of_device_id sun8i_pwm_dt_ids[] = {
-+ {
-+ .compatible = "allwinner,sun8i-v536-pwm",
-+ .data = &sun8i_pwm_data_c9,
-+ }, {
-+ .compatible = "allwinner,sun50i-r818-pwm",
-+ .data = &sun50i_pwm_data_c16,
-+ }, {
-+ /* sentinel */
-+ },
-+};
-+MODULE_DEVICE_TABLE(of, sun8i_pwm_dt_ids);
-+
-+static int sun8i_pwm_probe(struct platform_device *pdev)
-+{
-+ struct sun8i_pwm_chip *pc;
-+ int ret;
-+
-+ pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
-+ if (!pc)
-+ return dev_err_probe(&pdev->dev, -ENOMEM,
-+ "memory allocation failed\n");
-+
-+ pc->data = of_device_get_match_data(&pdev->dev);
-+ if (!pc->data)
-+ return dev_err_probe(&pdev->dev, -ENODEV,
-+ "can't get match data\n");
-+
-+ pc->base = devm_platform_ioremap_resource(pdev, 0);
-+ if (IS_ERR(pc->base))
-+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->base),
-+ "can't remap pwm resource\n");
-+
-+ pc->clk = devm_clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(pc->clk))
-+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
-+ "get clock failed\n");
-+
-+ pc->rst_clk = devm_reset_control_get_exclusive(&pdev->dev, NULL);
-+ if (IS_ERR(pc->rst_clk))
-+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->rst_clk),
-+ "get reset failed\n");
-+
-+ /* Deassert reset */
-+ ret = reset_control_deassert(pc->rst_clk);
-+ if (ret < 0)
-+ return dev_err_probe(&pdev->dev, ret,
-+ "cannot deassert reset control\n");
-+
-+ ret = clk_prepare_enable(pc->clk);
-+ if (ret) {
-+ dev_err(&pdev->dev, "cannot prepare and enable clk %pe\n",
-+ ERR_PTR(ret));
-+ goto err_clk;
-+ }
-+
-+ pc->chip.dev = &pdev->dev;
-+ pc->chip.ops = &sun8i_pwm_ops;
-+ pc->chip.npwm = pc->data->npwm;
-+ pc->chip.of_xlate = of_pwm_xlate_with_flags;
-+ pc->chip.base = -1;
-+ pc->chip.of_pwm_n_cells = 3;
-+
-+ ret = pwmchip_add(&pc->chip);
-+ if (ret < 0) {
-+ dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
-+ goto err_pwm_add;
-+ }
-+
-+ platform_set_drvdata(pdev, pc);
-+
-+ return 0;
-+
-+err_pwm_add:
-+ clk_disable_unprepare(pc->clk);
-+err_clk:
-+ reset_control_assert(pc->rst_clk);
-+
-+ return ret;
-+}
-+
-+static int sun8i_pwm_remove(struct platform_device *pdev)
-+{
-+ struct sun8i_pwm_chip *pc = platform_get_drvdata(pdev);
-+ int ret;
-+
-+ ret = pwmchip_remove(&pc->chip);
-+ if (ret)
-+ return ret;
-+
-+ clk_disable_unprepare(pc->clk);
-+ reset_control_assert(pc->rst_clk);
-+
-+ return 0;
-+}
-+
-+static struct platform_driver sun8i_pwm_driver = {
-+ .driver = {
-+ .name = "sun8i-pwm-v536",
-+ .of_match_table = sun8i_pwm_dt_ids,
-+ },
-+ .probe = sun8i_pwm_probe,
-+ .remove = sun8i_pwm_remove,
-+};
-+module_platform_driver(sun8i_pwm_driver);
-+
-+MODULE_ALIAS("platform:sun8i-v536-pwm");
-+MODULE_AUTHOR("Ban Tao <fengzheng923@gmail.com>");
-+MODULE_DESCRIPTION("Allwinner sun8i-v536 PWM driver");
-+MODULE_LICENSE("GPL v2");
+++ /dev/null
-From 2f452dd6047126c42a0ad32ef0f10145c6047d66 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 6 Jun 2021 11:05:20 -0500
-Subject: [PATCH 061/117] squash? pwm: sunxi: Add Allwinner SoC PWM controller
- driver
-
----
- drivers/pwm/Kconfig | 4 ++--
- drivers/pwm/pwm-sun8i-v536.c | 6 +-----
- 2 files changed, 3 insertions(+), 7 deletions(-)
-
---- a/drivers/pwm/Kconfig
-+++ b/drivers/pwm/Kconfig
-@@ -583,11 +583,11 @@ config PWM_SUN4I
- will be called pwm-sun4i.
-
- config PWM_SUN8I_V536
-- tristate "Allwinner SUN8I_V536 PWM support"
-+ tristate "Allwinner SUN8I V536 enhanced PWM support"
- depends on ARCH_SUNXI || COMPILE_TEST
- depends on HAS_IOMEM && COMMON_CLK
- help
-- Enhanced PWM framework driver for Allwinner R818, A133, R329,
-+ Enhanced PWM framework driver for Allwinner A133, D1, R329, R818,
- V536 and V833 SoCs.
-
- To compile this driver as a module, choose M here: the module
---- a/drivers/pwm/pwm-sun8i-v536.c
-+++ b/drivers/pwm/pwm-sun8i-v536.c
-@@ -373,12 +373,8 @@ err_clk:
- static int sun8i_pwm_remove(struct platform_device *pdev)
- {
- struct sun8i_pwm_chip *pc = platform_get_drvdata(pdev);
-- int ret;
--
-- ret = pwmchip_remove(&pc->chip);
-- if (ret)
-- return ret;
-
-+ pwmchip_remove(&pc->chip);
- clk_disable_unprepare(pc->clk);
- reset_control_assert(pc->rst_clk);
-
+++ /dev/null
-From 8bb576d8640fdf896650a4d4a1b2e60254d75eb2 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 6 Jun 2021 10:56:25 -0500
-Subject: [PATCH 062/117] pwm: sun8i-v536: Add support for the Allwinner D1
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/pwm/pwm-sun8i-v536.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/drivers/pwm/pwm-sun8i-v536.c
-+++ b/drivers/pwm/pwm-sun8i-v536.c
-@@ -285,6 +285,10 @@ static const struct sun8i_pwm_data sun8i
- .npwm = 9,
- };
-
-+static const struct sun8i_pwm_data sun20i_pwm_data_c8 = {
-+ .npwm = 8,
-+};
-+
- static const struct sun8i_pwm_data sun50i_pwm_data_c16 = {
- .npwm = 16,
- };
-@@ -294,6 +298,9 @@ static const struct of_device_id sun8i_p
- .compatible = "allwinner,sun8i-v536-pwm",
- .data = &sun8i_pwm_data_c9,
- }, {
-+ .compatible = "allwinner,sun20i-d1-pwm",
-+ .data = &sun20i_pwm_data_c8,
-+ }, {
- .compatible = "allwinner,sun50i-r818-pwm",
- .data = &sun50i_pwm_data_c16,
- }, {
+++ /dev/null
-From 2ee8994e4db3978261e6c644e897400c4df5edeb Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:24:52 -0500
-Subject: [PATCH 063/117] riscv: dts: allwinner: d1: Add PWM support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 35 ++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -155,6 +155,30 @@
- };
-
- /omit-if-no-ref/
-+ pwm0_pd16_pin: pwm0-pd16-pin {
-+ pins = "PD16";
-+ function = "pwm0";
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm2_pd18_pin: pwm2-pd18-pin {
-+ pins = "PD18";
-+ function = "pwm2";
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm4_pd20_pin: pwm4-pd20-pin {
-+ pins = "PD20";
-+ function = "pwm4";
-+ };
-+
-+ /omit-if-no-ref/
-+ pwm7_pd22_pin: pwm7-pd22-pin {
-+ pins = "PD22";
-+ function = "pwm7";
-+ };
-+
-+ /omit-if-no-ref/
- uart0_pb8_pins: uart0-pb8-pins {
- pins = "PB8", "PB9";
- function = "uart0";
-@@ -173,6 +197,17 @@
- };
- };
-
-+ pwm: pwm@2000c00 {
-+ compatible = "allwinner,sun20i-d1-pwm";
-+ reg = <0x2000c00 0x400>;
-+ interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_PWM>, <&osc24M>;
-+ clock-names = "bus", "mod";
-+ resets = <&ccu RST_BUS_PWM>;
-+ status = "disabled";
-+ #pwm-cells = <3>;
-+ };
-+
- ccu: clock-controller@2001000 {
- compatible = "allwinner,sun20i-d1-ccu";
- reg = <0x2001000 0x1000>;
+++ /dev/null
-From 5479c8efb6ffbbc8b7fd1068337037faf9c20a36 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:25:40 -0500
-Subject: [PATCH 064/117] riscv: dts: allwinner: d1: Hook up PWM-controlled CPU
- voltage regulators
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 19 +++++++++++--------
- .../sun20i-d1-dongshan-nezha-stu.dts | 19 +++++++++++--------
- .../boot/dts/allwinner/sun20i-d1-nezha.dts | 19 +++++++++++--------
- 3 files changed, 33 insertions(+), 24 deletions(-)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-@@ -48,16 +48,13 @@
- };
- };
-
-- /*
-- * This regulator is PWM-controlled, but the PWM controller is not
-- * yet supported, so fix the regulator to its default voltage.
-- */
- reg_vdd_cpu: vdd-cpu {
-- compatible = "regulator-fixed";
-+ compatible = "pwm-regulator";
-+ pwms = <&pwm 0 50000 0>;
-+ pwm-supply = <®_vcc>;
- regulator-name = "vdd-cpu";
-- regulator-min-microvolt = <1100000>;
-- regulator-max-microvolt = <1100000>;
-- vin-supply = <®_vcc>;
-+ regulator-min-microvolt = <810000>;
-+ regulator-max-microvolt = <1160000>;
- };
-
- wifi_pwrseq: wifi-pwrseq {
-@@ -254,6 +251,12 @@
- };
- };
-
-+&pwm {
-+ pinctrl-0 = <&pwm0_pd16_pin>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
- &uart0 {
- pinctrl-0 = <&uart0_pb8_pins>;
- pinctrl-names = "default";
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
-@@ -43,16 +43,13 @@
- vin-supply = <®_vcc>;
- };
-
-- /*
-- * This regulator is PWM-controlled, but the PWM controller is not
-- * yet supported, so fix the regulator to its default voltage.
-- */
- reg_vdd_cpu: vdd-cpu {
-- compatible = "regulator-fixed";
-+ compatible = "pwm-regulator";
-+ pwms = <&pwm 0 50000 0>;
-+ pwm-supply = <®_vcc>;
- regulator-name = "vdd-cpu";
-- regulator-min-microvolt = <1100000>;
-- regulator-max-microvolt = <1100000>;
-- vin-supply = <®_vcc>;
-+ regulator-min-microvolt = <810000>;
-+ regulator-max-microvolt = <1160000>;
- };
- };
-
-@@ -95,6 +92,12 @@
- status = "okay";
- };
-
-+&pwm {
-+ pinctrl-0 = <&pwm0_pd16_pin>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
- &uart0 {
- pinctrl-0 = <&uart0_pb8_pins>;
- pinctrl-names = "default";
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-@@ -35,16 +35,13 @@
- vin-supply = <®_vcc>;
- };
-
-- /*
-- * This regulator is PWM-controlled, but the PWM controller is not
-- * yet supported, so fix the regulator to its default voltage.
-- */
- reg_vdd_cpu: vdd-cpu {
-- compatible = "regulator-fixed";
-+ compatible = "pwm-regulator";
-+ pwms = <&pwm 0 50000 0>;
-+ pwm-supply = <®_vcc>;
- regulator-name = "vdd-cpu";
-- regulator-min-microvolt = <1100000>;
-- regulator-max-microvolt = <1100000>;
-- vin-supply = <®_vcc>;
-+ regulator-min-microvolt = <810000>;
-+ regulator-max-microvolt = <1160000>;
- };
-
- wifi_pwrseq: wifi-pwrseq {
-@@ -155,6 +152,12 @@
- status = "okay";
- };
-
-+&pwm {
-+ pinctrl-0 = <&pwm0_pd16_pin>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
- &uart0 {
- pinctrl-0 = <&uart0_pb8_pins>;
- pinctrl-names = "default";
+++ /dev/null
-From 29360e65c326ea8bbac6e63b42aa91fb8f14d3bf Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:57:13 -0500
-Subject: [PATCH 065/117] riscv: dts: allwinner: mangopi-mq-pro: Add PWM LED
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts | 12 ++++++++++++
- 1 file changed, 12 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-mangopi-mq-pro.dts
-@@ -4,6 +4,7 @@
- /dts-v1/;
-
- #include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-
- #include "sun20i-d1.dtsi"
- #include "sun20i-d1-common-regulators.dtsi"
-@@ -22,6 +23,17 @@
- stdout-path = "serial0:115200n8";
- };
-
-+ leds {
-+ compatible = "pwm-leds";
-+
-+ led {
-+ color = <LED_COLOR_ID_BLUE>;
-+ function = LED_FUNCTION_STATUS;
-+ max-brightness = <255>;
-+ pwms = <&pwm 2 50000 0>;
-+ };
-+ };
-+
- reg_avdd2v8: avdd2v8 {
- compatible = "regulator-fixed";
- regulator-name = "avdd2v8";
+++ /dev/null
-From bccb19038038c7377275d74bb815f5f9363ba2e3 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 13 Nov 2021 10:08:41 -0600
-Subject: [PATCH 066/117] ASoC: dt-bindings: sun4i-spdif: Require resets for H6
-
-The H6 variant has a module reset, and it is used by the driver. So the
-resets property should be required in the binding for this variant.
-
-Fixes: b20453031472 ("dt-bindings: sound: sun4i-spdif: Add Allwinner H6 compatible")
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
-+++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
-@@ -61,6 +61,7 @@ allOf:
- enum:
- - allwinner,sun6i-a31-spdif
- - allwinner,sun8i-h3-spdif
-+ - allwinner,sun50i-h6-spdif
-
- then:
- required:
+++ /dev/null
-From 4e72722bfb7dec028e11278a924bb8bef3e10897 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 13 Nov 2021 10:48:24 -0600
-Subject: [PATCH 067/117] ASoC: dt-bindings: sun4i-spdif: Add compatible for D1
-
-D1 mostly keeps the existing register layout, but it separates the
-module clock into separate clocks for the RX block and the TX block.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../sound/allwinner,sun4i-a10-spdif.yaml | 54 +++++++++++++++----
- 1 file changed, 44 insertions(+), 10 deletions(-)
-
---- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
-+++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-spdif.yaml
-@@ -18,10 +18,12 @@ properties:
-
- compatible:
- oneOf:
-- - const: allwinner,sun4i-a10-spdif
-- - const: allwinner,sun6i-a31-spdif
-- - const: allwinner,sun8i-h3-spdif
-- - const: allwinner,sun50i-h6-spdif
-+ - enum:
-+ - allwinner,sun4i-a10-spdif
-+ - allwinner,sun6i-a31-spdif
-+ - allwinner,sun8i-h3-spdif
-+ - allwinner,sun20i-d1-spdif
-+ - allwinner,sun50i-h6-spdif
- - items:
- - const: allwinner,sun8i-a83t-spdif
- - const: allwinner,sun8i-h3-spdif
-@@ -36,14 +38,12 @@ properties:
- maxItems: 1
-
- clocks:
-- items:
-- - description: Bus Clock
-- - description: Module Clock
-+ minItems: 2
-+ maxItems: 3
-
- clock-names:
-- items:
-- - const: apb
-- - const: spdif
-+ minItems: 2
-+ maxItems: 3
-
- # Even though it only applies to subschemas under the conditionals,
- # not listing them here will trigger a warning because of the
-@@ -59,8 +59,42 @@ allOf:
- compatible:
- contains:
- enum:
-+ - allwinner,sun20i-d1-spdif
-+
-+ then:
-+ properties:
-+ clocks:
-+ items:
-+ - description: Bus Clock
-+ - description: RX Module Clock
-+ - description: TX Module Clock
-+
-+ clock-names:
-+ items:
-+ - const: apb
-+ - const: rx
-+ - const: tx
-+
-+ else:
-+ properties:
-+ clocks:
-+ items:
-+ - description: Bus Clock
-+ - description: Module Clock
-+
-+ clock-names:
-+ items:
-+ - const: apb
-+ - const: spdif
-+
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ enum:
- - allwinner,sun6i-a31-spdif
- - allwinner,sun8i-h3-spdif
-+ - allwinner,sun20i-d1-spdif
- - allwinner,sun50i-h6-spdif
-
- then:
+++ /dev/null
-From 1d85b3609cf4239f7e971b839f1ab985413cd560 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 13 Nov 2021 11:12:14 -0600
-Subject: [PATCH 068/117] ASoC: sun4i-spdif: Assert reset when removing the
- device
-
-This completes reversing the process done in the probe function.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-spdif.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/sound/soc/sunxi/sun4i-spdif.c
-+++ b/sound/soc/sunxi/sun4i-spdif.c
-@@ -710,10 +710,14 @@ err_unregister:
-
- static int sun4i_spdif_remove(struct platform_device *pdev)
- {
-+ struct sun4i_spdif_dev *host = dev_get_drvdata(&pdev->dev);
-+
- pm_runtime_disable(&pdev->dev);
- if (!pm_runtime_status_suspended(&pdev->dev))
- sun4i_spdif_runtime_suspend(&pdev->dev);
-
-+ reset_control_assert(host->rst);
-+
- return 0;
- }
-
+++ /dev/null
-From 0efd742482dbe4b17a441eab5c57231d65f9a852 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 13 Nov 2021 11:14:30 -0600
-Subject: [PATCH 069/117] ASoC: sun4i-spdif: Simplify code around optional
- resets
-
-The driver does not need to care about which variants have a reset;
-the devicetree binding already enforces that the necessary resources are
-provided. Simplify the logic by always calling the optional getter,
-which will return NULL if no reset reference is found.
-
-Also clean up the error handling, which should not print a misleading
-error in the EPROBE_DEFER case.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-spdif.c | 22 ++++++----------------
- 1 file changed, 6 insertions(+), 16 deletions(-)
-
---- a/sound/soc/sunxi/sun4i-spdif.c
-+++ b/sound/soc/sunxi/sun4i-spdif.c
-@@ -170,12 +170,10 @@
- * struct sun4i_spdif_quirks - Differences between SoC variants.
- *
- * @reg_dac_txdata: TX FIFO offset for DMA config.
-- * @has_reset: SoC needs reset deasserted.
- * @val_fctl_ftx: TX FIFO flush bitmask.
- */
- struct sun4i_spdif_quirks {
- unsigned int reg_dac_txdata;
-- bool has_reset;
- unsigned int val_fctl_ftx;
- };
-
-@@ -546,19 +544,16 @@ static const struct sun4i_spdif_quirks s
- static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
- .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
- .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
-- .has_reset = true,
- };
-
- static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
- .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
- .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
-- .has_reset = true,
- };
-
- static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
- .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
- .val_fctl_ftx = SUN50I_H6_SPDIF_FCTL_FTX,
-- .has_reset = true,
- };
-
- static const struct of_device_id sun4i_spdif_of_match[] = {
-@@ -672,17 +667,12 @@ static int sun4i_spdif_probe(struct plat
-
- platform_set_drvdata(pdev, host);
-
-- if (quirks->has_reset) {
-- host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
-- NULL);
-- if (PTR_ERR(host->rst) == -EPROBE_DEFER) {
-- ret = -EPROBE_DEFER;
-- dev_err(&pdev->dev, "Failed to get reset: %d\n", ret);
-- return ret;
-- }
-- if (!IS_ERR(host->rst))
-- reset_control_deassert(host->rst);
-- }
-+ host->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
-+ if (IS_ERR(host->rst))
-+ return dev_err_probe(&pdev->dev, PTR_ERR(host->rst),
-+ "Failed to get reset\n");
-+
-+ reset_control_deassert(host->rst);
-
- ret = devm_snd_soc_register_component(&pdev->dev,
- &sun4i_spdif_component, &sun4i_spdif_dai, 1);
+++ /dev/null
-From b42a9e0cf6b0ca78b4ef5310de967d515a3cca03 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:53:16 -0500
-Subject: [PATCH 070/117] ASoC: sun4i-spdif: Add support for separate RX/TX
- clocks
-
-On older variants of the hardware, the RX and TX blocks share a single
-module clock, named "spdif" in the DT binding. The D1 variant has
-separate RX and TX clocks, so the TX module clock is named "tx" in the
-binding. To support this, supply the clock name in the quirks structure.
-
-Since the driver supports only TX, only the TX clock name is needed.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-spdif.c | 24 +++++++++++++++---------
- 1 file changed, 15 insertions(+), 9 deletions(-)
-
---- a/sound/soc/sunxi/sun4i-spdif.c
-+++ b/sound/soc/sunxi/sun4i-spdif.c
-@@ -169,18 +169,20 @@
- /**
- * struct sun4i_spdif_quirks - Differences between SoC variants.
- *
-+ * @tx_clk_name: firmware name for the TX clock reference.
- * @reg_dac_txdata: TX FIFO offset for DMA config.
- * @val_fctl_ftx: TX FIFO flush bitmask.
- */
- struct sun4i_spdif_quirks {
-+ const char *tx_clk_name;
- unsigned int reg_dac_txdata;
- unsigned int val_fctl_ftx;
- };
-
- struct sun4i_spdif_dev {
- struct platform_device *pdev;
-- struct clk *spdif_clk;
- struct clk *apb_clk;
-+ struct clk *tx_clk;
- struct reset_control *rst;
- struct snd_soc_dai_driver cpu_dai_drv;
- struct regmap *regmap;
-@@ -313,7 +315,7 @@ static int sun4i_spdif_hw_params(struct
- return -EINVAL;
- }
-
-- ret = clk_set_rate(host->spdif_clk, mclk);
-+ ret = clk_set_rate(host->tx_clk, mclk);
- if (ret < 0) {
- dev_err(&pdev->dev,
- "Setting SPDIF clock rate for %d Hz failed!\n", mclk);
-@@ -537,21 +539,25 @@ static struct snd_soc_dai_driver sun4i_s
- };
-
- static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
-+ .tx_clk_name = "spdif",
- .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
- .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
- };
-
- static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
-+ .tx_clk_name = "spdif",
- .reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
- .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
- };
-
- static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
-+ .tx_clk_name = "spdif",
- .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
- .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
- };
-
- static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
-+ .tx_clk_name = "spdif",
- .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
- .val_fctl_ftx = SUN50I_H6_SPDIF_FCTL_FTX,
- };
-@@ -591,7 +597,7 @@ static int sun4i_spdif_runtime_suspend(s
- {
- struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
-
-- clk_disable_unprepare(host->spdif_clk);
-+ clk_disable_unprepare(host->tx_clk);
- clk_disable_unprepare(host->apb_clk);
-
- return 0;
-@@ -602,12 +608,12 @@ static int sun4i_spdif_runtime_resume(st
- struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
- int ret;
-
-- ret = clk_prepare_enable(host->spdif_clk);
-+ ret = clk_prepare_enable(host->tx_clk);
- if (ret)
- return ret;
- ret = clk_prepare_enable(host->apb_clk);
- if (ret)
-- clk_disable_unprepare(host->spdif_clk);
-+ clk_disable_unprepare(host->tx_clk);
-
- return ret;
- }
-@@ -655,10 +661,10 @@ static int sun4i_spdif_probe(struct plat
- return PTR_ERR(host->apb_clk);
- }
-
-- host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
-- if (IS_ERR(host->spdif_clk)) {
-- dev_err(&pdev->dev, "failed to get a spdif clock.\n");
-- return PTR_ERR(host->spdif_clk);
-+ host->tx_clk = devm_clk_get(&pdev->dev, quirks->tx_clk_name);
-+ if (IS_ERR(host->tx_clk)) {
-+ dev_err(&pdev->dev, "failed to get TX module clock.\n");
-+ return PTR_ERR(host->tx_clk);
- }
-
- host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata;
+++ /dev/null
-From af01261bf4e334cad158519291e5bc38765c955f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:53:26 -0500
-Subject: [PATCH 071/117] ASoC: sun4i-spdif: Add support for the D1 variant
-
-The D1 variant is similar to the H6 variant, except for its clock setup.
-The clock tree changes impact some register fields on the RX side, but
-those are not yet relevant, because RX is not supported by this driver.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-spdif.c | 10 ++++++++++
- 1 file changed, 10 insertions(+)
-
---- a/sound/soc/sunxi/sun4i-spdif.c
-+++ b/sound/soc/sunxi/sun4i-spdif.c
-@@ -556,6 +556,12 @@ static const struct sun4i_spdif_quirks s
- .val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
- };
-
-+static const struct sun4i_spdif_quirks sun20i_d1_spdif_quirks = {
-+ .tx_clk_name = "tx",
-+ .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
-+ .val_fctl_ftx = SUN50I_H6_SPDIF_FCTL_FTX,
-+};
-+
- static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
- .tx_clk_name = "spdif",
- .reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
-@@ -576,6 +582,10 @@ static const struct of_device_id sun4i_s
- .data = &sun8i_h3_spdif_quirks,
- },
- {
-+ .compatible = "allwinner,sun20i-d1-spdif",
-+ .data = &sun20i_d1_spdif_quirks,
-+ },
-+ {
- .compatible = "allwinner,sun50i-h6-spdif",
- .data = &sun50i_h6_spdif_quirks,
- },
+++ /dev/null
-From 36153e325aa912268a5a5d4574dc7092e67c8008 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 17 Aug 2022 01:54:46 -0500
-Subject: [PATCH 072/117] riscv: dts: allwinner: d1: Add SPDIF support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 16 ++++++++++++++++
- 1 file changed, 16 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -333,6 +333,22 @@
- #sound-dai-cells = <0>;
- };
-
-+ // TODO: add receive functionality
-+ spdif: spdif@2036000 {
-+ compatible = "allwinner,sun20i-d1-spdif";
-+ reg = <0x2036000 0x400>;
-+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_SPDIF>,
-+ <&ccu CLK_SPDIF_RX>,
-+ <&ccu CLK_SPDIF_TX>;
-+ clock-names = "apb", "rx", "tx";
-+ resets = <&ccu RST_BUS_SPDIF>;
-+ dmas = <&dma 2>, <&dma 2>;
-+ dma-names = "rx", "tx";
-+ status = "disabled";
-+ #sound-dai-cells = <0>;
-+ };
-+
- timer: timer@2050000 {
- compatible = "allwinner,sun20i-d1-timer",
- "allwinner,sun8i-a23-timer";
+++ /dev/null
-From c2b3f2c723e1b558afe5661bb91669e3b68154f7 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 13 Jun 2021 23:52:47 -0500
-Subject: [PATCH 073/117] ASoC: sun4i-spdif: Add support for separate resets
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun4i-spdif.c | 5 +++--
- 1 file changed, 3 insertions(+), 2 deletions(-)
-
---- a/sound/soc/sunxi/sun4i-spdif.c
-+++ b/sound/soc/sunxi/sun4i-spdif.c
-@@ -28,10 +28,11 @@
- #include <sound/soc.h>
-
- #define SUN4I_SPDIF_CTL (0x00)
-+ #define SUN4I_SPDIF_CTL_RST_RX BIT(12)
- #define SUN4I_SPDIF_CTL_MCLKDIV(v) ((v) << 4) /* v even */
- #define SUN4I_SPDIF_CTL_MCLKOUTEN BIT(2)
- #define SUN4I_SPDIF_CTL_GEN BIT(1)
-- #define SUN4I_SPDIF_CTL_RESET BIT(0)
-+ #define SUN4I_SPDIF_CTL_RST_TX BIT(0)
-
- #define SUN4I_SPDIF_TXCFG (0x04)
- #define SUN4I_SPDIF_TXCFG_SINGLEMOD BIT(31)
-@@ -196,7 +197,7 @@ static void sun4i_spdif_configure(struct
- const struct sun4i_spdif_quirks *quirks = host->quirks;
-
- /* soft reset SPDIF */
-- regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RESET);
-+ regmap_write(host->regmap, SUN4I_SPDIF_CTL, SUN4I_SPDIF_CTL_RST_TX);
-
- /* flush TX FIFO */
- regmap_update_bits(host->regmap, SUN4I_SPDIF_FCTL,
+++ /dev/null
-From e8e8a9490b2d4acc8670256dd3ba7d2a77346c4d Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:23:05 -0500
-Subject: [PATCH 074/117] dt-bindings: spi: sun6i: Add R329 variant
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
-+++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
-@@ -21,6 +21,7 @@ properties:
- oneOf:
- - const: allwinner,sun6i-a31-spi
- - const: allwinner,sun8i-h3-spi
-+ - const: allwinner,sun50i-r329-spi
- - items:
- - enum:
- - allwinner,sun8i-r40-spi
-@@ -28,6 +29,13 @@ properties:
- - allwinner,sun50i-h616-spi
- - allwinner,suniv-f1c100s-spi
- - const: allwinner,sun8i-h3-spi
-+ - items:
-+ - const: allwinner,sun20i-d1-spi
-+ - const: allwinner,sun50i-r329-spi
-+ - items:
-+ - const: allwinner,sun20i-d1-spi-dbi
-+ - const: allwinner,sun50i-r329-spi-dbi
-+ - const: allwinner,sun50i-r329-spi
-
- reg:
- maxItems: 1
+++ /dev/null
-From dbc9e83cefe51d19877a4a7349ebbeafa31c0e06 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 16 Jul 2021 21:33:16 -0500
-Subject: [PATCH 075/117] spi: spi-sun6i: Use a struct for quirks
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/spi/spi-sun6i.c | 32 ++++++++++++++++++++++----------
- 1 file changed, 22 insertions(+), 10 deletions(-)
-
---- a/drivers/spi/spi-sun6i.c
-+++ b/drivers/spi/spi-sun6i.c
-@@ -85,7 +85,12 @@
- #define SUN6I_TXDATA_REG 0x200
- #define SUN6I_RXDATA_REG 0x300
-
-+struct sun6i_spi_quirks {
-+ unsigned long fifo_depth;
-+};
-+
- struct sun6i_spi {
-+ const struct sun6i_spi_quirks *quirks;
- struct spi_master *master;
- void __iomem *base_addr;
- dma_addr_t dma_addr_rx;
-@@ -100,7 +105,6 @@ struct sun6i_spi {
- const u8 *tx_buf;
- u8 *rx_buf;
- int len;
-- unsigned long fifo_depth;
- };
-
- static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
-@@ -157,7 +161,7 @@ static inline void sun6i_spi_fill_fifo(s
- u8 byte;
-
- /* See how much data we can fit */
-- cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
-+ cnt = sspi->quirks->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi);
-
- len = min((int)cnt, sspi->len);
-
-@@ -300,14 +304,14 @@ static int sun6i_spi_transfer_one(struct
- * the hardcoded value used in old generation of Allwinner
- * SPI controller. (See spi-sun4i.c)
- */
-- trig_level = sspi->fifo_depth / 4 * 3;
-+ trig_level = sspi->quirks->fifo_depth / 4 * 3;
- } else {
- /*
- * Setup FIFO DMA request trigger level
- * We choose 1/2 of the full fifo depth, that value will
- * be used as DMA burst length.
- */
-- trig_level = sspi->fifo_depth / 2;
-+ trig_level = sspi->quirks->fifo_depth / 2;
-
- if (tfr->tx_buf)
- reg |= SUN6I_FIFO_CTL_TF_DRQ_EN;
-@@ -421,9 +425,9 @@ static int sun6i_spi_transfer_one(struct
- reg = SUN6I_INT_CTL_TC;
-
- if (!use_dma) {
-- if (rx_len > sspi->fifo_depth)
-+ if (rx_len > sspi->quirks->fifo_depth)
- reg |= SUN6I_INT_CTL_RF_RDY;
-- if (tx_len > sspi->fifo_depth)
-+ if (tx_len > sspi->quirks->fifo_depth)
- reg |= SUN6I_INT_CTL_TF_ERQ;
- }
-
-@@ -569,7 +573,7 @@ static bool sun6i_spi_can_dma(struct spi
- * the fifo length we can just fill the fifo and wait for a single
- * irq, so don't bother setting up dma
- */
-- return xfer->len > sspi->fifo_depth;
-+ return xfer->len > sspi->quirks->fifo_depth;
- }
-
- static int sun6i_spi_probe(struct platform_device *pdev)
-@@ -608,7 +612,7 @@ static int sun6i_spi_probe(struct platfo
- }
-
- sspi->master = master;
-- sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
-+ sspi->quirks = of_device_get_match_data(&pdev->dev);
-
- master->max_speed_hz = 100 * 1000 * 1000;
- master->min_speed_hz = 3 * 1000;
-@@ -723,9 +727,17 @@ static int sun6i_spi_remove(struct platf
- return 0;
- }
-
-+static const struct sun6i_spi_quirks sun6i_a31_spi_quirks = {
-+ .fifo_depth = SUN6I_FIFO_DEPTH,
-+};
-+
-+static const struct sun6i_spi_quirks sun8i_h3_spi_quirks = {
-+ .fifo_depth = SUN8I_FIFO_DEPTH,
-+};
-+
- static const struct of_device_id sun6i_spi_match[] = {
-- { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
-- { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
-+ { .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_quirks },
-+ { .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_quirks },
- {}
- };
- MODULE_DEVICE_TABLE(of, sun6i_spi_match);
+++ /dev/null
-From ec8dfb455da3822451129257ab21e2f0d03a6ae3 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 16 Jul 2021 21:46:31 -0500
-Subject: [PATCH 076/117] spi: spi-sun6i: Add Allwinner R329 support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/spi/spi-sun6i.c | 78 ++++++++++++++++++++++++++---------------
- 1 file changed, 49 insertions(+), 29 deletions(-)
-
---- a/drivers/spi/spi-sun6i.c
-+++ b/drivers/spi/spi-sun6i.c
-@@ -30,6 +30,7 @@
- #define SUN6I_GBL_CTL_REG 0x04
- #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
- #define SUN6I_GBL_CTL_MASTER BIT(1)
-+#define SUN6I_GBL_CTL_SAMPLE_MODE BIT(2)
- #define SUN6I_GBL_CTL_TP BIT(7)
- #define SUN6I_GBL_CTL_RST BIT(31)
-
-@@ -87,6 +88,8 @@
-
- struct sun6i_spi_quirks {
- unsigned long fifo_depth;
-+ bool has_divider : 1;
-+ bool has_new_sample_mode : 1;
- };
-
- struct sun6i_spi {
-@@ -362,38 +365,44 @@ static int sun6i_spi_transfer_one(struct
- sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
-
- /* Ensure that we have a parent clock fast enough */
-- mclk_rate = clk_get_rate(sspi->mclk);
-- if (mclk_rate < (2 * tfr->speed_hz)) {
-- clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
-+ if (sspi->quirks->has_divider) {
- mclk_rate = clk_get_rate(sspi->mclk);
-- }
-+ if (mclk_rate < (2 * tfr->speed_hz)) {
-+ clk_set_rate(sspi->mclk, 2 * tfr->speed_hz);
-+ mclk_rate = clk_get_rate(sspi->mclk);
-+ }
-
-- /*
-- * Setup clock divider.
-- *
-- * We have two choices there. Either we can use the clock
-- * divide rate 1, which is calculated thanks to this formula:
-- * SPI_CLK = MOD_CLK / (2 ^ cdr)
-- * Or we can use CDR2, which is calculated with the formula:
-- * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
-- * Wether we use the former or the latter is set through the
-- * DRS bit.
-- *
-- * First try CDR2, and if we can't reach the expected
-- * frequency, fall back to CDR1.
-- */
-- div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
-- div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
-- if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
-- reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
-- tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
-+ /*
-+ * Setup clock divider.
-+ *
-+ * We have two choices there. Either we can use the clock
-+ * divide rate 1, which is calculated thanks to this formula:
-+ * SPI_CLK = MOD_CLK / (2 ^ cdr)
-+ * Or we can use CDR2, which is calculated with the formula:
-+ * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
-+ * Wether we use the former or the latter is set through the
-+ * DRS bit.
-+ *
-+ * First try CDR2, and if we can't reach the expected
-+ * frequency, fall back to CDR1.
-+ */
-+ div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz);
-+ div_cdr2 = DIV_ROUND_UP(div_cdr1, 2);
-+ if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
-+ reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS;
-+ tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2);
-+ } else {
-+ div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
-+ reg = SUN6I_CLK_CTL_CDR1(div);
-+ tfr->effective_speed_hz = mclk_rate / (1 << div);
-+ }
-+ sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
- } else {
-- div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1));
-- reg = SUN6I_CLK_CTL_CDR1(div);
-- tfr->effective_speed_hz = mclk_rate / (1 << div);
-+ clk_set_rate(sspi->mclk, tfr->speed_hz);
-+ mclk_rate = clk_get_rate(sspi->mclk);
-+ tfr->effective_speed_hz = mclk_rate;
- }
-
-- sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
- /* Finally enable the bus - doing so before might raise SCK to HIGH */
- reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG);
- reg |= SUN6I_GBL_CTL_BUS_ENABLE;
-@@ -518,6 +527,7 @@ static int sun6i_spi_runtime_resume(stru
- struct spi_master *master = dev_get_drvdata(dev);
- struct sun6i_spi *sspi = spi_master_get_devdata(master);
- int ret;
-+ u32 reg;
-
- ret = clk_prepare_enable(sspi->hclk);
- if (ret) {
-@@ -537,8 +547,10 @@ static int sun6i_spi_runtime_resume(stru
- goto err2;
- }
-
-- sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
-- SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
-+ reg = SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP;
-+ if (sspi->quirks->has_new_sample_mode)
-+ reg |= SUN6I_GBL_CTL_SAMPLE_MODE;
-+ sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg);
-
- return 0;
-
-@@ -729,15 +741,23 @@ static int sun6i_spi_remove(struct platf
-
- static const struct sun6i_spi_quirks sun6i_a31_spi_quirks = {
- .fifo_depth = SUN6I_FIFO_DEPTH,
-+ .has_divider = true,
- };
-
- static const struct sun6i_spi_quirks sun8i_h3_spi_quirks = {
- .fifo_depth = SUN8I_FIFO_DEPTH,
-+ .has_divider = true,
-+};
-+
-+static const struct sun6i_spi_quirks sun50i_r329_spi_quirks = {
-+ .fifo_depth = SUN8I_FIFO_DEPTH,
-+ .has_new_sample_mode = true,
- };
-
- static const struct of_device_id sun6i_spi_match[] = {
- { .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_quirks },
- { .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_quirks },
-+ { .compatible = "allwinner,sun50i-r329-spi", .data = &sun50i_r329_spi_quirks },
- {}
- };
- MODULE_DEVICE_TABLE(of, sun6i_spi_match);
+++ /dev/null
-From b300b013de16109f833782d9f4e7ee8cc204780f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 17 Jul 2021 11:19:29 -0500
-Subject: [PATCH 077/117] spi: spi-sun6i: Dual/Quad RX Support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/spi/spi-sun6i.c | 17 +++++++++++++++--
- 1 file changed, 15 insertions(+), 2 deletions(-)
-
---- a/drivers/spi/spi-sun6i.c
-+++ b/drivers/spi/spi-sun6i.c
-@@ -82,6 +82,8 @@
- #define SUN6I_XMIT_CNT_REG 0x34
-
- #define SUN6I_BURST_CTL_CNT_REG 0x38
-+#define SUN6I_BURST_CTL_CNT_QUAD_EN BIT(29)
-+#define SUN6I_BURST_CTL_CNT_DUAL_EN BIT(28)
-
- #define SUN6I_TXDATA_REG 0x200
- #define SUN6I_RXDATA_REG 0x300
-@@ -415,7 +417,17 @@ static int sun6i_spi_transfer_one(struct
- /* Setup the counters */
- sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len);
- sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len);
-- sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len);
-+
-+ reg = tx_len;
-+ switch (tfr->rx_nbits) {
-+ case SPI_NBITS_QUAD:
-+ reg |= SUN6I_BURST_CTL_CNT_QUAD_EN;
-+ break;
-+ case SPI_NBITS_DUAL:
-+ reg |= SUN6I_BURST_CTL_CNT_DUAL_EN;
-+ break;
-+ }
-+ sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, reg);
-
- if (!use_dma) {
- /* Fill the TX FIFO */
-@@ -632,7 +644,8 @@ static int sun6i_spi_probe(struct platfo
- master->set_cs = sun6i_spi_set_cs;
- master->transfer_one = sun6i_spi_transfer_one;
- master->num_chipselect = 4;
-- master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
-+ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST
-+ | SPI_RX_DUAL | SPI_RX_QUAD;
- master->bits_per_word_mask = SPI_BPW_MASK(8);
- master->dev.of_node = pdev->dev.of_node;
- master->auto_runtime_pm = true;
+++ /dev/null
-From aaabd3cf8c041b5122ca252f51fa616833e18749 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 00:54:01 -0500
-Subject: [PATCH 078/117] riscv: dts: allwinner: Add SPI support
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../dts/allwinner/sun20i-d1-lichee-rv.dts | 6 +++
- .../boot/dts/allwinner/sun20i-d1-nezha.dts | 44 ++++++++++++++++
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 51 +++++++++++++++++++
- 3 files changed, 101 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv.dts
-@@ -65,6 +65,12 @@
- status = "okay";
- };
-
-+&spi0 {
-+ pinctrl-0 = <&spi0_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
- &uart0 {
- pinctrl-0 = <&uart0_pb8_pins>;
- pinctrl-names = "default";
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-@@ -19,6 +19,7 @@
- ethernet1 = &xr829;
- mmc0 = &mmc0;
- serial0 = &uart0;
-+ spi0 = &spi0;
- };
-
- chosen {
-@@ -157,6 +158,49 @@
- pinctrl-names = "default";
- status = "okay";
- };
-+
-+&spi0 {
-+ pinctrl-0 = <&spi0_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ flash@0 {
-+ compatible = "spi-nand";
-+ reg = <0>;
-+
-+ partitions {
-+ compatible = "fixed-partitions";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "boot0";
-+ reg = <0x00000000 0x00100000>;
-+ };
-+
-+ partition@100000 {
-+ label = "uboot";
-+ reg = <0x00100000 0x00300000>;
-+ };
-+
-+ partition@400000 {
-+ label = "secure_storage";
-+ reg = <0x00400000 0x00100000>;
-+ };
-+
-+ partition@500000 {
-+ label = "sys";
-+ reg = <0x00500000 0x0fb00000>;
-+ };
-+ };
-+ };
-+};
-+
-+&spi1 {
-+ pinctrl-0 = <&spi1_pd_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-
- &uart0 {
- pinctrl-0 = <&uart0_pb8_pins>;
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -179,6 +179,24 @@
- };
-
- /omit-if-no-ref/
-+ spi0_pins: spi0-pins {
-+ pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7";
-+ function = "spi0";
-+ };
-+
-+ /omit-if-no-ref/
-+ spi1_pb_pins: spi1-pb-pins {
-+ pins = "PB0", "PB8", "PB9", "PB10", "PB11", "PB12";
-+ function = "spi1";
-+ };
-+
-+ /omit-if-no-ref/
-+ spi1_pd_pins: spi1-pd-pins {
-+ pins = "PD10", "PD11", "PD12", "PD13", "PD14", "PD15";
-+ function = "spi1";
-+ };
-+
-+ /omit-if-no-ref/
- uart0_pb8_pins: uart0-pb8-pins {
- pins = "PB8", "PB9";
- function = "uart0";
-@@ -631,6 +649,39 @@
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
-+ };
-+
-+ spi0: spi@4025000 {
-+ compatible = "allwinner,sun20i-d1-spi",
-+ "allwinner,sun50i-r329-spi";
-+ reg = <0x4025000 0x1000>;
-+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
-+ clock-names = "ahb", "mod";
-+ resets = <&ccu RST_BUS_SPI0>;
-+ dmas = <&dma 22>, <&dma 22>;
-+ dma-names = "rx", "tx";
-+ num-cs = <1>;
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ };
-+
-+ spi1: spi@4026000 {
-+ compatible = "allwinner,sun20i-d1-spi-dbi",
-+ "allwinner,sun50i-r329-spi-dbi",
-+ "allwinner,sun50i-r329-spi";
-+ reg = <0x4026000 0x1000>;
-+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
-+ clock-names = "ahb", "mod";
-+ resets = <&ccu RST_BUS_SPI1>;
-+ dmas = <&dma 23>, <&dma 23>;
-+ dma-names = "rx", "tx";
-+ num-cs = <1>;
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
- };
-
- usb_otg: usb@4100000 {
+++ /dev/null
-From 68c6f452bf42d6c5cbaf40537d8a17a7f3f5481e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 6 Jun 2021 10:03:12 -0500
-Subject: [PATCH 079/117] dt-bindings: thermal: sun8i: Add compatible for D1
-
-D1 contains a thermal sensor similar to other Allwinner SoCs. Like the
-H3 variant, it contains only one channel.
-
-D1's thermal sensor gets a reference voltage from AVCC. This may always
-have been the case; it is explicitly documented in the SoC user manuals
-since at least H616. However, it was not as important on earlier SoCs,
-because those reference designs foreced AVCC always-on by connecting it
-to the PLL power supply.
-
-Now, since D1 only uses AVCC for other optional peripherals, this supply
-could be turned off at runtime, so it must be made explicit in the DTS.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../thermal/allwinner,sun8i-a83t-ths.yaml | 21 ++++++++++++++++++-
- 1 file changed, 20 insertions(+), 1 deletion(-)
-
---- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
-+++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
-@@ -16,6 +16,7 @@ properties:
- - allwinner,sun8i-a83t-ths
- - allwinner,sun8i-h3-ths
- - allwinner,sun8i-r40-ths
-+ - allwinner,sun20i-d1-ths
- - allwinner,sun50i-a64-ths
- - allwinner,sun50i-a100-ths
- - allwinner,sun50i-h5-ths
-@@ -55,6 +56,10 @@ properties:
- - 0
- - 1
-
-+ vref-supply:
-+ description:
-+ Regulator for the analog reference voltage
-+
- allOf:
- - if:
- properties:
-@@ -84,7 +89,9 @@ allOf:
- properties:
- compatible:
- contains:
-- const: allwinner,sun8i-h3-ths
-+ enum:
-+ - allwinner,sun8i-h3-ths
-+ - allwinner,sun20i-d1-ths
-
- then:
- properties:
-@@ -103,6 +110,7 @@ allOf:
- enum:
- - allwinner,sun8i-h3-ths
- - allwinner,sun8i-r40-ths
-+ - allwinner,sun20i-d1-ths
- - allwinner,sun50i-a64-ths
- - allwinner,sun50i-a100-ths
- - allwinner,sun50i-h5-ths
-@@ -114,6 +122,17 @@ allOf:
- - clock-names
- - resets
-
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ enum:
-+ - allwinner,sun20i-d1-ths
-+
-+ then:
-+ required:
-+ - vref-supply
-+
- required:
- - compatible
- - reg
+++ /dev/null
-From c225b48d2cf5f5a824b5b0a4144511bdc5f65ab5 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 14 Aug 2022 11:18:11 -0500
-Subject: [PATCH 080/117] riscv: dts: allwinner: d1: Add thermal sensor and
- zone
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../sun20i-d1-common-regulators.dtsi | 4 ++
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 41 +++++++++++++++++++
- 2 files changed, 45 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
-@@ -49,3 +49,7 @@
- regulator-max-microvolt = <1800000>;
- ldo-in-supply = <®_vcc_3v3>;
- };
-+
-+&ths {
-+ vref-supply = <®_aldo>;
-+};
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -59,6 +59,35 @@
- #clock-cells = <0>;
- };
-
-+ thermal-zones {
-+ cpu-thermal {
-+ polling-delay = <0>;
-+ polling-delay-passive = <0>;
-+ thermal-sensors = <&ths>;
-+
-+ trips {
-+ cpu_target: cpu-target {
-+ hysteresis = <3000>;
-+ temperature = <85000>;
-+ type = "passive";
-+ };
-+
-+ cpu-crit {
-+ hysteresis = <0>;
-+ temperature = <110000>;
-+ type = "critical";
-+ };
-+ };
-+
-+ cooling-maps {
-+ map0 {
-+ trip = <&cpu_target>;
-+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
-+ };
-+ };
-+ };
-+ };
-+
- soc {
- compatible = "simple-bus";
- ranges;
-@@ -252,6 +281,18 @@
- #size-cells = <0>;
- };
-
-+ ths: temperature-sensor@2009400 {
-+ compatible = "allwinner,sun20i-d1-ths";
-+ reg = <0x2009400 0x400>;
-+ interrupts = <74 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_THS>, <&osc24M>;
-+ clock-names = "bus", "mod";
-+ resets = <&ccu RST_BUS_THS>;
-+ nvmem-cells = <&ths_calib>;
-+ nvmem-cell-names = "calibration";
-+ #thermal-sensor-cells = <0>;
-+ };
-+
- lradc: keys@2009800 {
- compatible = "allwinner,sun20i-d1-lradc",
- "allwinner,sun50i-r329-lradc";
+++ /dev/null
-From 9b6a07cacab9300c261b1f7e25857f96cfeae9cf Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sat, 12 Jun 2021 23:42:48 -0500
-Subject: [PATCH 081/117] ASoC: sun20i-codec: New driver for D1 internal codec
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/Kconfig | 6 +
- sound/soc/sunxi/Makefile | 1 +
- sound/soc/sunxi/sun20i-codec.c | 886 +++++++++++++++++++++++++++++++++
- 3 files changed, 893 insertions(+)
- create mode 100644 sound/soc/sunxi/sun20i-codec.c
-
---- a/sound/soc/sunxi/Kconfig
-+++ b/sound/soc/sunxi/Kconfig
-@@ -30,6 +30,12 @@ config SND_SUN8I_CODEC_ANALOG
- Say Y or M if you want to add support for the analog controls for
- the codec embedded in newer Allwinner SoCs.
-
-+config SND_SUN20I_CODEC
-+ tristate "Allwinner D1 (sun20i) Audio Codec"
-+ depends on ARCH_SUNXI || COMPILE_TEST
-+ help
-+ Say Y or M to add support for the audio codec in Allwinner D1 SoC.
-+
- config SND_SUN50I_CODEC_ANALOG
- tristate "Allwinner sun50i Codec Analog Controls Support"
- depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
---- a/sound/soc/sunxi/Makefile
-+++ b/sound/soc/sunxi/Makefile
-@@ -3,6 +3,7 @@ obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-c
- obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
- obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
- obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
-+obj-$(CONFIG_SND_SUN20I_CODEC) += sun20i-codec.o
- obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
- obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
- obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o
---- /dev/null
-+++ b/sound/soc/sunxi/sun20i-codec.c
-@@ -0,0 +1,886 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+
-+#include <linux/clk.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/platform_device.h>
-+#include <linux/regmap.h>
-+#include <linux/reset.h>
-+
-+#include <sound/dmaengine_pcm.h>
-+#include <sound/pcm_params.h>
-+#include <sound/simple_card_utils.h>
-+#include <sound/soc.h>
-+#include <sound/soc-dai.h>
-+#include <sound/soc-dapm.h>
-+#include <sound/tlv.h>
-+
-+#define SUN20I_CODEC_DAC_DPC 0x0000
-+#define SUN20I_CODEC_DAC_DPC_EN_DA 31
-+#define SUN20I_CODEC_DAC_DPC_HPF_EN 18
-+#define SUN20I_CODEC_DAC_DPC_DVOL 12
-+#define SUN20I_CODEC_DAC_VOL_CTRL 0x0004
-+#define SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_SEL 16
-+#define SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_L 8
-+#define SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_R 0
-+#define SUN20I_CODEC_DAC_FIFOC 0x0010
-+#define SUN20I_CODEC_DAC_FIFOC_FS 29
-+#define SUN20I_CODEC_DAC_FIFOC_FIFO_MODE 24
-+#define SUN20I_CODEC_DAC_FIFOC_DRQ_CLR_CNT 21
-+#define SUN20I_CODEC_DAC_FIFOC_TRIG_LEVEL 8
-+#define SUN20I_CODEC_DAC_FIFOC_MONO_EN 6
-+#define SUN20I_CODEC_DAC_FIFOC_SAMPLE_BITS 5
-+#define SUN20I_CODEC_DAC_FIFOC_DRQ_EN 4
-+#define SUN20I_CODEC_DAC_FIFOC_FIFO_FLUSH 0
-+#define SUN20I_CODEC_DAC_TXDATA 0x0020
-+#define SUN20I_CODEC_DAC_DEBUG 0x0028
-+#define SUN20I_CODEC_DAC_DEBUG_DA_SWP 6
-+#define SUN20I_CODEC_DAC_ADDA_LOOP_MODE 0
-+
-+#define SUN20I_CODEC_ADC_FIFOC 0x0030
-+#define SUN20I_CODEC_ADC_FIFOC_FS 29
-+#define SUN20I_CODEC_ADC_FIFOC_EN_AD 28
-+#define SUN20I_CODEC_ADC_FIFOC_FIFO_MODE 24
-+#define SUN20I_CODEC_ADC_FIFOC_SAMPLE_BITS 16
-+#define SUN20I_CODEC_ADC_FIFOC_TRIG_LEVEL 4
-+#define SUN20I_CODEC_ADC_FIFOC_DRQ_EN 3
-+#define SUN20I_CODEC_ADC_FIFOC_FIFO_FLUSH 0
-+#define SUN20I_CODEC_ADC_VOL_CTRL 0x0034
-+#define SUN20I_CODEC_ADC_VOL_CTRL_ADC3_VOL 16
-+#define SUN20I_CODEC_ADC_VOL_CTRL_ADC2_VOL 8
-+#define SUN20I_CODEC_ADC_VOL_CTRL_ADC1_VOL 0
-+#define SUN20I_CODEC_ADC_RXDATA 0x0040
-+#define SUN20I_CODEC_ADC_DEBUG 0x004c
-+#define SUN20I_CODEC_ADC_DEBUG_AD_SWP1 24
-+#define SUN20I_CODEC_ADC_DIG_CTRL 0x0050
-+#define SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN 16
-+#define SUN20I_CODEC_ADC_DIG_CTRL_ADC_EN 0
-+
-+#define SUN20I_CODEC_DAC_DAP_CTRL 0x00f0
-+#define SUN20I_CODEC_DAC_DAP_CTRL_DAP_EN 31
-+#define SUN20I_CODEC_DAC_DAP_CTRL_DAP_DRC_EN 29
-+#define SUN20I_CODEC_DAC_DAP_CTRL_DAP_HPF_EN 28
-+
-+#define SUN20I_CODEC_ADC_DAP_CTRL 0x00f8
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP0_EN 31
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP0_DRC_EN 29
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP0_HPF_EN 28
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP1_EN 27
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP1_DRC_EN 25
-+#define SUN20I_CODEC_ADC_DAP_CTRL_DAP1_HPF_EN 24
-+
-+#define SUN20I_CODEC_ADC1 0x0300
-+#define SUN20I_CODEC_ADC1_ADC1_EN 31
-+#define SUN20I_CODEC_ADC1_MICIN1_PGA_EN 30
-+#define SUN20I_CODEC_ADC1_ADC1_DITHER_EN 29
-+#define SUN20I_CODEC_ADC1_MICIN1_SIN_EN 28
-+#define SUN20I_CODEC_ADC1_FMINL_EN 27
-+#define SUN20I_CODEC_ADC1_FMINL_GAIN 26
-+#define SUN20I_CODEC_ADC1_DITHER_LEVEL 24
-+#define SUN20I_CODEC_ADC1_LINEINL_EN 23
-+#define SUN20I_CODEC_ADC1_LINEINL_GAIN 22
-+#define SUN20I_CODEC_ADC1_ADC1_PGA_GAIN 8
-+#define SUN20I_CODEC_ADC2 0x0304
-+#define SUN20I_CODEC_ADC2_ADC2_EN 31
-+#define SUN20I_CODEC_ADC2_MICIN2_PGA_EN 30
-+#define SUN20I_CODEC_ADC2_ADC2_DITHER_EN 29
-+#define SUN20I_CODEC_ADC2_MICIN2_SIN_EN 28
-+#define SUN20I_CODEC_ADC2_FMINR_EN 27
-+#define SUN20I_CODEC_ADC2_FMINR_GAIN 26
-+#define SUN20I_CODEC_ADC2_DITHER_LEVEL 24
-+#define SUN20I_CODEC_ADC2_LINEINR_EN 23
-+#define SUN20I_CODEC_ADC2_LINEINR_GAIN 22
-+#define SUN20I_CODEC_ADC2_ADC2_PGA_GAIN 8
-+#define SUN20I_CODEC_ADC3 0x0308
-+#define SUN20I_CODEC_ADC3_ADC3_EN 31
-+#define SUN20I_CODEC_ADC3_MICIN3_PGA_EN 30
-+#define SUN20I_CODEC_ADC3_ADC3_DITHER_EN 29
-+#define SUN20I_CODEC_ADC3_MICIN3_SIN_EN 28
-+#define SUN20I_CODEC_ADC3_DITHER_LEVEL 24
-+#define SUN20I_CODEC_ADC3_ADC3_PGA_GAIN 8
-+
-+#define SUN20I_CODEC_DAC 0x0310
-+#define SUN20I_CODEC_DAC_DACL_EN 15
-+#define SUN20I_CODEC_DAC_DACR_EN 14
-+#define SUN20I_CODEC_DAC_LINEOUTL_EN 13
-+#define SUN20I_CODEC_DAC_LMUTE 12
-+#define SUN20I_CODEC_DAC_LINEOUTR_EN 11
-+#define SUN20I_CODEC_DAC_RMUTE 10
-+#define SUN20I_CODEC_DAC_LINEOUTL_DIFFEN 6
-+#define SUN20I_CODEC_DAC_LINEOUTR_DIFFEN 5
-+#define SUN20I_CODEC_DAC_LINEOUT_VOL_CTRL 0
-+
-+#define SUN20I_CODEC_MICBIAS 0x0318
-+#define SUN20I_CODEC_MICBIAS_SELDETADCFS 28
-+#define SUN20I_CODEC_MICBIAS_SELDETADCDB 26
-+#define SUN20I_CODEC_MICBIAS_SELDETADCBF 24
-+#define SUN20I_CODEC_MICBIAS_JACKDETEN 23
-+#define SUN20I_CODEC_MICBIAS_SELDETADCDY 21
-+#define SUN20I_CODEC_MICBIAS_MICADCEN 20
-+#define SUN20I_CODEC_MICBIAS_POPFREE 19
-+#define SUN20I_CODEC_MICBIAS_DET_MODE 18
-+#define SUN20I_CODEC_MICBIAS_AUTOPLEN 17
-+#define SUN20I_CODEC_MICBIAS_MICDETPL 16
-+#define SUN20I_CODEC_MICBIAS_HMICBIASEN 15
-+#define SUN20I_CODEC_MICBIAS_HMICBIASSEL 13
-+#define SUN20I_CODEC_MICBIAS_HMIC_CHOPPER_EN 12
-+#define SUN20I_CODEC_MICBIAS_HMIC_CHOPPER_CLK 10
-+#define SUN20I_CODEC_MICBIAS_MMICBIASEN 7
-+#define SUN20I_CODEC_MICBIAS_MMICBIASSEL 5
-+#define SUN20I_CODEC_MICBIAS_MMIC_CHOPPER_EN 4
-+#define SUN20I_CODEC_MICBIAS_MMIC_CHOPPER_CLK 2
-+
-+/* TODO */
-+#define SUN20I_CODEC_RAMP 0x031c
-+#define SUN20I_CODEC_RAMP_HP_PULL_OUT_EN 15
-+
-+#define SUN20I_CODEC_HMIC_CTRL 0x0328
-+#define SUN20I_CODEC_HMIC_CTRL_SAMPLE_SELECT 21
-+#define SUN20I_CODEC_HMIC_CTRL_MDATA_THRESHOLD 16
-+#define SUN20I_CODEC_HMIC_CTRL_SF 14
-+#define SUN20I_CODEC_HMIC_CTRL_M 10
-+#define SUN20I_CODEC_HMIC_CTRL_N 6
-+#define SUN20I_CODEC_HMIC_CTRL_THRESH_DEBOUNCE 3
-+#define SUN20I_CODEC_HMIC_CTRL_JACK_OUT_IRQ_EN 2
-+#define SUN20I_CODEC_HMIC_CTRL_JACK_IN_IRQ_EN 1
-+#define SUN20I_CODEC_HMIC_CTRL_MIC_DET_IRQ_EN 0
-+#define SUN20I_CODEC_HMIC_STS 0x032c
-+#define SUN20I_CODEC_HMIC_STS_MDATA_DISCARD 13
-+#define SUN20I_CODEC_HMIC_STS_HMIC_DATA 8
-+#define SUN20I_CODEC_HMIC_STS_JACK_OUT_IRQ 4
-+#define SUN20I_CODEC_HMIC_STS_JACK_IN_IRQ 3
-+#define SUN20I_CODEC_HMIC_STS_MIC_DET_IRQ 0
-+
-+#define SUN20I_CODEC_HP2 0x0340
-+#define SUN20I_CODEC_HP2_HPFB_BUF_EN 31
-+#define SUN20I_CODEC_HP2_HEADPHONE_GAIN 28
-+#define SUN20I_CODEC_HP2_HPFB_RES 26
-+#define SUN20I_CODEC_HP2_HP_DRVEN 21
-+#define SUN20I_CODEC_HP2_HP_DRVOUTEN 20
-+#define SUN20I_CODEC_HP2_RSWITCH 19
-+#define SUN20I_CODEC_HP2_RAMPEN 18
-+#define SUN20I_CODEC_HP2_HPFB_IN_EN 17
-+#define SUN20I_CODEC_HP2_RAMP_FINAL_CONTROL 16
-+#define SUN20I_CODEC_HP2_RAMP_OUT_EN 15
-+#define SUN20I_CODEC_HP2_RAMP_FINAL_STATE_RES 13
-+
-+/* Not affected by codec bus clock/reset */
-+#define SUN20I_CODEC_POWER 0x0348
-+#define SUN20I_CODEC_POWER_ALDO_EN_MASK BIT(31)
-+#define SUN20I_CODEC_POWER_HPLDO_EN_MASK BIT(30)
-+#define SUN20I_CODEC_POWER_ALDO_VOLTAGE_MASK GENMASK(14, 12)
-+#define SUN20I_CODEC_POWER_HPLDO_VOLTAGE_MASK GENMASK(10, 8)
-+
-+#define SUN20I_CODEC_ADC_CUR 0x034c
-+
-+#define SUN20I_CODEC_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE|\
-+ SNDRV_PCM_FMTBIT_S20_LE|\
-+ SNDRV_PCM_FMTBIT_S32_LE)
-+
-+#define DRIVER_NAME "sun20i-codec"
-+
-+/* snd_soc_register_card() takes over drvdata, so the card must be first! */
-+struct sun20i_codec {
-+ struct snd_soc_card card;
-+ struct snd_soc_dai_link dai_link;
-+ struct snd_soc_dai_link_component dlcs[3];
-+ struct snd_dmaengine_dai_dma_data dma_data[2];
-+
-+ struct clk *bus_clk;
-+ struct clk *adc_clk;
-+ struct clk *dac_clk;
-+ struct reset_control *reset;
-+};
-+
-+static int sun20i_codec_dai_probe(struct snd_soc_dai *dai)
-+{
-+ struct sun20i_codec *codec = snd_soc_dai_get_drvdata(dai);
-+
-+ snd_soc_dai_init_dma_data(dai,
-+ &codec->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
-+ &codec->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
-+
-+ return 0;
-+}
-+
-+static struct clk *sun20i_codec_get_clk(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ struct sun20i_codec *codec = snd_soc_dai_get_drvdata(dai);
-+
-+ return substream->stream == SNDRV_PCM_STREAM_CAPTURE ?
-+ codec->adc_clk : codec->dac_clk;
-+}
-+
-+static const unsigned int sun20i_codec_rates[] = {
-+ 7350, 8000, 11025, 12000, 14700, 16000, 22050, 24000,
-+ 29400, 32000, 44100, 48000, 88200, 96000, 176400, 192000,
-+};
-+
-+static const struct snd_pcm_hw_constraint_list sun20i_codec_rate_lists[] = {
-+ [SNDRV_PCM_STREAM_PLAYBACK] = {
-+ .list = sun20i_codec_rates,
-+ .count = ARRAY_SIZE(sun20i_codec_rates),
-+ },
-+ [SNDRV_PCM_STREAM_CAPTURE] = {
-+ .list = sun20i_codec_rates,
-+ .count = ARRAY_SIZE(sun20i_codec_rates) - 4, /* max 48 kHz */
-+ },
-+};
-+
-+static int sun20i_codec_startup(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ const struct snd_pcm_hw_constraint_list *list;
-+ int ret;
-+
-+ list = &sun20i_codec_rate_lists[substream->stream];
-+ ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
-+ SNDRV_PCM_HW_PARAM_RATE, list);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(sun20i_codec_get_clk(substream, dai));
-+ if (ret)
-+ return ret;
-+
-+ return 0;
-+}
-+
-+static void sun20i_codec_shutdown(struct snd_pcm_substream *substream,
-+ struct snd_soc_dai *dai)
-+{
-+ clk_disable_unprepare(sun20i_codec_get_clk(substream, dai));
-+}
-+
-+static unsigned int sun20i_codec_get_clk_rate(unsigned int sample_rate)
-+{
-+ return (sample_rate % 4000) ? 22579200 : 24576000;
-+}
-+
-+static const unsigned short sun20i_codec_divisors[] = {
-+ 512, 1024, 2048, 128,
-+ 768, 1536, 3072, 256,
-+};
-+
-+static int sun20i_codec_get_fs(unsigned int clk_rate, unsigned int sample_rate)
-+{
-+ unsigned int divisor = clk_rate / sample_rate;
-+ int i;
-+
-+ for (i = 0; i < ARRAY_SIZE(sun20i_codec_divisors); ++i)
-+ if (sun20i_codec_divisors[i] == divisor)
-+ return i;
-+
-+ return -EINVAL;
-+}
-+
-+static int sun20i_codec_hw_params(struct snd_pcm_substream *substream,
-+ struct snd_pcm_hw_params *params,
-+ struct snd_soc_dai *dai)
-+{
-+ struct sun20i_codec *codec = snd_soc_dai_get_drvdata(dai);
-+ struct snd_soc_component *component = dai->component;
-+ unsigned int channels = params_channels(params);
-+ unsigned int sample_bits = params_width(params);
-+ unsigned int sample_rate = params_rate(params);
-+ unsigned int clk_rate = sun20i_codec_get_clk_rate(sample_rate);
-+ enum dma_slave_buswidth dma_width;
-+ unsigned int reg;
-+ int ret, val;
-+
-+ switch (params_physical_width(params)) {
-+ case 16:
-+ dma_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
-+ break;
-+ case 32:
-+ dma_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
-+ break;
-+ default:
-+ dev_err(dai->dev, "Unsupported physical sample width: %d\n",
-+ params_physical_width(params));
-+ return -EINVAL;
-+ }
-+ codec->dma_data[substream->stream].addr_width = dma_width;
-+
-+ ret = clk_set_rate(sun20i_codec_get_clk(substream, dai),
-+ sun20i_codec_get_clk_rate(sample_rate));
-+ if (ret)
-+ return ret;
-+
-+ reg = substream->stream == SNDRV_PCM_STREAM_CAPTURE ?
-+ SUN20I_CODEC_ADC_FIFOC : SUN20I_CODEC_DAC_FIFOC;
-+
-+ val = sun20i_codec_get_fs(clk_rate, sample_rate);
-+ if (val < 0)
-+ return val;
-+ snd_soc_component_update_bits(component, reg,
-+ 0x7 << SUN20I_CODEC_DAC_FIFOC_FS,
-+ val << SUN20I_CODEC_DAC_FIFOC_FS);
-+
-+ /* Data is at MSB for full 4-byte samples, otherwise at LSB. */
-+ val = sample_bits != 32;
-+ snd_soc_component_update_bits(component, reg,
-+ 0x1 << SUN20I_CODEC_DAC_FIFOC_FIFO_MODE,
-+ val << SUN20I_CODEC_DAC_FIFOC_FIFO_MODE);
-+
-+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
-+ val = sample_bits > 16;
-+ snd_soc_component_update_bits(component, reg,
-+ 0x1 << SUN20I_CODEC_ADC_FIFOC_SAMPLE_BITS,
-+ val << SUN20I_CODEC_ADC_FIFOC_SAMPLE_BITS);
-+
-+ val = BIT(channels) - 1;
-+ snd_soc_component_update_bits(component, SUN20I_CODEC_ADC_DIG_CTRL,
-+ 0xf << SUN20I_CODEC_ADC_DIG_CTRL_ADC_EN,
-+ val << SUN20I_CODEC_ADC_DIG_CTRL_ADC_EN);
-+ } else {
-+ val = sample_bits > 16;
-+ snd_soc_component_update_bits(component, reg,
-+ 0x1 << SUN20I_CODEC_DAC_FIFOC_SAMPLE_BITS,
-+ val << SUN20I_CODEC_DAC_FIFOC_SAMPLE_BITS);
-+
-+ val = channels == 1;
-+ snd_soc_component_update_bits(component, reg,
-+ 0x1 << SUN20I_CODEC_DAC_FIFOC_MONO_EN,
-+ val << SUN20I_CODEC_DAC_FIFOC_MONO_EN);
-+ }
-+
-+ return 0;
-+}
-+
-+static int sun20i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
-+ struct snd_soc_dai *dai)
-+{
-+ struct snd_soc_component *component = dai->component;
-+ unsigned int reg, mask;
-+
-+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
-+ reg = SUN20I_CODEC_ADC_FIFOC;
-+ mask = BIT(SUN20I_CODEC_ADC_FIFOC_DRQ_EN);
-+ } else {
-+ reg = SUN20I_CODEC_DAC_FIFOC;
-+ mask = BIT(SUN20I_CODEC_DAC_FIFOC_DRQ_EN);
-+ }
-+
-+ switch (cmd) {
-+ case SNDRV_PCM_TRIGGER_START:
-+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-+ case SNDRV_PCM_TRIGGER_RESUME:
-+ mask |= BIT(SUN20I_CODEC_DAC_FIFOC_FIFO_FLUSH);
-+ snd_soc_component_update_bits(component, reg, mask, mask);
-+ break;
-+ case SNDRV_PCM_TRIGGER_STOP:
-+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-+ case SNDRV_PCM_TRIGGER_SUSPEND:
-+ snd_soc_component_update_bits(component, reg, mask, 0);
-+ break;
-+ default:
-+ return -EINVAL;
-+ }
-+
-+ return 0;
-+}
-+
-+static const struct snd_soc_dai_ops sun20i_codec_dai_ops = {
-+ .startup = sun20i_codec_startup,
-+ .shutdown = sun20i_codec_shutdown,
-+ .hw_params = sun20i_codec_hw_params,
-+ .trigger = sun20i_codec_trigger,
-+};
-+
-+static struct snd_soc_dai_driver sun20i_codec_dai = {
-+ .name = DRIVER_NAME,
-+ .probe = sun20i_codec_dai_probe,
-+ .ops = &sun20i_codec_dai_ops,
-+ .capture = {
-+ .stream_name = "Capture",
-+ .channels_min = 1,
-+ .channels_max = 3, /* ??? */
-+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
-+ .formats = SUN20I_CODEC_PCM_FORMATS,
-+ .sig_bits = 20,
-+ },
-+ .playback = {
-+ .stream_name = "Playback",
-+ .channels_min = 1,
-+ .channels_max = 2,
-+ .rates = SNDRV_PCM_RATE_CONTINUOUS,
-+ .formats = SUN20I_CODEC_PCM_FORMATS,
-+ .sig_bits = 20,
-+ },
-+};
-+
-+static const DECLARE_TLV_DB_SCALE(sun20i_codec_boost_vol_scale, 0, 600, 0);
-+static const DECLARE_TLV_DB_SCALE(sun20i_codec_digital_vol_scale, -12000, 75, 1);
-+static const DECLARE_TLV_DB_SCALE(sun20i_codec_headphone_vol_scale, -4200, 600, 0);
-+/* FIXME */
-+static const DECLARE_TLV_DB_SCALE(sun20i_codec_line_out_vol_scale, -4650, 150, 1);
-+/* FIXME */
-+static const DECLARE_TLV_DB_SCALE(sun20i_codec_pga_vol_scale, 500, 100, 0);
-+
-+static const char *const sun20i_codec_line_out_mode_enum_text[] = {
-+ "Single-Ended", "Differential"
-+};
-+
-+static const SOC_ENUM_DOUBLE_DECL(sun20i_codec_line_out_mode_enum,
-+ SUN20I_CODEC_DAC,
-+ SUN20I_CODEC_DAC_LINEOUTL_DIFFEN,
-+ SUN20I_CODEC_DAC_LINEOUTR_DIFFEN,
-+ sun20i_codec_line_out_mode_enum_text);
-+
-+static const struct snd_kcontrol_new sun20i_codec_controls[] = {
-+ /* Digital Controls */
-+ SOC_DOUBLE_TLV("DAC Playback Volume",
-+ SUN20I_CODEC_DAC_VOL_CTRL,
-+ SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_L,
-+ SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_R,
-+ 0xc0, 0, sun20i_codec_digital_vol_scale),
-+ SOC_SINGLE_TLV("ADC3 Capture Volume",
-+ SUN20I_CODEC_ADC_VOL_CTRL,
-+ SUN20I_CODEC_ADC_VOL_CTRL_ADC3_VOL,
-+ 0xc0, 0, sun20i_codec_digital_vol_scale),
-+ SOC_SINGLE_TLV("ADC2 Capture Volume",
-+ SUN20I_CODEC_ADC_VOL_CTRL,
-+ SUN20I_CODEC_ADC_VOL_CTRL_ADC2_VOL,
-+ 0xc0, 0, sun20i_codec_digital_vol_scale),
-+ SOC_SINGLE_TLV("ADC1 Capture Volume",
-+ SUN20I_CODEC_ADC_VOL_CTRL,
-+ SUN20I_CODEC_ADC_VOL_CTRL_ADC1_VOL,
-+ 0xc0, 0, sun20i_codec_digital_vol_scale),
-+
-+ /* Analog Controls */
-+ SOC_DOUBLE_R_TLV("FM Capture Volume",
-+ SUN20I_CODEC_ADC1,
-+ SUN20I_CODEC_ADC2,
-+ SUN20I_CODEC_ADC1_FMINL_GAIN,
-+ 0x1, 0, sun20i_codec_boost_vol_scale),
-+ SOC_DOUBLE_R_TLV("Line In Capture Volume",
-+ SUN20I_CODEC_ADC1,
-+ SUN20I_CODEC_ADC2,
-+ SUN20I_CODEC_ADC1_LINEINL_GAIN,
-+ 0x1, 0, sun20i_codec_boost_vol_scale),
-+ SOC_ENUM("Line Out Mode Playback Enum",
-+ sun20i_codec_line_out_mode_enum),
-+ SOC_SINGLE_TLV("Line Out Playback Volume",
-+ SUN20I_CODEC_DAC,
-+ SUN20I_CODEC_DAC_LINEOUT_VOL_CTRL,
-+ 0x1f, 0, sun20i_codec_line_out_vol_scale),
-+ SOC_SINGLE_TLV("Headphone Playback Volume",
-+ SUN20I_CODEC_HP2,
-+ SUN20I_CODEC_HP2_HEADPHONE_GAIN,
-+ 0x7, 1, sun20i_codec_headphone_vol_scale),
-+};
-+
-+static const struct snd_kcontrol_new sun20i_codec_line_out_switch =
-+ SOC_DAPM_DOUBLE("Line Out Playback Switch",
-+ SUN20I_CODEC_DAC,
-+ SUN20I_CODEC_DAC_LMUTE,
-+ SUN20I_CODEC_DAC_RMUTE, 1, 1);
-+
-+static const struct snd_kcontrol_new sun20i_codec_hp_switch =
-+ SOC_DAPM_SINGLE("Headphone Playback Switch",
-+ SUN20I_CODEC_HP2,
-+ SUN20I_CODEC_HP2_HP_DRVOUTEN, 1, 0);
-+
-+static const struct snd_kcontrol_new sun20i_codec_adc12_mixer_controls[] = {
-+ /* ADC1 Only */
-+ SOC_DAPM_SINGLE("Mic1 Capture Switch",
-+ SUN20I_CODEC_ADC1,
-+ SUN20I_CODEC_ADC1_MICIN1_SIN_EN, 1, 0),
-+ /* Shared */
-+ SOC_DAPM_DOUBLE_R("FM Capture Switch",
-+ SUN20I_CODEC_ADC1,
-+ SUN20I_CODEC_ADC2,
-+ SUN20I_CODEC_ADC1_FMINL_EN, 1, 0),
-+ /* Shared */
-+ SOC_DAPM_DOUBLE_R("Line In Capture Switch",
-+ SUN20I_CODEC_ADC1,
-+ SUN20I_CODEC_ADC2,
-+ SUN20I_CODEC_ADC1_LINEINL_EN, 1, 0),
-+ /* ADC2 Only */
-+ SOC_DAPM_SINGLE("Mic2 Capture Switch",
-+ SUN20I_CODEC_ADC2,
-+ SUN20I_CODEC_ADC2_MICIN2_SIN_EN, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new sun20i_codec_adc3_mixer_controls[] = {
-+ SOC_DAPM_SINGLE("Mic3 Capture Switch",
-+ SUN20I_CODEC_ADC3,
-+ SUN20I_CODEC_ADC3_MICIN3_SIN_EN, 1, 0),
-+};
-+
-+static const struct snd_kcontrol_new sun20i_codec_mic1_volume =
-+ SOC_DAPM_SINGLE_TLV("Capture Volume",
-+ SUN20I_CODEC_ADC1,
-+ SUN20I_CODEC_ADC1_ADC1_PGA_GAIN,
-+ 0x1f, 0, sun20i_codec_pga_vol_scale);
-+
-+static const struct snd_kcontrol_new sun20i_codec_mic2_volume =
-+ SOC_DAPM_SINGLE_TLV("Capture Volume",
-+ SUN20I_CODEC_ADC2,
-+ SUN20I_CODEC_ADC2_ADC2_PGA_GAIN,
-+ 0x1f, 0, sun20i_codec_pga_vol_scale);
-+
-+static const struct snd_kcontrol_new sun20i_codec_mic3_volume =
-+ SOC_DAPM_SINGLE_TLV("Capture Volume",
-+ SUN20I_CODEC_ADC3,
-+ SUN20I_CODEC_ADC3_ADC3_PGA_GAIN,
-+ 0x1f, 0, sun20i_codec_pga_vol_scale);
-+
-+static const struct snd_soc_dapm_widget sun20i_codec_widgets[] = {
-+ /* Playback */
-+ SND_SOC_DAPM_OUTPUT("LINEOUTL"),
-+ SND_SOC_DAPM_OUTPUT("LINEOUTR"),
-+
-+ SND_SOC_DAPM_SWITCH("LINEOUTL Switch",
-+ SUN20I_CODEC_DAC,
-+ SUN20I_CODEC_DAC_LINEOUTL_EN, 0,
-+ &sun20i_codec_line_out_switch),
-+ SND_SOC_DAPM_SWITCH("LINEOUTR Switch",
-+ SUN20I_CODEC_DAC,
-+ SUN20I_CODEC_DAC_LINEOUTR_EN, 0,
-+ &sun20i_codec_line_out_switch),
-+
-+ SND_SOC_DAPM_OUTPUT("HPOUTL"),
-+ SND_SOC_DAPM_OUTPUT("HPOUTR"),
-+
-+ SND_SOC_DAPM_SWITCH("HPOUTL Switch",
-+ SND_SOC_NOPM, 0, 0, &sun20i_codec_hp_switch),
-+ SND_SOC_DAPM_SWITCH("HPOUTR Switch",
-+ SND_SOC_NOPM, 0, 0, &sun20i_codec_hp_switch),
-+ SND_SOC_DAPM_SUPPLY("Headphone Driver",
-+ SUN20I_CODEC_HP2,
-+ SUN20I_CODEC_HP2_HP_DRVEN, 0, NULL, 0),
-+
-+ SND_SOC_DAPM_DAC("DACL", NULL,
-+ SUN20I_CODEC_DAC,
-+ SUN20I_CODEC_DAC_DACL_EN, 0),
-+ SND_SOC_DAPM_DAC("DACR", NULL,
-+ SUN20I_CODEC_DAC,
-+ SUN20I_CODEC_DAC_DACR_EN, 0),
-+ SND_SOC_DAPM_SUPPLY("DAC",
-+ SUN20I_CODEC_DAC_DPC,
-+ SUN20I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0),
-+
-+ SND_SOC_DAPM_AIF_IN("DACL FIFO", "Playback", 0,
-+ SND_SOC_NOPM, 0, 0),
-+ SND_SOC_DAPM_AIF_IN("DACR FIFO", "Playback", 1,
-+ SND_SOC_NOPM, 0, 0),
-+
-+ /* Capture */
-+ SND_SOC_DAPM_AIF_OUT("ADC1 FIFO", "Capture", 0,
-+ SND_SOC_NOPM, 0, 0),
-+ SND_SOC_DAPM_AIF_OUT("ADC2 FIFO", "Capture", 1,
-+ SND_SOC_NOPM, 0, 0),
-+ SND_SOC_DAPM_AIF_OUT("ADC3 FIFO", "Capture", 2,
-+ SND_SOC_NOPM, 0, 0),
-+
-+ SND_SOC_DAPM_ADC("ADC1", NULL,
-+ SUN20I_CODEC_ADC1,
-+ SUN20I_CODEC_ADC1_ADC1_EN, 0),
-+ SND_SOC_DAPM_ADC("ADC2", NULL,
-+ SUN20I_CODEC_ADC2,
-+ SUN20I_CODEC_ADC2_ADC2_EN, 0),
-+ SND_SOC_DAPM_ADC("ADC3", NULL,
-+ SUN20I_CODEC_ADC3,
-+ SUN20I_CODEC_ADC3_ADC3_EN, 0),
-+ SND_SOC_DAPM_SUPPLY("ADC",
-+ SUN20I_CODEC_ADC_FIFOC,
-+ SUN20I_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0),
-+
-+ SND_SOC_DAPM_MIXER_NAMED_CTL("ADC1 Mixer", SND_SOC_NOPM, 0, 0,
-+ sun20i_codec_adc12_mixer_controls, 3),
-+ SND_SOC_DAPM_MIXER_NAMED_CTL("ADC2 Mixer", SND_SOC_NOPM, 0, 0,
-+ sun20i_codec_adc12_mixer_controls + 1, 3),
-+ SND_SOC_DAPM_MIXER_NAMED_CTL("ADC3 Mixer", SND_SOC_NOPM, 0, 0,
-+ sun20i_codec_adc3_mixer_controls,
-+ ARRAY_SIZE(sun20i_codec_adc3_mixer_controls)),
-+
-+ SND_SOC_DAPM_PGA("Mic1",
-+ SUN20I_CODEC_ADC1,
-+ SUN20I_CODEC_ADC1_MICIN1_PGA_EN, 0,
-+ &sun20i_codec_mic1_volume, 1),
-+ SND_SOC_DAPM_PGA("Mic2",
-+ SUN20I_CODEC_ADC2,
-+ SUN20I_CODEC_ADC2_MICIN2_PGA_EN, 0,
-+ &sun20i_codec_mic2_volume, 1),
-+ SND_SOC_DAPM_PGA("Mic3",
-+ SUN20I_CODEC_ADC3,
-+ SUN20I_CODEC_ADC3_MICIN3_PGA_EN, 0,
-+ &sun20i_codec_mic3_volume, 1),
-+
-+ SND_SOC_DAPM_INPUT("MICIN1"),
-+ SND_SOC_DAPM_INPUT("MICIN2"),
-+ SND_SOC_DAPM_INPUT("MICIN3"),
-+
-+ SND_SOC_DAPM_INPUT("FMINL"),
-+ SND_SOC_DAPM_INPUT("FMINR"),
-+
-+ SND_SOC_DAPM_INPUT("LINEINL"),
-+ SND_SOC_DAPM_INPUT("LINEINR"),
-+
-+ SND_SOC_DAPM_SUPPLY("HBIAS",
-+ SUN20I_CODEC_MICBIAS,
-+ SUN20I_CODEC_MICBIAS_HMICBIASEN, 0, NULL, 0),
-+ SND_SOC_DAPM_SUPPLY("MBIAS",
-+ SUN20I_CODEC_MICBIAS,
-+ SUN20I_CODEC_MICBIAS_MMICBIASEN, 0, NULL, 0),
-+
-+ SND_SOC_DAPM_REGULATOR_SUPPLY("avcc", 0, 0),
-+ SND_SOC_DAPM_REGULATOR_SUPPLY("hpvcc", 0, 0),
-+ SND_SOC_DAPM_REGULATOR_SUPPLY("vdd33", 0, 0),
-+};
-+
-+static const struct snd_soc_dapm_route sun20i_codec_routes[] = {
-+ /* Playback */
-+ { "LINEOUTL", NULL, "LINEOUTL Switch" },
-+ { "LINEOUTR", NULL, "LINEOUTR Switch" },
-+
-+ { "LINEOUTL Switch", "Line Out Playback Switch", "DACL" },
-+ { "LINEOUTR Switch", "Line Out Playback Switch", "DACR" },
-+
-+ { "HPOUTL", NULL, "HPOUTL Switch" },
-+ { "HPOUTR", NULL, "HPOUTR Switch" },
-+
-+ { "HPOUTL Switch", "Headphone Playback Switch", "DACL" },
-+ { "HPOUTR Switch", "Headphone Playback Switch", "DACR" },
-+ { "HPOUTL Switch", NULL, "Headphone Driver" },
-+ { "HPOUTR Switch", NULL, "Headphone Driver" },
-+ { "Headphone Driver", NULL, "hpvcc" },
-+
-+ { "DACL", NULL, "DACL FIFO" },
-+ { "DACR", NULL, "DACR FIFO" },
-+ { "DACL", NULL, "DAC" },
-+ { "DACR", NULL, "DAC" },
-+ { "DACL", NULL, "avcc" },
-+ { "DACR", NULL, "avcc" },
-+
-+ /* Capture */
-+ { "ADC1 FIFO", NULL, "ADC1" },
-+ { "ADC2 FIFO", NULL, "ADC2" },
-+ { "ADC3 FIFO", NULL, "ADC3" },
-+
-+ { "ADC1", NULL, "ADC1 Mixer" },
-+ { "ADC2", NULL, "ADC2 Mixer" },
-+ { "ADC3", NULL, "ADC3 Mixer" },
-+ { "ADC1", NULL, "ADC" },
-+ { "ADC2", NULL, "ADC" },
-+ { "ADC3", NULL, "ADC" },
-+ { "ADC1", NULL, "avcc" },
-+ { "ADC2", NULL, "avcc" },
-+ { "ADC3", NULL, "avcc" },
-+
-+ { "ADC1 Mixer", "Mic1 Capture Switch", "Mic1" },
-+ { "ADC2 Mixer", "Mic2 Capture Switch", "Mic2" },
-+ { "ADC3 Mixer", "Mic3 Capture Switch", "Mic3" },
-+ { "ADC1 Mixer", "FM Capture Switch", "FMINL" },
-+ { "ADC2 Mixer", "FM Capture Switch", "FMINR" },
-+ { "ADC1 Mixer", "Line In Capture Switch", "LINEINL" },
-+ { "ADC2 Mixer", "Line In Capture Switch", "LINEINR" },
-+
-+ { "Mic1", NULL, "MICIN1" },
-+ { "Mic2", NULL, "MICIN2" },
-+ { "Mic3", NULL, "MICIN3" },
-+
-+ { "HBIAS", NULL, "vdd33" },
-+ { "MBIAS", NULL, "vdd33" },
-+};
-+
-+static int sun20i_codec_component_probe(struct snd_soc_component *component)
-+{
-+ struct sun20i_codec *codec = snd_soc_component_get_drvdata(component);
-+ int ret;
-+
-+ ret = reset_control_deassert(codec->reset);
-+ if (ret)
-+ return ret;
-+
-+ ret = clk_prepare_enable(codec->bus_clk);
-+ if (ret)
-+ goto err_assert_reset;
-+
-+ /* Enable digital volume control. */
-+ snd_soc_component_update_bits(component, SUN20I_CODEC_DAC_VOL_CTRL,
-+ 0x1 << SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_SEL,
-+ 0x1 << SUN20I_CODEC_DAC_VOL_CTRL_DAC_VOL_SEL);
-+ snd_soc_component_update_bits(component, SUN20I_CODEC_ADC_DIG_CTRL,
-+ 0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN,
-+ 0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN);
-+
-+ return 0;
-+
-+err_assert_reset:
-+ reset_control_assert(codec->reset);
-+
-+ return ret;
-+}
-+
-+static void sun20i_codec_component_remove(struct snd_soc_component *component)
-+{
-+ struct sun20i_codec *codec = snd_soc_component_get_drvdata(component);
-+
-+ clk_disable_unprepare(codec->bus_clk);
-+ reset_control_assert(codec->reset);
-+}
-+
-+static const struct snd_soc_component_driver sun20i_codec_component = {
-+ .controls = sun20i_codec_controls,
-+ .num_controls = ARRAY_SIZE(sun20i_codec_controls),
-+ .dapm_widgets = sun20i_codec_widgets,
-+ .num_dapm_widgets = ARRAY_SIZE(sun20i_codec_widgets),
-+ .dapm_routes = sun20i_codec_routes,
-+ .num_dapm_routes = ARRAY_SIZE(sun20i_codec_routes),
-+ .probe = sun20i_codec_component_probe,
-+ .remove = sun20i_codec_component_remove,
-+};
-+
-+static int sun20i_codec_init_card(struct device *dev,
-+ struct sun20i_codec *codec)
-+{
-+ struct snd_soc_dai_link *dai_link = &codec->dai_link;
-+ struct snd_soc_card *card = &codec->card;
-+ int ret;
-+
-+ codec->dlcs[0].of_node = dev->of_node;
-+ codec->dlcs[0].dai_name = DRIVER_NAME;
-+ codec->dlcs[1].name = "snd-soc-dummy";
-+ codec->dlcs[1].dai_name = "snd-soc-dummy-dai";
-+ codec->dlcs[2].of_node = dev->of_node;
-+
-+ dai_link->name = DRIVER_NAME;
-+ dai_link->stream_name = DRIVER_NAME;
-+ dai_link->cpus = &codec->dlcs[0];
-+ dai_link->num_cpus = 1;
-+ dai_link->codecs = &codec->dlcs[1];
-+ dai_link->num_codecs = 1;
-+ dai_link->platforms = &codec->dlcs[2];
-+ dai_link->num_platforms = 1;
-+
-+ card->name = DRIVER_NAME;
-+ card->dev = dev;
-+ card->owner = THIS_MODULE;
-+ card->dai_link = dai_link;
-+ card->num_links = 1;
-+ card->fully_routed = true;
-+
-+ ret = snd_soc_of_parse_aux_devs(card, "aux-devs");
-+ if (ret)
-+ return ret;
-+
-+ ret = snd_soc_of_parse_pin_switches(card, "pin-switches");
-+ if (ret)
-+ return ret;
-+
-+ ret = snd_soc_of_parse_audio_routing(card, "routing");
-+ if (ret)
-+ return ret;
-+
-+ ret = snd_soc_of_parse_audio_simple_widgets(card, "widgets");
-+ if (ret)
-+ return ret;
-+
-+ return 0;
-+}
-+
-+static const struct regmap_config sun20i_codec_regmap_config = {
-+ .reg_bits = 32,
-+ .reg_stride = 4,
-+ .val_bits = 32,
-+ .max_register = SUN20I_CODEC_ADC_CUR,
-+};
-+
-+static int sun20i_codec_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
-+ struct sun20i_codec *codec;
-+ struct regmap *regmap;
-+ struct resource *res;
-+ void __iomem *base;
-+ int ret;
-+
-+ codec = devm_kzalloc(dev, sizeof(*codec), GFP_KERNEL);
-+ if (!codec)
-+ return -ENOMEM;
-+
-+ dev_set_drvdata(dev, codec);
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ base = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(base))
-+ return dev_err_probe(dev, PTR_ERR(base),
-+ "Failed to map registers\n");
-+
-+ regmap = devm_regmap_init_mmio(dev, base,
-+ &sun20i_codec_regmap_config);
-+ if (IS_ERR(regmap))
-+ return dev_err_probe(dev, PTR_ERR(regmap),
-+ "Failed to create regmap\n");
-+
-+ codec->bus_clk = devm_clk_get(dev, "bus");
-+ if (IS_ERR(codec->bus_clk))
-+ return dev_err_probe(dev, PTR_ERR(codec->bus_clk),
-+ "Failed to get bus clock\n");
-+
-+ codec->adc_clk = devm_clk_get(dev, "adc");
-+ if (IS_ERR(codec->adc_clk))
-+ return dev_err_probe(dev, PTR_ERR(codec->adc_clk),
-+ "Failed to get ADC clock\n");
-+
-+ codec->dac_clk = devm_clk_get(dev, "dac");
-+ if (IS_ERR(codec->dac_clk))
-+ return dev_err_probe(dev, PTR_ERR(codec->dac_clk),
-+ "Failed to get DAC clock\n");
-+
-+ codec->reset = devm_reset_control_get_exclusive(dev, NULL);
-+ if (IS_ERR(codec->reset))
-+ return dev_err_probe(dev, PTR_ERR(codec->reset),
-+ "Failed to get reset\n");
-+
-+ ret = devm_snd_soc_register_component(dev, &sun20i_codec_component,
-+ &sun20i_codec_dai, 1);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Failed to register component\n");
-+
-+ codec->dma_data[SNDRV_PCM_STREAM_PLAYBACK].addr =
-+ res->start + SUN20I_CODEC_DAC_TXDATA;
-+ codec->dma_data[SNDRV_PCM_STREAM_PLAYBACK].maxburst = 8;
-+ codec->dma_data[SNDRV_PCM_STREAM_CAPTURE].addr =
-+ res->start + SUN20I_CODEC_ADC_RXDATA;
-+ codec->dma_data[SNDRV_PCM_STREAM_CAPTURE].maxburst = 8;
-+
-+ ret = devm_snd_dmaengine_pcm_register(dev, NULL, 0);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Failed to register PCM\n");
-+
-+ ret = sun20i_codec_init_card(dev, codec);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Failed to initialize card\n");
-+
-+ ret = devm_snd_soc_register_card(dev, &codec->card);
-+ if (ret)
-+ return dev_err_probe(dev, ret, "Failed to register card\n");
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id sun20i_codec_of_match[] = {
-+ { .compatible = "allwinner,sun20i-d1-codec" },
-+ {}
-+};
-+MODULE_DEVICE_TABLE(of, sun20i_codec_of_match);
-+
-+static struct platform_driver sun20i_codec_driver = {
-+ .driver = {
-+ .name = DRIVER_NAME,
-+ .of_match_table = sun20i_codec_of_match,
-+ },
-+ .probe = sun20i_codec_probe,
-+};
-+module_platform_driver(sun20i_codec_driver);
-+
-+MODULE_DESCRIPTION("Allwinner D1 (sun20i) codec driver");
-+MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
-+MODULE_LICENSE("GPL");
-+MODULE_ALIAS("platform:sun20i-codec");
+++ /dev/null
-From 87a77f803f5038e3fc64f45d5142ea402512029a Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 23 Jun 2021 21:18:47 -0500
-Subject: [PATCH 082/117] ASoC: sun20i-codec: What is this ramp thing?
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- sound/soc/sunxi/sun20i-codec.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/sound/soc/sunxi/sun20i-codec.c
-+++ b/sound/soc/sunxi/sun20i-codec.c
-@@ -709,6 +709,10 @@ static int sun20i_codec_component_probe(
- 0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN,
- 0x3 << SUN20I_CODEC_ADC_DIG_CTRL_ADC_VOL_EN);
-
-+ /* Maaagic... */
-+ snd_soc_component_update_bits(component, SUN20I_CODEC_RAMP,
-+ BIT(1) | BIT(0), BIT(0));
-+
- return 0;
-
- err_assert_reset:
+++ /dev/null
-From 54b1030c72d74ba6390d62086cbfc6a511f58aa7 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 00:39:42 -0500
-Subject: [PATCH 083/117] riscv: dts: allwinner: d1: Add sound cards to boards
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../sun20i-d1-common-regulators.dtsi | 5 +++++
- .../sun20i-d1-lichee-rv-86-panel.dtsi | 21 +++++++++++++++++++
- .../allwinner/sun20i-d1-lichee-rv-dock.dts | 12 +++++++++++
- .../boot/dts/allwinner/sun20i-d1-nezha.dts | 12 +++++++++++
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 13 +++++++++++-
- 5 files changed, 62 insertions(+), 1 deletion(-)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-common-regulators.dtsi
-@@ -18,6 +18,11 @@
- };
- };
-
-+&codec {
-+ avcc-supply = <®_aldo>;
-+ hpvcc-supply = <®_hpldo>;
-+};
-+
- &lradc {
- vref-supply = <®_aldo>;
- };
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel.dtsi
-@@ -9,6 +9,12 @@
- ethernet1 = &xr829;
- };
-
-+ audio_amplifier: audio-amplifier {
-+ compatible = "simple-audio-amplifier";
-+ enable-gpios = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
-+ sound-name-prefix = "Amplifier";
-+ };
-+
- dmic_codec: dmic-codec {
- compatible = "dmic-codec";
- num-channels = <2>;
-@@ -51,6 +57,21 @@
- };
- };
-
-+&codec {
-+ aux-devs = <&audio_amplifier>;
-+ routing = "Internal Speaker", "Amplifier OUTL",
-+ "Internal Speaker", "Amplifier OUTR",
-+ "Amplifier INL", "HPOUTL",
-+ "Amplifier INR", "HPOUTR",
-+ "LINEINL", "HPOUTL",
-+ "LINEINR", "HPOUTR",
-+ "MICIN3", "Internal Microphone",
-+ "Internal Microphone", "HBIAS";
-+ widgets = "Microphone", "Internal Microphone",
-+ "Speaker", "Internal Speaker";
-+ status = "okay";
-+};
-+
- &dmic {
- pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
- pinctrl-names = "default";
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts
-@@ -48,6 +48,18 @@
- };
- };
-
-+&codec {
-+ routing = "Internal Speaker", "HPOUTL",
-+ "Internal Speaker", "HPOUTR",
-+ "LINEINL", "HPOUTL",
-+ "LINEINR", "HPOUTR",
-+ "MICIN3", "Internal Microphone",
-+ "Internal Microphone", "HBIAS";
-+ widgets = "Microphone", "Internal Microphone",
-+ "Speaker", "Internal Speaker";
-+ status = "okay";
-+};
-+
- &dmic {
- pinctrl-0 = <&dmic_pb11_d0_pin>, <&dmic_pe17_clk_pin>;
- pinctrl-names = "default";
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts
-@@ -51,6 +51,18 @@
- };
- };
-
-+&codec {
-+ routing = "Headphone Jack", "HPOUTL",
-+ "Headphone Jack", "HPOUTR",
-+ "LINEINL", "HPOUTL",
-+ "LINEINR", "HPOUTR",
-+ "MICIN3", "Headset Microphone",
-+ "Headset Microphone", "HBIAS";
-+ widgets = "Microphone", "Headset Microphone",
-+ "Headphone", "Headphone Jack";
-+ status = "okay";
-+};
-+
- &cpu0 {
- cpu-supply = <®_vdd_cpu>;
- };
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -312,10 +312,21 @@
- };
-
- codec: audio-codec@2030000 {
-- compatible = "simple-mfd", "syscon";
-+ compatible = "allwinner,sun20i-d1-codec", "simple-mfd", "syscon";
- reg = <0x2030000 0x1000>;
-+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_AUDIO>,
-+ <&ccu CLK_AUDIO_ADC>,
-+ <&ccu CLK_AUDIO_DAC>,
-+ <&osc24M>,
-+ <&rtc CLK_OSC32K>;
-+ clock-names = "bus", "adc", "dac", "hosc", "losc";
-+ resets = <&ccu RST_BUS_AUDIO>;
-+ dmas = <&dma 7>, <&dma 7>;
-+ dma-names = "rx", "tx";
- #address-cells = <1>;
- #size-cells = <1>;
-+ #sound-dai-cells = <0>;
-
- regulators@2030348 {
- compatible = "allwinner,sun20i-d1-analog-ldos";
+++ /dev/null
-From bae2790f627eb30ec3845167341b108e13328f6f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:46:43 -0500
-Subject: [PATCH 084/117] drm/sun4i: dsi: Allow panel attach before card
- registration
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-@@ -967,13 +967,12 @@ static int sun6i_dsi_attach(struct mipi_
-
- if (IS_ERR(panel))
- return PTR_ERR(panel);
-- if (!dsi->drm || !dsi->drm->registered)
-- return -EPROBE_DEFER;
-
- dsi->panel = panel;
- dsi->device = device;
-
-- drm_kms_helper_hotplug_event(dsi->drm);
-+ if (dsi->drm && dsi->drm->registered)
-+ drm_kms_helper_hotplug_event(dsi->drm);
-
- dev_info(host->dev, "Attached device %s\n", device->name);
-
-@@ -988,7 +987,8 @@ static int sun6i_dsi_detach(struct mipi_
- dsi->panel = NULL;
- dsi->device = NULL;
-
-- drm_kms_helper_hotplug_event(dsi->drm);
-+ if (dsi->drm && dsi->drm->registered)
-+ drm_kms_helper_hotplug_event(dsi->drm);
-
- return 0;
- }
+++ /dev/null
-From 5755bea969adcb00b102271b0cbaa3002acd7a35 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 27 Apr 2022 18:50:01 -0500
-Subject: [PATCH 085/117] drm/sun4i: mixer: Remove unused CMA headers
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun8i_mixer.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
-+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
-@@ -17,7 +17,7 @@
- #include <drm/drm_atomic_helper.h>
- #include <drm/drm_crtc.h>
- #include <drm/drm_framebuffer.h>
--#include <drm/drm_gem_dma_helper.h>
-+#include <drm/drm_print.h>
- #include <drm/drm_probe_helper.h>
-
- #include "sun4i_drv.h"
+++ /dev/null
-From 9a7acb8f03346705d7420a490d95b32309d90e22 Mon Sep 17 00:00:00 2001
-From: Roman Beranek <roman.beranek@prusa3d.com>
-Date: Wed, 25 Nov 2020 13:07:35 +0100
-Subject: [PATCH 086/117] drm/sun4i: decouple TCON_DCLK_DIV value from
- pll_mipi/dotclock ratio
-
-Observations showed that an actual refresh rate differs from the intended.
-Specifically, in case of 4-lane panels it was reduced by 1/3, and in case of
-2-lane panels by 2/3.
-
-BSP code apparently distinguishes between a `dsi_div` and a 'tcon inner div'.
-While this 'inner' divider is under DSI always 4, the `dsi_div` is defined
-as a number of bits per pixel over a number of DSI lanes. This value is then
-involved in setting the rate of PLL_MIPI.
-
-I couldn't really figure out how to fit this into the dotclock driver,
-so I opted for this hack where the requested rate is adjusted in such a way
-that the sun4i_dotclock driver can remain untouched.
-
-Signed-off-by: Roman Beranek <roman.beranek@prusa3d.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun4i_tcon.c | 44 +++++++++++++++++-------------
- 1 file changed, 25 insertions(+), 19 deletions(-)
-
---- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
-+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
-@@ -291,18 +291,6 @@ static int sun4i_tcon_get_clk_delay(cons
- return delay;
- }
-
--static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
-- const struct drm_display_mode *mode)
--{
-- /* Configure the dot clock */
-- clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
--
-- /* Set the resolution */
-- regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
-- SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
-- SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
--}
--
- static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
- const struct drm_connector *connector)
- {
-@@ -365,12 +353,18 @@ static void sun4i_tcon0_mode_set_cpu(str
- u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format);
- u8 lanes = device->lanes;
- u32 block_space, start_delay;
-- u32 tcon_div;
-
- tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
- tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
-
-- sun4i_tcon0_mode_set_common(tcon, mode);
-+ /* Configure the dot clock */
-+ clk_set_rate(tcon->dclk, mode->crtc_clock * 1000
-+ * bpp / (lanes * SUN6I_DSI_TCON_DIV));
-+
-+ /* Set the resolution */
-+ regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
-+ SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
-+ SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
-
- /* Set dithering if needed */
- sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
-@@ -394,9 +388,7 @@ static void sun4i_tcon0_mode_set_cpu(str
- * The datasheet says that this should be set higher than 20 *
- * pixel cycle, but it's not clear what a pixel cycle is.
- */
-- regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div);
-- tcon_div &= GENMASK(6, 0);
-- block_space = mode->htotal * bpp / (tcon_div * lanes);
-+ block_space = mode->htotal * bpp / (SUN6I_DSI_TCON_DIV * lanes);
- block_space -= mode->hdisplay + 40;
-
- regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG,
-@@ -438,7 +430,14 @@ static void sun4i_tcon0_mode_set_lvds(st
-
- tcon->dclk_min_div = 7;
- tcon->dclk_max_div = 7;
-- sun4i_tcon0_mode_set_common(tcon, mode);
-+
-+ /* Configure the dot clock */
-+ clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
-+
-+ /* Set the resolution */
-+ regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
-+ SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
-+ SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
-
- /* Set dithering if needed */
- sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
-@@ -515,7 +514,14 @@ static void sun4i_tcon0_mode_set_rgb(str
-
- tcon->dclk_min_div = tcon->quirks->dclk_min_div;
- tcon->dclk_max_div = 127;
-- sun4i_tcon0_mode_set_common(tcon, mode);
-+
-+ /* Configure the dot clock */
-+ clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
-+
-+ /* Set the resolution */
-+ regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
-+ SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
-+ SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
-
- /* Set dithering if needed */
- sun4i_tcon0_mode_set_dithering(tcon, connector);
+++ /dev/null
-From 9ea0c216d4f85a8ea888a38853e9573bbd9e995a Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 21:09:39 -0500
-Subject: [PATCH 087/117] drm/sun4i: tcon: Always protect the LCD dotclock rate
-
-This handles the case where multiple CRTCs get their .mode_set function
-called during the same atomic commit, before rate protection is applied
-by enabling the CRTC.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun4i_dotclock.c | 4 ++++
- drivers/gpu/drm/sun4i/sun4i_tcon.c | 6 ++++--
- 2 files changed, 8 insertions(+), 2 deletions(-)
-
---- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
-+++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
-@@ -6,6 +6,7 @@
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- */
-
-+#include <linux/clk.h>
- #include <linux/clk-provider.h>
- #include <linux/regmap.h>
-
-@@ -194,12 +195,15 @@ int sun4i_dclk_create(struct device *dev
- if (IS_ERR(tcon->dclk))
- return PTR_ERR(tcon->dclk);
-
-+ clk_rate_exclusive_get(tcon->dclk);
-+
- return 0;
- }
- EXPORT_SYMBOL(sun4i_dclk_create);
-
- int sun4i_dclk_free(struct sun4i_tcon *tcon)
- {
-+ clk_rate_exclusive_put(tcon->dclk);
- clk_unregister(tcon->dclk);
- return 0;
- }
---- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
-+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
-@@ -108,9 +108,11 @@ static void sun4i_tcon_channel_set_statu
-
- if (enabled) {
- clk_prepare_enable(clk);
-- clk_rate_exclusive_get(clk);
-+ if (clk != tcon->dclk)
-+ clk_rate_exclusive_get(clk);
- } else {
-- clk_rate_exclusive_put(clk);
-+ if (clk != tcon->dclk)
-+ clk_rate_exclusive_put(clk);
- clk_disable_unprepare(clk);
- }
- }
+++ /dev/null
-From f792492db1f42c43eb4b8bb72ce573418afc933d Mon Sep 17 00:00:00 2001
-From: Jagan Teki <jagan@amarulasolutions.com>
-Date: Tue, 31 Dec 2019 18:35:24 +0530
-Subject: [PATCH 088/117] drm/sun4i: tcon_top: Register reset, clock gates in
- probe
-
-TCON TOP is processing clock gates and reset control for
-TV0, TV1 and DSI channels during bind and release the same
-during unbind component ops.
-
-The usual DSI initialization would setup all controller
-clocks along with DPHY clocking during probe.
-
-Since the actual clock gates (along with DSI clock gate)
-are initialized during ton top bind, the DPHY is failed to
-get the DSI clock during that time.
-
-To solve, this circular dependency move the reset control,
-clock gate registration from bind to probe and release the
-same from unbind to remove.
-
-This eventually give a chance DPHY to initialize the DSI
-clock gate.
-
-Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 42 ++++++++++++++------------
- 1 file changed, 22 insertions(+), 20 deletions(-)
-
---- a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
-+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
-@@ -124,14 +124,29 @@ static struct clk_hw *sun8i_tcon_top_reg
- static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
- void *data)
- {
-- struct platform_device *pdev = to_platform_device(dev);
-+ return 0;
-+}
-+
-+static void sun8i_tcon_top_unbind(struct device *dev, struct device *master,
-+ void *data)
-+{
-+}
-+
-+static const struct component_ops sun8i_tcon_top_ops = {
-+ .bind = sun8i_tcon_top_bind,
-+ .unbind = sun8i_tcon_top_unbind,
-+};
-+
-+static int sun8i_tcon_top_probe(struct platform_device *pdev)
-+{
-+ struct device *dev = &pdev->dev;
- struct clk_hw_onecell_data *clk_data;
- struct sun8i_tcon_top *tcon_top;
- const struct sun8i_tcon_top_quirks *quirks;
- void __iomem *regs;
- int ret, i;
-
-- quirks = of_device_get_match_data(&pdev->dev);
-+ quirks = of_device_get_match_data(dev);
-
- tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
- if (!tcon_top)
-@@ -222,7 +237,7 @@ static int sun8i_tcon_top_bind(struct de
-
- dev_set_drvdata(dev, tcon_top);
-
-- return 0;
-+ return component_add(dev, &sun8i_tcon_top_ops);
-
- err_unregister_gates:
- for (i = 0; i < CLK_NUM; i++)
-@@ -235,13 +250,15 @@ err_assert_reset:
- return ret;
- }
-
--static void sun8i_tcon_top_unbind(struct device *dev, struct device *master,
-- void *data)
-+static int sun8i_tcon_top_remove(struct platform_device *pdev)
- {
-+ struct device *dev = &pdev->dev;
- struct sun8i_tcon_top *tcon_top = dev_get_drvdata(dev);
- struct clk_hw_onecell_data *clk_data = tcon_top->clk_data;
- int i;
-
-+ component_del(dev, &sun8i_tcon_top_ops);
-+
- of_clk_del_provider(dev->of_node);
- for (i = 0; i < CLK_NUM; i++)
- if (clk_data->hws[i])
-@@ -249,21 +266,6 @@ static void sun8i_tcon_top_unbind(struct
-
- clk_disable_unprepare(tcon_top->bus);
- reset_control_assert(tcon_top->rst);
--}
--
--static const struct component_ops sun8i_tcon_top_ops = {
-- .bind = sun8i_tcon_top_bind,
-- .unbind = sun8i_tcon_top_unbind,
--};
--
--static int sun8i_tcon_top_probe(struct platform_device *pdev)
--{
-- return component_add(&pdev->dev, &sun8i_tcon_top_ops);
--}
--
--static int sun8i_tcon_top_remove(struct platform_device *pdev)
--{
-- component_del(&pdev->dev, &sun8i_tcon_top_ops);
-
- return 0;
- }
+++ /dev/null
-From 03dbb926f6d65f75af902e421c44aeaaf84be66a Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:46:28 -0500
-Subject: [PATCH 089/117] riscv: dts: allwinner: lichee-rv-86-panel-480p: Add
- panel
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../sun20i-d1-lichee-rv-86-panel-480p.dts | 51 +++++++++++++++++++
- 1 file changed, 51 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-86-panel-480p.dts
-@@ -7,6 +7,40 @@
- model = "Sipeed Lichee RV 86 Panel (480p)";
- compatible = "sipeed,lichee-rv-86-panel-480p", "sipeed,lichee-rv",
- "allwinner,sun20i-d1";
-+
-+ backlight: backlight {
-+ compatible = "pwm-backlight";
-+ power-supply = <®_vcc>;
-+ pwms = <&pwm 7 50000 0>;
-+ };
-+
-+ spi {
-+ compatible = "spi-gpio";
-+ cs-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>; /* PE14 */
-+ mosi-gpios = <&pio 4 12 GPIO_ACTIVE_HIGH>; /* PE12 */
-+ sck-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>; /* PE15 */
-+ num-chipselects = <1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ panel@0 {
-+ compatible = "sitronix,st7701s";
-+ reg = <0>;
-+ backlight = <&backlight>;
-+ reset-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>; /* PG13 */
-+ spi-3wire;
-+
-+ port {
-+ panel_in_tcon_lcd0: endpoint {
-+ remote-endpoint = <&tcon_lcd0_out_panel>;
-+ };
-+ };
-+ };
-+ };
-+};
-+
-+&de {
-+ status = "okay";
- };
-
- &i2c2 {
-@@ -27,3 +61,20 @@
- wakeup-source;
- };
- };
-+
-+&pwm {
-+ pinctrl-0 = <&pwm7_pd22_pin>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+};
-+
-+&tcon_lcd0 {
-+ pinctrl-0 = <&lcd_rgb666_pins>;
-+ pinctrl-names = "default";
-+};
-+
-+&tcon_lcd0_out {
-+ tcon_lcd0_out_panel: endpoint {
-+ remote-endpoint = <&panel_in_tcon_lcd0>;
-+ };
-+};
+++ /dev/null
-From 4c72279c90469971ca5ec627a76e50bf51bf076f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:59:29 -0500
-Subject: [PATCH 090/117] riscv: dts: allwinner: d1: Add DSI pipeline
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 49 ++++++++++++++++++++
- 1 file changed, 49 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -124,6 +124,14 @@
- #interrupt-cells = <3>;
-
- /omit-if-no-ref/
-+ dsi_4lane_pins: dsi-4lane-pins {
-+ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
-+ "PD6", "PD7", "PD8", "PD9";
-+ drive-strength = <30>;
-+ function = "dsi";
-+ };
-+
-+ /omit-if-no-ref/
- i2c0_pb10_pins: i2c0-pb10-pins {
- pins = "PB10", "PB11";
- function = "i2c0";
-@@ -903,6 +911,40 @@
- };
- };
-
-+ dsi: dsi@5450000 {
-+ compatible = "allwinner,sun20i-d1-mipi-dsi",
-+ "allwinner,sun50i-a100-mipi-dsi";
-+ reg = <0x5450000 0x1000>;
-+ interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
-+ <&tcon_top CLK_TCON_TOP_DSI>;
-+ clock-names = "bus", "mod";
-+ resets = <&ccu RST_BUS_MIPI_DSI>;
-+ phys = <&dphy>;
-+ phy-names = "dphy";
-+ status = "disabled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ port {
-+ dsi_in_tcon_lcd0: endpoint {
-+ remote-endpoint = <&tcon_lcd0_out_dsi>;
-+ };
-+ };
-+ };
-+
-+ dphy: phy@5451000 {
-+ compatible = "allwinner,sun20i-d1-mipi-dphy",
-+ "allwinner,sun50i-a100-mipi-dphy";
-+ reg = <0x5451000 0x1000>;
-+ interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
-+ <&ccu CLK_MIPI_DSI>;
-+ clock-names = "bus", "mod";
-+ resets = <&ccu RST_BUS_MIPI_DSI>;
-+ #phy-cells = <0>;
-+ };
-+
- tcon_top: tcon-top@5460000 {
- compatible = "allwinner,sun20i-d1-tcon-top";
- reg = <0x5460000 0x1000>;
-@@ -1022,6 +1064,13 @@
-
- tcon_lcd0_out: port@1 {
- reg = <1>;
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ tcon_lcd0_out_dsi: endpoint@1 {
-+ reg = <1>;
-+ remote-endpoint = <&dsi_in_tcon_lcd0>;
-+ };
- };
- };
- };
+++ /dev/null
-From 7ac17ab7ea644ec27935865d6d0208ecc7fd4ed9 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 11 Aug 2022 22:29:03 -0500
-Subject: [PATCH 091/117] riscv: dts: allwinner: devterm: Add DSI panel and
- backlight
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../allwinner/sun20i-d1-clockworkpi-v3.14.dts | 8 +++++++-
- .../dts/allwinner/sun20i-d1-devterm-v3.14.dts | 20 +++++++++++++++++++
- 2 files changed, 27 insertions(+), 1 deletion(-)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-clockworkpi-v3.14.dts
-@@ -48,6 +48,12 @@
- };
- };
-
-+ backlight: backlight {
-+ compatible = "pwm-backlight";
-+ power-supply = <®_vcc>;
-+ pwms = <&pwm 4 50000 0>; /* PD20/GPIO9 */
-+ };
-+
- reg_vdd_cpu: vdd-cpu {
- compatible = "pwm-regulator";
- pwms = <&pwm 0 50000 0>;
-@@ -252,7 +258,7 @@
- };
-
- &pwm {
-- pinctrl-0 = <&pwm0_pd16_pin>;
-+ pinctrl-0 = <&pwm0_pd16_pin>, <&pwm4_pd20_pin>;
- pinctrl-names = "default";
- status = "okay";
- };
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-devterm-v3.14.dts
-@@ -35,3 +35,23 @@
- };
- };
- };
-+
-+&de {
-+ status = "okay";
-+};
-+
-+&dsi {
-+ pinctrl-0 = <&dsi_4lane_pins>;
-+ pinctrl-names = "default";
-+ status = "okay";
-+
-+ panel@0 {
-+ compatible = "clockwork,cwd686";
-+ reg = <0>;
-+ backlight = <&backlight>;
-+ reset-gpios = <&pio 3 19 GPIO_ACTIVE_LOW>; /* PD19/GPIO8 */
-+ rotation = <90>;
-+ iovcc-supply = <®_dcdc3>;
-+ vci-supply = <®_aldo2>;
-+ };
-+};
+++ /dev/null
-From 822fdc3556b688103cdaf7b4b34e98fbe1676425 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:58:02 -0500
-Subject: [PATCH 092/117] dt-bindings: display: sun4i-tcon: Add external LVDS
- PHY
-
-A100 and D1 use the same "combo" PHY for LVDS0 and DSI.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/display/allwinner,sun4i-a10-tcon.yaml | 7 +++++++
- 1 file changed, 7 insertions(+)
-
---- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-tcon.yaml
-@@ -80,6 +80,13 @@ properties:
- dmas:
- maxItems: 1
-
-+ phys:
-+ maxItems: 1
-+
-+ phy-names:
-+ items:
-+ - const: "lvds0"
-+
- resets:
- anyOf:
- - items:
+++ /dev/null
-From 7d95f6b52ea5f01c9e2414d4984e5a274328c021 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:58:57 -0500
-Subject: [PATCH 093/117] riscv: dts: allwinner: d1: Add LVDS0 PHY
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -1040,6 +1040,8 @@
- resets = <&ccu RST_BUS_TCON_LCD0>,
- <&ccu RST_BUS_LVDS0>;
- reset-names = "lcd", "lvds";
-+ phys = <&dphy>;
-+ phy-names = "lvds0";
- #clock-cells = <0>;
-
- ports {
+++ /dev/null
-From d0f7ed9dc803e09fb6c1e895efbd1182c9212483 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:49:30 -0500
-Subject: [PATCH 094/117] dt-bindings: display: sun6i-dsi: Fix clock
- conditional
-
-The A64 case should have limited maxItems, instead of duplicating the
-minItems value from the main binding. While here, simplify the binding
-by making this an "else" case of the two-clock conditional block.
-
-Fixes: fe5040f2843a ("dt-bindings: sun6i-dsi: Document A64 MIPI-DSI controller")
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml | 10 ++--------
- 1 file changed, 2 insertions(+), 8 deletions(-)
-
---- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
-@@ -78,16 +78,10 @@ allOf:
- required:
- - clock-names
-
-- - if:
-- properties:
-- compatible:
-- contains:
-- const: allwinner,sun50i-a64-mipi-dsi
--
-- then:
-+ else:
- properties:
- clocks:
-- minItems: 1
-+ maxItems: 1
-
- unevaluatedProperties: false
-
+++ /dev/null
-From 30abd0e5f27bc57fba7084ba51aca671316b6d24 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 10:50:21 -0500
-Subject: [PATCH 095/117] dt-bindings: display: sun6i-dsi: Add the A100 variant
-
-The "40nm" MIPI DSI controller found in the A100 and D1 SoCs has the
-same register layout as previous SoC integrations. However, its module
-clock now comes from the TCON, which means it no longer runs at a fixed
-rate, so this needs to be distinguished in the driver.
-
-The controller also now uses pins on Port D instead of dedicated pins,
-so it drops the separate power domain.
-
-Commit-notes:
-Removal of the vcc-dsi-supply is maybe a bit questionable. Since there
-is no "VCC-DSI" pin anymore, it's not obvious which pin actually does
-power the DSI controller/PHY. Possibly power comes from VCC-PD or VCC-IO
-or VCC-LVDS. So far, all boards have all of these as always-on supplies,
-so it is hard to test.
-END
-
-Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../display/allwinner,sun6i-a31-mipi-dsi.yaml | 28 +++++++++++++++----
- 1 file changed, 23 insertions(+), 5 deletions(-)
-
---- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
-+++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
-@@ -12,9 +12,14 @@ maintainers:
-
- properties:
- compatible:
-- enum:
-- - allwinner,sun6i-a31-mipi-dsi
-- - allwinner,sun50i-a64-mipi-dsi
-+ oneOf:
-+ - enum:
-+ - allwinner,sun6i-a31-mipi-dsi
-+ - allwinner,sun50i-a64-mipi-dsi
-+ - allwinner,sun50i-a100-mipi-dsi
-+ - items:
-+ - const: allwinner,sun20i-d1-mipi-dsi
-+ - const: allwinner,sun50i-a100-mipi-dsi
-
- reg:
- maxItems: 1
-@@ -59,7 +64,6 @@ required:
- - phys
- - phy-names
- - resets
-- - vcc-dsi-supply
- - port
-
- allOf:
-@@ -68,7 +72,9 @@ allOf:
- properties:
- compatible:
- contains:
-- const: allwinner,sun6i-a31-mipi-dsi
-+ enum:
-+ - allwinner,sun6i-a31-mipi-dsi
-+ - allwinner,sun50i-a100-mipi-dsi
-
- then:
- properties:
-@@ -83,6 +89,18 @@ allOf:
- clocks:
- maxItems: 1
-
-+ - if:
-+ properties:
-+ compatible:
-+ contains:
-+ enum:
-+ - allwinner,sun6i-a31-mipi-dsi
-+ - allwinner,sun50i-a64-mipi-dsi
-+
-+ then:
-+ required:
-+ - vcc-dsi-supply
-+
- unevaluatedProperties: false
-
- examples:
+++ /dev/null
-From 28e64e830ef487b400b3b943fa3bda83dfb2a937 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 9 Aug 2022 22:03:42 -0500
-Subject: [PATCH 096/117] drm/sun4i: dsi: Add a variant structure
-
-Replace the ad-hoc calls to of_device_is_compatible() with a structure
-describing the differences between variants. This is in preparation for
-adding more variants to the driver.
-
-Series-changes: 2
- - Add the variant check to the probe error path
-
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 53 +++++++++++++++++---------
- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h | 7 ++++
- 2 files changed, 42 insertions(+), 18 deletions(-)
-
---- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-@@ -1101,12 +1101,16 @@ static const struct component_ops sun6i_
-
- static int sun6i_dsi_probe(struct platform_device *pdev)
- {
-+ const struct sun6i_dsi_variant *variant;
- struct device *dev = &pdev->dev;
-- const char *bus_clk_name = NULL;
- struct sun6i_dsi *dsi;
- void __iomem *base;
- int ret;
-
-+ variant = device_get_match_data(dev);
-+ if (!variant)
-+ return -EINVAL;
-+
- dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
- if (!dsi)
- return -ENOMEM;
-@@ -1114,10 +1118,7 @@ static int sun6i_dsi_probe(struct platfo
- dsi->dev = dev;
- dsi->host.ops = &sun6i_dsi_host_ops;
- dsi->host.dev = dev;
--
-- if (of_device_is_compatible(dev->of_node,
-- "allwinner,sun6i-a31-mipi-dsi"))
-- bus_clk_name = "bus";
-+ dsi->variant = variant;
-
- base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(base)) {
-@@ -1142,7 +1143,7 @@ static int sun6i_dsi_probe(struct platfo
- return PTR_ERR(dsi->regs);
- }
-
-- dsi->bus_clk = devm_clk_get(dev, bus_clk_name);
-+ dsi->bus_clk = devm_clk_get(dev, variant->has_mod_clk ? "bus" : NULL);
- if (IS_ERR(dsi->bus_clk))
- return dev_err_probe(dev, PTR_ERR(dsi->bus_clk),
- "Couldn't get the DSI bus clock\n");
-@@ -1151,21 +1152,21 @@ static int sun6i_dsi_probe(struct platfo
- if (ret)
- return ret;
-
-- if (of_device_is_compatible(dev->of_node,
-- "allwinner,sun6i-a31-mipi-dsi")) {
-+ if (variant->has_mod_clk) {
- dsi->mod_clk = devm_clk_get(dev, "mod");
- if (IS_ERR(dsi->mod_clk)) {
- dev_err(dev, "Couldn't get the DSI mod clock\n");
- ret = PTR_ERR(dsi->mod_clk);
- goto err_attach_clk;
- }
-- }
-
-- /*
-- * In order to operate properly, that clock seems to be always
-- * set to 297MHz.
-- */
-- clk_set_rate_exclusive(dsi->mod_clk, 297000000);
-+ /*
-+ * In order to operate properly, the module clock on the
-+ * A31 variant always seems to be set to 297MHz.
-+ */
-+ if (variant->set_mod_clk)
-+ clk_set_rate_exclusive(dsi->mod_clk, 297000000);
-+ }
-
- dsi->dphy = devm_phy_get(dev, "dphy");
- if (IS_ERR(dsi->dphy)) {
-@@ -1191,7 +1192,8 @@ static int sun6i_dsi_probe(struct platfo
- err_remove_dsi_host:
- mipi_dsi_host_unregister(&dsi->host);
- err_unprotect_clk:
-- clk_rate_exclusive_put(dsi->mod_clk);
-+ if (dsi->variant->has_mod_clk && dsi->variant->set_mod_clk)
-+ clk_rate_exclusive_put(dsi->mod_clk);
- err_attach_clk:
- regmap_mmio_detach_clk(dsi->regs);
-
-@@ -1205,16 +1207,31 @@ static int sun6i_dsi_remove(struct platf
-
- component_del(&pdev->dev, &sun6i_dsi_ops);
- mipi_dsi_host_unregister(&dsi->host);
-- clk_rate_exclusive_put(dsi->mod_clk);
-+ if (dsi->variant->has_mod_clk && dsi->variant->set_mod_clk)
-+ clk_rate_exclusive_put(dsi->mod_clk);
-
- regmap_mmio_detach_clk(dsi->regs);
-
- return 0;
- }
-
-+static const struct sun6i_dsi_variant sun6i_a31_mipi_dsi_variant = {
-+ .has_mod_clk = true,
-+ .set_mod_clk = true,
-+};
-+
-+static const struct sun6i_dsi_variant sun50i_a64_mipi_dsi_variant = {
-+};
-+
- static const struct of_device_id sun6i_dsi_of_table[] = {
-- { .compatible = "allwinner,sun6i-a31-mipi-dsi" },
-- { .compatible = "allwinner,sun50i-a64-mipi-dsi" },
-+ {
-+ .compatible = "allwinner,sun6i-a31-mipi-dsi",
-+ .data = &sun6i_a31_mipi_dsi_variant,
-+ },
-+ {
-+ .compatible = "allwinner,sun50i-a64-mipi-dsi",
-+ .data = &sun50i_a64_mipi_dsi_variant,
-+ },
- { }
- };
- MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
---- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
-+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
-@@ -15,6 +15,11 @@
-
- #define SUN6I_DSI_TCON_DIV 4
-
-+struct sun6i_dsi_variant {
-+ bool has_mod_clk;
-+ bool set_mod_clk;
-+};
-+
- struct sun6i_dsi {
- struct drm_connector connector;
- struct drm_encoder encoder;
-@@ -31,6 +36,8 @@ struct sun6i_dsi {
- struct mipi_dsi_device *device;
- struct drm_device *drm;
- struct drm_panel *panel;
-+
-+ const struct sun6i_dsi_variant *variant;
- };
-
- static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
+++ /dev/null
-From 713029c6a33df9218d11593bc5be79420715633f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 11:06:22 -0500
-Subject: [PATCH 097/117] drm/sun4i: dsi: Add the A100 variant
-
-The A100 variant of the MIPI DSI controller now gets its module clock
-from the TCON via the TCON TOP, so the clock rate cannot be set to a
-fixed value. Otherwise, it appears to be the same as the A31 variant.
-
-Cover-letter:
-drm/sun4i: dsi: Support the A100/D1 controller variant
-This series adds support for the digital part of the DSI controller
-found in the A100 and D1 SoCs (plus T7, which is not supported by
-mainline Linux). There are two changes to the hardware integration:
- 1) the module clock routes through the TCON TOP, and
- 2) the separate I/O domain is removed.
-
-The actual register interface appears to be the same as before. The
-register definitions in the D1 BSP exactly match the A64 BSP.
-
-The BSP describes this as the "40nm" DSI controller variant. There is
-also a "28nm" variant with a different register interface; that one is
-found in a different subset of SoCs (V5 and A50).
-
-A100/D1 also come with an updated DPHY, described by the BSP as a
-"combo" PHY, which is now also used for LVDS channel 0. (LVDS and DSI
-share the same pins on Port D.) Since that is a different subsystem,
-I am sending that as a separate series.
-END
-
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-Series-to: Maxime Ripard <mripard@kernel.org>
-
-Series-version: 2
-
-Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-+++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
-@@ -1223,6 +1223,10 @@ static const struct sun6i_dsi_variant su
- static const struct sun6i_dsi_variant sun50i_a64_mipi_dsi_variant = {
- };
-
-+static const struct sun6i_dsi_variant sun50i_a100_mipi_dsi_variant = {
-+ .has_mod_clk = true,
-+};
-+
- static const struct of_device_id sun6i_dsi_of_table[] = {
- {
- .compatible = "allwinner,sun6i-a31-mipi-dsi",
-@@ -1232,6 +1236,10 @@ static const struct of_device_id sun6i_d
- .compatible = "allwinner,sun50i-a64-mipi-dsi",
- .data = &sun50i_a64_mipi_dsi_variant,
- },
-+ {
-+ .compatible = "allwinner,sun50i-a100-mipi-dsi",
-+ .data = &sun50i_a100_mipi_dsi_variant,
-+ },
- { }
- };
- MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table);
+++ /dev/null
-From b6af4b7f6f75904509747c08e87d91c1bb607bd4 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Thu, 22 Sep 2022 00:39:36 -0500
-Subject: [PATCH 098/117] riscv: Move cast inside kernel_mapping_[pv]a_to_[vp]a
-
-Before commit 44c922572952 ("RISC-V: enable XIP"), these macros cast
-their argument to unsigned long. That commit moved the cast after an
-assignment to an unsigned long variable, rendering it ineffectual.
-Move the cast back, so we can remove the cast at each call site.
-
-Series-to: Palmer Dabbelt <palmer@dabbelt.com>
-Series-to: linux-riscv@lists.infradead.org
-
-Series-version: 2
-
-Reviewed-by: Alexandre Ghiti <alexandre.ghiti@canonical.com>
-Reviewed-by: Heiko Stuebner <heiko@sntech.de>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/include/asm/page.h | 18 +++++++++---------
- arch/riscv/mm/init.c | 16 ++++++++--------
- 2 files changed, 17 insertions(+), 17 deletions(-)
-
---- a/arch/riscv/include/asm/page.h
-+++ b/arch/riscv/include/asm/page.h
-@@ -123,20 +123,20 @@ extern phys_addr_t phys_ram_base;
- ((x) >= PAGE_OFFSET && (!IS_ENABLED(CONFIG_64BIT) || (x) < PAGE_OFFSET + KERN_VIRT_SIZE))
-
- #define linear_mapping_pa_to_va(x) ((void *)((unsigned long)(x) + kernel_map.va_pa_offset))
--#define kernel_mapping_pa_to_va(y) ({ \
-- unsigned long _y = y; \
-- (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ? \
-- (void *)((unsigned long)(_y) + kernel_map.va_kernel_xip_pa_offset) : \
-- (void *)((unsigned long)(_y) + kernel_map.va_kernel_pa_offset + XIP_OFFSET); \
-+#define kernel_mapping_pa_to_va(y) ({ \
-+ unsigned long _y = (unsigned long)(y); \
-+ (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < phys_ram_base) ? \
-+ (void *)(_y + kernel_map.va_kernel_xip_pa_offset) : \
-+ (void *)(_y + kernel_map.va_kernel_pa_offset + XIP_OFFSET); \
- })
- #define __pa_to_va_nodebug(x) linear_mapping_pa_to_va(x)
-
- #define linear_mapping_va_to_pa(x) ((unsigned long)(x) - kernel_map.va_pa_offset)
- #define kernel_mapping_va_to_pa(y) ({ \
-- unsigned long _y = y; \
-- (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET) ? \
-- ((unsigned long)(_y) - kernel_map.va_kernel_xip_pa_offset) : \
-- ((unsigned long)(_y) - kernel_map.va_kernel_pa_offset - XIP_OFFSET); \
-+ unsigned long _y = (unsigned long)(y); \
-+ (IS_ENABLED(CONFIG_XIP_KERNEL) && _y < kernel_map.virt_addr + XIP_OFFSET) ? \
-+ (_y - kernel_map.va_kernel_xip_pa_offset) : \
-+ (_y - kernel_map.va_kernel_pa_offset - XIP_OFFSET); \
- })
-
- #define __va_to_pa_nodebug(x) ({ \
---- a/arch/riscv/mm/init.c
-+++ b/arch/riscv/mm/init.c
-@@ -903,15 +903,15 @@ static void __init pt_ops_set_early(void
- */
- static void __init pt_ops_set_fixmap(void)
- {
-- pt_ops.alloc_pte = kernel_mapping_pa_to_va((uintptr_t)alloc_pte_fixmap);
-- pt_ops.get_pte_virt = kernel_mapping_pa_to_va((uintptr_t)get_pte_virt_fixmap);
-+ pt_ops.alloc_pte = kernel_mapping_pa_to_va(alloc_pte_fixmap);
-+ pt_ops.get_pte_virt = kernel_mapping_pa_to_va(get_pte_virt_fixmap);
- #ifndef __PAGETABLE_PMD_FOLDED
-- pt_ops.alloc_pmd = kernel_mapping_pa_to_va((uintptr_t)alloc_pmd_fixmap);
-- pt_ops.get_pmd_virt = kernel_mapping_pa_to_va((uintptr_t)get_pmd_virt_fixmap);
-- pt_ops.alloc_pud = kernel_mapping_pa_to_va((uintptr_t)alloc_pud_fixmap);
-- pt_ops.get_pud_virt = kernel_mapping_pa_to_va((uintptr_t)get_pud_virt_fixmap);
-- pt_ops.alloc_p4d = kernel_mapping_pa_to_va((uintptr_t)alloc_p4d_fixmap);
-- pt_ops.get_p4d_virt = kernel_mapping_pa_to_va((uintptr_t)get_p4d_virt_fixmap);
-+ pt_ops.alloc_pmd = kernel_mapping_pa_to_va(alloc_pmd_fixmap);
-+ pt_ops.get_pmd_virt = kernel_mapping_pa_to_va(get_pmd_virt_fixmap);
-+ pt_ops.alloc_pud = kernel_mapping_pa_to_va(alloc_pud_fixmap);
-+ pt_ops.get_pud_virt = kernel_mapping_pa_to_va(get_pud_virt_fixmap);
-+ pt_ops.alloc_p4d = kernel_mapping_pa_to_va(alloc_p4d_fixmap);
-+ pt_ops.get_p4d_virt = kernel_mapping_pa_to_va(get_p4d_virt_fixmap);
- #endif
- }
-
+++ /dev/null
-From 20a204b31291befcd583f97dafc0a827f3bc7f00 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 12 Aug 2022 01:37:16 -0500
-Subject: [PATCH 099/117] dt-bindings: sun6i-a31-mipi-dphy: Add the interrupts
- property
-
-The sun6i DPHY can generate several interrupts, mostly for reporting
-error conditions, but also for detecting BTA and UPLS sequences.
-Document this capability in order to accurately describe the hardware.
-
-The DPHY has no interrupt number provided in the vendor documentation
-because its interrupt line is shared with the DSI controller.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
-+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
-@@ -24,6 +24,9 @@ properties:
- reg:
- maxItems: 1
-
-+ interrupts:
-+ maxItems: 1
-+
- clocks:
- items:
- - description: Bus Clock
-@@ -53,6 +56,7 @@ required:
- - "#phy-cells"
- - compatible
- - reg
-+ - interrupts
- - clocks
- - clock-names
- - resets
+++ /dev/null
-From 7d47c62b378a4dbbf3e46a80c7b03966f8964da1 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 12 Aug 2022 02:24:14 -0500
-Subject: [PATCH 100/117] ARM: dts: sun8i: a33: Add DPHY interrupt
-
-The DPHY has an interrupt line which is shared with the DSI controller.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/arm/boot/dts/sun8i-a33.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm/boot/dts/sun8i-a33.dtsi
-+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
-@@ -278,6 +278,7 @@
- dphy: d-phy@1ca1000 {
- compatible = "allwinner,sun6i-a31-mipi-dphy";
- reg = <0x01ca1000 0x1000>;
-+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_MIPI_DSI>,
- <&ccu CLK_DSI_DPHY>;
- clock-names = "bus", "mod";
+++ /dev/null
-From 11d78fce09e80ec246016c19ecc28a724e1e5530 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Fri, 12 Aug 2022 02:25:55 -0500
-Subject: [PATCH 101/117] arm64: dts: allwinner: a64: Add DPHY interrupt
-
-The DPHY has an interrupt line which is shared with the DSI controller.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
-@@ -1199,6 +1199,7 @@
- compatible = "allwinner,sun50i-a64-mipi-dphy",
- "allwinner,sun6i-a31-mipi-dphy";
- reg = <0x01ca1000 0x1000>;
-+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_MIPI_DSI>,
- <&ccu CLK_DSI_DPHY>;
- clock-names = "bus", "mod";
+++ /dev/null
-From c7fa1be12bf0ef02f5557dd1d1100d25af4e34f5 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 11:00:12 -0500
-Subject: [PATCH 102/117] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY
- variant
-
-A100 features an updated DPHY, which moves PLL control inside the DPHY
-register space. (Previously PLL-MIPI was controlled from the CCU. This
-does not affect the "clocks" property because the link between PLL-MIPI
-and the DPHY was never represented in the devicetree.) It also requires
-a modified analog power-on sequence. Finally, the new DPHY adds support
-for operating as an LVDS PHY. D1 uses this same variant.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
-+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
-@@ -17,9 +17,13 @@ properties:
- compatible:
- oneOf:
- - const: allwinner,sun6i-a31-mipi-dphy
-+ - const: allwinner,sun50i-a100-mipi-dphy
- - items:
- - const: allwinner,sun50i-a64-mipi-dphy
- - const: allwinner,sun6i-a31-mipi-dphy
-+ - items:
-+ - const: allwinner,sun20i-d1-mipi-dphy
-+ - const: allwinner,sun50i-a100-mipi-dphy
-
- reg:
- maxItems: 1
+++ /dev/null
-From 27c0c2cbe7b30b907b031016d2cd15fe9505cb1b Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 12:11:53 -0500
-Subject: [PATCH 103/117] phy: allwinner: phy-sun6i-mipi-dphy: Make RX support
- optional
-
-While all variants of the DPHY likely support RX mode, the new variant
-in the A100 is not used in this direction by the BSP, and it has some
-analog register changes, so its RX power-on sequence is unknown. To be
-safe, limit RX support to variants where the power-on sequence is known.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 25 +++++++++++++++++++--
- 1 file changed, 23 insertions(+), 2 deletions(-)
-
---- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-@@ -114,6 +114,10 @@ enum sun6i_dphy_direction {
- SUN6I_DPHY_DIRECTION_RX,
- };
-
-+struct sun6i_dphy_variant {
-+ bool supports_rx;
-+};
-+
- struct sun6i_dphy {
- struct clk *bus_clk;
- struct clk *mod_clk;
-@@ -123,6 +127,7 @@ struct sun6i_dphy {
- struct phy *phy;
- struct phy_configure_opts_mipi_dphy config;
-
-+ const struct sun6i_dphy_variant *variant;
- enum sun6i_dphy_direction direction;
- };
-
-@@ -409,6 +414,10 @@ static int sun6i_dphy_probe(struct platf
- if (!dphy)
- return -ENOMEM;
-
-+ dphy->variant = device_get_match_data(&pdev->dev);
-+ if (!dphy->variant)
-+ return -EINVAL;
-+
- regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(regs)) {
- dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
-@@ -445,8 +454,13 @@ static int sun6i_dphy_probe(struct platf
- ret = of_property_read_string(pdev->dev.of_node, "allwinner,direction",
- &direction);
-
-- if (!ret && !strncmp(direction, "rx", 2))
-+ if (!ret && !strncmp(direction, "rx", 2)) {
-+ if (!dphy->variant->supports_rx) {
-+ dev_err(&pdev->dev, "RX not supported on this variant\n");
-+ return -EOPNOTSUPP;
-+ }
- dphy->direction = SUN6I_DPHY_DIRECTION_RX;
-+ }
-
- phy_set_drvdata(dphy->phy, dphy);
- phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
-@@ -454,8 +468,15 @@ static int sun6i_dphy_probe(struct platf
- return PTR_ERR_OR_ZERO(phy_provider);
- }
-
-+static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
-+ .supports_rx = true,
-+};
-+
- static const struct of_device_id sun6i_dphy_of_table[] = {
-- { .compatible = "allwinner,sun6i-a31-mipi-dphy" },
-+ {
-+ .compatible = "allwinner,sun6i-a31-mipi-dphy",
-+ .data = &sun6i_a31_mipi_dphy_variant,
-+ },
- { }
- };
- MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
+++ /dev/null
-From 16993169c82c2c57e1df1e7f4598a7c2aa565fe2 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 11:12:02 -0500
-Subject: [PATCH 104/117] phy: allwinner: phy-sun6i-mipi-dphy: Set enable bit
- last
-
-The A100 variant of the DPHY requires configuring the analog registers
-before setting the global enable bit. Since this order also works on the
-other variants, always use it, to minimize the differences between them.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-@@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct
- SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
- SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
-
-- regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
-- SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
-- SUN6I_DPHY_GCTL_EN);
--
- regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
- SUN6I_DPHY_ANA0_REG_PWS |
- SUN6I_DPHY_ANA0_REG_DMPC |
-@@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct
- SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
- SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
-
-+ regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
-+ SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) |
-+ SUN6I_DPHY_GCTL_EN);
-+
- return 0;
- }
-
+++ /dev/null
-From b953c09bde508c2edd8acd95abba8542b6cebff6 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 11:44:09 -0500
-Subject: [PATCH 105/117] phy: allwinner: phy-sun6i-mipi-dphy: Add a variant
- power-on hook
-
-The A100 variant uses the same values for the timing registers, and it
-uses the same final power-on sequence, but it needs a different analog
-register configuration in the middle. Support this by moving the
-variant-specific parts to a hook provided by the variant.
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 59 ++++++++++++---------
- 1 file changed, 35 insertions(+), 24 deletions(-)
-
---- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-@@ -114,7 +114,10 @@ enum sun6i_dphy_direction {
- SUN6I_DPHY_DIRECTION_RX,
- };
-
-+struct sun6i_dphy;
-+
- struct sun6i_dphy_variant {
-+ void (*tx_power_on)(struct sun6i_dphy *dphy);
- bool supports_rx;
- };
-
-@@ -156,33 +159,10 @@ static int sun6i_dphy_configure(struct p
- return 0;
- }
-
--static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
-+static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
- {
- u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
-
-- regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
-- SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
--
-- regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
-- SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
-- SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
-- SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
--
-- regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
-- SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
-- SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
-- SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
-- SUN6I_DPHY_TX_TIME1_CLK_POST(10));
--
-- regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
-- SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
--
-- regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
--
-- regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
-- SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
-- SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
--
- regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
- SUN6I_DPHY_ANA0_REG_PWS |
- SUN6I_DPHY_ANA0_REG_DMPC |
-@@ -214,6 +194,36 @@ static int sun6i_dphy_tx_power_on(struct
- SUN6I_DPHY_ANA3_EN_LDOC |
- SUN6I_DPHY_ANA3_EN_LDOD);
- udelay(1);
-+}
-+
-+static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
-+{
-+ u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
-+
-+ regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
-+ SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
-+
-+ regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
-+ SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
-+ SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
-+ SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
-+
-+ regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
-+ SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
-+ SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
-+ SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
-+ SUN6I_DPHY_TX_TIME1_CLK_POST(10));
-+
-+ regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
-+ SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
-+
-+ regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
-+
-+ regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
-+ SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
-+ SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
-+
-+ dphy->variant->tx_power_on(dphy);
-
- regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
- SUN6I_DPHY_ANA3_EN_VTTC |
-@@ -469,6 +479,7 @@ static int sun6i_dphy_probe(struct platf
- }
-
- static const struct sun6i_dphy_variant sun6i_a31_mipi_dphy_variant = {
-+ .tx_power_on = sun6i_a31_mipi_dphy_tx_power_on,
- .supports_rx = true,
- };
-
+++ /dev/null
-From 474b608dee5e6285dd1981b00ab568a2f7f15fd0 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 10 Aug 2022 23:02:06 -0500
-Subject: [PATCH 106/117] phy: allwinner: phy-sun6i-mipi-dphy: Add the A100
- DPHY variant
-
-A100 features an updated DPHY, which moves PLL control inside the DPHY
-register space (previously the PLL was controlled from the CCU). It also
-requires a modified analog power-on sequence. This "combo PHY" can also
-be used as an LVDS PHY, but that is not yet supported by the driver.
-
-Cover-letter:
-phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY
-This series adds support for the updated DPHY found in a couple of
-recent Allwinner SoCs. The first three patches fix an omission in the
-existing binding. The remaining patches add the new hardware variant.
-END
-
-Series-to: Kishon Vijay Abraham I <kishon@ti.com>
-Series-to: Vinod Koul <vkoul@kernel.org>
-Series-to: Chen-Yu Tsai <wens@csie.org>
-Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
-Series-to: Maxime Ripard <mripard@kernel.org>
-Series-cc: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 143 +++++++++++++++++++-
- 1 file changed, 142 insertions(+), 1 deletion(-)
-
---- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-@@ -70,11 +70,19 @@
-
- #define SUN6I_DPHY_ANA0_REG 0x4c
- #define SUN6I_DPHY_ANA0_REG_PWS BIT(31)
-+#define SUN6I_DPHY_ANA0_REG_PWEND BIT(30)
-+#define SUN6I_DPHY_ANA0_REG_PWENC BIT(29)
- #define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
- #define SUN6I_DPHY_ANA0_REG_DMPD(n) (((n) & 0xf) << 24)
-+#define SUN6I_DPHY_ANA0_REG_SRXDT(n) (((n) & 0xf) << 20)
-+#define SUN6I_DPHY_ANA0_REG_SRXCK(n) (((n) & 0xf) << 16)
-+#define SUN6I_DPHY_ANA0_REG_SDIV2 BIT(15)
- #define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
- #define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
-+#define SUN6I_DPHY_ANA0_REG_PLR(n) (((n) & 0xf) << 4)
- #define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
-+#define SUN6I_DPHY_ANA0_REG_RSD BIT(1)
-+#define SUN6I_DPHY_ANA0_REG_SELSCK BIT(0)
-
- #define SUN6I_DPHY_ANA1_REG 0x50
- #define SUN6I_DPHY_ANA1_REG_VTTMODE BIT(31)
-@@ -97,8 +105,13 @@
- #define SUN6I_DPHY_ANA3_EN_LDOR BIT(18)
-
- #define SUN6I_DPHY_ANA4_REG 0x5c
-+#define SUN6I_DPHY_ANA4_REG_EN_MIPI BIT(31)
-+#define SUN6I_DPHY_ANA4_REG_EN_COMTEST BIT(30)
-+#define SUN6I_DPHY_ANA4_REG_COMTEST(n) (((n) & 3) << 28)
-+#define SUN6I_DPHY_ANA4_REG_IB(n) (((n) & 3) << 25)
- #define SUN6I_DPHY_ANA4_REG_DMPLVC BIT(24)
- #define SUN6I_DPHY_ANA4_REG_DMPLVD(n) (((n) & 0xf) << 20)
-+#define SUN6I_DPHY_ANA4_REG_VTT_SET(n) (((n) & 0x7) << 17)
- #define SUN6I_DPHY_ANA4_REG_CKDV(n) (((n) & 0x1f) << 12)
- #define SUN6I_DPHY_ANA4_REG_TMSC(n) (((n) & 3) << 10)
- #define SUN6I_DPHY_ANA4_REG_TMSD(n) (((n) & 3) << 8)
-@@ -109,6 +122,56 @@
-
- #define SUN6I_DPHY_DBG5_REG 0xf4
-
-+#define SUN50I_DPHY_TX_SLEW_REG0 0xf8
-+#define SUN50I_DPHY_TX_SLEW_REG1 0xfc
-+#define SUN50I_DPHY_TX_SLEW_REG2 0x100
-+
-+#define SUN50I_DPHY_PLL_REG0 0x104
-+#define SUN50I_DPHY_PLL_REG0_CP36_EN BIT(23)
-+#define SUN50I_DPHY_PLL_REG0_LDO_EN BIT(22)
-+#define SUN50I_DPHY_PLL_REG0_EN_LVS BIT(21)
-+#define SUN50I_DPHY_PLL_REG0_PLL_EN BIT(20)
-+#define SUN50I_DPHY_PLL_REG0_P(n) (((n) & 0xf) << 16)
-+#define SUN50I_DPHY_PLL_REG0_N(n) (((n) & 0xff) << 8)
-+#define SUN50I_DPHY_PLL_REG0_NDET BIT(7)
-+#define SUN50I_DPHY_PLL_REG0_TDIV BIT(6)
-+#define SUN50I_DPHY_PLL_REG0_M0(n) (((n) & 3) << 4)
-+#define SUN50I_DPHY_PLL_REG0_M1(n) ((n) & 0xf)
-+
-+#define SUN50I_DPHY_PLL_REG1 0x108
-+#define SUN50I_DPHY_PLL_REG1_UNLOCK_MDSEL(n) (((n) & 3) << 14)
-+#define SUN50I_DPHY_PLL_REG1_LOCKMDSEL BIT(13)
-+#define SUN50I_DPHY_PLL_REG1_LOCKDET_EN BIT(12)
-+#define SUN50I_DPHY_PLL_REG1_VSETA(n) (((n) & 0x7) << 9)
-+#define SUN50I_DPHY_PLL_REG1_VSETD(n) (((n) & 0x7) << 6)
-+#define SUN50I_DPHY_PLL_REG1_LPF_SW BIT(5)
-+#define SUN50I_DPHY_PLL_REG1_ICP_SEL(n) (((n) & 3) << 3)
-+#define SUN50I_DPHY_PLL_REG1_ATEST_SEL(n) (((n) & 3) << 1)
-+#define SUN50I_DPHY_PLL_REG1_TEST_EN BIT(0)
-+
-+#define SUN50I_DPHY_PLL_REG2 0x10c
-+#define SUN50I_DPHY_PLL_REG2_SDM_EN BIT(31)
-+#define SUN50I_DPHY_PLL_REG2_FF_EN BIT(30)
-+#define SUN50I_DPHY_PLL_REG2_SS_EN BIT(29)
-+#define SUN50I_DPHY_PLL_REG2_SS_FRAC(n) (((n) & 0x1ff) << 20)
-+#define SUN50I_DPHY_PLL_REG2_SS_INT(n) (((n) & 0xff) << 12)
-+#define SUN50I_DPHY_PLL_REG2_FRAC(n) ((n) & 0xfff)
-+
-+#define SUN50I_COMBO_PHY_REG0 0x110
-+#define SUN50I_COMBO_PHY_REG0_EN_TEST_COMBOLDO BIT(5)
-+#define SUN50I_COMBO_PHY_REG0_EN_TEST_0P8 BIT(4)
-+#define SUN50I_COMBO_PHY_REG0_EN_MIPI BIT(3)
-+#define SUN50I_COMBO_PHY_REG0_EN_LVDS BIT(2)
-+#define SUN50I_COMBO_PHY_REG0_EN_COMBOLDO BIT(1)
-+#define SUN50I_COMBO_PHY_REG0_EN_CP BIT(0)
-+
-+#define SUN50I_COMBO_PHY_REG1 0x114
-+#define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n) (((n) & 0x7) << 4)
-+#define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n) ((n) & 0x7)
-+
-+#define SUN50I_COMBO_PHY_REG2 0x118
-+#define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n) ((n) & 0xff)
-+
- enum sun6i_dphy_direction {
- SUN6I_DPHY_DIRECTION_TX,
- SUN6I_DPHY_DIRECTION_RX,
-@@ -196,6 +259,76 @@ static void sun6i_a31_mipi_dphy_tx_power
- udelay(1);
- }
-
-+static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
-+{
-+ unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
-+ unsigned int div, n;
-+
-+ regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
-+ SUN6I_DPHY_ANA4_REG_IB(2) |
-+ SUN6I_DPHY_ANA4_REG_DMPLVD(4) |
-+ SUN6I_DPHY_ANA4_REG_VTT_SET(3) |
-+ SUN6I_DPHY_ANA4_REG_CKDV(3) |
-+ SUN6I_DPHY_ANA4_REG_TMSD(1) |
-+ SUN6I_DPHY_ANA4_REG_TMSC(1) |
-+ SUN6I_DPHY_ANA4_REG_TXPUSD(2) |
-+ SUN6I_DPHY_ANA4_REG_TXPUSC(3) |
-+ SUN6I_DPHY_ANA4_REG_TXDNSD(2) |
-+ SUN6I_DPHY_ANA4_REG_TXDNSC(3));
-+
-+ regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
-+ SUN6I_DPHY_ANA2_EN_CK_CPU,
-+ SUN6I_DPHY_ANA2_EN_CK_CPU);
-+
-+ regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
-+ SUN6I_DPHY_ANA2_REG_ENIB,
-+ SUN6I_DPHY_ANA2_REG_ENIB);
-+
-+ regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
-+ SUN6I_DPHY_ANA3_EN_LDOR |
-+ SUN6I_DPHY_ANA3_EN_LDOC |
-+ SUN6I_DPHY_ANA3_EN_LDOD);
-+
-+ regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
-+ SUN6I_DPHY_ANA0_REG_PLR(4) |
-+ SUN6I_DPHY_ANA0_REG_SFB(1));
-+
-+ regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0,
-+ SUN50I_COMBO_PHY_REG0_EN_CP);
-+
-+ /* Choose a divider to limit the VCO frequency to around 2 GHz. */
-+ div = 16 >> order_base_2(DIV_ROUND_UP(mipi_symbol_rate, 264000000));
-+ n = mipi_symbol_rate * div / 24000000;
-+
-+ regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0,
-+ SUN50I_DPHY_PLL_REG0_CP36_EN |
-+ SUN50I_DPHY_PLL_REG0_LDO_EN |
-+ SUN50I_DPHY_PLL_REG0_EN_LVS |
-+ SUN50I_DPHY_PLL_REG0_PLL_EN |
-+ SUN50I_DPHY_PLL_REG0_NDET |
-+ SUN50I_DPHY_PLL_REG0_P((div - 1) % 8) |
-+ SUN50I_DPHY_PLL_REG0_N(n) |
-+ SUN50I_DPHY_PLL_REG0_M0((div - 1) / 8) |
-+ SUN50I_DPHY_PLL_REG0_M1(2));
-+
-+ /* Disable sigma-delta modulation. */
-+ regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
-+
-+ regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
-+ SUN6I_DPHY_ANA4_REG_EN_MIPI,
-+ SUN6I_DPHY_ANA4_REG_EN_MIPI);
-+
-+ regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
-+ SUN50I_COMBO_PHY_REG0_EN_MIPI |
-+ SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
-+ SUN50I_COMBO_PHY_REG0_EN_MIPI |
-+ SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
-+
-+ regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG2,
-+ SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(20));
-+ udelay(1);
-+}
-+
- static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
- {
- u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
-@@ -408,7 +541,7 @@ static const struct regmap_config sun6i_
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
-- .max_register = SUN6I_DPHY_DBG5_REG,
-+ .max_register = SUN50I_COMBO_PHY_REG2,
- .name = "mipi-dphy",
- };
-
-@@ -483,11 +616,19 @@ static const struct sun6i_dphy_variant s
- .supports_rx = true,
- };
-
-+static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant = {
-+ .tx_power_on = sun50i_a100_mipi_dphy_tx_power_on,
-+};
-+
- static const struct of_device_id sun6i_dphy_of_table[] = {
- {
- .compatible = "allwinner,sun6i-a31-mipi-dphy",
- .data = &sun6i_a31_mipi_dphy_variant,
- },
-+ {
-+ .compatible = "allwinner,sun50i-a100-mipi-dphy",
-+ .data = &sun50i_a100_mipi_dphy_variant,
-+ },
- { }
- };
- MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
+++ /dev/null
-From 5bf84a1a0a282a18bf9dd2d752537525aefc2e05 Mon Sep 17 00:00:00 2001
-From: Max Fierke <max@maxfierke.com>
-Date: Wed, 1 Jun 2022 00:17:48 -0500
-Subject: [PATCH 107/117] drm: panel: Add driver for Clockwork cwd686 panel
-
-The Clockwork DevTerm (all models) uses a 6.86" IPS display
-of unknown provenance, which uses the Chipone ICNL9707 IC driver.
-
-The display panel I have has two model numbers: TXW686001 and WTL068601G,
-but cannot find any manufacturer associated with either, so opting for the
-Clockwork model number.
-
-This driver is based on the GPL-licensed driver released by Clockwork,
-authored by Pinfan Zhu, with some additional cleanup, rotation support,
-and display sleep re-enabling done by me.
-
-Original driver here for reference: https://github.com/clockworkpi/DevTerm/blob/main/Code/patch/armbian_build_a06/patch/kernel-004-panel.patch
-Display IC datasheet provided here: https://github.com/clockworkpi/DevTerm/blob/main/Schematics/ICNL9707_Datasheet.pdf
-
-Signed-off-by: Max Fierke <max@maxfierke.com>
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/Kconfig | 12 +
- drivers/gpu/drm/panel/Makefile | 1 +
- .../gpu/drm/panel/panel-clockwork-cwd686.c | 456 ++++++++++++++++++
- 3 files changed, 469 insertions(+)
- create mode 100644 drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-
---- a/drivers/gpu/drm/panel/Kconfig
-+++ b/drivers/gpu/drm/panel/Kconfig
-@@ -68,6 +68,18 @@ config DRM_PANEL_BOE_TV101WUM_NL6
- Say Y here if you want to support for BOE TV101WUM and AUO KD101N80
- 45NA WUXGA PANEL DSI Video Mode panel
-
-+config DRM_PANEL_CLOCKWORK_CWD686
-+ tristate "Clockwork CWD686 panel"
-+ depends on OF
-+ depends on DRM_MIPI_DSI
-+ depends on BACKLIGHT_CLASS_DEVICE
-+ help
-+ Say Y here if you want to enable support for the Clockwork CWD686
-+ ICNL9707-based panel, e.g. as used within the Clockwork DevTerm.
-+ The panel has a 480x1280 resolution and uses 24 bit RGB per pixel.
-+
-+ To compile this driver as a module, choose M here.
-+
- config DRM_PANEL_DSI_CM
- tristate "Generic DSI command mode panels"
- depends on OF
---- a/drivers/gpu/drm/panel/Makefile
-+++ b/drivers/gpu/drm/panel/Makefile
-@@ -5,6 +5,7 @@ obj-$(CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_N
- obj-$(CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0) += panel-boe-bf060y8m-aj0.o
- obj-$(CONFIG_DRM_PANEL_BOE_HIMAX8279D) += panel-boe-himax8279d.o
- obj-$(CONFIG_DRM_PANEL_BOE_TV101WUM_NL6) += panel-boe-tv101wum-nl6.o
-+obj-$(CONFIG_DRM_PANEL_CLOCKWORK_CWD686) += panel-clockwork-cwd686.o
- obj-$(CONFIG_DRM_PANEL_DSI_CM) += panel-dsi-cm.o
- obj-$(CONFIG_DRM_PANEL_LVDS) += panel-lvds.o
- obj-$(CONFIG_DRM_PANEL_SIMPLE) += panel-simple.o
---- /dev/null
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -0,0 +1,456 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * Copyright (c) 2021 Clockwork Tech LLC
-+ * Copyright (c) 2021-2022 Max Fierke <max@maxfierke.com>
-+ *
-+ * Based on Pinfan Zhu's work on panel-cwd686.c for ClockworkPi's 5.10 BSP
-+ */
-+
-+#include <drm/drm_modes.h>
-+#include <drm/drm_mipi_dsi.h>
-+#include <drm/drm_panel.h>
-+#include <linux/backlight.h>
-+#include <linux/gpio/consumer.h>
-+#include <linux/regulator/consumer.h>
-+#include <linux/delay.h>
-+#include <linux/of_device.h>
-+#include <linux/module.h>
-+#include <video/mipi_display.h>
-+
-+struct cwd686 {
-+ struct device *dev;
-+ struct drm_panel panel;
-+ struct regulator *supply;
-+ struct gpio_desc *enable_gpio;
-+ struct gpio_desc *reset_gpio;
-+ struct backlight_device *backlight;
-+ enum drm_panel_orientation orientation;
-+ bool prepared;
-+ bool enabled;
-+};
-+
-+static const struct drm_display_mode default_mode = {
-+ .clock = 54465,
-+ .hdisplay = 480,
-+ .hsync_start = 480 + 150,
-+ .hsync_end = 480 + 150 + 24,
-+ .htotal = 480 + 150 + 24 + 40,
-+ .vdisplay = 1280,
-+ .vsync_start = 1280 + 12,
-+ .vsync_end = 1280 + 12 + 6,
-+ .vtotal = 1280 + 12 + 6 + 10,
-+};
-+
-+static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
-+{
-+ return container_of(panel, struct cwd686, panel);
-+}
-+
-+#define ICNL9707_DCS(seq...) \
-+({ \
-+ static const u8 d[] = { seq }; \
-+ mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
-+})
-+
-+#define ICNL9707_CMD_CGOUTL 0xB3
-+#define ICNL9707_CMD_CGOUTR 0xB4
-+#define ICNL9707_P_CGOUT_VGL 0x00
-+#define ICNL9707_P_CGOUT_VGH 0x01
-+#define ICNL9707_P_CGOUT_HZ 0x02
-+#define ICNL9707_P_CGOUT_GND 0x03
-+#define ICNL9707_P_CGOUT_GSP1 0x04
-+#define ICNL9707_P_CGOUT_GSP2 0x05
-+#define ICNL9707_P_CGOUT_GSP3 0x06
-+#define ICNL9707_P_CGOUT_GSP4 0x07
-+#define ICNL9707_P_CGOUT_GSP5 0x08
-+#define ICNL9707_P_CGOUT_GSP6 0x09
-+#define ICNL9707_P_CGOUT_GSP7 0x0A
-+#define ICNL9707_P_CGOUT_GSP8 0x0B
-+#define ICNL9707_P_CGOUT_GCK1 0x0C
-+#define ICNL9707_P_CGOUT_GCK2 0x0D
-+#define ICNL9707_P_CGOUT_GCK3 0x0E
-+#define ICNL9707_P_CGOUT_GCK4 0x0F
-+#define ICNL9707_P_CGOUT_GCK5 0x10
-+#define ICNL9707_P_CGOUT_GCK6 0x11
-+#define ICNL9707_P_CGOUT_GCK7 0x12
-+#define ICNL9707_P_CGOUT_GCK8 0x13
-+#define ICNL9707_P_CGOUT_GCK9 0x14
-+#define ICNL9707_P_CGOUT_GCK10 0x15
-+#define ICNL9707_P_CGOUT_GCK11 0x16
-+#define ICNL9707_P_CGOUT_GCK12 0x17
-+#define ICNL9707_P_CGOUT_GCK13 0x18
-+#define ICNL9707_P_CGOUT_GCK14 0x19
-+#define ICNL9707_P_CGOUT_GCK15 0x1A
-+#define ICNL9707_P_CGOUT_GCK16 0x1B
-+#define ICNL9707_P_CGOUT_DIR 0x1C
-+#define ICNL9707_P_CGOUT_DIRB 0x1D
-+#define ICNL9707_P_CGOUT_ECLK_AC 0x1E
-+#define ICNL9707_P_CGOUT_ECLK_ACB 0x1F
-+#define ICNL9707_P_CGOUT_ECLK_AC2 0x20
-+#define ICNL9707_P_CGOUT_ECLK_AC2B 0x21
-+#define ICNL9707_P_CGOUT_GCH 0x22
-+#define ICNL9707_P_CGOUT_GCL 0x23
-+#define ICNL9707_P_CGOUT_XDON 0x24
-+#define ICNL9707_P_CGOUT_XDONB 0x25
-+
-+#define ICNL9707_MADCTL_ML 0x10
-+#define ICNL9707_MADCTL_RGB 0x00
-+#define ICNL9707_MADCTL_BGR 0x08
-+#define ICNL9707_MADCTL_MH 0x04
-+
-+#define ICNL9707_CMD_PWRCON_VCOM 0xB6
-+#define ICNL9707_P_PWRCON_VCOM_0495V 0x0D
-+
-+#define ICNL9707_CMD_PWRCON_SEQ 0xB7
-+#define ICNL9707_CMD_PWRCON_CLK 0xB8
-+#define ICNL9707_CMD_PWRCON_BTA 0xB9
-+#define ICNL9707_CMD_PWRCON_MODE 0xBA
-+#define ICNL9707_CMD_PWRCON_REG 0xBD
-+
-+#define ICNL9707_CMD_TCON 0xC1
-+#define ICNL9707_CMD_TCON2 0xC2
-+#define ICNL9707_CMD_TCON3 0xC3
-+#define ICNL9707_CMD_SRC_TIM 0xC6
-+#define ICNL9707_CMD_SRCCON 0xC7
-+#define ICNL9707_CMD_SET_GAMMA 0xC8
-+
-+#define ICNL9707_CMD_ETC 0xD0
-+
-+#define ICNL9707_CMD_PASSWORD1 0xF0
-+#define ICNL9707_P_PASSWORD1_DEFAULT 0xA5
-+#define ICNL9707_P_PASSWORD1_ENABLE_LVL2 0x5A
-+
-+#define ICNL9707_CMD_PASSWORD2 0xF1
-+#define ICNL9707_P_PASSWORD2_DEFAULT 0x5A
-+#define ICNL9707_P_PASSWORD2_ENABLE_LVL2 0xA5
-+
-+static int cwd686_init_sequence(struct cwd686 *ctx)
-+{
-+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+ int err;
-+
-+ /* Enable access to Level 2 registers */
-+ ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
-+ ICNL9707_P_PASSWORD1_ENABLE_LVL2,
-+ ICNL9707_P_PASSWORD1_ENABLE_LVL2);
-+ ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
-+ ICNL9707_P_PASSWORD2_ENABLE_LVL2,
-+ ICNL9707_P_PASSWORD2_ENABLE_LVL2);
-+
-+ /* Set PWRCON_VCOM (-0.495V, -0.495V) */
-+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_VCOM,
-+ ICNL9707_P_PWRCON_VCOM_0495V,
-+ ICNL9707_P_PWRCON_VCOM_0495V);
-+
-+ /* Map ASG output signals */
-+ ICNL9707_DCS(ICNL9707_CMD_CGOUTR,
-+ ICNL9707_P_CGOUT_GSP7, ICNL9707_P_CGOUT_GSP5,
-+ ICNL9707_P_CGOUT_GCK7, ICNL9707_P_CGOUT_GCK5,
-+ ICNL9707_P_CGOUT_GCK3, ICNL9707_P_CGOUT_GCK1,
-+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
-+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+ ICNL9707_P_CGOUT_GSP1, ICNL9707_P_CGOUT_GSP3);
-+ ICNL9707_DCS(ICNL9707_CMD_CGOUTL,
-+ ICNL9707_P_CGOUT_GSP8, ICNL9707_P_CGOUT_GSP6,
-+ ICNL9707_P_CGOUT_GCK8, ICNL9707_P_CGOUT_GCK6,
-+ ICNL9707_P_CGOUT_GCK4, ICNL9707_P_CGOUT_GCK2,
-+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
-+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-+ ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+ ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-+ ICNL9707_P_CGOUT_GSP2, ICNL9707_P_CGOUT_GSP4);
-+
-+ /* Undocumented commands provided by the vendor */
-+ ICNL9707_DCS(0xB0, 0x54, 0x32, 0x23, 0x45, 0x44, 0x44, 0x44, 0x44, 0x90, 0x01, 0x90, 0x01);
-+ ICNL9707_DCS(0xB1, 0x32, 0x84, 0x02, 0x83, 0x30, 0x01, 0x6B, 0x01);
-+ ICNL9707_DCS(0xB2, 0x73);
-+
-+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_REG,
-+ 0x4E, 0x0E, 0x50, 0x50, 0x26,
-+ 0x1D, 0x00, 0x14, 0x42, 0x03);
-+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_SEQ,
-+ 0x01, 0x01, 0x09, 0x11, 0x0D, 0x55,
-+ 0x19, 0x19, 0x21, 0x1D, 0x00, 0x00,
-+ 0x00, 0x00, 0x02, 0xFF, 0x3C);
-+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_CLK, 0x23, 0x01, 0x30, 0x34, 0x63);
-+
-+ /* Disable abnormal power-off flag */
-+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_BTA, 0xA0, 0x22, 0x00, 0x44);
-+
-+ ICNL9707_DCS(ICNL9707_CMD_PWRCON_MODE, 0x12, 0x63);
-+
-+ /* Set VBP, VFP, VSW, HBP, HFP, HSW */
-+ ICNL9707_DCS(ICNL9707_CMD_TCON, 0x0C, 0x16, 0x04, 0x0C, 0x10, 0x04);
-+
-+ /* Set resolution */
-+ ICNL9707_DCS(ICNL9707_CMD_TCON2, 0x11, 0x41);
-+
-+ /* Set frame blanking */
-+ ICNL9707_DCS(ICNL9707_CMD_TCON3, 0x22, 0x31, 0x04);
-+
-+ ICNL9707_DCS(ICNL9707_CMD_SRCCON, 0x05, 0x23, 0x6B, 0x49, 0x00);
-+
-+ /* Another undocumented command */
-+ ICNL9707_DCS(0xC5, 0x00);
-+
-+ ICNL9707_DCS(ICNL9707_CMD_ETC, 0x37, 0xFF, 0xFF);
-+
-+ /* Another set of undocumented commands */
-+ ICNL9707_DCS(0xD2, 0x63, 0x0B, 0x08, 0x88);
-+ ICNL9707_DCS(0xD3, 0x01, 0x00, 0x00, 0x01, 0x01, 0x37, 0x25, 0x38, 0x31, 0x06, 0x07);
-+
-+ /* Set Gamma to 2.2 */
-+ ICNL9707_DCS(ICNL9707_CMD_SET_GAMMA,
-+ 0x7C, 0x6A, 0x5D, 0x53, 0x53, 0x45, 0x4B,
-+ 0x35, 0x4D, 0x4A, 0x49, 0x66, 0x53, 0x57,
-+ 0x4A, 0x48, 0x3B, 0x2A, 0x06, 0x7C, 0x6A,
-+ 0x5D, 0x53, 0x53, 0x45, 0x4B, 0x35, 0x4D,
-+ 0x4A, 0x49, 0x66, 0x53, 0x57, 0x4A, 0x48,
-+ 0x3B, 0x2A, 0x06);
-+
-+ ICNL9707_DCS(ICNL9707_CMD_SRC_TIM, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00);
-+
-+ /* Another undocumented command */
-+ ICNL9707_DCS(0xF4, 0x08, 0x77);
-+
-+ ICNL9707_DCS(MIPI_DCS_SET_ADDRESS_MODE,
-+ ICNL9707_MADCTL_RGB | ICNL9707_MADCTL_ML | ICNL9707_MADCTL_MH);
-+
-+ /* Enable tearing mode at VBLANK */
-+ err = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
-+ if (err) {
-+ dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", err);
-+ return err;
-+ }
-+
-+ /* Disable access to Level 2 registers */
-+ ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
-+ ICNL9707_P_PASSWORD2_DEFAULT,
-+ ICNL9707_P_PASSWORD2_DEFAULT);
-+ ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
-+ ICNL9707_P_PASSWORD1_DEFAULT,
-+ ICNL9707_P_PASSWORD1_DEFAULT);
-+
-+ return 0;
-+}
-+
-+static int cwd686_disable(struct drm_panel *panel)
-+{
-+ struct cwd686 *ctx = panel_to_cwd686(panel);
-+
-+ if (!ctx->enabled)
-+ return 0;
-+
-+ backlight_disable(ctx->backlight);
-+
-+ ctx->enabled = false;
-+
-+ return 0;
-+}
-+
-+static int cwd686_unprepare(struct drm_panel *panel)
-+{
-+ struct cwd686 *ctx = panel_to_cwd686(panel);
-+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+ int err;
-+
-+ if (!ctx->prepared)
-+ return 0;
-+
-+ err = mipi_dsi_dcs_set_display_off(dsi);
-+ if (err) {
-+ dev_err(ctx->dev, "failed to turn display off (%d)\n", err);
-+ return err;
-+ }
-+
-+ err = mipi_dsi_dcs_enter_sleep_mode(dsi);
-+ if (err) {
-+ dev_err(ctx->dev, "failed to enter sleep mode (%d)\n", err);
-+ return err;
-+ }
-+
-+ msleep(120);
-+
-+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
-+
-+ ctx->prepared = false;
-+
-+ return 0;
-+}
-+
-+static int cwd686_prepare(struct drm_panel *panel)
-+{
-+ struct cwd686 *ctx = panel_to_cwd686(panel);
-+ struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-+ int err;
-+
-+ if (ctx->prepared)
-+ return 0;
-+
-+ gpiod_set_value_cansleep(ctx->reset_gpio, 1);
-+ /* T2 */
-+ msleep(10);
-+
-+ gpiod_set_value_cansleep(ctx->reset_gpio, 0);
-+ /* T3 */
-+ msleep(20);
-+
-+ /* Exit sleep mode and power on */
-+
-+ err = cwd686_init_sequence(ctx);
-+ if (err) {
-+ dev_err(ctx->dev, "failed to initialize display (%d)\n", err);
-+ return err;
-+ }
-+
-+ err = mipi_dsi_dcs_exit_sleep_mode(dsi);
-+ if (err) {
-+ dev_err(ctx->dev, "failed to exit sleep mode (%d)\n", err);
-+ return err;
-+ }
-+ /* T6 */
-+ msleep(120);
-+
-+ err = mipi_dsi_dcs_set_display_on(dsi);
-+ if (err) {
-+ dev_err(ctx->dev, "failed to turn display on (%d)\n", err);
-+ return err;
-+ }
-+ msleep(20);
-+
-+ ctx->prepared = true;
-+
-+ return 0;
-+}
-+
-+static int cwd686_enable(struct drm_panel *panel)
-+{
-+ struct cwd686 *ctx = panel_to_cwd686(panel);
-+
-+ if (ctx->enabled)
-+ return 0;
-+
-+ backlight_enable(ctx->backlight);
-+
-+ ctx->enabled = true;
-+
-+ return 0;
-+}
-+
-+static int cwd686_get_modes(struct drm_panel *panel, struct drm_connector *connector)
-+{
-+ struct cwd686 *ctx = panel_to_cwd686(panel);
-+ struct drm_display_mode *mode;
-+
-+ mode = drm_mode_duplicate(connector->dev, &default_mode);
-+ if (!mode) {
-+ dev_err(panel->dev, "bad mode or failed to add mode\n");
-+ return -EINVAL;
-+ }
-+ drm_mode_set_name(mode);
-+ mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
-+
-+ connector->display_info.width_mm = mode->width_mm;
-+ connector->display_info.height_mm = mode->height_mm;
-+
-+ /* set up connector's "panel orientation" property */
-+ drm_connector_set_panel_orientation(connector, ctx->orientation);
-+
-+ drm_mode_probed_add(connector, mode);
-+
-+ return 1; /* Number of modes */
-+}
-+
-+static const struct drm_panel_funcs cwd686_drm_funcs = {
-+ .disable = cwd686_disable,
-+ .unprepare = cwd686_unprepare,
-+ .prepare = cwd686_prepare,
-+ .enable = cwd686_enable,
-+ .get_modes = cwd686_get_modes,
-+};
-+
-+static int cwd686_probe(struct mipi_dsi_device *dsi)
-+{
-+ struct device *dev = &dsi->dev;
-+ struct cwd686 *ctx;
-+ int err;
-+
-+ ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
-+ if (!ctx)
-+ return -ENOMEM;
-+
-+ mipi_dsi_set_drvdata(dsi, ctx);
-+ ctx->dev = dev;
-+
-+ dsi->lanes = 4;
-+ dsi->format = MIPI_DSI_FMT_RGB888;
-+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
-+ MIPI_DSI_MODE_VIDEO_BURST |
-+ MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
-+
-+ ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
-+ if (IS_ERR(ctx->reset_gpio)) {
-+ err = PTR_ERR(ctx->reset_gpio);
-+ if (err != -EPROBE_DEFER)
-+ dev_err(dev, "failed to request GPIO (%d)\n", err);
-+ return err;
-+ }
-+
-+ ctx->backlight = devm_of_find_backlight(dev);
-+ if (IS_ERR(ctx->backlight))
-+ return PTR_ERR(ctx->backlight);
-+
-+ err = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation);
-+ if (err) {
-+ dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
-+ return err;
-+ }
-+
-+ drm_panel_init(&ctx->panel, dev, &cwd686_drm_funcs, DRM_MODE_CONNECTOR_DSI);
-+
-+ drm_panel_add(&ctx->panel);
-+
-+ err = mipi_dsi_attach(dsi);
-+ if (err < 0) {
-+ dev_err(dev, "mipi_dsi_attach() failed: %d\n", err);
-+ drm_panel_remove(&ctx->panel);
-+ return err;
-+ }
-+
-+ return 0;
-+}
-+
-+static void cwd686_remove(struct mipi_dsi_device *dsi)
-+{
-+ struct cwd686 *ctx = mipi_dsi_get_drvdata(dsi);
-+
-+ mipi_dsi_detach(dsi);
-+ drm_panel_remove(&ctx->panel);
-+}
-+
-+static const struct of_device_id cwd686_of_match[] = {
-+ { .compatible = "clockwork,cwd686" },
-+ { /* sentinel */ }
-+};
-+MODULE_DEVICE_TABLE(of, cwd686_of_match);
-+
-+static struct mipi_dsi_driver cwd686_driver = {
-+ .probe = cwd686_probe,
-+ .remove = cwd686_remove,
-+ .driver = {
-+ .name = "panel-clockwork-cwd686",
-+ .of_match_table = cwd686_of_match,
-+ },
-+};
-+module_mipi_dsi_driver(cwd686_driver);
-+
-+MODULE_AUTHOR("Pinfan Zhu <zhu@clockworkpi.com>");
-+MODULE_AUTHOR("Max Fierke <max@maxfierke.com>");
-+MODULE_DESCRIPTION("ClockworkPi CWD686 panel driver");
-+MODULE_LICENSE("GPL");
+++ /dev/null
-From 979271f803c1578087a965a2a4b845c87e7d922f Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 19:14:21 -0500
-Subject: [PATCH 108/117] drm: panel: cwd686: Add regulators
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../gpu/drm/panel/panel-clockwork-cwd686.c | 26 ++++++++++++++++++-
- 1 file changed, 25 insertions(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -20,7 +20,8 @@
- struct cwd686 {
- struct device *dev;
- struct drm_panel panel;
-- struct regulator *supply;
-+ struct regulator *iovcc;
-+ struct regulator *vci;
- struct gpio_desc *enable_gpio;
- struct gpio_desc *reset_gpio;
- struct backlight_device *backlight;
-@@ -279,6 +280,9 @@ static int cwd686_unprepare(struct drm_p
-
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
-
-+ regulator_disable(ctx->vci);
-+ regulator_disable(ctx->iovcc);
-+
- ctx->prepared = false;
-
- return 0;
-@@ -293,6 +297,18 @@ static int cwd686_prepare(struct drm_pan
- if (ctx->prepared)
- return 0;
-
-+ err = regulator_enable(ctx->iovcc);
-+ if (err) {
-+ dev_err(ctx->dev, "failed to enable iovcc (%d)\n", err);
-+ return err;
-+ }
-+
-+ err = regulator_enable(ctx->vci);
-+ if (err) {
-+ dev_err(ctx->dev, "failed to enable vci (%d)\n", err);
-+ return err;
-+ }
-+
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- /* T2 */
- msleep(10);
-@@ -402,6 +418,14 @@ static int cwd686_probe(struct mipi_dsi_
- return err;
- }
-
-+ ctx->iovcc = devm_regulator_get(dev, "iovcc");
-+ if (IS_ERR(ctx->iovcc))
-+ return PTR_ERR(ctx->iovcc);
-+
-+ ctx->vci = devm_regulator_get(dev, "vci");
-+ if (IS_ERR(ctx->vci))
-+ return PTR_ERR(ctx->vci);
-+
- ctx->backlight = devm_of_find_backlight(dev);
- if (IS_ERR(ctx->backlight))
- return PTR_ERR(ctx->backlight);
+++ /dev/null
-From 6112585994a6bdbd882709e7187c8c9289211b3b Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 19:16:03 -0500
-Subject: [PATCH 109/117] drm: panel: cwd686: Make reset gpio mandatory
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -410,7 +410,7 @@ static int cwd686_probe(struct mipi_dsi_
- MIPI_DSI_MODE_VIDEO_BURST |
- MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
-
-- ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
-+ ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
- if (IS_ERR(ctx->reset_gpio)) {
- err = PTR_ERR(ctx->reset_gpio);
- if (err != -EPROBE_DEFER)
+++ /dev/null
-From 8d70f9f4a66522c2720de986623d1130337ff670 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 19:16:18 -0500
-Subject: [PATCH 110/117] drm: panel: cwd686: Increase post-reset delay
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -315,7 +315,7 @@ static int cwd686_prepare(struct drm_pan
-
- gpiod_set_value_cansleep(ctx->reset_gpio, 0);
- /* T3 */
-- msleep(20);
-+ msleep(120);
-
- /* Exit sleep mode and power on */
-
+++ /dev/null
-From 8fc2a02d1d2e98a01a2dad3bf3da8e33366725eb Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 19:17:35 -0500
-Subject: [PATCH 111/117] drm: panel: cwd686: Use vendor panel init sequence
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../gpu/drm/panel/panel-clockwork-cwd686.c | 142 ++++--------------
- 1 file changed, 32 insertions(+), 110 deletions(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -47,10 +47,12 @@ static inline struct cwd686 *panel_to_cw
- return container_of(panel, struct cwd686, panel);
- }
-
--#define ICNL9707_DCS(seq...) \
-+#define dcs_write_seq(seq...) \
- ({ \
- static const u8 d[] = { seq }; \
-- mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
-+ ssize_t r = mipi_dsi_dcs_write_buffer(dsi, d, ARRAY_SIZE(d)); \
-+ if (r < 0) \
-+ return r; \
- })
-
- #define ICNL9707_CMD_CGOUTL 0xB3
-@@ -128,115 +130,35 @@ static inline struct cwd686 *panel_to_cw
- static int cwd686_init_sequence(struct cwd686 *ctx)
- {
- struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-- int err;
-
-- /* Enable access to Level 2 registers */
-- ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
-- ICNL9707_P_PASSWORD1_ENABLE_LVL2,
-- ICNL9707_P_PASSWORD1_ENABLE_LVL2);
-- ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
-- ICNL9707_P_PASSWORD2_ENABLE_LVL2,
-- ICNL9707_P_PASSWORD2_ENABLE_LVL2);
--
-- /* Set PWRCON_VCOM (-0.495V, -0.495V) */
-- ICNL9707_DCS(ICNL9707_CMD_PWRCON_VCOM,
-- ICNL9707_P_PWRCON_VCOM_0495V,
-- ICNL9707_P_PWRCON_VCOM_0495V);
--
-- /* Map ASG output signals */
-- ICNL9707_DCS(ICNL9707_CMD_CGOUTR,
-- ICNL9707_P_CGOUT_GSP7, ICNL9707_P_CGOUT_GSP5,
-- ICNL9707_P_CGOUT_GCK7, ICNL9707_P_CGOUT_GCK5,
-- ICNL9707_P_CGOUT_GCK3, ICNL9707_P_CGOUT_GCK1,
-- ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
-- ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-- ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-- ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-- ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-- ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-- ICNL9707_P_CGOUT_GSP1, ICNL9707_P_CGOUT_GSP3);
-- ICNL9707_DCS(ICNL9707_CMD_CGOUTL,
-- ICNL9707_P_CGOUT_GSP8, ICNL9707_P_CGOUT_GSP6,
-- ICNL9707_P_CGOUT_GCK8, ICNL9707_P_CGOUT_GCK6,
-- ICNL9707_P_CGOUT_GCK4, ICNL9707_P_CGOUT_GCK2,
-- ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_VGL,
-- ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-- ICNL9707_P_CGOUT_VGL, ICNL9707_P_CGOUT_GND,
-- ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-- ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-- ICNL9707_P_CGOUT_GND, ICNL9707_P_CGOUT_GND,
-- ICNL9707_P_CGOUT_GSP2, ICNL9707_P_CGOUT_GSP4);
--
-- /* Undocumented commands provided by the vendor */
-- ICNL9707_DCS(0xB0, 0x54, 0x32, 0x23, 0x45, 0x44, 0x44, 0x44, 0x44, 0x90, 0x01, 0x90, 0x01);
-- ICNL9707_DCS(0xB1, 0x32, 0x84, 0x02, 0x83, 0x30, 0x01, 0x6B, 0x01);
-- ICNL9707_DCS(0xB2, 0x73);
--
-- ICNL9707_DCS(ICNL9707_CMD_PWRCON_REG,
-- 0x4E, 0x0E, 0x50, 0x50, 0x26,
-- 0x1D, 0x00, 0x14, 0x42, 0x03);
-- ICNL9707_DCS(ICNL9707_CMD_PWRCON_SEQ,
-- 0x01, 0x01, 0x09, 0x11, 0x0D, 0x55,
-- 0x19, 0x19, 0x21, 0x1D, 0x00, 0x00,
-- 0x00, 0x00, 0x02, 0xFF, 0x3C);
-- ICNL9707_DCS(ICNL9707_CMD_PWRCON_CLK, 0x23, 0x01, 0x30, 0x34, 0x63);
--
-- /* Disable abnormal power-off flag */
-- ICNL9707_DCS(ICNL9707_CMD_PWRCON_BTA, 0xA0, 0x22, 0x00, 0x44);
--
-- ICNL9707_DCS(ICNL9707_CMD_PWRCON_MODE, 0x12, 0x63);
--
-- /* Set VBP, VFP, VSW, HBP, HFP, HSW */
-- ICNL9707_DCS(ICNL9707_CMD_TCON, 0x0C, 0x16, 0x04, 0x0C, 0x10, 0x04);
--
-- /* Set resolution */
-- ICNL9707_DCS(ICNL9707_CMD_TCON2, 0x11, 0x41);
--
-- /* Set frame blanking */
-- ICNL9707_DCS(ICNL9707_CMD_TCON3, 0x22, 0x31, 0x04);
--
-- ICNL9707_DCS(ICNL9707_CMD_SRCCON, 0x05, 0x23, 0x6B, 0x49, 0x00);
--
-- /* Another undocumented command */
-- ICNL9707_DCS(0xC5, 0x00);
--
-- ICNL9707_DCS(ICNL9707_CMD_ETC, 0x37, 0xFF, 0xFF);
--
-- /* Another set of undocumented commands */
-- ICNL9707_DCS(0xD2, 0x63, 0x0B, 0x08, 0x88);
-- ICNL9707_DCS(0xD3, 0x01, 0x00, 0x00, 0x01, 0x01, 0x37, 0x25, 0x38, 0x31, 0x06, 0x07);
--
-- /* Set Gamma to 2.2 */
-- ICNL9707_DCS(ICNL9707_CMD_SET_GAMMA,
-- 0x7C, 0x6A, 0x5D, 0x53, 0x53, 0x45, 0x4B,
-- 0x35, 0x4D, 0x4A, 0x49, 0x66, 0x53, 0x57,
-- 0x4A, 0x48, 0x3B, 0x2A, 0x06, 0x7C, 0x6A,
-- 0x5D, 0x53, 0x53, 0x45, 0x4B, 0x35, 0x4D,
-- 0x4A, 0x49, 0x66, 0x53, 0x57, 0x4A, 0x48,
-- 0x3B, 0x2A, 0x06);
--
-- ICNL9707_DCS(ICNL9707_CMD_SRC_TIM, 0x00, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x00, 0x00);
--
-- /* Another undocumented command */
-- ICNL9707_DCS(0xF4, 0x08, 0x77);
--
-- ICNL9707_DCS(MIPI_DCS_SET_ADDRESS_MODE,
-- ICNL9707_MADCTL_RGB | ICNL9707_MADCTL_ML | ICNL9707_MADCTL_MH);
--
-- /* Enable tearing mode at VBLANK */
-- err = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK);
-- if (err) {
-- dev_err(ctx->dev, "failed to enable vblank TE (%d)\n", err);
-- return err;
-- }
--
-- /* Disable access to Level 2 registers */
-- ICNL9707_DCS(ICNL9707_CMD_PASSWORD2,
-- ICNL9707_P_PASSWORD2_DEFAULT,
-- ICNL9707_P_PASSWORD2_DEFAULT);
-- ICNL9707_DCS(ICNL9707_CMD_PASSWORD1,
-- ICNL9707_P_PASSWORD1_DEFAULT,
-- ICNL9707_P_PASSWORD1_DEFAULT);
-+ dcs_write_seq(0xF0,0x5A,0x5A);
-+ dcs_write_seq(0xF1,0xA5,0xA5);
-+ dcs_write_seq(0xB6,0x0D,0x0D);
-+ dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
-+ dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
-+ dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01);
-+ dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01);
-+ dcs_write_seq(0xB2,0x73);
-+ dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03);
-+ dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C);
-+ dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63);
-+ dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44);
-+ dcs_write_seq(0xBA,0x12,0x63);
-+ dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04);
-+ dcs_write_seq(0xC2,0x11,0x41);
-+ dcs_write_seq(0xC3,0x22,0x31,0x04);
-+ dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00);
-+ dcs_write_seq(0xC5,0x00);
-+ dcs_write_seq(0xD0,0x37,0xFF,0xFF);
-+ dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88);
-+ dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07);
-+ dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2
-+ dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00);
-+ dcs_write_seq(0xF4,0x08,0x77);
-+ dcs_write_seq(0x36,0x14);
-+ dcs_write_seq(0x35,0x00);
-+ dcs_write_seq(0xF1,0x5A,0x5A);
-+ dcs_write_seq(0xF0,0xA5,0xA5);
-
- return 0;
- }
+++ /dev/null
-From 6ea428297717faa16056076f7dd5a69e49c58fe6 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Sun, 7 Aug 2022 23:34:35 -0500
-Subject: [PATCH 112/117] drm: panel: cwd686: Fix timings
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 18 +++++++++---------
- 1 file changed, 9 insertions(+), 9 deletions(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -31,15 +31,15 @@ struct cwd686 {
- };
-
- static const struct drm_display_mode default_mode = {
-- .clock = 54465,
-- .hdisplay = 480,
-- .hsync_start = 480 + 150,
-- .hsync_end = 480 + 150 + 24,
-- .htotal = 480 + 150 + 24 + 40,
-- .vdisplay = 1280,
-- .vsync_start = 1280 + 12,
-- .vsync_end = 1280 + 12 + 6,
-- .vtotal = 1280 + 12 + 6 + 10,
-+ .clock = 54465,
-+ .hdisplay = 480,
-+ .hsync_start = 480 + 64,
-+ .hsync_end = 480 + 64 + 40,
-+ .htotal = 480 + 64 + 40 + 110,
-+ .vdisplay = 1280,
-+ .vsync_start = 1280 + 16,
-+ .vsync_end = 1280 + 16 + 10,
-+ .vtotal = 1280 + 16 + 10 + 2,
- };
-
- static inline struct cwd686 *panel_to_cwd686(struct drm_panel *panel)
+++ /dev/null
-From 16359ba0c5f5011e4742672454b35ad91a02fabe Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Mon, 8 Aug 2022 00:30:17 -0500
-Subject: [PATCH 113/117] drm: panel: cwd686: Disable burst
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -329,7 +329,6 @@ static int cwd686_probe(struct mipi_dsi_
- dsi->lanes = 4;
- dsi->format = MIPI_DSI_FMT_RGB888;
- dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
-- MIPI_DSI_MODE_VIDEO_BURST |
- MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
-
- ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
+++ /dev/null
-From 02da00f2215f3d755ec806636fe499331870e8d6 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 9 Aug 2022 20:14:59 -0500
-Subject: [PATCH 114/117] drm: panel: cwd686: Use the init sequence from the
- R-01 BSP
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- .../gpu/drm/panel/panel-clockwork-cwd686.c | 44 ++++++++-----------
- 1 file changed, 19 insertions(+), 25 deletions(-)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -131,34 +131,28 @@ static int cwd686_init_sequence(struct c
- {
- struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-
-- dcs_write_seq(0xF0,0x5A,0x5A);
-- dcs_write_seq(0xF1,0xA5,0xA5);
-- dcs_write_seq(0xB6,0x0D,0x0D);
-- dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
-- dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
-- dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x90,0x01,0x90,0x01);
-- dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x30,0x01,0x6B,0x01);
-+ dcs_write_seq(0xF0,0x5A,0x59);
-+ dcs_write_seq(0xF1,0xA5,0xA6);
-+ dcs_write_seq(0xB0,0x54,0x32,0x23,0x45,0x44,0x44,0x44,0x44,0x9F,0x00,0x01,0x9F,0x00,0x01);
-+ dcs_write_seq(0xB1,0x32,0x84,0x02,0x83,0x29,0x06,0x06,0x72,0x06,0x06);
- dcs_write_seq(0xB2,0x73);
-- dcs_write_seq(0xBD,0x4E,0x0E,0x50,0x50,0x26,0x1D,0x00,0x14,0x42,0x03);
-- dcs_write_seq(0xB7,0x01,0x01,0x09,0x11,0x0D,0x55,0x19,0x19,0x21,0x1D,0x00,0x00,0x00,0x00,0x02,0xFF,0x3C);
-- dcs_write_seq(0xB8,0x23,0x01,0x30,0x34,0x63);
-- dcs_write_seq(0xB9,0xA0,0x22,0x00,0x44);
-- dcs_write_seq(0xBA,0x12,0x63);
-- dcs_write_seq(0xC1,0x0C,0x16,0x04,0x0C,0x10,0x04);
-- dcs_write_seq(0xC2,0x11,0x41);
-- dcs_write_seq(0xC3,0x22,0x31,0x04);
-- dcs_write_seq(0xC7,0x05,0x23,0x6B,0x49,0x00);
-- dcs_write_seq(0xC5,0x00);
-- dcs_write_seq(0xD0,0x37,0xFF,0xFF);
-- dcs_write_seq(0xD2,0x63,0x0B,0x08,0x88);
-- dcs_write_seq(0xD3,0x01,0x00,0x00,0x01,0x01,0x37,0x25,0x38,0x31,0x06,0x07);
-- dcs_write_seq(0xC8,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06,0x7C,0x6A,0x5D,0x53,0x53,0x45,0x4B,0x35,0x4D,0x4A,0x49,0x66,0x53,0x57,0x4A,0x48,0x3B,0x2A,0x06);//GAMMA2.2
-- dcs_write_seq(0xC6,0x00,0x00,0xFF,0x00,0x00,0xFF,0x00,0x00);
-- dcs_write_seq(0xF4,0x08,0x77);
-+ dcs_write_seq(0xB3,0x0B,0x09,0x13,0x11,0x0F,0x0D,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x05,0x07);
-+ dcs_write_seq(0xB4,0x0A,0x08,0x12,0x10,0x0E,0x0C,0x00,0x00,0x00,0x03,0x00,0x03,0x03,0x03,0x03,0x03,0x03,0x03,0x04,0x06);
-+ dcs_write_seq(0xB6,0x13,0x13);
-+ dcs_write_seq(0xB8,0xB4,0x43,0x02,0xCC);
-+ dcs_write_seq(0xB9,0xA5,0x20,0xFF,0xC8);
-+ dcs_write_seq(0xBA,0x88,0x23);
-+ dcs_write_seq(0xBD,0x43,0x0E,0x0E,0x50,0x50,0x29,0x10,0x03,0x44,0x03);
-+ dcs_write_seq(0xC1,0x00,0x0C,0x16,0x04,0x00,0x30,0x10,0x04);
-+ dcs_write_seq(0xC2,0x21,0x81);
-+ dcs_write_seq(0xC3,0x02,0x30);
-+ dcs_write_seq(0xC7,0x25,0x6A);
-+ dcs_write_seq(0xC8,0x7C,0x68,0x59,0x4E,0x4B,0x3C,0x41,0x2B,0x44,0x43,0x43,0x60,0x4E,0x55,0x47,0x44,0x38,0x27,0x06,0x7C,0x68,0x59,0x4E,0x4B,0x3C,0x41,0x2B,0x44,0x43,0x43,0x60,0x4E,0x55,0x47,0x44,0x38,0x27,0x06);
-+ dcs_write_seq(0xD4,0x00,0x00,0x00,0x32,0x04,0x51);
-+ dcs_write_seq(0xF1,0x5A,0x59);
-+ dcs_write_seq(0xF0,0xA5,0xA6);
- dcs_write_seq(0x36,0x14);
- dcs_write_seq(0x35,0x00);
-- dcs_write_seq(0xF1,0x5A,0x5A);
-- dcs_write_seq(0xF0,0xA5,0xA5);
-
- return 0;
- }
+++ /dev/null
-From 6b438292e6b86a5cb5bffee2e517f1335903e39e Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 9 Aug 2022 20:15:24 -0500
-Subject: [PATCH 115/117] drm: panel: cwd686: Power up sequence
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -218,12 +218,14 @@ static int cwd686_prepare(struct drm_pan
- dev_err(ctx->dev, "failed to enable iovcc (%d)\n", err);
- return err;
- }
-+ msleep(20);
-
- err = regulator_enable(ctx->vci);
- if (err) {
- dev_err(ctx->dev, "failed to enable vci (%d)\n", err);
- return err;
- }
-+ msleep(120);
-
- gpiod_set_value_cansleep(ctx->reset_gpio, 1);
- /* T2 */
+++ /dev/null
-From a19565eccfdc0fce7f41cfe70cd67a1a10d2113c Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Tue, 9 Aug 2022 20:15:39 -0500
-Subject: [PATCH 116/117] drm: panel: cwd686: Why is this not getting called?
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- drivers/gpu/drm/panel/panel-clockwork-cwd686.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-+++ b/drivers/gpu/drm/panel/panel-clockwork-cwd686.c
-@@ -373,6 +373,8 @@ static void cwd686_remove(struct mipi_ds
-
- mipi_dsi_detach(dsi);
- drm_panel_remove(&ctx->panel);
-+ if (ctx->prepared)
-+ cwd686_unprepare(&ctx->panel);
- }
-
- static const struct of_device_id cwd686_of_match[] = {
+++ /dev/null
-From d6036571b774437bb3bdd378821033e118a01fe8 Mon Sep 17 00:00:00 2001
-From: Samuel Holland <samuel@sholland.org>
-Date: Wed, 2 Nov 2022 23:42:52 -0500
-Subject: [PATCH 117/117] riscv: dts: allwinner: d1: Add video engine node
-
-Signed-off-by: Samuel Holland <samuel@sholland.org>
----
- arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 30 ++++++++++++++++++++
- 1 file changed, 30 insertions(+)
-
---- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
-@@ -105,6 +105,21 @@
- status = "reserved";
- };
-
-+ ve: video-codec@1c0e000 {
-+ compatible = "allwinner,sun20i-d1-video-engine";
-+ reg = <0x1c0e000 0x2000>;
-+ interrupts = <82 IRQ_TYPE_LEVEL_HIGH>;
-+ clocks = <&ccu CLK_BUS_VE>,
-+ <&ccu CLK_VE>,
-+ <&ccu CLK_MBUS_VE>;
-+ clock-names = "ahb", "mod", "ram";
-+ resets = <&ccu RST_BUS_VE>;
-+ allwinner,sram = <&ve_sram 1>;
-+ interconnects = <&mbus 4>;
-+ interconnect-names = "dma-mem";
-+ iommus = <&iommu 0>;
-+ };
-+
- pio: pinctrl@2000000 {
- compatible = "allwinner,sun20i-d1-pinctrl";
- reg = <0x2000000 0x800>;
-@@ -591,6 +606,21 @@
- #address-cells = <1>;
- #size-cells = <1>;
-
-+ // FIXME: Address is not verified. It is copied from A64/H6.
-+ sram@1d00000 {
-+ compatible = "mmio-sram";
-+ reg = <0x1d00000 0x40000>;
-+ ranges = <0 0x1d00000 0x40000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ ve_sram: sram-section@0 {
-+ compatible = "allwinner,sun20i-d1-sram-c1",
-+ "allwinner,sun4i-a10-sram-c1";
-+ reg = <0 0x40000>;
-+ };
-+ };
-+
- regulators@3000150 {
- compatible = "allwinner,sun20i-d1-system-ldos";
- reg = <0x3000150 0x4>;
--- /dev/null
+From c6fd43b8420f3864ad1cd64d818d9b9abc2cb711 Mon Sep 17 00:00:00 2001
+From: Inochi Amaoto <inochiama@outlook.com>
+Date: Mon, 28 Aug 2023 12:30:22 +0800
+Subject: [PATCH 01/14] riscv: dts: allwinner: d1: Add PMU event node
+
+D1 has several pmu events supported by opensbi.
+These events can be used by perf for profiling.
+
+Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
+Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
+Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Reviewed-by: Guo Ren <guoren@kernel.org>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 39 +++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+@@ -72,4 +72,43 @@
+ #interrupt-cells = <2>;
+ };
+ };
++
++ pmu {
++ compatible = "riscv,pmu";
++ riscv,event-to-mhpmcounters =
++ <0x00003 0x00003 0x00000008>,
++ <0x00004 0x00004 0x00000010>,
++ <0x00005 0x00005 0x00000200>,
++ <0x00006 0x00006 0x00000100>,
++ <0x10000 0x10000 0x00004000>,
++ <0x10001 0x10001 0x00008000>,
++ <0x10002 0x10002 0x00010000>,
++ <0x10003 0x10003 0x00020000>,
++ <0x10019 0x10019 0x00000040>,
++ <0x10021 0x10021 0x00000020>;
++ riscv,event-to-mhpmevent =
++ <0x00003 0x00000000 0x00000001>,
++ <0x00004 0x00000000 0x00000002>,
++ <0x00005 0x00000000 0x00000007>,
++ <0x00006 0x00000000 0x00000006>,
++ <0x10000 0x00000000 0x0000000c>,
++ <0x10001 0x00000000 0x0000000d>,
++ <0x10002 0x00000000 0x0000000e>,
++ <0x10003 0x00000000 0x0000000f>,
++ <0x10019 0x00000000 0x00000004>,
++ <0x10021 0x00000000 0x00000003>;
++ riscv,raw-event-to-mhpmcounters =
++ <0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
++ <0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
++ <0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
++ <0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
++ <0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
++ <0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
++ <0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
++ <0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
++ <0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
++ <0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
++ <0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
++ <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
++ };
+ };
--- /dev/null
+From 99942611816c117a01f16dbcab54908a49b378c3 Mon Sep 17 00:00:00 2001
+From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+Date: Mon, 18 Dec 2023 12:05:39 +0100
+Subject: [PATCH 02/14] riscv: dts: allwinner: Update opp table to allow CPU
+ frequency scaling
+
+Two OPPs are currently defined for the D1/D1s; one at 408MHz and
+another at 1.08GHz. Switching between these can be done with the
+"sun50i-cpufreq-nvmem" driver. This patch populates the opp table
+appropriately, inspired by
+https://github.com/Tina-Linux/linux-5.4/blob/master/arch/riscv/boot/dts/sunxi/sun20iw1p1.dtsi
+
+The supply voltages are PWM-controlled, but support for that IP
+is still in the works. So stick to a target vdd-cpu supply of 0.9V,
+which seems to be the default on most D1 boards.
+
+Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+---
+ arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+@@ -36,16 +36,22 @@
+ };
+
+ opp_table_cpu: opp-table-cpu {
+- compatible = "operating-points-v2";
++ compatible = "allwinner,sun20i-d1-operating-points",
++ "allwinner,sun50i-h6-operating-points";
++ nvmem-cells = <&cpu_speed_grade>;
++ nvmem-cell-names = "speed";
++ opp-shared;
+
+ opp-408000000 {
++ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <408000000>;
+- opp-microvolt = <900000 900000 1100000>;
++ opp-microvolt-speed0 = <900000 900000 1100000>;
+ };
+
+ opp-1080000000 {
++ clock-latency-ns = <244144>; /* 8 32k periods */
+ opp-hz = /bits/ 64 <1008000000>;
+- opp-microvolt = <900000 900000 1100000>;
++ opp-microvolt-speed0 = <900000 900000 1100000>;
+ };
+ };
+
+@@ -112,3 +118,9 @@
+ <0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
+ };
+ };
++
++&sid {
++ cpu_speed_grade: cpu-speed-grade@0 {
++ reg = <0x00 0x2>;
++ };
++};
--- /dev/null
+From e904f32e5fe694ed7b8d1cd914bcf2bfd67e896c Mon Sep 17 00:00:00 2001
+From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+Date: Mon, 18 Dec 2023 12:05:40 +0100
+Subject: [PATCH 03/14] dt-bindings: opp: sun50i: Add binding for D1 CPUs
+
+Add binding for D1 CPU OPPs.
+
+Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+---
+ .../bindings/opp/allwinner,sun50i-h6-operating-points.yaml | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
++++ b/Documentation/devicetree/bindings/opp/allwinner,sun50i-h6-operating-points.yaml
+@@ -23,7 +23,9 @@ allOf:
+
+ properties:
+ compatible:
+- const: allwinner,sun50i-h6-operating-points
++ enum:
++ - allwinner,sun50i-h6-operating-points
++ - allwinner,sun20i-d1-operating-points
+
+ nvmem-cells:
+ description: |
--- /dev/null
+From b294def636629cc4d9feff4ed610a0d0c68a58fd Mon Sep 17 00:00:00 2001
+From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+Date: Mon, 18 Dec 2023 12:05:41 +0100
+Subject: [PATCH 04/14] cpufreq: sun50i: Add D1 support
+
+Add support for D1 based devices to the Allwinner H6 cpufreq
+driver
+
+Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+---
+ drivers/cpufreq/sun50i-cpufreq-nvmem.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+@@ -160,6 +160,7 @@ static struct platform_driver sun50i_cpu
+
+ static const struct of_device_id sun50i_cpufreq_match_list[] = {
+ { .compatible = "allwinner,sun50i-h6" },
++ { .compatible = "allwinner,sun20i-d1" },
+ {}
+ };
+ MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
--- /dev/null
+From 9d78aafd278577ef2a9d92127c9d35b00989c057 Mon Sep 17 00:00:00 2001
+From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+Date: Mon, 18 Dec 2023 12:05:42 +0100
+Subject: [PATCH 05/14] cpufreq: dt-platdev: Blocklist allwinner,sun20i-d1 SoC
+
+The Allwinner D1 uses H6 cpufreq driver. Add it to blocklist
+so the "cpufreq-dt" device is not created twice.
+
+Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+---
+ drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -104,6 +104,7 @@ static const struct of_device_id allowli
+ */
+ static const struct of_device_id blocklist[] __initconst = {
+ { .compatible = "allwinner,sun50i-h6", },
++ { .compatible = "allwinner,sun20i-d1", },
+
+ { .compatible = "apple,arm-platform", },
+
--- /dev/null
+From e4a8ff817e133d84f8a82f78461e0592e5e9d9cc Mon Sep 17 00:00:00 2001
+From: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+Date: Mon, 18 Dec 2023 12:05:43 +0100
+Subject: [PATCH 06/14] cpufreq: Make sun50i h6 cpufreq Kconfig option arch
+ generic
+
+Move the Allwinner SUN50I cpufreq driver from Kconfig.arm to the
+main Kconfig file so it supports other architectures, like RISC-V
+in our case, and drop the 'ARM_' prefix.
+
+Signed-off-by: Brandon Cheo Fusi <fusibrandon13@gmail.com>
+---
+ drivers/cpufreq/Kconfig | 12 ++++++++++++
+ drivers/cpufreq/Kconfig.arm | 12 ------------
+ drivers/cpufreq/Makefile | 2 +-
+ 3 files changed, 13 insertions(+), 13 deletions(-)
+
+--- a/drivers/cpufreq/Kconfig
++++ b/drivers/cpufreq/Kconfig
+@@ -312,5 +312,17 @@ config QORIQ_CPUFREQ
+ This adds the CPUFreq driver support for Freescale QorIQ SoCs
+ which are capable of changing the CPU's frequency dynamically.
+
++config ALLWINNER_SUN50I_CPUFREQ_NVMEM
++ tristate "Allwinner nvmem based SUN50I CPUFreq driver"
++ depends on ARCH_SUNXI
++ depends on NVMEM_SUNXI_SID
++ select PM_OPP
++ help
++ This adds the nvmem based CPUFreq driver for Allwinner
++ h6/D1 SoCs.
++
++ To compile this driver as a module, choose M here: the
++ module will be called sun50i-cpufreq-nvmem.
++
+ endif
+ endmenu
+--- a/drivers/cpufreq/Kconfig.arm
++++ b/drivers/cpufreq/Kconfig.arm
+@@ -29,18 +29,6 @@ config ACPI_CPPC_CPUFREQ_FIE
+
+ If in doubt, say N.
+
+-config ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM
+- tristate "Allwinner nvmem based SUN50I CPUFreq driver"
+- depends on ARCH_SUNXI
+- depends on NVMEM_SUNXI_SID
+- select PM_OPP
+- help
+- This adds the nvmem based CPUFreq driver for Allwinner
+- h6 SoC.
+-
+- To compile this driver as a module, choose M here: the
+- module will be called sun50i-cpufreq-nvmem.
+-
+ config ARM_APPLE_SOC_CPUFREQ
+ tristate "Apple Silicon SoC CPUFreq support"
+ depends on ARCH_APPLE || (COMPILE_TEST && 64BIT)
+--- a/drivers/cpufreq/Makefile
++++ b/drivers/cpufreq/Makefile
+@@ -78,7 +78,7 @@ obj-$(CONFIG_ARM_SCMI_CPUFREQ) += scmi-
+ obj-$(CONFIG_ARM_SCPI_CPUFREQ) += scpi-cpufreq.o
+ obj-$(CONFIG_ARM_SPEAR_CPUFREQ) += spear-cpufreq.o
+ obj-$(CONFIG_ARM_STI_CPUFREQ) += sti-cpufreq.o
+-obj-$(CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM) += sun50i-cpufreq-nvmem.o
++obj-$(CONFIG_ALLWINNER_SUN50I_CPUFREQ_NVMEM) += sun50i-cpufreq-nvmem.o
+ obj-$(CONFIG_ARM_TEGRA20_CPUFREQ) += tegra20-cpufreq.o
+ obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) += tegra124-cpufreq.o
+ obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += tegra186-cpufreq.o
--- /dev/null
+From 3341f884d75929a009801d4299d219e64c64a33c Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Sat, 5 Aug 2023 21:05:01 +0300
+Subject: [PATCH 07/14] ASoC: dt-bindings: sun4i-a10-codec: Add binding for
+ Allwinner D1 SoC
+
+The Allwinner D1 SoC has a internal audio codec that similar to previous
+ones, but it contains a three ADC channels instead of two, and also has
+a separate clocks for ADC and DAC modules.
+
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+---
+ .../sound/allwinner,sun4i-a10-codec.yaml | 64 ++++++++++++++++---
+ 1 file changed, 56 insertions(+), 8 deletions(-)
+
+--- a/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml
++++ b/Documentation/devicetree/bindings/sound/allwinner,sun4i-a10-codec.yaml
+@@ -22,6 +22,7 @@ properties:
+ - allwinner,sun8i-a23-codec
+ - allwinner,sun8i-h3-codec
+ - allwinner,sun8i-v3s-codec
++ - allwinner,sun20i-d1-codec
+
+ reg:
+ maxItems: 1
+@@ -29,15 +30,9 @@ properties:
+ interrupts:
+ maxItems: 1
+
+- clocks:
+- items:
+- - description: Bus Clock
+- - description: Module Clock
++ clocks: true
+
+- clock-names:
+- items:
+- - const: apb
+- - const: codec
++ clock-names: true
+
+ dmas:
+ items:
+@@ -106,11 +101,42 @@ allOf:
+ - if:
+ properties:
+ compatible:
++ const: allwinner,sun20i-d1-codec
++ then:
++ properties:
++ clocks:
++ items:
++ - description: Bus Clock
++ - description: ADC Module Clock
++ - description: DAC Module Clock
++
++ clock-names:
++ items:
++ - const: apb
++ - const: adc
++ - const: dac
++
++ else:
++ properties:
++ clocks:
++ items:
++ - description: Bus Clock
++ - description: Module Clock
++
++ clock-names:
++ items:
++ - const: apb
++ - const: codec
++
++ - if:
++ properties:
++ compatible:
+ enum:
+ - allwinner,sun6i-a31-codec
+ - allwinner,sun8i-a23-codec
+ - allwinner,sun8i-h3-codec
+ - allwinner,sun8i-v3s-codec
++ - allwinner,sun20i-d1-codec
+
+ then:
+ if:
+@@ -225,6 +251,28 @@ allOf:
+ - Headphone
+ - Headset Mic
+ - Line In
++ - Line Out
++ - Mic
++ - Speaker
++
++ - if:
++ properties:
++ compatible:
++ enum:
++ - allwinner,sun20i-d1-codec
++
++ then:
++ properties:
++ allwinner,audio-routing:
++ items:
++ enum:
++ - HP
++ - LINEIN
++ - MIC3
++ - MBIAS
++ - Headphone
++ - Headset Mic
++ - Line In
+ - Line Out
+ - Mic
+ - Speaker
--- /dev/null
+From 64efc9cc704d27c60dc9c96a02d842f22dbdfeae Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Sat, 5 Aug 2023 21:05:02 +0300
+Subject: [PATCH 08/14] ASoC: dt-bindings: Add schema for
+ "allwinner,sun20i-d1-codec-analog"
+
+Add a DT schema to describe the analog part of the Allwinner D1/T113s
+internal audio codec.
+
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+---
+ .../allwinner,sun20i-d1-codec-analog.yaml | 33 +++++++++++++++++++
+ 1 file changed, 33 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/sound/allwinner,sun20i-d1-codec-analog.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/sound/allwinner,sun20i-d1-codec-analog.yaml
+@@ -0,0 +1,33 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/sound/allwinner,sun20i-d1-codec-analog.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Allwinner D1 Analog Codec
++
++maintainers:
++ - Maksim Kiselev <bigunclemax@gmail.com>
++
++properties:
++ compatible:
++ const: allwinner,sun20i-d1-codec-analog
++
++ reg:
++ maxItems: 1
++
++required:
++ - compatible
++ - reg
++
++additionalProperties: false
++
++examples:
++ - |
++ codec_analog: codec-analog@2030300 {
++ compatible = "allwinner,sun20i-d1-codec-analog";
++ reg = <0x02030300 0xd00>;
++ };
++
++...
++
--- /dev/null
+From 0963766bc665769aebf370d44ee3a97facfbca57 Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Sat, 5 Aug 2023 21:05:03 +0300
+Subject: [PATCH 09/14] ASoC: sunxi: sun4i-codec: add basic support for D1
+ audio codec
+
+Allwinner D1 has an audio codec similar to earlier ones, but it comes
+with 3 channel ADC instead of 2, and many registers are moved.
+
+Add basic support for it.
+
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+---
+ sound/soc/sunxi/sun4i-codec.c | 364 ++++++++++++++++++++++++++++------
+ 1 file changed, 300 insertions(+), 64 deletions(-)
+
+--- a/sound/soc/sunxi/sun4i-codec.c
++++ b/sound/soc/sunxi/sun4i-codec.c
+@@ -232,15 +232,65 @@
+
+ /* TODO H3 DAP (Digital Audio Processing) bits */
+
++/*
++ * sun20i D1 and similar codecs specific registers
++ *
++ * Almost all registers moved on D1, including ADC digital controls,
++ * FIFO and RX data registers. Only DAC control are at the same offset.
++ */
++
++#define SUN20I_D1_CODEC_DAC_VOL_CTRL (0x04)
++#define SUN20I_D1_CODEC_DAC_VOL_SEL (16)
++#define SUN20I_D1_CODEC_DAC_VOL_L (8)
++#define SUN20I_D1_CODEC_DAC_VOL_R (0)
++#define SUN20I_D1_CODEC_DAC_FIFOC (0x10)
++#define SUN20I_D1_CODEC_ADC_FIFOC (0x30)
++#define SUN20I_D1_CODEC_ADC_FIFOC_EN_AD (28)
++#define SUN20I_D1_CODEC_ADC_FIFOC_RX_SAMPLE_BITS (16)
++#define SUN20I_D1_CODEC_ADC_FIFOC_RX_TRIG_LEVEL (4)
++#define SUN20I_D1_CODEC_ADC_FIFOC_ADC_DRQ_EN (3)
++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1 (0x34)
++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC3_VOL (16)
++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC2_VOL (8)
++#define SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC1_VOL (0)
++#define SUN20I_D1_CODEC_ADC_RXDATA (0x40)
++#define SUN20I_D1_CODEC_ADC_DIG_CTRL (0x50)
++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC3_CH_EN (2)
++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC2_CH_EN (1)
++#define SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC1_CH_EN (0)
++#define SUN20I_D1_CODEC_VRA1SPEEDUP_DOWN_CTRL (0x54)
++
++/* TODO D1 DAP (Digital Audio Processing) bits */
++
++struct sun4i_codec;
++
++struct sun4i_codec_quirks {
++ const struct regmap_config *regmap_config;
++ const struct snd_soc_component_driver *codec;
++ struct snd_soc_card * (*create_card)(struct device *dev);
++ struct reg_field reg_dac_fifoc; /* used for regmap_field */
++ struct reg_field reg_adc_fifoc; /* used for regmap_field */
++ unsigned int adc_drq_en;
++ unsigned int rx_sample_bits;
++ unsigned int rx_trig_level;
++ unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */
++ unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */
++ bool has_reset;
++ bool has_dual_clock;
++};
++
+ struct sun4i_codec {
+ struct device *dev;
+ struct regmap *regmap;
+ struct clk *clk_apb;
+- struct clk *clk_module;
++ struct clk *clk_module; /* used for ADC if clocks are separate */
++ struct clk *clk_module_dac;
+ struct reset_control *rst;
+ struct gpio_desc *gpio_pa;
++ const struct sun4i_codec_quirks *quirks;
+
+- /* ADC_FIFOC register is at different offset on different SoCs */
++ /* DAC/ADC FIFOC registers are at different offset on different SoCs */
++ struct regmap_field *reg_dac_fifoc;
+ struct regmap_field *reg_adc_fifoc;
+
+ struct snd_dmaengine_dai_dma_data capture_dma_data;
+@@ -250,33 +300,33 @@ struct sun4i_codec {
+ static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
+ {
+ /* Flush TX FIFO */
+- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
++ regmap_field_set_bits(scodec->reg_dac_fifoc,
++ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
+
+ /* Enable DAC DRQ */
+- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
++ regmap_field_set_bits(scodec->reg_dac_fifoc,
++ BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
+ }
+
+ static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
+ {
+ /* Disable DAC DRQ */
+- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
++ regmap_field_clear_bits(scodec->reg_dac_fifoc,
++ BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
+ }
+
+ static void sun4i_codec_start_capture(struct sun4i_codec *scodec)
+ {
+ /* Enable ADC DRQ */
+ regmap_field_set_bits(scodec->reg_adc_fifoc,
+- BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
++ BIT(scodec->quirks->adc_drq_en));
+ }
+
+ static void sun4i_codec_stop_capture(struct sun4i_codec *scodec)
+ {
+ /* Disable ADC DRQ */
+ regmap_field_clear_bits(scodec->reg_adc_fifoc,
+- BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
++ BIT(scodec->quirks->adc_drq_en));
+ }
+
+ static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
+@@ -325,8 +375,8 @@ static int sun4i_codec_prepare_capture(s
+
+ /* Set RX FIFO trigger level */
+ regmap_field_update_bits(scodec->reg_adc_fifoc,
+- 0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+- 0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL);
++ 0xf << scodec->quirks->rx_trig_level,
++ 0x7 << scodec->quirks->rx_trig_level);
+
+ /*
+ * FIXME: Undocumented in the datasheet, but
+@@ -360,13 +410,13 @@ static int sun4i_codec_prepare_playback(
+ u32 val;
+
+ /* Flush the TX FIFO */
+- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
++ regmap_field_set_bits(scodec->reg_dac_fifoc,
++ BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
+
+ /* Set TX FIFO Empty Trigger Level */
+- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
+- 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
++ regmap_field_update_bits(scodec->reg_dac_fifoc,
++ 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
++ 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
+
+ if (substream->runtime->rate > 32000)
+ /* Use 64 bits FIR filter */
+@@ -375,13 +425,12 @@ static int sun4i_codec_prepare_playback(
+ /* Use 32 bits FIR filter */
+ val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION);
+
+- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION),
+- val);
++ regmap_field_update_bits(scodec->reg_dac_fifoc,
++ BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION), val);
+
+ /* Send zeros when we have an underrun */
+- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT));
++ regmap_field_clear_bits(scodec->reg_dac_fifoc,
++ BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT));
+
+ return 0;
+ };
+@@ -476,30 +525,32 @@ static int sun4i_codec_hw_params_capture
+ 7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS,
+ hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS);
+
+- /* Set the number of channels we want to use */
+- if (params_channels(params) == 1)
+- regmap_field_set_bits(scodec->reg_adc_fifoc,
+- BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
+- else
+- regmap_field_clear_bits(scodec->reg_adc_fifoc,
+- BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
++ if (!scodec->quirks->has_dual_clock) {
++ /* Set the number of channels we want to use */
++ if (params_channels(params) == 1)
++ regmap_field_set_bits(scodec->reg_adc_fifoc,
++ BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
++ else
++ regmap_field_clear_bits(scodec->reg_adc_fifoc,
++ BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
++ }
+
+ /* Set the number of sample bits to either 16 or 24 bits */
+ if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
+ regmap_field_set_bits(scodec->reg_adc_fifoc,
+- BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
++ BIT(scodec->quirks->rx_sample_bits));
+
+ regmap_field_clear_bits(scodec->reg_adc_fifoc,
+- BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
++ BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
+
+ scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ } else {
+ regmap_field_clear_bits(scodec->reg_adc_fifoc,
+- BIT(SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS));
++ BIT(scodec->quirks->rx_sample_bits));
+
+ /* Fill most significant bits with valid data MSB */
+ regmap_field_set_bits(scodec->reg_adc_fifoc,
+- BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
++ BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
+
+ scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ }
+@@ -514,9 +565,9 @@ static int sun4i_codec_hw_params_playbac
+ u32 val;
+
+ /* Set DAC sample rate */
+- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
+- hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
++ regmap_field_update_bits(scodec->reg_dac_fifoc,
++ 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
++ hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
+
+ /* Set the number of channels we want to use */
+ if (params_channels(params) == 1)
+@@ -524,27 +575,26 @@ static int sun4i_codec_hw_params_playbac
+ else
+ val = 0;
+
+- regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN),
+- val);
++ regmap_field_update_bits(scodec->reg_dac_fifoc,
++ BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN), val);
+
+ /* Set the number of sample bits to either 16 or 24 bits */
+ if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
+- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
++ regmap_field_set_bits(scodec->reg_dac_fifoc,
++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
+
+ /* Set TX FIFO mode to padding the LSBs with 0 */
+- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
++ regmap_field_clear_bits(scodec->reg_dac_fifoc,
++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
+
+ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+ } else {
+- regmap_clear_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
++ regmap_field_clear_bits(scodec->reg_dac_fifoc,
++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
+
+ /* Set TX FIFO mode to repeat the MSB */
+- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
++ regmap_field_set_bits(scodec->reg_dac_fifoc,
++ BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
+
+ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+ }
+@@ -565,7 +615,11 @@ static int sun4i_codec_hw_params(struct
+ if (!clk_freq)
+ return -EINVAL;
+
+- ret = clk_set_rate(scodec->clk_module, clk_freq);
++ if (scodec->clk_module_dac &&
++ substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ ret = clk_set_rate(scodec->clk_module_dac, clk_freq);
++ else
++ ret = clk_set_rate(scodec->clk_module, clk_freq);
+ if (ret)
+ return ret;
+
+@@ -607,10 +661,14 @@ static int sun4i_codec_startup(struct sn
+ * Stop issuing DRQ when we have room for less than 16 samples
+ * in our TX FIFO
+ */
+- regmap_set_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
+- 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
++ regmap_field_set_bits(scodec->reg_dac_fifoc,
++ 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
+
+- return clk_prepare_enable(scodec->clk_module);
++ if (scodec->clk_module_dac &&
++ substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ return clk_prepare_enable(scodec->clk_module_dac);
++ else
++ return clk_prepare_enable(scodec->clk_module);
+ }
+
+ static void sun4i_codec_shutdown(struct snd_pcm_substream *substream,
+@@ -619,7 +677,11 @@ static void sun4i_codec_shutdown(struct
+ struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
+ struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
+
+- clk_disable_unprepare(scodec->clk_module);
++ if (scodec->clk_module_dac &&
++ substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
++ clk_disable_unprepare(scodec->clk_module_dac);
++ else
++ clk_disable_unprepare(scodec->clk_module);
+ }
+
+ static const struct snd_soc_dai_ops sun4i_codec_dai_ops = {
+@@ -1229,6 +1291,55 @@ static const struct snd_soc_component_dr
+ .endianness = 1,
+ };
+
++/* sun20i D1 codec */
++static const DECLARE_TLV_DB_SCALE(sun20i_d1_codec_dvol_scale, -12000, 75, 1);
++
++static const struct snd_kcontrol_new sun20i_d1_codec_codec_controls[] = {
++ SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
++ SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
++ sun6i_codec_dvol_scale),
++ SOC_DOUBLE_TLV("DAC Front Playback Volume", SUN20I_D1_CODEC_DAC_VOL_CTRL,
++ SUN20I_D1_CODEC_DAC_VOL_L, SUN20I_D1_CODEC_DAC_VOL_R,
++ 0xFF, 0, sun20i_d1_codec_dvol_scale),
++
++ SOC_SINGLE_TLV("ADC1 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1,
++ SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC1_VOL, 0xff, 0,
++ sun20i_d1_codec_dvol_scale),
++ SOC_SINGLE_TLV("ADC2 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1,
++ SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC2_VOL, 0xff, 0,
++ sun20i_d1_codec_dvol_scale),
++ SOC_SINGLE_TLV("ADC3 Capture Volume", SUN20I_D1_CODEC_ADC_VOL_CTRL1,
++ SUN20I_D1_CODEC_ADC_VOL_CTRL1_ADC3_VOL, 0xff, 0,
++ sun20i_d1_codec_dvol_scale),
++};
++
++static const struct snd_soc_dapm_widget sun20i_d1_codec_codec_widgets[] = {
++ /* Digital parts of the ADCs */
++ SND_SOC_DAPM_SUPPLY("ADC Enable", SUN20I_D1_CODEC_ADC_FIFOC,
++ SUN20I_D1_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0),
++ SND_SOC_DAPM_SUPPLY("ADC1 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL,
++ SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC1_CH_EN, 0, NULL, 0),
++ SND_SOC_DAPM_SUPPLY("ADC2 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL,
++ SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC2_CH_EN, 0, NULL, 0),
++ SND_SOC_DAPM_SUPPLY("ADC3 CH Enable", SUN20I_D1_CODEC_ADC_DIG_CTRL,
++ SUN20I_D1_CODEC_ADC_DIG_CTRL_ADC3_CH_EN, 0, NULL, 0),
++ /* Digital parts of the DACs */
++ SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
++ SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0),
++ SND_SOC_DAPM_SUPPLY("DAC VOL_SEL Enable", SUN20I_D1_CODEC_DAC_VOL_CTRL,
++ SUN20I_D1_CODEC_DAC_VOL_SEL, 0, NULL, 0),
++};
++
++static const struct snd_soc_component_driver sun20i_d1_codec_codec = {
++ .controls = sun20i_d1_codec_codec_controls,
++ .num_controls = ARRAY_SIZE(sun20i_d1_codec_codec_controls),
++ .dapm_widgets = sun20i_d1_codec_codec_widgets,
++ .num_dapm_widgets = ARRAY_SIZE(sun20i_d1_codec_codec_widgets),
++ .idle_bias_on = 1,
++ .use_pmdown_time = 1,
++ .endianness = 1,
++};
++
+ static const struct snd_soc_component_driver sun4i_codec_component = {
+ .name = "sun4i-codec",
+ .legacy_dai_naming = 1,
+@@ -1532,6 +1643,66 @@ static struct snd_soc_card *sun8i_v3s_co
+ return card;
+ };
+
++static const struct snd_soc_dapm_route sun20i_d1_codec_card_routes[] = {
++ /* ADC Routes */
++ { "ADC1", NULL, "ADC Enable" },
++ { "ADC2", NULL, "ADC Enable" },
++ { "ADC3", NULL, "ADC Enable" },
++ { "ADC1", NULL, "ADC1 CH Enable" },
++ { "ADC2", NULL, "ADC2 CH Enable" },
++ { "ADC3", NULL, "ADC3 CH Enable" },
++ { "Codec Capture", NULL, "ADC1" },
++ { "Codec Capture", NULL, "ADC2" },
++ { "Codec Capture", NULL, "ADC3" },
++
++ /* DAC Routes */
++ { "Left DAC", NULL, "DAC Enable" },
++ { "Right DAC", NULL, "DAC Enable" },
++ { "Left DAC", NULL, "DAC VOL_SEL Enable" },
++ { "Right DAC", NULL, "DAC VOL_SEL Enable" },
++ { "Left DAC", NULL, "Codec Playback" },
++ { "Right DAC", NULL, "Codec Playback" },
++};
++
++static struct snd_soc_card *sun20i_d1_codec_create_card(struct device *dev)
++{
++ struct snd_soc_card *card;
++ int ret;
++
++ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
++ if (!card)
++ return ERR_PTR(-ENOMEM);
++
++ aux_dev.dlc.of_node = of_parse_phandle(dev->of_node,
++ "allwinner,codec-analog-controls",
++ 0);
++ if (!aux_dev.dlc.of_node) {
++ dev_err(dev, "Can't find analog controls for codec.\n");
++ return ERR_PTR(-EINVAL);
++ }
++
++ card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
++ if (!card->dai_link)
++ return ERR_PTR(-ENOMEM);
++
++ card->dev = dev;
++ card->owner = THIS_MODULE;
++ card->name = "D1 Audio Codec";
++ card->dapm_widgets = sun6i_codec_card_dapm_widgets;
++ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
++ card->dapm_routes = sun20i_d1_codec_card_routes;
++ card->num_dapm_routes = ARRAY_SIZE(sun20i_d1_codec_card_routes);
++ card->aux_dev = &aux_dev;
++ card->num_aux_devs = 1;
++ card->fully_routed = true;
++
++ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
++ if (ret)
++ dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
++
++ return card;
++};
++
+ static const struct regmap_config sun4i_codec_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+@@ -1574,21 +1745,22 @@ static const struct regmap_config sun8i_
+ .max_register = SUN8I_H3_CODEC_ADC_DBG,
+ };
+
+-struct sun4i_codec_quirks {
+- const struct regmap_config *regmap_config;
+- const struct snd_soc_component_driver *codec;
+- struct snd_soc_card * (*create_card)(struct device *dev);
+- struct reg_field reg_adc_fifoc; /* used for regmap_field */
+- unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */
+- unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */
+- bool has_reset;
++static const struct regmap_config sun20i_d1_codec_regmap_config = {
++ .reg_bits = 32,
++ .reg_stride = 4,
++ .val_bits = 32,
++ .max_register = SUN20I_D1_CODEC_VRA1SPEEDUP_DOWN_CTRL,
+ };
+
+ static const struct sun4i_codec_quirks sun4i_codec_quirks = {
+ .regmap_config = &sun4i_codec_regmap_config,
+ .codec = &sun4i_codec_codec,
+ .create_card = sun4i_codec_create_card,
++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
+ };
+@@ -1597,7 +1769,11 @@ static const struct sun4i_codec_quirks s
+ .regmap_config = &sun6i_codec_regmap_config,
+ .codec = &sun6i_codec_codec,
+ .create_card = sun6i_codec_create_card,
++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
+ .has_reset = true,
+@@ -1607,7 +1783,11 @@ static const struct sun4i_codec_quirks s
+ .regmap_config = &sun7i_codec_regmap_config,
+ .codec = &sun7i_codec_codec,
+ .create_card = sun4i_codec_create_card,
++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
+ };
+@@ -1616,7 +1796,11 @@ static const struct sun4i_codec_quirks s
+ .regmap_config = &sun8i_a23_codec_regmap_config,
+ .codec = &sun8i_a23_codec_codec,
+ .create_card = sun8i_a23_codec_create_card,
++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
+ .has_reset = true,
+@@ -1631,7 +1815,11 @@ static const struct sun4i_codec_quirks s
+ */
+ .codec = &sun8i_a23_codec_codec,
+ .create_card = sun8i_h3_codec_create_card,
++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
+ .has_reset = true,
+@@ -1645,12 +1833,31 @@ static const struct sun4i_codec_quirks s
+ */
+ .codec = &sun8i_a23_codec_codec,
+ .create_card = sun8i_v3s_codec_create_card,
++ .reg_dac_fifoc = REG_FIELD(SUN4I_CODEC_DAC_FIFOC, 0, 31),
+ .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
++ .adc_drq_en = SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++ .rx_sample_bits = SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++ .rx_trig_level = SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
+ .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
+ .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
+ .has_reset = true,
+ };
+
++static const struct sun4i_codec_quirks sun20i_d1_codec_quirks = {
++ .regmap_config = &sun20i_d1_codec_regmap_config,
++ .codec = &sun20i_d1_codec_codec,
++ .create_card = sun20i_d1_codec_create_card,
++ .reg_dac_fifoc = REG_FIELD(SUN20I_D1_CODEC_DAC_FIFOC, 0, 31),
++ .reg_adc_fifoc = REG_FIELD(SUN20I_D1_CODEC_ADC_FIFOC, 0, 31),
++ .adc_drq_en = SUN20I_D1_CODEC_ADC_FIFOC_ADC_DRQ_EN,
++ .rx_sample_bits = SUN20I_D1_CODEC_ADC_FIFOC_RX_SAMPLE_BITS,
++ .rx_trig_level = SUN20I_D1_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
++ .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
++ .reg_adc_rxdata = SUN20I_D1_CODEC_ADC_RXDATA,
++ .has_reset = true,
++ .has_dual_clock = true,
++};
++
+ static const struct of_device_id sun4i_codec_of_match[] = {
+ {
+ .compatible = "allwinner,sun4i-a10-codec",
+@@ -1676,6 +1883,10 @@ static const struct of_device_id sun4i_c
+ .compatible = "allwinner,sun8i-v3s-codec",
+ .data = &sun8i_v3s_codec_quirks,
+ },
++ {
++ .compatible = "allwinner,sun20i-d1-codec",
++ .data = &sun20i_d1_codec_quirks,
++ },
+ {}
+ };
+ MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
+@@ -1704,6 +1915,7 @@ static int sun4i_codec_probe(struct plat
+ dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
+ return -ENODEV;
+ }
++ scodec->quirks = quirks;
+
+ scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+ quirks->regmap_config);
+@@ -1719,10 +1931,24 @@ static int sun4i_codec_probe(struct plat
+ return PTR_ERR(scodec->clk_apb);
+ }
+
+- scodec->clk_module = devm_clk_get(&pdev->dev, "codec");
+- if (IS_ERR(scodec->clk_module)) {
+- dev_err(&pdev->dev, "Failed to get the module clock\n");
+- return PTR_ERR(scodec->clk_module);
++ if (quirks->has_dual_clock) {
++ scodec->clk_module = devm_clk_get(&pdev->dev, "adc");
++ if (IS_ERR(scodec->clk_module)) {
++ dev_err(&pdev->dev, "Failed to get the ADC module clock\n");
++ return PTR_ERR(scodec->clk_module);
++ }
++
++ scodec->clk_module_dac = devm_clk_get(&pdev->dev, "dac");
++ if (IS_ERR(scodec->clk_module_dac)) {
++ dev_err(&pdev->dev, "Failed to get the DAC module clock\n");
++ return PTR_ERR(scodec->clk_module_dac);
++ }
++ } else {
++ scodec->clk_module = devm_clk_get(&pdev->dev, "codec");
++ if (IS_ERR(scodec->clk_module)) {
++ dev_err(&pdev->dev, "Failed to get the module clock\n");
++ return PTR_ERR(scodec->clk_module);
++ }
+ }
+
+ if (quirks->has_reset) {
+@@ -1751,6 +1977,16 @@ static int sun4i_codec_probe(struct plat
+ dev_err(&pdev->dev, "Failed to create regmap fields: %d\n",
+ ret);
+ return ret;
++ }
++
++ scodec->reg_dac_fifoc = devm_regmap_field_alloc(&pdev->dev,
++ scodec->regmap,
++ quirks->reg_dac_fifoc);
++ if (IS_ERR(scodec->reg_dac_fifoc)) {
++ ret = PTR_ERR(scodec->reg_dac_fifoc);
++ dev_err(&pdev->dev, "Failed to create regmap fields: %d\n",
++ ret);
++ return ret;
+ }
+
+ /* Enable the bus clock */
--- /dev/null
+From c8c3c516ca5c38e7858055ce0137efde17a07190 Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Sat, 5 Aug 2023 21:05:04 +0300
+Subject: [PATCH 10/14] ASoC: sunxi: Add new driver for Allwinner D1/T113s
+ codec's analog path controls
+
+The internal codec on D1/T113s is split into 2 parts like the previous
+ones. But now analog path controls registers are mapped directly
+on the bus, right after the registers of the digital part.
+
+Add an ASoC component driver for it. This should be tied to the codec
+audio card as an auxiliary device.
+
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+---
+ sound/soc/sunxi/Kconfig | 11 ++
+ sound/soc/sunxi/Makefile | 1 +
+ sound/soc/sunxi/sun20i-d1-codec-analog.c | 220 +++++++++++++++++++++++
+ 3 files changed, 232 insertions(+)
+ create mode 100644 sound/soc/sunxi/sun20i-d1-codec-analog.c
+
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -38,6 +38,17 @@ config SND_SUN50I_CODEC_ANALOG
+ Say Y or M if you want to add support for the analog controls for
+ the codec embedded in Allwinner A64 SoC.
+
++config SND_SUN20I_D1_CODEC_ANALOG
++ tristate "Allwinner D1 Codec Analog Controls Support"
++ depends on ARCH_SUNXI || COMPILE_TEST
++ select REGMAP_MMIO
++ help
++ This option enables the analog controls part of the internal audio
++ codec for Allwinner D1/T113s SoCs family.
++
++ Say Y or M if you want to add support for the analog part of
++ the D1/T113s audio codec.
++
+ config SND_SUN4I_I2S
+ tristate "Allwinner A10 I2S Support"
+ select SND_SOC_GENERIC_DMAENGINE_PCM
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -4,6 +4,7 @@ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s
+ obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
+ obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
+ obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
++obj-$(CONFIG_SND_SUN20I_D1_CODEC_ANALOG) += sun20i-d1-codec-analog.o
+ obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
+ obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o
+ obj-$(CONFIG_SND_SUN50I_DMIC) += sun50i-dmic.o
+--- /dev/null
++++ b/sound/soc/sunxi/sun20i-d1-codec-analog.c
+@@ -0,0 +1,220 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * This driver supports the analog controls for the internal codec
++ * found in Allwinner's D1/T113s SoCs family.
++ *
++ * Based on sun50i-codec-analog.c
++ */
++
++#include <linux/io.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++
++#include <sound/soc.h>
++#include <sound/soc-dapm.h>
++#include <sound/tlv.h>
++
++/* Codec analog control register offsets and bit fields */
++#define SUN20I_D1_ADDA_ADC1 (0x00)
++#define SUN20I_D1_ADDA_ADC2 (0x04)
++#define SUN20I_D1_ADDA_ADC3 (0x08)
++#define SUN20I_D1_ADDA_ADC_EN (31)
++#define SUN20I_D1_ADDA_ADC_PGA_EN (30)
++#define SUN20I_D1_ADDA_ADC_MIC_SIN_EN (28)
++#define SUN20I_D1_ADDA_ADC_LINEINLEN (23)
++#define SUN20I_D1_ADDA_ADC_PGA_GAIN (8)
++
++#define SUN20I_D1_ADDA_DAC (0x10)
++#define SUN20I_D1_ADDA_DAC_DACL_EN (15)
++#define SUN20I_D1_ADDA_DAC_DACR_EN (14)
++
++#define SUN20I_D1_ADDA_MICBIAS (0x18)
++#define SUN20I_D1_ADDA_MICBIAS_MMICBIASEN (7)
++
++#define SUN20I_D1_ADDA_RAMP (0x1C)
++#define SUN20I_D1_ADDA_RAMP_RD_EN (0)
++
++#define SUN20I_D1_ADDA_HP2 (0x40)
++#define SUN20I_D1_ADDA_HP2_HEADPHONE_GAIN (28)
++
++#define SUN20I_D1_ADDA_ADC_CUR_REG (0x4C)
++
++static const DECLARE_TLV_DB_RANGE(sun20i_d1_codec_adc_gain_scale,
++ 0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
++ 1, 3, TLV_DB_SCALE_ITEM(600, 0, 0),
++ 4, 4, TLV_DB_SCALE_ITEM(900, 0, 0),
++ 5, 31, TLV_DB_SCALE_ITEM(1000, 100, 0),
++);
++
++static const DECLARE_TLV_DB_SCALE(sun20i_d1_codec_hp_vol_scale, -4200, 600, 0);
++
++/* volume controls */
++static const struct snd_kcontrol_new sun20i_d1_codec_controls[] = {
++ SOC_SINGLE_TLV("Headphone Playback Volume",
++ SUN20I_D1_ADDA_HP2,
++ SUN20I_D1_ADDA_HP2_HEADPHONE_GAIN, 0x7, 1,
++ sun20i_d1_codec_hp_vol_scale),
++ SOC_SINGLE_TLV("ADC1 Gain Capture Volume",
++ SUN20I_D1_ADDA_ADC1,
++ SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0,
++ sun20i_d1_codec_adc_gain_scale),
++ SOC_SINGLE_TLV("ADC2 Gain Capture Volume",
++ SUN20I_D1_ADDA_ADC2,
++ SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0,
++ sun20i_d1_codec_adc_gain_scale),
++ SOC_SINGLE_TLV("ADC3 Gain Capture Volume",
++ SUN20I_D1_ADDA_ADC3,
++ SUN20I_D1_ADDA_ADC_PGA_GAIN, 0x1f, 0,
++ sun20i_d1_codec_adc_gain_scale),
++};
++
++/* ADC mixer controls */
++static const struct snd_kcontrol_new sun20i_d1_codec_mixer_controls[] = {
++ SOC_DAPM_DOUBLE_R("Line In Switch",
++ SUN20I_D1_ADDA_ADC1,
++ SUN20I_D1_ADDA_ADC2,
++ SUN20I_D1_ADDA_ADC_LINEINLEN, 1, 0),
++};
++
++static const char * const sun20i_d1_codec_mic3_src_enum_text[] = {
++ "Differential", "Single",
++};
++
++static SOC_ENUM_SINGLE_DECL(sun20i_d1_codec_mic3_src_enum,
++ SUN20I_D1_ADDA_ADC3,
++ SUN20I_D1_ADDA_ADC_MIC_SIN_EN,
++ sun20i_d1_codec_mic3_src_enum_text);
++
++static const struct snd_kcontrol_new sun20i_d1_codec_mic3_input_src[] = {
++ SOC_DAPM_ENUM("MIC3 Source Capture Route",
++ sun20i_d1_codec_mic3_src_enum),
++};
++
++static const struct snd_soc_dapm_widget sun20i_d1_codec_widgets[] = {
++ /* DAC */
++ SND_SOC_DAPM_DAC("Left DAC", NULL, SUN20I_D1_ADDA_DAC,
++ SUN20I_D1_ADDA_DAC_DACL_EN, 0),
++ SND_SOC_DAPM_DAC("Right DAC", NULL, SUN20I_D1_ADDA_DAC,
++ SUN20I_D1_ADDA_DAC_DACR_EN, 0),
++ /* ADC */
++ SND_SOC_DAPM_ADC("ADC1", NULL, SUN20I_D1_ADDA_ADC1,
++ SUN20I_D1_ADDA_ADC_EN, 0),
++ SND_SOC_DAPM_ADC("ADC2", NULL, SUN20I_D1_ADDA_ADC2,
++ SUN20I_D1_ADDA_ADC_EN, 0),
++ SND_SOC_DAPM_ADC("ADC3", NULL, SUN20I_D1_ADDA_ADC3,
++ SUN20I_D1_ADDA_ADC_EN, 0),
++
++ /* ADC Mixers */
++ SND_SOC_DAPM_MIXER("ADC1 Mixer", SND_SOC_NOPM, 0, 0,
++ sun20i_d1_codec_mixer_controls,
++ ARRAY_SIZE(sun20i_d1_codec_mixer_controls)),
++ SND_SOC_DAPM_MIXER("ADC2 Mixer", SND_SOC_NOPM, 0, 0,
++ sun20i_d1_codec_mixer_controls,
++ ARRAY_SIZE(sun20i_d1_codec_mixer_controls)),
++
++ /* Headphone */
++ SND_SOC_DAPM_OUTPUT("HP"),
++ SND_SOC_DAPM_SUPPLY("RAMP Enable", SUN20I_D1_ADDA_RAMP,
++ SUN20I_D1_ADDA_RAMP_RD_EN, 0, NULL, 0),
++
++ /* Line input */
++ SND_SOC_DAPM_INPUT("LINEIN"),
++
++ /* Microphone input */
++ SND_SOC_DAPM_INPUT("MIC3"),
++
++ /* Microphone input path */
++ SND_SOC_DAPM_MUX("MIC3 Source Capture Route", SND_SOC_NOPM, 0, 0,
++ sun20i_d1_codec_mic3_input_src),
++
++ SND_SOC_DAPM_PGA("Mic3 Amplifier", SUN20I_D1_ADDA_ADC3,
++ SUN20I_D1_ADDA_ADC_PGA_EN, 0, NULL, 0),
++
++ /* Microphone Bias */
++ SND_SOC_DAPM_SUPPLY("MBIAS", SUN20I_D1_ADDA_MICBIAS,
++ SUN20I_D1_ADDA_MICBIAS_MMICBIASEN, 0, NULL, 0),
++};
++
++static const struct snd_soc_dapm_route sun20i_d1_codec_routes[] = {
++ /* Headphone Routes */
++ { "HP", NULL, "Left DAC" },
++ { "HP", NULL, "Right DAC" },
++ { "HP", NULL, "RAMP Enable" },
++
++ /* Line input Routes */
++ { "ADC1", NULL, "ADC1 Mixer" },
++ { "ADC2", NULL, "ADC2 Mixer" },
++ { "ADC1 Mixer", "Line In Switch", "LINEIN" },
++ { "ADC2 Mixer", "Line In Switch", "LINEIN" },
++
++ /* Microphone Routes */
++ { "MIC3 Source Capture Route", "Differential", "MIC3" },
++ { "MIC3 Source Capture Route", "Single", "MIC3" },
++ { "Mic3 Amplifier", NULL, "MIC3 Source Capture Route" },
++ { "ADC3", NULL, "Mic3 Amplifier" },
++};
++
++static const struct snd_soc_component_driver sun20i_d1_codec_analog_cmpnt_drv = {
++ .controls = sun20i_d1_codec_controls,
++ .num_controls = ARRAY_SIZE(sun20i_d1_codec_controls),
++ .dapm_widgets = sun20i_d1_codec_widgets,
++ .num_dapm_widgets = ARRAY_SIZE(sun20i_d1_codec_widgets),
++ .dapm_routes = sun20i_d1_codec_routes,
++ .num_dapm_routes = ARRAY_SIZE(sun20i_d1_codec_routes),
++};
++
++static const struct of_device_id sun20i_d1_codec_analog_of_match[] = {
++ {
++ .compatible = "allwinner,sun20i-d1-codec-analog",
++ },
++ {}
++};
++MODULE_DEVICE_TABLE(of, sun20i_d1_codec_analog_of_match);
++
++static const struct regmap_config sun20i_d1_codec_regmap_config = {
++ .reg_bits = 32,
++ .reg_stride = 4,
++ .val_bits = 32,
++ .max_register = SUN20I_D1_ADDA_ADC_CUR_REG,
++};
++
++static int sun20i_d1_codec_analog_probe(struct platform_device *pdev)
++{
++ struct regmap *regmap;
++ void __iomem *base;
++
++ base = devm_platform_ioremap_resource(pdev, 0);
++ if (IS_ERR(base)) {
++ dev_err(&pdev->dev, "Failed to map the registers\n");
++ return PTR_ERR(base);
++ }
++
++ regmap = devm_regmap_init_mmio(&pdev->dev, base,
++ &sun20i_d1_codec_regmap_config);
++ if (IS_ERR(regmap)) {
++ dev_err(&pdev->dev, "Failed to create regmap\n");
++ return PTR_ERR(regmap);
++ }
++
++ return devm_snd_soc_register_component(&pdev->dev,
++ &sun20i_d1_codec_analog_cmpnt_drv,
++ NULL, 0);
++}
++
++static struct platform_driver sun20i_d1_codec_analog_driver = {
++ .driver = {
++ .name = "sun20i-d1-codec-analog",
++ .of_match_table = sun20i_d1_codec_analog_of_match,
++ },
++ .probe = sun20i_d1_codec_analog_probe,
++};
++module_platform_driver(sun20i_d1_codec_analog_driver);
++
++MODULE_DESCRIPTION("Allwinner internal codec analog controls driver for D1");
++MODULE_AUTHOR("Maksim Kiselev <bigunclemax@gmail.com>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:sun20i-d1-codec-analog");
--- /dev/null
+From 16728b748a44f1cea060a6ba57453c03e3745c1d Mon Sep 17 00:00:00 2001
+From: Maxim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 18 Dec 2023 00:06:22 +0300
+Subject: [PATCH 11/14] dt-bindings: thermal: sun8i: Add binding for D1/T113s
+ THS controller
+
+Add a binding for D1/T113s thermal sensor controller.
+
+Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+---
+ .../bindings/thermal/allwinner,sun8i-a83t-ths.yaml | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
++++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
+@@ -16,6 +16,7 @@ properties:
+ - allwinner,sun8i-a83t-ths
+ - allwinner,sun8i-h3-ths
+ - allwinner,sun8i-r40-ths
++ - allwinner,sun20i-d1-ths
+ - allwinner,sun50i-a64-ths
+ - allwinner,sun50i-a100-ths
+ - allwinner,sun50i-h5-ths
+@@ -61,6 +62,7 @@ allOf:
+ compatible:
+ contains:
+ enum:
++ - allwinner,sun20i-d1-ths
+ - allwinner,sun50i-a100-ths
+ - allwinner,sun50i-h6-ths
+
+@@ -84,7 +86,9 @@ allOf:
+ properties:
+ compatible:
+ contains:
+- const: allwinner,sun8i-h3-ths
++ enum:
++ - allwinner,sun8i-h3-ths
++ - allwinner,sun20i-d1-ths
+
+ then:
+ properties:
+@@ -103,6 +107,7 @@ allOf:
+ enum:
+ - allwinner,sun8i-h3-ths
+ - allwinner,sun8i-r40-ths
++ - allwinner,sun20i-d1-ths
+ - allwinner,sun50i-a64-ths
+ - allwinner,sun50i-a100-ths
+ - allwinner,sun50i-h5-ths
--- /dev/null
+From eb7e78f9e4bb9133898875afb0e0b9f09663e802 Mon Sep 17 00:00:00 2001
+From: Maxim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 18 Dec 2023 00:06:23 +0300
+Subject: [PATCH 12/14] thermal: sun8i: Add D1/T113s THS controller support
+
+This patch adds a thermal sensor controller support for the D1/T113s,
+which is similar to the one on H6, but with only one sensor and
+different scale and offset values.
+
+Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/thermal/sun8i_thermal.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -606,6 +606,18 @@ static const struct ths_thermal_chip sun
+ .calc_temp = sun8i_ths_calc_temp,
+ };
+
++static const struct ths_thermal_chip sun20i_d1_ths = {
++ .sensor_num = 1,
++ .has_bus_clk_reset = true,
++ .offset = 188552,
++ .scale = 673,
++ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
++ .calibrate = sun50i_h6_ths_calibrate,
++ .init = sun50i_h6_thermal_init,
++ .irq_ack = sun50i_h6_irq_ack,
++ .calc_temp = sun8i_ths_calc_temp,
++};
++
+ static const struct of_device_id of_ths_match[] = {
+ { .compatible = "allwinner,sun8i-a83t-ths", .data = &sun8i_a83t_ths },
+ { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+@@ -614,6 +626,7 @@ static const struct of_device_id of_ths_
+ { .compatible = "allwinner,sun50i-a100-ths", .data = &sun50i_a100_ths },
+ { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
+ { .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
++ { .compatible = "allwinner,sun20i-d1-ths", .data = &sun20i_d1_ths },
+ { /* sentinel */ },
+ };
+ MODULE_DEVICE_TABLE(of, of_ths_match);
--- /dev/null
+From 196423a17b92ef241766691b42dac0136342bdb5 Mon Sep 17 00:00:00 2001
+From: Maxim Kiselev <bigunclemax@gmail.com>
+Date: Mon, 18 Dec 2023 00:06:24 +0300
+Subject: [PATCH 13/14] riscv: dts: allwinner: d1: Add thermal sensor
+
+This patch adds a thermal sensor controller node for the D1/T113s.
+Also it adds a THS calibration data cell to efuse node.
+
+Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+---
+ .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+@@ -166,6 +166,19 @@
+ #io-channel-cells = <1>;
+ };
+
++ ths: thermal-sensor@2009400 {
++ compatible = "allwinner,sun20i-d1-ths";
++ reg = <0x02009400 0x400>;
++ interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_THS>;
++ clock-names = "bus";
++ resets = <&ccu RST_BUS_THS>;
++ nvmem-cells = <&ths_calibration>;
++ nvmem-cell-names = "calibration";
++ status = "disabled";
++ #thermal-sensor-cells = <0>;
++ };
++
+ dmic: dmic@2031000 {
+ compatible = "allwinner,sun20i-d1-dmic",
+ "allwinner,sun50i-h6-dmic";
+@@ -415,6 +428,10 @@
+ reg = <0x3006000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
++
++ ths_calibration: thermal-sensor-calibration@14 {
++ reg = <0x14 0x4>;
++ };
+ };
+
+ crypto: crypto@3040000 {
--- /dev/null
+From edebcc9d47f0bfe9bd769a2c578dda16acbfbef2 Mon Sep 17 00:00:00 2001
+From: Maksim Kiselev <bigunclemax@gmail.com>
+Date: Sat, 5 Aug 2023 21:05:05 +0300
+Subject: [PATCH 14/14] riscv: dts: allwinner: d1: Add device nodes for
+ internal audio codec
+
+Add DT nodes for the internal D1/T113s audio codec and its analog part.
+
+Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
+---
+ .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 22 +++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
++++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+@@ -179,6 +179,28 @@
+ #thermal-sensor-cells = <0>;
+ };
+
++ codec: codec@2030000 {
++ #sound-dai-cells = <0>;
++ compatible = "allwinner,sun20i-d1-codec";
++ reg = <0x02030000 0x300>;
++ interrupts = <SOC_PERIPHERAL_IRQ(25) IRQ_TYPE_LEVEL_HIGH>;
++ clocks = <&ccu CLK_BUS_AUDIO>,
++ <&ccu CLK_AUDIO_ADC>,
++ <&ccu CLK_AUDIO_DAC>;
++ clock-names = "apb", "adc", "dac";
++ resets = <&ccu RST_BUS_AUDIO>;
++ dmas = <&dma 7>, <&dma 7>;
++ dma-names = "rx", "tx";
++ allwinner,codec-analog-controls = <&codec_analog>;
++ status = "disabled";
++ };
++
++ codec_analog: codec-analog@2030300 {
++ compatible = "allwinner,sun20i-d1-codec-analog";
++ reg = <0x02030300 0xd00>;
++ status = "disabled";
++ };
++
+ dmic: dmic@2031000 {
+ compatible = "allwinner,sun20i-d1-dmic",
+ "allwinner,sun50i-h6-dmic";
--- /dev/null
+From 81889eb2b37bc21df4ff259441e8fc12d4f27cd9 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 9 May 2024 08:48:31 +0200
+Subject: [PATCH] net: ethernet: cortina: Locking fixes
+
+This fixes a probably long standing problem in the Cortina
+Gemini ethernet driver: there are some paths in the code
+where the IRQ registers are written without taking the proper
+locks.
+
+Fixes: 4d5ae32f5e1e ("net: ethernet: Add a driver for Gemini gigabit ethernet")
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 12 ++++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -1107,10 +1107,13 @@ static void gmac_tx_irq_enable(struct ne
+ {
+ struct gemini_ethernet_port *port = netdev_priv(netdev);
+ struct gemini_ethernet *geth = port->geth;
++ unsigned long flags;
+ u32 val, mask;
+
+ netdev_dbg(netdev, "%s device %d\n", __func__, netdev->dev_id);
+
++ spin_lock_irqsave(&geth->irq_lock, flags);
++
+ mask = GMAC0_IRQ0_TXQ0_INTS << (6 * netdev->dev_id + txq);
+
+ if (en)
+@@ -1119,6 +1122,8 @@ static void gmac_tx_irq_enable(struct ne
+ val = readl(geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
+ val = en ? val | mask : val & ~mask;
+ writel(val, geth->base + GLOBAL_INTERRUPT_ENABLE_0_REG);
++
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
+ }
+
+ static void gmac_tx_irq(struct net_device *netdev, unsigned int txq_num)
+@@ -1415,15 +1420,19 @@ static unsigned int gmac_rx(struct net_d
+ union gmac_rxdesc_3 word3;
+ struct page *page = NULL;
+ unsigned int page_offs;
++ unsigned long flags;
+ unsigned short r, w;
+ union dma_rwptr rw;
+ dma_addr_t mapping;
+ int frag_nr = 0;
+
++ spin_lock_irqsave(&geth->irq_lock, flags);
+ rw.bits32 = readl(ptr_reg);
+ /* Reset interrupt as all packages until here are taken into account */
+ writel(DEFAULT_Q0_INT_BIT << netdev->dev_id,
+ geth->base + GLOBAL_INTERRUPT_STATUS_1_REG);
++ spin_unlock_irqrestore(&geth->irq_lock, flags);
++
+ r = rw.bits.rptr;
+ w = rw.bits.wptr;
+
+@@ -1726,10 +1735,9 @@ static irqreturn_t gmac_irq(int irq, voi
+ gmac_update_hw_stats(netdev);
+
+ if (val & (GMAC0_RX_OVERRUN_INT_BIT << (netdev->dev_id * 8))) {
++ spin_lock(&geth->irq_lock);
+ writel(GMAC0_RXDERR_INT_BIT << (netdev->dev_id * 8),
+ geth->base + GLOBAL_INTERRUPT_STATUS_4_REG);
+-
+- spin_lock(&geth->irq_lock);
+ u64_stats_update_begin(&port->ir_stats_syncp);
+ ++port->stats.rx_fifo_errors;
+ u64_stats_update_end(&port->ir_stats_syncp);
--- /dev/null
+From 30fcba19ed88997a2909e4a68b4d39ff371357c3 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Wed, 1 May 2024 21:46:31 +0200
+Subject: [PATCH 1/5] net: ethernet: cortina: Restore TSO support
+
+An earlier commit deleted the TSO support in the Cortina Gemini
+driver because the driver was confusing gso_size and MTU,
+probably because what the Linux kernel calls "gso_size" was
+called "MTU" in the datasheet.
+
+Restore the functionality properly reading the gso_size from
+the skbuff.
+
+Tested with iperf3, running a server on a different machine
+and client on the device with the cortina gemini ethernet:
+
+Connecting to host 192.168.1.2, port 5201
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=1c8a
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=1c8a
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=27da
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=0b92
+60008000.ethernet-port eth0: segment offloading mss = 05ea len=2bda
+(...)
+
+(The hardware MSS 0x05ea here includes the ethernet headers.)
+
+If I disable all segment offloading on the receiving host and
+dump packets using tcpdump -xx like this:
+
+ethtool -K enp2s0 gro off gso off tso off
+tcpdump -xx -i enp2s0 host 192.168.1.136
+
+I get segmented packages such as this when running iperf3:
+
+23:16:54.024139 IP OpenWrt.lan.59168 > Fecusia.targus-getdata1:
+Flags [.], seq 1486:2934, ack 1, win 4198,
+options [nop,nop,TS val 3886192908 ecr 3601341877], length 1448
+0x0000: fc34 9701 a0c6 14d6 4da8 3c4f 0800 4500
+0x0010: 05dc 16a0 4000 4006 9aa1 c0a8 0188 c0a8
+0x0020: 0102 e720 1451 ff25 9822 4c52 29cf 8010
+0x0030: 1066 ac8c 0000 0101 080a e7a2 990c d6a8
+(...)
+0x05c0: 5e49 e109 fe8c 4617 5e18 7a82 7eae d647
+0x05d0: e8ee ae64 dc88 c897 3f8a 07a4 3a33 6b1b
+0x05e0: 3501 a30f 2758 cc44 4b4a
+
+Several such packets often follow after each other verifying
+the segmentation into 0x05a8 (1448) byte packages also on the
+reveiving end. As can be seen, the ethernet frames are
+0x05ea (1514) in size.
+
+Performance with iperf3 before this patch: ~15.5 Mbit/s
+Performance with iperf3 after this patch: ~175 Mbit/s
+
+This was running a 60 second test (twice) the best measurement
+was 179 Mbit/s.
+
+For comparison if I run iperf3 with UDP I get around 1.05 Mbit/s
+both before and after this patch.
+
+While this is a gigabit ethernet interface, the CPU is a cheap
+D-Link DIR-685 router (based on the ARMv5 Faraday FA526 at
+~50 MHz), and the software is not supposed to drive traffic,
+as the device has a DSA chip, so this kind of numbers can be
+expected.
+
+Fixes: ac631873c9e7 ("net: ethernet: cortina: Drop TSO support")
+Reviewed-by: Eric Dumazet <edumazet@google.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 23 +++++++++++++++++++----
+ 1 file changed, 19 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -79,7 +79,8 @@ MODULE_PARM_DESC(debug, "Debug level (0=
+ #define GMAC0_IRQ4_8 (GMAC0_MIB_INT_BIT | GMAC0_RX_OVERRUN_INT_BIT)
+
+ #define GMAC_OFFLOAD_FEATURES (NETIF_F_SG | NETIF_F_IP_CSUM | \
+- NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM)
++ NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM | \
++ NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6)
+
+ /**
+ * struct gmac_queue_page - page buffer per-page info
+@@ -1148,13 +1149,25 @@ static int gmac_map_tx_bufs(struct net_d
+ skb_frag_t *skb_frag;
+ dma_addr_t mapping;
+ void *buffer;
++ u16 mss;
+ int ret;
+
+- /* TODO: implement proper TSO using MTU in word3 */
+ word1 = skb->len;
+ word3 = SOF_BIT;
+
+- if (skb->len >= ETH_FRAME_LEN) {
++ mss = skb_shinfo(skb)->gso_size;
++ if (mss) {
++ /* This means we are dealing with TCP and skb->len is the
++ * sum total of all the segments. The TSO will deal with
++ * chopping this up for us.
++ */
++ /* The accelerator needs the full frame size here */
++ mss += skb_tcp_all_headers(skb);
++ netdev_dbg(netdev, "segment offloading mss = %04x len=%04x\n",
++ mss, skb->len);
++ word1 |= TSS_MTU_ENABLE_BIT;
++ word3 |= mss;
++ } else if (skb->len >= ETH_FRAME_LEN) {
+ /* Hardware offloaded checksumming isn't working on frames
+ * bigger than 1514 bytes. A hypothesis about this is that the
+ * checksum buffer is only 1518 bytes, so when the frames get
+@@ -1169,7 +1182,9 @@ static int gmac_map_tx_bufs(struct net_d
+ return ret;
+ }
+ word1 |= TSS_BYPASS_BIT;
+- } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
++ }
++
++ if (skb->ip_summed == CHECKSUM_PARTIAL) {
+ int tcp = 0;
+
+ /* We do not switch off the checksumming on non TCP/UDP
--- /dev/null
+From 91fb8a7328dda827bc6c0da240a1eb17028416cd Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 9 May 2024 23:59:28 +0200
+Subject: [PATCH 2/5] net: ethernet: cortina: Use TSO also on common TCP
+
+It is possible to push the segment offloader to also
+process non-segmented frames: just pass the skb->len
+or desired MSS to the offloader and it will handle them.
+
+This is especially good if the user sets up the MTU
+and the frames get big, because the checksumming engine
+cannot handle any frames bigger than 1518 bytes, so
+segmenting them all to be at max that will be helpful
+for the hardware, which only need to quirk odd frames
+such as big UDP ping packets.
+
+The vendor driver always uses the TSO like this, and
+the driver seems more stable after this, so apparently
+the hardware may have been engineered to always use
+the TSO on anything it can handle.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 31 +++++++++++++++++++++------
+ 1 file changed, 24 insertions(+), 7 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -1148,6 +1148,7 @@ static int gmac_map_tx_bufs(struct net_d
+ struct gmac_txdesc *txd;
+ skb_frag_t *skb_frag;
+ dma_addr_t mapping;
++ bool tcp = false;
+ void *buffer;
+ u16 mss;
+ int ret;
+@@ -1155,6 +1156,13 @@ static int gmac_map_tx_bufs(struct net_d
+ word1 = skb->len;
+ word3 = SOF_BIT;
+
++ /* Determine if we are doing TCP */
++ if (skb->protocol == htons(ETH_P_IP))
++ tcp = (ip_hdr(skb)->protocol == IPPROTO_TCP);
++ else
++ /* IPv6 */
++ tcp = (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP);
++
+ mss = skb_shinfo(skb)->gso_size;
+ if (mss) {
+ /* This means we are dealing with TCP and skb->len is the
+@@ -1167,6 +1175,20 @@ static int gmac_map_tx_bufs(struct net_d
+ mss, skb->len);
+ word1 |= TSS_MTU_ENABLE_BIT;
+ word3 |= mss;
++ } else if (tcp) {
++ /* Even if we are not using TSO, use the segment offloader
++ * for transferring the TCP frame: the TSO engine will deal
++ * with chopping up frames that exceed ETH_DATA_LEN which
++ * the checksumming engine cannot handle (see below) into
++ * manageable chunks. It flawlessly deals with quite big
++ * frames and frames containing custom DSA EtherTypes.
++ */
++ mss = netdev->mtu + skb_tcp_all_headers(skb);
++ mss = min(mss, skb->len);
++ netdev_dbg(netdev, "botched TSO len %04x mtu %04x mss %04x\n",
++ skb->len, netdev->mtu, mss);
++ word1 |= TSS_MTU_ENABLE_BIT;
++ word3 |= mss;
+ } else if (skb->len >= ETH_FRAME_LEN) {
+ /* Hardware offloaded checksumming isn't working on frames
+ * bigger than 1514 bytes. A hypothesis about this is that the
+@@ -1185,21 +1207,16 @@ static int gmac_map_tx_bufs(struct net_d
+ }
+
+ if (skb->ip_summed == CHECKSUM_PARTIAL) {
+- int tcp = 0;
+-
+ /* We do not switch off the checksumming on non TCP/UDP
+ * frames: as is shown from tests, the checksumming engine
+ * is smart enough to see that a frame is not actually TCP
+ * or UDP and then just pass it through without any changes
+ * to the frame.
+ */
+- if (skb->protocol == htons(ETH_P_IP)) {
++ if (skb->protocol == htons(ETH_P_IP))
+ word1 |= TSS_IP_CHKSUM_BIT;
+- tcp = ip_hdr(skb)->protocol == IPPROTO_TCP;
+- } else { /* IPv6 */
++ else
+ word1 |= TSS_IPV6_ENABLE_BIT;
+- tcp = ipv6_hdr(skb)->nexthdr == IPPROTO_TCP;
+- }
+
+ word1 |= tcp ? TSS_TCP_CHKSUM_BIT : TSS_UDP_CHKSUM_BIT;
+ }
--- /dev/null
+From fa01c904b844e6033445f75b0b4d46a8e83b6086 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 10 May 2024 19:48:27 +0200
+Subject: [PATCH 3/5] net: ethernet: cortina: Rename adjust link callback
+
+The callback passed to of_phy_get_and_connect() in the
+Cortina Gemini driver is called "gmac_speed_set" which is
+archaic, rename it to "gmac_adjust_link" following the
+pattern of most other drivers.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -288,7 +288,7 @@ static void gmac_set_flow_control(struct
+ spin_unlock_irqrestore(&port->config_lock, flags);
+ }
+
+-static void gmac_speed_set(struct net_device *netdev)
++static void gmac_adjust_link(struct net_device *netdev)
+ {
+ struct gemini_ethernet_port *port = netdev_priv(netdev);
+ struct phy_device *phydev = netdev->phydev;
+@@ -367,7 +367,7 @@ static int gmac_setup_phy(struct net_dev
+
+ phy = of_phy_get_and_connect(netdev,
+ dev->of_node,
+- gmac_speed_set);
++ gmac_adjust_link);
+ if (!phy)
+ return -ENODEV;
+ netdev->phydev = phy;
--- /dev/null
+From 50ac9765c674bac803719c6b8294670edc6df31d Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 10 May 2024 19:44:39 +0200
+Subject: [PATCH 4/5] net: ethernet: cortina: Use negotiated TX/RX pause
+
+Instead of directly poking into registers of the PHY, use
+the existing function to query phylib about this directly.
+
+Suggested-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 15 +++++----------
+ 1 file changed, 5 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -293,8 +293,8 @@ static void gmac_adjust_link(struct net_
+ struct gemini_ethernet_port *port = netdev_priv(netdev);
+ struct phy_device *phydev = netdev->phydev;
+ union gmac_status status, old_status;
+- int pause_tx = 0;
+- int pause_rx = 0;
++ bool pause_tx = false;
++ bool pause_rx = false;
+
+ status.bits32 = readl(port->gmac_base + GMAC_STATUS);
+ old_status.bits32 = status.bits32;
+@@ -329,14 +329,9 @@ static void gmac_adjust_link(struct net_
+ }
+
+ if (phydev->duplex == DUPLEX_FULL) {
+- u16 lcladv = phy_read(phydev, MII_ADVERTISE);
+- u16 rmtadv = phy_read(phydev, MII_LPA);
+- u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
+-
+- if (cap & FLOW_CTRL_RX)
+- pause_rx = 1;
+- if (cap & FLOW_CTRL_TX)
+- pause_tx = 1;
++ phy_get_pause(phydev, &pause_tx, &pause_rx);
++ netdev_dbg(netdev, "set negotiated pause params pause TX = %s, pause RX = %s\n",
++ pause_tx ? "ON" : "OFF", pause_rx ? "ON" : "OFF");
+ }
+
+ gmac_set_flow_control(netdev, pause_tx, pause_rx);
--- /dev/null
+From 4eed4b87f17d10b7586349c13c3a30f9c24c9ba4 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Wed, 8 May 2024 23:21:17 +0200
+Subject: [PATCH 5/5] net: ethernet: cortina: Implement .set_pauseparam()
+
+The Cortina Gemini ethernet can very well set up TX or RX
+pausing, so add this functionality to the driver in a
+.set_pauseparam() callback. Essentially just call down to
+phylib and let phylib deal with this, .adjust_link()
+will respect the setting from phylib.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/cortina/gemini.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/net/ethernet/cortina/gemini.c
++++ b/drivers/net/ethernet/cortina/gemini.c
+@@ -2143,6 +2143,19 @@ static void gmac_get_pauseparam(struct n
+ pparam->autoneg = true;
+ }
+
++static int gmac_set_pauseparam(struct net_device *netdev,
++ struct ethtool_pauseparam *pparam)
++{
++ struct phy_device *phydev = netdev->phydev;
++
++ if (!pparam->autoneg)
++ return -EOPNOTSUPP;
++
++ phy_set_asym_pause(phydev, pparam->rx_pause, pparam->tx_pause);
++
++ return 0;
++}
++
+ static void gmac_get_ringparam(struct net_device *netdev,
+ struct ethtool_ringparam *rp,
+ struct kernel_ethtool_ringparam *kernel_rp,
+@@ -2263,6 +2276,7 @@ static const struct ethtool_ops gmac_351
+ .set_link_ksettings = gmac_set_ksettings,
+ .nway_reset = gmac_nway_reset,
+ .get_pauseparam = gmac_get_pauseparam,
++ .set_pauseparam = gmac_set_pauseparam,
+ .get_ringparam = gmac_get_ringparam,
+ .set_ringparam = gmac_set_ringparam,
+ .get_coalesce = gmac_get_coalesce,
+++ /dev/null
-From: Richard Gobert <richardbgobert@gmail.com>
-Date: Wed, 3 Jan 2024 15:44:21 +0100
-Subject: [PATCH] net: gro: parse ipv6 ext headers without frag0 invalidation
-
-The existing code always pulls the IPv6 header and sets the transport
-offset initially. Then optionally again pulls any extension headers in
-ipv6_gso_pull_exthdrs and sets the transport offset again on return from
-that call. skb->data is set at the start of the first extension header
-before calling ipv6_gso_pull_exthdrs, and must disable the frag0
-optimization because that function uses pskb_may_pull/pskb_pull instead of
-skb_gro_ helpers. It sets the GRO offset to the TCP header with
-skb_gro_pull and sets the transport header. Then returns skb->data to its
-position before this block.
-
-This commit introduces a new helper function - ipv6_gro_pull_exthdrs -
-which is used in ipv6_gro_receive to pull ipv6 ext headers instead of
-ipv6_gso_pull_exthdrs. Thus, there is no modification of skb->data, all
-operations use skb_gro_* helpers, and the frag0 fast path can be taken for
-IPv6 packets with ext headers.
-
-Signed-off-by: Richard Gobert <richardbgobert@gmail.com>
-Reviewed-by: Willem de Bruijn <willemb@google.com>
-Reviewed-by: David Ahern <dsahern@kernel.org>
-Reviewed-by: Eric Dumazet <edumazet@google.com>
-Link: https://lore.kernel.org/r/504130f6-b56c-4dcc-882c-97942c59f5b7@gmail.com
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
-
---- a/net/ipv6/ip6_offload.c
-+++ b/net/ipv6/ip6_offload.c
-@@ -37,6 +37,40 @@
- INDIRECT_CALL_L4(cb, f2, f1, head, skb); \
- })
-
-+static int ipv6_gro_pull_exthdrs(struct sk_buff *skb, int off, int proto)
-+{
-+ const struct net_offload *ops = NULL;
-+ struct ipv6_opt_hdr *opth;
-+
-+ for (;;) {
-+ int len;
-+
-+ ops = rcu_dereference(inet6_offloads[proto]);
-+
-+ if (unlikely(!ops))
-+ break;
-+
-+ if (!(ops->flags & INET6_PROTO_GSO_EXTHDR))
-+ break;
-+
-+ opth = skb_gro_header(skb, off + sizeof(*opth), off);
-+ if (unlikely(!opth))
-+ break;
-+
-+ len = ipv6_optlen(opth);
-+
-+ opth = skb_gro_header(skb, off + len, off);
-+ if (unlikely(!opth))
-+ break;
-+ proto = opth->nexthdr;
-+
-+ off += len;
-+ }
-+
-+ skb_gro_pull(skb, off - skb_network_offset(skb));
-+ return proto;
-+}
-+
- static int ipv6_gso_pull_exthdrs(struct sk_buff *skb, int proto)
- {
- const struct net_offload *ops = NULL;
-@@ -206,28 +240,25 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
- goto out;
-
- skb_set_network_header(skb, off);
-- skb_gro_pull(skb, sizeof(*iph));
-- skb_set_transport_header(skb, skb_gro_offset(skb));
-
-- flush += ntohs(iph->payload_len) != skb_gro_len(skb);
-+ flush += ntohs(iph->payload_len) != skb->len - hlen;
-
- proto = iph->nexthdr;
- ops = rcu_dereference(inet6_offloads[proto]);
- if (!ops || !ops->callbacks.gro_receive) {
-- pskb_pull(skb, skb_gro_offset(skb));
-- skb_gro_frag0_invalidate(skb);
-- proto = ipv6_gso_pull_exthdrs(skb, proto);
-- skb_gro_pull(skb, -skb_transport_offset(skb));
-- skb_reset_transport_header(skb);
-- __skb_push(skb, skb_gro_offset(skb));
-+ proto = ipv6_gro_pull_exthdrs(skb, hlen, proto);
-
- ops = rcu_dereference(inet6_offloads[proto]);
- if (!ops || !ops->callbacks.gro_receive)
- goto out;
-
-- iph = ipv6_hdr(skb);
-+ iph = skb_gro_network_header(skb);
-+ } else {
-+ skb_gro_pull(skb, sizeof(*iph));
- }
-
-+ skb_set_transport_header(skb, skb_gro_offset(skb));
-+
- NAPI_GRO_CB(skb)->proto = proto;
-
- flush--;
+++ /dev/null
-From: Richard Gobert <richardbgobert@gmail.com>
-Date: Tue, 30 Apr 2024 16:35:54 +0200
-Subject: [PATCH] net: gro: fix udp bad offset in socket lookup by adding
- {inner_}network_offset to napi_gro_cb
-
-Commits a602456 ("udp: Add GRO functions to UDP socket") and 57c67ff ("udp:
-additional GRO support") introduce incorrect usage of {ip,ipv6}_hdr in the
-complete phase of gro. The functions always return skb->network_header,
-which in the case of encapsulated packets at the gro complete phase, is
-always set to the innermost L3 of the packet. That means that calling
-{ip,ipv6}_hdr for skbs which completed the GRO receive phase (both in
-gro_list and *_gro_complete) when parsing an encapsulated packet's _outer_
-L3/L4 may return an unexpected value.
-
-This incorrect usage leads to a bug in GRO's UDP socket lookup.
-udp{4,6}_lib_lookup_skb functions use ip_hdr/ipv6_hdr respectively. These
-*_hdr functions return network_header which will point to the innermost L3,
-resulting in the wrong offset being used in __udp{4,6}_lib_lookup with
-encapsulated packets.
-
-This patch adds network_offset and inner_network_offset to napi_gro_cb, and
-makes sure both are set correctly.
-
-To fix the issue, network_offsets union is used inside napi_gro_cb, in
-which both the outer and the inner network offsets are saved.
-
-Reproduction example:
-
-Endpoint configuration example (fou + local address bind)
-
- # ip fou add port 6666 ipproto 4
- # ip link add name tun1 type ipip remote 2.2.2.1 local 2.2.2.2 encap fou encap-dport 5555 encap-sport 6666 mode ipip
- # ip link set tun1 up
- # ip a add 1.1.1.2/24 dev tun1
-
-Netperf TCP_STREAM result on net-next before patch is applied:
-
-net-next main, GRO enabled:
- $ netperf -H 1.1.1.2 -t TCP_STREAM -l 5
- Recv Send Send
- Socket Socket Message Elapsed
- Size Size Size Time Throughput
- bytes bytes bytes secs. 10^6bits/sec
-
- 131072 16384 16384 5.28 2.37
-
-net-next main, GRO disabled:
- $ netperf -H 1.1.1.2 -t TCP_STREAM -l 5
- Recv Send Send
- Socket Socket Message Elapsed
- Size Size Size Time Throughput
- bytes bytes bytes secs. 10^6bits/sec
-
- 131072 16384 16384 5.01 2745.06
-
-patch applied, GRO enabled:
- $ netperf -H 1.1.1.2 -t TCP_STREAM -l 5
- Recv Send Send
- Socket Socket Message Elapsed
- Size Size Size Time Throughput
- bytes bytes bytes secs. 10^6bits/sec
-
- 131072 16384 16384 5.01 2877.38
-
-Fixes: a6024562ffd7 ("udp: Add GRO functions to UDP socket")
-Signed-off-by: Richard Gobert <richardbgobert@gmail.com>
-Reviewed-by: Eric Dumazet <edumazet@google.com>
-Reviewed-by: Willem de Bruijn <willemb@google.com>
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
-
---- a/include/net/gro.h
-+++ b/include/net/gro.h
-@@ -86,6 +86,15 @@ struct napi_gro_cb {
-
- /* used to support CHECKSUM_COMPLETE for tunneling protocols */
- __wsum csum;
-+
-+ /* L3 offsets */
-+ union {
-+ struct {
-+ u16 network_offset;
-+ u16 inner_network_offset;
-+ };
-+ u16 network_offsets[2];
-+ };
- };
-
- #define NAPI_GRO_CB(skb) ((struct napi_gro_cb *)(skb)->cb)
---- a/net/8021q/vlan_core.c
-+++ b/net/8021q/vlan_core.c
-@@ -478,6 +478,8 @@ static struct sk_buff *vlan_gro_receive(
- if (unlikely(!vhdr))
- goto out;
-
-+ NAPI_GRO_CB(skb)->network_offsets[NAPI_GRO_CB(skb)->encap_mark] = hlen;
-+
- type = vhdr->h_vlan_encapsulated_proto;
-
- ptype = gro_find_receive_by_type(type);
---- a/net/core/gro.c
-+++ b/net/core/gro.c
-@@ -373,6 +373,7 @@ static inline void skb_gro_reset_offset(
- const struct skb_shared_info *pinfo = skb_shinfo(skb);
- const skb_frag_t *frag0 = &pinfo->frags[0];
-
-+ NAPI_GRO_CB(skb)->network_offset = 0;
- NAPI_GRO_CB(skb)->data_offset = 0;
- NAPI_GRO_CB(skb)->frag0 = NULL;
- NAPI_GRO_CB(skb)->frag0_len = 0;
---- a/net/ipv4/af_inet.c
-+++ b/net/ipv4/af_inet.c
-@@ -1571,6 +1571,7 @@ struct sk_buff *inet_gro_receive(struct
- /* The above will be needed by the transport layer if there is one
- * immediately following this IP hdr.
- */
-+ NAPI_GRO_CB(skb)->inner_network_offset = off;
-
- /* Note : No need to call skb_gro_postpull_rcsum() here,
- * as we already checked checksum over ipv4 header was 0
---- a/net/ipv4/udp.c
-+++ b/net/ipv4/udp.c
-@@ -534,7 +534,8 @@ static inline struct sock *__udp4_lib_lo
- struct sock *udp4_lib_lookup_skb(const struct sk_buff *skb,
- __be16 sport, __be16 dport)
- {
-- const struct iphdr *iph = ip_hdr(skb);
-+ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation];
-+ const struct iphdr *iph = (struct iphdr *)(skb->data + offset);
- struct net *net = dev_net(skb->dev);
- int iif, sdif;
-
---- a/net/ipv4/udp_offload.c
-+++ b/net/ipv4/udp_offload.c
-@@ -718,7 +718,8 @@ EXPORT_SYMBOL(udp_gro_complete);
-
- INDIRECT_CALLABLE_SCOPE int udp4_gro_complete(struct sk_buff *skb, int nhoff)
- {
-- const struct iphdr *iph = ip_hdr(skb);
-+ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation];
-+ const struct iphdr *iph = (struct iphdr *)(skb->data + offset);
- struct udphdr *uh = (struct udphdr *)(skb->data + nhoff);
-
- /* do fraglist only if there is no outer UDP encap (or we already processed it) */
---- a/net/ipv6/ip6_offload.c
-+++ b/net/ipv6/ip6_offload.c
-@@ -240,6 +240,7 @@ INDIRECT_CALLABLE_SCOPE struct sk_buff *
- goto out;
-
- skb_set_network_header(skb, off);
-+ NAPI_GRO_CB(skb)->inner_network_offset = off;
-
- flush += ntohs(iph->payload_len) != skb->len - hlen;
-
---- a/net/ipv6/udp.c
-+++ b/net/ipv6/udp.c
-@@ -275,7 +275,8 @@ static struct sock *__udp6_lib_lookup_sk
- struct sock *udp6_lib_lookup_skb(const struct sk_buff *skb,
- __be16 sport, __be16 dport)
- {
-- const struct ipv6hdr *iph = ipv6_hdr(skb);
-+ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation];
-+ const struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + offset);
- struct net *net = dev_net(skb->dev);
- int iif, sdif;
-
---- a/net/ipv6/udp_offload.c
-+++ b/net/ipv6/udp_offload.c
-@@ -164,7 +164,8 @@ flush:
-
- INDIRECT_CALLABLE_SCOPE int udp6_gro_complete(struct sk_buff *skb, int nhoff)
- {
-- const struct ipv6hdr *ipv6h = ipv6_hdr(skb);
-+ const u16 offset = NAPI_GRO_CB(skb)->network_offsets[skb->encapsulation];
-+ const struct ipv6hdr *ipv6h = (struct ipv6hdr *)(skb->data + offset);
- struct udphdr *uh = (struct udphdr *)(skb->data + nhoff);
-
- /* do fraglist only if there is no outer UDP encap (or we already processed it) */
+++ /dev/null
-From: Richard Gobert <richardbgobert@gmail.com>
-Date: Tue, 30 Apr 2024 16:35:55 +0200
-Subject: [PATCH] net: gro: add flush check in udp_gro_receive_segment
-
-GRO-GSO path is supposed to be transparent and as such L3 flush checks are
-relevant to all UDP flows merging in GRO. This patch uses the same logic
-and code from tcp_gro_receive, terminating merge if flush is non zero.
-
-Fixes: e20cf8d3f1f7 ("udp: implement GRO for plain UDP sockets.")
-Signed-off-by: Richard Gobert <richardbgobert@gmail.com>
-Reviewed-by: Willem de Bruijn <willemb@google.com>
-Signed-off-by: Paolo Abeni <pabeni@redhat.com>
----
-
---- a/net/ipv4/udp_offload.c
-+++ b/net/ipv4/udp_offload.c
-@@ -471,6 +471,7 @@ static struct sk_buff *udp_gro_receive_s
- struct sk_buff *p;
- unsigned int ulen;
- int ret = 0;
-+ int flush;
-
- /* requires non zero csum, for symmetry with GSO */
- if (!uh->check) {
-@@ -504,13 +505,22 @@ static struct sk_buff *udp_gro_receive_s
- return p;
- }
-
-+ flush = NAPI_GRO_CB(p)->flush;
-+
-+ if (NAPI_GRO_CB(p)->flush_id != 1 ||
-+ NAPI_GRO_CB(p)->count != 1 ||
-+ !NAPI_GRO_CB(p)->is_atomic)
-+ flush |= NAPI_GRO_CB(p)->flush_id;
-+ else
-+ NAPI_GRO_CB(p)->is_atomic = false;
-+
- /* Terminate the flow on len mismatch or if it grow "too much".
- * Under small packet flood GRO count could elsewhere grow a lot
- * leading to excessive truesize values.
- * On len mismatch merge the first packet shorter than gso_size,
- * otherwise complete the GRO packet.
- */
-- if (ulen > ntohs(uh2->len)) {
-+ if (ulen > ntohs(uh2->len) || flush) {
- pp = p;
- } else {
- if (NAPI_GRO_CB(skb)->is_flist) {
--- /dev/null
+From 97eb5d51b4a584a60e5d096bdb6b33edc9f50d8d Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Mon, 15 Jan 2024 12:43:38 +0000
+Subject: [PATCH] net: sfp-bus: fix SFP mode detect from bitrate
+
+The referenced commit moved the setting of the Autoneg and pause bits
+early in sfp_parse_support(). However, we check whether the modes are
+empty before using the bitrate to set some modes. Setting these bits
+so early causes that test to always be false, preventing this working,
+and thus some modules that used to work no longer do.
+
+Move them just before the call to the quirk.
+
+Fixes: 8110633db49d ("net: sfp-bus: allow SFP quirks to override Autoneg and pause bits")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
+Link: https://lore.kernel.org/r/E1rPMJW-001Ahf-L0@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/sfp-bus.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/sfp-bus.c
++++ b/drivers/net/phy/sfp-bus.c
+@@ -151,10 +151,6 @@ void sfp_parse_support(struct sfp_bus *b
+ unsigned int br_min, br_nom, br_max;
+ __ETHTOOL_DECLARE_LINK_MODE_MASK(modes) = { 0, };
+
+- phylink_set(modes, Autoneg);
+- phylink_set(modes, Pause);
+- phylink_set(modes, Asym_Pause);
+-
+ /* Decode the bitrate information to MBd */
+ br_min = br_nom = br_max = 0;
+ if (id->base.br_nominal) {
+@@ -339,6 +335,10 @@ void sfp_parse_support(struct sfp_bus *b
+ }
+ }
+
++ phylink_set(modes, Autoneg);
++ phylink_set(modes, Pause);
++ phylink_set(modes, Asym_Pause);
++
+ if (bus->sfp_quirk && bus->sfp_quirk->modes)
+ bus->sfp_quirk->modes(id, modes, interfaces);
+
--- /dev/null
+From 5d0fad48d2dec175ecb999974b94203c577973ef Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Wed, 8 May 2024 11:43:34 +0100
+Subject: [PATCH] net: ethernet: mediatek: split tx and rx fields in
+ mtk_soc_data struct
+
+Split tx and rx fields in mtk_soc_data struct. This is a preliminary
+patch to roll back to ADMAv1 for MT7986 and MT7981 SoC in order to fix a
+hw hang if the device receives a corrupted packet when using ADMAv2.0.
+
+Fixes: 197c9e9b17b1 ("net: ethernet: mtk_eth_soc: introduce support for mt7986 chipset")
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
+Link: https://lore.kernel.org/r/70a799b1f060ec2f57883e88ccb420ac0fb0abb5.1715164770.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 210 ++++++++++++--------
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h | 29 +--
+ 2 files changed, 139 insertions(+), 100 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1138,7 +1138,7 @@ static int mtk_init_fq_dma(struct mtk_et
+ eth->scratch_ring = eth->sram_base;
+ else
+ eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
+- cnt * soc->txrx.txd_size,
++ cnt * soc->tx.desc_size,
+ ð->phy_scratch_ring,
+ GFP_KERNEL);
+ if (unlikely(!eth->scratch_ring))
+@@ -1154,16 +1154,16 @@ static int mtk_init_fq_dma(struct mtk_et
+ if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
+ return -ENOMEM;
+
+- phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
++ phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
+
+ for (i = 0; i < cnt; i++) {
+ struct mtk_tx_dma_v2 *txd;
+
+- txd = eth->scratch_ring + i * soc->txrx.txd_size;
++ txd = eth->scratch_ring + i * soc->tx.desc_size;
+ txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
+ if (i < cnt - 1)
+ txd->txd2 = eth->phy_scratch_ring +
+- (i + 1) * soc->txrx.txd_size;
++ (i + 1) * soc->tx.desc_size;
+
+ txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
+ txd->txd4 = 0;
+@@ -1412,7 +1412,7 @@ static int mtk_tx_map(struct sk_buff *sk
+ if (itxd == ring->last_free)
+ return -ENOMEM;
+
+- itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
++ itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
+ memset(itx_buf, 0, sizeof(*itx_buf));
+
+ txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
+@@ -1453,7 +1453,7 @@ static int mtk_tx_map(struct sk_buff *sk
+
+ memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
+ txd_info.size = min_t(unsigned int, frag_size,
+- soc->txrx.dma_max_len);
++ soc->tx.dma_max_len);
+ txd_info.qid = queue;
+ txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
+ !(frag_size - txd_info.size);
+@@ -1466,7 +1466,7 @@ static int mtk_tx_map(struct sk_buff *sk
+ mtk_tx_set_dma_desc(dev, txd, &txd_info);
+
+ tx_buf = mtk_desc_to_tx_buf(ring, txd,
+- soc->txrx.txd_size);
++ soc->tx.desc_size);
+ if (new_desc)
+ memset(tx_buf, 0, sizeof(*tx_buf));
+ tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
+@@ -1509,7 +1509,7 @@ static int mtk_tx_map(struct sk_buff *sk
+ } else {
+ int next_idx;
+
+- next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
++ next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
+ ring->dma_size);
+ mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
+ }
+@@ -1518,7 +1518,7 @@ static int mtk_tx_map(struct sk_buff *sk
+
+ err_dma:
+ do {
+- tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
++ tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
+
+ /* unmap dma */
+ mtk_tx_unmap(eth, tx_buf, NULL, false);
+@@ -1543,7 +1543,7 @@ static int mtk_cal_txd_req(struct mtk_et
+ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+ frag = &skb_shinfo(skb)->frags[i];
+ nfrags += DIV_ROUND_UP(skb_frag_size(frag),
+- eth->soc->txrx.dma_max_len);
++ eth->soc->tx.dma_max_len);
+ }
+ } else {
+ nfrags += skb_shinfo(skb)->nr_frags;
+@@ -1650,7 +1650,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
+
+ ring = ð->rx_ring[i];
+ idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
+- rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
++ rxd = ring->dma + idx * eth->soc->rx.desc_size;
+ if (rxd->rxd2 & RX_DMA_DONE) {
+ ring->calc_idx_update = true;
+ return ring;
+@@ -1818,7 +1818,7 @@ static int mtk_xdp_submit_frame(struct m
+ }
+ htxd = txd;
+
+- tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
++ tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
+ memset(tx_buf, 0, sizeof(*tx_buf));
+ htx_buf = tx_buf;
+
+@@ -1837,7 +1837,7 @@ static int mtk_xdp_submit_frame(struct m
+ goto unmap;
+
+ tx_buf = mtk_desc_to_tx_buf(ring, txd,
+- soc->txrx.txd_size);
++ soc->tx.desc_size);
+ memset(tx_buf, 0, sizeof(*tx_buf));
+ n_desc++;
+ }
+@@ -1875,7 +1875,7 @@ static int mtk_xdp_submit_frame(struct m
+ } else {
+ int idx;
+
+- idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
++ idx = txd_to_idx(ring, txd, soc->tx.desc_size);
+ mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
+ MT7628_TX_CTX_IDX0);
+ }
+@@ -1886,7 +1886,7 @@ static int mtk_xdp_submit_frame(struct m
+
+ unmap:
+ while (htxd != txd) {
+- tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
++ tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
+ mtk_tx_unmap(eth, tx_buf, NULL, false);
+
+ htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
+@@ -2017,7 +2017,7 @@ static int mtk_poll_rx(struct napi_struc
+ goto rx_done;
+
+ idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
+- rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
++ rxd = ring->dma + idx * eth->soc->rx.desc_size;
+ data = ring->data[idx];
+
+ if (!mtk_rx_get_desc(eth, &trxd, rxd))
+@@ -2152,7 +2152,7 @@ static int mtk_poll_rx(struct napi_struc
+ rxdcsum = &trxd.rxd4;
+ }
+
+- if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
++ if (*rxdcsum & eth->soc->rx.dma_l4_valid)
+ skb->ip_summed = CHECKSUM_UNNECESSARY;
+ else
+ skb_checksum_none_assert(skb);
+@@ -2276,7 +2276,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
+ break;
+
+ tx_buf = mtk_desc_to_tx_buf(ring, desc,
+- eth->soc->txrx.txd_size);
++ eth->soc->tx.desc_size);
+ if (!tx_buf->data)
+ break;
+
+@@ -2327,7 +2327,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
+ }
+ mtk_tx_unmap(eth, tx_buf, &bq, true);
+
+- desc = ring->dma + cpu * eth->soc->txrx.txd_size;
++ desc = ring->dma + cpu * eth->soc->tx.desc_size;
+ ring->last_free = desc;
+ atomic_inc(&ring->free_count);
+
+@@ -2417,7 +2417,7 @@ static int mtk_napi_rx(struct napi_struc
+ do {
+ int rx_done;
+
+- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
++ mtk_w32(eth, eth->soc->rx.irq_done_mask,
+ reg_map->pdma.irq_status);
+ rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
+ rx_done_total += rx_done;
+@@ -2433,10 +2433,10 @@ static int mtk_napi_rx(struct napi_struc
+ return budget;
+
+ } while (mtk_r32(eth, reg_map->pdma.irq_status) &
+- eth->soc->txrx.rx_irq_done_mask);
++ eth->soc->rx.irq_done_mask);
+
+ if (napi_complete_done(napi, rx_done_total))
+- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
++ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
+
+ return rx_done_total;
+ }
+@@ -2445,7 +2445,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+ {
+ const struct mtk_soc_data *soc = eth->soc;
+ struct mtk_tx_ring *ring = ð->tx_ring;
+- int i, sz = soc->txrx.txd_size;
++ int i, sz = soc->tx.desc_size;
+ struct mtk_tx_dma_v2 *txd;
+ int ring_size;
+ u32 ofs, val;
+@@ -2568,14 +2568,14 @@ static void mtk_tx_clean(struct mtk_eth
+ }
+ if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
+ dma_free_coherent(eth->dma_dev,
+- ring->dma_size * soc->txrx.txd_size,
++ ring->dma_size * soc->tx.desc_size,
+ ring->dma, ring->phys);
+ ring->dma = NULL;
+ }
+
+ if (ring->dma_pdma) {
+ dma_free_coherent(eth->dma_dev,
+- ring->dma_size * soc->txrx.txd_size,
++ ring->dma_size * soc->tx.desc_size,
+ ring->dma_pdma, ring->phys_pdma);
+ ring->dma_pdma = NULL;
+ }
+@@ -2630,15 +2630,15 @@ static int mtk_rx_alloc(struct mtk_eth *
+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
+ rx_flag != MTK_RX_FLAGS_NORMAL) {
+ ring->dma = dma_alloc_coherent(eth->dma_dev,
+- rx_dma_size * eth->soc->txrx.rxd_size,
+- &ring->phys, GFP_KERNEL);
++ rx_dma_size * eth->soc->rx.desc_size,
++ &ring->phys, GFP_KERNEL);
+ } else {
+ struct mtk_tx_ring *tx_ring = ð->tx_ring;
+
+ ring->dma = tx_ring->dma + tx_ring_size *
+- eth->soc->txrx.txd_size * (ring_no + 1);
++ eth->soc->tx.desc_size * (ring_no + 1);
+ ring->phys = tx_ring->phys + tx_ring_size *
+- eth->soc->txrx.txd_size * (ring_no + 1);
++ eth->soc->tx.desc_size * (ring_no + 1);
+ }
+
+ if (!ring->dma)
+@@ -2649,7 +2649,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+ dma_addr_t dma_addr;
+ void *data;
+
+- rxd = ring->dma + i * eth->soc->txrx.rxd_size;
++ rxd = ring->dma + i * eth->soc->rx.desc_size;
+ if (ring->page_pool) {
+ data = mtk_page_pool_get_buff(ring->page_pool,
+ &dma_addr, GFP_KERNEL);
+@@ -2740,7 +2740,7 @@ static void mtk_rx_clean(struct mtk_eth
+ if (!ring->data[i])
+ continue;
+
+- rxd = ring->dma + i * eth->soc->txrx.rxd_size;
++ rxd = ring->dma + i * eth->soc->rx.desc_size;
+ if (!rxd->rxd1)
+ continue;
+
+@@ -2757,7 +2757,7 @@ static void mtk_rx_clean(struct mtk_eth
+
+ if (!in_sram && ring->dma) {
+ dma_free_coherent(eth->dma_dev,
+- ring->dma_size * eth->soc->txrx.rxd_size,
++ ring->dma_size * eth->soc->rx.desc_size,
+ ring->dma, ring->phys);
+ ring->dma = NULL;
+ }
+@@ -3120,7 +3120,7 @@ static void mtk_dma_free(struct mtk_eth
+ netdev_reset_queue(eth->netdev[i]);
+ if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
+ dma_free_coherent(eth->dma_dev,
+- MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
++ MTK_QDMA_RING_SIZE * soc->tx.desc_size,
+ eth->scratch_ring, eth->phy_scratch_ring);
+ eth->scratch_ring = NULL;
+ eth->phy_scratch_ring = 0;
+@@ -3170,7 +3170,7 @@ static irqreturn_t mtk_handle_irq_rx(int
+
+ eth->rx_events++;
+ if (likely(napi_schedule_prep(ð->rx_napi))) {
+- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
++ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
+ __napi_schedule(ð->rx_napi);
+ }
+
+@@ -3196,9 +3196,9 @@ static irqreturn_t mtk_handle_irq(int ir
+ const struct mtk_reg_map *reg_map = eth->soc->reg_map;
+
+ if (mtk_r32(eth, reg_map->pdma.irq_mask) &
+- eth->soc->txrx.rx_irq_done_mask) {
++ eth->soc->rx.irq_done_mask) {
+ if (mtk_r32(eth, reg_map->pdma.irq_status) &
+- eth->soc->txrx.rx_irq_done_mask)
++ eth->soc->rx.irq_done_mask)
+ mtk_handle_irq_rx(irq, _eth);
+ }
+ if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
+@@ -3216,10 +3216,10 @@ static void mtk_poll_controller(struct n
+ struct mtk_eth *eth = mac->hw;
+
+ mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
+- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
++ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
+ mtk_handle_irq_rx(eth->irq[2], dev);
+ mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
+- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
++ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
+ }
+ #endif
+
+@@ -3383,7 +3383,7 @@ static int mtk_open(struct net_device *d
+ napi_enable(ð->tx_napi);
+ napi_enable(ð->rx_napi);
+ mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
+- mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
++ mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
+ refcount_set(ð->dma_refcnt, 1);
+ }
+ else
+@@ -3467,7 +3467,7 @@ static int mtk_stop(struct net_device *d
+ mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
+
+ mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
+- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
++ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
+ napi_disable(ð->tx_napi);
+ napi_disable(ð->rx_napi);
+
+@@ -3943,9 +3943,9 @@ static int mtk_hw_init(struct mtk_eth *e
+
+ /* FE int grouping */
+ mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
+- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
++ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
+ mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
+- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
++ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
+ mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
+
+ if (mtk_is_netsys_v3_or_greater(eth)) {
+@@ -5037,11 +5037,15 @@ static const struct mtk_soc_data mt2701_
+ .required_clks = MT7623_CLKS_BITMAP,
+ .required_pctl = true,
+ .version = 1,
+- .txrx = {
+- .txd_size = sizeof(struct mtk_tx_dma),
+- .rxd_size = sizeof(struct mtk_rx_dma),
+- .rx_irq_done_mask = MTK_RX_DONE_INT,
+- .rx_dma_l4_valid = RX_DMA_L4_VALID,
++ .tx = {
++ .desc_size = sizeof(struct mtk_tx_dma),
++ .dma_max_len = MTK_TX_DMA_BUF_LEN,
++ .dma_len_offset = 16,
++ },
++ .rx = {
++ .desc_size = sizeof(struct mtk_rx_dma),
++ .irq_done_mask = MTK_RX_DONE_INT,
++ .dma_l4_valid = RX_DMA_L4_VALID,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
+ },
+@@ -5057,11 +5061,15 @@ static const struct mtk_soc_data mt7621_
+ .offload_version = 1,
+ .hash_offset = 2,
+ .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+- .txrx = {
+- .txd_size = sizeof(struct mtk_tx_dma),
+- .rxd_size = sizeof(struct mtk_rx_dma),
+- .rx_irq_done_mask = MTK_RX_DONE_INT,
+- .rx_dma_l4_valid = RX_DMA_L4_VALID,
++ .tx = {
++ .desc_size = sizeof(struct mtk_tx_dma),
++ .dma_max_len = MTK_TX_DMA_BUF_LEN,
++ .dma_len_offset = 16,
++ },
++ .rx = {
++ .desc_size = sizeof(struct mtk_rx_dma),
++ .irq_done_mask = MTK_RX_DONE_INT,
++ .dma_l4_valid = RX_DMA_L4_VALID,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
+ },
+@@ -5079,11 +5087,15 @@ static const struct mtk_soc_data mt7622_
+ .hash_offset = 2,
+ .has_accounting = true,
+ .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+- .txrx = {
+- .txd_size = sizeof(struct mtk_tx_dma),
+- .rxd_size = sizeof(struct mtk_rx_dma),
+- .rx_irq_done_mask = MTK_RX_DONE_INT,
+- .rx_dma_l4_valid = RX_DMA_L4_VALID,
++ .tx = {
++ .desc_size = sizeof(struct mtk_tx_dma),
++ .dma_max_len = MTK_TX_DMA_BUF_LEN,
++ .dma_len_offset = 16,
++ },
++ .rx = {
++ .desc_size = sizeof(struct mtk_rx_dma),
++ .irq_done_mask = MTK_RX_DONE_INT,
++ .dma_l4_valid = RX_DMA_L4_VALID,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
+ },
+@@ -5100,11 +5112,15 @@ static const struct mtk_soc_data mt7623_
+ .hash_offset = 2,
+ .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
+ .disable_pll_modes = true,
+- .txrx = {
+- .txd_size = sizeof(struct mtk_tx_dma),
+- .rxd_size = sizeof(struct mtk_rx_dma),
+- .rx_irq_done_mask = MTK_RX_DONE_INT,
+- .rx_dma_l4_valid = RX_DMA_L4_VALID,
++ .tx = {
++ .desc_size = sizeof(struct mtk_tx_dma),
++ .dma_max_len = MTK_TX_DMA_BUF_LEN,
++ .dma_len_offset = 16,
++ },
++ .rx = {
++ .desc_size = sizeof(struct mtk_rx_dma),
++ .irq_done_mask = MTK_RX_DONE_INT,
++ .dma_l4_valid = RX_DMA_L4_VALID,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
+ },
+@@ -5119,11 +5135,15 @@ static const struct mtk_soc_data mt7629_
+ .required_pctl = false,
+ .has_accounting = true,
+ .version = 1,
+- .txrx = {
+- .txd_size = sizeof(struct mtk_tx_dma),
+- .rxd_size = sizeof(struct mtk_rx_dma),
+- .rx_irq_done_mask = MTK_RX_DONE_INT,
+- .rx_dma_l4_valid = RX_DMA_L4_VALID,
++ .tx = {
++ .desc_size = sizeof(struct mtk_tx_dma),
++ .dma_max_len = MTK_TX_DMA_BUF_LEN,
++ .dma_len_offset = 16,
++ },
++ .rx = {
++ .desc_size = sizeof(struct mtk_rx_dma),
++ .irq_done_mask = MTK_RX_DONE_INT,
++ .dma_l4_valid = RX_DMA_L4_VALID,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
+ },
+@@ -5141,11 +5161,15 @@ static const struct mtk_soc_data mt7981_
+ .hash_offset = 4,
+ .has_accounting = true,
+ .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
+- .txrx = {
+- .txd_size = sizeof(struct mtk_tx_dma_v2),
+- .rxd_size = sizeof(struct mtk_rx_dma_v2),
+- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
+- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
++ .tx = {
++ .desc_size = sizeof(struct mtk_tx_dma_v2),
++ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
++ .dma_len_offset = 8,
++ },
++ .rx = {
++ .desc_size = sizeof(struct mtk_rx_dma_v2),
++ .irq_done_mask = MTK_RX_DONE_INT_V2,
++ .dma_l4_valid = RX_DMA_L4_VALID_V2,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+ .dma_len_offset = 8,
+ },
+@@ -5163,11 +5187,15 @@ static const struct mtk_soc_data mt7986_
+ .hash_offset = 4,
+ .has_accounting = true,
+ .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
+- .txrx = {
+- .txd_size = sizeof(struct mtk_tx_dma_v2),
+- .rxd_size = sizeof(struct mtk_rx_dma_v2),
+- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
+- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
++ .tx = {
++ .desc_size = sizeof(struct mtk_tx_dma_v2),
++ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
++ .dma_len_offset = 8,
++ },
++ .rx = {
++ .desc_size = sizeof(struct mtk_rx_dma_v2),
++ .irq_done_mask = MTK_RX_DONE_INT_V2,
++ .dma_l4_valid = RX_DMA_L4_VALID_V2,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+ .dma_len_offset = 8,
+ },
+@@ -5185,11 +5213,15 @@ static const struct mtk_soc_data mt7988_
+ .hash_offset = 4,
+ .has_accounting = true,
+ .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
+- .txrx = {
+- .txd_size = sizeof(struct mtk_tx_dma_v2),
+- .rxd_size = sizeof(struct mtk_rx_dma_v2),
+- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
+- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
++ .tx = {
++ .desc_size = sizeof(struct mtk_tx_dma_v2),
++ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
++ .dma_len_offset = 8,
++ },
++ .rx = {
++ .desc_size = sizeof(struct mtk_rx_dma_v2),
++ .irq_done_mask = MTK_RX_DONE_INT_V2,
++ .dma_l4_valid = RX_DMA_L4_VALID_V2,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+ .dma_len_offset = 8,
+ },
+@@ -5202,11 +5234,15 @@ static const struct mtk_soc_data rt5350_
+ .required_clks = MT7628_CLKS_BITMAP,
+ .required_pctl = false,
+ .version = 1,
+- .txrx = {
+- .txd_size = sizeof(struct mtk_tx_dma),
+- .rxd_size = sizeof(struct mtk_rx_dma),
+- .rx_irq_done_mask = MTK_RX_DONE_INT,
+- .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
++ .tx = {
++ .desc_size = sizeof(struct mtk_tx_dma),
++ .dma_max_len = MTK_TX_DMA_BUF_LEN,
++ .dma_len_offset = 16,
++ },
++ .rx = {
++ .desc_size = sizeof(struct mtk_rx_dma),
++ .irq_done_mask = MTK_RX_DONE_INT,
++ .dma_l4_valid = RX_DMA_L4_VALID_PDMA,
+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
+ .dma_len_offset = 16,
+ },
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -327,8 +327,8 @@
+ /* QDMA descriptor txd3 */
+ #define TX_DMA_OWNER_CPU BIT(31)
+ #define TX_DMA_LS0 BIT(30)
+-#define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
+-#define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len)
++#define TX_DMA_PLEN0(x) (((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
++#define TX_DMA_PLEN1(x) ((x) & eth->soc->tx.dma_max_len)
+ #define TX_DMA_SWC BIT(14)
+ #define TX_DMA_PQID GENMASK(3, 0)
+ #define TX_DMA_ADDR64_MASK GENMASK(3, 0)
+@@ -348,8 +348,8 @@
+ /* QDMA descriptor rxd2 */
+ #define RX_DMA_DONE BIT(31)
+ #define RX_DMA_LSO BIT(30)
+-#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
+-#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
++#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
++#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
+ #define RX_DMA_VTAG BIT(15)
+ #define RX_DMA_ADDR64_MASK GENMASK(3, 0)
+ #if IS_ENABLED(CONFIG_64BIT)
+@@ -1153,10 +1153,9 @@ struct mtk_reg_map {
+ * @foe_entry_size Foe table entry size.
+ * @has_accounting Bool indicating support for accounting of
+ * offloaded flows.
+- * @txd_size Tx DMA descriptor size.
+- * @rxd_size Rx DMA descriptor size.
+- * @rx_irq_done_mask Rx irq done register mask.
+- * @rx_dma_l4_valid Rx DMA valid register mask.
++ * @desc_size Tx/Rx DMA descriptor size.
++ * @irq_done_mask Rx irq done register mask.
++ * @dma_l4_valid Rx DMA valid register mask.
+ * @dma_max_len Max DMA tx/rx buffer length.
+ * @dma_len_offset Tx/Rx DMA length field offset.
+ */
+@@ -1174,13 +1173,17 @@ struct mtk_soc_data {
+ bool has_accounting;
+ bool disable_pll_modes;
+ struct {
+- u32 txd_size;
+- u32 rxd_size;
+- u32 rx_irq_done_mask;
+- u32 rx_dma_l4_valid;
++ u32 desc_size;
+ u32 dma_max_len;
+ u32 dma_len_offset;
+- } txrx;
++ } tx;
++ struct {
++ u32 desc_size;
++ u32 irq_done_mask;
++ u32 dma_l4_valid;
++ u32 dma_max_len;
++ u32 dma_len_offset;
++ } rx;
+ };
+
+ #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000)
--- /dev/null
+From 4d572e867bdb372bb4add39a0fa495c6a9c9a8da Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 8 May 2024 11:43:56 +0100
+Subject: [PATCH] net: ethernet: mediatek: use ADMAv1 instead of ADMAv2.0 on
+ MT7981 and MT7986
+
+ADMAv2.0 is plagued by RX hangs which can't easily detected and happen upon
+receival of a corrupted Ethernet frame.
+
+Use ADMAv1 instead which is also still present and usable, and doesn't
+suffer from that problem.
+
+Fixes: 197c9e9b17b1 ("net: ethernet: mtk_eth_soc: introduce support for mt7986 chipset")
+Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Link: https://lore.kernel.org/r/57cef74bbd0c243366ad1ff4221e3f72f437ec80.1715164770.git.daniel@makrotopia.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++-----------
+ 1 file changed, 23 insertions(+), 23 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -110,16 +110,16 @@ static const struct mtk_reg_map mt7986_r
+ .tx_irq_mask = 0x461c,
+ .tx_irq_status = 0x4618,
+ .pdma = {
+- .rx_ptr = 0x6100,
+- .rx_cnt_cfg = 0x6104,
+- .pcrx_ptr = 0x6108,
+- .glo_cfg = 0x6204,
+- .rst_idx = 0x6208,
+- .delay_irq = 0x620c,
+- .irq_status = 0x6220,
+- .irq_mask = 0x6228,
+- .adma_rx_dbg0 = 0x6238,
+- .int_grp = 0x6250,
++ .rx_ptr = 0x4100,
++ .rx_cnt_cfg = 0x4104,
++ .pcrx_ptr = 0x4108,
++ .glo_cfg = 0x4204,
++ .rst_idx = 0x4208,
++ .delay_irq = 0x420c,
++ .irq_status = 0x4220,
++ .irq_mask = 0x4228,
++ .adma_rx_dbg0 = 0x4238,
++ .int_grp = 0x4250,
+ },
+ .qdma = {
+ .qtx_cfg = 0x4400,
+@@ -1106,7 +1106,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+ rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
+ rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
+ rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
+- if (mtk_is_netsys_v2_or_greater(eth)) {
++ if (mtk_is_netsys_v3_or_greater(eth)) {
+ rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
+ rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
+ }
+@@ -2024,7 +2024,7 @@ static int mtk_poll_rx(struct napi_struc
+ break;
+
+ /* find out which mac the packet come from. values start at 1 */
+- if (mtk_is_netsys_v2_or_greater(eth)) {
++ if (mtk_is_netsys_v3_or_greater(eth)) {
+ u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
+
+ switch (val) {
+@@ -2136,7 +2136,7 @@ static int mtk_poll_rx(struct napi_struc
+ skb->dev = netdev;
+ bytes += skb->len;
+
+- if (mtk_is_netsys_v2_or_greater(eth)) {
++ if (mtk_is_netsys_v3_or_greater(eth)) {
+ reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
+ hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
+ if (hash != MTK_RXD5_FOE_ENTRY)
+@@ -2686,7 +2686,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+
+ rxd->rxd3 = 0;
+ rxd->rxd4 = 0;
+- if (mtk_is_netsys_v2_or_greater(eth)) {
++ if (mtk_is_netsys_v3_or_greater(eth)) {
+ rxd->rxd5 = 0;
+ rxd->rxd6 = 0;
+ rxd->rxd7 = 0;
+@@ -3889,7 +3889,7 @@ static int mtk_hw_init(struct mtk_eth *e
+ else
+ mtk_hw_reset(eth);
+
+- if (mtk_is_netsys_v2_or_greater(eth)) {
++ if (mtk_is_netsys_v3_or_greater(eth)) {
+ /* Set FE to PDMAv2 if necessary */
+ val = mtk_r32(eth, MTK_FE_GLO_MISC);
+ mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
+@@ -5167,11 +5167,11 @@ static const struct mtk_soc_data mt7981_
+ .dma_len_offset = 8,
+ },
+ .rx = {
+- .desc_size = sizeof(struct mtk_rx_dma_v2),
+- .irq_done_mask = MTK_RX_DONE_INT_V2,
++ .desc_size = sizeof(struct mtk_rx_dma),
++ .irq_done_mask = MTK_RX_DONE_INT,
+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
+- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+- .dma_len_offset = 8,
++ .dma_max_len = MTK_TX_DMA_BUF_LEN,
++ .dma_len_offset = 16,
+ },
+ };
+
+@@ -5193,11 +5193,11 @@ static const struct mtk_soc_data mt7986_
+ .dma_len_offset = 8,
+ },
+ .rx = {
+- .desc_size = sizeof(struct mtk_rx_dma_v2),
+- .irq_done_mask = MTK_RX_DONE_INT_V2,
++ .desc_size = sizeof(struct mtk_rx_dma),
++ .irq_done_mask = MTK_RX_DONE_INT,
+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
+- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
+- .dma_len_offset = 8,
++ .dma_max_len = MTK_TX_DMA_BUF_LEN,
++ .dma_len_offset = 16,
+ },
+ };
+
--- /dev/null
+From 52ea72ad0daa0f29535b4cef39257616c5a211d3 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 24 Oct 2023 00:00:19 +0200
+Subject: [PATCH 1/5] net: ethernet: mtk_wed: fix firmware loading for MT7986
+ SoC
+
+The WED mcu firmware does not contain all the memory regions defined in
+the dts reserved_memory node (e.g. MT7986 WED firmware does not contain
+cpu-boot region).
+Reverse the mtk_wed_mcu_run_firmware() logic to check all the fw
+sections are defined in the dts reserved_memory node.
+
+Fixes: c6d961aeaa77 ("net: ethernet: mtk_wed: move mem_region array out of mtk_wed_mcu_load_firmware")
+Tested-by: Frank Wunderlich <frank-w@public-files.de>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
+Link: https://lore.kernel.org/r/d983cbfe8ea562fef9264de8f0c501f7d5705bd5.1698098381.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 48 +++++++++++----------
+ 1 file changed, 25 insertions(+), 23 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -258,16 +258,12 @@ mtk_wed_get_memory_region(struct mtk_wed
+ }
+
+ static int
+-mtk_wed_mcu_run_firmware(struct mtk_wed_wo *wo, const struct firmware *fw,
+- struct mtk_wed_wo_memory_region *region)
++mtk_wed_mcu_run_firmware(struct mtk_wed_wo *wo, const struct firmware *fw)
+ {
+ const u8 *first_region_ptr, *region_ptr, *trailer_ptr, *ptr = fw->data;
+ const struct mtk_wed_fw_trailer *trailer;
+ const struct mtk_wed_fw_region *fw_region;
+
+- if (!region->phy_addr || !region->size)
+- return 0;
+-
+ trailer_ptr = fw->data + fw->size - sizeof(*trailer);
+ trailer = (const struct mtk_wed_fw_trailer *)trailer_ptr;
+ region_ptr = trailer_ptr - trailer->num_region * sizeof(*fw_region);
+@@ -275,33 +271,41 @@ mtk_wed_mcu_run_firmware(struct mtk_wed_
+
+ while (region_ptr < trailer_ptr) {
+ u32 length;
++ int i;
+
+ fw_region = (const struct mtk_wed_fw_region *)region_ptr;
+ length = le32_to_cpu(fw_region->len);
+-
+- if (region->phy_addr != le32_to_cpu(fw_region->addr))
+- goto next;
+-
+- if (region->size < length)
+- goto next;
+-
+ if (first_region_ptr < ptr + length)
+ goto next;
+
+- if (region->shared && region->consumed)
+- return 0;
++ for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
++ struct mtk_wed_wo_memory_region *region;
+
+- if (!region->shared || !region->consumed) {
+- memcpy_toio(region->addr, ptr, length);
+- region->consumed = true;
+- return 0;
++ region = &mem_region[i];
++ if (region->phy_addr != le32_to_cpu(fw_region->addr))
++ continue;
++
++ if (region->size < length)
++ continue;
++
++ if (region->shared && region->consumed)
++ break;
++
++ if (!region->shared || !region->consumed) {
++ memcpy_toio(region->addr, ptr, length);
++ region->consumed = true;
++ break;
++ }
+ }
++
++ if (i == ARRAY_SIZE(mem_region))
++ return -EINVAL;
+ next:
+ region_ptr += sizeof(*fw_region);
+ ptr += length;
+ }
+
+- return -EINVAL;
++ return 0;
+ }
+
+ static int
+@@ -360,11 +364,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ dev_info(wo->hw->dev, "MTK WED WO Chip ID %02x Region %d\n",
+ trailer->chip_id, trailer->num_region);
+
+- for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
+- ret = mtk_wed_mcu_run_firmware(wo, fw, &mem_region[i]);
+- if (ret)
+- goto out;
+- }
++ ret = mtk_wed_mcu_run_firmware(wo, fw);
++ if (ret)
++ goto out;
+
+ /* set the start address */
+ if (!mtk_wed_is_v3_or_greater(wo->hw) && wo->hw->index)
--- /dev/null
+From 7aa8defd3495208289abcc629946af26a2af3391 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 24 Oct 2023 00:01:30 +0200
+Subject: [PATCH 2/5] net: ethernet: mtk_wed: remove wo pointer in
+ wo_r32/wo_w32 signature
+
+wo pointer is no longer used in wo_r32 and wo_w32 routines so get rid of
+it.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/530537db0872f7523deff21f0a5dfdd9b75fdc9d.1698098459.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 12 ++++++------
+ 1 file changed, 6 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -32,12 +32,12 @@ static struct mtk_wed_wo_memory_region m
+ },
+ };
+
+-static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
++static u32 wo_r32(u32 reg)
+ {
+ return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
+ }
+
+-static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
++static void wo_w32(u32 reg, u32 val)
+ {
+ writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
+ }
+@@ -373,13 +373,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ boot_cr = MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR;
+ else
+ boot_cr = MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
+- wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
++ wo_w32(boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
+ /* wo firmware reset */
+- wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
++ wo_w32(MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
+
+- val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
++ val = wo_r32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
+ MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
+- wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
++ wo_w32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
+ out:
+ release_firmware(fw);
+
--- /dev/null
+From 65aacd457eaf5d0c958ed8030ec46f99ea808dd9 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Fri, 17 Nov 2023 17:39:22 +0100
+Subject: [PATCH 3/5] net: ethernet: mtk_wed: rely on __dev_alloc_page in
+ mtk_wed_tx_buffer_alloc
+
+Simplify the code and use __dev_alloc_page() instead of __dev_alloc_pages()
+with order 0 in mtk_wed_tx_buffer_alloc routine
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/mediatek/mtk_wed.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -670,7 +670,7 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
+ void *buf;
+ int s;
+
+- page = __dev_alloc_pages(GFP_KERNEL, 0);
++ page = __dev_alloc_page(GFP_KERNEL);
+ if (!page)
+ return -ENOMEM;
+
--- /dev/null
+From 5f5997322584b6257543d4d103f81484b8006d84 Mon Sep 17 00:00:00 2001
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Fri, 17 Nov 2023 17:42:59 +0100
+Subject: [PATCH 4/5] net: ethernet: mtk_wed: add support for devices with more
+ than 4GB of dram
+
+Introduce WED offloading support for boards with more than 4GB of
+memory.
+
+Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/1c7efdf5d384ea7af3c0209723e40b2ee0f956bf.1700239272.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
+ drivers/net/ethernet/mediatek/mtk_wed.c | 8 +++++---
+ drivers/net/ethernet/mediatek/mtk_wed_wo.c | 3 ++-
+ 3 files changed, 11 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -1158,15 +1158,18 @@ static int mtk_init_fq_dma(struct mtk_et
+ phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
+
+ for (i = 0; i < cnt; i++) {
++ dma_addr_t addr = dma_addr + i * MTK_QDMA_PAGE_SIZE;
+ struct mtk_tx_dma_v2 *txd;
+
+ txd = eth->scratch_ring + i * soc->tx.desc_size;
+- txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
++ txd->txd1 = addr;
+ if (i < cnt - 1)
+ txd->txd2 = eth->phy_scratch_ring +
+ (i + 1) * soc->tx.desc_size;
+
+ txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
++ if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA))
++ txd->txd3 |= TX_DMA_PREP_ADDR64(addr);
+ txd->txd4 = 0;
+ if (mtk_is_netsys_v2_or_greater(eth)) {
+ txd->txd5 = 0;
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -691,10 +691,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
+
+ for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
+ struct mtk_wdma_desc *desc = desc_ptr;
++ u32 ctrl;
+
+ desc->buf0 = cpu_to_le32(buf_phys);
+ if (!mtk_wed_is_v3_or_greater(dev->hw)) {
+- u32 txd_size, ctrl;
++ u32 txd_size;
+
+ txd_size = dev->wlan.init_buf(buf, buf_phys,
+ token++);
+@@ -708,11 +709,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
+ ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG0 |
+ FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2,
+ MTK_WED_BUF_SIZE - txd_size);
+- desc->ctrl = cpu_to_le32(ctrl);
+ desc->info = 0;
+ } else {
+- desc->ctrl = cpu_to_le32(token << 16);
++ ctrl = token << 16 | TX_DMA_PREP_ADDR64(buf_phys);
+ }
++ desc->ctrl = cpu_to_le32(ctrl);
+
+ desc_ptr += desc_size;
+ buf += MTK_WED_BUF_SIZE;
+@@ -811,6 +812,7 @@ mtk_wed_hwrro_buffer_alloc(struct mtk_we
+ buf_phys = page_phys;
+ for (s = 0; s < MTK_WED_RX_BUF_PER_PAGE; s++) {
+ desc->buf0 = cpu_to_le32(buf_phys);
++ desc->token = cpu_to_le32(RX_DMA_PREP_ADDR64(buf_phys));
+ buf_phys += MTK_WED_PAGE_BUF_SIZE;
+ desc++;
+ }
+--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.c
+@@ -142,7 +142,8 @@ mtk_wed_wo_queue_refill(struct mtk_wed_w
+ dma_addr_t addr;
+ void *buf;
+
+- buf = page_frag_alloc(&q->cache, q->buf_size, GFP_ATOMIC);
++ buf = page_frag_alloc(&q->cache, q->buf_size,
++ GFP_ATOMIC | GFP_DMA32);
+ if (!buf)
+ break;
+
--- /dev/null
+From c278ec644377249aba5b1e1ca2b5705fd1c0132c Mon Sep 17 00:00:00 2001
+From: Paweł Owoc <frut3k7@gmail.com>
+Date: Mon, 1 Apr 2024 16:51:06 +0200
+Subject: [PATCH net-next v2] net: phy: aquantia: add support for AQR114C PHY ID
+
+Add support for AQR114C PHY ID. This PHY advertise 10G speed:
+SPEED(0x04): 0x6031
+ capabilities: -400g +5g +2.5g -200g -25g -10g-xr -100g -40g -10g/1g -10
+ +100 +1000 -10-ts -2-tl +10g
+EXTABLE(0x0B): 0x40fc
+ capabilities: -10g-cx4 -10g-lrm +10g-t +10g-kx4 +10g-kr +1000-t +1000-kx
+ +100-tx -10-t -p2mp -40g/100g -1000/100-t1 -25g -200g/400g
+ +2.5g/5g -1000-h
+
+but supports only up to 5G speed (as with AQR111/111B0).
+AQR111 init config is used to set max speed 5G.
+
+Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240401145114.1699451-1-frut3k7@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/aquantia/aquantia_main.c | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -28,6 +28,7 @@
+ #define PHY_ID_AQR412 0x03a1b712
+ #define PHY_ID_AQR113 0x31c31c40
+ #define PHY_ID_AQR113C 0x31c31c12
++#define PHY_ID_AQR114C 0x31c31c22
+ #define PHY_ID_AQR813 0x31c31cb2
+
+ #define MDIO_PHYXS_VEND_IF_STATUS 0xe812
+@@ -880,6 +881,25 @@ static struct phy_driver aqr_driver[] =
+ .link_change_notify = aqr107_link_change_notify,
+ },
+ {
++ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C),
++ .name = "Aquantia AQR114C",
++ .probe = aqr107_probe,
++ .get_rate_matching = aqr107_get_rate_matching,
++ .config_init = aqr111_config_init,
++ .config_aneg = aqr_config_aneg,
++ .config_intr = aqr_config_intr,
++ .handle_interrupt = aqr_handle_interrupt,
++ .read_status = aqr107_read_status,
++ .get_tunable = aqr107_get_tunable,
++ .set_tunable = aqr107_set_tunable,
++ .suspend = aqr107_suspend,
++ .resume = aqr107_resume,
++ .get_sset_count = aqr107_get_sset_count,
++ .get_strings = aqr107_get_strings,
++ .get_stats = aqr107_get_stats,
++ .link_change_notify = aqr107_link_change_notify,
++},
++{
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
+ .name = "Aquantia AQR813",
+ .probe = aqr107_probe,
+@@ -916,6 +936,7 @@ static struct mdio_device_id __maybe_unu
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
++ { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
+ { }
+ };
--- a/drivers/nvmem/qfprom.c
+++ b/drivers/nvmem/qfprom.c
-@@ -423,12 +423,12 @@ static int qfprom_probe(struct platform_
+@@ -424,12 +424,12 @@ static int qfprom_probe(struct platform_
if (IS_ERR(priv->vcc))
return PTR_ERR(priv->vcc);
+++ /dev/null
-From 2cc3b37f5b6df8189d55d0e812d9658ce256dfec Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Fri, 20 Oct 2023 11:55:41 +0100
-Subject: [PATCH] nvmem: add explicit config option to read old syntax fixed OF
- cells
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Binding for fixed NVMEM cells defined directly as NVMEM device subnodes
-has been deprecated. It has been replaced by the "fixed-layout" NVMEM
-layout binding.
-
-New syntax is meant to be clearer and should help avoiding imprecise
-bindings.
-
-NVMEM subsystem already supports the new binding. It should be a good
-idea to limit support for old syntax to existing drivers that actually
-support & use it (we can't break backward compatibility!). That way we
-additionally encourage new bindings & drivers to ignore deprecated
-binding.
-
-It wasn't clear (to me) if rtc and w1 code actually uses old syntax
-fixed cells. I enabled them to don't risk any breakage.
-
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
-[for meson-{efuse,mx-efuse}.c]
-Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
-[for mtk-efuse.c, nvmem/core.c, nvmem-provider.h]
-Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-[MT8192, MT8195 Chromebooks]
-Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
-[for microchip-otpc.c]
-Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-[SAMA7G5-EK]
-Tested-by: Claudiu Beznea <claudiu.beznea@microchip.com>
-Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
-Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
-Link: https://lore.kernel.org/r/20231020105545.216052-3-srinivas.kandagatla@linaro.org
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/mtd/mtdcore.c | 2 ++
- drivers/nvmem/apple-efuses.c | 1 +
- drivers/nvmem/core.c | 8 +++++---
- drivers/nvmem/imx-ocotp-scu.c | 1 +
- drivers/nvmem/imx-ocotp.c | 1 +
- drivers/nvmem/meson-efuse.c | 1 +
- drivers/nvmem/meson-mx-efuse.c | 1 +
- drivers/nvmem/microchip-otpc.c | 1 +
- drivers/nvmem/mtk-efuse.c | 1 +
- drivers/nvmem/qcom-spmi-sdam.c | 1 +
- drivers/nvmem/qfprom.c | 1 +
- drivers/nvmem/rave-sp-eeprom.c | 1 +
- drivers/nvmem/rockchip-efuse.c | 1 +
- drivers/nvmem/sc27xx-efuse.c | 1 +
- drivers/nvmem/sec-qfprom.c | 1 +
- drivers/nvmem/sprd-efuse.c | 1 +
- drivers/nvmem/stm32-romem.c | 1 +
- drivers/nvmem/sunplus-ocotp.c | 1 +
- drivers/nvmem/sunxi_sid.c | 1 +
- drivers/nvmem/uniphier-efuse.c | 1 +
- drivers/nvmem/zynqmp_nvmem.c | 1 +
- drivers/rtc/nvmem.c | 1 +
- drivers/w1/slaves/w1_ds250x.c | 1 +
- include/linux/nvmem-provider.h | 2 ++
- 24 files changed, 30 insertions(+), 3 deletions(-)
-
---- a/drivers/mtd/mtdcore.c
-+++ b/drivers/mtd/mtdcore.c
-@@ -552,6 +552,7 @@ static int mtd_nvmem_add(struct mtd_info
- config.dev = &mtd->dev;
- config.name = dev_name(&mtd->dev);
- config.owner = THIS_MODULE;
-+ config.add_legacy_fixed_of_cells = of_device_is_compatible(node, "nvmem-cells");
- config.reg_read = mtd_nvmem_reg_read;
- config.size = mtd->size;
- config.word_size = 1;
-@@ -898,6 +899,7 @@ static struct nvmem_device *mtd_otp_nvme
- config.name = compatible;
- config.id = NVMEM_DEVID_AUTO;
- config.owner = THIS_MODULE;
-+ config.add_legacy_fixed_of_cells = true;
- config.type = NVMEM_TYPE_OTP;
- config.root_only = true;
- config.ignore_wp = true;
---- a/drivers/nvmem/apple-efuses.c
-+++ b/drivers/nvmem/apple-efuses.c
-@@ -36,6 +36,7 @@ static int apple_efuses_probe(struct pla
- struct resource *res;
- struct nvmem_config config = {
- .dev = &pdev->dev,
-+ .add_legacy_fixed_of_cells = true,
- .read_only = true,
- .reg_read = apple_efuses_read,
- .stride = sizeof(u32),
---- a/drivers/nvmem/core.c
-+++ b/drivers/nvmem/core.c
-@@ -1003,9 +1003,11 @@ struct nvmem_device *nvmem_register(cons
- if (rval)
- goto err_remove_cells;
-
-- rval = nvmem_add_cells_from_legacy_of(nvmem);
-- if (rval)
-- goto err_remove_cells;
-+ if (config->add_legacy_fixed_of_cells) {
-+ rval = nvmem_add_cells_from_legacy_of(nvmem);
-+ if (rval)
-+ goto err_remove_cells;
-+ }
-
- rval = nvmem_add_cells_from_fixed_layout(nvmem);
- if (rval)
---- a/drivers/nvmem/imx-ocotp-scu.c
-+++ b/drivers/nvmem/imx-ocotp-scu.c
-@@ -220,6 +220,7 @@ static int imx_scu_ocotp_write(void *con
-
- static struct nvmem_config imx_scu_ocotp_nvmem_config = {
- .name = "imx-scu-ocotp",
-+ .add_legacy_fixed_of_cells = true,
- .read_only = false,
- .word_size = 4,
- .stride = 1,
---- a/drivers/nvmem/imx-ocotp.c
-+++ b/drivers/nvmem/imx-ocotp.c
-@@ -615,6 +615,7 @@ static int imx_ocotp_probe(struct platfo
- return PTR_ERR(priv->clk);
-
- priv->params = of_device_get_match_data(&pdev->dev);
-+ imx_ocotp_nvmem_config.add_legacy_fixed_of_cells = true;
- imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
- imx_ocotp_nvmem_config.dev = dev;
- imx_ocotp_nvmem_config.priv = priv;
---- a/drivers/nvmem/meson-efuse.c
-+++ b/drivers/nvmem/meson-efuse.c
-@@ -74,6 +74,7 @@ static int meson_efuse_probe(struct plat
-
- econfig->dev = dev;
- econfig->name = dev_name(dev);
-+ econfig->add_legacy_fixed_of_cells = true;
- econfig->stride = 1;
- econfig->word_size = 1;
- econfig->reg_read = meson_efuse_read;
---- a/drivers/nvmem/meson-mx-efuse.c
-+++ b/drivers/nvmem/meson-mx-efuse.c
-@@ -210,6 +210,7 @@ static int meson_mx_efuse_probe(struct p
- efuse->config.owner = THIS_MODULE;
- efuse->config.dev = &pdev->dev;
- efuse->config.priv = efuse;
-+ efuse->config.add_legacy_fixed_of_cells = true;
- efuse->config.stride = drvdata->word_size;
- efuse->config.word_size = drvdata->word_size;
- efuse->config.size = SZ_512;
---- a/drivers/nvmem/microchip-otpc.c
-+++ b/drivers/nvmem/microchip-otpc.c
-@@ -261,6 +261,7 @@ static int mchp_otpc_probe(struct platfo
- return ret;
-
- mchp_nvmem_config.dev = otpc->dev;
-+ mchp_nvmem_config.add_legacy_fixed_of_cells = true;
- mchp_nvmem_config.size = size;
- mchp_nvmem_config.priv = otpc;
- nvmem = devm_nvmem_register(&pdev->dev, &mchp_nvmem_config);
---- a/drivers/nvmem/mtk-efuse.c
-+++ b/drivers/nvmem/mtk-efuse.c
-@@ -83,6 +83,7 @@ static int mtk_efuse_probe(struct platfo
- return PTR_ERR(priv->base);
-
- pdata = device_get_match_data(dev);
-+ econfig.add_legacy_fixed_of_cells = true;
- econfig.stride = 1;
- econfig.word_size = 1;
- econfig.reg_read = mtk_reg_read;
---- a/drivers/nvmem/qcom-spmi-sdam.c
-+++ b/drivers/nvmem/qcom-spmi-sdam.c
-@@ -142,6 +142,7 @@ static int sdam_probe(struct platform_de
- sdam->sdam_config.name = "spmi_sdam";
- sdam->sdam_config.id = NVMEM_DEVID_AUTO;
- sdam->sdam_config.owner = THIS_MODULE;
-+ sdam->sdam_config.add_legacy_fixed_of_cells = true;
- sdam->sdam_config.stride = 1;
- sdam->sdam_config.word_size = 1;
- sdam->sdam_config.reg_read = sdam_read;
---- a/drivers/nvmem/qfprom.c
-+++ b/drivers/nvmem/qfprom.c
-@@ -357,6 +357,7 @@ static int qfprom_probe(struct platform_
- {
- struct nvmem_config econfig = {
- .name = "qfprom",
-+ .add_legacy_fixed_of_cells = true,
- .stride = 1,
- .word_size = 1,
- .id = NVMEM_DEVID_AUTO,
---- a/drivers/nvmem/rave-sp-eeprom.c
-+++ b/drivers/nvmem/rave-sp-eeprom.c
-@@ -328,6 +328,7 @@ static int rave_sp_eeprom_probe(struct p
- of_property_read_string(np, "zii,eeprom-name", &config.name);
- config.priv = eeprom;
- config.dev = dev;
-+ config.add_legacy_fixed_of_cells = true;
- config.size = size;
- config.reg_read = rave_sp_eeprom_reg_read;
- config.reg_write = rave_sp_eeprom_reg_write;
---- a/drivers/nvmem/rockchip-efuse.c
-+++ b/drivers/nvmem/rockchip-efuse.c
-@@ -205,6 +205,7 @@ static int rockchip_rk3399_efuse_read(vo
-
- static struct nvmem_config econfig = {
- .name = "rockchip-efuse",
-+ .add_legacy_fixed_of_cells = true,
- .stride = 1,
- .word_size = 1,
- .read_only = true,
---- a/drivers/nvmem/sc27xx-efuse.c
-+++ b/drivers/nvmem/sc27xx-efuse.c
-@@ -247,6 +247,7 @@ static int sc27xx_efuse_probe(struct pla
- econfig.reg_read = sc27xx_efuse_read;
- econfig.priv = efuse;
- econfig.dev = &pdev->dev;
-+ econfig.add_legacy_fixed_of_cells = true;
- nvmem = devm_nvmem_register(&pdev->dev, &econfig);
- if (IS_ERR(nvmem)) {
- dev_err(&pdev->dev, "failed to register nvmem config\n");
---- a/drivers/nvmem/sec-qfprom.c
-+++ b/drivers/nvmem/sec-qfprom.c
-@@ -47,6 +47,7 @@ static int sec_qfprom_probe(struct platf
- {
- struct nvmem_config econfig = {
- .name = "sec-qfprom",
-+ .add_legacy_fixed_of_cells = true,
- .stride = 1,
- .word_size = 1,
- .id = NVMEM_DEVID_AUTO,
---- a/drivers/nvmem/sprd-efuse.c
-+++ b/drivers/nvmem/sprd-efuse.c
-@@ -408,6 +408,7 @@ static int sprd_efuse_probe(struct platf
- econfig.read_only = false;
- econfig.name = "sprd-efuse";
- econfig.size = efuse->data->blk_nums * SPRD_EFUSE_BLOCK_WIDTH;
-+ econfig.add_legacy_fixed_of_cells = true;
- econfig.reg_read = sprd_efuse_read;
- econfig.reg_write = sprd_efuse_write;
- econfig.priv = efuse;
---- a/drivers/nvmem/stm32-romem.c
-+++ b/drivers/nvmem/stm32-romem.c
-@@ -207,6 +207,7 @@ static int stm32_romem_probe(struct plat
- priv->cfg.priv = priv;
- priv->cfg.owner = THIS_MODULE;
- priv->cfg.type = NVMEM_TYPE_OTP;
-+ priv->cfg.add_legacy_fixed_of_cells = true;
-
- priv->lower = 0;
-
---- a/drivers/nvmem/sunplus-ocotp.c
-+++ b/drivers/nvmem/sunplus-ocotp.c
-@@ -145,6 +145,7 @@ disable_clk:
-
- static struct nvmem_config sp_ocotp_nvmem_config = {
- .name = "sp-ocotp",
-+ .add_legacy_fixed_of_cells = true,
- .read_only = true,
- .word_size = 1,
- .size = QAC628_OTP_SIZE,
---- a/drivers/nvmem/sunxi_sid.c
-+++ b/drivers/nvmem/sunxi_sid.c
-@@ -153,6 +153,7 @@ static int sunxi_sid_probe(struct platfo
- nvmem_cfg->dev = dev;
- nvmem_cfg->name = "sunxi-sid";
- nvmem_cfg->type = NVMEM_TYPE_OTP;
-+ nvmem_cfg->add_legacy_fixed_of_cells = true;
- nvmem_cfg->read_only = true;
- nvmem_cfg->size = cfg->size;
- nvmem_cfg->word_size = 1;
---- a/drivers/nvmem/uniphier-efuse.c
-+++ b/drivers/nvmem/uniphier-efuse.c
-@@ -52,6 +52,7 @@ static int uniphier_efuse_probe(struct p
- econfig.size = resource_size(res);
- econfig.priv = priv;
- econfig.dev = dev;
-+ econfig.add_legacy_fixed_of_cells = true;
- nvmem = devm_nvmem_register(dev, &econfig);
-
- return PTR_ERR_OR_ZERO(nvmem);
---- a/drivers/nvmem/zynqmp_nvmem.c
-+++ b/drivers/nvmem/zynqmp_nvmem.c
-@@ -58,6 +58,7 @@ static int zynqmp_nvmem_probe(struct pla
-
- priv->dev = dev;
- econfig.dev = dev;
-+ econfig.add_legacy_fixed_of_cells = true;
- econfig.reg_read = zynqmp_nvmem_read;
- econfig.priv = priv;
-
---- a/drivers/rtc/nvmem.c
-+++ b/drivers/rtc/nvmem.c
-@@ -21,6 +21,7 @@ int devm_rtc_nvmem_register(struct rtc_d
-
- nvmem_config->dev = dev;
- nvmem_config->owner = rtc->owner;
-+ nvmem_config->add_legacy_fixed_of_cells = true;
- nvmem = devm_nvmem_register(dev, nvmem_config);
- if (IS_ERR(nvmem))
- dev_err(dev, "failed to register nvmem device for RTC\n");
---- a/drivers/w1/slaves/w1_ds250x.c
-+++ b/drivers/w1/slaves/w1_ds250x.c
-@@ -168,6 +168,7 @@ static int w1_eprom_add_slave(struct w1_
- struct nvmem_device *nvmem;
- struct nvmem_config nvmem_cfg = {
- .dev = &sl->dev,
-+ .add_legacy_fixed_of_cells = true,
- .reg_read = w1_nvmem_read,
- .type = NVMEM_TYPE_OTP,
- .read_only = true,
---- a/include/linux/nvmem-provider.h
-+++ b/include/linux/nvmem-provider.h
-@@ -82,6 +82,7 @@ struct nvmem_cell_info {
- * @owner: Pointer to exporter module. Used for refcounting.
- * @cells: Optional array of pre-defined NVMEM cells.
- * @ncells: Number of elements in cells.
-+ * @add_legacy_fixed_of_cells: Read fixed NVMEM cells from old OF syntax.
- * @keepout: Optional array of keepout ranges (sorted ascending by start).
- * @nkeepout: Number of elements in the keepout array.
- * @type: Type of the nvmem storage
-@@ -112,6 +113,7 @@ struct nvmem_config {
- struct module *owner;
- const struct nvmem_cell_info *cells;
- int ncells;
-+ bool add_legacy_fixed_of_cells;
- const struct nvmem_keepout *keepout;
- unsigned int nkeepout;
- enum nvmem_type type;
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC_ITU_T is not set
# CONFIG_CRC_T10DIF is not set
+# CONFIG_CROS_HPS_I2C is not set
CONFIG_CROSS_COMPILE=""
# CONFIG_CROSS_MEMORY_ATTACH is not set
CONFIG_CRYPTO=y
# CONFIG_CRYPTO_DEV_CCREE is not set
# CONFIG_CRYPTO_DEV_FSL_CAAM is not set
# CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
# CONFIG_CRYPTO_DEV_HIFN_795X is not set
# CONFIG_CRYPTO_DEV_HISI_SEC is not set
# CONFIG_CRYPTO_DEV_HISI_ZIP is not set
# CONFIG_IMG_MDC_DMA is not set
# CONFIG_IMX7D_ADC is not set
# CONFIG_IMX8QXP_ADC is not set
+# CONFIG_IMX93_ADC is not set
# CONFIG_IMX_IPUV3_CORE is not set
# CONFIG_IMX_THERMAL is not set
# CONFIG_INA2XX_ADC is not set
# CONFIG_VIDEO_IMX477 is not set
# CONFIG_VIDEO_IMX519 is not set
# CONFIG_VIDEO_IMX708 is not set
+# CONFIG_VIDEO_IMX7_CSI is not set
+# CONFIG_VIDEO_IMX8MQ_MIPI_CSI2 is not set
+# CONFIG_VIDEO_IMX8_ISI is not set
# CONFIG_VIDEO_IMX8_JPEG is not set
# CONFIG_VIDEO_IMX_MIPI_CSIS is not set
# CONFIG_VIDEO_IMX_PXP is not set
+From a7ae4ed0a3951c45d4a59ee575951b64ae4a23fb Mon Sep 17 00:00:00 2001
+From: Felix Fietkau <nbd@nbd.name>
+Date: Tue, 7 May 2024 12:22:15 +0200
+Subject: [PATCH] kernel: fix tools build breakage on macos with x86
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
--- a/tools/scripts/Makefile.include
+++ b/tools/scripts/Makefile.include
@@ -72,8 +72,6 @@ $(call allow-override,CXX,$(CROSS_COMPIL
+++ /dev/null
-From b14784e7883390c20ed3ff904892255404a5914b Mon Sep 17 00:00:00 2001
-From: Felix Fietkau <nbd@nbd.name>
-Date: Fri, 7 Jul 2017 17:05:53 +0200
-Subject: add an optional config option for stripping all unnecessary symbol exports from the kernel image
-
-lede-commit: bb5a40c64b7c4f4848509fa0a6625055fc9e66cc
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
- include/asm-generic/vmlinux.lds.h | 18 +++++++++++++++---
- include/linux/export.h | 9 ++++++++-
- scripts/Makefile.build | 2 +-
- 3 files changed, 24 insertions(+), 5 deletions(-)
-
---- a/include/asm-generic/vmlinux.lds.h
-+++ b/include/asm-generic/vmlinux.lds.h
-@@ -81,6 +81,16 @@
- #define RO_EXCEPTION_TABLE
- #endif
-
-+#ifndef SYMTAB_KEEP
-+#define SYMTAB_KEEP KEEP(*(SORT(___ksymtab+*)))
-+#define SYMTAB_KEEP_GPL KEEP(*(SORT(___ksymtab_gpl+*)))
-+#endif
-+
-+#ifndef SYMTAB_DISCARD
-+#define SYMTAB_DISCARD
-+#define SYMTAB_DISCARD_GPL
-+#endif
-+
- /* Align . function alignment. */
- #define ALIGN_FUNCTION() . = ALIGN(CONFIG_FUNCTION_ALIGNMENT)
-
-@@ -486,14 +496,14 @@
- /* Kernel symbol table: Normal symbols */ \
- __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \
- __start___ksymtab = .; \
-- KEEP(*(SORT(___ksymtab+*))) \
-+ SYMTAB_KEEP \
- __stop___ksymtab = .; \
- } \
- \
- /* Kernel symbol table: GPL-only symbols */ \
- __ksymtab_gpl : AT(ADDR(__ksymtab_gpl) - LOAD_OFFSET) { \
- __start___ksymtab_gpl = .; \
-- KEEP(*(SORT(___ksymtab_gpl+*))) \
-+ SYMTAB_KEEP_GPL \
- __stop___ksymtab_gpl = .; \
- } \
- \
-@@ -513,7 +523,7 @@
- \
- /* Kernel symbol table: strings */ \
- __ksymtab_strings : AT(ADDR(__ksymtab_strings) - LOAD_OFFSET) { \
-- *(__ksymtab_strings) \
-+ *(__ksymtab_strings+*) \
- } \
- \
- /* __*init sections */ \
-@@ -1000,6 +1010,8 @@
- #define COMMON_DISCARDS \
- SANITIZER_DISCARDS \
- PATCHABLE_DISCARDS \
-+ SYMTAB_DISCARD \
-+ SYMTAB_DISCARD_GPL \
- *(.discard) \
- *(.discard.*) \
- *(.export_symbol) \
---- a/include/linux/export-internal.h
-+++ b/include/linux/export-internal.h
-@@ -26,6 +26,12 @@
- #define __KSYM_REF(sym) ".long " #sym
- #endif
-
-+#ifdef MODULE
-+#define __EXPORT_SUFFIX(sym)
-+#else
-+#define __EXPORT_SUFFIX(sym) "+" #sym
-+#endif
-+
- /*
- * For every exported symbol, do the following:
- *
-@@ -38,7 +44,7 @@
- * former apparently works on all arches according to the binutils source.
- */
- #define __KSYMTAB(name, sym, sec, ns) \
-- asm(" .section \"__ksymtab_strings\",\"aMS\",%progbits,1" "\n" \
-+ asm(" .section \"__ksymtab_strings" __EXPORT_SUFFIX(sym) "\",\"aMS\",%progbits,1" "\n" \
- "__kstrtab_" #name ":" "\n" \
- " .asciz \"" #name "\"" "\n" \
- "__kstrtabns_" #name ":" "\n" \
---- a/scripts/Makefile.build
-+++ b/scripts/Makefile.build
-@@ -366,7 +366,7 @@ targets += $(real-dtb-y) $(lib-y) $(alwa
- # Linker scripts preprocessor (.lds.S -> .lds)
- # ---------------------------------------------------------------------------
- quiet_cmd_cpp_lds_S = LDS $@
-- cmd_cpp_lds_S = $(CPP) $(cpp_flags) -P -U$(ARCH) \
-+ cmd_cpp_lds_S = $(CPP) $(EXTRA_LDSFLAGS) $(cpp_flags) -P -U$(ARCH) \
- -D__ASSEMBLY__ -DLINKER_SCRIPT -o $@ $<
-
- $(obj)/%.lds: $(src)/%.lds.S FORCE
#include <linux/mutex.h>
#include <linux/err.h>
#include <linux/property.h>
-@@ -3433,3 +3434,5 @@ static int __init regmap_initcall(void)
+@@ -3470,3 +3471,5 @@ static int __init regmap_initcall(void)
return 0;
}
postcore_initcall(regmap_initcall);
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -3353,6 +3353,9 @@ static int mv88e6xxx_setup_port(struct m
+@@ -3365,6 +3365,9 @@ static int mv88e6xxx_setup_port(struct m
else
reg = 1 << port;
*/
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -3080,6 +3080,10 @@ static inline int pskb_trim(struct sk_bu
+@@ -3095,6 +3095,10 @@ static inline int pskb_trim(struct sk_bu
return (len < skb->len) ? __pskb_trim(skb, len) : 0;
}
/**
* pskb_trim_unique - remove end from a paged unique (not cloned) buffer
* @skb: buffer to alter
-@@ -3245,16 +3249,6 @@ static inline struct sk_buff *dev_alloc_
+@@ -3260,16 +3264,6 @@ static inline struct sk_buff *dev_alloc_
}
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -101,6 +101,29 @@
- #define AQR107_OP_IN_PROG_SLEEP 1000
- #define AQR107_OP_IN_PROG_TIMEOUT 100000
+@@ -127,6 +127,29 @@ struct aqr107_priv {
+ u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
+ };
+/* registers in MDIO_MMD_VEND1 region */
+#define AQUANTIA_VND1_GLOBAL_SC 0x000
+#define AQUANTIA_VND1_GSYSCFG_5G 3
+#define AQUANTIA_VND1_GSYSCFG_10G 4
+
- struct aqr107_hw_stat {
- const char *name;
- int reg;
-@@ -232,6 +255,51 @@ static int aqr_config_aneg(struct phy_de
+ static int aqr107_get_sset_count(struct phy_device *phydev)
+ {
+ return AQR107_SGMII_STAT_SZ;
+@@ -233,6 +256,51 @@ static int aqr_config_aneg(struct phy_de
return genphy_c45_check_and_restart_aneg(phydev, changed);
}
static int aqr_config_intr(struct phy_device *phydev)
{
bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
-@@ -809,7 +877,7 @@ static struct phy_driver aqr_driver[] =
+@@ -838,7 +906,7 @@ static struct phy_driver aqr_driver[] =
PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
.name = "Aquantia AQR112",
.probe = aqr107_probe,
.config_intr = aqr_config_intr,
.handle_interrupt = aqr_handle_interrupt,
.get_tunable = aqr107_get_tunable,
-@@ -827,7 +895,7 @@ static struct phy_driver aqr_driver[] =
+@@ -863,7 +931,7 @@ static struct phy_driver aqr_driver[] =
PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
.name = "Aquantia AQR412",
.probe = aqr107_probe,
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -288,10 +288,16 @@ static int aqr_config_aneg_set_prot(stru
+@@ -289,10 +289,16 @@ static int aqr_config_aneg_set_prot(stru
phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
aquantia_syscfg[if_type].start_rate);
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
-@@ -29,6 +29,8 @@
- #define PHY_ID_AQR113 0x31c31c40
+@@ -30,6 +30,8 @@
#define PHY_ID_AQR113C 0x31c31c12
+ #define PHY_ID_AQR114C 0x31c31c22
#define PHY_ID_AQR813 0x31c31cb2
+#define PHY_ID_AQR112C 0x03a1b790
+#define PHY_ID_AQR112R 0x31c31d12
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
-@@ -972,6 +974,30 @@ static struct phy_driver aqr_driver[] =
- .get_stats = aqr107_get_stats,
- .link_change_notify = aqr107_link_change_notify,
+@@ -1062,6 +1064,30 @@ static struct phy_driver aqr_driver[] =
+ .led_polarity_set = aqr_phy_led_polarity_set,
+ #endif
},
+{
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C),
};
module_phy_driver(aqr_driver);
-@@ -991,6 +1017,8 @@ static struct mdio_device_id __maybe_unu
- { PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
+@@ -1082,6 +1108,8 @@ static struct mdio_device_id __maybe_unu
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR114C) },
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
+ { PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },
+++ /dev/null
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Wed, 27 Mar 2024 23:18:51 +0100
-Subject: [PATCH] mtd: don't look for OTP legacy NVMEM cells if proper node
- doesn't exist
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-If node with "user-otp" / "factory-otp" compatible doesn't exist it's
-important to prevent NVMEM core from looking for legacy NVMEM cells.
-Otherwise it would look for them in the device node.
-
-This fixes treating NAND controller attached chips as NVMEM cell.
-Problem example:
-[ 0.410107] nand: device found, Manufacturer ID: 0xc2, Chip ID: 0xdc
-[ 0.416531] nand: Macronix MX30LF4G18AC
-[ 0.420409] nand: 512 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
-[ 0.428022] iproc_nand 18028000.nand-controller: detected 512MiB total, 128KiB blocks, 2KiB pages, 16B OOB, 8-bit, BCH-8
-[ 0.438991] Scanning device for bad blocks
-(...)
-[ 2.848418] nvmem user-otp1: nvmem: invalid reg on /nand-controller@18028000/nand@0
-[ 2.856126] iproc_nand 18028000.nand-controller: error -EINVAL: Failed to register OTP NVMEM device
-
-This long standing issue was exposed by the support for Macronix OTP.
-
-Reported-by: Christian Marangi <ansuelsmth@gmail.com>
-Fixes: 4b361cfa8624 ("mtd: core: add OTP nvmem provider support")
-Fixes: e87161321a40 ("mtd: rawnand: macronix: OTP access for MX30LFxG18AC")
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
- drivers/mtd/mtdcore.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/drivers/mtd/mtdcore.c
-+++ b/drivers/mtd/mtdcore.c
-@@ -931,7 +931,7 @@ static struct nvmem_device *mtd_otp_nvme
- config.name = compatible;
- config.id = NVMEM_DEVID_AUTO;
- config.owner = THIS_MODULE;
-- config.add_legacy_fixed_of_cells = true;
-+ config.add_legacy_fixed_of_cells = !!np;
- config.type = NVMEM_TYPE_OTP;
- config.root_only = true;
- config.ignore_wp = true;
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -3047,7 +3047,7 @@ static inline int pskb_network_may_pull(
+@@ -3062,7 +3062,7 @@ static inline int pskb_network_may_pull(
* NET_IP_ALIGN(2) + ethernet_header(14) + IP_header(20/40) + ports(8)
*/
#ifndef NET_SKB_PAD
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Sat, 27 Apr 2024 18:54:25 +0200
-Subject: [PATCH] net: bridge: fix multicast-to-unicast with fraglist GSO
-
-Calling skb_copy on a SKB_GSO_FRAGLIST skb is not valid, since it returns
-an invalid linearized skb. This code only needs to change the ethernet
-header, so pskb_copy is the right function to call here.
-
-Fixes: 6db6f0eae605 ("bridge: multicast to unicast")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/net/bridge/br_forward.c
-+++ b/net/bridge/br_forward.c
-@@ -266,7 +266,7 @@ static void maybe_deliver_addr(struct ne
- if (skb->dev == p->dev && ether_addr_equal(src, addr))
- return;
-
-- skb = skb_copy(skb, GFP_ATOMIC);
-+ skb = pskb_copy(skb, GFP_ATOMIC);
- if (!skb) {
- DEV_STATS_INC(dev, tx_dropped);
- return;
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Sat, 27 Apr 2024 19:29:45 +0200
-Subject: [PATCH] net: core: reject skb_copy(_expand) for fraglist GSO skbs
-
-SKB_GSO_FRAGLIST skbs must not be linearized, otherwise they become
-invalid. Return NULL if such an skb is passed to skb_copy or
-skb_copy_expand, in order to prevent a crash on a potential later
-call to skb_gso_segment.
-
-Fixes: 3a1296a38d0c ("net: Support GRO/GSO fraglist chaining.")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/net/core/skbuff.c
-+++ b/net/core/skbuff.c
-@@ -1971,11 +1971,17 @@ static inline int skb_alloc_rx_flag(cons
-
- struct sk_buff *skb_copy(const struct sk_buff *skb, gfp_t gfp_mask)
- {
-- int headerlen = skb_headroom(skb);
-- unsigned int size = skb_end_offset(skb) + skb->data_len;
-- struct sk_buff *n = __alloc_skb(size, gfp_mask,
-- skb_alloc_rx_flag(skb), NUMA_NO_NODE);
-+ struct sk_buff *n;
-+ unsigned int size;
-+ int headerlen;
-
-+ if (WARN_ON_ONCE(skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST))
-+ return NULL;
-+
-+ headerlen = skb_headroom(skb);
-+ size = skb_end_offset(skb) + skb->data_len;
-+ n = __alloc_skb(size, gfp_mask,
-+ skb_alloc_rx_flag(skb), NUMA_NO_NODE);
- if (!n)
- return NULL;
-
-@@ -2303,12 +2309,17 @@ struct sk_buff *skb_copy_expand(const st
- /*
- * Allocate the copy buffer
- */
-- struct sk_buff *n = __alloc_skb(newheadroom + skb->len + newtailroom,
-- gfp_mask, skb_alloc_rx_flag(skb),
-- NUMA_NO_NODE);
-- int oldheadroom = skb_headroom(skb);
- int head_copy_len, head_copy_off;
-+ struct sk_buff *n;
-+ int oldheadroom;
-+
-+ if (WARN_ON_ONCE(skb_shinfo(skb)->gso_type & SKB_GSO_FRAGLIST))
-+ return NULL;
-
-+ oldheadroom = skb_headroom(skb);
-+ n = __alloc_skb(newheadroom + skb->len + newtailroom,
-+ gfp_mask, skb_alloc_rx_flag(skb),
-+ NUMA_NO_NODE);
- if (!n)
- return NULL;
-
+++ /dev/null
-From: Felix Fietkau <nbd@nbd.name>
-Date: Sun, 5 May 2024 20:36:56 +0200
-Subject: [PATCH] net: bridge: fix corrupted ethernet header on
- multicast-to-unicast
-
-The change from skb_copy to pskb_copy unfortunately changed the data
-copying to omit the ethernet header, since it was pulled before reaching
-this point. Fix this by calling __skb_push/pull around pskb_copy.
-
-Fixes: 59c878cbcdd8 ("net: bridge: fix multicast-to-unicast with fraglist GSO")
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
----
-
---- a/net/bridge/br_forward.c
-+++ b/net/bridge/br_forward.c
-@@ -258,6 +258,7 @@ static void maybe_deliver_addr(struct ne
- {
- struct net_device *dev = BR_INPUT_SKB_CB(skb)->brdev;
- const unsigned char *src = eth_hdr(skb)->h_source;
-+ struct sk_buff *nskb;
-
- if (!should_deliver(p, skb))
- return;
-@@ -266,12 +267,16 @@ static void maybe_deliver_addr(struct ne
- if (skb->dev == p->dev && ether_addr_equal(src, addr))
- return;
-
-- skb = pskb_copy(skb, GFP_ATOMIC);
-- if (!skb) {
-+ __skb_push(skb, ETH_HLEN);
-+ nskb = pskb_copy(skb, GFP_ATOMIC);
-+ __skb_pull(skb, ETH_HLEN);
-+ if (!nskb) {
- DEV_STATS_INC(dev, tx_dropped);
- return;
- }
-
-+ skb = nskb;
-+ __skb_pull(skb, ETH_HLEN);
- if (!is_broadcast_ether_addr(addr))
- memcpy(eth_hdr(skb)->h_dest, addr, ETH_ALEN);
-
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4981,6 +4981,8 @@ static int mtk_probe(struct platform_dev
+@@ -4984,6 +4984,8 @@ static int mtk_probe(struct platform_dev
* for NAPI to work
*/
init_dummy_netdev(ð->dummy_dev);
return -EMSGSIZE;
timerval = br_timer_value(&p->message_age_timer);
-@@ -901,6 +903,7 @@ static const struct nla_policy br_port_p
+@@ -902,6 +904,7 @@ static const struct nla_policy br_port_p
[IFLA_BRPORT_MCAST_MAX_GROUPS] = { .type = NLA_U32 },
[IFLA_BRPORT_NEIGH_VLAN_SUPPRESS] = NLA_POLICY_MAX(NLA_U8, 1),
[IFLA_BRPORT_BACKUP_NHID] = { .type = NLA_U32 },
};
/* Change the state of the port and notify spanning tree */
-@@ -969,6 +972,7 @@ static int br_setport(struct net_bridge_
+@@ -970,6 +973,7 @@ static int br_setport(struct net_bridge_
br_set_port_flag(p, tb, IFLA_BRPORT_MAB, BR_PORT_MAB);
br_set_port_flag(p, tb, IFLA_BRPORT_NEIGH_VLAN_SUPPRESS,
BR_NEIGH_VLAN_SUPPRESS);
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1326,6 +1326,22 @@ struct mtk_mac {
+@@ -1329,6 +1329,22 @@ struct mtk_mac {
/* the struct describing the SoC. these are declared in the soc_xyz.c files */
extern const struct of_device_id of_mtk_match[];
static inline bool mtk_is_netsys_v1(struct mtk_eth *eth)
{
return eth->soc->version == 1;
-@@ -1340,6 +1356,7 @@ static inline bool mtk_is_netsys_v3_or_g
+@@ -1343,6 +1359,7 @@ static inline bool mtk_is_netsys_v3_or_g
{
return eth->soc->version > 2;
}
#include <net/page_pool/helpers.h>
#include "mtk_eth_soc.h"
-@@ -1578,12 +1579,28 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1581,12 +1582,28 @@ static void mtk_wake_queue(struct mtk_et
}
}
bool gso = false;
int tx_num;
-@@ -1605,6 +1622,18 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1608,6 +1625,18 @@ static netdev_tx_t mtk_start_xmit(struct
return NETDEV_TX_BUSY;
}
/* TSO: fill MSS info in tcp checksum field */
if (skb_is_gso(skb)) {
if (skb_cow_head(skb, 0)) {
-@@ -1620,8 +1649,14 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1623,8 +1652,14 @@ static netdev_tx_t mtk_start_xmit(struct
}
}
.mac_finish = mtk_mac_finish,
.mac_link_down = mtk_mac_link_down,
.mac_link_up = mtk_mac_link_up,
-@@ -3390,6 +3531,9 @@ static int mtk_open(struct net_device *d
+@@ -3393,6 +3534,9 @@ static int mtk_open(struct net_device *d
struct mtk_eth *eth = mac->hw;
int i, err;
err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
if (err) {
netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
-@@ -3519,6 +3663,9 @@ static int mtk_stop(struct net_device *d
+@@ -3522,6 +3666,9 @@ static int mtk_stop(struct net_device *d
for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
mtk_ppe_stop(eth->ppe[i]);
return 0;
}
-@@ -4516,6 +4663,7 @@ static const struct net_device_ops mtk_n
+@@ -4519,6 +4666,7 @@ static const struct net_device_ops mtk_n
static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
{
const __be32 *_id = of_get_property(np, "reg", NULL);
phy_interface_t phy_mode;
struct phylink *phylink;
struct mtk_mac *mac;
-@@ -4552,16 +4700,41 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4555,16 +4703,41 @@ static int mtk_add_mac(struct mtk_eth *e
mac->id = id;
mac->hw = eth;
mac->of_node = np;
}
memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
-@@ -4644,8 +4817,21 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4647,8 +4820,21 @@ static int mtk_add_mac(struct mtk_eth *e
phy_interface_zero(mac->phylink_config.supported_interfaces);
__set_bit(PHY_INTERFACE_MODE_INTERNAL,
mac->phylink_config.supported_interfaces);
phylink = phylink_create(&mac->phylink_config,
of_fwnode_handle(mac->of_node),
phy_mode, &mtk_phylink_ops);
-@@ -4696,6 +4882,26 @@ free_netdev:
+@@ -4699,6 +4885,26 @@ free_netdev:
return err;
}
void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
{
struct net_device *dev, *tmp;
-@@ -4842,7 +5048,8 @@ static int mtk_probe(struct platform_dev
+@@ -4845,7 +5051,8 @@ static int mtk_probe(struct platform_dev
regmap_write(cci, 0, 3);
}
err = mtk_sgmii_init(eth);
if (err)
-@@ -4953,6 +5160,24 @@ static int mtk_probe(struct platform_dev
+@@ -4956,6 +5163,24 @@ static int mtk_probe(struct platform_dev
}
}
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
err = devm_request_irq(eth->dev, eth->irq[0],
mtk_handle_irq, 0,
-@@ -5055,6 +5280,11 @@ static int mtk_remove(struct platform_de
+@@ -5058,6 +5283,11 @@ static int mtk_remove(struct platform_de
mtk_stop(eth->netdev[i]);
mac = netdev_priv(eth->netdev[i]);
phylink_disconnect_phy(mac->phylink);
struct mtk_tx_dma_desc_info {
dma_addr_t addr;
-@@ -1314,6 +1371,9 @@ struct mtk_mac {
+@@ -1317,6 +1374,9 @@ struct mtk_mac {
struct device_node *of_node;
struct phylink *phylink;
struct phylink_config phylink_config;
struct mtk_eth *hw;
struct mtk_hw_stats *hw_stats;
__be32 hwlro_ip[MTK_MAX_LRO_IP_CNT];
-@@ -1437,6 +1497,19 @@ static inline u32 mtk_get_ib2_multicast_
+@@ -1440,6 +1500,19 @@ static inline u32 mtk_get_ib2_multicast_
return MTK_FOE_IB2_MULTICAST;
}
/* read the hardware status register */
void mtk_stats_update_mac(struct mtk_mac *mac);
-@@ -1445,8 +1518,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
+@@ -1448,8 +1521,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
--- /dev/null
+From c6a1759365fc35463138a7d9e335ee53f384b8df Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 10 May 2024 02:53:52 +0100
+Subject: [PATCH] net: phy: aquantia: add support for PHY LEDs
+
+Aquantia Ethernet PHYs got 3 LED output pins which are typically used
+to indicate link status and activity.
+Add a minimal LED controller driver supporting the most common uses
+with the 'netdev' trigger as well as software-driven forced control of
+the LEDs.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/phy/aquantia/Makefile | 3 +
+ drivers/net/phy/aquantia/aquantia.h | 84 +++++++++++++
+ drivers/net/phy/aquantia/aquantia_leds.c | 152 +++++++++++++++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c | 127 +++++++++++++------
+ 4 files changed, 329 insertions(+), 37 deletions(-)
+ create mode 100644 drivers/net/phy/aquantia/aquantia_leds.c
+
+--- a/drivers/net/phy/aquantia/Makefile
++++ b/drivers/net/phy/aquantia/Makefile
+@@ -3,4 +3,7 @@ aquantia-objs += aquantia_main.o aquan
+ ifdef CONFIG_HWMON
+ aquantia-objs += aquantia_hwmon.o
+ endif
++ifdef CONFIG_PHYLIB_LEDS
++aquantia-objs += aquantia_leds.o
++endif
+ obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
+--- a/drivers/net/phy/aquantia/aquantia.h
++++ b/drivers/net/phy/aquantia/aquantia.h
+@@ -62,6 +62,26 @@
+ #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL 0xc422
+ #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN 0xc423
+ #define VEND1_THERMAL_PROV_LOW_TEMP_WARN 0xc424
++
++#define AQR_NUM_LEDS 3
++
++#define VEND1_GLOBAL_LED_PROV 0xc430
++#define AQR_LED_PROV(x) (VEND1_GLOBAL_LED_PROV + x)
++#define VEND1_GLOBAL_LED_PROV_ACT_STRETCH GENMASK(0, 1)
++#define VEND1_GLOBAL_LED_PROV_TX_ACT BIT(2)
++#define VEND1_GLOBAL_LED_PROV_RX_ACT BIT(3)
++#define VEND1_GLOBAL_LED_PROV_LINK_MASK (GENMASK(15, 14) | GENMASK(8, 5))
++#define VEND1_GLOBAL_LED_PROV_LINK100 BIT(5)
++#define VEND1_GLOBAL_LED_PROV_LINK1000 BIT(6)
++#define VEND1_GLOBAL_LED_PROV_LINK10000 BIT(7)
++#define VEND1_GLOBAL_LED_PROV_FORCE_ON BIT(8)
++#define VEND1_GLOBAL_LED_PROV_LINK2500 BIT(14)
++#define VEND1_GLOBAL_LED_PROV_LINK5000 BIT(15)
++
++#define VEND1_GLOBAL_LED_DRIVE 0xc438
++#define VEND1_GLOBAL_LED_DRIVE_VDD BIT(1)
++#define AQR_LED_DRIVE(x) (VEND1_GLOBAL_LED_DRIVE + x)
++
+ #define VEND1_THERMAL_STAT1 0xc820
+ #define VEND1_THERMAL_STAT2 0xc821
+ #define VEND1_THERMAL_STAT2_VALID BIT(0)
+@@ -115,3 +135,23 @@ static inline int aqr_hwmon_probe(struct
+ #endif
+
+ int aqr_firmware_load(struct phy_device *phydev);
++
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++int aqr_phy_led_blink_set(struct phy_device *phydev, u8 index,
++ unsigned long *delay_on,
++ unsigned long *delay_off);
++
++int aqr_phy_led_brightness_set(struct phy_device *phydev,
++ u8 index, enum led_brightness value);
++
++int aqr_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
++ unsigned long rules);
++
++int aqr_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
++ unsigned long *rules);
++
++int aqr_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
++ unsigned long rules);
++
++int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes);
++#endif
+--- /dev/null
++++ b/drivers/net/phy/aquantia/aquantia_leds.c
+@@ -0,0 +1,140 @@
++// SPDX-License-Identifier: GPL-2.0
++/* LED driver for Aquantia PHY
++ *
++ * Author: Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/phy.h>
++
++#include "aquantia.h"
++
++int aqr_phy_led_brightness_set(struct phy_device *phydev,
++ u8 index, enum led_brightness value)
++{
++ if (index > 2)
++ return -EINVAL;
++
++ return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index), VEND1_GLOBAL_LED_PROV_LINK_MASK |
++ VEND1_GLOBAL_LED_PROV_FORCE_ON |
++ VEND1_GLOBAL_LED_PROV_RX_ACT |
++ VEND1_GLOBAL_LED_PROV_TX_ACT,
++ value ? VEND1_GLOBAL_LED_PROV_FORCE_ON : 0);
++}
++
++static const unsigned long supported_triggers = (BIT(TRIGGER_NETDEV_LINK) |
++ BIT(TRIGGER_NETDEV_LINK_100) |
++ BIT(TRIGGER_NETDEV_LINK_1000) |
++ BIT(TRIGGER_NETDEV_LINK_2500) |
++ BIT(TRIGGER_NETDEV_LINK_5000) |
++ BIT(TRIGGER_NETDEV_LINK_10000) |
++ BIT(TRIGGER_NETDEV_RX) |
++ BIT(TRIGGER_NETDEV_TX));
++
++int aqr_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
++ unsigned long rules)
++{
++ if (index >= AQR_NUM_LEDS)
++ return -EINVAL;
++
++ /* All combinations of the supported triggers are allowed */
++ if (rules & ~supported_triggers)
++ return -EOPNOTSUPP;
++
++ return 0;
++}
++
++int aqr_phy_led_hw_control_get(struct phy_device *phydev, u8 index,
++ unsigned long *rules)
++{
++ int val;
++
++ if (index >= AQR_NUM_LEDS)
++ return -EINVAL;
++
++ val = phy_read_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index));
++ if (val < 0)
++ return val;
++
++ *rules = 0;
++ if (val & VEND1_GLOBAL_LED_PROV_LINK100)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_100);
++
++ if (val & VEND1_GLOBAL_LED_PROV_LINK1000)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_1000);
++
++ if (val & VEND1_GLOBAL_LED_PROV_LINK2500)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_2500);
++
++ if (val & VEND1_GLOBAL_LED_PROV_LINK5000)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_5000);
++
++ if (val & VEND1_GLOBAL_LED_PROV_LINK10000)
++ *rules |= BIT(TRIGGER_NETDEV_LINK_10000);
++
++ if (val & VEND1_GLOBAL_LED_PROV_RX_ACT)
++ *rules |= BIT(TRIGGER_NETDEV_RX);
++
++ if (val & VEND1_GLOBAL_LED_PROV_TX_ACT)
++ *rules |= BIT(TRIGGER_NETDEV_TX);
++
++ return 0;
++}
++
++int aqr_phy_led_hw_control_set(struct phy_device *phydev, u8 index,
++ unsigned long rules)
++{
++ u16 val = 0;
++
++ if (index >= AQR_NUM_LEDS)
++ return -EINVAL;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
++ val |= VEND1_GLOBAL_LED_PROV_LINK100;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
++ val |= VEND1_GLOBAL_LED_PROV_LINK1000;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
++ val |= VEND1_GLOBAL_LED_PROV_LINK2500;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_5000) | BIT(TRIGGER_NETDEV_LINK)))
++ val |= VEND1_GLOBAL_LED_PROV_LINK5000;
++
++ if (rules & (BIT(TRIGGER_NETDEV_LINK_10000) | BIT(TRIGGER_NETDEV_LINK)))
++ val |= VEND1_GLOBAL_LED_PROV_LINK10000;
++
++ if (rules & BIT(TRIGGER_NETDEV_RX))
++ val |= VEND1_GLOBAL_LED_PROV_RX_ACT;
++
++ if (rules & BIT(TRIGGER_NETDEV_TX))
++ val |= VEND1_GLOBAL_LED_PROV_TX_ACT;
++
++ return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_PROV(index),
++ VEND1_GLOBAL_LED_PROV_LINK_MASK |
++ VEND1_GLOBAL_LED_PROV_FORCE_ON |
++ VEND1_GLOBAL_LED_PROV_RX_ACT |
++ VEND1_GLOBAL_LED_PROV_TX_ACT, val);
++}
++
++int aqr_phy_led_polarity_set(struct phy_device *phydev, int index, unsigned long modes)
++{
++ bool active_low = false;
++ u32 mode;
++
++ if (index >= AQR_NUM_LEDS)
++ return -EINVAL;
++
++ for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
++ switch (mode) {
++ case PHY_LED_ACTIVE_LOW:
++ active_low = true;
++ break;
++ default:
++ return -EINVAL;
++ }
++ }
++
++ return phy_modify_mmd(phydev, MDIO_MMD_VEND1, AQR_LED_DRIVE(index),
++ VEND1_GLOBAL_LED_DRIVE_VDD,
++ active_low ? VEND1_GLOBAL_LED_DRIVE_VDD : 0);
++}
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -740,6 +740,13 @@ static struct phy_driver aqr_driver[] =
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++ .led_brightness_set = aqr_phy_led_brightness_set,
++ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
++ .led_hw_control_set = aqr_phy_led_hw_control_set,
++ .led_hw_control_get = aqr_phy_led_hw_control_get,
++ .led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
+@@ -759,6 +766,13 @@ static struct phy_driver aqr_driver[] =
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++ .led_brightness_set = aqr_phy_led_brightness_set,
++ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
++ .led_hw_control_set = aqr_phy_led_hw_control_set,
++ .led_hw_control_get = aqr_phy_led_hw_control_get,
++ .led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR111),
+@@ -778,6 +792,13 @@ static struct phy_driver aqr_driver[] =
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++ .led_brightness_set = aqr_phy_led_brightness_set,
++ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
++ .led_hw_control_set = aqr_phy_led_hw_control_set,
++ .led_hw_control_get = aqr_phy_led_hw_control_get,
++ .led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0),
+@@ -797,6 +818,13 @@ static struct phy_driver aqr_driver[] =
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++ .led_brightness_set = aqr_phy_led_brightness_set,
++ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
++ .led_hw_control_set = aqr_phy_led_hw_control_set,
++ .led_hw_control_get = aqr_phy_led_hw_control_get,
++ .led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
+@@ -823,6 +851,13 @@ static struct phy_driver aqr_driver[] =
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++ .led_brightness_set = aqr_phy_led_brightness_set,
++ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
++ .led_hw_control_set = aqr_phy_led_hw_control_set,
++ .led_hw_control_get = aqr_phy_led_hw_control_get,
++ .led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
+@@ -841,6 +876,13 @@ static struct phy_driver aqr_driver[] =
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++ .led_brightness_set = aqr_phy_led_brightness_set,
++ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
++ .led_hw_control_set = aqr_phy_led_hw_control_set,
++ .led_hw_control_get = aqr_phy_led_hw_control_get,
++ .led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
+@@ -860,6 +902,13 @@ static struct phy_driver aqr_driver[] =
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++ .led_brightness_set = aqr_phy_led_brightness_set,
++ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
++ .led_hw_control_set = aqr_phy_led_hw_control_set,
++ .led_hw_control_get = aqr_phy_led_hw_control_get,
++ .led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
+@@ -879,6 +928,13 @@ static struct phy_driver aqr_driver[] =
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++ .led_brightness_set = aqr_phy_led_brightness_set,
++ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
++ .led_hw_control_set = aqr_phy_led_hw_control_set,
++ .led_hw_control_get = aqr_phy_led_hw_control_get,
++ .led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR114C),
+@@ -898,6 +954,13 @@ static struct phy_driver aqr_driver[] =
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++ .led_brightness_set = aqr_phy_led_brightness_set,
++ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
++ .led_hw_control_set = aqr_phy_led_hw_control_set,
++ .led_hw_control_get = aqr_phy_led_hw_control_get,
++ .led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ {
+ PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
+@@ -917,6 +980,13 @@ static struct phy_driver aqr_driver[] =
+ .get_strings = aqr107_get_strings,
+ .get_stats = aqr107_get_stats,
+ .link_change_notify = aqr107_link_change_notify,
++#if IS_ENABLED(CONFIG_PHYLIB_LEDS)
++ .led_brightness_set = aqr_phy_led_brightness_set,
++ .led_hw_is_supported = aqr_phy_led_hw_is_supported,
++ .led_hw_control_set = aqr_phy_led_hw_control_set,
++ .led_hw_control_get = aqr_phy_led_hw_control_get,
++ .led_polarity_set = aqr_phy_led_polarity_set,
++#endif
+ },
+ };
+
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -6935,6 +6935,7 @@ static int mv88e6xxx_register_switch(str
+@@ -6947,6 +6947,7 @@ static int mv88e6xxx_register_switch(str
ds->ops = &mv88e6xxx_switch_ops;
ds->ageing_time_min = chip->info->age_time_coeff;
ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
+++ /dev/null
-From 4a44a52f16ccd3d03e0cb5fb437a5eb31a5f9f05 Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Mon, 26 Feb 2024 21:39:34 +0100
-Subject: [PATCH] net l2tp: drop flow hash on forward
-
-Drop the flow-hash of the skb when forwarding to the L2TP netdev.
-
-This avoids the L2TP qdisc from using the flow-hash from the outer
-packet, which is identical for every flow within the tunnel.
-
-This does not affect every platform but is specific for the ethernet
-driver. It depends on the platform including L4 information in the
-flow-hash.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- net/l2tp/l2tp_eth.c | 3 +++
- 1 file changed, 3 insertions(+)
-
---- a/net/l2tp/l2tp_eth.c
-+++ b/net/l2tp/l2tp_eth.c
-@@ -136,6 +136,9 @@ static void l2tp_eth_dev_recv(struct l2t
- /* checksums verified by L2TP */
- skb->ip_summed = CHECKSUM_NONE;
-
-+ /* drop outer flow-hash */
-+ skb_clear_hash(skb);
-+
- skb_dst_drop(skb);
- nf_reset_ct(skb);
-
--- /dev/null
+From 6e6fff51ae5e54092611d174fa45fa78c237a415 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 21 May 2024 20:01:46 +0200
+Subject: [PATCH] net: phy: move LED polarity to phy_init_hw
+
+Some PHY reset the polarity on reset and this cause the LED to
+malfunction as LED polarity is configured only when LED is
+registered.
+
+To better handle this, move the LED polarity configuration in
+phy_init_hw to reconfigure it after PHY reset.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ drivers/net/phy/phy_device.c | 53 +++++++++++++++++++++++++-----------
+ 1 file changed, 37 insertions(+), 16 deletions(-)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1223,6 +1223,37 @@ static int phy_poll_reset(struct phy_dev
+ return 0;
+ }
+
++static int of_phy_led_init(struct phy_device *phydev)
++{
++ struct phy_led *phyled;
++
++ list_for_each_entry(phyled, &phydev->leds, list) {
++ struct led_classdev *cdev = &phyled->led_cdev;
++ struct device_node *np = cdev->dev->of_node;
++ unsigned long modes = 0;
++ int err;
++
++ if (of_property_read_bool(np, "active-low"))
++ set_bit(PHY_LED_ACTIVE_LOW, &modes);
++ if (of_property_read_bool(np, "inactive-high-impedance"))
++ set_bit(PHY_LED_INACTIVE_HIGH_IMPEDANCE, &modes);
++
++ if (!modes)
++ continue;
++
++ /* Return error if asked to set polarity modes but not supported */
++ if (!phydev->drv->led_polarity_set)
++ return -EINVAL;
++
++ err = phydev->drv->led_polarity_set(phydev, phyled->index,
++ modes);
++ if (err)
++ return err;
++ }
++
++ return 0;
++}
++
+ int phy_init_hw(struct phy_device *phydev)
+ {
+ int ret = 0;
+@@ -1259,6 +1290,12 @@ int phy_init_hw(struct phy_device *phyde
+ return ret;
+ }
+
++ if (IS_ENABLED(CONFIG_PHYLIB_LEDS)) {
++ ret = of_phy_led_init(phydev);
++ if (ret < 0)
++ return ret;
++ }
++
+ return 0;
+ }
+ EXPORT_SYMBOL(phy_init_hw);
+@@ -3204,7 +3241,6 @@ static int of_phy_led(struct phy_device
+ struct device *dev = &phydev->mdio.dev;
+ struct led_init_data init_data = {};
+ struct led_classdev *cdev;
+- unsigned long modes = 0;
+ struct phy_led *phyled;
+ u32 index;
+ int err;
+@@ -3222,21 +3258,6 @@ static int of_phy_led(struct phy_device
+ if (index > U8_MAX)
+ return -EINVAL;
+
+- if (of_property_read_bool(led, "active-low"))
+- set_bit(PHY_LED_ACTIVE_LOW, &modes);
+- if (of_property_read_bool(led, "inactive-high-impedance"))
+- set_bit(PHY_LED_INACTIVE_HIGH_IMPEDANCE, &modes);
+-
+- if (modes) {
+- /* Return error if asked to set polarity modes but not supported */
+- if (!phydev->drv->led_polarity_set)
+- return -EINVAL;
+-
+- err = phydev->drv->led_polarity_set(phydev, index, modes);
+- if (err)
+- return err;
+- }
+-
+ phyled->index = index;
+ if (phydev->drv->led_brightness_set)
+ cdev->brightness_set_blocking = phy_led_set_brightness;
$(call Device/FitImage)
DEVICE_VENDOR := EnGenius
DEVICE_MODEL := EAP1300
+ DEVICE_ALT0_VENDOR := EnGenius
+ DEVICE_ALT0_MODEL := EAP1300EXT
DEVICE_DTS_CONFIG := config@4
BOARD_NAME := eap1300
SOC := qcom-ipq4018
+#endif
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
-@@ -4642,6 +4642,9 @@ enum skb_ext_id {
+@@ -4657,6 +4657,9 @@ enum skb_ext_id {
#if IS_ENABLED(CONFIG_MCTP_FLOWS)
SKB_EXT_MCTP,
#endif
+ }
+ }
+
-+ panic("PSGMII work is unstable !!! "
++ dev_err(priv->dev, "PSGMII work is unstable !!! "
+ "Repeated recalibration attempts did not help(0x%x) !\n",
+ test_result);
+
&pcie0 {
status = "okay";
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
bridge@0,0 {
reg = <0x0 0 0 0 0>;
#address-cells = <3>;
&pcie1 {
status = "okay";
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
bridge@0,0 {
reg = <0x0 0 0 0 0>;
#address-cells = <3>;
&pcie2 {
status = "okay";
- /delete-property/ pinctrl-0;
- /delete-property/ pinctrl-names;
- /delete-property/ perst-gpios;
-
bridge@0,0 {
reg = <0x0 0 0 0 0>;
#address-cells = <3>;
ARCH:=armeb
BOARD:=ixp4xx
BOARDNAME:=Intel XScale IXP4xx
-FEATURES:=dt squashfs gpio
+FEATURES:=dt squashfs gpio ext4 rootfs-part
CPU_TYPE:=xscale
SUBTARGETS:=generic
-KERNEL_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.6
define Target/Description
Build firmware images for the IXP4xx XScale CPU
board_config_update
case "$(board_name)" in
+freecom,fsg-3|\
gateworks,gw2348|\
gateworks,gw2358)
ucidef_set_interfaces_lan_wan "eth0" "eth1"
;;
+dlink,dsm-g600-a|\
+iom,nas-100d|\
linksys,nslu2)
ucidef_set_interface_lan "eth0" "dhcp"
;;
+++ /dev/null
-CONFIG_ALIGNMENT_TRAP=y
-CONFIG_AMD_PHY=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_IXP4XX=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MULTIPLATFORM=y
-CONFIG_ARCH_MULTI_CPU_AUTO=y
-# CONFIG_ARCH_MULTI_V4 is not set
-# CONFIG_ARCH_MULTI_V4T is not set
-CONFIG_ARCH_MULTI_V4_V5=y
-CONFIG_ARCH_MULTI_V5=y
-CONFIG_ARCH_NR_GPIO=0
-CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARM=y
-CONFIG_ARM_APPENDED_DTB=y
-# CONFIG_ARM_ATAG_DTB_COMPAT is not set
-CONFIG_ARM_HAS_GROUP_RELOCS=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_PATCH_PHYS_VIRT=y
-CONFIG_ARM_THUMB=y
-CONFIG_ARM_UNWIND=y
-CONFIG_ATA=y
-CONFIG_ATAGS=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKSRC_MMIO=y
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_BIG_ENDIAN=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_CPU_ENDIAN_BE32=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_THUMB_CAPABLE=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_USE_DOMAINS=y
-CONFIG_CPU_XSCALE=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_DEV_IXP4XX=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_HW=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_DES=m
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
-CONFIG_DEBUG_UART_8250=y
-CONFIG_DEBUG_UART_8250_SHIFT=2
-CONFIG_DEBUG_UART_PHYS=0xc8000003
-CONFIG_DEBUG_UART_VIRT=0xfec00003
-CONFIG_DMA_OPS=y
-CONFIG_DTC=y
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-# CONFIG_FARSYNC is not set
-CONFIG_FIXED_PHY=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FORCE_PCI=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FWNODE_MDIO=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_IDLE_POLL_SETUP=y
-CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_GENERIC=y
-CONFIG_GPIO_GW_PLD=y
-CONFIG_GPIO_IXP4XX=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HDLC=y
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_IXP4XX=y
-CONFIG_HZ_FIXED=0
-CONFIG_HZ_PERIODIC=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_GPIO=y
-CONFIG_I2C_IOP3XX=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INTEL_IXP4XX_EB=y
-CONFIG_IRQCHIP=y
-CONFIG_IRQSTACKS=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_IWMMXT is not set
-CONFIG_IXP4XX_ETH=y
-CONFIG_IXP4XX_HSS=y
-CONFIG_IXP4XX_IRQ=y
-CONFIG_IXP4XX_NPE=y
-CONFIG_IXP4XX_QMGR=y
-CONFIG_IXP4XX_TIMER=y
-CONFIG_IXP4XX_WATCHDOG=y
-CONFIG_JBD2=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MDIO_BUS=y
-CONFIG_MDIO_DEVICE=y
-CONFIG_MDIO_DEVRES=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_OTP=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_IXP4XX=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_SPLIT_FIRMWARE=y
-CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NEED_KUSER_HELPERS=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6060=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NET_SELFTESTS=y
-CONFIG_NET_VENDOR_XSCALE=y
-CONFIG_NLS=y
-CONFIG_NVMEM=y
-CONFIG_NVMEM_SYSFS=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_GPIO=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_OF_MDIO=y
-# CONFIG_OLD_SIGACTION is not set
-# CONFIG_OLD_SIGSUSPEND3 is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PATA_IXP4XX_CF=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DOMAINS_GENERIC=y
-CONFIG_PCI_IXP4XX=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYLIB=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_GPIO=y
-CONFIG_PREEMPT_NONE_BUILD=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_REALTEK_PHY=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RUST_IS_AVAILABLE=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-# CONFIG_SERIAL_8250_EXAR is not set
-# CONFIG_SERIAL_8250_FSL is not set
-# CONFIG_SERIAL_8250_PCI is not set
-# CONFIG_SERIAL_8250_PERICOM is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SG_POOL=y
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-CONFIG_SRCU=y
-CONFIG_SWPHY=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TINY_SRCU=y
-CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UNWINDER_ARM=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
-CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PCI=y
-# CONFIG_USB_OHCI_HCD_PLATFORM is not set
-CONFIG_USB_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_UHCI_HCD=y
-CONFIG_USE_OF=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_WAN=y
-CONFIG_WATCHDOG_CORE=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-CONFIG_XZ_DEC_ARM=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_ZBOOT_ROM_TEXT=0x0
--- /dev/null
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_AMD_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_IXP4XX=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_CPU_AUTO=y
+# CONFIG_ARCH_MULTI_V4 is not set
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V4_V5=y
+CONFIG_ARCH_MULTI_V5=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+# CONFIG_ARM_ATAG_DTB_COMPAT is not set
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_ENDIAN_BE32=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_USE_DOMAINS=y
+CONFIG_CPU_XSCALE=y
+CONFIG_CRC16=y
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_DEV_IXP4XX=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=m
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="debug/8250.S"
+CONFIG_DEBUG_UART_8250=y
+CONFIG_DEBUG_UART_8250_SHIFT=2
+CONFIG_DEBUG_UART_PHYS=0xc8000003
+CONFIG_DEBUG_UART_VIRT=0xfec00003
+CONFIG_DMA_OPS=y
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+# CONFIG_FARSYNC is not set
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FORCE_PCI=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GW_PLD=y
+CONFIG_GPIO_IXP4XX=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HDLC=y
+CONFIG_HWMON=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_IXP4XX=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_IOP3XX=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INTEL_IXP4XX_EB=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_IWMMXT is not set
+CONFIG_IXP4XX_ETH=y
+CONFIG_IXP4XX_HSS=y
+CONFIG_IXP4XX_IRQ=y
+CONFIG_IXP4XX_NPE=y
+CONFIG_IXP4XX_QMGR=y
+CONFIG_IXP4XX_TIMER=y
+CONFIG_IXP4XX_WATCHDOG=y
+CONFIG_JBD2=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MIGRATION=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_OTP=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_IXP4XX=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIRMWARE_NAME="linux"
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MV88E6060=y
+CONFIG_NET_DSA_TAG_TRAILER=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_VENDOR_XSCALE=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PATA_IXP4XX_CF=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_IXP4XX=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RATIONAL=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SG_POOL=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SWPHY=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_EHCI_BIG_ENDIAN_DESC=y
+CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+# CONFIG_USB_OHCI_HCD_PLATFORM is not set
+CONFIG_USB_PCI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_UHCI_HCD=y
+CONFIG_USE_OF=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_WAN=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ZBOOT_ROM_TEXT=0x0
mv $@.new $@
endef
+define Build/freecom-image
+ mkdir -p $@.tmptar
+ # Add kernel
+ cp $@ $@.tmptar/zImage
+ cd $@.tmptar && tar -c -j -f $@.new --numeric-owner --owner=0 --group=0 *
+ rm -rf $@.tmptar
+ encode_crc $@.new $@
+ rm -f $@.new
+endef
+
# Build sysupgrade image
define BuildFirmware/Generic
dd if=$(KDIR)/zImage of=$(KDIR)/zImage.pad bs=64k conv=sync; \
define Device/Default
PROFILES := Default
+ DEVICE_DTS_DIR = $$(DTS_DIR)/intel/ixp
KERNEL_DEPENDS = $$(wildcard $(DTS_DIR)/$$(DEVICE_DTS).dts)
KERNEL_NAME := zImage
KERNEL := kernel-bin | append-dtb
BLOCKSIZE := 128k
endef
+define Device/dlink_dsm_g600_a
+ DEVICE_VENDOR := D-Link
+ DEVICE_MODEL := DSM G600 A
+ DEVICE_PACKAGES := ixp4xx-microcode-ethernet kmod-rtc-pcf8563 kmod-via-velocity kmod-ata-artop kmod-ath5k wpad-basic-mbedtls
+ DEVICE_DTS := intel-ixp42x-dlink-dsm-g600
+ KERNEL := kernel-bin | append-dtb
+ IMAGES := kernel.bin rootfs.bin
+ IMAGE/kernel.bin := append-kernel
+ IMAGE/rootfs.bin := append-rootfs | pad-rootfs | pad-to 128k
+endef
+TARGET_DEVICES += dlink_dsm_g600_a
+
+define Device/freecom_fsg_3
+ DEVICE_VENDOR := Freecom
+ DEVICE_MODEL := FSG-3
+ DEVICE_PACKAGES := ixp4xx-microcode-ethernet kmod-rtc-isl1208 kmod-ath5k wpad-basic-mbedtls
+ # Only 4 MB of Flash so not building by default
+ DEFAULT := n
+ DEVICE_DTS := intel-ixp42x-freecom-fsg-3
+ KERNEL := kernel-bin | append-dtb
+ IMAGES := factory.bin
+ # This has to boot from harddisk so just append the kernel
+ IMAGE/factory.bin := append-kernel | freecom-image
+endef
+TARGET_DEVICES += freecom_fsg_3
+
define Device/gateworks_avila
DEVICE_VENDOR := Gateworks
DEVICE_MODEL := Avila GW2348-4
endef
TARGET_DEVICES += gateworks_cambria
+define Device/iomega_nas100d
+ DEVICE_VENDOR := Iomega
+ DEVICE_MODEL := NAS100d
+ # USB2 is compiled in and needs no package
+ DEVICE_PACKAGES := ixp4xx-microcode-ethernet kmod-rtc-pcf8563
+ DEVICE_DTS := intel-ixp42x-iomega-nas100d
+ KERNEL := kernel-bin | append-dtb
+ IMAGES := factory.bin
+ # This has to boot from harddisk so just append the kernel
+ IMAGE/factory.bin := append-kernel | linksys-ixp425-image "nas100d"
+endef
+TARGET_DEVICES += iomega_nas100d
+
define Device/linksys_nslu2
DEVICE_VENDOR := Linksys
DEVICE_MODEL := NSLU2
+++ /dev/null
-From fc58944733a2082e3290eda240eb3247a00ad73a Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Thu, 21 Sep 2023 00:12:42 +0200
-Subject: [PATCH] gpio: ixp4xx: Handle clock output on pin 14 and 15
-
-This makes it possible to provide basic clock output on pins
-14 and 15. The clocks are typically used by random electronics,
-not modeled in the device tree, so they just need to be provided
-on request.
-
-In order to not disturb old systems that require that the
-hardware defaults are kept in the clock setting bits, we only
-manipulate these if either device tree property is present.
-Once we know a device needs one of the clocks we can set it
-in the device tree.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/gpio/gpio-ixp4xx.c | 49 +++++++++++++++++++++++++++++++++++++-
- 1 file changed, 48 insertions(+), 1 deletion(-)
-
---- a/drivers/gpio/gpio-ixp4xx.c
-+++ b/drivers/gpio/gpio-ixp4xx.c
-@@ -38,6 +38,18 @@
- #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)
- #define IXP4XX_GPIO_STYLE_SIZE 3
-
-+/*
-+ * Clock output control register defines.
-+ */
-+#define IXP4XX_GPCLK_CLK0DC_SHIFT 0
-+#define IXP4XX_GPCLK_CLK0TC_SHIFT 4
-+#define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0)
-+#define IXP4XX_GPCLK_MUX14 BIT(8)
-+#define IXP4XX_GPCLK_CLK1DC_SHIFT 16
-+#define IXP4XX_GPCLK_CLK1TC_SHIFT 20
-+#define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16)
-+#define IXP4XX_GPCLK_MUX15 BIT(24)
-+
- /**
- * struct ixp4xx_gpio - IXP4 GPIO state container
- * @dev: containing device for this instance
-@@ -203,6 +215,8 @@ static int ixp4xx_gpio_probe(struct plat
- struct ixp4xx_gpio *g;
- struct gpio_irq_chip *girq;
- struct device_node *irq_parent;
-+ bool clk_14, clk_15;
-+ u32 val;
- int ret;
-
- g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
-@@ -233,7 +247,40 @@ static int ixp4xx_gpio_probe(struct plat
- */
- if (of_machine_is_compatible("dlink,dsm-g600-a") ||
- of_machine_is_compatible("iom,nas-100d"))
-- __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
-+ val = 0;
-+ else
-+ val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
-+
-+ /*
-+ * If either clock output is enabled explicitly in the device tree
-+ * we take full control of the clock by masking off all bits for
-+ * the clock control and selectively enabling them. Otherwise
-+ * we leave the hardware default settings.
-+ *
-+ * Enable clock outputs with default timings of requested clock.
-+ * If you need control over TC and DC, add these to the device
-+ * tree bindings and use them here.
-+ */
-+ clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");
-+ clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");
-+ if (clk_14 || clk_15) {
-+ val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);
-+ val &= ~IXP4XX_GPCLK_CLK0_MASK;
-+ val &= ~IXP4XX_GPCLK_CLK1_MASK;
-+ if (clk_14) {
-+ val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT);
-+ val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);
-+ val |= IXP4XX_GPCLK_MUX14;
-+ }
-+
-+ if (clk_15) {
-+ val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT);
-+ val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);
-+ val |= IXP4XX_GPCLK_MUX15;
-+ }
-+ }
-+
-+ __raw_writel(val, g->base + IXP4XX_REG_GPCLK);
-
- /*
- * This is a very special big-endian ARM issue: when the IXP4xx is
+++ /dev/null
-From 02693ffdb93bffcbe772bd91a399dabd123b8c19 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Tue, 19 Sep 2023 16:02:15 +0200
-Subject: [PATCH 4/4] ARM: dts: ixp4xx: Add USRobotics USR8200 device tree
-
-This is a USRobotics NAS/Firewall/router that has been supported
-by OpenWrt in the past. It had dedicated users so let's get it
-properly supported.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/dts/Makefile | 3 +-
- .../dts/intel-ixp42x-usrobotics-usr8200.dts | 229 ++++++++++++++++++
- 2 files changed, 231 insertions(+), 1 deletion(-)
- create mode 100644 arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-
---- a/arch/arm/boot/dts/Makefile
-+++ b/arch/arm/boot/dts/Makefile
-@@ -292,7 +292,8 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
- intel-ixp43x-gateworks-gw2358.dtb \
- intel-ixp42x-netgear-wg302v1.dtb \
- intel-ixp42x-arcom-vulcan.dtb \
-- intel-ixp42x-gateway-7001.dtb
-+ intel-ixp42x-gateway-7001.dtb \
-+ intel-ixp42x-usrobotics-usr8200.dtb
- dtb-$(CONFIG_ARCH_KEYSTONE) += \
- keystone-k2hk-evm.dtb \
- keystone-k2l-evm.dtb \
---- /dev/null
-+++ b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-@@ -0,0 +1,229 @@
-+// SPDX-License-Identifier: ISC
-+/*
-+ * Device Tree file for the USRobotics USR8200 firewall
-+ * VPN and NAS. Based on know-how from Peter Denison.
-+ *
-+ * This machine is based on IXP422, the USR internal codename
-+ * is "Jeeves".
-+ */
-+
-+/dts-v1/;
-+
-+#include "intel-ixp42x.dtsi"
-+#include <dt-bindings/input/input.h>
-+
-+/ {
-+ model = "USRobotics USR8200";
-+ compatible = "usr,usr8200", "intel,ixp42x";
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ memory@0 {
-+ device_type = "memory";
-+ reg = <0x00000000 0x4000000>;
-+ };
-+
-+ chosen {
-+ bootargs = "console=ttyS0,115200n8";
-+ stdout-path = "uart1:115200n8";
-+ };
-+
-+ aliases {
-+ /* These are switched around */
-+ serial0 = &uart1;
-+ serial1 = &uart0;
-+ };
-+
-+ leds {
-+ compatible = "gpio-leds";
-+ ieee1394_led: led-1394 {
-+ label = "usr8200:green:1394";
-+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ usb1_led: led-usb1 {
-+ label = "usr8200:green:usb1";
-+ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ usb2_led: led-usb2 {
-+ label = "usr8200:green:usb2";
-+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ wireless_led: led-wireless {
-+ /*
-+ * This LED is mounted inside the case but cannot be
-+ * seen from the outside: probably USR planned at one
-+ * point for the device to have a wireless card, then
-+ * changed their mind and didn't mount it, leaving the
-+ * LED in place.
-+ */
-+ label = "usr8200:green:wireless";
-+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
-+ default-state = "off";
-+ };
-+ pwr_led: led-pwr {
-+ label = "usr8200:green:pwr";
-+ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
-+ default-state = "on";
-+ linux,default-trigger = "heartbeat";
-+ };
-+ };
-+
-+ gpio_keys {
-+ compatible = "gpio-keys";
-+
-+ button-reset {
-+ wakeup-source;
-+ linux,code = <KEY_RESTART>;
-+ label = "reset";
-+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
-+ };
-+ };
-+
-+ soc {
-+ bus@c4000000 {
-+ flash@0,0 {
-+ compatible = "intel,ixp4xx-flash", "cfi-flash";
-+ bank-width = <2>;
-+ /* Enable writes on the expansion bus */
-+ intel,ixp4xx-eb-write-enable = <1>;
-+ /* 16 MB of Flash mapped in at CS0 */
-+ reg = <0 0x00000000 0x1000000>;
-+
-+ partitions {
-+ compatible = "redboot-fis";
-+ /* Eraseblock at 0x0fe0000 */
-+ fis-index-block = <0x7f>;
-+ };
-+ };
-+ rtc@2,0 {
-+ /* EPSON RTC7301 DG DIL-capsule */
-+ compatible = "epson,rtc7301dg";
-+ /*
-+ * These timing settings were found in the boardfile patch:
-+ * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
-+ * IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
-+ */
-+ intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
-+ intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
-+ intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
-+ intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
-+ intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
-+ intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
-+ intel,ixp4xx-eb-byte-access-on-halfword = <0>;
-+ intel,ixp4xx-eb-mux-address-and-data = <0>;
-+ intel,ixp4xx-eb-ahb-split-transfers = <0>;
-+ intel,ixp4xx-eb-write-enable = <1>;
-+ intel,ixp4xx-eb-byte-access = <1>;
-+ /* 512 bytes at CS2 */
-+ reg = <2 0x00000000 0x0000200>;
-+ reg-io-width = <1>;
-+ native-endian;
-+ /* FIXME: try to check if there is an IRQ for the RTC? */
-+ };
-+ };
-+
-+ pci@c0000000 {
-+ status = "okay";
-+
-+ /*
-+ * Taken from USR8200 boardfile from OpenWrt
-+ *
-+ * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
-+ * We assume the same IRQ for all pins on the remaining slots, that
-+ * is what the boardfile was doing.
-+ */
-+ #interrupt-cells = <1>;
-+ interrupt-map-mask = <0xf800 0 0 7>;
-+ interrupt-map =
-+ /* IDSEL 14 used for "Wireless" in the board file */
-+ <0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
-+ /* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
-+ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
-+ /* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
-+ <0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
-+ <0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
-+ <0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
-+ };
-+
-+ gpio@c8004000 {
-+ /* Enable clock out on GPIO 15 */
-+ intel,ixp4xx-gpio15-clkout;
-+ };
-+
-+ /* EthB WAN */
-+ ethernet@c8009000 {
-+ status = "okay";
-+ queue-rx = <&qmgr 3>;
-+ queue-txready = <&qmgr 20>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy9>;
-+
-+ mdio {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ phy9: ethernet-phy@9 {
-+ reg = <9>;
-+ };
-+
-+ /* The switch uses MDIO addresses 16 thru 31 */
-+ switch@16 {
-+ compatible = "marvell,mv88e6060";
-+ reg = <16>;
-+
-+ ports {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+
-+ port@0 {
-+ reg = <0>;
-+ label = "lan1";
-+ };
-+
-+ port@1 {
-+ reg = <1>;
-+ label = "lan2";
-+ };
-+
-+ port@2 {
-+ reg = <2>;
-+ label = "lan3";
-+ };
-+
-+ port@3 {
-+ reg = <3>;
-+ label = "lan4";
-+ };
-+
-+ port@5 {
-+ /* Port 5 is the CPU port according to the MV88E6060 datasheet */
-+ reg = <5>;
-+ phy-mode = "rgmii-id";
-+ ethernet = <ðc>;
-+ label = "cpu";
-+ fixed-link {
-+ speed = <100>;
-+ full-duplex;
-+ };
-+ };
-+ };
-+ };
-+ };
-+ };
-+
-+ /* EthC LAN connected to the Marvell DSA Switch */
-+ ethc: ethernet@c800a000 {
-+ status = "okay";
-+ queue-rx = <&qmgr 4>;
-+ queue-txready = <&qmgr 21>;
-+ phy-mode = "rgmii";
-+ fixed-link {
-+ speed = <100>;
-+ full-duplex;
-+ };
-+ };
-+ };
-+};
+++ /dev/null
-From 6599df775e2cbb4988bdf8239acf4fbec70e5ef9 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sat, 23 Sep 2023 20:38:22 +0200
-Subject: [PATCH 3/4] net: ixp4xx_eth: Support changing the MTU
-
-As we don't specify the MTU in the driver, the framework
-will fall back to 1500 bytes and this doesn't work very
-well when we try to attach a DSA switch:
-
- eth1: mtu greater than device maximum
- ixp4xx_eth c800a000.ethernet eth1: error -22 setting
- MTU to 1504 to include DSA overhead
-
-After locating an out-of-tree patch in OpenWrt I found
-suitable code to set the MTU on the interface and ported
-it and updated it. Now the MTU gets set properly.
-
-Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- drivers/net/ethernet/xscale/ixp4xx_eth.c | 65 +++++++++++++++++++++++-
- 1 file changed, 64 insertions(+), 1 deletion(-)
-
---- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
-+++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
-@@ -24,6 +24,7 @@
- #include <linux/dma-mapping.h>
- #include <linux/dmapool.h>
- #include <linux/etherdevice.h>
-+#include <linux/if_vlan.h>
- #include <linux/io.h>
- #include <linux/kernel.h>
- #include <linux/net_tstamp.h>
-@@ -63,7 +64,15 @@
-
- #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
- #define REGS_SIZE 0x1000
--#define MAX_MRU 1536 /* 0x600 */
-+
-+/* MRU is said to be 14320 in a code dump, the SW manual says that
-+ * MRU/MTU is 16320 and includes VLAN and ethernet headers.
-+ * See "IXP400 Software Programmer's Guide" section 10.3.2, page 161.
-+ *
-+ * FIXME: we have chosen the safe default (14320) but if you can test
-+ * jumboframes, experiment with 16320 and see what happens!
-+ */
-+#define MAX_MRU (14320 - VLAN_ETH_HLEN)
- #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
-
- #define NAPI_WEIGHT 16
-@@ -1182,6 +1191,54 @@ static void destroy_queues(struct port *
- }
- }
-
-+static int ixp4xx_do_change_mtu(struct net_device *dev, int new_mtu)
-+{
-+ struct port *port = netdev_priv(dev);
-+ struct npe *npe = port->npe;
-+ int framesize, chunks;
-+ struct msg msg = {};
-+
-+ /* adjust for ethernet headers */
-+ framesize = new_mtu + VLAN_ETH_HLEN;
-+ /* max rx/tx 64 byte chunks */
-+ chunks = DIV_ROUND_UP(framesize, 64);
-+
-+ msg.cmd = NPE_SETMAXFRAMELENGTHS;
-+ msg.eth_id = port->id;
-+
-+ /* Firmware wants to know buffer size in 64 byte chunks */
-+ msg.byte2 = chunks << 8;
-+ msg.byte3 = chunks << 8;
-+
-+ msg.byte4 = msg.byte6 = framesize >> 8;
-+ msg.byte5 = msg.byte7 = framesize & 0xff;
-+
-+ if (npe_send_recv_message(npe, &msg, "ETH_SET_MAX_FRAME_LENGTH"))
-+ return -EIO;
-+ netdev_dbg(dev, "set MTU on NPE %s to %d bytes\n",
-+ npe_name(npe), new_mtu);
-+
-+ return 0;
-+}
-+
-+static int ixp4xx_eth_change_mtu(struct net_device *dev, int new_mtu)
-+{
-+ int ret;
-+
-+ /* MTU can only be changed when the interface is up. We also
-+ * set the MTU from dev->mtu when opening the device.
-+ */
-+ if (dev->flags & IFF_UP) {
-+ ret = ixp4xx_do_change_mtu(dev, new_mtu);
-+ if (ret < 0)
-+ return ret;
-+ }
-+
-+ dev->mtu = new_mtu;
-+
-+ return 0;
-+}
-+
- static int eth_open(struct net_device *dev)
- {
- struct port *port = netdev_priv(dev);
-@@ -1232,6 +1289,8 @@ static int eth_open(struct net_device *d
- if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
- return -EIO;
-
-+ ixp4xx_do_change_mtu(dev, dev->mtu);
-+
- if ((err = request_queues(port)) != 0)
- return err;
-
-@@ -1374,6 +1433,7 @@ static int eth_close(struct net_device *
- static const struct net_device_ops ixp4xx_netdev_ops = {
- .ndo_open = eth_open,
- .ndo_stop = eth_close,
-+ .ndo_change_mtu = ixp4xx_eth_change_mtu,
- .ndo_start_xmit = eth_xmit,
- .ndo_set_rx_mode = eth_set_mcast_list,
- .ndo_eth_ioctl = eth_ioctl,
-@@ -1488,6 +1548,9 @@ static int ixp4xx_eth_probe(struct platf
- ndev->dev.dma_mask = dev->dma_mask;
- ndev->dev.coherent_dma_mask = dev->coherent_dma_mask;
-
-+ ndev->min_mtu = ETH_MIN_MTU;
-+ ndev->max_mtu = MAX_MRU;
-+
- netif_napi_add_weight(ndev, &port->napi, eth_poll, NAPI_WEIGHT);
-
- if (!(port->npe = npe_request(NPE_ID(port->id))))
+++ /dev/null
-From a1ab45966e5a21841af58742adf27725e523d303 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Sat, 14 Oct 2023 19:53:24 +0200
-Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
-
-The MV88E6060 switch has internal PHY registers at MDIO
-addresses 0x00..0x04. Tie each port to the corresponding
-PHY.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- .../dts/intel-ixp42x-usrobotics-usr8200.dts | 22 +++++++++++++++++++
- 1 file changed, 22 insertions(+)
-
---- a/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-+++ b/arch/arm/boot/dts/intel-ixp42x-usrobotics-usr8200.dts
-@@ -165,6 +165,24 @@
- #address-cells = <1>;
- #size-cells = <0>;
-
-+ /*
-+ * PHY 0..4 are internal to the MV88E6060 switch but appear
-+ * as independent devices.
-+ */
-+ phy0: ethernet-phy@0 {
-+ reg = <0>;
-+ };
-+ phy1: ethernet-phy@1 {
-+ reg = <1>;
-+ };
-+ phy2: ethernet-phy@2 {
-+ reg = <2>;
-+ };
-+ phy3: ethernet-phy@3 {
-+ reg = <3>;
-+ };
-+
-+ /* Altima AMI101L used by the WAN port */
- phy9: ethernet-phy@9 {
- reg = <9>;
- };
-@@ -181,21 +199,25 @@
- port@0 {
- reg = <0>;
- label = "lan1";
-+ phy-handle = <&phy0>;
- };
-
- port@1 {
- reg = <1>;
- label = "lan2";
-+ phy-handle = <&phy1>;
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
-+ phy-handle = <&phy2>;
- };
-
- port@3 {
- reg = <3>;
- label = "lan4";
-+ phy-handle = <&phy3>;
- };
-
- port@5 {
+++ /dev/null
-From 2792791a19f90b0141ed2e781599ba0a42a8cfd5 Mon Sep 17 00:00:00 2001
-From: Linus Walleij <linus.walleij@linaro.org>
-Date: Mon, 29 May 2023 23:32:44 +0200
-Subject: [PATCH] ARM: dts: ixp4xx: Boot NSLU2 from harddrive
-
-This enforces harddrive boot on the NSLU2. The flash is too small
-to hold any rootfs these days.
-
-Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
----
- arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
-+++ b/arch/arm/boot/dts/intel-ixp42x-linksys-nslu2.dts
-@@ -21,7 +21,7 @@
- };
-
- chosen {
-- bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
-+ bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
- stdout-path = "uart0:115200n8";
- };
-
--- /dev/null
+From fc58944733a2082e3290eda240eb3247a00ad73a Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Thu, 21 Sep 2023 00:12:42 +0200
+Subject: [PATCH] gpio: ixp4xx: Handle clock output on pin 14 and 15
+
+This makes it possible to provide basic clock output on pins
+14 and 15. The clocks are typically used by random electronics,
+not modeled in the device tree, so they just need to be provided
+on request.
+
+In order to not disturb old systems that require that the
+hardware defaults are kept in the clock setting bits, we only
+manipulate these if either device tree property is present.
+Once we know a device needs one of the clocks we can set it
+in the device tree.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/gpio/gpio-ixp4xx.c | 49 +++++++++++++++++++++++++++++++++++++-
+ 1 file changed, 48 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpio/gpio-ixp4xx.c
++++ b/drivers/gpio/gpio-ixp4xx.c
+@@ -38,6 +38,18 @@
+ #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0)
+ #define IXP4XX_GPIO_STYLE_SIZE 3
+
++/*
++ * Clock output control register defines.
++ */
++#define IXP4XX_GPCLK_CLK0DC_SHIFT 0
++#define IXP4XX_GPCLK_CLK0TC_SHIFT 4
++#define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0)
++#define IXP4XX_GPCLK_MUX14 BIT(8)
++#define IXP4XX_GPCLK_CLK1DC_SHIFT 16
++#define IXP4XX_GPCLK_CLK1TC_SHIFT 20
++#define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16)
++#define IXP4XX_GPCLK_MUX15 BIT(24)
++
+ /**
+ * struct ixp4xx_gpio - IXP4 GPIO state container
+ * @dev: containing device for this instance
+@@ -202,6 +214,8 @@ static int ixp4xx_gpio_probe(struct plat
+ struct ixp4xx_gpio *g;
+ struct gpio_irq_chip *girq;
+ struct device_node *irq_parent;
++ bool clk_14, clk_15;
++ u32 val;
+ int ret;
+
+ g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
+@@ -231,7 +245,40 @@ static int ixp4xx_gpio_probe(struct plat
+ */
+ if (of_machine_is_compatible("dlink,dsm-g600-a") ||
+ of_machine_is_compatible("iom,nas-100d"))
+- __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK);
++ val = 0;
++ else
++ val = __raw_readl(g->base + IXP4XX_REG_GPCLK);
++
++ /*
++ * If either clock output is enabled explicitly in the device tree
++ * we take full control of the clock by masking off all bits for
++ * the clock control and selectively enabling them. Otherwise
++ * we leave the hardware default settings.
++ *
++ * Enable clock outputs with default timings of requested clock.
++ * If you need control over TC and DC, add these to the device
++ * tree bindings and use them here.
++ */
++ clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout");
++ clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout");
++ if (clk_14 || clk_15) {
++ val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15);
++ val &= ~IXP4XX_GPCLK_CLK0_MASK;
++ val &= ~IXP4XX_GPCLK_CLK1_MASK;
++ if (clk_14) {
++ val |= (0 << IXP4XX_GPCLK_CLK0DC_SHIFT);
++ val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT);
++ val |= IXP4XX_GPCLK_MUX14;
++ }
++
++ if (clk_15) {
++ val |= (0 << IXP4XX_GPCLK_CLK1DC_SHIFT);
++ val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT);
++ val |= IXP4XX_GPCLK_MUX15;
++ }
++ }
++
++ __raw_writel(val, g->base + IXP4XX_REG_GPCLK);
+
+ /*
+ * This is a very special big-endian ARM issue: when the IXP4xx is
--- /dev/null
+From 6599df775e2cbb4988bdf8239acf4fbec70e5ef9 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 23 Sep 2023 20:38:22 +0200
+Subject: [PATCH 3/4] net: ixp4xx_eth: Support changing the MTU
+
+As we don't specify the MTU in the driver, the framework
+will fall back to 1500 bytes and this doesn't work very
+well when we try to attach a DSA switch:
+
+ eth1: mtu greater than device maximum
+ ixp4xx_eth c800a000.ethernet eth1: error -22 setting
+ MTU to 1504 to include DSA overhead
+
+After locating an out-of-tree patch in OpenWrt I found
+suitable code to set the MTU on the interface and ported
+it and updated it. Now the MTU gets set properly.
+
+Reviewed-by: Jacob Keller <jacob.e.keller@intel.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ drivers/net/ethernet/xscale/ixp4xx_eth.c | 65 +++++++++++++++++++++++-
+ 1 file changed, 64 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/xscale/ixp4xx_eth.c
++++ b/drivers/net/ethernet/xscale/ixp4xx_eth.c
+@@ -24,6 +24,7 @@
+ #include <linux/dma-mapping.h>
+ #include <linux/dmapool.h>
+ #include <linux/etherdevice.h>
++#include <linux/if_vlan.h>
+ #include <linux/io.h>
+ #include <linux/kernel.h>
+ #include <linux/net_tstamp.h>
+@@ -63,7 +64,15 @@
+
+ #define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
+ #define REGS_SIZE 0x1000
+-#define MAX_MRU 1536 /* 0x600 */
++
++/* MRU is said to be 14320 in a code dump, the SW manual says that
++ * MRU/MTU is 16320 and includes VLAN and ethernet headers.
++ * See "IXP400 Software Programmer's Guide" section 10.3.2, page 161.
++ *
++ * FIXME: we have chosen the safe default (14320) but if you can test
++ * jumboframes, experiment with 16320 and see what happens!
++ */
++#define MAX_MRU (14320 - VLAN_ETH_HLEN)
+ #define RX_BUFF_SIZE ALIGN((NET_IP_ALIGN) + MAX_MRU, 4)
+
+ #define NAPI_WEIGHT 16
+@@ -1182,6 +1191,54 @@ static void destroy_queues(struct port *
+ }
+ }
+
++static int ixp4xx_do_change_mtu(struct net_device *dev, int new_mtu)
++{
++ struct port *port = netdev_priv(dev);
++ struct npe *npe = port->npe;
++ int framesize, chunks;
++ struct msg msg = {};
++
++ /* adjust for ethernet headers */
++ framesize = new_mtu + VLAN_ETH_HLEN;
++ /* max rx/tx 64 byte chunks */
++ chunks = DIV_ROUND_UP(framesize, 64);
++
++ msg.cmd = NPE_SETMAXFRAMELENGTHS;
++ msg.eth_id = port->id;
++
++ /* Firmware wants to know buffer size in 64 byte chunks */
++ msg.byte2 = chunks << 8;
++ msg.byte3 = chunks << 8;
++
++ msg.byte4 = msg.byte6 = framesize >> 8;
++ msg.byte5 = msg.byte7 = framesize & 0xff;
++
++ if (npe_send_recv_message(npe, &msg, "ETH_SET_MAX_FRAME_LENGTH"))
++ return -EIO;
++ netdev_dbg(dev, "set MTU on NPE %s to %d bytes\n",
++ npe_name(npe), new_mtu);
++
++ return 0;
++}
++
++static int ixp4xx_eth_change_mtu(struct net_device *dev, int new_mtu)
++{
++ int ret;
++
++ /* MTU can only be changed when the interface is up. We also
++ * set the MTU from dev->mtu when opening the device.
++ */
++ if (dev->flags & IFF_UP) {
++ ret = ixp4xx_do_change_mtu(dev, new_mtu);
++ if (ret < 0)
++ return ret;
++ }
++
++ dev->mtu = new_mtu;
++
++ return 0;
++}
++
+ static int eth_open(struct net_device *dev)
+ {
+ struct port *port = netdev_priv(dev);
+@@ -1232,6 +1289,8 @@ static int eth_open(struct net_device *d
+ if (npe_send_recv_message(port->npe, &msg, "ETH_SET_FIREWALL_MODE"))
+ return -EIO;
+
++ ixp4xx_do_change_mtu(dev, dev->mtu);
++
+ if ((err = request_queues(port)) != 0)
+ return err;
+
+@@ -1374,6 +1433,7 @@ static int eth_close(struct net_device *
+ static const struct net_device_ops ixp4xx_netdev_ops = {
+ .ndo_open = eth_open,
+ .ndo_stop = eth_close,
++ .ndo_change_mtu = ixp4xx_eth_change_mtu,
+ .ndo_start_xmit = eth_xmit,
+ .ndo_set_rx_mode = eth_set_mcast_list,
+ .ndo_eth_ioctl = eth_ioctl,
+@@ -1488,6 +1548,9 @@ static int ixp4xx_eth_probe(struct platf
+ ndev->dev.dma_mask = dev->dma_mask;
+ ndev->dev.coherent_dma_mask = dev->coherent_dma_mask;
+
++ ndev->min_mtu = ETH_MIN_MTU;
++ ndev->max_mtu = MAX_MRU;
++
+ netif_napi_add_weight(ndev, &port->napi, eth_poll, NAPI_WEIGHT);
+
+ if (!(port->npe = npe_request(NPE_ID(port->id))))
--- /dev/null
+From a1490c1e8a12a8286c6a34c3d277a519066fc51e Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Sat, 7 Oct 2023 14:32:40 +0200
+Subject: [PATCH] ARM: dts: ixp4xx: Add USRobotics USR8200 device tree
+
+This is a USRobotics NAS/Firewall/router that has been supported
+by OpenWrt in the past. It had dedicated users so let's get it
+properly supported.
+
+Some debugging and fixing was provided by Howard Harte.
+
+Link: https://lore.kernel.org/r/20231007-ixp4xx-usr8200-v1-1-aded3d6ff6f1@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/Makefile | 3 +-
+ .../ixp/intel-ixp42x-usrobotics-usr8200.dts | 229 ++++++++++++++++++
+ 2 files changed, 231 insertions(+), 1 deletion(-)
+ create mode 100644 arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+
+--- a/arch/arm/boot/dts/intel/ixp/Makefile
++++ b/arch/arm/boot/dts/intel/ixp/Makefile
+@@ -16,4 +16,5 @@ dtb-$(CONFIG_ARCH_IXP4XX) += \
+ intel-ixp43x-gateworks-gw2358.dtb \
+ intel-ixp42x-netgear-wg302v1.dtb \
+ intel-ixp42x-arcom-vulcan.dtb \
+- intel-ixp42x-gateway-7001.dtb
++ intel-ixp42x-gateway-7001.dtb \
++ intel-ixp42x-usrobotics-usr8200.dtb
+--- /dev/null
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+@@ -0,0 +1,229 @@
++// SPDX-License-Identifier: ISC
++/*
++ * Device Tree file for the USRobotics USR8200 firewall
++ * VPN and NAS. Based on know-how from Peter Denison.
++ *
++ * This machine is based on IXP422, the USR internal codename
++ * is "Jeeves".
++ */
++
++/dts-v1/;
++
++#include "intel-ixp42x.dtsi"
++#include <dt-bindings/input/input.h>
++
++/ {
++ model = "USRobotics USR8200";
++ compatible = "usr,usr8200", "intel,ixp42x";
++ #address-cells = <1>;
++ #size-cells = <1>;
++
++ memory@0 {
++ device_type = "memory";
++ reg = <0x00000000 0x4000000>;
++ };
++
++ chosen {
++ bootargs = "console=ttyS0,115200n8";
++ stdout-path = "uart1:115200n8";
++ };
++
++ aliases {
++ /* These are switched around */
++ serial0 = &uart1;
++ serial1 = &uart0;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ ieee1394_led: led-1394 {
++ label = "usr8200:green:1394";
++ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ usb1_led: led-usb1 {
++ label = "usr8200:green:usb1";
++ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ usb2_led: led-usb2 {
++ label = "usr8200:green:usb2";
++ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ wireless_led: led-wireless {
++ /*
++ * This LED is mounted inside the case but cannot be
++ * seen from the outside: probably USR planned at one
++ * point for the device to have a wireless card, then
++ * changed their mind and didn't mount it, leaving the
++ * LED in place.
++ */
++ label = "usr8200:green:wireless";
++ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
++ default-state = "off";
++ };
++ pwr_led: led-pwr {
++ label = "usr8200:green:pwr";
++ gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
++ default-state = "on";
++ linux,default-trigger = "heartbeat";
++ };
++ };
++
++ gpio_keys {
++ compatible = "gpio-keys";
++
++ button-reset {
++ wakeup-source;
++ linux,code = <KEY_RESTART>;
++ label = "reset";
++ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
++ };
++ };
++
++ soc {
++ bus@c4000000 {
++ flash@0,0 {
++ compatible = "intel,ixp4xx-flash", "cfi-flash";
++ bank-width = <2>;
++ /* Enable writes on the expansion bus */
++ intel,ixp4xx-eb-write-enable = <1>;
++ /* 16 MB of Flash mapped in at CS0 */
++ reg = <0 0x00000000 0x1000000>;
++
++ partitions {
++ compatible = "redboot-fis";
++ /* Eraseblock at 0x0fe0000 */
++ fis-index-block = <0x7f>;
++ };
++ };
++ rtc@2,0 {
++ /* EPSON RTC7301 DG DIL-capsule */
++ compatible = "epson,rtc7301dg";
++ /*
++ * These timing settings were found in the boardfile patch:
++ * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN |
++ * IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN;
++ */
++ intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase
++ intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase
++ intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase
++ intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase
++ intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase
++ intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle
++ intel,ixp4xx-eb-byte-access-on-halfword = <0>;
++ intel,ixp4xx-eb-mux-address-and-data = <0>;
++ intel,ixp4xx-eb-ahb-split-transfers = <0>;
++ intel,ixp4xx-eb-write-enable = <1>;
++ intel,ixp4xx-eb-byte-access = <1>;
++ /* 512 bytes at CS2 */
++ reg = <2 0x00000000 0x0000200>;
++ reg-io-width = <1>;
++ native-endian;
++ /* FIXME: try to check if there is an IRQ for the RTC? */
++ };
++ };
++
++ pci@c0000000 {
++ status = "okay";
++
++ /*
++ * Taken from USR8200 boardfile from OpenWrt
++ *
++ * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16.
++ * We assume the same IRQ for all pins on the remaining slots, that
++ * is what the boardfile was doing.
++ */
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0xf800 0 0 7>;
++ interrupt-map =
++ /* IDSEL 14 used for "Wireless" in the board file */
++ <0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */
++ /* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */
++ <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */
++ /* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */
++ <0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */
++ <0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */
++ <0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */
++ };
++
++ gpio@c8004000 {
++ /* Enable clock out on GPIO 15 */
++ intel,ixp4xx-gpio15-clkout;
++ };
++
++ /* EthB WAN */
++ ethernet@c8009000 {
++ status = "okay";
++ queue-rx = <&qmgr 3>;
++ queue-txready = <&qmgr 20>;
++ phy-mode = "rgmii";
++ phy-handle = <&phy9>;
++
++ mdio {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ phy9: ethernet-phy@9 {
++ reg = <9>;
++ };
++
++ /* The switch uses MDIO addresses 16 thru 31 */
++ switch@16 {
++ compatible = "marvell,mv88e6060";
++ reg = <16>;
++
++ ports {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ port@0 {
++ reg = <0>;
++ label = "lan1";
++ };
++
++ port@1 {
++ reg = <1>;
++ label = "lan2";
++ };
++
++ port@2 {
++ reg = <2>;
++ label = "lan3";
++ };
++
++ port@3 {
++ reg = <3>;
++ label = "lan4";
++ };
++
++ port@5 {
++ /* Port 5 is the CPU port according to the MV88E6060 datasheet */
++ reg = <5>;
++ phy-mode = "rgmii-id";
++ ethernet = <ðc>;
++ label = "cpu";
++ fixed-link {
++ speed = <100>;
++ full-duplex;
++ };
++ };
++ };
++ };
++ };
++ };
++
++ /* EthC LAN connected to the Marvell DSA Switch */
++ ethc: ethernet@c800a000 {
++ status = "okay";
++ queue-rx = <&qmgr 4>;
++ queue-txready = <&qmgr 21>;
++ phy-mode = "rgmii";
++ fixed-link {
++ speed = <100>;
++ full-duplex;
++ };
++ };
++ };
++};
--- /dev/null
+From 98f3b5f44b9ae86c4a80185b57149867472a2570 Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 20 Oct 2023 15:11:41 +0200
+Subject: [PATCH] ARM: dts: usr8200: Fix phy registers
+
+The MV88E6060 switch has internal PHY registers at MDIO
+addresses 0x00..0x04. Tie each port to the corresponding
+PHY.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/20231020-ixp4xx-usr8200-dtsfix-v1-1-3a8591dea259@linaro.org
+Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+---
+ .../ixp/intel-ixp42x-usrobotics-usr8200.dts | 22 +++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-usrobotics-usr8200.dts
+@@ -165,6 +165,24 @@
+ #address-cells = <1>;
+ #size-cells = <0>;
+
++ /*
++ * PHY 0..4 are internal to the MV88E6060 switch but appear
++ * as independent devices.
++ */
++ phy0: ethernet-phy@0 {
++ reg = <0>;
++ };
++ phy1: ethernet-phy@1 {
++ reg = <1>;
++ };
++ phy2: ethernet-phy@2 {
++ reg = <2>;
++ };
++ phy3: ethernet-phy@3 {
++ reg = <3>;
++ };
++
++ /* Altima AMI101L used by the WAN port */
+ phy9: ethernet-phy@9 {
+ reg = <9>;
+ };
+@@ -181,21 +199,25 @@
+ port@0 {
+ reg = <0>;
+ label = "lan1";
++ phy-handle = <&phy0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
++ phy-handle = <&phy1>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
++ phy-handle = <&phy2>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
++ phy-handle = <&phy3>;
+ };
+
+ port@5 {
--- /dev/null
+From 89eccb6726d93c9c78997e91bd641b0e46bc3c5f Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 8 Sep 2023 12:49:48 +0200
+Subject: [PATCH] ARM: dts: ixp4xx-nslu2: Enable write on flash
+
+To upgrade the firmware and similar, the flash needs write
+access.
+
+Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-1-98d36264ed6d@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
+@@ -101,6 +101,8 @@
+ flash@0,0 {
+ compatible = "intel,ixp4xx-flash", "cfi-flash";
+ bank-width = <2>;
++ /* Enable writes on the expansion bus */
++ intel,ixp4xx-eb-write-enable = <1>;
+ /*
+ * 8 MB of Flash in 0x20000 byte blocks
+ * mapped in at CS0.
--- /dev/null
+From deb93908958e74dffbef1ce6a1cc2f82ac4f96ed Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Fri, 8 Sep 2023 12:49:49 +0200
+Subject: [PATCH] ARM: dts: ixp4xx: Use right restart keycode
+
+The "reset" key on a few IXP4xx routers were sending KEY_ESC
+but what we want to send is KEY_RESTART which will make
+OpenWrt and similar userspace do a controlled reboot.
+
+Link: https://lore.kernel.org/r/20230908-ixp4xx-dts-v1-2-98d36264ed6d@linaro.org
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts | 2 +-
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts | 2 +-
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts | 2 +-
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-dlink-dsm-g600.dts
+@@ -57,7 +57,7 @@
+
+ button-reset {
+ wakeup-source;
+- linux,code = <KEY_ESC>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ };
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-freecom-fsg-3.dts
+@@ -44,7 +44,7 @@
+ };
+ button-reset {
+ wakeup-source;
+- linux,code = <KEY_ESC>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
+ };
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-iomega-nas100d.dts
+@@ -63,7 +63,7 @@
+ };
+ button-reset {
+ wakeup-source;
+- linux,code = <KEY_ESC>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ };
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
+@@ -65,7 +65,7 @@
+ };
+ button-reset {
+ wakeup-source;
+- linux,code = <KEY_ESC>;
++ linux,code = <KEY_RESTART>;
+ label = "reset";
+ gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ };
--- /dev/null
+From 6484f966af53447deefcd4b805c201d8624981cb Mon Sep 17 00:00:00 2001
+From: Linus Walleij <linus.walleij@linaro.org>
+Date: Mon, 29 May 2023 23:32:44 +0200
+Subject: [PATCH] ARM: dts: ixp4xx: Boot NSLU2 from harddrive
+
+This enforces harddrive boot on the NSLU2. The flash is too small
+to hold any rootfs these days.
+
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+---
+ arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
++++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts
+@@ -21,7 +21,7 @@
+ };
+
+ chosen {
+- bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait";
++ bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
+ stdout-path = "uart0:115200n8";
+ };
+
cloudengines,pogoe02|\
cloudengines,pogoplugv4|\
ctera,c200-v1|\
+ dlink,dns320l|\
globalscale,sheevaplug|\
iom,iconnect-1.1|\
iom,ix2-200|\
local label_mac=""
case "$board" in
+ dlink,dns320l)
+ lan_mac=$(mtd_get_mac_text "mini firmware")
+ ;;
iptime,nas1)
lan_mac=$(mtd_get_mac_binary u-boot 0x3ffa8)
label_mac=$lan_mac
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree file for DLINK DNS-320L
+ *
+ * Copyright (C) 2024, Zoltan HERPAI <wigyori@uid0.hu>
+ * Copyright (C) 2015, Sunke Schlüters <sunke-dev@schlueters.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * This file is based on the works of:
+ * - Sunke Schlüters <sunke-dev@schlueters.de>
+ * - https://github.com/scus1/dns320l/blob/master/kernel/dts/kirkwood-dns320l.dts
+ * - Andreas Böhler <dev@aboehler.at>:
+ * - http://www.aboehler.at/doku/doku.php/projects:dns320l
+ * - http://www.aboehler.at/hg/linux-dns320l/file/ba7a60ad7687/linux-3.12/kirkwood-dns320l.dts
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "D-Link DNS-320L";
+ compatible = "dlink,dns320l", "marvell,kirkwood-88f6702", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_buttons>;
+ pinctrl-names = "default";
+
+ button@1 {
+ label = "Reset push button";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio0 28 1>;
+ };
+
+ button@2 {
+ label = "USB unmount button";
+ linux,code = <KEY_EJECTCD>;
+ gpios = <&gpio0 27 1>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_leds>;
+ pinctrl-names = "default";
+
+ blue-usb {
+ label = "dns320l:usb:blue";
+ gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "usbport";
+ };
+
+ orange-usb {
+ label = "dns320l:usb:orange";
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ };
+
+ orange-l-hdd {
+ label = "dns320l:orange:l_hdd";
+ gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ orange-r-hdd {
+ label = "dns320l:orange:r_hdd";
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ ocp@f1000000 {
+ sata@80000 {
+ status = "okay";
+ nr-ports = <2>;
+ };
+
+ serial@12000 {
+ status = "okay";
+ };
+
+ serial@12100 {
+ pinctrl-0 = <&pmx_uart1>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_power_sata>;
+ pinctrl-names = "default";
+
+ sata_power: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "SATA Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 24 0>;
+ };
+ };
+};
+
+&nand {
+ pinctrl-0 = <&pmx_nand>;
+ pinctrl-names = "default";
+ chip-delay = <40>;
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ };
+
+ partition@100000 {
+ label = "ubootenv";
+ reg = <0x100000 0x20000>;
+ };
+
+ partition@120000 {
+ label = "ubi";
+ reg = <0x120000 0x6de0000>;
+ };
+
+ partition@6f00000 {
+ label = "mini firmware";
+ reg = <0x6f00000 0xa00000>;
+ };
+
+ partition@7900000 {
+ label = "config";
+ reg = <0x7900000 0x500000>;
+ };
+
+ partition@7e00000 {
+ label = "my-dlink";
+ reg = <0x7e00000 0x200000>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&pinctrl {
+ pmx_sata1: pmx-sata1 {
+ marvell,pins = "mpp20";
+ marvell,function = "sata1";
+ };
+
+ pmx_sata0: pmx-sata0 {
+ marvell,pins = "mpp21";
+ marvell,function = "sata0";
+ };
+
+ pmx_power_sata: pmx-power-sata {
+ marvell,pins = "mpp24";
+ marvell,function = "gpio";
+ };
+
+ pmx_leds: pmx-leds {
+ marvell,pins = "mpp22", "mpp23", "mpp25", "mpp26";
+ marvell,function = "gpio";
+ };
+
+ pmx_buttons: pmx-buttons {
+ marvell,pins = "mpp27", "mpp28", "mpp29";
+ marvell,function = "gpio";
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Device Tree file for DLINK DNS-320L
+ *
+ * Copyright (C) 2024, Zoltan HERPAI <wigyori@uid0.hu>
+ * Copyright (C) 2015, Sunke Schlüters <sunke-dev@schlueters.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * This file is based on the works of:
+ * - Sunke Schlüters <sunke-dev@schlueters.de>
+ * - https://github.com/scus1/dns320l/blob/master/kernel/dts/kirkwood-dns320l.dts
+ * - Andreas Böhler <dev@aboehler.at>:
+ * - http://www.aboehler.at/doku/doku.php/projects:dns320l
+ * - http://www.aboehler.at/hg/linux-dns320l/file/ba7a60ad7687/linux-3.12/kirkwood-dns320l.dts
+ */
+
+/dts-v1/;
+
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+
+/ {
+ model = "D-Link DNS-320L";
+ compatible = "dlink,dns320l", "marvell,kirkwood-88f6702", "marvell,kirkwood";
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_buttons>;
+ pinctrl-names = "default";
+
+ button@1 {
+ label = "Reset push button";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio0 28 1>;
+ };
+
+ button@2 {
+ label = "USB unmount button";
+ linux,code = <KEY_EJECTCD>;
+ gpios = <&gpio0 27 1>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&pmx_leds>;
+ pinctrl-names = "default";
+
+ blue-usb {
+ label = "dns320l:usb:blue";
+ gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "usbport";
+ };
+
+ orange-usb {
+ label = "dns320l:usb:orange";
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ };
+
+ orange-l-hdd {
+ label = "dns320l:orange:l_hdd";
+ gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>;
+ };
+
+ orange-r-hdd {
+ label = "dns320l:orange:r_hdd";
+ gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ ocp@f1000000 {
+ sata@80000 {
+ status = "okay";
+ nr-ports = <2>;
+ };
+
+ serial@12000 {
+ status = "okay";
+ };
+
+ serial@12100 {
+ pinctrl-0 = <&pmx_uart1>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-0 = <&pmx_power_sata>;
+ pinctrl-names = "default";
+
+ sata_power: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "SATA Power";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ gpio = <&gpio0 24 0>;
+ };
+ };
+};
+
+&nand {
+ pinctrl-0 = <&pmx_nand>;
+ pinctrl-names = "default";
+ chip-delay = <40>;
+ status = "okay";
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x100000>;
+ };
+
+ partition@100000 {
+ label = "ubootenv";
+ reg = <0x100000 0x20000>;
+ };
+
+ partition@120000 {
+ label = "ubi";
+ reg = <0x120000 0x6de0000>;
+ };
+
+ partition@6f00000 {
+ label = "mini firmware";
+ reg = <0x6f00000 0xa00000>;
+ };
+
+ partition@7900000 {
+ label = "config";
+ reg = <0x7900000 0x500000>;
+ };
+
+ partition@7e00000 {
+ label = "my-dlink";
+ reg = <0x7e00000 0x200000>;
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&pinctrl {
+ pmx_sata1: pmx-sata1 {
+ marvell,pins = "mpp20";
+ marvell,function = "sata1";
+ };
+
+ pmx_sata0: pmx-sata0 {
+ marvell,pins = "mpp21";
+ marvell,function = "sata0";
+ };
+
+ pmx_power_sata: pmx-power-sata {
+ marvell,pins = "mpp24";
+ marvell,function = "gpio";
+ };
+
+ pmx_leds: pmx-leds {
+ marvell,pins = "mpp22", "mpp23", "mpp25", "mpp26";
+ marvell,function = "gpio";
+ };
+
+ pmx_buttons: pmx-buttons {
+ marvell,pins = "mpp27", "mpp28", "mpp29";
+ marvell,function = "gpio";
+ };
+};
+
+ð0 {
+ status = "okay";
+ ethernet0-port@0 {
+ phy-handle = <ðphy0>;
+ };
+};
endef
TARGET_DEVICES += ctera_c200-v1
+define Device/dlink_dns320l
+ DEVICE_VENDOR := D-Link
+ DEVICE_MODEL := DNS-320L
+ DEVICE_PACKAGES := kmod-ata-marvell-sata kmod-fs-ext4 kmod-gpio-button-hotplug \
+ kmod-usb-storage kmod-usb-ledtrig-usbport dns320l-mcu
+endef
+TARGET_DEVICES += dlink_dns320l
+
define Device/endian_4i-edge-200
DEVICE_VENDOR := Endian
DEVICE_MODEL := 4i Edge 200
--- /dev/null
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -310,6 +310,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
+ kirkwood-db-88f6282.dtb \
+ kirkwood-dir665.dtb \
+ kirkwood-dns320.dtb \
++ kirkwood-dns320l.dtb \
+ kirkwood-dns325.dtb \
+ kirkwood-dockstar.dtb \
+ kirkwood-dreamplug.dtb \
+--- a/arch/arm/boot/dts/kirkwood-dns320l.dts
++++ b/arch/arm/boot/dts/kirkwood-dns320l.dts
+@@ -32,6 +32,13 @@
+ reg = <0x00000000 0x10000000>;
+ };
+
++ aliases {
++ led-boot = &led_orange_usb;
++ led-failsafe = &led_orange_usb;
++ led-running = &led_orange_usb;
++ led-upgrade = &led_orange_usb;
++ };
++
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+@@ -68,7 +75,7 @@
+ linux,default-trigger = "usbport";
+ };
+
+- orange-usb {
++ led_orange_usb: orange-usb {
+ label = "dns320l:usb:orange";
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ };
--- /dev/null
+--- a/arch/arm/boot/dts/marvell/Makefile
++++ b/arch/arm/boot/dts/marvell/Makefile
+@@ -92,6 +92,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
+ kirkwood-db-88f6282.dtb \
+ kirkwood-dir665.dtb \
+ kirkwood-dns320.dtb \
++ kirkwood-dns320l.dtb \
+ kirkwood-dns325.dtb \
+ kirkwood-dockstar.dtb \
+ kirkwood-dreamplug.dtb \
+--- a/arch/arm/boot/dts/marvell/kirkwood-dns320l.dts
++++ b/arch/arm/boot/dts/marvell/kirkwood-dns320l.dts
+@@ -32,6 +32,13 @@
+ reg = <0x00000000 0x10000000>;
+ };
+
++ aliases {
++ led-boot = &led_orange_usb;
++ led-failsafe = &led_orange_usb;
++ led-running = &led_orange_usb;
++ led-upgrade = &led_orange_usb;
++ };
++
+ chosen {
+ bootargs = "console=ttyS0,115200n8 earlyprintk";
+ stdout-path = &uart0;
+@@ -68,7 +75,7 @@
+ linux,default-trigger = "usbport";
+ };
+
+- orange-usb {
++ led_orange_usb: orange-usb {
+ label = "dns320l:usb:orange";
+ gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ };
FEATURES:=squashfs
SUBTARGETS:=xrx200 xway xway_legacy falcon ase
-KERNEL_PATCHVER:=5.15
-KERNEL_TESTING_PATCHVER:=6.1
+KERNEL_PATCHVER:=6.1
define Target/Description
Build firmware images for Lantiq SoC
DEVICE_PACKAGES := kmod-rt2800-pci wpad-basic-mbedtls kmod-usb-dwc2 kmod-usb-ledtrig-usbport
KERNEL_SIZE := 3072k
SUPPORTED_DEVICES += P2812HNUF1
+ DEFAULT := n
endef
TARGET_DEVICES += zyxel_p-2812hnu-f1
--- /dev/null
+From f038380835033e376d89c72516f087254792bbad Mon Sep 17 00:00:00 2001
+From: Martin Schiller <ms@dev.tdt.de>
+Date: Mon, 6 May 2024 09:41:42 +0200
+Subject: [PATCH] MIPS: pci: lantiq: restore reset gpio polarity
+
+Commit 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API") not
+only switched to the gpiod API, but also inverted / changed the polarity
+of the GPIO.
+
+According to the PCI specification, the RST# pin is an active-low
+signal. However, most of the device trees that have been widely used for
+a long time (mainly in the openWrt project) define this GPIO as
+active-high and the old driver code inverted the signal internally.
+
+Apparently there are actually boards where the reset gpio must be
+operated inverted. For this reason, we cannot use the GPIOD_OUT_LOW/HIGH
+flag for initialization. Instead, we must explicitly set the gpio to
+value 1 in order to take into account any "GPIO_ACTIVE_LOW" flag that
+may have been set.
+
+In order to remain compatible with all these existing device trees, we
+should therefore keep the logic as it was before the commit.
+
+Fixes: 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API")
+Cc: stable@vger.kernel.org
+Signed-off-by: Martin Schiller <ms@dev.tdt.de>
+---
+ arch/mips/pci/pci-lantiq.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/pci/pci-lantiq.c
++++ b/arch/mips/pci/pci-lantiq.c
+@@ -124,14 +124,14 @@ static int ltq_pci_startup(struct platfo
+ clk_disable(clk_external);
+
+ /* setup reset gpio used by pci */
+- reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
+- GPIOD_OUT_LOW);
++ reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS);
+ error = PTR_ERR_OR_ZERO(reset_gpio);
+ if (error) {
+ dev_err(&pdev->dev, "failed to request gpio: %d\n", error);
+ return error;
+ }
+ gpiod_set_consumer_name(reset_gpio, "pci_reset");
++ gpiod_direction_output(reset_gpio, 1);
+
+ /* enable auto-switching between PCI and EBU */
+ ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
+@@ -194,10 +194,10 @@ static int ltq_pci_startup(struct platfo
+
+ /* toggle reset pin */
+ if (reset_gpio) {
+- gpiod_set_value_cansleep(reset_gpio, 1);
++ gpiod_set_value_cansleep(reset_gpio, 0);
+ wmb();
+ mdelay(1);
+- gpiod_set_value_cansleep(reset_gpio, 0);
++ gpiod_set_value_cansleep(reset_gpio, 1);
+ }
+ return 0;
+ }
BOARDNAME:=NXP Layerscape
KERNEL_PATCHVER:=6.1
+KERNEL_TESTING_PATCHVER:=6.6
FEATURES:=squashfs nand usb pcie gpio fpu ubifs ext4 rootfs-part boot-part
SUBTARGETS:=armv8_64b armv7
CONFIG_GPIO_MPC8XXX=y
CONFIG_GPIO_MXC=y
CONFIG_GPIO_VF610=y
-# CONFIG_HARDEN_BRANCH_HISTORY is not set
-# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
--- /dev/null
+CONFIG_AD525X_DPOT=y
+CONFIG_AD525X_DPOT_I2C=y
+# CONFIG_AD525X_DPOT_SPI is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_APDS9802ALS=y
+CONFIG_AQUANTIA_PHY=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_ERRATA_798181=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+# CONFIG_ARM_IMX8M_DDRC_DEVFREQ is not set
+# CONFIG_ARM_IMX_BUS_DEVFREQ is not set
+# CONFIG_ARM_IMX_CPUFREQ_DT is not set
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ATAGS=y
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BATTERY_SBS=y
+CONFIG_BCM_NET_PHYLIB=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=262144
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CDROM=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CLKSRC_IMX_GPT=y
+CONFIG_CLKSRC_MMIO=y
+# CONFIG_CLK_IMX8MM is not set
+# CONFIG_CLK_IMX8MN is not set
+# CONFIG_CLK_IMX8MP is not set
+# CONFIG_CLK_IMX8MQ is not set
+# CONFIG_CLK_IMX8ULP is not set
+# CONFIG_CLK_IMX93 is not set
+CONFIG_CLK_QORIQ=y
+# CONFIG_CLK_VEXPRESS_OSC is not set
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=64
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC_CCITT=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DNOTIFY=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DW_DMAC=y
+CONFIG_DW_DMAC_CORE=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_93CX6=y
+CONFIG_EEPROM_AT24=y
+CONFIG_ELF_CORE=y
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_F2FS_FS=y
+CONFIG_FAILOVER=y
+CONFIG_FAT_FS=y
+# CONFIG_FEC is not set
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FREEZER=y
+CONFIG_FSL_EDMA=y
+CONFIG_FSL_GUTS=y
+CONFIG_FSL_IFC=y
+# CONFIG_FSL_PPFE is not set
+CONFIG_FSL_PQ_MDIO=y
+CONFIG_FSL_RCPM=y
+CONFIG_FSL_XGMAC_MDIO=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FTRACE=y
+# CONFIG_FTRACE_SYSCALLS is not set
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FUSE_FS=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GCC11_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GIANFAR=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_VF610=y
+# CONFIG_HARDEN_BRANCH_HISTORY is not set
+# CONFIG_HARDEN_BRANCH_PREDICTOR is not set
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+# CONFIG_HIST_TRIGGERS is not set
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_DEMUX_PINCTRL=y
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_IMX=y
+# CONFIG_I2C_IMX_LPI2C is not set
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_MUX_PINCTRL=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=y
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_I2C_XILINX=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_ICS932S401=y
+CONFIG_IMX2_WDT=y
+# CONFIG_IMX7ULP_WDT is not set
+# CONFIG_IMX8MM_THERMAL is not set
+CONFIG_IMX_DMA=y
+# CONFIG_IMX_GPCV2_PM_DOMAINS is not set
+CONFIG_IMX_INTMUX=y
+# CONFIG_IMX_IRQSTEER is not set
+# CONFIG_IMX_MU_MSI is not set
+CONFIG_IMX_SDMA=y
+# CONFIG_IMX_WEIM is not set
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+# CONFIG_INPUT_BBNSM_PWRKEY is not set
+# CONFIG_IOMMUFD is not set
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IPC_NS=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_ISL29003=y
+CONFIG_JBD2=y
+CONFIG_KALLSYMS=y
+CONFIG_KCMP=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_LEGACY_DIRECT_IO=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LS_EXTIRQ=y
+CONFIG_LS_SCFG_MSI=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MCPM=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+# CONFIG_MFD_HI6421_SPMI is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_VEXPRESS_SYSREG is not set
+CONFIG_MICREL_PHY=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=16
+# CONFIG_MMC_MXC is not set
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_ESDHC_IMX is not set
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MSDOS_FS=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_BLOCK is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MXC_CLK=y
+# CONFIG_MXS_DMA is not set
+CONFIG_NAMESPACES=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+CONFIG_NEON=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_NS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=16
+CONFIG_NTFS_FS=y
+CONFIG_NVMEM=y
+# CONFIG_NVMEM_IMX_IIM is not set
+# CONFIG_NVMEM_IMX_OCOTP_ELE is not set
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_SNVS_LPGPR is not set
+# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PACKET_DIAG=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+# CONFIG_PCI_IMX6_HOST is not set
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_MSI=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_PID_NS=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_IMX8ULP is not set
+# CONFIG_PINCTRL_IMX93 is not set
+# CONFIG_PINCTRL_IMXRT1050 is not set
+# CONFIG_PINCTRL_IMXRT1170 is not set
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_BRCMKONA=y
+CONFIG_POWER_RESET_BRCMSTB=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_COMPRESS=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_RAM=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK_QORIQ=y
+CONFIG_QORIQ_CPUFREQ=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_BBNSM is not set
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_EM3027=y
+CONFIG_RTC_DRV_FSL_FTM_ALARM=y
+# CONFIG_RTC_DRV_IMXDI is not set
+# CONFIG_RTC_DRV_MXC is not set
+# CONFIG_RTC_DRV_MXC_V2 is not set
+CONFIG_RTC_DRV_PCF2127=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
+CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_IMX_EARLYCON=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_ST_ASC=y
+CONFIG_SERIAL_ST_ASC_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SMSC_PHY=y
+CONFIG_SOCK_DIAG=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BRCMSTB=y
+CONFIG_SOC_BUS=y
+# CONFIG_SOC_IMX50 is not set
+# CONFIG_SOC_IMX51 is not set
+# CONFIG_SOC_IMX53 is not set
+# CONFIG_SOC_IMX6Q is not set
+# CONFIG_SOC_IMX6SL is not set
+# CONFIG_SOC_IMX6SLL is not set
+# CONFIG_SOC_IMX6SX is not set
+# CONFIG_SOC_IMX6UL is not set
+# CONFIG_SOC_IMX7D is not set
+# CONFIG_SOC_IMX7ULP is not set
+# CONFIG_SOC_IMX8M is not set
+# CONFIG_SOC_IMX9 is not set
+CONFIG_SOC_LS1021A=y
+# CONFIG_SOC_VF610 is not set
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_CADENCE=y
+CONFIG_SPI_DYNAMIC=y
+# CONFIG_SPI_FSL_LPSPI is not set
+# CONFIG_SPI_FSL_QUADSPI is not set
+# CONFIG_SPI_IMX is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPI_XILINX=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+# CONFIG_SSIF_IPMI_BMC is not set
+CONFIG_STACKTRACE=y
+CONFIG_STAGING_BOARD=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNIX_DIAG=y
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USER_NS=y
+CONFIG_USE_OF=y
+CONFIG_UTS_NS=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XILINX_WATCHDOG=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
--- /dev/null
+CONFIG_64BIT=y
+CONFIG_AQUANTIA_PHY=y
+CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
+CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
+CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_FORCE_MAX_ORDER=10
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_NXP=y
+CONFIG_ARCH_PROC_KCORE_TEXT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_WANTS_NO_INSTR=y
+CONFIG_ARCH_WANTS_THP_SWAP=y
+CONFIG_ARM64=y
+CONFIG_ARM64_4K_PAGES=y
+CONFIG_ARM64_CNP=y
+CONFIG_ARM64_EPAN=y
+CONFIG_ARM64_ERRATUM_1165522=y
+CONFIG_ARM64_ERRATUM_1286807=y
+CONFIG_ARM64_ERRATUM_2051678=y
+CONFIG_ARM64_ERRATUM_2054223=y
+CONFIG_ARM64_ERRATUM_2067961=y
+CONFIG_ARM64_ERRATUM_2077057=y
+CONFIG_ARM64_ERRATUM_2658417=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_HW_AFDBM=y
+CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+CONFIG_ARM64_PA_BITS=48
+CONFIG_ARM64_PA_BITS_48=y
+CONFIG_ARM64_PTR_AUTH=y
+CONFIG_ARM64_PTR_AUTH_KERNEL=y
+CONFIG_ARM64_SME=y
+CONFIG_ARM64_SVE=y
+CONFIG_ARM64_TAGGED_ADDR_ABI=y
+CONFIG_ARM64_VA_BITS=48
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y
+CONFIG_ARM64_WORKAROUND_REPEAT_TLBI=y
+CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT=y
+CONFIG_ARM64_WORKAROUND_TSB_FLUSH_FAILURE=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+CONFIG_ARM_GIC_V3_ITS_FSL_MC=y
+CONFIG_ARM_GIC_V3_ITS_PCI=y
+# CONFIG_ARM_PL172_MPMC is not set
+CONFIG_ARM_PSCI_CPUIDLE=y
+CONFIG_ARM_PSCI_FW=y
+CONFIG_ARM_SMMU=y
+# CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT is not set
+# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set
+CONFIG_ARM_SMMU_V3=y
+# CONFIG_ARM_SMMU_V3_SVA is not set
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_ASM_MODVERSIONS=y
+CONFIG_ASN1=y
+CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
+CONFIG_ATA=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUTOFS_FS=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_BATTERY_BQ27XXX=y
+# CONFIG_BATTERY_BQ27XXX_DT_UPDATES_NVM is not set
+CONFIG_BATTERY_BQ27XXX_I2C=y
+CONFIG_BLK_CGROUP_PUNT_BIO=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSGLIB=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_INTEGRITY_T10=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=262144
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_MQ_VIRTIO=y
+CONFIG_BLK_PM=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BTRFS_FS=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y
+CONFIG_CAVIUM_ERRATUM_22375=y
+CONFIG_CAVIUM_ERRATUM_23144=y
+CONFIG_CAVIUM_ERRATUM_23154=y
+CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CC_HAVE_SHADOW_CALL_STACK=y
+CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CLK_LS1028A_PLLDIG=y
+CONFIG_CLK_QORIQ=y
+# CONFIG_CLK_VEXPRESS_OSC is not set
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_CS2000_CP=y
+CONFIG_COMMON_CLK_FSL_FLEXSPI=y
+# CONFIG_COMMON_CLK_FSL_SAI is not set
+CONFIG_COMMON_CLK_XGENE=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_COREDUMP=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_FREQ=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_THERMAL=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRASH_CORE=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC64=y
+CONFIG_CRC64_ROCKSOFT=y
+CONFIG_CRC7=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_CROS_EC is not set
+CONFIG_CRYPTO_AES_ARM64=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_BLAKE2B=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRC64_ROCKSOFT=y
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_CURVE25519=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API_DESC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
+CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
+CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ENGINE=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HASH_INFO=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_CURVE25519_GENERIC=y
+CONFIG_CRYPTO_LIB_DES=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_XXHASH=y
+CONFIG_CRYPTO_ZSTD=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DIMLIB=y
+CONFIG_DMADEVICES=y
+CONFIG_DMATEST=y
+CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_DIRECT_REMAP=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ENGINE_RAID=y
+# CONFIG_DMA_NUMA_CMA is not set
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DNOTIFY=y
+CONFIG_DPAA2_CONSOLE=y
+CONFIG_DPAA_ERRATUM_A050385=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_ELF_CORE=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXTCON=y
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_F2FS_FS=y
+CONFIG_FAILOVER=y
+CONFIG_FANOTIFY=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FHANDLE=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FREEZER=y
+# CONFIG_FSL_BMAN_TEST is not set
+CONFIG_FSL_DPAA=y
+CONFIG_FSL_DPAA2_ETH=y
+CONFIG_FSL_DPAA2_PTP_CLOCK=y
+# CONFIG_FSL_DPAA2_QDMA is not set
+# CONFIG_FSL_DPAA_CHECKING is not set
+CONFIG_FSL_DPAA_ETH=y
+CONFIG_FSL_EDMA=y
+CONFIG_FSL_ENETC=y
+CONFIG_FSL_ENETC_CORE=y
+CONFIG_FSL_ENETC_IERB=y
+CONFIG_FSL_ENETC_MDIO=y
+CONFIG_FSL_ENETC_PTP_CLOCK=y
+CONFIG_FSL_ENETC_VF=y
+CONFIG_FSL_ERRATUM_A008585=y
+CONFIG_FSL_FMAN=y
+CONFIG_FSL_GUTS=y
+CONFIG_FSL_IFC=y
+CONFIG_FSL_MC_BUS=y
+CONFIG_FSL_MC_DPIO=y
+CONFIG_FSL_MC_UAPI_SUPPORT=y
+# CONFIG_FSL_PPFE is not set
+# CONFIG_FSL_QMAN_TEST is not set
+CONFIG_FSL_RCPM=y
+CONFIG_FSL_XGMAC_MDIO=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FUNCTION_ALIGNMENT=4
+CONFIG_FUNCTION_ALIGNMENT_4B=y
+CONFIG_FUSE_FS=y
+CONFIG_FWNODE_MDIO=y
+CONFIG_FW_CACHE=y
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GARP=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_NUMA=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IOREMAP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+# CONFIG_GIANFAR is not set
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GRO_CELLS=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_HIBERNATION_SNAPSHOT_DEV=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_IRQ=y
+CONFIG_HVC_XEN=y
+CONFIG_HVC_XEN_FRONTEND=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_SLAVE=y
+# CONFIG_I2C_SLAVE_TESTUNIT is not set
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+CONFIG_IMX2_WDT=y
+CONFIG_INET_DIAG=y
+# CONFIG_INET_DIAG_DESTROY is not set
+# CONFIG_INET_RAW_DIAG is not set
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_FF_MEMLESS=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_VIVALDIFMAP=y
+CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
+CONFIG_INTERVAL_TREE=y
+# CONFIG_IOMMUFD is not set
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
+CONFIG_IOMMU_DEFAULT_PASSTHROUGH=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_IO_PGTABLE=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_DART is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IPC_NS=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_MSI_IOMMU=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KCMP=y
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KSM=y
+CONFIG_LEGACY_DIRECT_IO=y
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LS_EXTIRQ=y
+CONFIG_LS_SCFG_MSI=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BUS=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
+CONFIG_MDIO_DEVICE=y
+CONFIG_MDIO_DEVRES=y
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MEMORY=y
+CONFIG_MEMORY_BALLOON=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MEMTEST=y
+# CONFIG_MFD_HI6421_SPMI is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_VEXPRESS_SYSREG is not set
+CONFIG_MICREL_PHY=y
+CONFIG_MICROSEMI_PHY=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MMU_NOTIFIER=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SMBUS=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MPILIB=y
+CONFIG_MRP=y
+CONFIG_MSCC_OCELOT_SWITCH_LIB=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+CONFIG_MTD_NAND_CORE=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_ECC_SW_HAMMING=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SPLIT_FIRMWARE=y
+CONFIG_MTD_SPLIT_FIT_FW=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MULTIPLEXER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MUX_MMIO=y
+CONFIG_MV_XOR_V2=y
+CONFIG_NAMESPACES=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_NEED_SG_DMA_FLAGS=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NET_DEVLINK=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_MSCC_FELIX=y
+CONFIG_NET_DSA_MSCC_FELIX_DSA_LIB=y
+CONFIG_NET_DSA_TAG_OCELOT=y
+CONFIG_NET_DSA_TAG_OCELOT_8021Q=y
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FAILOVER=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_NS=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SELFTESTS=y
+CONFIG_NET_SWITCHDEV=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NODES_SHIFT=2
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=64
+CONFIG_NUMA=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYERSCAPE_SFP=y
+CONFIG_NVMEM_LAYOUTS=y
+# CONFIG_NVMEM_SPMI_SDAM is not set
+CONFIG_NVMEM_SYSFS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NUMA=y
+CONFIG_PACKET_DIAG=y
+CONFIG_PACKING=y
+CONFIG_PADATA=y
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_REPORTING=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PARAVIRT=y
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_DW_HOST=y
+CONFIG_PCIE_LAYERSCAPE_GEN4=y
+CONFIG_PCIE_MOBIVEIL=y
+CONFIG_PCIE_MOBIVEIL_HOST=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_ATS=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HISI=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_MSI=y
+CONFIG_PCS_LYNX=y
+CONFIG_PER_VMA_LOCK=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
+CONFIG_PHYLINK=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_PHY_FSL_LYNX_28G is not set
+CONFIG_PID_IN_CONTEXTIDR=y
+CONFIG_PID_NS=y
+CONFIG_PL330_DMA=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_STD_PARTITION=""
+CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPTION=y
+CONFIG_PREEMPT_BUILD=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROFILING=y
+CONFIG_PTP_1588_CLOCK=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PTP_1588_CLOCK_QORIQ=y
+CONFIG_QCOM_HIDMA=y
+CONFIG_QCOM_HIDMA_MGMT=y
+CONFIG_QCOM_QDF2400_ERRATUM_0065=y
+# CONFIG_QFMT_V2 is not set
+CONFIG_QORIQ_CPUFREQ=y
+CONFIG_QORIQ_THERMAL=y
+CONFIG_QUEUED_RWLOCKS=y
+CONFIG_QUEUED_SPINLOCKS=y
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+CONFIG_RAID6_PQ=y
+# CONFIG_RANDOMIZE_KSTACK_OFFSET is not set
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RODATA_FULL_DEFAULT_ENABLED=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_FSL_FTM_ALARM=y
+CONFIG_RTC_DRV_PCF2127=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MC=y
+CONFIG_SCHED_THERMAL_PRESSURE=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_PROC_FS is not set
+# CONFIG_SCSI_SAS_ATA is not set
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_SECRETMEM=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_DWLIB=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PCILIB=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_SC16IS7XX=y
+CONFIG_SERIAL_SC16IS7XX_CORE=y
+# CONFIG_SERIAL_SC16IS7XX_I2C is not set
+CONFIG_SERIAL_SC16IS7XX_SPI=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SOCK_DIAG=y
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_DSPI=y
+CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_NXP_FLEXSPI=y
+CONFIG_SPI_PL022=y
+CONFIG_SPMI=y
+# CONFIG_SPMI_HISI3670 is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+# CONFIG_SQUASHFS_XZ is not set
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SRAM=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+CONFIG_SWIOTLB_XEN=y
+CONFIG_SWPHY=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_HYPERVISOR=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASK_XACCT=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_OF=y
+CONFIG_THP_SWAP=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TRANS_TABLE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+CONFIG_UBIFS_FS=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UIO=y
+CONFIG_UIO_AEC=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_DMEM_GENIRQ=y
+CONFIG_UIO_MF624=y
+CONFIG_UIO_NETX=y
+CONFIG_UIO_PCI_GENERIC=y
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_UIO_PRUSS is not set
+CONFIG_UIO_SERCOS3=y
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNIX_DIAG=y
+CONFIG_UNMAP_KERNEL_AT_EL0=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USER_NS=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_UTS_NS=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VFAT_FS=y
+CONFIG_VFIO=y
+# CONFIG_VFIO_AMBA is not set
+CONFIG_VFIO_CONTAINER=y
+CONFIG_VFIO_FSL_MC=y
+CONFIG_VFIO_GROUP=y
+CONFIG_VFIO_IOMMU_TYPE1=y
+# CONFIG_VFIO_NOIOMMU is not set
+CONFIG_VFIO_PCI=y
+CONFIG_VFIO_PCI_CORE=y
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI_MMAP=y
+CONFIG_VFIO_VIRQFD=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_ANCHOR=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_VIRTIO_IOMMU is not set
+CONFIG_VIRTIO_MMIO=y
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTIO_PCI_LIB=y
+CONFIG_VIRTIO_PCI_LIB_LEGACY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_VMAP_STACK=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XARRAY_MULTI=y
+CONFIG_XEN=y
+CONFIG_XENFS=y
+CONFIG_XEN_AUTO_XLATE=y
+CONFIG_XEN_BACKEND=y
+CONFIG_XEN_BALLOON=y
+# CONFIG_XEN_BLKDEV_BACKEND is not set
+CONFIG_XEN_BLKDEV_FRONTEND=y
+CONFIG_XEN_COMPAT_XENFS=y
+CONFIG_XEN_DEV_EVTCHN=y
+CONFIG_XEN_DOM0=y
+CONFIG_XEN_FBDEV_FRONTEND=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GRANT_DEV_ALLOC=y
+# CONFIG_XEN_NETDEV_BACKEND is not set
+CONFIG_XEN_NETDEV_FRONTEND=y
+# CONFIG_XEN_PCIDEV_STUB is not set
+CONFIG_XEN_PRIVCMD=y
+# CONFIG_XEN_PVCALLS_BACKEND is not set
+# CONFIG_XEN_SCSI_FRONTEND is not set
+CONFIG_XEN_SYS_HYPERVISOR=y
+# CONFIG_XEN_VIRTIO is not set
+# CONFIG_XEN_WDT is not set
+CONFIG_XEN_XENBUS_FRONTEND=y
+CONFIG_XFS_FS=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_RT=y
+CONFIG_XOR_BLOCKS=y
+CONFIG_XPS=y
+CONFIG_XXHASH=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZONE_DMA32=y
+CONFIG_ZSTD_COMMON=y
+CONFIG_ZSTD_COMPRESS=y
+CONFIG_ZSTD_DECOMPRESS=y
endef
define Build/ls-append-dtb
- dd if=$(DTS_DIR)/$(1).dtb >> $@
+ dd if=$(DEVICE_DTS_DIR)/$(1).dtb >> $@
endef
define Build/ls-append-kernel
PROFILES := Default
FILESYSTEMS := squashfs
IMAGES := firmware.bin sysupgrade.bin
+ifdef CONFIG_LINUX_6_1
+ DEVICE_DTS_DIR := $(DTS_DIR)
+else
+ DEVICE_DTS_DIR := $(DTS_DIR)/nxp/ls
+endif
KERNEL := kernel-bin | uImage none
- KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+ KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
KERNEL_NAME := zImage
KERNEL_LOADADDR := 0x80008000
DEVICE_DTS = $(lastword $(subst _, ,$(1)))
endef
define Device/fsl-sdboot
- KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+ KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
IMAGES := sdcard.img.gz sysupgrade.bin
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
define Device/Default
PROFILES := Default
IMAGES := firmware.bin sysupgrade.bin
+ DEVICE_DTS_DIR := $(DTS_DIR)/freescale
+ DEVICE_DTS = $(subst _,-,$(1))
FILESYSTEMS := squashfs
KERNEL := kernel-bin | gzip | uImage gzip
- KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+ KERNEL_INITRAMFS = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
KERNEL_LOADADDR := 0x80000000
- DEVICE_DTS = freescale/$(subst _,-,$(1))
IMAGE_SIZE := 64m
IMAGE/sysupgrade.bin = \
ls-append-dtb $$(DEVICE_DTS) | pad-to 1M | \
endef
define Device/fsl-sdboot
- KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+ KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
IMAGES := sdcard.img.gz sysupgrade.bin
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
append-kernel | pad-to $$(BLOCKSIZE) | \
append-rootfs | pad-rootfs | \
check-size $(LS_SYSUPGRADE_IMAGE_SIZE) | append-metadata
- KERNEL := kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+ KERNEL := kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
endef
TARGET_DEVICES += fsl_ls1012a-frdm
layerscape-ppfe \
trusted-firmware-a-ls1012a-frwy-sdboot \
kmod-ppfe
- DEVICE_DTS := freescale/fsl-ls1012a-frwy
+ DEVICE_DTS := fsl-ls1012a-frwy
IMAGES += firmware.bin
IMAGE/firmware.bin := \
ls-clean | \
DEVICE_VENDOR := NXP
DEVICE_MODEL := LS1028A-RDB
DEVICE_VARIANT := Default
- DEVICE_DTS := freescale/fsl-ls1028a-rdb
- KERNEL = kernel-bin | gzip | fit gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+ KERNEL = kernel-bin | gzip | fit gzip $$(DEVICE_DTS_DIR)/$$(DEVICE_DTS).dtb
DEVICE_PACKAGES += \
trusted-firmware-a-ls1028a-rdb \
kmod-hwmon-ina2xx \
DEVICE_VENDOR := NXP
DEVICE_MODEL := LS1028A-RDB
DEVICE_VARIANT := SD Card Boot
- DEVICE_DTS := freescale/fsl-ls1028a-rdb
+ DEVICE_DTS := fsl-ls1028a-rdb
DEVICE_PACKAGES += \
trusted-firmware-a-ls1028a-rdb-sdboot \
kmod-hwmon-ina2xx \
kmod-ahci-qoriq \
kmod-hwmon-ina2xx \
kmod-hwmon-lm90
- DEVICE_DTS := freescale/fsl-ls1043a-rdb
IMAGE/firmware.bin := \
ls-clean | \
ls-append $(1)-bl2.pbl | pad-to 1M | \
kmod-ahci-qoriq \
kmod-hwmon-ina2xx \
kmod-hwmon-lm90
- DEVICE_DTS := freescale/fsl-ls1043a-rdb
+ DEVICE_DTS := fsl-ls1043a-rdb
IMAGE/sdcard.img.gz := \
ls-clean | \
ls-append-sdhead $(1) | pad-to 4K | \
DEVICE_PACKAGES += \
layerscape-fman \
trusted-firmware-a-ls1046a-frwy
- DEVICE_DTS := freescale/fsl-ls1046a-frwy
IMAGE/firmware.bin := \
ls-clean | \
ls-append $(1)-bl2.pbl | pad-to 1M | \
DEVICE_PACKAGES += \
layerscape-fman \
trusted-firmware-a-ls1046a-frwy-sdboot
- DEVICE_DTS := freescale/fsl-ls1046a-frwy
+ DEVICE_DTS := fsl-ls1046a-frwy
IMAGE/sdcard.img.gz := \
ls-clean | \
ls-append-sdhead $(1) | pad-to 4K | \
kmod-ahci-qoriq \
kmod-hwmon-ina2xx \
kmod-hwmon-lm90
- DEVICE_DTS := freescale/fsl-ls1046a-rdb
IMAGE/firmware.bin := \
ls-clean | \
ls-append $(1)-bl2.pbl | pad-to 1M | \
kmod-ahci-qoriq \
kmod-hwmon-ina2xx \
kmod-hwmon-lm90
- DEVICE_DTS := freescale/fsl-ls1046a-rdb
+ DEVICE_DTS := fsl-ls1046a-rdb
IMAGE/sdcard.img.gz := \
ls-clean | \
ls-append-sdhead $(1) | pad-to 4K | \
kmod-ahci-qoriq \
kmod-hwmon-ina2xx \
kmod-hwmon-lm90
- DEVICE_DTS := freescale/fsl-ls1088a-rdb
+ DEVICE_DTS := fsl-ls1088a-rdb
IMAGE/sdcard.img.gz := \
ls-clean | \
ls-append-sdhead $(1) | pad-to 4K | \
layerscape-ddr-phy \
trusted-firmware-a-lx2160a-rdb-sdboot \
restool
- DEVICE_DTS := freescale/fsl-lx2160a-rdb
+ DEVICE_DTS := fsl-lx2160a-rdb
IMAGE/sdcard.img.gz := \
ls-clean | \
ls-append-sdhead $(1) | pad-to 4K | \
KERNEL_ENTRY_POINT := 0x80000000
FDT_LOADADDR := 0x90000000
KERNEL_SUFFIX := -kernel.itb
- DEVICE_DTS := freescale/fsl-ls1088a-ten64
+ DEVICE_DTS := fsl-ls1088a-ten64
IMAGES := nand.ubi sysupgrade.bin
KERNEL := kernel-bin | gzip | traverse-fit-ls1088 gzip $$(DTS_DIR)/$$(DEVICE_DTS).dtb $$(FDT_LOADADDR)
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
--- /dev/null
+From 008465a02bf29b366ca7a56dba48ad3a85417ba2 Mon Sep 17 00:00:00 2001
+From: Li Yang <leoyang.li@nxp.com>
+Date: Thu, 18 Nov 2021 21:46:21 -0600
+Subject: [PATCH] arm64: dts: ls1012a: add ppfe support to boards
+
+Update ls1012a dtsi and platform dts files with
+support for ppfe.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+---
+ .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 44 +++++++++++++++++++
+ .../boot/dts/freescale/fsl-ls1012a-qds.dts | 43 ++++++++++++++++++
+ .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 40 +++++++++++++++++
+ .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 29 ++++++++++++
+ 4 files changed, 156 insertions(+)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+@@ -14,6 +14,11 @@
+ model = "LS1012A Freedom Board";
+ compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
+
++ aliases {
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
++ };
++
+ sys_mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+@@ -110,6 +115,45 @@
+ };
+ };
+
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ pfe_mac0: ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ phy-handle = <&sgmii_phy1>;
++ };
++
++ pfe_mac1: ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ phy-handle = <&sgmii_phy2>;
++ };
++
++ mdio@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ sgmii_phy1: ethernet-phy@2 {
++ reg = <0x2>;
++ };
++
++ sgmii_phy2: ethernet-phy@1 {
++ reg = <0x1>;
++ };
++ };
++};
++
+ &sai2 {
+ status = "okay";
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+@@ -16,6 +16,8 @@
+ aliases {
+ mmc0 = &esdhc0;
+ mmc1 = &esdhc1;
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
+ };
+
+ sys_mclk: clock-mclk {
+@@ -148,6 +150,47 @@
+ };
+ };
+
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ pfe_mac0: ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,mdio-mux-val = <0x2>;
++ phy-mode = "sgmii-2500";
++ phy-handle = <&sgmii_phy1>;
++ };
++
++ pfe_mac1: ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,mdio-mux-val = <0x3>;
++ phy-mode = "sgmii-2500";
++ phy-handle = <&sgmii_phy2>;
++ };
++
++ mdio@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ sgmii_phy1: ethernet-phy@1 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <0x1>;
++ };
++
++ sgmii_phy2: ethernet-phy@2 {
++ compatible = "ethernet-phy-ieee802.3-c45";
++ reg = <0x2>;
++ };
++ };
++};
++
+ &sai2 {
+ status = "okay";
+ };
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+@@ -18,6 +18,8 @@
+ serial0 = &duart0;
+ mmc0 = &esdhc0;
+ mmc1 = &esdhc1;
++ ethernet0 = &pfe_mac0;
++ ethernet1 = &pfe_mac1;
+ };
+ };
+
+@@ -104,3 +106,41 @@
+ &sata {
+ status = "okay";
+ };
++
++&pfe {
++ status = "okay";
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ pfe_mac0: ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ phy-handle = <&sgmii_phy>;
++ };
++
++ pfe_mac1: ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "rgmii-id";
++ phy-handle = <&rgmii_phy>;
++ };
++ mdio@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ sgmii_phy: ethernet-phy@2 {
++ reg = <0x2>;
++ };
++
++ rgmii_phy: ethernet-phy@1 {
++ reg = <0x1>;
++ };
++ };
++};
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+@@ -568,6 +568,35 @@
+ };
+ };
+
++ reserved-memory {
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++
++ pfe_reserved: packetbuffer@83400000 {
++ reg = <0 0x83400000 0 0xc00000>;
++ };
++ };
++
++ pfe: pfe@4000000 {
++ compatible = "fsl,pfe";
++ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
++ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
++ reg-names = "pfe", "pfe-ddr";
++ fsl,pfe-num-interfaces = <0x2>;
++ interrupts = <0 172 0x4>, /* HIF interrupt */
++ <0 173 0x4>, /*HIF_NOCPY interrupt */
++ <0 174 0x4>; /* WoL interrupt */
++ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
++ memory-region = <&pfe_reserved>;
++ fsl,pfe-scfg = <&scfg 0>;
++ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
++ clocks = <&clockgen 4 0>;
++ clock-names = "pfe";
++
++ status = "okay";
++ };
++
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
--- /dev/null
+From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001
+From: Pawel Dembicki <paweldembicki@gmail.com>
+Date: Fri, 28 Sep 2022 17:14:32 +0200
+Subject: [PATCH] arm64: dts: ls1012a-frdm/qds: workaround by updating qspi flash to
+ single mode
+
+Update rx and tx bus-width to 1 to use single mode to workaround ubifs
+issue found with double mode. (The same method as RDB board)
+
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 4 ++--
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 4 ++--
+ 2 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+@@ -110,8 +110,8 @@
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ reg = <0>;
+- spi-rx-bus-width = <2>;
+- spi-tx-bus-width = <2>;
++ spi-rx-bus-width = <1>;
++ spi-tx-bus-width = <1>;
+ };
+ };
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+@@ -145,8 +145,8 @@
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ reg = <0>;
+- spi-rx-bus-width = <2>;
+- spi-tx-bus-width = <2>;
++ spi-rx-bus-width = <1>;
++ spi-tx-bus-width = <1>;
+ };
+ };
+
--- /dev/null
+From 9c5c18dbf8e1845d349ef7020f8af5bc9b56ed1f Mon Sep 17 00:00:00 2001
+From: Kuldeep Singh <kuldeep.singh@nxp.com>
+Date: Tue, 7 Jan 2020 17:14:32 +0530
+Subject: [PATCH] arm64: dts: ls1012a-rdb: workaround by updating qspi flash to
+ single mode
+
+Update rx and tx bus-width to 1 to use single mode to workaround ubifs
+issue found with double mode.
+
+[ Leo: Local workaround ]
+
+Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+@@ -98,8 +98,8 @@
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ reg = <0>;
+- spi-rx-bus-width = <2>;
+- spi-tx-bus-width = <2>;
++ spi-rx-bus-width = <1>;
++ spi-tx-bus-width = <1>;
+ };
+ };
+
--- /dev/null
+From 38093ebbf25eb60a1aa863f46118a68a0300c56e Mon Sep 17 00:00:00 2001
+From: Kuldeep Singh <kuldeep.singh@nxp.com>
+Date: Fri, 3 Jan 2020 14:49:07 +0530
+Subject: [PATCH] arm64: dts: ls1046a-rdb: Update qspi spi-rx-bus-width to 1
+
+Update rx width from quad mode to single mode as a workaround.
+
+[Leo: Local workaround ]
+
+Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
+---
+ arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+@@ -104,7 +104,7 @@
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+- spi-rx-bus-width = <4>;
++ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ reg = <0>;
+ };
+@@ -114,7 +114,7 @@
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+- spi-rx-bus-width = <4>;
++ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ reg = <1>;
+ };
--- /dev/null
+From bd3fa0b0ed51dd6a6564c01d37b36ff475f87ed4 Mon Sep 17 00:00:00 2001
+From: Han Xu <han.xu@nxp.com>
+Date: Tue, 14 Apr 2020 11:58:44 -0500
+Subject: [PATCH] LF-20-3 mtd: spi-nor: Use 1 bit mode of spansion(s25fs512s)
+ flash
+
+This is a workaround patch which uses only single bit mode of s25fs512s
+flash
+
+Signed-off-by: Han Xu <han.xu@nxp.com>
+Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
+---
+ drivers/mtd/spi-nor/spansion.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/spi-nor/spansion.c
++++ b/drivers/mtd/spi-nor/spansion.c
+@@ -798,8 +798,8 @@ static const struct flash_info spansion_
+ MFR_FLAGS(USE_CLSR)
+ },
+ { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
+- NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
+ MFR_FLAGS(USE_CLSR)
++ FIXUP_FLAGS(SPI_NOR_4B_OPCODES)
+ .fixups = &s25fs_s_nor_fixups, },
+ { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) },
+ { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) },
--- /dev/null
+From 9ee016f90af0bbcac576af881f1760ee9d9e38e0 Mon Sep 17 00:00:00 2001
+From: Calvin Johnson <calvin.johnson@nxp.com>
+Date: Sat, 16 Sep 2017 07:05:49 +0530
+Subject: [PATCH] staging: add fsl_ppfe driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is squash of all commits with ppfe driver taken from NXP 6.6 tree:
+https://github.com/nxp-qoriq/linux/tree/lf-6.6.y
+
+net: fsl_ppfe: dts binding for ppfe
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: header files for pfe driver
+
+This patch has all pfe header files.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: introduce pfe driver
+
+ This patch introduces Linux support for NXP's LS1012A Packet
+Forwarding Engine (pfe_eth). LS1012A uses hardware packet forwarding
+engine to provide high performance Ethernet interfaces. The device
+includes two Ethernet ports.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: fix RGMII tx delay issue
+
+Recently logic to enable RGMII tx delay was changed by
+below patch.
+
+https://patchwork.kernel.org/patch/9447581/
+
+Based on the patch, appropriate change is made in PFE driver.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: remove unused functions
+
+Remove unused functions hif_xmit_pkt & hif_lib_xmit_pkt.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: fix read/write/ack idx issue
+
+While fixing checkpatch errors some of the index increments
+were commented out. They are enabled.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: Make phy_ethtool_ksettings_get return void
+
+Make return value void since function never return meaningful value
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: add function to update tmu credits
+
+__hif_lib_update_credit function is used to update the tmu credits.
+If tx_qos is set, tmu credit is updated based on the number of packets
+transmitted by tmu.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: Avoid packet drop at TMU queues
+
+Added flow control between TMU queues and PFE Linux driver,
+based on TMU credits availability.
+Added tx_qos module parameter to control this behavior.
+Use queue-0 as default queue to transmit packets.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+Signed-off-by: Akhila Kavi <akhila.kavi@nxp.com>
+Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: Enable PFE in clause 45 mode
+
+when we opearate in clause 45 mode, we need to call
+the function get_phy_device() with its 3rd argument as
+"true" and then the resultant phy device needs to be
+register with phy layer via phy_device_register()
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+
+staging: fsl_ppfe/eth: Disable autonegotiation for 2.5G SGMII
+
+PCS initialization sequence for 2.5G SGMII interface governs
+auto negotiation to be in disabled mode
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+
+staging: fsl_ppfe/eth: calculate PFE_PKT_SIZE with SKB_DATA_ALIGN
+
+pfe packet size was calculated without considering skb data alignment
+and this resulted in jumbo frames crashing kernel when the
+cacheline size increased from 64 to 128 bytes with
+commit 97303480753e ("arm64: Increase the max granular size").
+
+Modify pfe packet size caclulation to include skb data alignment of
+sizeof(struct skb_shared_info).
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: support for userspace networking
+
+This patch adds the userspace mode support to fsl_ppfe network driver.
+In the new mode, basic hardware initialization is performed in kernel, while
+the datapath and HIF handling is the responsibility of the userspace.
+
+The new command line parameter is added to initialize the ppfe module
+in userspace mode. By default the module remains in kernelspace networking
+mode.
+To enable userspace mode, use "insmod pfe.ko us=1"
+
+Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
+Signed-off-by: Gagandeep Singh <g.singh@nxp.com>
+
+staging: fsl_ppfe/eth: unregister netdev after pfe_phy_exit
+
+rmmod pfe.ko throws below warning:
+
+kernfs: can not remove 'phydev', no directory
+------------[ cut here ]------------
+WARNING: CPU: 0 PID: 2230 at fs/kernfs/dir.c:1481
+kernfs_remove_by_name_ns+0x90/0xa0
+
+This is caused when the unregistered netdev structure is accessed to
+disconnect phy.
+
+Resolve the issue by unregistering netdev after disconnecting phy.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: HW parse results for DPDK
+
+HW Parse results are included in the packet headroom.
+Length and Offset calculation now accommodates parse info size.
+
+Signed-off-by: Archana Madhavan <archana.madhavan@nxp.com>
+
+staging: fsl_ppfe/eth: reorganize pfe_netdev_ops
+
+Reorganize members of struct pfe_netdev_ops to match with the order
+of members in struct net_device_ops defined in include/linux/netdevice.h
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: use mask for rx max frame len
+
+Define and use PFE_RCR_MAX_FL_MASK to properly set Rx max frame
+length of MAC Receive Control Register.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: define pfe ndo_change_mtu function
+
+Define ndo_change_mtu function for pfe. This sets the max Rx frame
+length to the new mtu.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: remove jumbo frame enable from gemac init
+
+MAC Receive Control Register was configured to allow jumbo frames.
+This is removed as jumbo frames can be supported anytime by changing
+mtu which will in turn modify MAX_FL field of MAC RCR.
+Jumbo frames caused pfe to hang on LS1012A rev 1.0 Silicon due to
+erratum A-010897.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: disable CRC removal
+
+Disable CRC removal from the packet, so that packets are forwarded
+as is to Linux.
+CRC configuration in MAC will be reflected in the packet received
+to Linux.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: handle ls1012a errata_a010897
+
+On LS1012A rev 1.0, Jumbo frames are not supported as it causes
+the PFE controller to hang. A reset of the entire chip is required
+to resume normal operation.
+
+To handle this errata, frames with length > 1900 are truncated for
+rev 1.0 of LS1012A.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: replace magic numbers
+
+Replace magic numbers and some cosmetic changes.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: resolve indentation warning
+
+Resolve the following indentation warning:
+
+drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:
+In function ‘pfe_get_gemac_if_proprties’:
+drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:96:2:
+warning: this ‘else’ clause does not guard...
+[-Wmisleading-indentation]
+ else
+ ^~~~
+drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c:98:3:
+note: ...this statement, but the latter is misleadingly indented as
+if it were guarded by the ‘else’
+ pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id;
+ ^~~~~
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: add fixed-link support
+
+In cases where MAC is not connected to a normal MDIO-managed PHY
+device, and instead to a switch, it is configured as a "fixed-link".
+Code to handle this scenario is added here.
+
+phy_node in the dtb is checked to identify a fixed-link.
+On identification of a fixed-link, it is registered and connected.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe: add support for a char dev for link status
+
+Read and IOCTL support is added. Application would need to open,
+read/ioctl the /dev/pfe_us_cdev device.
+select is pending as it requires a wait_queue.
+
+Signed-off-by: Shreyansh Jain <shreyansh.jain@nxp.com>
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe: enable hif event from userspace
+
+HIF interrupts are enabled using ioctl from user space,
+and epoll wait from user space wakes up when there is an HIF
+interrupt.
+
+Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
+
+staging: fsl_ppfe: performance tuning for user space
+
+interrupt coalescing of 100 usec is added.
+
+Signed-off-by: Akhil Goyal <akhil.goyal@nxp.com>
+Signed-off-by: Sachin Saxena <sachin.saxena@nxp.com>
+
+staging: fsl_ppfe/eth: Update to use SPDX identifiers
+
+Replace license text with corresponding SPDX identifiers and update the
+format of existing SPDX identifiers to follow the new guideline
+Documentation/process/license-rules.rst.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: misc clean up
+
+- remove redundant hwfeature init
+- remove unused vars from ls1012a_eth_platform_data
+- To handle ls1012a errata_a010897, PPFE driver requires GUTS driver
+to be compiled in. Select FSL_GUTS when PPFE driver is compiled.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: reorganize platform phy parameters
+
+- Use "phy-handle" and of_* functions to get phy node and fixed-link
+parameters
+
+- Reorganize phy parameters and initialize them only if phy-handle
+or fixed-link is defined in the dtb.
+
+- correct typo pfe_get_gemac_if_proprties to pfe_get_gemac_if_properties
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: support single interface initialization
+
+- arrange members of struct mii_bus in sequence matching phy.h
+- if mdio node is defined, use of_mdiobus_register to register
+ child nodes (phy devices) available on the mdio bus.
+- remove of_phy_register_fixed_link from pfe_phy_init as it is being
+ handled in pfe_get_gemac_if_properties
+- remove mdio enabled check
+- skip phy init, if no PHY or fixed-link
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+net: fsl_ppfe: update dts properties for phy
+
+Use commonly used phy-handle property and mdio subnode to handle
+phy properties.
+
+Deprecate bindings fsl,gemac-phy-id & fsl,pfe-phy-if-flags.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: remove unused code
+
+- remove gemac-bus-id related code that is unused.
+- remove unused prototype gemac_set_mdc_div.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: separate mdio init from mac init
+
+- separate mdio initialization from mac initialization
+- Define pfe_mdio_priv_s structure to hold mii_bus structure and other
+ related data.
+- Modify functions to work with the separted mdio init model.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: adapt to link mode based phydev changes
+
+Setting link mode bits have changed with the integration of
+commit (3c1bcc8 net: ethernet: Convert phydev advertize and
+supported from u32 to link mode). Adapt to the new method of
+setting and clearing the link mode bits.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: use generic soc_device infra instead of fsl_guts_get_svr()
+
+Commit ("soc: fsl: guts: make fsl_guts_get_svr() static") has
+made fsl_guts_get_svr() static and hence use generic soc_device
+infrastructure to check SoC revision.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: use memremap() to map RAM area used by PFE
+
+RAM area used by PFE should be mapped using memremap() instead of
+directly traslating physical addr to virtual. This will ensure proper
+checks are done before the area is used.
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+
+staging: fsl_ppfe/eth: remove 'fallback' argument from dev->ndo_select_queue()
+
+To be consistent with upstream API change.
+
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+
+staging: fsl_ppfe/eth: prefix header search paths with $(srctree)/
+
+Currently, the rules for configuring search paths in Kbuild have
+changed: https://lkml.org/lkml/2019/5/13/37
+
+This will lead the below error:
+
+fatal error: pfe/pfe.h: No such file or directory
+
+Fix it by adding $(srctree)/ prefix to the search paths.
+
+Signed-off-by: Ting Liu <ting.liu@nxp.com>
+
+staging: fsl_ppfe/eth: add pfe support to Kconfig and Makefile
+
+Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
+[ Aisheng: fix minor conflict due to removed VBOXSF_FS ]
+Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
+
+staging: fsl_ppfe/eth: Disable termination of CRC fwd.
+
+LS1012A MAC PCS block has an erratum that is seen with specific PHY AR803x.
+The issue is triggered by the (spec-compliant) operation of the AR803x PHY
+on the LS1012A-FRWY board.Due to this, good FCS packet is reported as error
+packet by MAC, so for these error packets FCS should be validated and
+discard only real error packets in PFE Rx packet path.
+
+Signed-off-by: Nagesh Koneti <koneti.nagesh@nxp.com>
+Signed-off-by: Nagesh Koneti <“koneti.nagesh@nxp.com”>
+
+net: ppfe: Cope with of_get_phy_mode() API change
+
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+
+staging: fsl_ppfe/eth: Enhance error checking in platform probe
+
+Fix the kernel crash when MAC addr is not passed in dtb.
+
+Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: reject unsupported coalescing params
+
+Set ethtool_ops->supported_coalesce_params to let
+the core reject unsupported coalescing parameters.
+
+Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth:check "reg" property before pfe_get_gemac_if_properties()
+
+It has been observed that the function pfe_get_gemac_if_properties() is
+been called blindly for the next two child nodes. There might be some
+cases where it may go wrong and that lead to missing interfaces.
+with these changes it is ensured thats not the case.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: "struct firmware" dereference is reduced in many functions
+
+firmware structure's data variable is the actual elf data. It has been
+dereferenced in multiple functions and this has been reduced.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: LF-27 load pfe binaries from FDT
+
+FDT prepared in uboot now has pfe firmware part of it.
+These changes will read the firmware by default from it and tries to load
+the elf into the PFE PEs. This help build the pfe driver pasrt of kernel.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+Signed-off-by: Anji J <anji.jagarlmudi@nxp.com>
+
+staging: fsl_ppfe/eth: proper handling for RGMII delay mode
+
+The correct setting for the RGMII ports on LS1012ARDB is to
+enable delay on both Tx and Rx. So the phy mode to be matched
+is PHY_INTERFACE_MODE_RGMII_ID.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+Signed-off-by: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
+
+LF-1762-2 staging: fsl_ppfe: replace '---help---' in Kconfig files with 'help'
+
+Update Kconfig to cope with upstream change
+commit 84af7a6194e4 ("checkpatch: kconfig: prefer 'help' over
+'---help---'").
+
+Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
+
+staging: fsl_ppfe/eth: Nesting level does not match indentation
+
+corrected nesting level
+LF-1661 and Coverity CID: 8879316
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Initialized scalar variable
+
+Proper initialization of scalar variable
+LF-1657 and Coverity CID: 3335133
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: misspelt variable name
+
+variable name corrected
+LF-1656 and Coverity CID: 3335119
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Avoiding out-of-bound writes
+
+avoid out-of-bound writes with proper error handling
+LF-1654, LF-1652 and Coverity CID: 3335106, 3335090
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Initializing scalar variable
+
+proper initialization of scalar variable.
+LF-1653 and Coverity CID: 3335101
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: checking return value
+
+proper checks added and handled for return value.
+LF-1644 and Coverity CID: 241888
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Avoid out-of-bound access
+
+proper handling to avoid out-of-bound access
+LF-1642, LF-1641 and Coverity CID: 240910, 240891
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Avoiding out-of-bound writes
+
+avoid out-of-bound writes with proper error handling
+LF-1654, LF-1652 and Coverity CID: 3335106, 3335090
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: return value init in error case
+
+proper err return in error case.
+LF-1806 and Coverity CID: 10468592
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Avoid recursion in header inclusion
+
+Avoiding header inclusions that are not necessary and also that are
+causing header inclusion recursion.
+
+LF-2102 and Coverity CID: 240838
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Avoiding return value overwrite
+
+avoid return value overwrite at the end of function.
+LF-2136, LF-2137 and Coverity CID: 8879341, 8879364
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: LF-27 enabling PFE firmware load from FDT
+
+The macro, "LOAD_PFEFIRMWARE_FROM_FILESYSTEM" is been disabled to load
+the firmware from FDT by default. Enabling the macro will load the
+firmware from filesystem.
+
+Also, the Makefile is now tuned to build pfe as per the config option
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: Ethtool stats correction for IEEE_rx_drop counter
+
+Due to carrier extended bug the phy counter IEEE_rx_drop counter is
+incremented some times and phy reports the packet has crc error.
+Because of this PFE revalidates all the packets that are marked crc
+error by phy. Now, the counter phy reports is till bogus and this
+patch decrements the counter by pfe revalidated (and are crc ok)
+counter amount.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe/eth: PFE firmware load enhancements
+
+PFE driver enhancements to load the PE firmware from filesystem
+when the firmware is not found in FDT.
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe: deal with upstream API change of of_get_mac_address()
+
+Uptream commit 83216e398 changed the of_get_mac_address() API, update
+the user accordingly.
+
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+
+staging: fsl_ppfe: update coalesce setting uAPI usage
+
+API changed since:
+f3ccfda19319 ("ethtool: extend coalesce setting uAPI with CQE mode")
+
+Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
+
+staging: fsl_ppfe: Addressed build warnings
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe: Addressed build warnings
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe: Remove C45 check and related code in driver
+
+The MDIO core will not pass a C45 request via the C22 API call any
+more. So, removed the code. The old way of C45 muxed addresses is
+removed from the upstream kernel after clear seperation of C45 and
+C22.
+Upstream kernel commit details for reference:
+99d5fe9c7f3d net: mdio: Remove support for building C45 muxed addresses
+
+Signed-off-by: Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+staging: fsl_ppfe: update class_create() usage
+
+Cope with API change:
+1aaba11da9aa ("driver core: class: remove module * from class_create()")
+
+Signed-off-by: Krishna Chaitanya Sakinam <chaitanya.sakinam@nxp.com>
+
+LF-10777-2 staging: fsl_ppfe: remove unused pfe_eth_mdio_write_addr
+
+Fix the following build warning:
+drivers/staging/fsl_ppfe/pfe_eth.c:887:12: warning: ‘pfe_eth_mdio_write_addr’ defined but not used [-Wunused-function]
+ 887 | static int pfe_eth_mdio_write_addr(struct mii_bus *bus, int mii_id,
+
+The only user of this API is MII_ADDR_C45 checking logic which
+was removed since the commit 9d95b13bd084 ("staging: fsl_ppfe: Remove
+C45 check and related code in driver"). So this API should be removed
+together as no users anymore.
+
+Fixes: 9d95b13bd084 ("staging: fsl_ppfe: Remove C45 check and related code in driver")
+Reviewed-by: Jason Liu <jason.hui.liu@nxp.com>
+Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
+---
+ .../devicetree/bindings/net/fsl_ppfe/pfe.txt | 199 ++
+ MAINTAINERS | 8 +
+ drivers/staging/Kconfig | 2 +
+ drivers/staging/Makefile | 1 +
+ drivers/staging/fsl_ppfe/Kconfig | 21 +
+ drivers/staging/fsl_ppfe/Makefile | 20 +
+ drivers/staging/fsl_ppfe/TODO | 2 +
+ drivers/staging/fsl_ppfe/include/pfe/cbus.h | 78 +
+ .../staging/fsl_ppfe/include/pfe/cbus/bmu.h | 55 +
+ .../fsl_ppfe/include/pfe/cbus/class_csr.h | 289 ++
+ .../fsl_ppfe/include/pfe/cbus/emac_mtip.h | 242 ++
+ .../staging/fsl_ppfe/include/pfe/cbus/gpi.h | 86 +
+ .../staging/fsl_ppfe/include/pfe/cbus/hif.h | 100 +
+ .../fsl_ppfe/include/pfe/cbus/hif_nocpy.h | 50 +
+ .../fsl_ppfe/include/pfe/cbus/tmu_csr.h | 168 ++
+ .../fsl_ppfe/include/pfe/cbus/util_csr.h | 61 +
+ drivers/staging/fsl_ppfe/include/pfe/pfe.h | 372 +++
+ drivers/staging/fsl_ppfe/pfe_cdev.c | 258 ++
+ drivers/staging/fsl_ppfe/pfe_cdev.h | 41 +
+ drivers/staging/fsl_ppfe/pfe_ctrl.c | 226 ++
+ drivers/staging/fsl_ppfe/pfe_ctrl.h | 100 +
+ drivers/staging/fsl_ppfe/pfe_debugfs.c | 99 +
+ drivers/staging/fsl_ppfe/pfe_debugfs.h | 13 +
+ drivers/staging/fsl_ppfe/pfe_eth.c | 2550 +++++++++++++++++
+ drivers/staging/fsl_ppfe/pfe_eth.h | 175 ++
+ drivers/staging/fsl_ppfe/pfe_firmware.c | 398 +++
+ drivers/staging/fsl_ppfe/pfe_firmware.h | 21 +
+ drivers/staging/fsl_ppfe/pfe_hal.c | 1517 ++++++++++
+ drivers/staging/fsl_ppfe/pfe_hif.c | 1063 +++++++
+ drivers/staging/fsl_ppfe/pfe_hif.h | 199 ++
+ drivers/staging/fsl_ppfe/pfe_hif_lib.c | 628 ++++
+ drivers/staging/fsl_ppfe/pfe_hif_lib.h | 229 ++
+ drivers/staging/fsl_ppfe/pfe_hw.c | 164 ++
+ drivers/staging/fsl_ppfe/pfe_hw.h | 15 +
+ .../staging/fsl_ppfe/pfe_ls1012a_platform.c | 383 +++
+ drivers/staging/fsl_ppfe/pfe_mod.c | 158 +
+ drivers/staging/fsl_ppfe/pfe_mod.h | 103 +
+ drivers/staging/fsl_ppfe/pfe_perfmon.h | 26 +
+ drivers/staging/fsl_ppfe/pfe_sysfs.c | 840 ++++++
+ drivers/staging/fsl_ppfe/pfe_sysfs.h | 17 +
+ 40 files changed, 10977 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
+ create mode 100644 drivers/staging/fsl_ppfe/Kconfig
+ create mode 100644 drivers/staging/fsl_ppfe/Makefile
+ create mode 100644 drivers/staging/fsl_ppfe/TODO
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h
+ create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pfe.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_cdev.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hal.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.h
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.c
+ create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.h
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
+@@ -0,0 +1,199 @@
++=============================================================================
++NXP Programmable Packet Forwarding Engine Device Bindings
++
++CONTENTS
++ - PFE Node
++ - Ethernet Node
++
++=============================================================================
++PFE Node
++
++DESCRIPTION
++
++PFE Node has all the properties associated with Packet Forwarding Engine block.
++
++PROPERTIES
++
++- compatible
++ Usage: required
++ Value type: <stringlist>
++ Definition: Must include "fsl,pfe"
++
++- reg
++ Usage: required
++ Value type: <prop-encoded-array>
++ Definition: A standard property.
++ Specifies the offset of the following registers:
++ - PFE configuration registers
++ - DDR memory used by PFE
++
++- fsl,pfe-num-interfaces
++ Usage: required
++ Value type: <u32>
++ Definition: Must be present. Value can be either one or two.
++
++- interrupts
++ Usage: required
++ Value type: <prop-encoded-array>
++ Definition: Three interrupts are specified in this property.
++ - HIF interrupt
++ - HIF NO COPY interrupt
++ - Wake On LAN interrupt
++
++- interrupt-names
++ Usage: required
++ Value type: <stringlist>
++ Definition: Following strings are defined for the 3 interrupts.
++ "pfe_hif" - HIF interrupt
++ "pfe_hif_nocpy" - HIF NO COPY interrupt
++ "pfe_wol" - Wake On LAN interrupt
++
++- memory-region
++ Usage: required
++ Value type: <phandle>
++ Definition: phandle to a node describing reserved memory used by pfe.
++ Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
++
++- fsl,pfe-scfg
++ Usage: required
++ Value type: <phandle>
++ Definition: phandle for scfg.
++
++- fsl,rcpm-wakeup
++ Usage: required
++ Value type: <phandle>
++ Definition: phandle for rcpm.
++
++- clocks
++ Usage: required
++ Value type: <phandle>
++ Definition: phandle for clockgen.
++
++- clock-names
++ Usage: required
++ Value type: <string>
++ Definition: phandle for clock name.
++
++EXAMPLE
++
++pfe: pfe@04000000 {
++ compatible = "fsl,pfe";
++ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
++ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
++ reg-names = "pfe", "pfe-ddr";
++ fsl,pfe-num-interfaces = <0x2>;
++ interrupts = <0 172 0x4>, /* HIF interrupt */
++ <0 173 0x4>, /*HIF_NOCPY interrupt */
++ <0 174 0x4>; /* WoL interrupt */
++ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
++ memory-region = <&pfe_reserved>;
++ fsl,pfe-scfg = <&scfg 0>;
++ fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
++ clocks = <&clockgen 4 0>;
++ clock-names = "pfe";
++
++ status = "okay";
++ pfe_mac0: ethernet@0 {
++ };
++
++ pfe_mac1: ethernet@1 {
++ };
++};
++
++=============================================================================
++Ethernet Node
++
++DESCRIPTION
++
++Ethernet Node has all the properties associated with PFE used by platforms to
++connect to PHY:
++
++PROPERTIES
++
++- compatible
++ Usage: required
++ Value type: <stringlist>
++ Definition: Must include "fsl,pfe-gemac-port"
++
++- reg
++ Usage: required
++ Value type: <prop-encoded-array>
++ Definition: A standard property.
++ Specifies the gemacid of the interface.
++
++- fsl,gemac-bus-id
++ Usage: required
++ Value type: <u32>
++ Definition: Must be present. Value should be the id of the bus
++ connected to gemac.
++
++- fsl,gemac-phy-id (deprecated binding)
++ Usage: required
++ Value type: <u32>
++ Definition: This binding shouldn't be used with new platforms.
++ Must be present. Value should be the id of the phy
++ connected to gemac.
++
++- fsl,mdio-mux-val
++ Usage: required
++ Value type: <u32>
++ Definition: Must be present. Value can be either 0 or 2 or 3.
++ This value is used to configure the mux to enable mdio.
++
++- phy-mode
++ Usage: required
++ Value type: <string>
++ Definition: Must include "sgmii"
++
++- fsl,pfe-phy-if-flags (deprecated binding)
++ Usage: required
++ Value type: <u32>
++ Definition: This binding shouldn't be used with new platforms.
++ Must be present. Value should be 0 by default.
++ If there is not phy connected, this need to be 1.
++
++- phy-handle
++ Usage: optional
++ Value type: <phandle>
++ Definition: phandle to the PHY device connected to this device.
++
++- mdio : A required subnode which specifies the mdio bus in the PFE and used as
++a container for phy nodes according to ../phy.txt.
++
++EXAMPLE
++
++ethernet@0 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x0>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x0>; /* BUS_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ phy-handle = <&sgmii_phy1>;
++};
++
++
++ethernet@1 {
++ compatible = "fsl,pfe-gemac-port";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ reg = <0x1>; /* GEM_ID */
++ fsl,gemac-bus-id = <0x1>; /* BUS_ID */
++ fsl,mdio-mux-val = <0x0>;
++ phy-mode = "sgmii";
++ phy-handle = <&sgmii_phy2>;
++};
++
++mdio@0 {
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ sgmii_phy1: ethernet-phy@2 {
++ reg = <0x2>;
++ };
++
++ sgmii_phy2: ethernet-phy@1 {
++ reg = <0x1>;
++ };
++};
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -8359,6 +8359,14 @@ F: drivers/ptp/ptp_qoriq.c
+ F: drivers/ptp/ptp_qoriq_debugfs.c
+ F: include/linux/fsl/ptp_qoriq.h
+
++FREESCALE QORIQ PPFE ETHERNET DRIVER
++M: Anji Jagarlmudi <anji.jagarlmudi@nxp.com>
++M: Calvin Johnson <calvin.johnson@nxp.com>
++L: netdev@vger.kernel.org
++S: Maintained
++F: drivers/staging/fsl_ppfe
++F: Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt
++
+ FREESCALE QUAD SPI DRIVER
+ M: Han Xu <han.xu@nxp.com>
+ L: linux-spi@vger.kernel.org
+--- a/drivers/staging/Kconfig
++++ b/drivers/staging/Kconfig
+@@ -78,4 +78,6 @@ source "drivers/staging/qlge/Kconfig"
+
+ source "drivers/staging/vme_user/Kconfig"
+
++source "drivers/staging/fsl_ppfe/Kconfig"
++
+ endif # STAGING
+--- a/drivers/staging/Makefile
++++ b/drivers/staging/Makefile
+@@ -28,3 +28,4 @@ obj-$(CONFIG_PI433) += pi433/
+ obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/
+ obj-$(CONFIG_FIELDBUS_DEV) += fieldbus/
+ obj-$(CONFIG_QLGE) += qlge/
++obj-$(CONFIG_FSL_PPFE) += fsl_ppfe/
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/Kconfig
+@@ -0,0 +1,21 @@
++#
++# Freescale Programmable Packet Forwarding Engine driver
++#
++config FSL_PPFE
++ tristate "Freescale PPFE Driver"
++ select FSL_GUTS
++ default n
++ help
++ Freescale LS1012A SoC has a Programmable Packet Forwarding Engine.
++ It provides two high performance ethernet interfaces.
++ This driver initializes, programs and controls the PPFE.
++ Use this driver to enable network connectivity on LS1012A platforms.
++
++if FSL_PPFE
++
++config FSL_PPFE_UTIL_DISABLED
++ bool "Disable PPFE UTIL Processor Engine"
++ help
++ UTIL PE has to be enabled only if required.
++
++endif # FSL_PPFE
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/Makefile
+@@ -0,0 +1,20 @@
++#
++# Makefile for Freesecale PPFE driver
++#
++
++ccflags-y += -I $(srctree)/$(src)/include -I $(srctree)/$(src)
++
++obj-$(CONFIG_FSL_PPFE) += pfe.o
++
++pfe-y += pfe_mod.o \
++ pfe_hw.o \
++ pfe_firmware.o \
++ pfe_ctrl.o \
++ pfe_hif.o \
++ pfe_hif_lib.o\
++ pfe_eth.o \
++ pfe_sysfs.o \
++ pfe_debugfs.o \
++ pfe_ls1012a_platform.o \
++ pfe_hal.o \
++ pfe_cdev.o
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/TODO
+@@ -0,0 +1,2 @@
++TODO:
++ - provide pfe pe monitoring support
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus.h
+@@ -0,0 +1,78 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _CBUS_H_
++#define _CBUS_H_
++
++#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000)
++#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000)
++#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000)
++#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000)
++#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000)
++#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000)
++#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000)
++#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000)
++#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000)
++#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000)
++#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000)
++#define LMEM_SIZE 0x10000
++#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE)
++#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000)
++#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000)
++#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000)
++#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000)
++#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000)
++
++/*
++ * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
++ * XXX_MEM_ACCESS_ADDR register bit definitions.
++ */
++#define PE_MEM_ACCESS_WRITE BIT(31) /* Internal Memory Write. */
++#define PE_MEM_ACCESS_IMEM BIT(15)
++#define PE_MEM_ACCESS_DMEM BIT(16)
++
++/* Byte Enables of the Internal memory access. These are interpred in BE */
++#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) \
++ ({ typeof(size) size_ = (size); \
++ (((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; })
++
++#include "cbus/emac_mtip.h"
++#include "cbus/gpi.h"
++#include "cbus/bmu.h"
++#include "cbus/hif.h"
++#include "cbus/tmu_csr.h"
++#include "cbus/class_csr.h"
++#include "cbus/hif_nocpy.h"
++#include "cbus/util_csr.h"
++
++/* PFE cores states */
++#define CORE_DISABLE 0x00000000
++#define CORE_ENABLE 0x00000001
++#define CORE_SW_RESET 0x00000002
++
++/* LMEM defines */
++#define LMEM_HDR_SIZE 0x0010
++#define LMEM_BUF_SIZE_LN2 0x7
++#define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2)
++
++/* DDR defines */
++#define DDR_HDR_SIZE 0x0100
++#define DDR_BUF_SIZE_LN2 0xb
++#define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2)
++
++#endif /* _CBUS_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h
+@@ -0,0 +1,55 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _BMU_H_
++#define _BMU_H_
++
++#define BMU_VERSION 0x000
++#define BMU_CTRL 0x004
++#define BMU_UCAST_CONFIG 0x008
++#define BMU_UCAST_BASE_ADDR 0x00c
++#define BMU_BUF_SIZE 0x010
++#define BMU_BUF_CNT 0x014
++#define BMU_THRES 0x018
++#define BMU_INT_SRC 0x020
++#define BMU_INT_ENABLE 0x024
++#define BMU_ALLOC_CTRL 0x030
++#define BMU_FREE_CTRL 0x034
++#define BMU_FREE_ERR_ADDR 0x038
++#define BMU_CURR_BUF_CNT 0x03c
++#define BMU_MCAST_CNT 0x040
++#define BMU_MCAST_ALLOC_CTRL 0x044
++#define BMU_REM_BUF_CNT 0x048
++#define BMU_LOW_WATERMARK 0x050
++#define BMU_HIGH_WATERMARK 0x054
++#define BMU_INT_MEM_ACCESS 0x100
++
++struct BMU_CFG {
++ unsigned long baseaddr;
++ u32 count;
++ u32 size;
++ u32 low_watermark;
++ u32 high_watermark;
++};
++
++#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2
++#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2
++
++#define BMU2_MCAST_ALLOC_CTRL (BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL)
++
++#endif /* _BMU_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h
+@@ -0,0 +1,289 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _CLASS_CSR_H_
++#define _CLASS_CSR_H_
++
++/* @file class_csr.h.
++ * class_csr - block containing all the classifier control and status register.
++ * Mapped on CBUS and accessible from all PE's and ARM.
++ */
++#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
++#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
++#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
++
++/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
++#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014)
++
++/* LMEM header size for the Classifier block.\ Data in the LMEM
++ * is written from this offset.
++ */
++#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f)
++
++/* DDR header size for the Classifier block.\ Data in the DDR
++ * is written from this offset.
++ */
++#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16)
++
++#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020)
++
++/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
++#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024)
++
++/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
++#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060)
++
++/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
++#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064)
++
++/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
++
++/* @name Class PE memory access. Allows external PE's and HOST to
++ * read/write PMEM/DMEM memory ranges for each classifier PE.
++ */
++/* {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]},
++ * See \ref XXX_MEM_ACCESS_ADDR for details.
++ */
++#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100)
++
++/* Internal Memory Access Write Data [31:0] */
++#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104)
++
++/* Internal Memory Access Read Data [31:0] */
++#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108)
++#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114)
++#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118)
++
++#define CLASS_PHY1_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x11c)
++#define CLASS_PHY1_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x120)
++#define CLASS_PHY1_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x124)
++#define CLASS_PHY1_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x128)
++#define CLASS_PHY1_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x12c)
++#define CLASS_PHY1_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x130)
++#define CLASS_PHY1_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x134)
++#define CLASS_PHY1_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x138)
++#define CLASS_PHY1_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x13c)
++#define CLASS_PHY1_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x140)
++#define CLASS_PHY2_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x144)
++#define CLASS_PHY2_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x148)
++#define CLASS_PHY2_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x14c)
++#define CLASS_PHY2_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x150)
++#define CLASS_PHY2_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x154)
++#define CLASS_PHY2_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x158)
++#define CLASS_PHY2_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x15c)
++#define CLASS_PHY2_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x160)
++#define CLASS_PHY2_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x164)
++#define CLASS_PHY2_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x168)
++#define CLASS_PHY3_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x16c)
++#define CLASS_PHY3_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x170)
++#define CLASS_PHY3_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x174)
++#define CLASS_PHY3_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x178)
++#define CLASS_PHY3_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x17c)
++#define CLASS_PHY3_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x180)
++#define CLASS_PHY3_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x184)
++#define CLASS_PHY3_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x188)
++#define CLASS_PHY3_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x18c)
++#define CLASS_PHY3_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x190)
++#define CLASS_PHY1_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x194)
++#define CLASS_PHY1_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x198)
++#define CLASS_PHY1_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x19c)
++#define CLASS_PHY1_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a0)
++#define CLASS_PHY2_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a4)
++#define CLASS_PHY2_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a8)
++#define CLASS_PHY2_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1ac)
++#define CLASS_PHY2_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b0)
++#define CLASS_PHY3_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b4)
++#define CLASS_PHY3_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b8)
++#define CLASS_PHY3_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1bc)
++#define CLASS_PHY3_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c0)
++#define CLASS_PHY4_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c4)
++#define CLASS_PHY4_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c8)
++#define CLASS_PHY4_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1cc)
++#define CLASS_PHY4_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1d0)
++#define CLASS_PHY4_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d4)
++#define CLASS_PHY4_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d8)
++#define CLASS_PHY4_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1dc)
++#define CLASS_PHY4_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e0)
++#define CLASS_PHY4_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x1e4)
++#define CLASS_PHY4_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e8)
++#define CLASS_PHY4_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x1ec)
++#define CLASS_PHY4_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x1f0)
++#define CLASS_PHY4_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f4)
++#define CLASS_PHY4_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f8)
++
++#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200)
++#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204)
++#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208)
++#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c)
++#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210)
++#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214)
++#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218)
++#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c)
++#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220)
++#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224)
++
++#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228)
++
++#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c)
++#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230)
++
++/* (route_entry_size[9:0], route_hash_size[23:16]
++ * (this is actually ln2(size)))
++ */
++#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234)
++
++#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff)
++#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
++
++#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238)
++
++#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c)
++#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240)
++#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244)
++#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248)
++#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c)
++#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250)
++#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254)
++
++#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258)
++#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000)
++/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
++
++#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c)
++
++#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260)
++#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
++#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268)
++#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
++#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270)
++#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
++#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278)
++#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
++#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280)
++#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
++#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288)
++#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c)
++
++#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290)
++#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294)
++
++#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298)
++#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
++
++#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0)
++
++#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4)
++#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8)
++#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac)
++#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0)
++#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4)
++#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8)
++
++#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc)
++
++/* CLASS defines */
++#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */
++#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */
++
++/* Can be configured */
++#define CLASS_PBUF0_BASE_ADDR 0x000
++/* Can be configured */
++#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
++/* Can be configured */
++#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
++/* Can be configured */
++#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
++
++#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + \
++ CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + \
++ CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + \
++ CLASS_PBUF_HEADER_OFFSET)
++#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR + \
++ CLASS_PBUF_HEADER_OFFSET)
++
++#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) | \
++ CLASS_PBUF0_BASE_ADDR)
++#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) | \
++ CLASS_PBUF2_BASE_ADDR)
++
++#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) |\
++ CLASS_PBUF0_HEADER_BASE_ADDR)
++#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) |\
++ CLASS_PBUF2_HEADER_BASE_ADDR)
++
++#define CLASS_ROUTE_SIZE 128
++#define CLASS_MAX_ROUTE_SIZE 256
++#define CLASS_ROUTE_HASH_BITS 20
++#define CLASS_ROUTE_HASH_MASK (BIT(CLASS_ROUTE_HASH_BITS) - 1)
++
++/* Can be configured */
++#define CLASS_ROUTE0_BASE_ADDR 0x400
++/* Can be configured */
++#define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE)
++/* Can be configured */
++#define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE)
++/* Can be configured */
++#define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE)
++
++#define CLASS_SA_SIZE 128
++#define CLASS_IPSEC_SA0_BASE_ADDR 0x600
++/* not used */
++#define CLASS_IPSEC_SA1_BASE_ADDR (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE)
++/* not used */
++#define CLASS_IPSEC_SA2_BASE_ADDR (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE)
++/* not used */
++#define CLASS_IPSEC_SA3_BASE_ADDR (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE)
++
++/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */
++#define CLASS_GP_DMEM_BUF_SIZE (2048 - (CLASS_PBUF_SIZE * 4) - \
++ (CLASS_ROUTE_SIZE * 4) - (CLASS_SA_SIZE))
++#define CLASS_GP_DMEM_BUF ((void *)(CLASS_IPSEC_SA0_BASE_ADDR + \
++ CLASS_SA_SIZE))
++
++#define TWO_LEVEL_ROUTE BIT(0)
++#define PHYNO_IN_HASH BIT(1)
++#define HW_ROUTE_FETCH BIT(3)
++#define HW_BRIDGE_FETCH BIT(5)
++#define IP_ALIGNED BIT(6)
++#define ARC_HIT_CHECK_EN BIT(7)
++#define CLASS_TOE BIT(11)
++#define HASH_NORMAL (0 << 12)
++#define HASH_CRC_PORT BIT(12)
++#define HASH_CRC_IP (2 << 12)
++#define HASH_CRC_PORT_IP (3 << 12)
++#define QB2BUS_LE BIT(15)
++
++#define TCP_CHKSUM_DROP BIT(0)
++#define UDP_CHKSUM_DROP BIT(1)
++#define IPV4_CHKSUM_DROP BIT(9)
++
++/*CLASS_HIF_PARSE bits*/
++#define HIF_PKT_CLASS_EN BIT(0)
++#define HIF_PKT_OFFSET(ofst) (((ofst) & 0xF) << 1)
++
++struct class_cfg {
++ u32 toe_mode;
++ unsigned long route_table_baseaddr;
++ u32 route_table_hash_bits;
++ u32 pe_sys_clk_ratio;
++ u32 resume;
++};
++
++#endif /* _CLASS_CSR_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h
+@@ -0,0 +1,242 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _EMAC_H_
++#define _EMAC_H_
++
++#include <linux/ethtool.h>
++
++#define EMAC_IEVENT_REG 0x004
++#define EMAC_IMASK_REG 0x008
++#define EMAC_R_DES_ACTIVE_REG 0x010
++#define EMAC_X_DES_ACTIVE_REG 0x014
++#define EMAC_ECNTRL_REG 0x024
++#define EMAC_MII_DATA_REG 0x040
++#define EMAC_MII_CTRL_REG 0x044
++#define EMAC_MIB_CTRL_STS_REG 0x064
++#define EMAC_RCNTRL_REG 0x084
++#define EMAC_TCNTRL_REG 0x0C4
++#define EMAC_PHY_ADDR_LOW 0x0E4
++#define EMAC_PHY_ADDR_HIGH 0x0E8
++#define EMAC_GAUR 0x120
++#define EMAC_GALR 0x124
++#define EMAC_TFWR_STR_FWD 0x144
++#define EMAC_RX_SECTION_FULL 0x190
++#define EMAC_RX_SECTION_EMPTY 0x194
++#define EMAC_TX_SECTION_EMPTY 0x1A0
++#define EMAC_TRUNC_FL 0x1B0
++
++#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
++#define RMON_T_PACKETS 0x204 /* RMON TX packet count */
++#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
++#define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */
++#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
++#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
++#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
++#define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */
++#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
++#define RMON_T_COL 0x224 /* RMON TX collision count */
++#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
++#define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */
++#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
++#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
++#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
++#define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */
++#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
++#define RMON_T_OCTETS 0x244 /* RMON TX octets */
++#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
++#define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */
++#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
++#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
++#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
++#define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */
++#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
++#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
++#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
++#define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */
++#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
++#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
++#define RMON_R_PACKETS 0x284 /* RMON RX packet count */
++#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
++#define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */
++#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
++#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
++#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
++#define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */
++#define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
++#define RMON_R_RESVD_O 0x2a4 /* Reserved */
++#define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */
++#define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */
++#define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */
++#define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */
++#define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */
++#define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */
++#define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */
++#define RMON_R_OCTETS 0x2c4 /* RMON RX octets */
++#define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */
++#define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */
++#define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */
++#define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */
++#define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */
++#define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */
++#define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */
++
++#define EMAC_SMAC_0_0 0x500 /*Supplemental MAC Address 0 (RW).*/
++#define EMAC_SMAC_0_1 0x504 /*Supplemental MAC Address 0 (RW).*/
++
++/* GEMAC definitions and settings */
++
++#define EMAC_PORT_0 0
++#define EMAC_PORT_1 1
++
++/* GEMAC Bit definitions */
++#define EMAC_IEVENT_HBERR 0x80000000
++#define EMAC_IEVENT_BABR 0x40000000
++#define EMAC_IEVENT_BABT 0x20000000
++#define EMAC_IEVENT_GRA 0x10000000
++#define EMAC_IEVENT_TXF 0x08000000
++#define EMAC_IEVENT_TXB 0x04000000
++#define EMAC_IEVENT_RXF 0x02000000
++#define EMAC_IEVENT_RXB 0x01000000
++#define EMAC_IEVENT_MII 0x00800000
++#define EMAC_IEVENT_EBERR 0x00400000
++#define EMAC_IEVENT_LC 0x00200000
++#define EMAC_IEVENT_RL 0x00100000
++#define EMAC_IEVENT_UN 0x00080000
++
++#define EMAC_IMASK_HBERR 0x80000000
++#define EMAC_IMASK_BABR 0x40000000
++#define EMAC_IMASKT_BABT 0x20000000
++#define EMAC_IMASK_GRA 0x10000000
++#define EMAC_IMASKT_TXF 0x08000000
++#define EMAC_IMASK_TXB 0x04000000
++#define EMAC_IMASKT_RXF 0x02000000
++#define EMAC_IMASK_RXB 0x01000000
++#define EMAC_IMASK_MII 0x00800000
++#define EMAC_IMASK_EBERR 0x00400000
++#define EMAC_IMASK_LC 0x00200000
++#define EMAC_IMASKT_RL 0x00100000
++#define EMAC_IMASK_UN 0x00080000
++
++#define EMAC_RCNTRL_MAX_FL_SHIFT 16
++#define EMAC_RCNTRL_LOOP 0x00000001
++#define EMAC_RCNTRL_DRT 0x00000002
++#define EMAC_RCNTRL_MII_MODE 0x00000004
++#define EMAC_RCNTRL_PROM 0x00000008
++#define EMAC_RCNTRL_BC_REJ 0x00000010
++#define EMAC_RCNTRL_FCE 0x00000020
++#define EMAC_RCNTRL_RGMII 0x00000040
++#define EMAC_RCNTRL_SGMII 0x00000080
++#define EMAC_RCNTRL_RMII 0x00000100
++#define EMAC_RCNTRL_RMII_10T 0x00000200
++#define EMAC_RCNTRL_CRC_FWD 0x00004000
++
++#define EMAC_TCNTRL_GTS 0x00000001
++#define EMAC_TCNTRL_HBC 0x00000002
++#define EMAC_TCNTRL_FDEN 0x00000004
++#define EMAC_TCNTRL_TFC_PAUSE 0x00000008
++#define EMAC_TCNTRL_RFC_PAUSE 0x00000010
++
++#define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */
++#define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */
++#define EMAC_ECNTRL_MAGIC_ENA 0x00000004
++#define EMAC_ECNTRL_SLEEP 0x00000008
++#define EMAC_ECNTRL_SPEED 0x00000020
++#define EMAC_ECNTRL_DBSWAP 0x00000100
++
++#define EMAC_X_WMRK_STRFWD 0x00000100
++
++#define EMAC_X_DES_ACTIVE_TDAR 0x01000000
++#define EMAC_R_DES_ACTIVE_RDAR 0x01000000
++
++#define EMAC_RX_SECTION_EMPTY_V 0x00010006
++/*
++ * The possible operating speeds of the MAC, currently supporting 10, 100 and
++ * 1000Mb modes.
++ */
++enum mac_speed {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS};
++
++/* MII-related definitios */
++#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
++#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
++#define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */
++#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
++#define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */
++#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
++#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
++#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */
++#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
++
++#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
++#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */
++#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
++#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */
++
++#define EMAC_MII_DATA_RA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
++ EMAC_MII_DATA_RA_SHIFT)
++#define EMAC_MII_DATA_PA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
++ EMAC_MII_DATA_PA_SHIFT)
++#define EMAC_MII_DATA(v) ((v) & 0xffff)
++
++#define EMAC_MII_SPEED_SHIFT 1
++#define EMAC_HOLDTIME_SHIFT 8
++#define EMAC_HOLDTIME_MASK 0x7
++#define EMAC_HOLDTIME(v) (((v) & EMAC_HOLDTIME_MASK) << \
++ EMAC_HOLDTIME_SHIFT)
++
++/*
++ * The Address organisation for the MAC device. All addresses are split into
++ * two 32-bit register fields. The first one (bottom) is the lower 32-bits of
++ * the address and the other field are the high order bits - this may be 16-bits
++ * in the case of MAC addresses, or 32-bits for the hash address.
++ * In terms of memory storage, the first item (bottom) is assumed to be at a
++ * lower address location than 'top'. i.e. top should be at address location of
++ * 'bottom' + 4 bytes.
++ */
++struct pfe_mac_addr {
++ u32 bottom; /* Lower 32-bits of address. */
++ u32 top; /* Upper 32-bits of address. */
++};
++
++/*
++ * The following is the organisation of the address filters section of the MAC
++ * registers. The Cadence MAC contains four possible specific address match
++ * addresses, if an incoming frame corresponds to any one of these four
++ * addresses then the frame will be copied to memory.
++ * It is not necessary for all four of the address match registers to be
++ * programmed, this is application dependent.
++ */
++struct spec_addr {
++ struct pfe_mac_addr one; /* Specific address register 1. */
++ struct pfe_mac_addr two; /* Specific address register 2. */
++ struct pfe_mac_addr three; /* Specific address register 3. */
++ struct pfe_mac_addr four; /* Specific address register 4. */
++};
++
++struct gemac_cfg {
++ u32 mode;
++ u32 speed;
++ u32 duplex;
++};
++
++/* EMAC Hash size */
++#define EMAC_HASH_REG_BITS 64
++
++#define EMAC_SPEC_ADDR_MAX 4
++
++#endif /* _EMAC_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h
+@@ -0,0 +1,86 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _GPI_H_
++#define _GPI_H_
++
++#define GPI_VERSION 0x00
++#define GPI_CTRL 0x04
++#define GPI_RX_CONFIG 0x08
++#define GPI_HDR_SIZE 0x0c
++#define GPI_BUF_SIZE 0x10
++#define GPI_LMEM_ALLOC_ADDR 0x14
++#define GPI_LMEM_FREE_ADDR 0x18
++#define GPI_DDR_ALLOC_ADDR 0x1c
++#define GPI_DDR_FREE_ADDR 0x20
++#define GPI_CLASS_ADDR 0x24
++#define GPI_DRX_FIFO 0x28
++#define GPI_TRX_FIFO 0x2c
++#define GPI_INQ_PKTPTR 0x30
++#define GPI_DDR_DATA_OFFSET 0x34
++#define GPI_LMEM_DATA_OFFSET 0x38
++#define GPI_TMLF_TX 0x4c
++#define GPI_DTX_ASEQ 0x50
++#define GPI_FIFO_STATUS 0x54
++#define GPI_FIFO_DEBUG 0x58
++#define GPI_TX_PAUSE_TIME 0x5c
++#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60
++#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64
++#define GPI_TOE_CHKSUM_EN 0x68
++#define GPI_OVERRUN_DROPCNT 0x6c
++#define GPI_CSR_MTIP_PAUSE_REG 0x74
++#define GPI_CSR_MTIP_PAUSE_QUANTUM 0x78
++#define GPI_CSR_RX_CNT 0x7c
++#define GPI_CSR_TX_CNT 0x80
++#define GPI_CSR_DEBUG1 0x84
++#define GPI_CSR_DEBUG2 0x88
++
++struct gpi_cfg {
++ u32 lmem_rtry_cnt;
++ u32 tmlf_txthres;
++ u32 aseq_len;
++ u32 mtip_pause_reg;
++};
++
++/* GPI commons defines */
++#define GPI_LMEM_BUF_EN 0x1
++#define GPI_DDR_BUF_EN 0x1
++
++/* EGPI 1 defines */
++#define EGPI1_LMEM_RTRY_CNT 0x40
++#define EGPI1_TMLF_TXTHRES 0xBC
++#define EGPI1_ASEQ_LEN 0x50
++
++/* EGPI 2 defines */
++#define EGPI2_LMEM_RTRY_CNT 0x40
++#define EGPI2_TMLF_TXTHRES 0xBC
++#define EGPI2_ASEQ_LEN 0x40
++
++/* EGPI 3 defines */
++#define EGPI3_LMEM_RTRY_CNT 0x40
++#define EGPI3_TMLF_TXTHRES 0xBC
++#define EGPI3_ASEQ_LEN 0x40
++
++/* HGPI defines */
++#define HGPI_LMEM_RTRY_CNT 0x40
++#define HGPI_TMLF_TXTHRES 0xBC
++#define HGPI_ASEQ_LEN 0x40
++
++#define EGPI_PAUSE_TIME 0x000007D0
++#define EGPI_PAUSE_ENABLE 0x40000000
++#endif /* _GPI_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h
+@@ -0,0 +1,100 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _HIF_H_
++#define _HIF_H_
++
++/* @file hif.h.
++ * hif - PFE hif block control and status register.
++ * Mapped on CBUS and accessible from all PE's and ARM.
++ */
++#define HIF_VERSION (HIF_BASE_ADDR + 0x00)
++#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04)
++#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08)
++#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c)
++#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10)
++#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14)
++#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20)
++#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24)
++#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30)
++#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34)
++#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38)
++#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c)
++#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40)
++#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44)
++#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48)
++#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c)
++#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50)
++
++/* HIF_INT_SRC/ HIF_INT_ENABLE control bits */
++#define HIF_INT BIT(0)
++#define HIF_RXBD_INT BIT(1)
++#define HIF_RXPKT_INT BIT(2)
++#define HIF_TXBD_INT BIT(3)
++#define HIF_TXPKT_INT BIT(4)
++
++/* HIF_TX_CTRL bits */
++#define HIF_CTRL_DMA_EN BIT(0)
++#define HIF_CTRL_BDP_POLL_CTRL_EN BIT(1)
++#define HIF_CTRL_BDP_CH_START_WSTB BIT(2)
++
++/* HIF_RX_STATUS bits */
++#define BDP_CSR_RX_DMA_ACTV BIT(16)
++
++/* HIF_INT_ENABLE bits */
++#define HIF_INT_EN BIT(0)
++#define HIF_RXBD_INT_EN BIT(1)
++#define HIF_RXPKT_INT_EN BIT(2)
++#define HIF_TXBD_INT_EN BIT(3)
++#define HIF_TXPKT_INT_EN BIT(4)
++
++/* HIF_POLL_CTRL bits*/
++#define HIF_RX_POLL_CTRL_CYCLE 0x0400
++#define HIF_TX_POLL_CTRL_CYCLE 0x0400
++
++/* HIF_INT_COAL bits*/
++#define HIF_INT_COAL_ENABLE BIT(31)
++
++/* Buffer descriptor control bits */
++#define BD_CTRL_BUFLEN_MASK 0x3fff
++#define BD_BUF_LEN(x) ((x) & BD_CTRL_BUFLEN_MASK)
++#define BD_CTRL_CBD_INT_EN BIT(16)
++#define BD_CTRL_PKT_INT_EN BIT(17)
++#define BD_CTRL_LIFM BIT(18)
++#define BD_CTRL_LAST_BD BIT(19)
++#define BD_CTRL_DIR BIT(20)
++#define BD_CTRL_LMEM_CPY BIT(21) /* Valid only for HIF_NOCPY */
++#define BD_CTRL_PKT_XFER BIT(24)
++#define BD_CTRL_DESC_EN BIT(31)
++#define BD_CTRL_PARSE_DISABLE BIT(25)
++#define BD_CTRL_BRFETCH_DISABLE BIT(26)
++#define BD_CTRL_RTFETCH_DISABLE BIT(27)
++
++/* Buffer descriptor status bits*/
++#define BD_STATUS_CONN_ID(x) ((x) & 0xffff)
++#define BD_STATUS_DIR_PROC_ID BIT(16)
++#define BD_STATUS_CONN_ID_EN BIT(17)
++#define BD_STATUS_PE2PROC_ID(x) (((x) & 7) << 18)
++#define BD_STATUS_LE_DATA BIT(21)
++#define BD_STATUS_CHKSUM_EN BIT(22)
++
++/* HIF Buffer descriptor status bits */
++#define DIR_PROC_ID BIT(16)
++#define PROC_ID(id) ((id) << 18)
++
++#endif /* _HIF_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h
+@@ -0,0 +1,50 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _HIF_NOCPY_H_
++#define _HIF_NOCPY_H_
++
++#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00)
++#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04)
++#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08)
++#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c)
++#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10)
++#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14)
++#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20)
++#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24)
++#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30)
++#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34)
++#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38)
++#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c)
++#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40)
++#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44)
++#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48)
++#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c)
++#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50)
++#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54)
++#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60)
++#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64)
++#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68)
++#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70)
++#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74)
++#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c)
++#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80)
++#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84)
++#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90)
++
++#endif /* _HIF_NOCPY_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h
+@@ -0,0 +1,168 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _TMU_CSR_H_
++#define _TMU_CSR_H_
++
++#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000)
++#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004)
++#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008)
++#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c)
++#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010)
++#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014)
++#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018)
++#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c)
++#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020)
++#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024)
++#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028)
++#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c)
++#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030)
++#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034)
++#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038)
++#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c)
++#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040)
++#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044)
++#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048)
++#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c)
++#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050)
++#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054)
++#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058)
++#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c)
++#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060)
++#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064)
++#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068)
++#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c)
++#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070)
++#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074)
++#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078)
++#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c)
++#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080)
++#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084)
++#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088)
++#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c)
++#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090)
++#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094)
++#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098)
++#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c)
++#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0)
++#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4)
++#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8)
++#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac)
++#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0)
++#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4)
++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
++ * This is a global Enable for all schedulers in PHY0
++ */
++#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8)
++
++#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc)
++#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0)
++#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4)
++#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8)
++#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc)
++#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0)
++#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4)
++#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8)
++#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc)
++#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0)
++
++/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory
++ * Write [27:24] Byte Enables of the Internal memory access [23:0] Address of
++ * the internal memory. This address is used to access both the PM and DM of
++ * all the PE's
++ */
++#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4)
++
++/* Internal Memory Access Write Data */
++#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8)
++/* Internal Memory Access Read Data. The commands are blocked
++ * at the mem_access only
++ */
++#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec)
++
++/* [31:0] PHY0 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0)
++/* [31:0] PHY1 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4)
++/* [31:0] PHY2 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY2_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f8)
++/* [31:0] PHY3 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc)
++#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100)
++#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104)
++
++#define TMU_BUS_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x108)
++#define TMU_BUS_ACCESS (TMU_CSR_BASE_ADDR + 0x10c)
++#define TMU_BUS_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x110)
++
++#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114)
++#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118)
++#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c)
++/* [31:0] PHY4 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134)
++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
++ * This is a global Enable for all schedulers in PHY1
++ */
++#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138)
++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
++ * This is a global Enable for all schedulers in PHY2
++ */
++#define TMU_TDQ2_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x13c)
++/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
++ * This is a global Enable for all schedulers in PHY3
++ */
++#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140)
++#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144)
++/* [31:0] PHY5 in queue address (must be initialized with one of the
++ * xxx_INQ_PKTPTR cbus addresses)
++ */
++#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148)
++
++#define SW_RESET BIT(0) /* Global software reset */
++#define INQ_RESET BIT(2)
++#define TEQ_RESET BIT(3)
++#define TDQ_RESET BIT(4)
++#define PE_RESET BIT(5)
++#define MEM_INIT BIT(6)
++#define MEM_INIT_DONE BIT(7)
++#define LLM_INIT BIT(8)
++#define LLM_INIT_DONE BIT(9)
++#define ECC_MEM_INIT_DONE BIT(10)
++
++struct tmu_cfg {
++ u32 pe_sys_clk_ratio;
++ unsigned long llm_base_addr;
++ u32 llm_queue_len;
++};
++
++/* Not HW related for pfe_ctrl / pfe common defines */
++#define DEFAULT_MAX_QDEPTH 80
++#define DEFAULT_Q0_QDEPTH 511 /*We keep one large queue for host tx qos */
++#define DEFAULT_TMU3_QDEPTH 127
++
++#endif /* _TMU_CSR_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h
+@@ -0,0 +1,61 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _UTIL_CSR_H_
++#define _UTIL_CSR_H_
++
++#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
++#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
++#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
++
++#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
++
++#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
++#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
++#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
++#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
++
++#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
++#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
++#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108)
++
++#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114)
++#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118)
++
++#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200)
++#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204)
++#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208)
++#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c)
++#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210)
++#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214)
++#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218)
++#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c)
++#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220)
++#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224)
++
++#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228)
++#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c)
++#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230)
++
++#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234)
++
++struct util_cfg {
++ u32 pe_sys_clk_ratio;
++};
++
++#endif /* _UTIL_CSR_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/include/pfe/pfe.h
+@@ -0,0 +1,372 @@
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#ifndef _PFE_H_
++#define _PFE_H_
++
++#include "cbus.h"
++
++#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
++/*
++ * Only valid for mem access register interface
++ */
++#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
++#define CLASS_DMEM_SIZE 0x00002000
++#define CLASS_IMEM_SIZE 0x00008000
++
++#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
++/*
++ * Only valid for mem access register interface
++ */
++#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
++#define TMU_DMEM_SIZE 0x00000800
++#define TMU_IMEM_SIZE 0x00002000
++
++#define UTIL_DMEM_BASE_ADDR 0x00000000
++#define UTIL_DMEM_SIZE 0x00002000
++
++#define PE_LMEM_BASE_ADDR 0xc3010000
++#define PE_LMEM_SIZE 0x8000
++#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
++
++#define DMEM_BASE_ADDR 0x00000000
++#define DMEM_SIZE 0x2000 /* TMU has less... */
++#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
++
++#define PMEM_BASE_ADDR 0x00010000
++#define PMEM_SIZE 0x8000 /* TMU has less... */
++#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
++
++/* These check memory ranges from PE point of view/memory map */
++#define IS_DMEM(addr, len) \
++ ({ typeof(addr) addr_ = (addr); \
++ ((unsigned long)(addr_) >= DMEM_BASE_ADDR) && \
++ (((unsigned long)(addr_) + (len)) <= DMEM_END); })
++
++#define IS_PMEM(addr, len) \
++ ({ typeof(addr) addr_ = (addr); \
++ ((unsigned long)(addr_) >= PMEM_BASE_ADDR) && \
++ (((unsigned long)(addr_) + (len)) <= PMEM_END); })
++
++#define IS_PE_LMEM(addr, len) \
++ ({ typeof(addr) addr_ = (addr); \
++ ((unsigned long)(addr_) >= \
++ PE_LMEM_BASE_ADDR) && \
++ (((unsigned long)(addr_) + \
++ (len)) <= PE_LMEM_END); })
++
++#define IS_PFE_LMEM(addr, len) \
++ ({ typeof(addr) addr_ = (addr); \
++ ((unsigned long)(addr_) >= \
++ CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && \
++ (((unsigned long)(addr_) + (len)) <= \
++ CBUS_VIRT_TO_PFE(LMEM_END)); })
++
++#define __IS_PHYS_DDR(addr, len) \
++ ({ typeof(addr) addr_ = (addr); \
++ ((unsigned long)(addr_) >= \
++ DDR_PHYS_BASE_ADDR) && \
++ (((unsigned long)(addr_) + (len)) <= \
++ DDR_PHYS_END); })
++
++#define IS_PHYS_DDR(addr, len) __IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len)
++
++/*
++ * If using a run-time virtual address for the cbus base address use this code
++ */
++extern void *cbus_base_addr;
++extern void *ddr_base_addr;
++extern unsigned long ddr_phys_base_addr;
++extern unsigned int ddr_size;
++
++#define CBUS_BASE_ADDR cbus_base_addr
++#define DDR_PHYS_BASE_ADDR ddr_phys_base_addr
++#define DDR_BASE_ADDR ddr_base_addr
++#define DDR_SIZE ddr_size
++
++#define DDR_PHYS_END (DDR_PHYS_BASE_ADDR + DDR_SIZE)
++
++#define LS1012A_PFE_RESET_WA /*
++ * PFE doesn't have global reset and re-init
++ * should takecare few things to make PFE
++ * functional after reset
++ */
++#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /* CBUS physical base address
++ * as seen by PE's.
++ */
++/* CBUS physical base address as seen by PE's. */
++#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE 0xc0000000
++
++#define DDR_PHYS_TO_PFE(p) (((unsigned long int)(p)) & 0x7FFFFFFF)
++#define DDR_PFE_TO_PHYS(p) (((unsigned long int)(p)) | 0x80000000)
++#define CBUS_PHYS_TO_PFE(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + \
++ PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE)
++/* Translates to PFE address map */
++
++#define DDR_PHYS_TO_VIRT(p) (((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR)
++#define DDR_VIRT_TO_PHYS(v) (((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR)
++#define DDR_VIRT_TO_PFE(p) (DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p)))
++
++#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + \
++ PFE_CBUS_PHYS_BASE_ADDR)
++#define CBUS_PFE_TO_VIRT(p) (((unsigned long int)(p) - \
++ PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
++
++/* The below part of the code is used in QOS control driver from host */
++#define TMU_APB_BASE_ADDR 0xc1000000 /* TMU base address seen by
++ * pe's
++ */
++
++enum {
++ CLASS0_ID = 0,
++ CLASS1_ID,
++ CLASS2_ID,
++ CLASS3_ID,
++ CLASS4_ID,
++ CLASS5_ID,
++ TMU0_ID,
++ TMU1_ID,
++ TMU2_ID,
++ TMU3_ID,
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ UTIL_ID,
++#endif
++ MAX_PE
++};
++
++#define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) |\
++ BIT(CLASS2_ID) | BIT(CLASS3_ID) |\
++ BIT(CLASS4_ID) | BIT(CLASS5_ID))
++#define CLASS_MAX_ID CLASS5_ID
++
++#define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) |\
++ BIT(TMU3_ID))
++
++#define TMU_MAX_ID TMU3_ID
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++#define UTIL_MASK BIT(UTIL_ID)
++#endif
++
++struct pe_status {
++ u32 cpu_state;
++ u32 activity_counter;
++ u32 rx;
++ union {
++ u32 tx;
++ u32 tmu_qstatus;
++ };
++ u32 drop;
++#if defined(CFG_PE_DEBUG)
++ u32 debug_indicator;
++ u32 debug[16];
++#endif
++} __aligned(16);
++
++struct pe_sync_mailbox {
++ u32 stop;
++ u32 stopped;
++};
++
++/* Drop counter definitions */
++
++#define CLASS_NUM_DROP_COUNTERS 13
++#define UTIL_NUM_DROP_COUNTERS 8
++
++/* PE information.
++ * Structure containing PE's specific information. It is used to create
++ * generic C functions common to all PE's.
++ * Before using the library functions this structure needs to be initialized
++ * with the different registers virtual addresses
++ * (according to the ARM MMU mmaping). The default initialization supports a
++ * virtual == physical mapping.
++ */
++struct pe_info {
++ u32 dmem_base_addr; /* PE's dmem base address */
++ u32 pmem_base_addr; /* PE's pmem base address */
++ u32 pmem_size; /* PE's pmem size */
++
++ void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA register
++ * address
++ */
++ void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR register
++ * address
++ */
++ void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA register
++ * address
++ */
++};
++
++void pe_lmem_read(u32 *dst, u32 len, u32 offset);
++void pe_lmem_write(u32 *src, u32 len, u32 offset);
++
++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
++
++u32 pe_pmem_read(int id, u32 addr, u8 size);
++
++void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
++u32 pe_dmem_read(int id, u32 addr, u8 size);
++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len);
++void class_pe_lmem_memset(u32 dst, int val, unsigned int len);
++void class_bus_write(u32 val, u32 addr, u8 size);
++u32 class_bus_read(u32 addr, u8 size);
++
++#define class_bus_readl(addr) class_bus_read(addr, 4)
++#define class_bus_readw(addr) class_bus_read(addr, 2)
++#define class_bus_readb(addr) class_bus_read(addr, 1)
++
++#define class_bus_writel(val, addr) class_bus_write(val, addr, 4)
++#define class_bus_writew(val, addr) class_bus_write(val, addr, 2)
++#define class_bus_writeb(val, addr) class_bus_write(val, addr, 1)
++
++#define pe_dmem_readl(id, addr) pe_dmem_read(id, addr, 4)
++#define pe_dmem_readw(id, addr) pe_dmem_read(id, addr, 2)
++#define pe_dmem_readb(id, addr) pe_dmem_read(id, addr, 1)
++
++#define pe_dmem_writel(id, val, addr) pe_dmem_write(id, val, addr, 4)
++#define pe_dmem_writew(id, val, addr) pe_dmem_write(id, val, addr, 2)
++#define pe_dmem_writeb(id, val, addr) pe_dmem_write(id, val, addr, 1)
++
++/*int pe_load_elf_section(int id, const void *data, elf32_shdr *shdr); */
++int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr,
++ struct device *dev);
++
++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,
++ unsigned int ddr_size);
++void bmu_init(void *base, struct BMU_CFG *cfg);
++void bmu_reset(void *base);
++void bmu_enable(void *base);
++void bmu_disable(void *base);
++void bmu_set_config(void *base, struct BMU_CFG *cfg);
++
++/*
++ * An enumerated type for loopback values. This can be one of three values, no
++ * loopback -normal operation, local loopback with internal loopback module of
++ * MAC or PHY loopback which is through the external PHY.
++ */
++#ifndef __MAC_LOOP_ENUM__
++#define __MAC_LOOP_ENUM__
++enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL};
++#endif
++
++void gemac_init(void *base, void *config);
++void gemac_disable_rx_checksum_offload(void *base);
++void gemac_enable_rx_checksum_offload(void *base);
++void gemac_set_speed(void *base, enum mac_speed gem_speed);
++void gemac_set_duplex(void *base, int duplex);
++void gemac_set_mode(void *base, int mode);
++void gemac_enable(void *base);
++void gemac_tx_disable(void *base);
++void gemac_tx_enable(void *base);
++void gemac_disable(void *base);
++void gemac_reset(void *base);
++void gemac_set_address(void *base, struct spec_addr *addr);
++struct spec_addr gemac_get_address(void *base);
++void gemac_set_loop(void *base, enum mac_loop gem_loop);
++void gemac_set_laddr1(void *base, struct pfe_mac_addr *address);
++void gemac_set_laddr2(void *base, struct pfe_mac_addr *address);
++void gemac_set_laddr3(void *base, struct pfe_mac_addr *address);
++void gemac_set_laddr4(void *base, struct pfe_mac_addr *address);
++void gemac_set_laddrN(void *base, struct pfe_mac_addr *address,
++ unsigned int entry_index);
++void gemac_clear_laddr1(void *base);
++void gemac_clear_laddr2(void *base);
++void gemac_clear_laddr3(void *base);
++void gemac_clear_laddr4(void *base);
++void gemac_clear_laddrN(void *base, unsigned int entry_index);
++struct pfe_mac_addr gemac_get_hash(void *base);
++void gemac_set_hash(void *base, struct pfe_mac_addr *hash);
++struct pfe_mac_addr gem_get_laddr1(void *base);
++struct pfe_mac_addr gem_get_laddr2(void *base);
++struct pfe_mac_addr gem_get_laddr3(void *base);
++struct pfe_mac_addr gem_get_laddr4(void *base);
++struct pfe_mac_addr gem_get_laddrN(void *base, unsigned int entry_index);
++void gemac_set_config(void *base, struct gemac_cfg *cfg);
++void gemac_allow_broadcast(void *base);
++void gemac_no_broadcast(void *base);
++void gemac_enable_1536_rx(void *base);
++void gemac_disable_1536_rx(void *base);
++void gemac_set_rx_max_fl(void *base, int mtu);
++void gemac_enable_rx_jmb(void *base);
++void gemac_disable_rx_jmb(void *base);
++void gemac_enable_stacked_vlan(void *base);
++void gemac_disable_stacked_vlan(void *base);
++void gemac_enable_pause_rx(void *base);
++void gemac_disable_pause_rx(void *base);
++void gemac_enable_copy_all(void *base);
++void gemac_disable_copy_all(void *base);
++void gemac_set_bus_width(void *base, int width);
++void gemac_set_wol(void *base, u32 wol_conf);
++
++void gpi_init(void *base, struct gpi_cfg *cfg);
++void gpi_reset(void *base);
++void gpi_enable(void *base);
++void gpi_disable(void *base);
++void gpi_set_config(void *base, struct gpi_cfg *cfg);
++
++void class_init(struct class_cfg *cfg);
++void class_reset(void);
++void class_enable(void);
++void class_disable(void);
++void class_set_config(struct class_cfg *cfg);
++
++void tmu_reset(void);
++void tmu_init(struct tmu_cfg *cfg);
++void tmu_enable(u32 pe_mask);
++void tmu_disable(u32 pe_mask);
++u32 tmu_qstatus(u32 if_id);
++u32 tmu_pkts_processed(u32 if_id);
++
++void util_init(struct util_cfg *cfg);
++void util_reset(void);
++void util_enable(void);
++void util_disable(void);
++
++void hif_init(void);
++void hif_tx_enable(void);
++void hif_tx_disable(void);
++void hif_rx_enable(void);
++void hif_rx_disable(void);
++
++/* Get Chip Revision level
++ *
++ */
++static inline unsigned int CHIP_REVISION(void)
++{
++ /*For LS1012A return always 1 */
++ return 1;
++}
++
++/* Start HIF rx DMA
++ *
++ */
++static inline void hif_rx_dma_start(void)
++{
++ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL);
++}
++
++/* Start HIF tx DMA
++ *
++ */
++static inline void hif_tx_dma_start(void)
++{
++ writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL);
++}
++
++#endif /* _PFE_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_cdev.c
+@@ -0,0 +1,258 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2018 NXP
++ */
++
++/* @pfe_cdev.c.
++ * Dummy device representing the PFE US in userspace.
++ * - used for interacting with the kernel layer for link status
++ */
++
++#include <linux/eventfd.h>
++#include <linux/irqreturn.h>
++#include <linux/io.h>
++#include <asm/irq.h>
++
++#include "pfe_cdev.h"
++#include "pfe_mod.h"
++
++static int pfe_majno;
++static struct class *pfe_char_class;
++static struct device *pfe_char_dev;
++struct eventfd_ctx *g_trigger;
++
++struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT];
++
++static int pfe_cdev_open(struct inode *inp, struct file *fp)
++{
++ pr_debug("PFE CDEV device opened.\n");
++ return 0;
++}
++
++static ssize_t pfe_cdev_read(struct file *fp, char *buf,
++ size_t len, loff_t *off)
++{
++ int ret = 0;
++
++ pr_info("PFE CDEV attempt copying (%lu) size of user.\n",
++ sizeof(link_states));
++
++ pr_debug("Dump link_state on screen before copy_to_user\n");
++ for (; ret < PFE_CDEV_ETH_COUNT; ret++) {
++ pr_debug("%u %u", link_states[ret].phy_id,
++ link_states[ret].state);
++ pr_debug("\n");
++ }
++
++ /* Copy to user the value in buffer sized len */
++ ret = copy_to_user(buf, &link_states, sizeof(link_states));
++ if (ret != 0) {
++ pr_err("Failed to send (%d)bytes of (%lu) requested.\n",
++ ret, len);
++ return -EFAULT;
++ }
++
++ /* offset set back to 0 as there is contextual reading offset */
++ *off = 0;
++ pr_debug("Read of (%lu) bytes performed.\n", sizeof(link_states));
++
++ return sizeof(link_states);
++}
++
++/**
++ * This function is for getting some commands from user through non-IOCTL
++ * channel. It can used to configure the device.
++ * TODO: To be filled in future, if require duplex communication with user
++ * space.
++ */
++static ssize_t pfe_cdev_write(struct file *fp, const char *buf,
++ size_t len, loff_t *off)
++{
++ pr_info("PFE CDEV Write operation not supported!\n");
++
++ return -EFAULT;
++}
++
++static int pfe_cdev_release(struct inode *inp, struct file *fp)
++{
++ if (g_trigger) {
++ free_irq(pfe->hif_irq, g_trigger);
++ eventfd_ctx_put(g_trigger);
++ g_trigger = NULL;
++ }
++
++ pr_info("PFE_CDEV: Device successfully closed\n");
++ return 0;
++}
++
++/*
++ * hif_us_isr-
++ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block
++ */
++static irqreturn_t hif_us_isr(int irq, void *arg)
++{
++ struct eventfd_ctx *trigger = (struct eventfd_ctx *)arg;
++ int int_status;
++ int int_enable_mask;
++
++ /*Read hif interrupt source register */
++ int_status = readl_relaxed(HIF_INT_SRC);
++ int_enable_mask = readl_relaxed(HIF_INT_ENABLE);
++
++ if ((int_status & HIF_INT) == 0)
++ return IRQ_NONE;
++
++ if (int_status & HIF_RXPKT_INT) {
++ int_enable_mask &= ~(HIF_RXPKT_INT);
++ /* Disable interrupts, they will be enabled after
++ * they are serviced
++ */
++ writel_relaxed(int_enable_mask, HIF_INT_ENABLE);
++
++ eventfd_signal(trigger, 1);
++ }
++
++ return IRQ_HANDLED;
++}
++
++#define PFE_INTR_COAL_USECS 100
++static long pfe_cdev_ioctl(struct file *fp, unsigned int cmd,
++ unsigned long arg)
++{
++ int ret = -EFAULT;
++ int __user *argp = (int __user *)arg;
++
++ pr_debug("PFE CDEV IOCTL Called with cmd=(%u)\n", cmd);
++
++ switch (cmd) {
++ case PFE_CDEV_ETH0_STATE_GET:
++ /* Return an unsigned int (link state) for ETH0 */
++ *argp = link_states[0].state;
++ pr_debug("Returning state=%d for ETH0\n", *argp);
++ ret = 0;
++ break;
++ case PFE_CDEV_ETH1_STATE_GET:
++ /* Return an unsigned int (link state) for ETH0 */
++ *argp = link_states[1].state;
++ pr_debug("Returning state=%d for ETH1\n", *argp);
++ ret = 0;
++ break;
++ case PFE_CDEV_HIF_INTR_EN:
++ /* Return success/failure */
++ g_trigger = eventfd_ctx_fdget(*argp);
++ if (IS_ERR(g_trigger))
++ return PTR_ERR(g_trigger);
++ ret = request_irq(pfe->hif_irq, hif_us_isr, 0, "pfe_hif",
++ g_trigger);
++ if (ret) {
++ pr_err("%s: failed to get the hif IRQ = %d\n",
++ __func__, pfe->hif_irq);
++ eventfd_ctx_put(g_trigger);
++ g_trigger = NULL;
++ }
++ writel((PFE_INTR_COAL_USECS * (pfe->ctrl.sys_clk / 1000)) |
++ HIF_INT_COAL_ENABLE, HIF_INT_COAL);
++
++ pr_debug("request_irq for hif interrupt: %d\n", pfe->hif_irq);
++ ret = 0;
++ break;
++ default:
++ pr_info("Unsupport cmd (%d) for PFE CDEV.\n", cmd);
++ break;
++ };
++
++ return ret;
++}
++
++static unsigned int pfe_cdev_poll(struct file *fp,
++ struct poll_table_struct *wait)
++{
++ pr_info("PFE CDEV poll method not supported\n");
++ return 0;
++}
++
++static const struct file_operations pfe_cdev_fops = {
++ .open = pfe_cdev_open,
++ .read = pfe_cdev_read,
++ .write = pfe_cdev_write,
++ .release = pfe_cdev_release,
++ .unlocked_ioctl = pfe_cdev_ioctl,
++ .poll = pfe_cdev_poll,
++};
++
++int pfe_cdev_init(void)
++{
++ int ret;
++
++ pr_debug("PFE CDEV initialization begin\n");
++
++ /* Register the major number for the device */
++ pfe_majno = register_chrdev(0, PFE_CDEV_NAME, &pfe_cdev_fops);
++ if (pfe_majno < 0) {
++ pr_err("Unable to register PFE CDEV. PFE CDEV not available\n");
++ ret = pfe_majno;
++ goto cleanup;
++ }
++
++ pr_debug("PFE CDEV assigned major number: %d\n", pfe_majno);
++
++ /* Register the class for the device */
++ pfe_char_class = class_create(PFE_CLASS_NAME);
++ if (IS_ERR(pfe_char_class)) {
++ pr_err(
++ "Failed to init class for PFE CDEV. PFE CDEV not available.\n");
++ ret = PTR_ERR(pfe_char_class);
++ goto cleanup;
++ }
++
++ pr_debug("PFE CDEV Class created successfully.\n");
++
++ /* Create the device without any parent and without any callback data */
++ pfe_char_dev = device_create(pfe_char_class, NULL,
++ MKDEV(pfe_majno, 0), NULL,
++ PFE_CDEV_NAME);
++ if (IS_ERR(pfe_char_dev)) {
++ pr_err("Unable to PFE CDEV device. PFE CDEV not available.\n");
++ ret = PTR_ERR(pfe_char_dev);
++ goto cleanup;
++ }
++
++ /* Information structure being shared with the userspace */
++ memset(link_states, 0, sizeof(struct pfe_shared_info) *
++ PFE_CDEV_ETH_COUNT);
++
++ pr_info("PFE CDEV created: %s\n", PFE_CDEV_NAME);
++
++ ret = 0;
++ return ret;
++
++cleanup:
++ if (!IS_ERR(pfe_char_class))
++ class_destroy(pfe_char_class);
++
++ if (pfe_majno > 0)
++ unregister_chrdev(pfe_majno, PFE_CDEV_NAME);
++
++ return ret;
++}
++
++void pfe_cdev_exit(void)
++{
++ if (!IS_ERR(pfe_char_dev))
++ device_destroy(pfe_char_class, MKDEV(pfe_majno, 0));
++
++ if (!IS_ERR(pfe_char_class)) {
++ class_unregister(pfe_char_class);
++ class_destroy(pfe_char_class);
++ }
++
++ if (pfe_majno > 0)
++ unregister_chrdev(pfe_majno, PFE_CDEV_NAME);
++
++ /* reset the variables */
++ pfe_majno = 0;
++ pfe_char_class = NULL;
++ pfe_char_dev = NULL;
++
++ pr_info("PFE CDEV Removed.\n");
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_cdev.h
+@@ -0,0 +1,41 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2018 NXP
++ */
++
++#ifndef _PFE_CDEV_H_
++#define _PFE_CDEV_H_
++
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/kernel.h>
++#include <linux/fs.h>
++#include <linux/uaccess.h>
++#include <linux/poll.h>
++
++#define PFE_CDEV_NAME "pfe_us_cdev"
++#define PFE_CLASS_NAME "ppfe_us"
++
++/* Extracted from ls1012a_pfe_platform_data, there are 3 interfaces which are
++ * supported by PFE driver. Should be updated if number of eth devices are
++ * changed.
++ */
++#define PFE_CDEV_ETH_COUNT 3
++
++struct pfe_shared_info {
++ uint32_t phy_id; /* Link phy ID */
++ uint8_t state; /* Has either 0 or 1 */
++};
++
++extern struct pfe_shared_info link_states[PFE_CDEV_ETH_COUNT];
++
++/* IOCTL Commands */
++#define PFE_CDEV_ETH0_STATE_GET _IOR('R', 0, int)
++#define PFE_CDEV_ETH1_STATE_GET _IOR('R', 1, int)
++#define PFE_CDEV_HIF_INTR_EN _IOWR('R', 2, int)
++
++int pfe_cdev_init(void);
++void pfe_cdev_exit(void);
++
++#endif /* _PFE_CDEV_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_ctrl.c
+@@ -0,0 +1,226 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/kernel.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <linux/list.h>
++#include <linux/kthread.h>
++
++#include "pfe_mod.h"
++#include "pfe_ctrl.h"
++
++#define TIMEOUT_MS 1000
++
++int relax(unsigned long end)
++{
++ if (time_after(jiffies, end)) {
++ if (time_after(jiffies, end + (TIMEOUT_MS * HZ) / 1000))
++ return -1;
++
++ if (need_resched())
++ schedule();
++ }
++
++ return 0;
++}
++
++void pfe_ctrl_suspend(struct pfe_ctrl *ctrl)
++{
++ int id;
++
++ mutex_lock(&ctrl->mutex);
++
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++)
++ pe_dmem_write(id, cpu_to_be32(0x1), CLASS_DM_RESUME, 4);
++
++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) {
++ if (id == TMU2_ID)
++ continue;
++ pe_dmem_write(id, cpu_to_be32(0x1), TMU_DM_RESUME, 4);
++ }
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ pe_dmem_write(UTIL_ID, cpu_to_be32(0x1), UTIL_DM_RESUME, 4);
++#endif
++ mutex_unlock(&ctrl->mutex);
++}
++
++void pfe_ctrl_resume(struct pfe_ctrl *ctrl)
++{
++ int pe_mask = CLASS_MASK | TMU_MASK;
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ pe_mask |= UTIL_MASK;
++#endif
++ mutex_lock(&ctrl->mutex);
++ pe_start(&pfe->ctrl, pe_mask);
++ mutex_unlock(&ctrl->mutex);
++}
++
++/* PE sync stop.
++ * Stops packet processing for a list of PE's (specified using a bitmask).
++ * The caller must hold ctrl->mutex.
++ *
++ * @param ctrl Control context
++ * @param pe_mask Mask of PE id's to stop
++ *
++ */
++int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask)
++{
++ struct pe_sync_mailbox *mbox;
++ int pe_stopped = 0;
++ unsigned long end = jiffies + 2;
++ int i;
++
++ pe_mask &= 0x2FF; /*Exclude Util + TMU2 */
++
++ for (i = 0; i < MAX_PE; i++)
++ if (pe_mask & (1 << i)) {
++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++ pe_dmem_write(i, cpu_to_be32(0x1), (unsigned
++ long)&mbox->stop, 4);
++ }
++
++ while (pe_stopped != pe_mask) {
++ for (i = 0; i < MAX_PE; i++)
++ if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) {
++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++ if (pe_dmem_read(i, (unsigned
++ long)&mbox->stopped, 4) &
++ cpu_to_be32(0x1))
++ pe_stopped |= (1 << i);
++ }
++
++ if (relax(end) < 0)
++ goto err;
++ }
++
++ return 0;
++
++err:
++ pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped);
++
++ for (i = 0; i < MAX_PE; i++)
++ if (pe_mask & (1 << i)) {
++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned
++ long)&mbox->stop, 4);
++ }
++
++ return -EIO;
++}
++
++/* PE start.
++ * Starts packet processing for a list of PE's (specified using a bitmask).
++ * The caller must hold ctrl->mutex.
++ *
++ * @param ctrl Control context
++ * @param pe_mask Mask of PE id's to start
++ *
++ */
++void pe_start(struct pfe_ctrl *ctrl, int pe_mask)
++{
++ struct pe_sync_mailbox *mbox;
++ int i;
++
++ for (i = 0; i < MAX_PE; i++)
++ if (pe_mask & (1 << i)) {
++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++ pe_dmem_write(i, cpu_to_be32(0x0), (unsigned
++ long)&mbox->stop, 4);
++ }
++}
++
++/* This function will ensure all PEs are put in to idle state */
++int pe_reset_all(struct pfe_ctrl *ctrl)
++{
++ struct pe_sync_mailbox *mbox;
++ int pe_stopped = 0;
++ unsigned long end = jiffies + 2;
++ int i;
++ int pe_mask = CLASS_MASK | TMU_MASK;
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ pe_mask |= UTIL_MASK;
++#endif
++
++ for (i = 0; i < MAX_PE; i++)
++ if (pe_mask & (1 << i)) {
++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++ pe_dmem_write(i, cpu_to_be32(0x2), (unsigned
++ long)&mbox->stop, 4);
++ }
++
++ while (pe_stopped != pe_mask) {
++ for (i = 0; i < MAX_PE; i++)
++ if ((pe_mask & (1 << i)) && !(pe_stopped & (1 << i))) {
++ mbox = (void *)ctrl->sync_mailbox_baseaddr[i];
++
++ if (pe_dmem_read(i, (unsigned long)
++ &mbox->stopped, 4) &
++ cpu_to_be32(0x1))
++ pe_stopped |= (1 << i);
++ }
++
++ if (relax(end) < 0)
++ goto err;
++ }
++
++ return 0;
++
++err:
++ pr_err("%s: timeout, %x %x\n", __func__, pe_mask, pe_stopped);
++ return -EIO;
++}
++
++int pfe_ctrl_init(struct pfe *pfe)
++{
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++ int id;
++
++ pr_info("%s\n", __func__);
++
++ mutex_init(&ctrl->mutex);
++ spin_lock_init(&ctrl->lock);
++
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++ ctrl->sync_mailbox_baseaddr[id] = CLASS_DM_SYNC_MBOX;
++ ctrl->msg_mailbox_baseaddr[id] = CLASS_DM_MSG_MBOX;
++ }
++
++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) {
++ if (id == TMU2_ID)
++ continue;
++ ctrl->sync_mailbox_baseaddr[id] = TMU_DM_SYNC_MBOX;
++ ctrl->msg_mailbox_baseaddr[id] = TMU_DM_MSG_MBOX;
++ }
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ ctrl->sync_mailbox_baseaddr[UTIL_ID] = UTIL_DM_SYNC_MBOX;
++ ctrl->msg_mailbox_baseaddr[UTIL_ID] = UTIL_DM_MSG_MBOX;
++#endif
++
++ ctrl->hash_array_baseaddr = pfe->ddr_baseaddr + ROUTE_TABLE_BASEADDR;
++ ctrl->hash_array_phys_baseaddr = pfe->ddr_phys_baseaddr +
++ ROUTE_TABLE_BASEADDR;
++
++ ctrl->dev = pfe->dev;
++
++ pr_info("%s finished\n", __func__);
++
++ return 0;
++}
++
++void pfe_ctrl_exit(struct pfe *pfe)
++{
++ pr_info("%s\n", __func__);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_ctrl.h
+@@ -0,0 +1,100 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_CTRL_H_
++#define _PFE_CTRL_H_
++
++#include <linux/dmapool.h>
++
++#include "pfe/pfe.h"
++
++#define DMA_BUF_SIZE_128 0x80 /* enough for 1 conntracks */
++#define DMA_BUF_SIZE_256 0x100
++/* enough for 2 conntracks, 1 bridge entry or 1 multicast entry */
++#define DMA_BUF_SIZE_512 0x200
++/* 512bytes dma allocated buffers used by rtp relay feature */
++#define DMA_BUF_MIN_ALIGNMENT 8
++#define DMA_BUF_BOUNDARY (4 * 1024)
++/* bursts can not cross 4k boundary */
++
++#define CMD_TX_ENABLE 0x0501
++#define CMD_TX_DISABLE 0x0502
++
++#define CMD_RX_LRO 0x0011
++#define CMD_PKTCAP_ENABLE 0x0d01
++#define CMD_QM_EXPT_RATE 0x020c
++
++#define CLASS_DM_SH_STATIC (0x800)
++#define CLASS_DM_CPU_TICKS (CLASS_DM_SH_STATIC)
++#define CLASS_DM_SYNC_MBOX (0x808)
++#define CLASS_DM_MSG_MBOX (0x810)
++#define CLASS_DM_DROP_CNTR (0x820)
++#define CLASS_DM_RESUME (0x854)
++#define CLASS_DM_PESTATUS (0x860)
++#define CLASS_DM_CRC_VALIDATED (0x14b0)
++
++#define TMU_DM_SH_STATIC (0x80)
++#define TMU_DM_CPU_TICKS (TMU_DM_SH_STATIC)
++#define TMU_DM_SYNC_MBOX (0x88)
++#define TMU_DM_MSG_MBOX (0x90)
++#define TMU_DM_RESUME (0xA0)
++#define TMU_DM_PESTATUS (0xB0)
++#define TMU_DM_CONTEXT (0x300)
++#define TMU_DM_TX_TRANS (0x480)
++
++#define UTIL_DM_SH_STATIC (0x0)
++#define UTIL_DM_CPU_TICKS (UTIL_DM_SH_STATIC)
++#define UTIL_DM_SYNC_MBOX (0x8)
++#define UTIL_DM_MSG_MBOX (0x10)
++#define UTIL_DM_DROP_CNTR (0x20)
++#define UTIL_DM_RESUME (0x40)
++#define UTIL_DM_PESTATUS (0x50)
++
++struct pfe_ctrl {
++ struct mutex mutex; /* to serialize pfe control access */
++ spinlock_t lock;
++
++ void *dma_pool;
++ void *dma_pool_512;
++ void *dma_pool_128;
++
++ struct device *dev;
++
++ void *hash_array_baseaddr; /*
++ * Virtual base address of
++ * the conntrack hash array
++ */
++ unsigned long hash_array_phys_baseaddr; /*
++ * Physical base address of
++ * the conntrack hash array
++ */
++
++ int (*event_cb)(u16, u16, u16*);
++
++ unsigned long sync_mailbox_baseaddr[MAX_PE]; /*
++ * Sync mailbox PFE
++ * internal address,
++ * initialized
++ * when parsing elf images
++ */
++ unsigned long msg_mailbox_baseaddr[MAX_PE]; /*
++ * Msg mailbox PFE internal
++ * address, initialized
++ * when parsing elf images
++ */
++ unsigned int sys_clk; /* AXI clock value, in KHz */
++};
++
++int pfe_ctrl_init(struct pfe *pfe);
++void pfe_ctrl_exit(struct pfe *pfe);
++int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask);
++void pe_start(struct pfe_ctrl *ctrl, int pe_mask);
++int pe_reset_all(struct pfe_ctrl *ctrl);
++void pfe_ctrl_suspend(struct pfe_ctrl *ctrl);
++void pfe_ctrl_resume(struct pfe_ctrl *ctrl);
++int relax(unsigned long end);
++
++#endif /* _PFE_CTRL_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_debugfs.c
+@@ -0,0 +1,99 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/module.h>
++#include <linux/debugfs.h>
++#include <linux/platform_device.h>
++
++#include "pfe_mod.h"
++
++static int dmem_show(struct seq_file *s, void *unused)
++{
++ u32 dmem_addr, val;
++ int id = (long int)s->private;
++ int i;
++
++ for (dmem_addr = 0; dmem_addr < CLASS_DMEM_SIZE; dmem_addr += 8 * 4) {
++ seq_printf(s, "%04x:", dmem_addr);
++
++ for (i = 0; i < 8; i++) {
++ val = pe_dmem_read(id, dmem_addr + i * 4, 4);
++ seq_printf(s, " %02x %02x %02x %02x", val & 0xff,
++ (val >> 8) & 0xff, (val >> 16) & 0xff,
++ (val >> 24) & 0xff);
++ }
++
++ seq_puts(s, "\n");
++ }
++
++ return 0;
++}
++
++static int dmem_open(struct inode *inode, struct file *file)
++{
++ return single_open(file, dmem_show, inode->i_private);
++}
++
++static const struct file_operations dmem_fops = {
++ .open = dmem_open,
++ .read = seq_read,
++ .llseek = seq_lseek,
++ .release = single_release,
++};
++
++int pfe_debugfs_init(struct pfe *pfe)
++{
++ struct dentry *d;
++
++ pr_info("%s\n", __func__);
++
++ pfe->dentry = debugfs_create_dir("pfe", NULL);
++ if (IS_ERR_OR_NULL(pfe->dentry))
++ goto err_dir;
++
++ d = debugfs_create_file("pe0_dmem", 0444, pfe->dentry, (void *)0,
++ &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ d = debugfs_create_file("pe1_dmem", 0444, pfe->dentry, (void *)1,
++ &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ d = debugfs_create_file("pe2_dmem", 0444, pfe->dentry, (void *)2,
++ &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ d = debugfs_create_file("pe3_dmem", 0444, pfe->dentry, (void *)3,
++ &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ d = debugfs_create_file("pe4_dmem", 0444, pfe->dentry, (void *)4,
++ &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ d = debugfs_create_file("pe5_dmem", 0444, pfe->dentry, (void *)5,
++ &dmem_fops);
++ if (IS_ERR_OR_NULL(d))
++ goto err_pe;
++
++ return 0;
++
++err_pe:
++ debugfs_remove_recursive(pfe->dentry);
++
++err_dir:
++ return -1;
++}
++
++void pfe_debugfs_exit(struct pfe *pfe)
++{
++ debugfs_remove_recursive(pfe->dentry);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_debugfs.h
+@@ -0,0 +1,13 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_DEBUGFS_H_
++#define _PFE_DEBUGFS_H_
++
++int pfe_debugfs_init(struct pfe *pfe);
++void pfe_debugfs_exit(struct pfe *pfe);
++
++#endif /* _PFE_DEBUGFS_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_eth.c
+@@ -0,0 +1,2550 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++/* @pfe_eth.c.
++ * Ethernet driver for to handle exception path for PFE.
++ * - uses HIF functions to send/receive packets.
++ * - uses ctrl function to start/stop interfaces.
++ * - uses direct register accesses to control phy operation.
++ */
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/mii.h>
++#include <linux/phy.h>
++#include <linux/timer.h>
++#include <linux/hrtimer.h>
++#include <linux/platform_device.h>
++
++#include <net/ip.h>
++#include <net/sock.h>
++
++#include <linux/of.h>
++#include <linux/of_mdio.h>
++
++#include <linux/io.h>
++#include <asm/irq.h>
++#include <linux/delay.h>
++#include <linux/regmap.h>
++#include <linux/i2c.h>
++#include <linux/sys_soc.h>
++
++#if defined(CONFIG_NF_CONNTRACK_MARK)
++#include <net/netfilter/nf_conntrack.h>
++#endif
++
++#include "pfe_mod.h"
++#include "pfe_eth.h"
++#include "pfe_cdev.h"
++
++#define LS1012A_REV_1_0 0x87040010
++
++bool pfe_use_old_dts_phy;
++bool pfe_errata_a010897;
++
++static void *cbus_emac_base[3];
++static void *cbus_gpi_base[3];
++
++/* Forward Declaration */
++static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv);
++static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv);
++static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int
++ from_tx, int n_desc);
++
++/* MDIO registers */
++#define MDIO_SGMII_CR 0x00
++#define MDIO_SGMII_SR 0x01
++#define MDIO_SGMII_DEV_ABIL_SGMII 0x04
++#define MDIO_SGMII_LINK_TMR_L 0x12
++#define MDIO_SGMII_LINK_TMR_H 0x13
++#define MDIO_SGMII_IF_MODE 0x14
++
++/* SGMII Control defines */
++#define SGMII_CR_RST 0x8000
++#define SGMII_CR_AN_EN 0x1000
++#define SGMII_CR_RESTART_AN 0x0200
++#define SGMII_CR_FD 0x0100
++#define SGMII_CR_SPEED_SEL1_1G 0x0040
++#define SGMII_CR_DEF_VAL (SGMII_CR_AN_EN | SGMII_CR_FD | \
++ SGMII_CR_SPEED_SEL1_1G)
++
++/* SGMII IF Mode */
++#define SGMII_DUPLEX_HALF 0x10
++#define SGMII_SPEED_10MBPS 0x00
++#define SGMII_SPEED_100MBPS 0x04
++#define SGMII_SPEED_1GBPS 0x08
++#define SGMII_USE_SGMII_AN 0x02
++#define SGMII_EN 0x01
++
++/* SGMII Device Ability for SGMII */
++#define SGMII_DEV_ABIL_ACK 0x4000
++#define SGMII_DEV_ABIL_EEE_CLK_STP_EN 0x0100
++#define SGMII_DEV_ABIL_SGMII 0x0001
++
++unsigned int gemac_regs[] = {
++ 0x0004, /* Interrupt event */
++ 0x0008, /* Interrupt mask */
++ 0x0024, /* Ethernet control */
++ 0x0064, /* MIB Control/Status */
++ 0x0084, /* Receive control/status */
++ 0x00C4, /* Transmit control */
++ 0x00E4, /* Physical address low */
++ 0x00E8, /* Physical address high */
++ 0x0144, /* Transmit FIFO Watermark and Store and Forward Control*/
++ 0x0190, /* Receive FIFO Section Full Threshold */
++ 0x01A0, /* Transmit FIFO Section Empty Threshold */
++ 0x01B0, /* Frame Truncation Length */
++};
++
++const struct soc_device_attribute ls1012a_rev1_soc_attr[] = {
++ { .family = "QorIQ LS1012A",
++ .soc_id = "svr:0x87040010",
++ .revision = "1.0",
++ .data = NULL },
++ { },
++};
++
++/********************************************************************/
++/* SYSFS INTERFACE */
++/********************************************************************/
++
++#ifdef PFE_ETH_NAPI_STATS
++/*
++ * pfe_eth_show_napi_stats
++ */
++static ssize_t pfe_eth_show_napi_stats(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ ssize_t len = 0;
++
++ len += sprintf(buf + len, "sched: %u\n",
++ priv->napi_counters[NAPI_SCHED_COUNT]);
++ len += sprintf(buf + len, "poll: %u\n",
++ priv->napi_counters[NAPI_POLL_COUNT]);
++ len += sprintf(buf + len, "packet: %u\n",
++ priv->napi_counters[NAPI_PACKET_COUNT]);
++ len += sprintf(buf + len, "budget: %u\n",
++ priv->napi_counters[NAPI_FULL_BUDGET_COUNT]);
++ len += sprintf(buf + len, "desc: %u\n",
++ priv->napi_counters[NAPI_DESC_COUNT]);
++
++ return len;
++}
++
++/*
++ * pfe_eth_set_napi_stats
++ */
++static ssize_t pfe_eth_set_napi_stats(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++
++ memset(priv->napi_counters, 0, sizeof(priv->napi_counters));
++
++ return count;
++}
++#endif
++#ifdef PFE_ETH_TX_STATS
++/* pfe_eth_show_tx_stats
++ *
++ */
++static ssize_t pfe_eth_show_tx_stats(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ ssize_t len = 0;
++ int i;
++
++ len += sprintf(buf + len, "TX queues stats:\n");
++
++ for (i = 0; i < emac_txq_cnt; i++) {
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++ i);
++
++ len += sprintf(buf + len, "\n");
++ __netif_tx_lock_bh(tx_queue);
++
++ hif_tx_lock(&pfe->hif);
++ len += sprintf(buf + len,
++ "Queue %2d : credits = %10d\n"
++ , i, hif_lib_tx_credit_avail(pfe, priv->id, i));
++ len += sprintf(buf + len,
++ " tx packets = %10d\n"
++ , pfe->tmu_credit.tx_packets[priv->id][i]);
++ hif_tx_unlock(&pfe->hif);
++
++ /* Don't output additionnal stats if queue never used */
++ if (!pfe->tmu_credit.tx_packets[priv->id][i])
++ goto skip;
++
++ len += sprintf(buf + len,
++ " clean_fail = %10d\n"
++ , priv->clean_fail[i]);
++ len += sprintf(buf + len,
++ " stop_queue = %10d\n"
++ , priv->stop_queue_total[i]);
++ len += sprintf(buf + len,
++ " stop_queue_hif = %10d\n"
++ , priv->stop_queue_hif[i]);
++ len += sprintf(buf + len,
++ " stop_queue_hif_client = %10d\n"
++ , priv->stop_queue_hif_client[i]);
++ len += sprintf(buf + len,
++ " stop_queue_credit = %10d\n"
++ , priv->stop_queue_credit[i]);
++skip:
++ __netif_tx_unlock_bh(tx_queue);
++ }
++ return len;
++}
++
++/* pfe_eth_set_tx_stats
++ *
++ */
++static ssize_t pfe_eth_set_tx_stats(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ int i;
++
++ for (i = 0; i < emac_txq_cnt; i++) {
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++ i);
++
++ __netif_tx_lock_bh(tx_queue);
++ priv->clean_fail[i] = 0;
++ priv->stop_queue_total[i] = 0;
++ priv->stop_queue_hif[i] = 0;
++ priv->stop_queue_hif_client[i] = 0;
++ priv->stop_queue_credit[i] = 0;
++ __netif_tx_unlock_bh(tx_queue);
++ }
++
++ return count;
++}
++#endif
++/* pfe_eth_show_txavail
++ *
++ */
++static ssize_t pfe_eth_show_txavail(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ ssize_t len = 0;
++ int i;
++
++ for (i = 0; i < emac_txq_cnt; i++) {
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++ i);
++
++ __netif_tx_lock_bh(tx_queue);
++
++ len += sprintf(buf + len, "%d",
++ hif_lib_tx_avail(&priv->client, i));
++
++ __netif_tx_unlock_bh(tx_queue);
++
++ if (i == (emac_txq_cnt - 1))
++ len += sprintf(buf + len, "\n");
++ else
++ len += sprintf(buf + len, " ");
++ }
++
++ return len;
++}
++
++/* pfe_eth_show_default_priority
++ *
++ */
++static ssize_t pfe_eth_show_default_priority(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ unsigned long flags;
++ int rc;
++
++ spin_lock_irqsave(&priv->lock, flags);
++ rc = sprintf(buf, "%d\n", priv->default_priority);
++ spin_unlock_irqrestore(&priv->lock, flags);
++
++ return rc;
++}
++
++/* pfe_eth_set_default_priority
++ *
++ */
++
++static ssize_t pfe_eth_set_default_priority(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(to_net_dev(dev));
++ unsigned long flags;
++
++ spin_lock_irqsave(&priv->lock, flags);
++ priv->default_priority = kstrtoul(buf, 0, 0);
++ spin_unlock_irqrestore(&priv->lock, flags);
++
++ return count;
++}
++
++static DEVICE_ATTR(txavail, 0444, pfe_eth_show_txavail, NULL);
++static DEVICE_ATTR(default_priority, 0644, pfe_eth_show_default_priority,
++ pfe_eth_set_default_priority);
++
++#ifdef PFE_ETH_NAPI_STATS
++static DEVICE_ATTR(napi_stats, 0644, pfe_eth_show_napi_stats,
++ pfe_eth_set_napi_stats);
++#endif
++
++#ifdef PFE_ETH_TX_STATS
++static DEVICE_ATTR(tx_stats, 0644, pfe_eth_show_tx_stats,
++ pfe_eth_set_tx_stats);
++#endif
++
++/*
++ * pfe_eth_sysfs_init
++ *
++ */
++static int pfe_eth_sysfs_init(struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ int err;
++
++ /* Initialize the default values */
++
++ /*
++ * By default, packets without conntrack will use this default low
++ * priority queue
++ */
++ priv->default_priority = 0;
++
++ /* Create our sysfs files */
++ err = device_create_file(&ndev->dev, &dev_attr_default_priority);
++ if (err) {
++ netdev_err(ndev,
++ "failed to create default_priority sysfs files\n");
++ goto err_priority;
++ }
++
++ err = device_create_file(&ndev->dev, &dev_attr_txavail);
++ if (err) {
++ netdev_err(ndev,
++ "failed to create default_priority sysfs files\n");
++ goto err_txavail;
++ }
++
++#ifdef PFE_ETH_NAPI_STATS
++ err = device_create_file(&ndev->dev, &dev_attr_napi_stats);
++ if (err) {
++ netdev_err(ndev, "failed to create napi stats sysfs files\n");
++ goto err_napi;
++ }
++#endif
++
++#ifdef PFE_ETH_TX_STATS
++ err = device_create_file(&ndev->dev, &dev_attr_tx_stats);
++ if (err) {
++ netdev_err(ndev, "failed to create tx stats sysfs files\n");
++ goto err_tx;
++ }
++#endif
++
++ return 0;
++
++#ifdef PFE_ETH_TX_STATS
++err_tx:
++#endif
++#ifdef PFE_ETH_NAPI_STATS
++ device_remove_file(&ndev->dev, &dev_attr_napi_stats);
++
++err_napi:
++#endif
++ device_remove_file(&ndev->dev, &dev_attr_txavail);
++
++err_txavail:
++ device_remove_file(&ndev->dev, &dev_attr_default_priority);
++
++err_priority:
++ return -1;
++}
++
++/* pfe_eth_sysfs_exit
++ *
++ */
++void pfe_eth_sysfs_exit(struct net_device *ndev)
++{
++#ifdef PFE_ETH_TX_STATS
++ device_remove_file(&ndev->dev, &dev_attr_tx_stats);
++#endif
++
++#ifdef PFE_ETH_NAPI_STATS
++ device_remove_file(&ndev->dev, &dev_attr_napi_stats);
++#endif
++ device_remove_file(&ndev->dev, &dev_attr_txavail);
++ device_remove_file(&ndev->dev, &dev_attr_default_priority);
++}
++
++/*************************************************************************/
++/* ETHTOOL INTERCAE */
++/*************************************************************************/
++
++/*MTIP GEMAC */
++static const struct fec_stat {
++ char name[ETH_GSTRING_LEN];
++ u16 offset;
++} fec_stats[] = {
++ /* RMON TX */
++ { "tx_dropped", RMON_T_DROP },
++ { "tx_packets", RMON_T_PACKETS },
++ { "tx_broadcast", RMON_T_BC_PKT },
++ { "tx_multicast", RMON_T_MC_PKT },
++ { "tx_crc_errors", RMON_T_CRC_ALIGN },
++ { "tx_undersize", RMON_T_UNDERSIZE },
++ { "tx_oversize", RMON_T_OVERSIZE },
++ { "tx_fragment", RMON_T_FRAG },
++ { "tx_jabber", RMON_T_JAB },
++ { "tx_collision", RMON_T_COL },
++ { "tx_64byte", RMON_T_P64 },
++ { "tx_65to127byte", RMON_T_P65TO127 },
++ { "tx_128to255byte", RMON_T_P128TO255 },
++ { "tx_256to511byte", RMON_T_P256TO511 },
++ { "tx_512to1023byte", RMON_T_P512TO1023 },
++ { "tx_1024to2047byte", RMON_T_P1024TO2047 },
++ { "tx_GTE2048byte", RMON_T_P_GTE2048 },
++ { "tx_octets", RMON_T_OCTETS },
++
++ /* IEEE TX */
++ { "IEEE_tx_drop", IEEE_T_DROP },
++ { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
++ { "IEEE_tx_1col", IEEE_T_1COL },
++ { "IEEE_tx_mcol", IEEE_T_MCOL },
++ { "IEEE_tx_def", IEEE_T_DEF },
++ { "IEEE_tx_lcol", IEEE_T_LCOL },
++ { "IEEE_tx_excol", IEEE_T_EXCOL },
++ { "IEEE_tx_macerr", IEEE_T_MACERR },
++ { "IEEE_tx_cserr", IEEE_T_CSERR },
++ { "IEEE_tx_sqe", IEEE_T_SQE },
++ { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
++ { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
++
++ /* RMON RX */
++ { "rx_packets", RMON_R_PACKETS },
++ { "rx_broadcast", RMON_R_BC_PKT },
++ { "rx_multicast", RMON_R_MC_PKT },
++ { "rx_crc_errors", RMON_R_CRC_ALIGN },
++ { "rx_undersize", RMON_R_UNDERSIZE },
++ { "rx_oversize", RMON_R_OVERSIZE },
++ { "rx_fragment", RMON_R_FRAG },
++ { "rx_jabber", RMON_R_JAB },
++ { "rx_64byte", RMON_R_P64 },
++ { "rx_65to127byte", RMON_R_P65TO127 },
++ { "rx_128to255byte", RMON_R_P128TO255 },
++ { "rx_256to511byte", RMON_R_P256TO511 },
++ { "rx_512to1023byte", RMON_R_P512TO1023 },
++ { "rx_1024to2047byte", RMON_R_P1024TO2047 },
++ { "rx_GTE2048byte", RMON_R_P_GTE2048 },
++ { "rx_octets", RMON_R_OCTETS },
++
++ /* IEEE RX */
++ { "IEEE_rx_drop", IEEE_R_DROP },
++ { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
++ { "IEEE_rx_crc", IEEE_R_CRC },
++ { "IEEE_rx_align", IEEE_R_ALIGN },
++ { "IEEE_rx_macerr", IEEE_R_MACERR },
++ { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
++ { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
++};
++
++static void pfe_eth_fill_stats(struct net_device *ndev, struct ethtool_stats
++ *stats, u64 *data)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ int i;
++ u64 pfe_crc_validated = 0;
++ int id;
++
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++ pfe_crc_validated += be32_to_cpu(pe_dmem_read(id,
++ CLASS_DM_CRC_VALIDATED + (priv->id * 4), 4));
++ }
++
++ for (i = 0; i < ARRAY_SIZE(fec_stats); i++) {
++ data[i] = readl(priv->EMAC_baseaddr + fec_stats[i].offset);
++
++ if (fec_stats[i].offset == IEEE_R_DROP)
++ data[i] -= pfe_crc_validated;
++ }
++}
++
++static void pfe_eth_gstrings(struct net_device *netdev,
++ u32 stringset, u8 *data)
++{
++ int i;
++
++ switch (stringset) {
++ case ETH_SS_STATS:
++ for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
++ memcpy(data + i * ETH_GSTRING_LEN,
++ fec_stats[i].name, ETH_GSTRING_LEN);
++ break;
++ }
++}
++
++static int pfe_eth_stats_count(struct net_device *ndev, int sset)
++{
++ switch (sset) {
++ case ETH_SS_STATS:
++ return ARRAY_SIZE(fec_stats);
++ default:
++ return -EOPNOTSUPP;
++ }
++}
++
++/*
++ * pfe_eth_gemac_reglen - Return the length of the register structure.
++ *
++ */
++static int pfe_eth_gemac_reglen(struct net_device *ndev)
++{
++ pr_info("%s()\n", __func__);
++ return (sizeof(gemac_regs) / sizeof(u32));
++}
++
++/*
++ * pfe_eth_gemac_get_regs - Return the gemac register structure.
++ *
++ */
++static void pfe_eth_gemac_get_regs(struct net_device *ndev, struct ethtool_regs
++ *regs, void *regbuf)
++{
++ int i;
++
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ u32 *buf = (u32 *)regbuf;
++
++ pr_info("%s()\n", __func__);
++ for (i = 0; i < sizeof(gemac_regs) / sizeof(u32); i++)
++ buf[i] = readl(priv->EMAC_baseaddr + gemac_regs[i]);
++}
++
++/*
++ * pfe_eth_set_wol - Set the magic packet option, in WoL register.
++ *
++ */
++static int pfe_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ if (wol->wolopts & ~WAKE_MAGIC)
++ return -EOPNOTSUPP;
++
++ /* for MTIP we store wol->wolopts */
++ priv->wol = wol->wolopts;
++
++ device_set_wakeup_enable(&ndev->dev, wol->wolopts & WAKE_MAGIC);
++
++ return 0;
++}
++
++/*
++ *
++ * pfe_eth_get_wol - Get the WoL options.
++ *
++ */
++static void pfe_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo
++ *wol)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ wol->supported = WAKE_MAGIC;
++ wol->wolopts = 0;
++
++ if (priv->wol & WAKE_MAGIC)
++ wol->wolopts = WAKE_MAGIC;
++
++ memset(&wol->sopass, 0, sizeof(wol->sopass));
++}
++
++/*
++ * pfe_eth_get_drvinfo - Fills in the drvinfo structure with some basic info
++ *
++ */
++static void pfe_eth_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo
++ *drvinfo)
++{
++ strlcpy(drvinfo->driver, DRV_NAME, sizeof(drvinfo->driver));
++ strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
++ strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
++ strlcpy(drvinfo->bus_info, "N/A", sizeof(drvinfo->bus_info));
++}
++
++/*
++ * pfe_eth_set_settings - Used to send commands to PHY.
++ *
++ */
++static int pfe_eth_set_settings(struct net_device *ndev,
++ const struct ethtool_link_ksettings *cmd)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ struct phy_device *phydev = priv->phydev;
++
++ if (!phydev)
++ return -ENODEV;
++
++ return phy_ethtool_ksettings_set(phydev, cmd);
++}
++
++/*
++ * pfe_eth_getsettings - Return the current settings in the ethtool_cmd
++ * structure.
++ *
++ */
++static int pfe_eth_get_settings(struct net_device *ndev,
++ struct ethtool_link_ksettings *cmd)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ struct phy_device *phydev = priv->phydev;
++
++ if (!phydev)
++ return -ENODEV;
++
++ phy_ethtool_ksettings_get(phydev, cmd);
++
++ return 0;
++}
++
++/*
++ * pfe_eth_get_msglevel - Gets the debug message mask.
++ *
++ */
++static uint32_t pfe_eth_get_msglevel(struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ return priv->msg_enable;
++}
++
++/*
++ * pfe_eth_set_msglevel - Sets the debug message mask.
++ *
++ */
++static void pfe_eth_set_msglevel(struct net_device *ndev, uint32_t data)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ priv->msg_enable = data;
++}
++
++#define HIF_RX_COAL_MAX_CLKS (~(1 << 31))
++#define HIF_RX_COAL_CLKS_PER_USEC (pfe->ctrl.sys_clk / 1000)
++#define HIF_RX_COAL_MAX_USECS (HIF_RX_COAL_MAX_CLKS / \
++ HIF_RX_COAL_CLKS_PER_USEC)
++
++/*
++ * pfe_eth_set_coalesce - Sets rx interrupt coalescing timer.
++ *
++ */
++static int pfe_eth_set_coalesce(struct net_device *ndev,
++ struct ethtool_coalesce *ec,
++ struct kernel_ethtool_coalesce *kernel_coal,
++ struct netlink_ext_ack *extack)
++{
++ if (ec->rx_coalesce_usecs > HIF_RX_COAL_MAX_USECS)
++ return -EINVAL;
++
++ if (!ec->rx_coalesce_usecs) {
++ writel(0, HIF_INT_COAL);
++ return 0;
++ }
++
++ writel((ec->rx_coalesce_usecs * HIF_RX_COAL_CLKS_PER_USEC) |
++ HIF_INT_COAL_ENABLE, HIF_INT_COAL);
++
++ return 0;
++}
++
++/*
++ * pfe_eth_get_coalesce - Gets rx interrupt coalescing timer value.
++ *
++ */
++static int pfe_eth_get_coalesce(struct net_device *ndev,
++ struct ethtool_coalesce *ec,
++ struct kernel_ethtool_coalesce *kernel_coal,
++ struct netlink_ext_ack *extack)
++{
++ int reg_val = readl(HIF_INT_COAL);
++
++ if (reg_val & HIF_INT_COAL_ENABLE)
++ ec->rx_coalesce_usecs = (reg_val & HIF_RX_COAL_MAX_CLKS) /
++ HIF_RX_COAL_CLKS_PER_USEC;
++ else
++ ec->rx_coalesce_usecs = 0;
++
++ return 0;
++}
++
++/*
++ * pfe_eth_set_pauseparam - Sets pause parameters
++ *
++ */
++static int pfe_eth_set_pauseparam(struct net_device *ndev,
++ struct ethtool_pauseparam *epause)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ if (epause->tx_pause != epause->rx_pause) {
++ netdev_info(ndev,
++ "hardware only support enable/disable both tx and rx\n");
++ return -EINVAL;
++ }
++
++ priv->pause_flag = 0;
++ priv->pause_flag |= epause->rx_pause ? PFE_PAUSE_FLAG_ENABLE : 0;
++ priv->pause_flag |= epause->autoneg ? PFE_PAUSE_FLAG_AUTONEG : 0;
++
++ if (epause->rx_pause || epause->autoneg) {
++ gemac_enable_pause_rx(priv->EMAC_baseaddr);
++ writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) |
++ EGPI_PAUSE_ENABLE),
++ priv->GPI_baseaddr + GPI_TX_PAUSE_TIME);
++ if (priv->phydev) {
++ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
++ priv->phydev->supported);
++ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
++ priv->phydev->supported);
++ linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT,
++ priv->phydev->advertising);
++ linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
++ priv->phydev->advertising);
++ }
++ } else {
++ gemac_disable_pause_rx(priv->EMAC_baseaddr);
++ writel((readl(priv->GPI_baseaddr + GPI_TX_PAUSE_TIME) &
++ ~EGPI_PAUSE_ENABLE),
++ priv->GPI_baseaddr + GPI_TX_PAUSE_TIME);
++ if (priv->phydev) {
++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
++ priv->phydev->supported);
++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
++ priv->phydev->supported);
++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Pause_BIT,
++ priv->phydev->advertising);
++ linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
++ priv->phydev->advertising);
++ }
++ }
++
++ return 0;
++}
++
++/*
++ * pfe_eth_get_pauseparam - Gets pause parameters
++ *
++ */
++static void pfe_eth_get_pauseparam(struct net_device *ndev,
++ struct ethtool_pauseparam *epause)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ epause->autoneg = (priv->pause_flag & PFE_PAUSE_FLAG_AUTONEG) != 0;
++ epause->tx_pause = (priv->pause_flag & PFE_PAUSE_FLAG_ENABLE) != 0;
++ epause->rx_pause = epause->tx_pause;
++}
++
++/*
++ * pfe_eth_get_hash
++ */
++#define PFE_HASH_BITS 6 /* #bits in hash */
++#define CRC32_POLY 0xEDB88320
++
++static int pfe_eth_get_hash(u8 *addr)
++{
++ unsigned int i, bit, data, crc, hash;
++
++ /* calculate crc32 value of mac address */
++ crc = 0xffffffff;
++
++ for (i = 0; i < 6; i++) {
++ data = addr[i];
++ for (bit = 0; bit < 8; bit++, data >>= 1) {
++ crc = (crc >> 1) ^
++ (((crc ^ data) & 1) ? CRC32_POLY : 0);
++ }
++ }
++
++ /*
++ * only upper 6 bits (PFE_HASH_BITS) are used
++ * which point to specific bit in the hash registers
++ */
++ hash = (crc >> (32 - PFE_HASH_BITS)) & 0x3f;
++
++ return hash;
++}
++
++const struct ethtool_ops pfe_ethtool_ops = {
++ .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS,
++ .get_drvinfo = pfe_eth_get_drvinfo,
++ .get_regs_len = pfe_eth_gemac_reglen,
++ .get_regs = pfe_eth_gemac_get_regs,
++ .get_link = ethtool_op_get_link,
++ .get_wol = pfe_eth_get_wol,
++ .set_wol = pfe_eth_set_wol,
++ .set_pauseparam = pfe_eth_set_pauseparam,
++ .get_pauseparam = pfe_eth_get_pauseparam,
++ .get_strings = pfe_eth_gstrings,
++ .get_sset_count = pfe_eth_stats_count,
++ .get_ethtool_stats = pfe_eth_fill_stats,
++ .get_msglevel = pfe_eth_get_msglevel,
++ .set_msglevel = pfe_eth_set_msglevel,
++ .set_coalesce = pfe_eth_set_coalesce,
++ .get_coalesce = pfe_eth_get_coalesce,
++ .get_link_ksettings = pfe_eth_get_settings,
++ .set_link_ksettings = pfe_eth_set_settings,
++};
++
++/* pfe_eth_mdio_reset
++ */
++int pfe_eth_mdio_reset(struct mii_bus *bus)
++{
++ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;
++ u32 phy_speed;
++
++
++ mutex_lock(&bus->mdio_lock);
++
++ /*
++ * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
++ *
++ * The formula for FEC MDC is 'ref_freq / (MII_SPEED x 2)' while
++ * for ENET-MAC is 'ref_freq / ((MII_SPEED + 1) x 2)'.
++ */
++ phy_speed = (DIV_ROUND_UP((pfe->ctrl.sys_clk * 1000), 4000000)
++ << EMAC_MII_SPEED_SHIFT);
++ phy_speed |= EMAC_HOLDTIME(0x5);
++ __raw_writel(phy_speed, priv->mdio_base + EMAC_MII_CTRL_REG);
++
++ mutex_unlock(&bus->mdio_lock);
++
++ return 0;
++}
++
++/* pfe_eth_mdio_timeout
++ *
++ */
++static int pfe_eth_mdio_timeout(struct pfe_mdio_priv_s *priv, int timeout)
++{
++ while (!(__raw_readl(priv->mdio_base + EMAC_IEVENT_REG) &
++ EMAC_IEVENT_MII)) {
++ if (timeout-- <= 0)
++ return -1;
++ usleep_range(10, 20);
++ }
++ __raw_writel(EMAC_IEVENT_MII, priv->mdio_base + EMAC_IEVENT_REG);
++ return 0;
++}
++
++static int pfe_eth_mdio_mux(u8 muxval)
++{
++ struct i2c_adapter *a;
++ struct i2c_msg msg;
++ unsigned char buf[2];
++ int ret;
++
++ a = i2c_get_adapter(0);
++ if (!a)
++ return -ENODEV;
++
++ /* set bit 1 (the second bit) of chip at 0x09, register 0x13 */
++ buf[0] = 0x54; /* reg number */
++ buf[1] = (muxval << 6) | 0x3; /* data */
++ msg.addr = 0x66;
++ msg.buf = buf;
++ msg.len = 2;
++ msg.flags = 0;
++ ret = i2c_transfer(a, &msg, 1);
++ i2c_put_adapter(a);
++ if (ret != 1)
++ return -ENODEV;
++ return 0;
++}
++
++static int pfe_eth_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
++ u16 value)
++{
++ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;
++
++ /*To access external PHYs on QDS board mux needs to be configured*/
++ if ((mii_id) && (pfe->mdio_muxval[mii_id]))
++ pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]);
++
++ /* start a write op */
++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR |
++ EMAC_MII_DATA_PA(mii_id) |
++ EMAC_MII_DATA_RA(regnum) |
++ EMAC_MII_DATA_TA | EMAC_MII_DATA(value),
++ priv->mdio_base + EMAC_MII_DATA_REG);
++
++ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) {
++ dev_err(&bus->dev, "%s: phy MDIO write timeout\n", __func__);
++ return -1;
++ }
++ return 0;
++}
++
++static int pfe_eth_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
++{
++ struct pfe_mdio_priv_s *priv = (struct pfe_mdio_priv_s *)bus->priv;
++ u16 value = 0;
++
++ /*To access external PHYs on QDS board mux needs to be configured*/
++ if ((mii_id) && (pfe->mdio_muxval[mii_id]))
++ pfe_eth_mdio_mux(pfe->mdio_muxval[mii_id]);
++
++ /* start a read op */
++ __raw_writel(EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD |
++ EMAC_MII_DATA_PA(mii_id) |
++ EMAC_MII_DATA_RA(regnum) |
++ EMAC_MII_DATA_TA, priv->mdio_base +
++ EMAC_MII_DATA_REG);
++
++ if (pfe_eth_mdio_timeout(priv, EMAC_MDIO_TIMEOUT)) {
++ dev_err(&bus->dev, "%s: phy MDIO read timeout\n", __func__);
++ return -1;
++ }
++
++ value = EMAC_MII_DATA(__raw_readl(priv->mdio_base +
++ EMAC_MII_DATA_REG));
++ return value;
++}
++
++static int pfe_eth_mdio_init(struct pfe *pfe,
++ struct ls1012a_pfe_platform_data *pfe_info,
++ int ii)
++{
++ struct pfe_mdio_priv_s *priv = NULL;
++ struct ls1012a_mdio_platform_data *mdio_info;
++ struct mii_bus *bus;
++ struct device_node *mdio_node;
++ int rc = 0;
++
++ mdio_info = (struct ls1012a_mdio_platform_data *)
++ pfe_info->ls1012a_mdio_pdata;
++ mdio_info->id = ii;
++
++ bus = mdiobus_alloc_size(sizeof(struct pfe_mdio_priv_s));
++ if (!bus) {
++ pr_err("mdiobus_alloc() failed\n");
++ rc = -ENOMEM;
++ goto err_mdioalloc;
++ }
++
++ bus->name = "ls1012a MDIO Bus";
++ snprintf(bus->id, MII_BUS_ID_SIZE, "ls1012a-%x", mdio_info->id);
++
++ bus->read = &pfe_eth_mdio_read;
++ bus->write = &pfe_eth_mdio_write;
++ bus->reset = &pfe_eth_mdio_reset;
++ bus->parent = pfe->dev;
++ bus->phy_mask = mdio_info->phy_mask;
++ bus->irq[0] = mdio_info->irq[0];
++ priv = bus->priv;
++ priv->mdio_base = cbus_emac_base[ii];
++
++ priv->mdc_div = mdio_info->mdc_div;
++ if (!priv->mdc_div)
++ priv->mdc_div = 64;
++
++ dev_info(bus->parent, "%s: mdc_div: %d, phy_mask: %x\n",
++ __func__, priv->mdc_div, bus->phy_mask);
++ mdio_node = of_get_child_by_name(pfe->dev->of_node, "mdio");
++ if ((mdio_info->id == 0) && mdio_node) {
++ rc = of_mdiobus_register(bus, mdio_node);
++ of_node_put(mdio_node);
++ } else {
++ rc = mdiobus_register(bus);
++ }
++
++ if (rc) {
++ dev_err(bus->parent, "mdiobus_register(%s) failed\n",
++ bus->name);
++ goto err_mdioregister;
++ }
++
++ priv->mii_bus = bus;
++ pfe->mdio.mdio_priv[ii] = priv;
++
++ pfe_eth_mdio_reset(bus);
++
++ return 0;
++
++err_mdioregister:
++ mdiobus_free(bus);
++err_mdioalloc:
++ return rc;
++}
++
++/* pfe_eth_mdio_exit
++ */
++static void pfe_eth_mdio_exit(struct pfe *pfe,
++ int ii)
++{
++ struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[ii];
++ struct mii_bus *bus = mdio_priv->mii_bus;
++
++ if (!bus)
++ return;
++ mdiobus_unregister(bus);
++ mdiobus_free(bus);
++}
++
++/* pfe_get_phydev_speed
++ */
++static int pfe_get_phydev_speed(struct phy_device *phydev)
++{
++ switch (phydev->speed) {
++ case 10:
++ return SPEED_10M;
++ case 100:
++ return SPEED_100M;
++ case 1000:
++ default:
++ return SPEED_1000M;
++ }
++}
++
++/* pfe_set_rgmii_speed
++ */
++#define RGMIIPCR 0x434
++/* RGMIIPCR bit definitions*/
++#define SCFG_RGMIIPCR_EN_AUTO (0x00000008)
++#define SCFG_RGMIIPCR_SETSP_1000M (0x00000004)
++#define SCFG_RGMIIPCR_SETSP_100M (0x00000000)
++#define SCFG_RGMIIPCR_SETSP_10M (0x00000002)
++#define SCFG_RGMIIPCR_SETFD (0x00000001)
++
++#define MDIOSELCR 0x484
++#define MDIOSEL_SERDES 0x0
++#define MDIOSEL_EXTPHY 0x80000000
++
++static void pfe_set_rgmii_speed(struct phy_device *phydev)
++{
++ u32 rgmii_pcr;
++
++ regmap_read(pfe->scfg, RGMIIPCR, &rgmii_pcr);
++ rgmii_pcr &= ~(SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETSP_10M);
++
++ switch (phydev->speed) {
++ case 10:
++ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
++ break;
++ case 1000:
++ rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
++ break;
++ case 100:
++ default:
++ /* Default is 100M */
++ break;
++ }
++ regmap_write(pfe->scfg, RGMIIPCR, rgmii_pcr);
++}
++
++/* pfe_get_phydev_duplex
++ */
++static int pfe_get_phydev_duplex(struct phy_device *phydev)
++{
++ /*return (phydev->duplex == DUPLEX_HALF) ? DUP_HALF:DUP_FULL ; */
++ return DUPLEX_FULL;
++}
++
++/* pfe_eth_adjust_link
++ */
++static void pfe_eth_adjust_link(struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ unsigned long flags;
++ struct phy_device *phydev = priv->phydev;
++ int new_state = 0;
++
++ netif_info(priv, drv, ndev, "%s\n", __func__);
++
++ spin_lock_irqsave(&priv->lock, flags);
++
++ if (phydev->link) {
++ /*
++ * Now we make sure that we can be in full duplex mode.
++ * If not, we operate in half-duplex mode.
++ */
++ if (phydev->duplex != priv->oldduplex) {
++ new_state = 1;
++ gemac_set_duplex(priv->EMAC_baseaddr,
++ pfe_get_phydev_duplex(phydev));
++ priv->oldduplex = phydev->duplex;
++ }
++
++ if (phydev->speed != priv->oldspeed) {
++ new_state = 1;
++ gemac_set_speed(priv->EMAC_baseaddr,
++ pfe_get_phydev_speed(phydev));
++ if (priv->einfo->mii_config ==
++ PHY_INTERFACE_MODE_RGMII_ID)
++ pfe_set_rgmii_speed(phydev);
++ priv->oldspeed = phydev->speed;
++ }
++
++ if (!priv->oldlink) {
++ new_state = 1;
++ priv->oldlink = 1;
++ }
++
++ } else if (priv->oldlink) {
++ new_state = 1;
++ priv->oldlink = 0;
++ priv->oldspeed = 0;
++ priv->oldduplex = -1;
++ }
++
++ if (new_state && netif_msg_link(priv))
++ phy_print_status(phydev);
++
++ spin_unlock_irqrestore(&priv->lock, flags);
++
++ /* Now, dump the details to the cdev.
++ * XXX: Locking would be required? (uniprocess arch)
++ * Or, maybe move it in spinlock above
++ */
++ if (us && priv->einfo->gem_id < PFE_CDEV_ETH_COUNT) {
++ pr_debug("Changing link state from (%u) to (%u) for ID=(%u)\n",
++ link_states[priv->einfo->gem_id].state,
++ phydev->link,
++ priv->einfo->gem_id);
++ link_states[priv->einfo->gem_id].phy_id = priv->einfo->gem_id;
++ link_states[priv->einfo->gem_id].state = phydev->link;
++ }
++}
++
++/* pfe_phy_exit
++ */
++static void pfe_phy_exit(struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ netif_info(priv, drv, ndev, "%s\n", __func__);
++
++ phy_disconnect(priv->phydev);
++ priv->phydev = NULL;
++}
++
++/* pfe_eth_stop
++ */
++static void pfe_eth_stop(struct net_device *ndev, int wake)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ netif_info(priv, drv, ndev, "%s\n", __func__);
++
++ if (wake) {
++ gemac_tx_disable(priv->EMAC_baseaddr);
++ } else {
++ gemac_disable(priv->EMAC_baseaddr);
++ gpi_disable(priv->GPI_baseaddr);
++
++ if (priv->phydev)
++ phy_stop(priv->phydev);
++ }
++}
++
++/* pfe_eth_start
++ */
++static int pfe_eth_start(struct pfe_eth_priv_s *priv)
++{
++ netif_info(priv, drv, priv->ndev, "%s\n", __func__);
++
++ if (priv->phydev)
++ phy_start(priv->phydev);
++
++ gpi_enable(priv->GPI_baseaddr);
++ gemac_enable(priv->EMAC_baseaddr);
++
++ return 0;
++}
++
++/*
++ * Configure on chip serdes through mdio
++ */
++static void ls1012a_configure_serdes(struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *eth_priv = netdev_priv(ndev);
++ struct pfe_mdio_priv_s *mdio_priv = pfe->mdio.mdio_priv[eth_priv->id];
++ int sgmii_2500 = 0;
++ struct mii_bus *bus = mdio_priv->mii_bus;
++ u16 value = 0;
++
++ if (eth_priv->einfo->mii_config == PHY_INTERFACE_MODE_2500SGMII)
++ sgmii_2500 = 1;
++
++ netif_info(eth_priv, drv, ndev, "%s\n", __func__);
++ /* PCS configuration done with corresponding GEMAC */
++
++ pfe_eth_mdio_read(bus, 0, MDIO_SGMII_CR);
++ pfe_eth_mdio_read(bus, 0, MDIO_SGMII_SR);
++
++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, SGMII_CR_RST);
++
++ if (sgmii_2500) {
++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE, SGMII_SPEED_1GBPS
++ | SGMII_EN);
++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
++ SGMII_DEV_ABIL_ACK | SGMII_DEV_ABIL_SGMII);
++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0xa120);
++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x7);
++ /* Autonegotiation need to be disabled for 2.5G SGMII mode*/
++ value = SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
++ } else {
++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_IF_MODE,
++ SGMII_SPEED_1GBPS
++ | SGMII_USE_SGMII_AN
++ | SGMII_EN);
++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_DEV_ABIL_SGMII,
++ SGMII_DEV_ABIL_EEE_CLK_STP_EN
++ | 0xa0
++ | SGMII_DEV_ABIL_SGMII);
++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_L, 0x400);
++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_LINK_TMR_H, 0x0);
++ value = SGMII_CR_AN_EN | SGMII_CR_FD | SGMII_CR_SPEED_SEL1_1G;
++ pfe_eth_mdio_write(bus, 0, MDIO_SGMII_CR, value);
++ }
++}
++
++/*
++ * pfe_phy_init
++ *
++ */
++static int pfe_phy_init(struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ struct phy_device *phydev;
++ char phy_id[MII_BUS_ID_SIZE + 3];
++ char bus_id[MII_BUS_ID_SIZE];
++ phy_interface_t interface;
++
++ priv->oldlink = 0;
++ priv->oldspeed = 0;
++ priv->oldduplex = -1;
++
++ snprintf(bus_id, MII_BUS_ID_SIZE, "ls1012a-%d", 0);
++ snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
++ priv->einfo->phy_id);
++ netif_info(priv, drv, ndev, "%s: %s\n", __func__, phy_id);
++ interface = priv->einfo->mii_config;
++ if ((interface == PHY_INTERFACE_MODE_SGMII) ||
++ (interface == PHY_INTERFACE_MODE_2500SGMII)) {
++ /*Configure SGMII PCS */
++ if (pfe->scfg) {
++ /* Config MDIO from serdes */
++ regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_SERDES);
++ }
++ ls1012a_configure_serdes(ndev);
++ }
++
++ if (pfe->scfg) {
++ /*Config MDIO from PAD */
++ regmap_write(pfe->scfg, MDIOSELCR, MDIOSEL_EXTPHY);
++ }
++
++ priv->oldlink = 0;
++ priv->oldspeed = 0;
++ priv->oldduplex = -1;
++ pr_info("%s interface %x\n", __func__, interface);
++
++ if (priv->phy_node) {
++ phydev = of_phy_connect(ndev, priv->phy_node,
++ pfe_eth_adjust_link, 0,
++ priv->einfo->mii_config);
++ if (!(phydev)) {
++ netdev_err(ndev, "Unable to connect to phy\n");
++ return -ENODEV;
++ }
++
++ } else {
++ phydev = phy_connect(ndev, phy_id,
++ &pfe_eth_adjust_link, interface);
++ if (IS_ERR(phydev)) {
++ netdev_err(ndev, "Unable to connect to phy\n");
++ return PTR_ERR(phydev);
++ }
++ }
++
++ priv->phydev = phydev;
++ phydev->irq = PHY_POLL;
++
++ return 0;
++}
++
++/* pfe_gemac_init
++ */
++static int pfe_gemac_init(struct pfe_eth_priv_s *priv)
++{
++ struct gemac_cfg cfg;
++
++ netif_info(priv, ifup, priv->ndev, "%s\n", __func__);
++
++ cfg.mode = 0;
++ cfg.speed = SPEED_1000M;
++ cfg.duplex = DUPLEX_FULL;
++
++ gemac_set_config(priv->EMAC_baseaddr, &cfg);
++ gemac_allow_broadcast(priv->EMAC_baseaddr);
++ gemac_enable_1536_rx(priv->EMAC_baseaddr);
++ gemac_enable_stacked_vlan(priv->EMAC_baseaddr);
++ gemac_enable_pause_rx(priv->EMAC_baseaddr);
++ gemac_set_bus_width(priv->EMAC_baseaddr, 64);
++
++ /*GEM will perform checksum verifications*/
++ if (priv->ndev->features & NETIF_F_RXCSUM)
++ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr);
++ else
++ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr);
++
++ return 0;
++}
++
++/* pfe_eth_event_handler
++ */
++static int pfe_eth_event_handler(void *data, int event, int qno)
++{
++ struct pfe_eth_priv_s *priv = data;
++
++ switch (event) {
++ case EVENT_RX_PKT_IND:
++
++ if (qno == 0) {
++ if (napi_schedule_prep(&priv->high_napi)) {
++ netif_info(priv, intr, priv->ndev,
++ "%s: schedule high prio poll\n"
++ , __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++
++ __napi_schedule(&priv->high_napi);
++ }
++ } else if (qno == 1) {
++ if (napi_schedule_prep(&priv->low_napi)) {
++ netif_info(priv, intr, priv->ndev,
++ "%s: schedule low prio poll\n"
++ , __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++ __napi_schedule(&priv->low_napi);
++ }
++ } else if (qno == 2) {
++ if (napi_schedule_prep(&priv->lro_napi)) {
++ netif_info(priv, intr, priv->ndev,
++ "%s: schedule lro prio poll\n"
++ , __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++ __napi_schedule(&priv->lro_napi);
++ }
++ }
++
++ break;
++
++ case EVENT_TXDONE_IND:
++ pfe_eth_flush_tx(priv);
++ hif_lib_event_handler_start(&priv->client, EVENT_TXDONE_IND, 0);
++ break;
++ case EVENT_HIGH_RX_WM:
++ default:
++ break;
++ }
++
++ return 0;
++}
++
++static int pfe_eth_change_mtu(struct net_device *ndev, int new_mtu)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ ndev->mtu = new_mtu;
++ new_mtu += ETH_HLEN + ETH_FCS_LEN;
++ gemac_set_rx_max_fl(priv->EMAC_baseaddr, new_mtu);
++
++ return 0;
++}
++
++/* pfe_eth_open
++ */
++static int pfe_eth_open(struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ struct hif_client_s *client;
++ int rc;
++
++ netif_info(priv, ifup, ndev, "%s\n", __func__);
++
++ /* Register client driver with HIF */
++ client = &priv->client;
++ memset(client, 0, sizeof(*client));
++ client->id = PFE_CL_GEM0 + priv->id;
++ client->tx_qn = emac_txq_cnt;
++ client->rx_qn = EMAC_RXQ_CNT;
++ client->priv = priv;
++ client->pfe = priv->pfe;
++ client->event_handler = pfe_eth_event_handler;
++
++ client->tx_qsize = EMAC_TXQ_DEPTH;
++ client->rx_qsize = EMAC_RXQ_DEPTH;
++
++ rc = hif_lib_client_register(client);
++ if (rc) {
++ netdev_err(ndev, "%s: hif_lib_client_register(%d) failed\n",
++ __func__, client->id);
++ goto err0;
++ }
++
++ netif_info(priv, drv, ndev, "%s: registered client: %p\n", __func__,
++ client);
++
++ pfe_gemac_init(priv);
++
++ if (!is_valid_ether_addr(ndev->dev_addr)) {
++ netdev_err(ndev, "%s: invalid MAC address\n", __func__);
++ rc = -EADDRNOTAVAIL;
++ goto err1;
++ }
++
++ gemac_set_laddrN(priv->EMAC_baseaddr,
++ (struct pfe_mac_addr *)ndev->dev_addr, 1);
++
++ napi_enable(&priv->high_napi);
++ napi_enable(&priv->low_napi);
++ napi_enable(&priv->lro_napi);
++
++ rc = pfe_eth_start(priv);
++
++ netif_tx_wake_all_queues(ndev);
++
++ return rc;
++
++err1:
++ hif_lib_client_unregister(&priv->client);
++
++err0:
++ return rc;
++}
++
++/*
++ * pfe_eth_shutdown
++ */
++int pfe_eth_shutdown(struct net_device *ndev, int wake)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ int i, qstatus, id;
++ unsigned long next_poll = jiffies + 1, end = jiffies +
++ (TX_POLL_TIMEOUT_MS * HZ) / 1000;
++ int tx_pkts, prv_tx_pkts;
++
++ netif_info(priv, ifdown, ndev, "%s\n", __func__);
++
++ for (i = 0; i < emac_txq_cnt; i++)
++ hrtimer_cancel(&priv->fast_tx_timeout[i].timer);
++
++ netif_tx_stop_all_queues(ndev);
++
++ do {
++ tx_pkts = 0;
++ pfe_eth_flush_tx(priv);
++
++ for (i = 0; i < emac_txq_cnt; i++)
++ tx_pkts += hif_lib_tx_pending(&priv->client, i);
++
++ if (tx_pkts) {
++ /*Don't wait forever, break if we cross max timeout */
++ if (time_after(jiffies, end)) {
++ pr_err(
++ "(%s)Tx is not complete after %dmsec\n",
++ ndev->name, TX_POLL_TIMEOUT_MS);
++ break;
++ }
++
++ pr_info("%s : (%s) Waiting for tx packets to free. Pending tx pkts = %d.\n"
++ , __func__, ndev->name, tx_pkts);
++ if (need_resched())
++ schedule();
++ }
++
++ } while (tx_pkts);
++
++ end = jiffies + (TX_POLL_TIMEOUT_MS * HZ) / 1000;
++
++ prv_tx_pkts = tmu_pkts_processed(priv->id);
++ /*
++ * Wait till TMU transmits all pending packets
++ * poll tmu_qstatus and pkts processed by TMU for every 10ms
++ * Consider TMU is busy, If we see TMU qeueu pending or any packets
++ * processed by TMU
++ */
++ while (1) {
++ if (time_after(jiffies, next_poll)) {
++ tx_pkts = tmu_pkts_processed(priv->id);
++ qstatus = tmu_qstatus(priv->id) & 0x7ffff;
++
++ if (!qstatus && (tx_pkts == prv_tx_pkts))
++ break;
++ /* Don't wait forever, break if we cross max
++ * timeout(TX_POLL_TIMEOUT_MS)
++ */
++ if (time_after(jiffies, end)) {
++ pr_err("TMU%d is busy after %dmsec\n",
++ priv->id, TX_POLL_TIMEOUT_MS);
++ break;
++ }
++ prv_tx_pkts = tx_pkts;
++ next_poll++;
++ }
++ if (need_resched())
++ schedule();
++ }
++ /* Wait for some more time to complete transmitting packet if any */
++ next_poll = jiffies + 1;
++ while (1) {
++ if (time_after(jiffies, next_poll))
++ break;
++ if (need_resched())
++ schedule();
++ }
++
++ pfe_eth_stop(ndev, wake);
++
++ napi_disable(&priv->lro_napi);
++ napi_disable(&priv->low_napi);
++ napi_disable(&priv->high_napi);
++
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++ pe_dmem_write(id, 0, CLASS_DM_CRC_VALIDATED
++ + (priv->id * 4), 4);
++ }
++
++ hif_lib_client_unregister(&priv->client);
++
++ return 0;
++}
++
++/* pfe_eth_close
++ *
++ */
++static int pfe_eth_close(struct net_device *ndev)
++{
++ pfe_eth_shutdown(ndev, 0);
++
++ return 0;
++}
++
++/* pfe_eth_suspend
++ *
++ * return value : 1 if netdevice is configured to wakeup system
++ * 0 otherwise
++ */
++int pfe_eth_suspend(struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ int retval = 0;
++
++ if (priv->wol) {
++ gemac_set_wol(priv->EMAC_baseaddr, priv->wol);
++ retval = 1;
++ }
++ pfe_eth_shutdown(ndev, priv->wol);
++
++ return retval;
++}
++
++/* pfe_eth_resume
++ *
++ */
++int pfe_eth_resume(struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ if (priv->wol)
++ gemac_set_wol(priv->EMAC_baseaddr, 0);
++ gemac_tx_enable(priv->EMAC_baseaddr);
++
++ return pfe_eth_open(ndev);
++}
++
++/* pfe_eth_get_queuenum
++ */
++static int pfe_eth_get_queuenum(struct pfe_eth_priv_s *priv, struct sk_buff
++ *skb)
++{
++ int queuenum = 0;
++ unsigned long flags;
++
++ /* Get the Fast Path queue number */
++ /*
++ * Use conntrack mark (if conntrack exists), then packet mark (if any),
++ * then fallback to default
++ */
++#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK)
++ if (skb->_nfct) {
++ enum ip_conntrack_info cinfo;
++ struct nf_conn *ct;
++
++ ct = nf_ct_get(skb, &cinfo);
++
++ if (ct) {
++ u32 connmark;
++
++ connmark = ct->mark;
++
++ if ((connmark & 0x80000000) && priv->id != 0)
++ connmark >>= 16;
++
++ queuenum = connmark & EMAC_QUEUENUM_MASK;
++ }
++ } else {/* continued after #endif ... */
++#endif
++ if (skb->mark) {
++ queuenum = skb->mark & EMAC_QUEUENUM_MASK;
++ } else {
++ spin_lock_irqsave(&priv->lock, flags);
++ queuenum = priv->default_priority & EMAC_QUEUENUM_MASK;
++ spin_unlock_irqrestore(&priv->lock, flags);
++ }
++#if defined(CONFIG_IP_NF_CONNTRACK_MARK) || defined(CONFIG_NF_CONNTRACK_MARK)
++ }
++#endif
++ return queuenum;
++}
++
++/* pfe_eth_might_stop_tx
++ *
++ */
++static int pfe_eth_might_stop_tx(struct pfe_eth_priv_s *priv, int queuenum,
++ struct netdev_queue *tx_queue,
++ unsigned int n_desc,
++ unsigned int n_segs)
++{
++ ktime_t kt;
++ int tried = 0;
++
++try_again:
++ if (unlikely((__hif_tx_avail(&pfe->hif) < n_desc) ||
++ (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) ||
++ (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) < n_segs))) {
++ if (!tried) {
++ __hif_lib_update_credit(&priv->client, queuenum);
++ tried = 1;
++ goto try_again;
++ }
++#ifdef PFE_ETH_TX_STATS
++ if (__hif_tx_avail(&pfe->hif) < n_desc) {
++ priv->stop_queue_hif[queuenum]++;
++ } else if (hif_lib_tx_avail(&priv->client, queuenum) < n_desc) {
++ priv->stop_queue_hif_client[queuenum]++;
++ } else if (hif_lib_tx_credit_avail(pfe, priv->id, queuenum) <
++ n_segs) {
++ priv->stop_queue_credit[queuenum]++;
++ }
++ priv->stop_queue_total[queuenum]++;
++#endif
++ netif_tx_stop_queue(tx_queue);
++
++ kt = ktime_set(0, LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS *
++ NSEC_PER_MSEC);
++ hrtimer_start(&priv->fast_tx_timeout[queuenum].timer, kt,
++ HRTIMER_MODE_REL);
++ return -1;
++ } else {
++ return 0;
++ }
++}
++
++#define SA_MAX_OP 2
++/* pfe_hif_send_packet
++ *
++ * At this level if TX fails we drop the packet
++ */
++static void pfe_hif_send_packet(struct sk_buff *skb, struct pfe_eth_priv_s
++ *priv, int queuenum)
++{
++ struct skb_shared_info *sh = skb_shinfo(skb);
++ unsigned int nr_frags;
++ u32 ctrl = 0;
++
++ netif_info(priv, tx_queued, priv->ndev, "%s\n", __func__);
++
++ if (skb_is_gso(skb)) {
++ priv->stats.tx_dropped++;
++ return;
++ }
++
++ if (skb->ip_summed == CHECKSUM_PARTIAL)
++ ctrl = HIF_CTRL_TX_CHECKSUM;
++
++ nr_frags = sh->nr_frags;
++
++ if (nr_frags) {
++ skb_frag_t *f;
++ int i;
++
++ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data,
++ skb_headlen(skb), ctrl, HIF_FIRST_BUFFER,
++ skb);
++
++ for (i = 0; i < nr_frags - 1; i++) {
++ f = &sh->frags[i];
++ __hif_lib_xmit_pkt(&priv->client, queuenum,
++ skb_frag_address(f),
++ skb_frag_size(f),
++ 0x0, 0x0, skb);
++ }
++
++ f = &sh->frags[i];
++
++ __hif_lib_xmit_pkt(&priv->client, queuenum,
++ skb_frag_address(f), skb_frag_size(f),
++ 0x0, HIF_LAST_BUFFER | HIF_DATA_VALID,
++ skb);
++
++ netif_info(priv, tx_queued, priv->ndev,
++ "%s: pkt sent successfully skb:%p nr_frags:%d len:%d\n",
++ __func__, skb, nr_frags, skb->len);
++ } else {
++ __hif_lib_xmit_pkt(&priv->client, queuenum, skb->data,
++ skb->len, ctrl, HIF_FIRST_BUFFER |
++ HIF_LAST_BUFFER | HIF_DATA_VALID,
++ skb);
++ netif_info(priv, tx_queued, priv->ndev,
++ "%s: pkt sent successfully skb:%p len:%d\n",
++ __func__, skb, skb->len);
++ }
++ hif_tx_dma_start();
++ priv->stats.tx_packets++;
++ priv->stats.tx_bytes += skb->len;
++ hif_lib_tx_credit_use(pfe, priv->id, queuenum, 1);
++}
++
++/* pfe_eth_flush_txQ
++ */
++static void pfe_eth_flush_txQ(struct pfe_eth_priv_s *priv, int tx_q_num, int
++ from_tx, int n_desc)
++{
++ struct sk_buff *skb;
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++ tx_q_num);
++ unsigned int flags;
++
++ netif_info(priv, tx_done, priv->ndev, "%s\n", __func__);
++
++ if (!from_tx)
++ __netif_tx_lock_bh(tx_queue);
++
++ /* Clean HIF and client queue */
++ while ((skb = hif_lib_tx_get_next_complete(&priv->client,
++ tx_q_num, &flags,
++ HIF_TX_DESC_NT))) {
++ if (flags & HIF_DATA_VALID)
++ dev_kfree_skb_any(skb);
++ }
++ if (!from_tx)
++ __netif_tx_unlock_bh(tx_queue);
++}
++
++/* pfe_eth_flush_tx
++ */
++static void pfe_eth_flush_tx(struct pfe_eth_priv_s *priv)
++{
++ int ii;
++
++ netif_info(priv, tx_done, priv->ndev, "%s\n", __func__);
++
++ for (ii = 0; ii < emac_txq_cnt; ii++) {
++ pfe_eth_flush_txQ(priv, ii, 0, 0);
++ __hif_lib_update_credit(&priv->client, ii);
++ }
++}
++
++void pfe_tx_get_req_desc(struct sk_buff *skb, unsigned int *n_desc, unsigned int
++ *n_segs)
++{
++ struct skb_shared_info *sh = skb_shinfo(skb);
++
++ /* Scattered data */
++ if (sh->nr_frags) {
++ *n_desc = sh->nr_frags + 1;
++ *n_segs = 1;
++ /* Regular case */
++ } else {
++ *n_desc = 1;
++ *n_segs = 1;
++ }
++}
++
++/* pfe_eth_send_packet
++ */
++static int pfe_eth_send_packet(struct sk_buff *skb, struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ int tx_q_num = skb_get_queue_mapping(skb);
++ int n_desc, n_segs;
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++ tx_q_num);
++
++ netif_info(priv, tx_queued, ndev, "%s\n", __func__);
++
++ if ((!skb_is_gso(skb)) && (skb_headroom(skb) < (PFE_PKT_HEADER_SZ +
++ sizeof(unsigned long)))) {
++ netif_warn(priv, tx_err, priv->ndev, "%s: copying skb\n",
++ __func__);
++
++ if (pskb_expand_head(skb, (PFE_PKT_HEADER_SZ + sizeof(unsigned
++ long)), 0, GFP_ATOMIC)) {
++ /* No need to re-transmit, no way to recover*/
++ kfree_skb(skb);
++ priv->stats.tx_dropped++;
++ return NETDEV_TX_OK;
++ }
++ }
++
++ pfe_tx_get_req_desc(skb, &n_desc, &n_segs);
++
++ hif_tx_lock(&pfe->hif);
++ if (unlikely(pfe_eth_might_stop_tx(priv, tx_q_num, tx_queue, n_desc,
++ n_segs))) {
++#ifdef PFE_ETH_TX_STATS
++ if (priv->was_stopped[tx_q_num]) {
++ priv->clean_fail[tx_q_num]++;
++ priv->was_stopped[tx_q_num] = 0;
++ }
++#endif
++ hif_tx_unlock(&pfe->hif);
++ return NETDEV_TX_BUSY;
++ }
++
++ pfe_hif_send_packet(skb, priv, tx_q_num);
++
++ hif_tx_unlock(&pfe->hif);
++
++ tx_queue->trans_start = jiffies;
++
++#ifdef PFE_ETH_TX_STATS
++ priv->was_stopped[tx_q_num] = 0;
++#endif
++
++ return NETDEV_TX_OK;
++}
++
++/* pfe_eth_select_queue
++ *
++ */
++static u16 pfe_eth_select_queue(struct net_device *ndev, struct sk_buff *skb,
++ struct net_device *sb_dev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ return pfe_eth_get_queuenum(priv, skb);
++}
++
++/* pfe_eth_get_stats
++ */
++static struct net_device_stats *pfe_eth_get_stats(struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++
++ netif_info(priv, drv, ndev, "%s\n", __func__);
++
++ return &priv->stats;
++}
++
++/* pfe_eth_set_mac_address
++ */
++static int pfe_eth_set_mac_address(struct net_device *ndev, void *addr)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ struct sockaddr *sa = addr;
++
++ netif_info(priv, drv, ndev, "%s\n", __func__);
++
++ if (!is_valid_ether_addr(sa->sa_data))
++ return -EADDRNOTAVAIL;
++
++ dev_addr_set(ndev, sa->sa_data);
++
++ gemac_set_laddrN(priv->EMAC_baseaddr,
++ (struct pfe_mac_addr *)ndev->dev_addr, 1);
++
++ return 0;
++}
++
++/* pfe_eth_enet_addr_byte_mac
++ */
++int pfe_eth_enet_addr_byte_mac(u8 *enet_byte_addr,
++ struct pfe_mac_addr *enet_addr)
++{
++ if (!enet_byte_addr || !enet_addr) {
++ return -1;
++
++ } else {
++ enet_addr->bottom = enet_byte_addr[0] |
++ (enet_byte_addr[1] << 8) |
++ (enet_byte_addr[2] << 16) |
++ (enet_byte_addr[3] << 24);
++ enet_addr->top = enet_byte_addr[4] |
++ (enet_byte_addr[5] << 8);
++ return 0;
++ }
++}
++
++/* pfe_eth_set_multi
++ */
++static void pfe_eth_set_multi(struct net_device *ndev)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ struct pfe_mac_addr hash_addr; /* hash register structure */
++ /* specific mac address register structure */
++ struct pfe_mac_addr spec_addr;
++ int result; /* index into hash register to set.. */
++ int uc_count = 0;
++ struct netdev_hw_addr *ha;
++
++ if (ndev->flags & IFF_PROMISC) {
++ netif_info(priv, drv, ndev, "entering promiscuous mode\n");
++
++ priv->promisc = 1;
++ gemac_enable_copy_all(priv->EMAC_baseaddr);
++ } else {
++ priv->promisc = 0;
++ gemac_disable_copy_all(priv->EMAC_baseaddr);
++ }
++
++ /* Enable broadcast frame reception if required. */
++ if (ndev->flags & IFF_BROADCAST) {
++ gemac_allow_broadcast(priv->EMAC_baseaddr);
++ } else {
++ netif_info(priv, drv, ndev,
++ "disabling broadcast frame reception\n");
++
++ gemac_no_broadcast(priv->EMAC_baseaddr);
++ }
++
++ if (ndev->flags & IFF_ALLMULTI) {
++ /* Set the hash to rx all multicast frames */
++ hash_addr.bottom = 0xFFFFFFFF;
++ hash_addr.top = 0xFFFFFFFF;
++ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr);
++ netdev_for_each_uc_addr(ha, ndev) {
++ if (uc_count >= MAX_UC_SPEC_ADDR_REG)
++ break;
++ pfe_eth_enet_addr_byte_mac(ha->addr, &spec_addr);
++ gemac_set_laddrN(priv->EMAC_baseaddr, &spec_addr,
++ uc_count + 2);
++ uc_count++;
++ }
++ } else if ((netdev_mc_count(ndev) > 0) || (netdev_uc_count(ndev))) {
++ u8 *addr;
++
++ hash_addr.bottom = 0;
++ hash_addr.top = 0;
++
++ netdev_for_each_mc_addr(ha, ndev) {
++ addr = ha->addr;
++
++ netif_info(priv, drv, ndev,
++ "adding multicast address %X:%X:%X:%X:%X:%X to gem filter\n",
++ addr[0], addr[1], addr[2],
++ addr[3], addr[4], addr[5]);
++
++ result = pfe_eth_get_hash(addr);
++
++ if (result < EMAC_HASH_REG_BITS) {
++ if (result < 32)
++ hash_addr.bottom |= (1 << result);
++ else
++ hash_addr.top |= (1 << (result - 32));
++ } else {
++ break;
++ }
++ }
++
++ uc_count = -1;
++ netdev_for_each_uc_addr(ha, ndev) {
++ addr = ha->addr;
++
++ if (++uc_count < MAX_UC_SPEC_ADDR_REG) {
++ netdev_info(ndev,
++ "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem filter\n",
++ addr[0], addr[1], addr[2],
++ addr[3], addr[4], addr[5]);
++ pfe_eth_enet_addr_byte_mac(addr, &spec_addr);
++ gemac_set_laddrN(priv->EMAC_baseaddr,
++ &spec_addr, uc_count + 2);
++ } else {
++ netif_info(priv, drv, ndev,
++ "adding unicast address %02x:%02x:%02x:%02x:%02x:%02x to gem hash\n",
++ addr[0], addr[1], addr[2],
++ addr[3], addr[4], addr[5]);
++
++ result = pfe_eth_get_hash(addr);
++ if (result >= EMAC_HASH_REG_BITS) {
++ break;
++
++ } else {
++ if (result < 32)
++ hash_addr.bottom |= (1 <<
++ result);
++ else
++ hash_addr.top |= (1 <<
++ (result - 32));
++ }
++ }
++ }
++
++ gemac_set_hash(priv->EMAC_baseaddr, &hash_addr);
++ }
++
++ if (!(netdev_uc_count(ndev) >= MAX_UC_SPEC_ADDR_REG)) {
++ /*
++ * Check if there are any specific address HW registers that
++ * need to be flushed
++ */
++ for (uc_count = netdev_uc_count(ndev); uc_count <
++ MAX_UC_SPEC_ADDR_REG; uc_count++)
++ gemac_clear_laddrN(priv->EMAC_baseaddr, uc_count + 2);
++ }
++
++ if (ndev->flags & IFF_LOOPBACK)
++ gemac_set_loop(priv->EMAC_baseaddr, LB_LOCAL);
++}
++
++/* pfe_eth_set_features
++ */
++static int pfe_eth_set_features(struct net_device *ndev, netdev_features_t
++ features)
++{
++ struct pfe_eth_priv_s *priv = netdev_priv(ndev);
++ int rc = 0;
++
++ if (features & NETIF_F_RXCSUM)
++ gemac_enable_rx_checksum_offload(priv->EMAC_baseaddr);
++ else
++ gemac_disable_rx_checksum_offload(priv->EMAC_baseaddr);
++ return rc;
++}
++
++/* pfe_eth_fast_tx_timeout
++ */
++static enum hrtimer_restart pfe_eth_fast_tx_timeout(struct hrtimer *timer)
++{
++ struct pfe_eth_fast_timer *fast_tx_timeout = container_of(timer, struct
++ pfe_eth_fast_timer,
++ timer);
++ struct pfe_eth_priv_s *priv = container_of(fast_tx_timeout->base,
++ struct pfe_eth_priv_s,
++ fast_tx_timeout);
++ struct netdev_queue *tx_queue = netdev_get_tx_queue(priv->ndev,
++ fast_tx_timeout->queuenum);
++
++ if (netif_tx_queue_stopped(tx_queue)) {
++#ifdef PFE_ETH_TX_STATS
++ priv->was_stopped[fast_tx_timeout->queuenum] = 1;
++#endif
++ netif_tx_wake_queue(tx_queue);
++ }
++
++ return HRTIMER_NORESTART;
++}
++
++/* pfe_eth_fast_tx_timeout_init
++ */
++static void pfe_eth_fast_tx_timeout_init(struct pfe_eth_priv_s *priv)
++{
++ int i;
++
++ for (i = 0; i < emac_txq_cnt; i++) {
++ priv->fast_tx_timeout[i].queuenum = i;
++ hrtimer_init(&priv->fast_tx_timeout[i].timer, CLOCK_MONOTONIC,
++ HRTIMER_MODE_REL);
++ priv->fast_tx_timeout[i].timer.function =
++ pfe_eth_fast_tx_timeout;
++ priv->fast_tx_timeout[i].base = priv->fast_tx_timeout;
++ }
++}
++
++static struct sk_buff *pfe_eth_rx_skb(struct net_device *ndev,
++ struct pfe_eth_priv_s *priv,
++ unsigned int qno)
++{
++ void *buf_addr;
++ unsigned int rx_ctrl;
++ unsigned int desc_ctrl = 0;
++ struct hif_ipsec_hdr *ipsec_hdr = NULL;
++ struct sk_buff *skb;
++ struct sk_buff *skb_frag, *skb_frag_last = NULL;
++ int length = 0, offset;
++
++ skb = priv->skb_inflight[qno];
++
++ if (skb) {
++ skb_frag_last = skb_shinfo(skb)->frag_list;
++ if (skb_frag_last) {
++ while (skb_frag_last->next)
++ skb_frag_last = skb_frag_last->next;
++ }
++ }
++
++ while (!(desc_ctrl & CL_DESC_LAST)) {
++ buf_addr = hif_lib_receive_pkt(&priv->client, qno, &length,
++ &offset, &rx_ctrl, &desc_ctrl,
++ (void **)&ipsec_hdr);
++ if (!buf_addr)
++ goto incomplete;
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_DESC_COUNT]++;
++#endif
++
++ /* First frag */
++ if (desc_ctrl & CL_DESC_FIRST) {
++ skb = build_skb(buf_addr, 0);
++ if (unlikely(!skb))
++ goto pkt_drop;
++
++ skb_reserve(skb, offset);
++ skb_put(skb, length);
++ skb->dev = ndev;
++
++ if ((ndev->features & NETIF_F_RXCSUM) && (rx_ctrl &
++ HIF_CTRL_RX_CHECKSUMMED))
++ skb->ip_summed = CHECKSUM_UNNECESSARY;
++ else
++ skb_checksum_none_assert(skb);
++
++ } else {
++ /* Next frags */
++ if (unlikely(!skb)) {
++ pr_err("%s: NULL skb_inflight\n",
++ __func__);
++ goto pkt_drop;
++ }
++
++ skb_frag = build_skb(buf_addr, 0);
++
++ if (unlikely(!skb_frag)) {
++ kfree(buf_addr);
++ goto pkt_drop;
++ }
++
++ skb_reserve(skb_frag, offset);
++ skb_put(skb_frag, length);
++
++ skb_frag->dev = ndev;
++
++ if (skb_shinfo(skb)->frag_list)
++ skb_frag_last->next = skb_frag;
++ else
++ skb_shinfo(skb)->frag_list = skb_frag;
++
++ skb->truesize += skb_frag->truesize;
++ skb->data_len += length;
++ skb->len += length;
++ skb_frag_last = skb_frag;
++ }
++ }
++
++ priv->skb_inflight[qno] = NULL;
++ return skb;
++
++incomplete:
++ priv->skb_inflight[qno] = skb;
++ return NULL;
++
++pkt_drop:
++ priv->skb_inflight[qno] = NULL;
++
++ if (skb)
++ kfree_skb(skb);
++ else
++ kfree(buf_addr);
++
++ priv->stats.rx_errors++;
++
++ return NULL;
++}
++
++/* pfe_eth_poll
++ */
++static int pfe_eth_poll(struct pfe_eth_priv_s *priv, struct napi_struct *napi,
++ unsigned int qno, int budget)
++{
++ struct net_device *ndev = priv->ndev;
++ struct sk_buff *skb;
++ int work_done = 0;
++ unsigned int len;
++
++ netif_info(priv, intr, priv->ndev, "%s\n", __func__);
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_POLL_COUNT]++;
++#endif
++
++ do {
++ skb = pfe_eth_rx_skb(ndev, priv, qno);
++
++ if (!skb)
++ break;
++
++ len = skb->len;
++
++ /* Packet will be processed */
++ skb->protocol = eth_type_trans(skb, ndev);
++
++ netif_receive_skb(skb);
++
++ priv->stats.rx_packets++;
++ priv->stats.rx_bytes += len;
++
++ work_done++;
++
++#ifdef PFE_ETH_NAPI_STATS
++ priv->napi_counters[NAPI_PACKET_COUNT]++;
++#endif
++
++ } while (work_done < budget);
++
++ /*
++ * If no Rx receive nor cleanup work was done, exit polling mode.
++ * No more netif_running(dev) check is required here , as this is
++ * checked in net/core/dev.c (2.6.33.5 kernel specific).
++ */
++ if (work_done < budget) {
++ napi_complete(napi);
++
++ hif_lib_event_handler_start(&priv->client, EVENT_RX_PKT_IND,
++ qno);
++ }
++#ifdef PFE_ETH_NAPI_STATS
++ else
++ priv->napi_counters[NAPI_FULL_BUDGET_COUNT]++;
++#endif
++
++ return work_done;
++}
++
++/*
++ * pfe_eth_lro_poll
++ */
++static int pfe_eth_lro_poll(struct napi_struct *napi, int budget)
++{
++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,
++ lro_napi);
++
++ netif_info(priv, intr, priv->ndev, "%s\n", __func__);
++
++ return pfe_eth_poll(priv, napi, 2, budget);
++}
++
++/* pfe_eth_low_poll
++ */
++static int pfe_eth_low_poll(struct napi_struct *napi, int budget)
++{
++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,
++ low_napi);
++
++ netif_info(priv, intr, priv->ndev, "%s\n", __func__);
++
++ return pfe_eth_poll(priv, napi, 1, budget);
++}
++
++/* pfe_eth_high_poll
++ */
++static int pfe_eth_high_poll(struct napi_struct *napi, int budget)
++{
++ struct pfe_eth_priv_s *priv = container_of(napi, struct pfe_eth_priv_s,
++ high_napi);
++
++ netif_info(priv, intr, priv->ndev, "%s\n", __func__);
++
++ return pfe_eth_poll(priv, napi, 0, budget);
++}
++
++static const struct net_device_ops pfe_netdev_ops = {
++ .ndo_open = pfe_eth_open,
++ .ndo_stop = pfe_eth_close,
++ .ndo_start_xmit = pfe_eth_send_packet,
++ .ndo_select_queue = pfe_eth_select_queue,
++ .ndo_set_rx_mode = pfe_eth_set_multi,
++ .ndo_set_mac_address = pfe_eth_set_mac_address,
++ .ndo_validate_addr = eth_validate_addr,
++ .ndo_change_mtu = pfe_eth_change_mtu,
++ .ndo_get_stats = pfe_eth_get_stats,
++ .ndo_set_features = pfe_eth_set_features,
++};
++
++/* pfe_eth_init_one
++ */
++static int pfe_eth_init_one(struct pfe *pfe,
++ struct ls1012a_pfe_platform_data *pfe_info,
++ int id)
++{
++ struct net_device *ndev = NULL;
++ struct pfe_eth_priv_s *priv = NULL;
++ struct ls1012a_eth_platform_data *einfo;
++ int err;
++
++ einfo = (struct ls1012a_eth_platform_data *)
++ pfe_info->ls1012a_eth_pdata;
++
++ /* einfo never be NULL, but no harm in having this check */
++ if (!einfo) {
++ pr_err(
++ "%s: pfe missing additional gemacs platform data\n"
++ , __func__);
++ err = -ENODEV;
++ goto err0;
++ }
++
++ if (us)
++ emac_txq_cnt = EMAC_TXQ_CNT;
++ /* Create an ethernet device instance */
++ ndev = alloc_etherdev_mq(sizeof(*priv), emac_txq_cnt);
++
++ if (!ndev) {
++ pr_err("%s: gemac %d device allocation failed\n",
++ __func__, einfo[id].gem_id);
++ err = -ENOMEM;
++ goto err0;
++ }
++
++ priv = netdev_priv(ndev);
++ priv->ndev = ndev;
++ priv->id = einfo[id].gem_id;
++ priv->pfe = pfe;
++ priv->phy_node = einfo[id].phy_node;
++
++ SET_NETDEV_DEV(priv->ndev, priv->pfe->dev);
++
++ pfe->eth.eth_priv[id] = priv;
++
++ /* Set the info in the priv to the current info */
++ priv->einfo = &einfo[id];
++ priv->EMAC_baseaddr = cbus_emac_base[id];
++ priv->GPI_baseaddr = cbus_gpi_base[id];
++
++ spin_lock_init(&priv->lock);
++
++ pfe_eth_fast_tx_timeout_init(priv);
++
++ /* Copy the station address into the dev structure, */
++ dev_addr_set(ndev, einfo[id].mac_addr);
++
++ if (us)
++ goto phy_init;
++
++ ndev->mtu = 1500;
++
++ /* Set MTU limits */
++ ndev->min_mtu = ETH_MIN_MTU;
++
++/*
++ * Jumbo frames are not supported on LS1012A rev-1.0.
++ * So max mtu should be restricted to supported frame length.
++ */
++ if (pfe_errata_a010897)
++ ndev->max_mtu = JUMBO_FRAME_SIZE_V1 - ETH_HLEN - ETH_FCS_LEN;
++ else
++ ndev->max_mtu = JUMBO_FRAME_SIZE_V2 - ETH_HLEN - ETH_FCS_LEN;
++
++ /*Enable after checksum offload is validated */
++ ndev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM |
++ NETIF_F_IPV6_CSUM | NETIF_F_SG;
++
++ /* enabled by default */
++ ndev->features = ndev->hw_features;
++
++ priv->usr_features = ndev->features;
++
++ ndev->netdev_ops = &pfe_netdev_ops;
++
++ ndev->ethtool_ops = &pfe_ethtool_ops;
++
++ /* Enable basic messages by default */
++ priv->msg_enable = NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK |
++ NETIF_MSG_PROBE;
++
++ netif_napi_add(ndev, &priv->low_napi, pfe_eth_low_poll);
++ netif_napi_add(ndev, &priv->high_napi, pfe_eth_high_poll);
++ netif_napi_add(ndev, &priv->lro_napi, pfe_eth_lro_poll);
++
++ err = register_netdev(ndev);
++ if (err) {
++ netdev_err(ndev, "register_netdev() failed\n");
++ goto err1;
++ }
++
++ if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) ||
++ ((pfe_use_old_dts_phy) &&
++ (priv->einfo->phy_flags & GEMAC_NO_PHY))) {
++ pr_info("%s: No PHY or fixed-link\n", __func__);
++ goto skip_phy_init;
++ }
++
++phy_init:
++ device_init_wakeup(&ndev->dev, true);
++
++ err = pfe_phy_init(ndev);
++ if (err) {
++ netdev_err(ndev, "%s: pfe_phy_init() failed\n",
++ __func__);
++ goto err2;
++ }
++
++ if (us) {
++ if (priv->phydev)
++ phy_start(priv->phydev);
++ return 0;
++ }
++
++ netif_carrier_on(ndev);
++
++skip_phy_init:
++ /* Create all the sysfs files */
++ if (pfe_eth_sysfs_init(ndev))
++ goto err3;
++
++ netif_info(priv, probe, ndev, "%s: created interface, baseaddr: %p\n",
++ __func__, priv->EMAC_baseaddr);
++
++ return 0;
++
++err3:
++ pfe_phy_exit(priv->ndev);
++err2:
++ if (us)
++ goto err1;
++ unregister_netdev(ndev);
++err1:
++ free_netdev(priv->ndev);
++err0:
++ return err;
++}
++
++/* pfe_eth_init
++ */
++int pfe_eth_init(struct pfe *pfe)
++{
++ int ii = 0;
++ int err;
++ struct ls1012a_pfe_platform_data *pfe_info;
++
++ pr_info("%s\n", __func__);
++
++ cbus_emac_base[0] = EMAC1_BASE_ADDR;
++ cbus_emac_base[1] = EMAC2_BASE_ADDR;
++
++ cbus_gpi_base[0] = EGPI1_BASE_ADDR;
++ cbus_gpi_base[1] = EGPI2_BASE_ADDR;
++
++ pfe_info = (struct ls1012a_pfe_platform_data *)
++ pfe->dev->platform_data;
++ if (!pfe_info) {
++ pr_err("%s: pfe missing additional platform data\n", __func__);
++ err = -ENODEV;
++ goto err_pdata;
++ }
++
++ for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) {
++ err = pfe_eth_mdio_init(pfe, pfe_info, ii);
++ if (err) {
++ pr_err("%s: pfe_eth_mdio_init() failed\n", __func__);
++ goto err_mdio_init;
++ }
++ }
++
++ if (soc_device_match(ls1012a_rev1_soc_attr))
++ pfe_errata_a010897 = true;
++ else
++ pfe_errata_a010897 = false;
++
++ for (ii = 0; ii < NUM_GEMAC_SUPPORT; ii++) {
++ err = pfe_eth_init_one(pfe, pfe_info, ii);
++ if (err)
++ goto err_eth_init;
++ }
++
++ return 0;
++
++err_eth_init:
++ while (ii--) {
++ pfe_eth_exit_one(pfe->eth.eth_priv[ii]);
++ pfe_eth_mdio_exit(pfe, ii);
++ }
++
++err_mdio_init:
++err_pdata:
++ return err;
++}
++
++/* pfe_eth_exit_one
++ */
++static void pfe_eth_exit_one(struct pfe_eth_priv_s *priv)
++{
++ netif_info(priv, probe, priv->ndev, "%s\n", __func__);
++
++ if (!us)
++ pfe_eth_sysfs_exit(priv->ndev);
++
++ if ((!(pfe_use_old_dts_phy) && !(priv->phy_node)) ||
++ ((pfe_use_old_dts_phy) &&
++ (priv->einfo->phy_flags & GEMAC_NO_PHY))) {
++ pr_info("%s: No PHY or fixed-link\n", __func__);
++ goto skip_phy_exit;
++ }
++
++ pfe_phy_exit(priv->ndev);
++
++skip_phy_exit:
++ if (!us)
++ unregister_netdev(priv->ndev);
++
++ free_netdev(priv->ndev);
++}
++
++/* pfe_eth_exit
++ */
++void pfe_eth_exit(struct pfe *pfe)
++{
++ int ii;
++
++ pr_info("%s\n", __func__);
++
++ for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--)
++ pfe_eth_exit_one(pfe->eth.eth_priv[ii]);
++
++ for (ii = NUM_GEMAC_SUPPORT - 1; ii >= 0; ii--)
++ pfe_eth_mdio_exit(pfe, ii);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_eth.h
+@@ -0,0 +1,175 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_ETH_H_
++#define _PFE_ETH_H_
++#include <linux/kernel.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/mii.h>
++#include <linux/phy.h>
++#include <linux/clk.h>
++#include <linux/interrupt.h>
++#include <linux/time.h>
++
++#define PFE_ETH_NAPI_STATS
++#define PFE_ETH_TX_STATS
++
++#define PFE_ETH_FRAGS_MAX (65536 / HIF_RX_PKT_MIN_SIZE)
++#define LRO_LEN_COUNT_MAX 32
++#define LRO_NB_COUNT_MAX 32
++
++#define PFE_PAUSE_FLAG_ENABLE 1
++#define PFE_PAUSE_FLAG_AUTONEG 2
++
++/* GEMAC configured by SW */
++/* GEMAC configured by phy lines (not for MII/GMII) */
++
++#define GEMAC_SW_FULL_DUPLEX BIT(9)
++#define GEMAC_SW_SPEED_10M (0 << 12)
++#define GEMAC_SW_SPEED_100M BIT(12)
++#define GEMAC_SW_SPEED_1G (2 << 12)
++
++#define GEMAC_NO_PHY BIT(0)
++
++struct ls1012a_eth_platform_data {
++ /* board specific information */
++ phy_interface_t mii_config;
++ u32 phy_flags;
++ u32 gem_id;
++ u32 phy_id;
++ u32 mdio_muxval;
++ u8 mac_addr[ETH_ALEN];
++ struct device_node *phy_node;
++};
++
++struct ls1012a_mdio_platform_data {
++ int id;
++ int irq[32];
++ u32 phy_mask;
++ int mdc_div;
++};
++
++struct ls1012a_pfe_platform_data {
++ struct ls1012a_eth_platform_data ls1012a_eth_pdata[3];
++ struct ls1012a_mdio_platform_data ls1012a_mdio_pdata[3];
++};
++
++#define NUM_GEMAC_SUPPORT 2
++#define DRV_NAME "pfe-eth"
++#define DRV_VERSION "1.0"
++
++#define LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS 3
++#define TX_POLL_TIMEOUT_MS 1000
++
++#define EMAC_TXQ_CNT 16
++#define EMAC_TXQ_DEPTH (HIF_TX_DESC_NT)
++
++#define JUMBO_FRAME_SIZE_V1 1900
++#define JUMBO_FRAME_SIZE_V2 10258
++/*
++ * Client Tx queue threshold, for txQ flush condition.
++ * It must be smaller than the queue size (in case we ever change it in the
++ * future).
++ */
++#define HIF_CL_TX_FLUSH_MARK 32
++
++/*
++ * Max number of TX resources (HIF descriptors or skbs) that will be released
++ * in a single go during batch recycling.
++ * Should be lower than the flush mark so the SW can provide the HW with a
++ * continuous stream of packets instead of bursts.
++ */
++#define TX_FREE_MAX_COUNT 16
++#define EMAC_RXQ_CNT 3
++#define EMAC_RXQ_DEPTH HIF_RX_DESC_NT
++/* make sure clients can receive a full burst of packets */
++#define EMAC_RMON_TXBYTES_POS 0x00
++#define EMAC_RMON_RXBYTES_POS 0x14
++
++#define EMAC_QUEUENUM_MASK (emac_txq_cnt - 1)
++#define EMAC_MDIO_TIMEOUT 1000
++#define MAX_UC_SPEC_ADDR_REG 31
++
++struct pfe_eth_fast_timer {
++ int queuenum;
++ struct hrtimer timer;
++ void *base;
++};
++
++struct pfe_eth_priv_s {
++ struct pfe *pfe;
++ struct hif_client_s client;
++ struct napi_struct lro_napi;
++ struct napi_struct low_napi;
++ struct napi_struct high_napi;
++ int low_tmu_q;
++ int high_tmu_q;
++ struct net_device_stats stats;
++ struct net_device *ndev;
++ int id;
++ int promisc;
++ unsigned int msg_enable;
++ unsigned int usr_features;
++
++ spinlock_t lock; /* protect member variables */
++ unsigned int event_status;
++ int irq;
++ void *EMAC_baseaddr;
++ void *GPI_baseaddr;
++ /* PHY stuff */
++ struct phy_device *phydev;
++ int oldspeed;
++ int oldduplex;
++ int oldlink;
++ struct device_node *phy_node;
++ struct clk *gemtx_clk;
++ int wol;
++ int pause_flag;
++
++ int default_priority;
++ struct pfe_eth_fast_timer fast_tx_timeout[EMAC_TXQ_CNT];
++
++ struct ls1012a_eth_platform_data *einfo;
++ struct sk_buff *skb_inflight[EMAC_RXQ_CNT + 6];
++
++#ifdef PFE_ETH_TX_STATS
++ unsigned int stop_queue_total[EMAC_TXQ_CNT];
++ unsigned int stop_queue_hif[EMAC_TXQ_CNT];
++ unsigned int stop_queue_hif_client[EMAC_TXQ_CNT];
++ unsigned int stop_queue_credit[EMAC_TXQ_CNT];
++ unsigned int clean_fail[EMAC_TXQ_CNT];
++ unsigned int was_stopped[EMAC_TXQ_CNT];
++#endif
++
++#ifdef PFE_ETH_NAPI_STATS
++ unsigned int napi_counters[NAPI_MAX_COUNT];
++#endif
++ unsigned int frags_inflight[EMAC_RXQ_CNT + 6];
++};
++
++struct pfe_eth {
++ struct pfe_eth_priv_s *eth_priv[3];
++};
++
++struct pfe_mdio_priv_s {
++ void __iomem *mdio_base;
++ int mdc_div;
++ struct mii_bus *mii_bus;
++};
++
++struct pfe_mdio {
++ struct pfe_mdio_priv_s *mdio_priv[3];
++};
++
++int pfe_eth_init(struct pfe *pfe);
++void pfe_eth_exit(struct pfe *pfe);
++int pfe_eth_suspend(struct net_device *dev);
++int pfe_eth_resume(struct net_device *dev);
++int pfe_eth_mdio_reset(struct mii_bus *bus);
++
++#endif /* _PFE_ETH_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_firmware.c
+@@ -0,0 +1,398 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++/*
++ * @file
++ * Contains all the functions to handle parsing and loading of PE firmware
++ * files.
++ */
++#include <linux/firmware.h>
++
++#include "pfe_mod.h"
++#include "pfe_firmware.h"
++#include "pfe/pfe.h"
++#include <linux/of_platform.h>
++#include <linux/of_address.h>
++
++static struct elf32_shdr *get_elf_section_header(const u8 *fw,
++ const char *section)
++{
++ struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw;
++ struct elf32_shdr *shdr;
++ struct elf32_shdr *shdr_shstr;
++ Elf32_Off e_shoff = be32_to_cpu(elf_hdr->e_shoff);
++ Elf32_Half e_shentsize = be16_to_cpu(elf_hdr->e_shentsize);
++ Elf32_Half e_shnum = be16_to_cpu(elf_hdr->e_shnum);
++ Elf32_Half e_shstrndx = be16_to_cpu(elf_hdr->e_shstrndx);
++ Elf32_Off shstr_offset;
++ Elf32_Word sh_name;
++ const char *name;
++ int i;
++
++ /* Section header strings */
++ shdr_shstr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff + e_shstrndx
++ * e_shentsize);
++ shstr_offset = be32_to_cpu(shdr_shstr->sh_offset);
++
++ for (i = 0; i < e_shnum; i++) {
++ shdr = (struct elf32_shdr *)((u8 *)elf_hdr + e_shoff
++ + i * e_shentsize);
++
++ sh_name = be32_to_cpu(shdr->sh_name);
++
++ name = (const char *)((u8 *)elf_hdr + shstr_offset + sh_name);
++
++ if (!strcmp(name, section))
++ return shdr;
++ }
++
++ pr_err("%s: didn't find section %s\n", __func__, section);
++
++ return NULL;
++}
++
++#if defined(CFG_DIAGS)
++static int pfe_get_diags_info(const u8 *fw, struct pfe_diags_info
++ *diags_info)
++{
++ struct elf32_shdr *shdr;
++ unsigned long offset, size;
++
++ shdr = get_elf_section_header(fw, ".pfe_diags_str");
++ if (shdr) {
++ offset = be32_to_cpu(shdr->sh_offset);
++ size = be32_to_cpu(shdr->sh_size);
++ diags_info->diags_str_base = be32_to_cpu(shdr->sh_addr);
++ diags_info->diags_str_size = size;
++ diags_info->diags_str_array = kmalloc(size, GFP_KERNEL);
++ memcpy(diags_info->diags_str_array, fw + offset, size);
++
++ return 0;
++ } else {
++ return -1;
++ }
++}
++#endif
++
++static void pfe_check_version_info(const u8 *fw)
++{
++ /*static char *version = NULL;*/
++ const u8 *elf_data = fw;
++ static char *version;
++
++ struct elf32_shdr *shdr = get_elf_section_header(fw, ".version");
++
++ if (shdr) {
++ if (!version) {
++ /*
++ * this is the first fw we load, use its version
++ * string as reference (whatever it is)
++ */
++ version = (char *)(elf_data +
++ be32_to_cpu(shdr->sh_offset));
++
++ pr_info("PFE binary version: %s\n", version);
++ } else {
++ /*
++ * already have loaded at least one firmware, check
++ * sequence can start now
++ */
++ if (strcmp(version, (char *)(elf_data +
++ be32_to_cpu(shdr->sh_offset)))) {
++ pr_info(
++ "WARNING: PFE firmware binaries from incompatible version\n");
++ }
++ }
++ } else {
++ /*
++ * version cannot be verified, a potential issue that should
++ * be reported
++ */
++ pr_info(
++ "WARNING: PFE firmware binaries from incompatible version\n");
++ }
++}
++
++/* PFE elf firmware loader.
++ * Loads an elf firmware image into a list of PE's (specified using a bitmask)
++ *
++ * @param pe_mask Mask of PE id's to load firmware to
++ * @param fw Pointer to the firmware image
++ *
++ * @return 0 on success, a negative value on error
++ *
++ */
++int pfe_load_elf(int pe_mask, const u8 *fw, struct pfe *pfe)
++{
++ struct elf32_hdr *elf_hdr = (struct elf32_hdr *)fw;
++ Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);
++ struct elf32_shdr *shdr = (struct elf32_shdr *)(fw +
++ be32_to_cpu(elf_hdr->e_shoff));
++ int id, section;
++ int rc;
++
++ pr_info("%s\n", __func__);
++
++ /* Some sanity checks */
++ if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG)) {
++ pr_err("%s: incorrect elf magic number\n", __func__);
++ return -EINVAL;
++ }
++
++ if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32) {
++ pr_err("%s: incorrect elf class(%x)\n", __func__,
++ elf_hdr->e_ident[EI_CLASS]);
++ return -EINVAL;
++ }
++
++ if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB) {
++ pr_err("%s: incorrect elf data(%x)\n", __func__,
++ elf_hdr->e_ident[EI_DATA]);
++ return -EINVAL;
++ }
++
++ if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC) {
++ pr_err("%s: incorrect elf file type(%x)\n", __func__,
++ be16_to_cpu(elf_hdr->e_type));
++ return -EINVAL;
++ }
++
++ for (section = 0; section < sections; section++, shdr++) {
++ if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC |
++ SHF_EXECINSTR)))
++ continue;
++
++ for (id = 0; id < MAX_PE; id++)
++ if (pe_mask & (1 << id)) {
++ rc = pe_load_elf_section(id, elf_hdr, shdr,
++ pfe->dev);
++ if (rc < 0)
++ goto err;
++ }
++ }
++
++ pfe_check_version_info(fw);
++
++ return 0;
++
++err:
++ return rc;
++}
++
++int get_firmware_in_fdt(const u8 **pe_fw, const char *name)
++{
++ struct device_node *np;
++ const unsigned int *len;
++ const void *data;
++
++ if (!strcmp(name, CLASS_FIRMWARE_FILENAME)) {
++ /* The firmware should be inside the device tree. */
++ np = of_find_compatible_node(NULL, NULL,
++ "fsl,pfe-class-firmware");
++ if (!np) {
++ pr_info("Failed to find the node\n");
++ return -ENOENT;
++ }
++
++ data = of_get_property(np, "fsl,class-firmware", NULL);
++ if (data) {
++ len = of_get_property(np, "length", NULL);
++ pr_info("CLASS fw of length %d bytes loaded from FDT.\n",
++ be32_to_cpu(*len));
++ } else {
++ pr_info("fsl,class-firmware not found!!!!\n");
++ return -ENOENT;
++ }
++ of_node_put(np);
++ *pe_fw = data;
++ } else if (!strcmp(name, TMU_FIRMWARE_FILENAME)) {
++ np = of_find_compatible_node(NULL, NULL,
++ "fsl,pfe-tmu-firmware");
++ if (!np) {
++ pr_info("Failed to find the node\n");
++ return -ENOENT;
++ }
++
++ data = of_get_property(np, "fsl,tmu-firmware", NULL);
++ if (data) {
++ len = of_get_property(np, "length", NULL);
++ pr_info("TMU fw of length %d bytes loaded from FDT.\n",
++ be32_to_cpu(*len));
++ } else {
++ pr_info("fsl,tmu-firmware not found!!!!\n");
++ return -ENOENT;
++ }
++ of_node_put(np);
++ *pe_fw = data;
++ } else if (!strcmp(name, UTIL_FIRMWARE_FILENAME)) {
++ np = of_find_compatible_node(NULL, NULL,
++ "fsl,pfe-util-firmware");
++ if (!np) {
++ pr_info("Failed to find the node\n");
++ return -ENOENT;
++ }
++
++ data = of_get_property(np, "fsl,util-firmware", NULL);
++ if (data) {
++ len = of_get_property(np, "length", NULL);
++ pr_info("UTIL fw of length %d bytes loaded from FDT.\n",
++ be32_to_cpu(*len));
++ } else {
++ pr_info("fsl,util-firmware not found!!!!\n");
++ return -ENOENT;
++ }
++ of_node_put(np);
++ *pe_fw = data;
++ } else {
++ pr_err("firmware:%s not known\n", name);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/* PFE firmware initialization.
++ * Loads different firmware files from filesystem.
++ * Initializes PE IMEM/DMEM and UTIL-PE DDR
++ * Initializes control path symbol addresses (by looking them up in the elf
++ * firmware files
++ * Takes PE's out of reset
++ *
++ * @return 0 on success, a negative value on error
++ *
++ */
++int pfe_firmware_init(struct pfe *pfe)
++{
++ const struct firmware *class_fw, *tmu_fw;
++ const u8 *class_elf_fw, *tmu_elf_fw;
++ int rc = 0, fs_load = 0;
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ const struct firmware *util_fw;
++ const u8 *util_elf_fw;
++
++#endif
++
++ pr_info("%s\n", __func__);
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) ||
++ get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME) ||
++ get_firmware_in_fdt(&util_elf_fw, UTIL_FIRMWARE_FILENAME))
++#else
++ if (get_firmware_in_fdt(&class_elf_fw, CLASS_FIRMWARE_FILENAME) ||
++ get_firmware_in_fdt(&tmu_elf_fw, TMU_FIRMWARE_FILENAME))
++#endif
++ {
++ pr_info("%s:PFE firmware not found in FDT.\n", __func__);
++ pr_info("%s:Trying to load firmware from filesystem...!\n", __func__);
++
++ /* look for firmware in filesystem...!*/
++ fs_load = 1;
++ if (request_firmware(&class_fw, CLASS_FIRMWARE_FILENAME, pfe->dev)) {
++ pr_err("%s: request firmware %s failed\n", __func__,
++ CLASS_FIRMWARE_FILENAME);
++ rc = -ETIMEDOUT;
++ goto err0;
++ }
++ class_elf_fw = class_fw->data;
++
++ if (request_firmware(&tmu_fw, TMU_FIRMWARE_FILENAME, pfe->dev)) {
++ pr_err("%s: request firmware %s failed\n", __func__,
++ TMU_FIRMWARE_FILENAME);
++ rc = -ETIMEDOUT;
++ goto err1;
++ }
++ tmu_elf_fw = tmu_fw->data;
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ if (request_firmware(&util_fw, UTIL_FIRMWARE_FILENAME, pfe->dev)) {
++ pr_err("%s: request firmware %s failed\n", __func__,
++ UTIL_FIRMWARE_FILENAME);
++ rc = -ETIMEDOUT;
++ goto err2;
++ }
++ util_elf_fw = util_fw->data;
++#endif
++ }
++
++ rc = pfe_load_elf(CLASS_MASK, class_elf_fw, pfe);
++ if (rc < 0) {
++ pr_err("%s: class firmware load failed\n", __func__);
++ goto err3;
++ }
++
++#if defined(CFG_DIAGS)
++ rc = pfe_get_diags_info(class_elf_fw, &pfe->diags.class_diags_info);
++ if (rc < 0) {
++ pr_warn(
++ "PFE diags won't be available for class PEs\n");
++ rc = 0;
++ }
++#endif
++
++ rc = pfe_load_elf(TMU_MASK, tmu_elf_fw, pfe);
++ if (rc < 0) {
++ pr_err("%s: tmu firmware load failed\n", __func__);
++ goto err3;
++ }
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ rc = pfe_load_elf(UTIL_MASK, util_elf_fw, pfe);
++ if (rc < 0) {
++ pr_err("%s: util firmware load failed\n", __func__);
++ goto err3;
++ }
++
++#if defined(CFG_DIAGS)
++ rc = pfe_get_diags_info(util_elf_fw, &pfe->diags.util_diags_info);
++ if (rc < 0) {
++ pr_warn(
++ "PFE diags won't be available for util PE\n");
++ rc = 0;
++ }
++#endif
++
++ util_enable();
++#endif
++
++ tmu_enable(0xf);
++ class_enable();
++
++err3:
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ if (fs_load)
++ release_firmware(util_fw);
++err2:
++#endif
++ if (fs_load)
++ release_firmware(tmu_fw);
++
++err1:
++ if (fs_load)
++ release_firmware(class_fw);
++
++err0:
++ return rc;
++}
++
++/* PFE firmware cleanup
++ * Puts PE's in reset
++ *
++ *
++ */
++void pfe_firmware_exit(struct pfe *pfe)
++{
++ pr_info("%s\n", __func__);
++
++ if (pe_reset_all(&pfe->ctrl) != 0)
++ pr_err("Error: Failed to stop PEs, PFE reload may not work correctly\n");
++
++ class_disable();
++ tmu_disable(0xf);
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ util_disable();
++#endif
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_firmware.h
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_FIRMWARE_H_
++#define _PFE_FIRMWARE_H_
++
++#define CLASS_FIRMWARE_FILENAME "ppfe_class_ls1012a.elf"
++#define TMU_FIRMWARE_FILENAME "ppfe_tmu_ls1012a.elf"
++#define UTIL_FIRMWARE_FILENAME "ppfe_util_ls1012a.elf"
++
++#define PFE_FW_CHECK_PASS 0
++#define PFE_FW_CHECK_FAIL 1
++#define NUM_PFE_FW 3
++
++int pfe_firmware_init(struct pfe *pfe);
++void pfe_firmware_exit(struct pfe *pfe);
++
++#endif /* _PFE_FIRMWARE_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hal.c
+@@ -0,0 +1,1517 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include "pfe_mod.h"
++#include "pfe/pfe.h"
++
++/* A-010897: Jumbo frame is not supported */
++extern bool pfe_errata_a010897;
++
++#define PFE_RCR_MAX_FL_MASK 0xC000FFFF
++
++void *cbus_base_addr;
++void *ddr_base_addr;
++unsigned long ddr_phys_base_addr;
++unsigned int ddr_size;
++
++static struct pe_info pe[MAX_PE];
++
++/* Initializes the PFE library.
++ * Must be called before using any of the library functions.
++ *
++ * @param[in] cbus_base CBUS virtual base address (as mapped in
++ * the host CPU address space)
++ * @param[in] ddr_base PFE DDR range virtual base address (as
++ * mapped in the host CPU address space)
++ * @param[in] ddr_phys_base PFE DDR range physical base address (as
++ * mapped in platform)
++ * @param[in] size PFE DDR range size (as defined by the host
++ * software)
++ */
++void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,
++ unsigned int size)
++{
++ cbus_base_addr = cbus_base;
++ ddr_base_addr = ddr_base;
++ ddr_phys_base_addr = ddr_phys_base;
++ ddr_size = size;
++
++ pe[CLASS0_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(0);
++ pe[CLASS0_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(0);
++ pe[CLASS0_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS0_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS0_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS0_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS1_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(1);
++ pe[CLASS1_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(1);
++ pe[CLASS1_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS1_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS1_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS1_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS2_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(2);
++ pe[CLASS2_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(2);
++ pe[CLASS2_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS2_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS2_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS2_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS3_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(3);
++ pe[CLASS3_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(3);
++ pe[CLASS3_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS3_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS3_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS3_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS4_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(4);
++ pe[CLASS4_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(4);
++ pe[CLASS4_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS4_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS4_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS4_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++ pe[CLASS5_ID].dmem_base_addr = CLASS_DMEM_BASE_ADDR(5);
++ pe[CLASS5_ID].pmem_base_addr = CLASS_IMEM_BASE_ADDR(5);
++ pe[CLASS5_ID].pmem_size = CLASS_IMEM_SIZE;
++ pe[CLASS5_ID].mem_access_wdata = CLASS_MEM_ACCESS_WDATA;
++ pe[CLASS5_ID].mem_access_addr = CLASS_MEM_ACCESS_ADDR;
++ pe[CLASS5_ID].mem_access_rdata = CLASS_MEM_ACCESS_RDATA;
++
++ pe[TMU0_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(0);
++ pe[TMU0_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(0);
++ pe[TMU0_ID].pmem_size = TMU_IMEM_SIZE;
++ pe[TMU0_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
++ pe[TMU0_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
++ pe[TMU0_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
++
++ pe[TMU1_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(1);
++ pe[TMU1_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(1);
++ pe[TMU1_ID].pmem_size = TMU_IMEM_SIZE;
++ pe[TMU1_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
++ pe[TMU1_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
++ pe[TMU1_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
++
++ pe[TMU3_ID].dmem_base_addr = TMU_DMEM_BASE_ADDR(3);
++ pe[TMU3_ID].pmem_base_addr = TMU_IMEM_BASE_ADDR(3);
++ pe[TMU3_ID].pmem_size = TMU_IMEM_SIZE;
++ pe[TMU3_ID].mem_access_wdata = TMU_MEM_ACCESS_WDATA;
++ pe[TMU3_ID].mem_access_addr = TMU_MEM_ACCESS_ADDR;
++ pe[TMU3_ID].mem_access_rdata = TMU_MEM_ACCESS_RDATA;
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ pe[UTIL_ID].dmem_base_addr = UTIL_DMEM_BASE_ADDR;
++ pe[UTIL_ID].mem_access_wdata = UTIL_MEM_ACCESS_WDATA;
++ pe[UTIL_ID].mem_access_addr = UTIL_MEM_ACCESS_ADDR;
++ pe[UTIL_ID].mem_access_rdata = UTIL_MEM_ACCESS_RDATA;
++#endif
++}
++
++/* Writes a buffer to PE internal memory from the host
++ * through indirect access registers.
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] src Buffer source address
++ * @param[in] mem_access_addr DMEM destination address (must be 32bit
++ * aligned)
++ * @param[in] len Number of bytes to copy
++ */
++void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned
++int len)
++{
++ u32 offset = 0, val, addr;
++ unsigned int len32 = len >> 2;
++ int i;
++
++ addr = mem_access_addr | PE_MEM_ACCESS_WRITE |
++ PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
++
++ for (i = 0; i < len32; i++, offset += 4, src += 4) {
++ val = *(u32 *)src;
++ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
++ writel(addr + offset, pe[id].mem_access_addr);
++ }
++
++ len = (len & 0x3);
++ if (len) {
++ val = 0;
++
++ addr = (mem_access_addr | PE_MEM_ACCESS_WRITE |
++ PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
++
++ for (i = 0; i < len; i++, src++)
++ val |= (*(u8 *)src) << (8 * i);
++
++ writel(cpu_to_be32(val), pe[id].mem_access_wdata);
++ writel(addr, pe[id].mem_access_addr);
++ }
++}
++
++/* Writes a buffer to PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] src Buffer source address
++ * @param[in] dst DMEM destination address (must be 32bit
++ * aligned)
++ * @param[in] len Number of bytes to copy
++ */
++void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++{
++ pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst |
++ PE_MEM_ACCESS_DMEM, src, len);
++}
++
++/* Writes a buffer to PE internal program memory (PMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., TMU3_ID)
++ * @param[in] src Buffer source address
++ * @param[in] dst PMEM destination address (must be 32bit
++ * aligned)
++ * @param[in] len Number of bytes to copy
++ */
++void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
++{
++ pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size
++ - 1)) | PE_MEM_ACCESS_IMEM, src, len);
++}
++
++/* Reads PE internal program memory (IMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., TMU3_ID)
++ * @param[in] addr PMEM read address (must be aligned on size)
++ * @param[in] size Number of bytes to read (maximum 4, must not
++ * cross 32bit boundaries)
++ * @return the data read (in PE endianness, i.e BE).
++ */
++u32 pe_pmem_read(int id, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++ u32 mask = 0xffffffff >> ((4 - size) << 3);
++ u32 val;
++
++ addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1))
++ | PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++ writel(addr, pe[id].mem_access_addr);
++ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
++
++ return (val >> (offset << 3)) & mask;
++}
++
++/* Writes PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] addr DMEM write address (must be aligned on size)
++ * @param[in] val Value to write (in PE endianness, i.e BE)
++ * @param[in] size Number of bytes to write (maximum 4, must not
++ * cross 32bit boundaries)
++ */
++void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++
++ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE |
++ PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++ /* Indirect access interface is byte swapping data being written */
++ writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
++ writel(addr, pe[id].mem_access_addr);
++}
++
++/* Reads PE internal data memory (DMEM) from the host
++ * through indirect access registers.
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] addr DMEM read address (must be aligned on size)
++ * @param[in] size Number of bytes to read (maximum 4, must not
++ * cross 32bit boundaries)
++ * @return the data read (in PE endianness, i.e BE).
++ */
++u32 pe_dmem_read(int id, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++ u32 mask = 0xffffffff >> ((4 - size) << 3);
++ u32 val;
++
++ addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_DMEM |
++ PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
++
++ writel(addr, pe[id].mem_access_addr);
++
++ /* Indirect access interface is byte swapping data being read */
++ val = be32_to_cpu(readl(pe[id].mem_access_rdata));
++
++ return (val >> (offset << 3)) & mask;
++}
++
++/* This function is used to write to CLASS internal bus peripherals (ccu,
++ * pe-lem) from the host
++ * through indirect access registers.
++ * @param[in] val value to write
++ * @param[in] addr Address to write to (must be aligned on size)
++ * @param[in] size Number of bytes to write (1, 2 or 4)
++ *
++ */
++void class_bus_write(u32 val, u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++
++ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE |
++ (size << 24);
++
++ writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
++ writel(addr, CLASS_BUS_ACCESS_ADDR);
++}
++
++/* Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
++ * through indirect access registers.
++ * @param[in] addr Address to read from (must be aligned on size)
++ * @param[in] size Number of bytes to read (1, 2 or 4)
++ * @return the read data
++ *
++ */
++u32 class_bus_read(u32 addr, u8 size)
++{
++ u32 offset = addr & 0x3;
++ u32 mask = 0xffffffff >> ((4 - size) << 3);
++ u32 val;
++
++ writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
++
++ addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
++
++ writel(addr, CLASS_BUS_ACCESS_ADDR);
++ val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
++
++ return (val >> (offset << 3)) & mask;
++}
++
++/* Writes data to the cluster memory (PE_LMEM)
++ * @param[in] dst PE LMEM destination address (must be 32bit aligned)
++ * @param[in] src Buffer source address
++ * @param[in] len Number of bytes to copy
++ */
++void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len)
++{
++ u32 len32 = len >> 2;
++ int i;
++
++ for (i = 0; i < len32; i++, src += 4, dst += 4)
++ class_bus_write(*(u32 *)src, dst, 4);
++
++ if (len & 0x2) {
++ class_bus_write(*(u16 *)src, dst, 2);
++ src += 2;
++ dst += 2;
++ }
++
++ if (len & 0x1) {
++ class_bus_write(*(u8 *)src, dst, 1);
++ src++;
++ dst++;
++ }
++}
++
++/* Writes value to the cluster memory (PE_LMEM)
++ * @param[in] dst PE LMEM destination address (must be 32bit aligned)
++ * @param[in] val Value to write
++ * @param[in] len Number of bytes to write
++ */
++void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
++{
++ u32 len32 = len >> 2;
++ int i;
++
++ val = val | (val << 8) | (val << 16) | (val << 24);
++
++ for (i = 0; i < len32; i++, dst += 4)
++ class_bus_write(val, dst, 4);
++
++ if (len & 0x2) {
++ class_bus_write(val, dst, 2);
++ dst += 2;
++ }
++
++ if (len & 0x1) {
++ class_bus_write(val, dst, 1);
++ dst++;
++ }
++}
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++
++/* Writes UTIL program memory (DDR) from the host.
++ *
++ * @param[in] addr Address to write (virtual, must be aligned on size)
++ * @param[in] val Value to write (in PE endianness, i.e BE)
++ * @param[in] size Number of bytes to write (2 or 4)
++ */
++static void util_pmem_write(u32 val, void *addr, u8 size)
++{
++ void *addr64 = (void *)((unsigned long)addr & ~0x7);
++ unsigned long off = 8 - ((unsigned long)addr & 0x7) - size;
++
++ /*
++ * IMEM should be loaded as a 64bit swapped value in a 64bit aligned
++ * location
++ */
++ if (size == 4)
++ writel(be32_to_cpu(val), addr64 + off);
++ else
++ writew(be16_to_cpu((u16)val), addr64 + off);
++}
++
++/* Writes a buffer to UTIL program memory (DDR) from the host.
++ *
++ * @param[in] dst Address to write (virtual, must be at least 16bit
++ * aligned)
++ * @param[in] src Buffer to write (in PE endianness, i.e BE, must have
++ * same alignment as dst)
++ * @param[in] len Number of bytes to write (must be at least 16bit
++ * aligned)
++ */
++static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
++{
++ unsigned int len32;
++ int i;
++
++ if ((unsigned long)src & 0x2) {
++ util_pmem_write(*(u16 *)src, dst, 2);
++ src += 2;
++ dst += 2;
++ len -= 2;
++ }
++
++ len32 = len >> 2;
++
++ for (i = 0; i < len32; i++, dst += 4, src += 4)
++ util_pmem_write(*(u32 *)src, dst, 4);
++
++ if (len & 0x2)
++ util_pmem_write(*(u16 *)src, dst, len & 0x2);
++}
++#endif
++
++/* Loads an elf section into pmem
++ * Code needs to be at least 16bit aligned and only PROGBITS sections are
++ * supported
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID, ...,
++ * TMU3_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_pmem_section(int id, const void *data,
++ struct elf32_shdr *shdr)
++{
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ if (id == UTIL_ID) {
++ pr_err("%s: unsupported pmem section for UTIL\n",
++ __func__);
++ return -EINVAL;
++ }
++#endif
++
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
++ pr_err(
++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n"
++ , __func__, addr, (unsigned long)data + offset);
++
++ return -EINVAL;
++ }
++
++ if (addr & 0x1) {
++ pr_err("%s: load address(%x) is not 16bit aligned\n",
++ __func__, addr);
++ return -EINVAL;
++ }
++
++ if (size & 0x1) {
++ pr_err("%s: load size(%x) is not 16bit aligned\n",
++ __func__, size);
++ return -EINVAL;
++ }
++
++ switch (type) {
++ case SHT_PROGBITS:
++ pe_pmem_memcpy_to32(id, addr, data + offset, size);
++
++ break;
++
++ default:
++ pr_err("%s: unsupported section type(%x)\n", __func__,
++ type);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/* Loads an elf section into dmem
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
++ * initialized to 0
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_dmem_section(int id, const void *data,
++ struct elf32_shdr *shdr)
++{
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++ u32 size32 = size >> 2;
++ int i;
++
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
++ pr_err(
++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long)data + offset);
++
++ return -EINVAL;
++ }
++
++ if (addr & 0x3) {
++ pr_err("%s: load address(%x) is not 32bit aligned\n",
++ __func__, addr);
++ return -EINVAL;
++ }
++
++ switch (type) {
++ case SHT_PROGBITS:
++ pe_dmem_memcpy_to32(id, addr, data + offset, size);
++ break;
++
++ case SHT_NOBITS:
++ for (i = 0; i < size32; i++, addr += 4)
++ pe_dmem_write(id, 0, addr, 4);
++
++ if (size & 0x3)
++ pe_dmem_write(id, 0, addr, size & 0x3);
++
++ break;
++
++ default:
++ pr_err("%s: unsupported section type(%x)\n", __func__,
++ type);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/* Loads an elf section into DDR
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
++ * initialized to 0
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_ddr_section(int id, const void *data,
++ struct elf32_shdr *shdr,
++ struct device *dev) {
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++ u32 flags = be32_to_cpu(shdr->sh_flags);
++
++ switch (type) {
++ case SHT_PROGBITS:
++ if (flags & SHF_EXECINSTR) {
++ if (id <= CLASS_MAX_ID) {
++ /* DO the loading only once in DDR */
++ if (id == CLASS0_ID) {
++ pr_err(
++ "%s: load address(%x) and elf file address(%lx) rcvd\n",
++ __func__, addr,
++ (unsigned long)data + offset);
++ if (((unsigned long)(data + offset)
++ & 0x3) != (addr & 0x3)) {
++ pr_err(
++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n"
++ , __func__, addr,
++ (unsigned long)data + offset);
++
++ return -EINVAL;
++ }
++
++ if (addr & 0x1) {
++ pr_err(
++ "%s: load address(%x) is not 16bit aligned\n"
++ , __func__, addr);
++ return -EINVAL;
++ }
++
++ if (size & 0x1) {
++ pr_err(
++ "%s: load length(%x) is not 16bit aligned\n"
++ , __func__, size);
++ return -EINVAL;
++ }
++ memcpy(DDR_PHYS_TO_VIRT(
++ DDR_PFE_TO_PHYS(addr)),
++ data + offset, size);
++ }
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ } else if (id == UTIL_ID) {
++ if (((unsigned long)(data + offset) & 0x3)
++ != (addr & 0x3)) {
++ pr_err(
++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n"
++ , __func__, addr,
++ (unsigned long)data + offset);
++
++ return -EINVAL;
++ }
++
++ if (addr & 0x1) {
++ pr_err(
++ "%s: load address(%x) is not 16bit aligned\n"
++ , __func__, addr);
++ return -EINVAL;
++ }
++
++ if (size & 0x1) {
++ pr_err(
++ "%s: load length(%x) is not 16bit aligned\n"
++ , __func__, size);
++ return -EINVAL;
++ }
++
++ util_pmem_memcpy(DDR_PHYS_TO_VIRT(
++ DDR_PFE_TO_PHYS(addr)),
++ data + offset, size);
++ }
++#endif
++ } else {
++ pr_err(
++ "%s: unsupported ddr section type(%x) for PE(%d)\n"
++ , __func__, type, id);
++ return -EINVAL;
++ }
++
++ } else {
++ memcpy(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), data
++ + offset, size);
++ }
++
++ break;
++
++ case SHT_NOBITS:
++ memset(DDR_PHYS_TO_VIRT(DDR_PFE_TO_PHYS(addr)), 0, size);
++
++ break;
++
++ default:
++ pr_err("%s: unsupported section type(%x)\n", __func__,
++ type);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/* Loads an elf section into pe lmem
++ * Data needs to be at least 32bit aligned, NOBITS sections are correctly
++ * initialized to 0
++ *
++ * @param[in] id PE identification (CLASS0_ID,..., CLASS5_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++static int pe_load_pe_lmem_section(int id, const void *data,
++ struct elf32_shdr *shdr)
++{
++ u32 offset = be32_to_cpu(shdr->sh_offset);
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++ u32 type = be32_to_cpu(shdr->sh_type);
++
++ if (id > CLASS_MAX_ID) {
++ pr_err(
++ "%s: unsupported pe-lmem section type(%x) for PE(%d)\n",
++ __func__, type, id);
++ return -EINVAL;
++ }
++
++ if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3)) {
++ pr_err(
++ "%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
++ __func__, addr, (unsigned long)data + offset);
++
++ return -EINVAL;
++ }
++
++ if (addr & 0x3) {
++ pr_err("%s: load address(%x) is not 32bit aligned\n",
++ __func__, addr);
++ return -EINVAL;
++ }
++
++ switch (type) {
++ case SHT_PROGBITS:
++ class_pe_lmem_memcpy_to32(addr, data + offset, size);
++ break;
++
++ case SHT_NOBITS:
++ class_pe_lmem_memset(addr, 0, size);
++ break;
++
++ default:
++ pr_err("%s: unsupported section type(%x)\n", __func__,
++ type);
++ return -EINVAL;
++ }
++
++ return 0;
++}
++
++/* Loads an elf section into a PE
++ * For now only supports loading a section to dmem (all PE's), pmem (class and
++ * tmu PE's),
++ * DDDR (util PE code)
++ *
++ * @param[in] id PE identification (CLASS0_ID, ..., TMU0_ID,
++ * ..., UTIL_ID)
++ * @param[in] data pointer to the elf firmware
++ * @param[in] shdr pointer to the elf section header
++ *
++ */
++int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr,
++ struct device *dev) {
++ u32 addr = be32_to_cpu(shdr->sh_addr);
++ u32 size = be32_to_cpu(shdr->sh_size);
++
++ if (IS_DMEM(addr, size))
++ return pe_load_dmem_section(id, data, shdr);
++ else if (IS_PMEM(addr, size))
++ return pe_load_pmem_section(id, data, shdr);
++ else if (IS_PFE_LMEM(addr, size))
++ return 0;
++ else if (IS_PHYS_DDR(addr, size))
++ return pe_load_ddr_section(id, data, shdr, dev);
++ else if (IS_PE_LMEM(addr, size))
++ return pe_load_pe_lmem_section(id, data, shdr);
++
++ pr_err("%s: unsupported memory range(%x)\n", __func__,
++ addr);
++ return 0;
++}
++
++/**************************** BMU ***************************/
++
++/* Initializes a BMU block.
++ * @param[in] base BMU block base address
++ * @param[in] cfg BMU configuration
++ */
++void bmu_init(void *base, struct BMU_CFG *cfg)
++{
++ bmu_disable(base);
++
++ bmu_set_config(base, cfg);
++
++ bmu_reset(base);
++}
++
++/* Resets a BMU block.
++ * @param[in] base BMU block base address
++ */
++void bmu_reset(void *base)
++{
++ writel(CORE_SW_RESET, base + BMU_CTRL);
++
++ /* Wait for self clear */
++ while (readl(base + BMU_CTRL) & CORE_SW_RESET)
++ ;
++}
++
++/* Enabled a BMU block.
++ * @param[in] base BMU block base address
++ */
++void bmu_enable(void *base)
++{
++ writel(CORE_ENABLE, base + BMU_CTRL);
++}
++
++/* Disables a BMU block.
++ * @param[in] base BMU block base address
++ */
++void bmu_disable(void *base)
++{
++ writel(CORE_DISABLE, base + BMU_CTRL);
++}
++
++/* Sets the configuration of a BMU block.
++ * @param[in] base BMU block base address
++ * @param[in] cfg BMU configuration
++ */
++void bmu_set_config(void *base, struct BMU_CFG *cfg)
++{
++ writel(cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
++ writel(cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
++ writel(cfg->size & 0xffff, base + BMU_BUF_SIZE);
++
++ /* Interrupts are never used */
++ writel(cfg->low_watermark, base + BMU_LOW_WATERMARK);
++ writel(cfg->high_watermark, base + BMU_HIGH_WATERMARK);
++ writel(0x0, base + BMU_INT_ENABLE);
++}
++
++/**************************** MTIP GEMAC ***************************/
++
++/* Enable Rx Checksum Engine. With this enabled, Frame with bad IP,
++ * TCP or UDP checksums are discarded
++ *
++ * @param[in] base GEMAC base address.
++ */
++void gemac_enable_rx_checksum_offload(void *base)
++{
++ /*Do not find configuration to do this */
++}
++
++/* Disable Rx Checksum Engine.
++ *
++ * @param[in] base GEMAC base address.
++ */
++void gemac_disable_rx_checksum_offload(void *base)
++{
++ /*Do not find configuration to do this */
++}
++
++/* GEMAC set speed.
++ * @param[in] base GEMAC base address
++ * @param[in] speed GEMAC speed (10, 100 or 1000 Mbps)
++ */
++void gemac_set_speed(void *base, enum mac_speed gem_speed)
++{
++ u32 ecr = readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
++ u32 rcr = readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
++
++ switch (gem_speed) {
++ case SPEED_10M:
++ rcr |= EMAC_RCNTRL_RMII_10T;
++ break;
++
++ case SPEED_1000M:
++ ecr |= EMAC_ECNTRL_SPEED;
++ break;
++
++ case SPEED_100M:
++ default:
++ /*It is in 100M mode */
++ break;
++ }
++ writel(ecr, (base + EMAC_ECNTRL_REG));
++ writel(rcr, (base + EMAC_RCNTRL_REG));
++}
++
++/* GEMAC set duplex.
++ * @param[in] base GEMAC base address
++ * @param[in] duplex GEMAC duplex mode (Full, Half)
++ */
++void gemac_set_duplex(void *base, int duplex)
++{
++ if (duplex == DUPLEX_HALF) {
++ writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_FDEN, base
++ + EMAC_TCNTRL_REG);
++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_DRT, (base
++ + EMAC_RCNTRL_REG));
++ } else{
++ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_FDEN, base
++ + EMAC_TCNTRL_REG);
++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_DRT, (base
++ + EMAC_RCNTRL_REG));
++ }
++}
++
++/* GEMAC set mode.
++ * @param[in] base GEMAC base address
++ * @param[in] mode GEMAC operation mode (MII, RMII, RGMII, SGMII)
++ */
++void gemac_set_mode(void *base, int mode)
++{
++ u32 val = readl(base + EMAC_RCNTRL_REG);
++
++ /*Remove loopbank*/
++ val &= ~EMAC_RCNTRL_LOOP;
++
++ /* Enable flow control and MII mode.PFE firmware always expects
++ CRC should be forwarded by MAC to validate CRC in software.*/
++ val |= (EMAC_RCNTRL_FCE | EMAC_RCNTRL_MII_MODE);
++
++ writel(val, base + EMAC_RCNTRL_REG);
++}
++
++/* GEMAC enable function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_enable(void *base)
++{
++ writel(readl(base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, base +
++ EMAC_ECNTRL_REG);
++}
++
++/* GEMAC disable function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_disable(void *base)
++{
++ writel(readl(base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, base +
++ EMAC_ECNTRL_REG);
++}
++
++/* GEMAC TX disable function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_tx_disable(void *base)
++{
++ writel(readl(base + EMAC_TCNTRL_REG) | EMAC_TCNTRL_GTS, base +
++ EMAC_TCNTRL_REG);
++}
++
++void gemac_tx_enable(void *base)
++{
++ writel(readl(base + EMAC_TCNTRL_REG) & ~EMAC_TCNTRL_GTS, base +
++ EMAC_TCNTRL_REG);
++}
++
++/* Sets the hash register of the MAC.
++ * This register is used for matching unicast and multicast frames.
++ *
++ * @param[in] base GEMAC base address.
++ * @param[in] hash 64-bit hash to be configured.
++ */
++void gemac_set_hash(void *base, struct pfe_mac_addr *hash)
++{
++ writel(hash->bottom, base + EMAC_GALR);
++ writel(hash->top, base + EMAC_GAUR);
++}
++
++void gemac_set_laddrN(void *base, struct pfe_mac_addr *address,
++ unsigned int entry_index)
++{
++ if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX))
++ return;
++
++ entry_index = entry_index - 1;
++ if (entry_index < 1) {
++ writel(htonl(address->bottom), base + EMAC_PHY_ADDR_LOW);
++ writel((htonl(address->top) | 0x8808), base +
++ EMAC_PHY_ADDR_HIGH);
++ } else {
++ writel(htonl(address->bottom), base + ((entry_index - 1) * 8)
++ + EMAC_SMAC_0_0);
++ writel((htonl(address->top) | 0x8808), base + ((entry_index -
++ 1) * 8) + EMAC_SMAC_0_1);
++ }
++}
++
++void gemac_clear_laddrN(void *base, unsigned int entry_index)
++{
++ if ((entry_index < 1) || (entry_index > EMAC_SPEC_ADDR_MAX))
++ return;
++
++ entry_index = entry_index - 1;
++ if (entry_index < 1) {
++ writel(0, base + EMAC_PHY_ADDR_LOW);
++ writel(0, base + EMAC_PHY_ADDR_HIGH);
++ } else {
++ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_0);
++ writel(0, base + ((entry_index - 1) * 8) + EMAC_SMAC_0_1);
++ }
++}
++
++/* Set the loopback mode of the MAC. This can be either no loopback for
++ * normal operation, local loopback through MAC internal loopback module or PHY
++ * loopback for external loopback through a PHY. This asserts the external
++ * loop pin.
++ *
++ * @param[in] base GEMAC base address.
++ * @param[in] gem_loop Loopback mode to be enabled. LB_LOCAL - MAC
++ * Loopback,
++ * LB_EXT - PHY Loopback.
++ */
++void gemac_set_loop(void *base, enum mac_loop gem_loop)
++{
++ pr_info("%s()\n", __func__);
++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_LOOP, (base +
++ EMAC_RCNTRL_REG));
++}
++
++/* GEMAC allow frames
++ * @param[in] base GEMAC base address
++ */
++void gemac_enable_copy_all(void *base)
++{
++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_PROM, (base +
++ EMAC_RCNTRL_REG));
++}
++
++/* GEMAC do not allow frames
++ * @param[in] base GEMAC base address
++ */
++void gemac_disable_copy_all(void *base)
++{
++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_PROM, (base +
++ EMAC_RCNTRL_REG));
++}
++
++/* GEMAC allow broadcast function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_allow_broadcast(void *base)
++{
++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_BC_REJ, base +
++ EMAC_RCNTRL_REG);
++}
++
++/* GEMAC no broadcast function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_no_broadcast(void *base)
++{
++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_BC_REJ, base +
++ EMAC_RCNTRL_REG);
++}
++
++/* GEMAC enable 1536 rx function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_enable_1536_rx(void *base)
++{
++ /* Set 1536 as Maximum frame length */
++ writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK)
++ | (1536 << 16), base + EMAC_RCNTRL_REG);
++}
++
++/* GEMAC set rx Max frame length.
++ * @param[in] base GEMAC base address
++ * @param[in] mtu new mtu
++ */
++void gemac_set_rx_max_fl(void *base, int mtu)
++{
++ /* Set mtu as Maximum frame length */
++ writel((readl(base + EMAC_RCNTRL_REG) & PFE_RCR_MAX_FL_MASK)
++ | (mtu << 16), base + EMAC_RCNTRL_REG);
++}
++
++/* GEMAC enable stacked vlan function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_enable_stacked_vlan(void *base)
++{
++ /* MTIP doesn't support stacked vlan */
++}
++
++/* GEMAC enable pause rx function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_enable_pause_rx(void *base)
++{
++ writel(readl(base + EMAC_RCNTRL_REG) | EMAC_RCNTRL_FCE,
++ base + EMAC_RCNTRL_REG);
++}
++
++/* GEMAC disable pause rx function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_disable_pause_rx(void *base)
++{
++ writel(readl(base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_FCE,
++ base + EMAC_RCNTRL_REG);
++}
++
++/* GEMAC enable pause tx function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_enable_pause_tx(void *base)
++{
++ writel(EMAC_RX_SECTION_EMPTY_V, base + EMAC_RX_SECTION_EMPTY);
++}
++
++/* GEMAC disable pause tx function.
++ * @param[in] base GEMAC base address
++ */
++void gemac_disable_pause_tx(void *base)
++{
++ writel(0x0, base + EMAC_RX_SECTION_EMPTY);
++}
++
++/* GEMAC wol configuration
++ * @param[in] base GEMAC base address
++ * @param[in] wol_conf WoL register configuration
++ */
++void gemac_set_wol(void *base, u32 wol_conf)
++{
++ u32 val = readl(base + EMAC_ECNTRL_REG);
++
++ if (wol_conf)
++ val |= (EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);
++ else
++ val &= ~(EMAC_ECNTRL_MAGIC_ENA | EMAC_ECNTRL_SLEEP);
++ writel(val, base + EMAC_ECNTRL_REG);
++}
++
++/* Sets Gemac bus width to 64bit
++ * @param[in] base GEMAC base address
++ * @param[in] width gemac bus width to be set possible values are 32/64/128
++ */
++void gemac_set_bus_width(void *base, int width)
++{
++}
++
++/* Sets Gemac configuration.
++ * @param[in] base GEMAC base address
++ * @param[in] cfg GEMAC configuration
++ */
++void gemac_set_config(void *base, struct gemac_cfg *cfg)
++{
++ /*GEMAC config taken from VLSI */
++ writel(0x00000004, base + EMAC_TFWR_STR_FWD);
++ writel(0x00000005, base + EMAC_RX_SECTION_FULL);
++
++ if (pfe_errata_a010897)
++ writel(0x0000076c, base + EMAC_TRUNC_FL);
++ else
++ writel(0x00003fff, base + EMAC_TRUNC_FL);
++
++ writel(0x00000030, base + EMAC_TX_SECTION_EMPTY);
++ writel(0x00000000, base + EMAC_MIB_CTRL_STS_REG);
++
++ gemac_set_mode(base, cfg->mode);
++
++ gemac_set_speed(base, cfg->speed);
++
++ gemac_set_duplex(base, cfg->duplex);
++}
++
++/**************************** GPI ***************************/
++
++/* Initializes a GPI block.
++ * @param[in] base GPI base address
++ * @param[in] cfg GPI configuration
++ */
++void gpi_init(void *base, struct gpi_cfg *cfg)
++{
++ gpi_reset(base);
++
++ gpi_disable(base);
++
++ gpi_set_config(base, cfg);
++}
++
++/* Resets a GPI block.
++ * @param[in] base GPI base address
++ */
++void gpi_reset(void *base)
++{
++ writel(CORE_SW_RESET, base + GPI_CTRL);
++}
++
++/* Enables a GPI block.
++ * @param[in] base GPI base address
++ */
++void gpi_enable(void *base)
++{
++ writel(CORE_ENABLE, base + GPI_CTRL);
++}
++
++/* Disables a GPI block.
++ * @param[in] base GPI base address
++ */
++void gpi_disable(void *base)
++{
++ writel(CORE_DISABLE, base + GPI_CTRL);
++}
++
++/* Sets the configuration of a GPI block.
++ * @param[in] base GPI base address
++ * @param[in] cfg GPI configuration
++ */
++void gpi_set_config(void *base, struct gpi_cfg *cfg)
++{
++ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL), base
++ + GPI_LMEM_ALLOC_ADDR);
++ writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL), base
++ + GPI_LMEM_FREE_ADDR);
++ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL), base
++ + GPI_DDR_ALLOC_ADDR);
++ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL), base
++ + GPI_DDR_FREE_ADDR);
++ writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR), base + GPI_CLASS_ADDR);
++ writel(DDR_HDR_SIZE, base + GPI_DDR_DATA_OFFSET);
++ writel(LMEM_HDR_SIZE, base + GPI_LMEM_DATA_OFFSET);
++ writel(0, base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
++ writel(0, base + GPI_DDR_SEC_BUF_DATA_OFFSET);
++ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, base + GPI_HDR_SIZE);
++ writel((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE, base + GPI_BUF_SIZE);
++
++ writel(((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) |
++ GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
++ writel(cfg->tmlf_txthres, base + GPI_TMLF_TX);
++ writel(cfg->aseq_len, base + GPI_DTX_ASEQ);
++ writel(1, base + GPI_TOE_CHKSUM_EN);
++
++ if (cfg->mtip_pause_reg) {
++ writel(cfg->mtip_pause_reg, base + GPI_CSR_MTIP_PAUSE_REG);
++ writel(EGPI_PAUSE_TIME, base + GPI_TX_PAUSE_TIME);
++ }
++}
++
++/**************************** CLASSIFIER ***************************/
++
++/* Initializes CLASSIFIER block.
++ * @param[in] cfg CLASSIFIER configuration
++ */
++void class_init(struct class_cfg *cfg)
++{
++ class_reset();
++
++ class_disable();
++
++ class_set_config(cfg);
++}
++
++/* Resets CLASSIFIER block.
++ *
++ */
++void class_reset(void)
++{
++ writel(CORE_SW_RESET, CLASS_TX_CTRL);
++}
++
++/* Enables all CLASS-PE's cores.
++ *
++ */
++void class_enable(void)
++{
++ writel(CORE_ENABLE, CLASS_TX_CTRL);
++}
++
++/* Disables all CLASS-PE's cores.
++ *
++ */
++void class_disable(void)
++{
++ writel(CORE_DISABLE, CLASS_TX_CTRL);
++}
++
++/*
++ * Sets the configuration of the CLASSIFIER block.
++ * @param[in] cfg CLASSIFIER configuration
++ */
++void class_set_config(struct class_cfg *cfg)
++{
++ u32 val;
++
++ /* Initialize route table */
++ if (!cfg->resume)
++ memset(DDR_PHYS_TO_VIRT(cfg->route_table_baseaddr), 0, (1 <<
++ cfg->route_table_hash_bits) * CLASS_ROUTE_SIZE);
++
++#if !defined(LS1012A_PFE_RESET_WA)
++ writel(cfg->pe_sys_clk_ratio, CLASS_PE_SYS_CLK_RATIO);
++#endif
++
++ writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE, CLASS_HDR_SIZE);
++ writel(LMEM_BUF_SIZE, CLASS_LMEM_BUF_SIZE);
++ writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) |
++ CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits),
++ CLASS_ROUTE_HASH_ENTRY_SIZE);
++ writel(HIF_PKT_CLASS_EN | HIF_PKT_OFFSET(sizeof(struct hif_hdr)),
++ CLASS_HIF_PARSE);
++
++ val = HASH_CRC_PORT_IP | QB2BUS_LE;
++
++#if defined(CONFIG_IP_ALIGNED)
++ val |= IP_ALIGNED;
++#endif
++
++ /*
++ * Class PE packet steering will only work if TOE mode, bridge fetch or
++ * route fetch are enabled (see class/qb_fet.v). Route fetch would
++ * trigger additional memory copies (likely from DDR because of hash
++ * table size, which cannot be reduced because PE software still
++ * relies on hash value computed in HW), so when not in TOE mode we
++ * simply enable HW bridge fetch even though we don't use it.
++ */
++ if (cfg->toe_mode)
++ val |= CLASS_TOE;
++ else
++ val |= HW_BRIDGE_FETCH;
++
++ writel(val, CLASS_ROUTE_MULTI);
++
++ writel(DDR_PHYS_TO_PFE(cfg->route_table_baseaddr),
++ CLASS_ROUTE_TABLE_BASE);
++ writel(CLASS_PE0_RO_DM_ADDR0_VAL, CLASS_PE0_RO_DM_ADDR0);
++ writel(CLASS_PE0_RO_DM_ADDR1_VAL, CLASS_PE0_RO_DM_ADDR1);
++ writel(CLASS_PE0_QB_DM_ADDR0_VAL, CLASS_PE0_QB_DM_ADDR0);
++ writel(CLASS_PE0_QB_DM_ADDR1_VAL, CLASS_PE0_QB_DM_ADDR1);
++ writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR), CLASS_TM_INQ_ADDR);
++
++ writel(23, CLASS_AFULL_THRES);
++ writel(23, CLASS_TSQ_FIFO_THRES);
++
++ writel(24, CLASS_MAX_BUF_CNT);
++ writel(24, CLASS_TSQ_MAX_CNT);
++}
++
++/**************************** TMU ***************************/
++
++void tmu_reset(void)
++{
++ writel(SW_RESET, TMU_CTRL);
++}
++
++/* Initializes TMU block.
++ * @param[in] cfg TMU configuration
++ */
++void tmu_init(struct tmu_cfg *cfg)
++{
++ int q, phyno;
++
++ tmu_disable(0xF);
++ mdelay(10);
++
++#if !defined(LS1012A_PFE_RESET_WA)
++ /* keep in soft reset */
++ writel(SW_RESET, TMU_CTRL);
++#endif
++ writel(0x3, TMU_SYS_GENERIC_CONTROL);
++ writel(750, TMU_INQ_WATERMARK);
++ writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR +
++ GPI_INQ_PKTPTR), TMU_PHY0_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR +
++ GPI_INQ_PKTPTR), TMU_PHY1_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR +
++ GPI_INQ_PKTPTR), TMU_PHY3_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR), TMU_PHY4_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR), TMU_PHY5_INQ_ADDR);
++ writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),
++ TMU_BMU_INQ_ADDR);
++
++ writel(0x3FF, TMU_TDQ0_SCH_CTRL); /*
++ * enabling all 10
++ * schedulers [9:0] of each TDQ
++ */
++ writel(0x3FF, TMU_TDQ1_SCH_CTRL);
++ writel(0x3FF, TMU_TDQ3_SCH_CTRL);
++
++#if !defined(LS1012A_PFE_RESET_WA)
++ writel(cfg->pe_sys_clk_ratio, TMU_PE_SYS_CLK_RATIO);
++#endif
++
++#if !defined(LS1012A_PFE_RESET_WA)
++ writel(DDR_PHYS_TO_PFE(cfg->llm_base_addr), TMU_LLM_BASE_ADDR);
++ /* Extra packet pointers will be stored from this address onwards */
++
++ writel(cfg->llm_queue_len, TMU_LLM_QUE_LEN);
++ writel(5, TMU_TDQ_IIFG_CFG);
++ writel(DDR_BUF_SIZE, TMU_BMU_BUF_SIZE);
++
++ writel(0x0, TMU_CTRL);
++
++ /* MEM init */
++ pr_info("%s: mem init\n", __func__);
++ writel(MEM_INIT, TMU_CTRL);
++
++ while (!(readl(TMU_CTRL) & MEM_INIT_DONE))
++ ;
++
++ /* LLM init */
++ pr_info("%s: lmem init\n", __func__);
++ writel(LLM_INIT, TMU_CTRL);
++
++ while (!(readl(TMU_CTRL) & LLM_INIT_DONE))
++ ;
++#endif
++ /* set up each queue for tail drop */
++ for (phyno = 0; phyno < 4; phyno++) {
++ if (phyno == 2)
++ continue;
++ for (q = 0; q < 16; q++) {
++ u32 qdepth;
++
++ writel((phyno << 8) | q, TMU_TEQ_CTRL);
++ writel(1 << 22, TMU_TEQ_QCFG); /*Enable tail drop */
++
++ if (phyno == 3)
++ qdepth = DEFAULT_TMU3_QDEPTH;
++ else
++ qdepth = (q == 0) ? DEFAULT_Q0_QDEPTH :
++ DEFAULT_MAX_QDEPTH;
++
++ /* LOG: 68855 */
++ /*
++ * The following is a workaround for the reordered
++ * packet and BMU2 buffer leakage issue.
++ */
++ if (CHIP_REVISION() == 0)
++ qdepth = 31;
++
++ writel(qdepth << 18, TMU_TEQ_HW_PROB_CFG2);
++ writel(qdepth >> 14, TMU_TEQ_HW_PROB_CFG3);
++ }
++ }
++
++#ifdef CFG_LRO
++ /* Set TMU-3 queue 5 (LRO) in no-drop mode */
++ writel((3 << 8) | TMU_QUEUE_LRO, TMU_TEQ_CTRL);
++ writel(0, TMU_TEQ_QCFG);
++#endif
++
++ writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
++
++ writel(0x0, TMU_CTRL);
++}
++
++/* Enables TMU-PE cores.
++ * @param[in] pe_mask TMU PE mask
++ */
++void tmu_enable(u32 pe_mask)
++{
++ writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
++}
++
++/* Disables TMU cores.
++ * @param[in] pe_mask TMU PE mask
++ */
++void tmu_disable(u32 pe_mask)
++{
++ writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);
++}
++
++/* This will return the tmu queue status
++ * @param[in] if_id gem interface id or TMU index
++ * @return returns the bit mask of busy queues, zero means all
++ * queues are empty
++ */
++u32 tmu_qstatus(u32 if_id)
++{
++ return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS +
++ offsetof(struct pe_status, tmu_qstatus), 4));
++}
++
++u32 tmu_pkts_processed(u32 if_id)
++{
++ return cpu_to_be32(pe_dmem_read(TMU0_ID + if_id, TMU_DM_PESTATUS +
++ offsetof(struct pe_status, rx), 4));
++}
++
++/**************************** UTIL ***************************/
++
++/* Resets UTIL block.
++ */
++void util_reset(void)
++{
++ writel(CORE_SW_RESET, UTIL_TX_CTRL);
++}
++
++/* Initializes UTIL block.
++ * @param[in] cfg UTIL configuration
++ */
++void util_init(struct util_cfg *cfg)
++{
++ writel(cfg->pe_sys_clk_ratio, UTIL_PE_SYS_CLK_RATIO);
++}
++
++/* Enables UTIL-PE core.
++ *
++ */
++void util_enable(void)
++{
++ writel(CORE_ENABLE, UTIL_TX_CTRL);
++}
++
++/* Disables UTIL-PE core.
++ *
++ */
++void util_disable(void)
++{
++ writel(CORE_DISABLE, UTIL_TX_CTRL);
++}
++
++/**************************** HIF ***************************/
++/* Initializes HIF copy block.
++ *
++ */
++void hif_init(void)
++{
++ /*Initialize HIF registers*/
++ writel((HIF_RX_POLL_CTRL_CYCLE << 16) | HIF_TX_POLL_CTRL_CYCLE,
++ HIF_POLL_CTRL);
++}
++
++/* Enable hif tx DMA and interrupt
++ *
++ */
++void hif_tx_enable(void)
++{
++ writel(HIF_CTRL_DMA_EN, HIF_TX_CTRL);
++ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN),
++ HIF_INT_ENABLE);
++}
++
++/* Disable hif tx DMA and interrupt
++ *
++ */
++void hif_tx_disable(void)
++{
++ u32 hif_int;
++
++ writel(0, HIF_TX_CTRL);
++
++ hif_int = readl(HIF_INT_ENABLE);
++ hif_int &= HIF_TXPKT_INT_EN;
++ writel(hif_int, HIF_INT_ENABLE);
++}
++
++/* Enable hif rx DMA and interrupt
++ *
++ */
++void hif_rx_enable(void)
++{
++ hif_rx_dma_start();
++ writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN),
++ HIF_INT_ENABLE);
++}
++
++/* Disable hif rx DMA and interrupt
++ *
++ */
++void hif_rx_disable(void)
++{
++ u32 hif_int;
++
++ writel(0, HIF_RX_CTRL);
++
++ hif_int = readl(HIF_INT_ENABLE);
++ hif_int &= HIF_RXPKT_INT_EN;
++ writel(hif_int, HIF_INT_ENABLE);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif.c
+@@ -0,0 +1,1063 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/sched.h>
++#include <linux/module.h>
++#include <linux/list.h>
++#include <linux/kthread.h>
++#include <linux/slab.h>
++
++#include <linux/io.h>
++#include <asm/irq.h>
++
++#include "pfe_mod.h"
++
++#define HIF_INT_MASK (HIF_INT | HIF_RXPKT_INT | HIF_TXPKT_INT)
++
++unsigned char napi_first_batch;
++
++static void pfe_tx_do_cleanup(unsigned long data);
++
++static int pfe_hif_alloc_descr(struct pfe_hif *hif)
++{
++ void *addr;
++ dma_addr_t dma_addr;
++ int err = 0;
++
++ pr_info("%s\n", __func__);
++ addr = dma_alloc_coherent(pfe->dev,
++ HIF_RX_DESC_NT * sizeof(struct hif_desc) +
++ HIF_TX_DESC_NT * sizeof(struct hif_desc),
++ &dma_addr, GFP_KERNEL);
++
++ if (!addr) {
++ pr_err("%s: Could not allocate buffer descriptors!\n"
++ , __func__);
++ err = -ENOMEM;
++ goto err0;
++ }
++
++ hif->descr_baseaddr_p = dma_addr;
++ hif->descr_baseaddr_v = addr;
++ hif->rx_ring_size = HIF_RX_DESC_NT;
++ hif->tx_ring_size = HIF_TX_DESC_NT;
++
++ return 0;
++
++err0:
++ return err;
++}
++
++#if defined(LS1012A_PFE_RESET_WA)
++static void pfe_hif_disable_rx_desc(struct pfe_hif *hif)
++{
++ int ii;
++ struct hif_desc *desc = hif->rx_base;
++
++ /*Mark all descriptors as LAST_BD */
++ for (ii = 0; ii < hif->rx_ring_size; ii++) {
++ desc->ctrl |= BD_CTRL_LAST_BD;
++ desc++;
++ }
++}
++
++struct class_rx_hdr_t {
++ u32 next_ptr; /* ptr to the start of the first DDR buffer */
++ u16 length; /* total packet length */
++ u16 phyno; /* input physical port number */
++ u32 status; /* gemac status bits */
++ u32 status2; /* reserved for software usage */
++};
++
++/* STATUS_BAD_FRAME_ERR is set for all errors (including checksums if enabled)
++ * except overflow
++ */
++#define STATUS_BAD_FRAME_ERR BIT(16)
++#define STATUS_LENGTH_ERR BIT(17)
++#define STATUS_CRC_ERR BIT(18)
++#define STATUS_TOO_SHORT_ERR BIT(19)
++#define STATUS_TOO_LONG_ERR BIT(20)
++#define STATUS_CODE_ERR BIT(21)
++#define STATUS_MC_HASH_MATCH BIT(22)
++#define STATUS_CUMULATIVE_ARC_HIT BIT(23)
++#define STATUS_UNICAST_HASH_MATCH BIT(24)
++#define STATUS_IP_CHECKSUM_CORRECT BIT(25)
++#define STATUS_TCP_CHECKSUM_CORRECT BIT(26)
++#define STATUS_UDP_CHECKSUM_CORRECT BIT(27)
++#define STATUS_OVERFLOW_ERR BIT(28) /* GPI error */
++#define MIN_PKT_SIZE 64
++
++static inline void copy_to_lmem(u32 *dst, u32 *src, int len)
++{
++ int i;
++
++ for (i = 0; i < len; i += sizeof(u32)) {
++ *dst = htonl(*src);
++ dst++; src++;
++ }
++}
++
++static void send_dummy_pkt_to_hif(void)
++{
++ void *lmem_ptr, *ddr_ptr, *lmem_virt_addr;
++ u32 physaddr;
++ struct class_rx_hdr_t local_hdr;
++ static u32 dummy_pkt[] = {
++ 0x33221100, 0x2b785544, 0xd73093cb, 0x01000608,
++ 0x04060008, 0x2b780200, 0xd73093cb, 0x0a01a8c0,
++ 0x33221100, 0xa8c05544, 0x00000301, 0x00000000,
++ 0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };
++
++ ddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL));
++ if (!ddr_ptr)
++ return;
++
++ lmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL));
++ if (!lmem_ptr)
++ return;
++
++ pr_info("Sending a dummy pkt to HIF %p %p\n", ddr_ptr, lmem_ptr);
++ physaddr = (u32)DDR_VIRT_TO_PFE(ddr_ptr);
++
++ lmem_virt_addr = (void *)CBUS_PFE_TO_VIRT((unsigned long int)lmem_ptr);
++
++ local_hdr.phyno = htons(0); /* RX_PHY_0 */
++ local_hdr.length = htons(MIN_PKT_SIZE);
++
++ local_hdr.next_ptr = htonl((u32)physaddr);
++ /*Mark checksum is correct */
++ local_hdr.status = htonl((STATUS_IP_CHECKSUM_CORRECT |
++ STATUS_UDP_CHECKSUM_CORRECT |
++ STATUS_TCP_CHECKSUM_CORRECT |
++ STATUS_UNICAST_HASH_MATCH |
++ STATUS_CUMULATIVE_ARC_HIT));
++ local_hdr.status2 = 0;
++
++ copy_to_lmem((u32 *)lmem_virt_addr, (u32 *)&local_hdr,
++ sizeof(local_hdr));
++
++ copy_to_lmem((u32 *)(lmem_virt_addr + LMEM_HDR_SIZE), (u32 *)dummy_pkt,
++ 0x40);
++
++ writel((unsigned long int)lmem_ptr, CLASS_INQ_PKTPTR);
++}
++
++void pfe_hif_rx_idle(struct pfe_hif *hif)
++{
++ int hif_stop_loop = 10;
++ u32 rx_status;
++
++ pfe_hif_disable_rx_desc(hif);
++ pr_info("Bringing hif to idle state...");
++ writel(0, HIF_INT_ENABLE);
++ /*If HIF Rx BDP is busy send a dummy packet */
++ do {
++ rx_status = readl(HIF_RX_STATUS);
++ if (rx_status & BDP_CSR_RX_DMA_ACTV)
++ send_dummy_pkt_to_hif();
++
++ usleep_range(100, 150);
++ } while (--hif_stop_loop);
++
++ if (readl(HIF_RX_STATUS) & BDP_CSR_RX_DMA_ACTV)
++ pr_info("Failed\n");
++ else
++ pr_info("Done\n");
++}
++#endif
++
++static void pfe_hif_free_descr(struct pfe_hif *hif)
++{
++ pr_info("%s\n", __func__);
++
++ dma_free_coherent(pfe->dev,
++ hif->rx_ring_size * sizeof(struct hif_desc) +
++ hif->tx_ring_size * sizeof(struct hif_desc),
++ hif->descr_baseaddr_v, hif->descr_baseaddr_p);
++}
++
++void pfe_hif_desc_dump(struct pfe_hif *hif)
++{
++ struct hif_desc *desc;
++ unsigned long desc_p;
++ int ii = 0;
++
++ pr_info("%s\n", __func__);
++
++ desc = hif->rx_base;
++ desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v +
++ hif->descr_baseaddr_p);
++
++ pr_info("HIF Rx desc base %p physical %x\n", desc, (u32)desc_p);
++ for (ii = 0; ii < hif->rx_ring_size; ii++) {
++ pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n",
++ readl(&desc->status), readl(&desc->ctrl),
++ readl(&desc->data), readl(&desc->next));
++ desc++;
++ }
++
++ desc = hif->tx_base;
++ desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v +
++ hif->descr_baseaddr_p);
++
++ pr_info("HIF Tx desc base %p physical %x\n", desc, (u32)desc_p);
++ for (ii = 0; ii < hif->tx_ring_size; ii++) {
++ pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n",
++ readl(&desc->status), readl(&desc->ctrl),
++ readl(&desc->data), readl(&desc->next));
++ desc++;
++ }
++}
++
++/* pfe_hif_release_buffers */
++static void pfe_hif_release_buffers(struct pfe_hif *hif)
++{
++ struct hif_desc *desc;
++ int i = 0;
++
++ hif->rx_base = hif->descr_baseaddr_v;
++
++ pr_info("%s\n", __func__);
++
++ /*Free Rx buffers */
++ desc = hif->rx_base;
++ for (i = 0; i < hif->rx_ring_size; i++) {
++ if (readl(&desc->data)) {
++ if ((i < hif->shm->rx_buf_pool_cnt) &&
++ (!hif->shm->rx_buf_pool[i])) {
++ /*
++ * dma_unmap_single(hif->dev, desc->data,
++ * hif->rx_buf_len[i], DMA_FROM_DEVICE);
++ */
++ dma_unmap_single(hif->dev,
++ DDR_PFE_TO_PHYS(
++ readl(&desc->data)),
++ hif->rx_buf_len[i],
++ DMA_FROM_DEVICE);
++ hif->shm->rx_buf_pool[i] = hif->rx_buf_addr[i];
++ } else {
++ pr_err("%s: buffer pool already full\n"
++ , __func__);
++ }
++ }
++
++ writel(0, &desc->data);
++ writel(0, &desc->status);
++ writel(0, &desc->ctrl);
++ desc++;
++ }
++}
++
++/*
++ * pfe_hif_init_buffers
++ * This function initializes the HIF Rx/Tx ring descriptors and
++ * initialize Rx queue with buffers.
++ */
++static int pfe_hif_init_buffers(struct pfe_hif *hif)
++{
++ struct hif_desc *desc, *first_desc_p;
++ u32 data;
++ int i = 0;
++
++ pr_info("%s\n", __func__);
++
++ /* Check enough Rx buffers available in the shared memory */
++ if (hif->shm->rx_buf_pool_cnt < hif->rx_ring_size)
++ return -ENOMEM;
++
++ hif->rx_base = hif->descr_baseaddr_v;
++ memset(hif->rx_base, 0, hif->rx_ring_size * sizeof(struct hif_desc));
++
++ /*Initialize Rx descriptors */
++ desc = hif->rx_base;
++ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p;
++
++ for (i = 0; i < hif->rx_ring_size; i++) {
++ /* Initialize Rx buffers from the shared memory */
++
++ data = (u32)dma_map_single(hif->dev, hif->shm->rx_buf_pool[i],
++ pfe_pkt_size, DMA_FROM_DEVICE);
++ hif->rx_buf_addr[i] = hif->shm->rx_buf_pool[i];
++ hif->rx_buf_len[i] = pfe_pkt_size;
++ hif->shm->rx_buf_pool[i] = NULL;
++
++ if (likely(dma_mapping_error(hif->dev, data) == 0)) {
++ writel(DDR_PHYS_TO_PFE(data), &desc->data);
++ } else {
++ pr_err("%s : low on mem\n", __func__);
++
++ goto err;
++ }
++
++ writel(0, &desc->status);
++
++ /*
++ * Ensure everything else is written to DDR before
++ * writing bd->ctrl
++ */
++ wmb();
++
++ writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM
++ | BD_CTRL_DIR | BD_CTRL_DESC_EN
++ | BD_BUF_LEN(pfe_pkt_size)), &desc->ctrl);
++
++ /* Chain descriptors */
++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next);
++ desc++;
++ }
++
++ /* Overwrite last descriptor to chain it to first one*/
++ desc--;
++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next);
++
++ hif->rxtoclean_index = 0;
++
++ /*Initialize Rx buffer descriptor ring base address */
++ writel(DDR_PHYS_TO_PFE(hif->descr_baseaddr_p), HIF_RX_BDP_ADDR);
++
++ hif->tx_base = hif->rx_base + hif->rx_ring_size;
++ first_desc_p = (struct hif_desc *)hif->descr_baseaddr_p +
++ hif->rx_ring_size;
++ memset(hif->tx_base, 0, hif->tx_ring_size * sizeof(struct hif_desc));
++
++ /*Initialize tx descriptors */
++ desc = hif->tx_base;
++
++ for (i = 0; i < hif->tx_ring_size; i++) {
++ /* Chain descriptors */
++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p + i + 1), &desc->next);
++ writel(0, &desc->ctrl);
++ desc++;
++ }
++
++ /* Overwrite last descriptor to chain it to first one */
++ desc--;
++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), &desc->next);
++ hif->txavail = hif->tx_ring_size;
++ hif->txtosend = 0;
++ hif->txtoclean = 0;
++ hif->txtoflush = 0;
++
++ /*Initialize Tx buffer descriptor ring base address */
++ writel((u32)DDR_PHYS_TO_PFE(first_desc_p), HIF_TX_BDP_ADDR);
++
++ return 0;
++
++err:
++ pfe_hif_release_buffers(hif);
++ return -ENOMEM;
++}
++
++/*
++ * pfe_hif_client_register
++ *
++ * This function used to register a client driver with the HIF driver.
++ *
++ * Return value:
++ * 0 - on Successful registration
++ */
++static int pfe_hif_client_register(struct pfe_hif *hif, u32 client_id,
++ struct hif_client_shm *client_shm)
++{
++ struct hif_client *client = &hif->client[client_id];
++ u32 i, cnt;
++ struct rx_queue_desc *rx_qbase;
++ struct tx_queue_desc *tx_qbase;
++ struct hif_rx_queue *rx_queue;
++ struct hif_tx_queue *tx_queue;
++ int err = 0;
++
++ pr_info("%s\n", __func__);
++
++ spin_lock_bh(&hif->tx_lock);
++
++ if (test_bit(client_id, &hif->shm->g_client_status[0])) {
++ pr_err("%s: client %d already registered\n",
++ __func__, client_id);
++ err = -1;
++ goto unlock;
++ }
++
++ memset(client, 0, sizeof(struct hif_client));
++
++ /* Initialize client Rx queues baseaddr, size */
++
++ cnt = CLIENT_CTRL_RX_Q_CNT(client_shm->ctrl);
++ /* Check if client is requesting for more queues than supported */
++ if (cnt > HIF_CLIENT_QUEUES_MAX)
++ cnt = HIF_CLIENT_QUEUES_MAX;
++
++ client->rx_qn = cnt;
++ rx_qbase = (struct rx_queue_desc *)client_shm->rx_qbase;
++ for (i = 0; i < cnt; i++) {
++ rx_queue = &client->rx_q[i];
++ rx_queue->base = rx_qbase + i * client_shm->rx_qsize;
++ rx_queue->size = client_shm->rx_qsize;
++ rx_queue->write_idx = 0;
++ }
++
++ /* Initialize client Tx queues baseaddr, size */
++ cnt = CLIENT_CTRL_TX_Q_CNT(client_shm->ctrl);
++
++ /* Check if client is requesting for more queues than supported */
++ if (cnt > HIF_CLIENT_QUEUES_MAX)
++ cnt = HIF_CLIENT_QUEUES_MAX;
++
++ client->tx_qn = cnt;
++ tx_qbase = (struct tx_queue_desc *)client_shm->tx_qbase;
++ for (i = 0; i < cnt; i++) {
++ tx_queue = &client->tx_q[i];
++ tx_queue->base = tx_qbase + i * client_shm->tx_qsize;
++ tx_queue->size = client_shm->tx_qsize;
++ tx_queue->ack_idx = 0;
++ }
++
++ set_bit(client_id, &hif->shm->g_client_status[0]);
++
++unlock:
++ spin_unlock_bh(&hif->tx_lock);
++
++ return err;
++}
++
++/*
++ * pfe_hif_client_unregister
++ *
++ * This function used to unregister a client from the HIF driver.
++ *
++ */
++static void pfe_hif_client_unregister(struct pfe_hif *hif, u32 client_id)
++{
++ pr_info("%s\n", __func__);
++
++ /*
++ * Mark client as no longer available (which prevents further packet
++ * receive for this client)
++ */
++ spin_lock_bh(&hif->tx_lock);
++
++ if (!test_bit(client_id, &hif->shm->g_client_status[0])) {
++ pr_err("%s: client %d not registered\n", __func__,
++ client_id);
++
++ spin_unlock_bh(&hif->tx_lock);
++ return;
++ }
++
++ clear_bit(client_id, &hif->shm->g_client_status[0]);
++
++ spin_unlock_bh(&hif->tx_lock);
++}
++
++/*
++ * client_put_rxpacket-
++ * This functions puts the Rx pkt in the given client Rx queue.
++ * It actually swap the Rx pkt in the client Rx descriptor buffer
++ * and returns the free buffer from it.
++ *
++ * If the function returns NULL means client Rx queue is full and
++ * packet couldn't send to client queue.
++ */
++static void *client_put_rxpacket(struct hif_rx_queue *queue, void *pkt, u32 len,
++ u32 flags, u32 client_ctrl, u32 *rem_len)
++{
++ void *free_pkt = NULL;
++ struct rx_queue_desc *desc = queue->base + queue->write_idx;
++
++ if (readl(&desc->ctrl) & CL_DESC_OWN) {
++ if (page_mode) {
++ int rem_page_size = PAGE_SIZE -
++ PRESENT_OFST_IN_PAGE(pkt);
++ int cur_pkt_size = ROUND_MIN_RX_SIZE(len +
++ pfe_pkt_headroom);
++ *rem_len = (rem_page_size - cur_pkt_size);
++ if (*rem_len) {
++ free_pkt = pkt + cur_pkt_size;
++ get_page(virt_to_page(free_pkt));
++ } else {
++ free_pkt = (void
++ *)__get_free_page(GFP_ATOMIC | GFP_DMA_PFE);
++ *rem_len = pfe_pkt_size;
++ }
++ } else {
++ free_pkt = kmalloc(PFE_BUF_SIZE, GFP_ATOMIC |
++ GFP_DMA_PFE);
++ *rem_len = PFE_BUF_SIZE - pfe_pkt_headroom;
++ }
++
++ if (free_pkt) {
++ desc->data = pkt;
++ desc->client_ctrl = client_ctrl;
++ /*
++ * Ensure everything else is written to DDR before
++ * writing bd->ctrl
++ */
++ smp_wmb();
++ writel(CL_DESC_BUF_LEN(len) | flags, &desc->ctrl);
++ queue->write_idx = (queue->write_idx + 1)
++ & (queue->size - 1);
++
++ free_pkt += pfe_pkt_headroom;
++ }
++ }
++
++ return free_pkt;
++}
++
++/*
++ * pfe_hif_rx_process-
++ * This function does pfe hif rx queue processing.
++ * Dequeue packet from Rx queue and send it to corresponding client queue
++ */
++static int pfe_hif_rx_process(struct pfe_hif *hif, int budget)
++{
++ struct hif_desc *desc;
++ struct hif_hdr *pkt_hdr;
++ struct __hif_hdr hif_hdr;
++ void *free_buf;
++ int rtc, len, rx_processed = 0;
++ struct __hif_desc local_desc;
++ int flags;
++ unsigned int desc_p;
++ unsigned int buf_size = 0;
++
++ spin_lock_bh(&hif->lock);
++
++ rtc = hif->rxtoclean_index;
++
++ while (rx_processed < budget) {
++ desc = hif->rx_base + rtc;
++
++ __memcpy12(&local_desc, desc);
++
++ /* ACK pending Rx interrupt */
++ if (local_desc.ctrl & BD_CTRL_DESC_EN) {
++ writel(HIF_INT | HIF_RXPKT_INT, HIF_INT_SRC);
++
++ if (rx_processed == 0) {
++ if (napi_first_batch == 1) {
++ desc_p = hif->descr_baseaddr_p +
++ ((unsigned long int)(desc) -
++ (unsigned long
++ int)hif->descr_baseaddr_v);
++ napi_first_batch = 0;
++ }
++ }
++
++ __memcpy12(&local_desc, desc);
++
++ if (local_desc.ctrl & BD_CTRL_DESC_EN)
++ break;
++ }
++
++ napi_first_batch = 0;
++
++#ifdef HIF_NAPI_STATS
++ hif->napi_counters[NAPI_DESC_COUNT]++;
++#endif
++ len = BD_BUF_LEN(local_desc.ctrl);
++ /*
++ * dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data),
++ * hif->rx_buf_len[rtc], DMA_FROM_DEVICE);
++ */
++ dma_unmap_single(hif->dev, DDR_PFE_TO_PHYS(local_desc.data),
++ hif->rx_buf_len[rtc], DMA_FROM_DEVICE);
++
++ pkt_hdr = (struct hif_hdr *)hif->rx_buf_addr[rtc];
++
++ /* Track last HIF header received */
++ if (!hif->started) {
++ hif->started = 1;
++
++ __memcpy8(&hif_hdr, pkt_hdr);
++
++ hif->qno = hif_hdr.hdr.q_num;
++ hif->client_id = hif_hdr.hdr.client_id;
++ hif->client_ctrl = (hif_hdr.hdr.client_ctrl1 << 16) |
++ hif_hdr.hdr.client_ctrl;
++ flags = CL_DESC_FIRST;
++
++ } else {
++ flags = 0;
++ }
++
++ if (local_desc.ctrl & BD_CTRL_LIFM)
++ flags |= CL_DESC_LAST;
++
++ /* Check for valid client id and still registered */
++ if ((hif->client_id >= HIF_CLIENTS_MAX) ||
++ !(test_bit(hif->client_id,
++ &hif->shm->g_client_status[0]))) {
++ printk_ratelimited("%s: packet with invalid client id %d q_num %d\n",
++ __func__,
++ hif->client_id,
++ hif->qno);
++
++ free_buf = pkt_hdr;
++
++ goto pkt_drop;
++ }
++
++ /* Check to valid queue number */
++ if (hif->client[hif->client_id].rx_qn <= hif->qno) {
++ pr_info("%s: packet with invalid queue: %d\n"
++ , __func__, hif->qno);
++ hif->qno = 0;
++ }
++
++ free_buf =
++ client_put_rxpacket(&hif->client[hif->client_id].rx_q[hif->qno],
++ (void *)pkt_hdr, len, flags,
++ hif->client_ctrl, &buf_size);
++
++ hif_lib_indicate_client(hif->client_id, EVENT_RX_PKT_IND,
++ hif->qno);
++
++ if (unlikely(!free_buf)) {
++#ifdef HIF_NAPI_STATS
++ hif->napi_counters[NAPI_CLIENT_FULL_COUNT]++;
++#endif
++ /*
++ * If we want to keep in polling mode to retry later,
++ * we need to tell napi that we consumed
++ * the full budget or we will hit a livelock scenario.
++ * The core code keeps this napi instance
++ * at the head of the list and none of the other
++ * instances get to run
++ */
++ rx_processed = budget;
++
++ if (flags & CL_DESC_FIRST)
++ hif->started = 0;
++
++ break;
++ }
++
++pkt_drop:
++ /*Fill free buffer in the descriptor */
++ hif->rx_buf_addr[rtc] = free_buf;
++ hif->rx_buf_len[rtc] = min(pfe_pkt_size, buf_size);
++ writel((DDR_PHYS_TO_PFE
++ ((u32)dma_map_single(hif->dev,
++ free_buf, hif->rx_buf_len[rtc], DMA_FROM_DEVICE))),
++ &desc->data);
++ /*
++ * Ensure everything else is written to DDR before
++ * writing bd->ctrl
++ */
++ wmb();
++ writel((BD_CTRL_PKT_INT_EN | BD_CTRL_LIFM | BD_CTRL_DIR |
++ BD_CTRL_DESC_EN | BD_BUF_LEN(hif->rx_buf_len[rtc])),
++ &desc->ctrl);
++
++ rtc = (rtc + 1) & (hif->rx_ring_size - 1);
++
++ if (local_desc.ctrl & BD_CTRL_LIFM) {
++ if (!(hif->client_ctrl & HIF_CTRL_RX_CONTINUED)) {
++ rx_processed++;
++
++#ifdef HIF_NAPI_STATS
++ hif->napi_counters[NAPI_PACKET_COUNT]++;
++#endif
++ }
++ hif->started = 0;
++ }
++ }
++
++ hif->rxtoclean_index = rtc;
++ spin_unlock_bh(&hif->lock);
++
++ /* we made some progress, re-start rx dma in case it stopped */
++ hif_rx_dma_start();
++
++ return rx_processed;
++}
++
++/*
++ * client_ack_txpacket-
++ * This function ack the Tx packet in the give client Tx queue by resetting
++ * ownership bit in the descriptor.
++ */
++static int client_ack_txpacket(struct pfe_hif *hif, unsigned int client_id,
++ unsigned int q_no)
++{
++ struct hif_tx_queue *queue = &hif->client[client_id].tx_q[q_no];
++ struct tx_queue_desc *desc = queue->base + queue->ack_idx;
++
++ if (readl(&desc->ctrl) & CL_DESC_OWN) {
++ writel((readl(&desc->ctrl) & ~CL_DESC_OWN), &desc->ctrl);
++ queue->ack_idx = (queue->ack_idx + 1) & (queue->size - 1);
++
++ return 0;
++
++ } else {
++ /*This should not happen */
++ pr_err("%s: %d %d %d %d %d %p %d\n", __func__,
++ hif->txtosend, hif->txtoclean, hif->txavail,
++ client_id, q_no, queue, queue->ack_idx);
++ WARN(1, "%s: doesn't own this descriptor", __func__);
++ return 1;
++ }
++}
++
++void __hif_tx_done_process(struct pfe_hif *hif, int count)
++{
++ struct hif_desc *desc;
++ struct hif_desc_sw *desc_sw;
++ int ttc, tx_avl;
++ int pkts_done[HIF_CLIENTS_MAX] = {0, 0};
++
++ ttc = hif->txtoclean;
++ tx_avl = hif->txavail;
++
++ while ((tx_avl < hif->tx_ring_size) && count--) {
++ desc = hif->tx_base + ttc;
++
++ if (readl(&desc->ctrl) & BD_CTRL_DESC_EN)
++ break;
++
++ desc_sw = &hif->tx_sw_queue[ttc];
++
++ if (desc_sw->data) {
++ /*
++ * dmap_unmap_single(hif->dev, desc_sw->data,
++ * desc_sw->len, DMA_TO_DEVICE);
++ */
++ dma_unmap_single(hif->dev, desc_sw->data,
++ desc_sw->len, DMA_TO_DEVICE);
++ }
++
++ if (desc_sw->client_id >= HIF_CLIENTS_MAX) {
++ pr_err("Invalid cl id %d\n", desc_sw->client_id);
++ break;
++ }
++
++ pkts_done[desc_sw->client_id]++;
++
++ client_ack_txpacket(hif, desc_sw->client_id, desc_sw->q_no);
++
++ ttc = (ttc + 1) & (hif->tx_ring_size - 1);
++ tx_avl++;
++ }
++
++ if (pkts_done[0])
++ hif_lib_indicate_client(0, EVENT_TXDONE_IND, 0);
++ if (pkts_done[1])
++ hif_lib_indicate_client(1, EVENT_TXDONE_IND, 0);
++
++ hif->txtoclean = ttc;
++ hif->txavail = tx_avl;
++
++ if (!count) {
++ tasklet_schedule(&hif->tx_cleanup_tasklet);
++ } else {
++ /*Enable Tx done interrupt */
++ writel(readl_relaxed(HIF_INT_ENABLE) | HIF_TXPKT_INT,
++ HIF_INT_ENABLE);
++ }
++}
++
++static void pfe_tx_do_cleanup(unsigned long data)
++{
++ struct pfe_hif *hif = (struct pfe_hif *)data;
++
++ writel(HIF_INT | HIF_TXPKT_INT, HIF_INT_SRC);
++
++ hif_tx_done_process(hif, 64);
++}
++
++/*
++ * __hif_xmit_pkt -
++ * This function puts one packet in the HIF Tx queue
++ */
++void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int
++ q_no, void *data, u32 len, unsigned int flags)
++{
++ struct hif_desc *desc;
++ struct hif_desc_sw *desc_sw;
++
++ desc = hif->tx_base + hif->txtosend;
++ desc_sw = &hif->tx_sw_queue[hif->txtosend];
++
++ desc_sw->len = len;
++ desc_sw->client_id = client_id;
++ desc_sw->q_no = q_no;
++ desc_sw->flags = flags;
++
++ if (flags & HIF_DONT_DMA_MAP) {
++ desc_sw->data = 0;
++ writel((u32)DDR_PHYS_TO_PFE(data), &desc->data);
++ } else {
++ desc_sw->data = dma_map_single(hif->dev, data, len,
++ DMA_TO_DEVICE);
++ writel((u32)DDR_PHYS_TO_PFE(desc_sw->data), &desc->data);
++ }
++
++ hif->txtosend = (hif->txtosend + 1) & (hif->tx_ring_size - 1);
++ hif->txavail--;
++
++ if ((!((flags & HIF_DATA_VALID) && (flags &
++ HIF_LAST_BUFFER))))
++ goto skip_tx;
++
++ /*
++ * Ensure everything else is written to DDR before
++ * writing bd->ctrl
++ */
++ wmb();
++
++ do {
++ desc_sw = &hif->tx_sw_queue[hif->txtoflush];
++ desc = hif->tx_base + hif->txtoflush;
++
++ if (desc_sw->flags & HIF_LAST_BUFFER) {
++ writel((BD_CTRL_LIFM |
++ BD_CTRL_BRFETCH_DISABLE | BD_CTRL_RTFETCH_DISABLE
++ | BD_CTRL_PARSE_DISABLE | BD_CTRL_DESC_EN |
++ BD_CTRL_PKT_INT_EN | BD_BUF_LEN(desc_sw->len)),
++ &desc->ctrl);
++ } else {
++ writel((BD_CTRL_DESC_EN |
++ BD_BUF_LEN(desc_sw->len)), &desc->ctrl);
++ }
++ hif->txtoflush = (hif->txtoflush + 1) & (hif->tx_ring_size - 1);
++ }
++ while (hif->txtoflush != hif->txtosend)
++ ;
++
++skip_tx:
++ return;
++}
++
++static irqreturn_t wol_isr(int irq, void *dev_id)
++{
++ pr_info("WoL\n");
++ gemac_set_wol(EMAC1_BASE_ADDR, 0);
++ gemac_set_wol(EMAC2_BASE_ADDR, 0);
++ return IRQ_HANDLED;
++}
++
++/*
++ * hif_isr-
++ * This ISR routine processes Rx/Tx done interrupts from the HIF hardware block
++ */
++static irqreturn_t hif_isr(int irq, void *dev_id)
++{
++ struct pfe_hif *hif = (struct pfe_hif *)dev_id;
++ int int_status;
++ int int_enable_mask;
++
++ /*Read hif interrupt source register */
++ int_status = readl_relaxed(HIF_INT_SRC);
++ int_enable_mask = readl_relaxed(HIF_INT_ENABLE);
++
++ if ((int_status & HIF_INT) == 0)
++ return IRQ_NONE;
++
++ int_status &= ~(HIF_INT);
++
++ if (int_status & HIF_RXPKT_INT) {
++ int_status &= ~(HIF_RXPKT_INT);
++ int_enable_mask &= ~(HIF_RXPKT_INT);
++
++ napi_first_batch = 1;
++
++ if (napi_schedule_prep(&hif->napi)) {
++#ifdef HIF_NAPI_STATS
++ hif->napi_counters[NAPI_SCHED_COUNT]++;
++#endif
++ __napi_schedule(&hif->napi);
++ }
++ }
++
++ if (int_status & HIF_TXPKT_INT) {
++ int_status &= ~(HIF_TXPKT_INT);
++ int_enable_mask &= ~(HIF_TXPKT_INT);
++ /*Schedule tx cleanup tassklet */
++ tasklet_schedule(&hif->tx_cleanup_tasklet);
++ }
++
++ /*Disable interrupts, they will be enabled after they are serviced */
++ writel_relaxed(int_enable_mask, HIF_INT_ENABLE);
++
++ if (int_status) {
++ pr_info("%s : Invalid interrupt : %d\n", __func__,
++ int_status);
++ writel(int_status, HIF_INT_SRC);
++ }
++
++ return IRQ_HANDLED;
++}
++
++void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int data2)
++{
++ unsigned int client_id = data1;
++
++ if (client_id >= HIF_CLIENTS_MAX) {
++ pr_err("%s: client id %d out of bounds\n", __func__,
++ client_id);
++ return;
++ }
++
++ switch (req) {
++ case REQUEST_CL_REGISTER:
++ /* Request for register a client */
++ pr_info("%s: register client_id %d\n",
++ __func__, client_id);
++ pfe_hif_client_register(hif, client_id, (struct
++ hif_client_shm *)&hif->shm->client[client_id]);
++ break;
++
++ case REQUEST_CL_UNREGISTER:
++ pr_info("%s: unregister client_id %d\n",
++ __func__, client_id);
++
++ /* Request for unregister a client */
++ pfe_hif_client_unregister(hif, client_id);
++
++ break;
++
++ default:
++ pr_err("%s: unsupported request %d\n",
++ __func__, req);
++ break;
++ }
++
++ /*
++ * Process client Tx queues
++ * Currently we don't have checking for tx pending
++ */
++}
++
++/*
++ * pfe_hif_rx_poll
++ * This function is NAPI poll function to process HIF Rx queue.
++ */
++static int pfe_hif_rx_poll(struct napi_struct *napi, int budget)
++{
++ struct pfe_hif *hif = container_of(napi, struct pfe_hif, napi);
++ int work_done;
++
++#ifdef HIF_NAPI_STATS
++ hif->napi_counters[NAPI_POLL_COUNT]++;
++#endif
++
++ work_done = pfe_hif_rx_process(hif, budget);
++
++ if (work_done < budget) {
++ napi_complete(napi);
++ writel(readl_relaxed(HIF_INT_ENABLE) | HIF_RXPKT_INT,
++ HIF_INT_ENABLE);
++ }
++#ifdef HIF_NAPI_STATS
++ else
++ hif->napi_counters[NAPI_FULL_BUDGET_COUNT]++;
++#endif
++
++ return work_done;
++}
++
++/*
++ * pfe_hif_init
++ * This function initializes the baseaddresses and irq, etc.
++ */
++int pfe_hif_init(struct pfe *pfe)
++{
++ struct pfe_hif *hif = &pfe->hif;
++ int err;
++
++ pr_info("%s\n", __func__);
++
++ hif->dev = pfe->dev;
++ hif->irq = pfe->hif_irq;
++
++ err = pfe_hif_alloc_descr(hif);
++ if (err)
++ goto err0;
++
++ if (pfe_hif_init_buffers(hif)) {
++ pr_err("%s: Could not initialize buffer descriptors\n"
++ , __func__);
++ err = -ENOMEM;
++ goto err1;
++ }
++
++ /* Initialize NAPI for Rx processing */
++ init_dummy_netdev(&hif->dummy_dev);
++ netif_napi_add(&hif->dummy_dev, &hif->napi, pfe_hif_rx_poll);
++ napi_enable(&hif->napi);
++
++ spin_lock_init(&hif->tx_lock);
++ spin_lock_init(&hif->lock);
++
++ hif_init();
++ hif_rx_enable();
++ hif_tx_enable();
++
++ /* Disable tx done interrupt */
++ writel(HIF_INT_MASK, HIF_INT_ENABLE);
++
++ gpi_enable(HGPI_BASE_ADDR);
++
++ err = request_irq(hif->irq, hif_isr, 0, "pfe_hif", hif);
++ if (err) {
++ pr_err("%s: failed to get the hif IRQ = %d\n",
++ __func__, hif->irq);
++ goto err1;
++ }
++
++ err = request_irq(pfe->wol_irq, wol_isr, 0, "pfe_wol", pfe);
++ if (err) {
++ pr_err("%s: failed to get the wol IRQ = %d\n",
++ __func__, pfe->wol_irq);
++ goto err1;
++ }
++
++ tasklet_init(&hif->tx_cleanup_tasklet,
++ (void(*)(unsigned long))pfe_tx_do_cleanup,
++ (unsigned long)hif);
++
++ return 0;
++err1:
++ pfe_hif_free_descr(hif);
++err0:
++ return err;
++}
++
++/* pfe_hif_exit- */
++void pfe_hif_exit(struct pfe *pfe)
++{
++ struct pfe_hif *hif = &pfe->hif;
++
++ pr_info("%s\n", __func__);
++
++ tasklet_kill(&hif->tx_cleanup_tasklet);
++
++ spin_lock_bh(&hif->lock);
++ hif->shm->g_client_status[0] = 0;
++ /* Make sure all clients are disabled*/
++ hif->shm->g_client_status[1] = 0;
++
++ spin_unlock_bh(&hif->lock);
++
++ /*Disable Rx/Tx */
++ gpi_disable(HGPI_BASE_ADDR);
++ hif_rx_disable();
++ hif_tx_disable();
++
++ napi_disable(&hif->napi);
++ netif_napi_del(&hif->napi);
++
++ free_irq(pfe->wol_irq, pfe);
++ free_irq(hif->irq, hif);
++
++ pfe_hif_release_buffers(hif);
++ pfe_hif_free_descr(hif);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif.h
+@@ -0,0 +1,199 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_HIF_H_
++#define _PFE_HIF_H_
++
++#include <linux/netdevice.h>
++
++#define HIF_NAPI_STATS
++
++#define HIF_CLIENT_QUEUES_MAX 16
++#define HIF_RX_POLL_WEIGHT 64
++
++#define HIF_RX_PKT_MIN_SIZE 0x800 /* 2KB */
++#define HIF_RX_PKT_MIN_SIZE_MASK ~(HIF_RX_PKT_MIN_SIZE - 1)
++#define ROUND_MIN_RX_SIZE(_sz) (((_sz) + (HIF_RX_PKT_MIN_SIZE - 1)) \
++ & HIF_RX_PKT_MIN_SIZE_MASK)
++#define PRESENT_OFST_IN_PAGE(_buf) (((unsigned long int)(_buf) & (PAGE_SIZE \
++ - 1)) & HIF_RX_PKT_MIN_SIZE_MASK)
++
++enum {
++ NAPI_SCHED_COUNT = 0,
++ NAPI_POLL_COUNT,
++ NAPI_PACKET_COUNT,
++ NAPI_DESC_COUNT,
++ NAPI_FULL_BUDGET_COUNT,
++ NAPI_CLIENT_FULL_COUNT,
++ NAPI_MAX_COUNT
++};
++
++/*
++ * HIF_TX_DESC_NT value should be always greter than 4,
++ * Otherwise HIF_TX_POLL_MARK will become zero.
++ */
++#define HIF_RX_DESC_NT 256
++#define HIF_TX_DESC_NT 2048
++
++#define HIF_FIRST_BUFFER BIT(0)
++#define HIF_LAST_BUFFER BIT(1)
++#define HIF_DONT_DMA_MAP BIT(2)
++#define HIF_DATA_VALID BIT(3)
++#define HIF_TSO BIT(4)
++
++enum {
++ PFE_CL_GEM0 = 0,
++ PFE_CL_GEM1,
++ HIF_CLIENTS_MAX
++};
++
++/*structure to store client queue info */
++struct hif_rx_queue {
++ struct rx_queue_desc *base;
++ u32 size;
++ u32 write_idx;
++};
++
++struct hif_tx_queue {
++ struct tx_queue_desc *base;
++ u32 size;
++ u32 ack_idx;
++};
++
++/*Structure to store the client info */
++struct hif_client {
++ int rx_qn;
++ struct hif_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX];
++ int tx_qn;
++ struct hif_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX];
++};
++
++/*HIF hardware buffer descriptor */
++struct hif_desc {
++ u32 ctrl;
++ u32 status;
++ u32 data;
++ u32 next;
++};
++
++struct __hif_desc {
++ u32 ctrl;
++ u32 status;
++ u32 data;
++};
++
++struct hif_desc_sw {
++ dma_addr_t data;
++ u16 len;
++ u8 client_id;
++ u8 q_no;
++ u16 flags;
++};
++
++struct hif_hdr {
++ u8 client_id;
++ u8 q_num;
++ u16 client_ctrl;
++ u16 client_ctrl1;
++};
++
++struct __hif_hdr {
++ union {
++ struct hif_hdr hdr;
++ u32 word[2];
++ };
++};
++
++struct hif_ipsec_hdr {
++ u16 sa_handle[2];
++} __packed;
++
++/* HIF_CTRL_TX... defines */
++#define HIF_CTRL_TX_CHECKSUM BIT(2)
++
++/* HIF_CTRL_RX... defines */
++#define HIF_CTRL_RX_OFFSET_OFST (24)
++#define HIF_CTRL_RX_CHECKSUMMED BIT(2)
++#define HIF_CTRL_RX_CONTINUED BIT(1)
++
++struct pfe_hif {
++ /* To store registered clients in hif layer */
++ struct hif_client client[HIF_CLIENTS_MAX];
++ struct hif_shm *shm;
++ int irq;
++
++ void *descr_baseaddr_v;
++ unsigned long descr_baseaddr_p;
++
++ struct hif_desc *rx_base;
++ u32 rx_ring_size;
++ u32 rxtoclean_index;
++ void *rx_buf_addr[HIF_RX_DESC_NT];
++ int rx_buf_len[HIF_RX_DESC_NT];
++ unsigned int qno;
++ unsigned int client_id;
++ unsigned int client_ctrl;
++ unsigned int started;
++
++ struct hif_desc *tx_base;
++ u32 tx_ring_size;
++ u32 txtosend;
++ u32 txtoclean;
++ u32 txavail;
++ u32 txtoflush;
++ struct hif_desc_sw tx_sw_queue[HIF_TX_DESC_NT];
++
++/* tx_lock synchronizes hif packet tx as well as pfe_hif structure access */
++ spinlock_t tx_lock;
++/* lock synchronizes hif rx queue processing */
++ spinlock_t lock;
++ struct net_device dummy_dev;
++ struct napi_struct napi;
++ struct device *dev;
++
++#ifdef HIF_NAPI_STATS
++ unsigned int napi_counters[NAPI_MAX_COUNT];
++#endif
++ struct tasklet_struct tx_cleanup_tasklet;
++};
++
++void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int
++ q_no, void *data, u32 len, unsigned int flags);
++int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no,
++ void *data, unsigned int len);
++void __hif_tx_done_process(struct pfe_hif *hif, int count);
++void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int
++ data2);
++int pfe_hif_init(struct pfe *pfe);
++void pfe_hif_exit(struct pfe *pfe);
++void pfe_hif_rx_idle(struct pfe_hif *hif);
++static inline void hif_tx_done_process(struct pfe_hif *hif, int count)
++{
++ spin_lock_bh(&hif->tx_lock);
++ __hif_tx_done_process(hif, count);
++ spin_unlock_bh(&hif->tx_lock);
++}
++
++static inline void hif_tx_lock(struct pfe_hif *hif)
++{
++ spin_lock_bh(&hif->tx_lock);
++}
++
++static inline void hif_tx_unlock(struct pfe_hif *hif)
++{
++ spin_unlock_bh(&hif->tx_lock);
++}
++
++static inline int __hif_tx_avail(struct pfe_hif *hif)
++{
++ return hif->txavail;
++}
++
++#define __memcpy8(dst, src) memcpy(dst, src, 8)
++#define __memcpy12(dst, src) memcpy(dst, src, 12)
++#define __memcpy(dst, src, len) memcpy(dst, src, len)
++
++#endif /* _PFE_HIF_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.c
+@@ -0,0 +1,628 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/version.h>
++#include <linux/kernel.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/workqueue.h>
++#include <linux/dma-mapping.h>
++#include <linux/dmapool.h>
++#include <linux/sched.h>
++#include <linux/skbuff.h>
++#include <linux/moduleparam.h>
++#include <linux/cpu.h>
++
++#include "pfe_mod.h"
++#include "pfe_hif.h"
++#include "pfe_hif_lib.h"
++
++unsigned int lro_mode;
++unsigned int page_mode;
++unsigned int tx_qos = 1;
++module_param(tx_qos, uint, 0444);
++MODULE_PARM_DESC(tx_qos, "0: disable ,\n"
++ "1: enable (default), guarantee no packet drop at TMU level\n");
++unsigned int pfe_pkt_size;
++unsigned int pfe_pkt_headroom;
++unsigned int emac_txq_cnt;
++
++/*
++ * @pfe_hal_lib.c.
++ * Common functions used by HIF client drivers
++ */
++
++/*HIF shared memory Global variable */
++struct hif_shm ghif_shm;
++
++/* Cleanup the HIF shared memory, release HIF rx_buffer_pool.
++ * This function should be called after pfe_hif_exit
++ *
++ * @param[in] hif_shm Shared memory address location in DDR
++ */
++static void pfe_hif_shm_clean(struct hif_shm *hif_shm)
++{
++ int i;
++ void *pkt;
++
++ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {
++ pkt = hif_shm->rx_buf_pool[i];
++ if (pkt) {
++ hif_shm->rx_buf_pool[i] = NULL;
++ pkt -= pfe_pkt_headroom;
++
++ if (page_mode)
++ put_page(virt_to_page(pkt));
++ else
++ kfree(pkt);
++ }
++ }
++}
++
++/* Initialize shared memory used between HIF driver and clients,
++ * allocate rx_buffer_pool required for HIF Rx descriptors.
++ * This function should be called before initializing HIF driver.
++ *
++ * @param[in] hif_shm Shared memory address location in DDR
++ * @rerurn 0 - on succes, <0 on fail to initialize
++ */
++static int pfe_hif_shm_init(struct hif_shm *hif_shm)
++{
++ int i;
++ void *pkt;
++
++ memset(hif_shm, 0, sizeof(struct hif_shm));
++ hif_shm->rx_buf_pool_cnt = HIF_RX_DESC_NT;
++
++ for (i = 0; i < hif_shm->rx_buf_pool_cnt; i++) {
++ if (page_mode) {
++ pkt = (void *)__get_free_page(GFP_KERNEL |
++ GFP_DMA_PFE);
++ } else {
++ pkt = kmalloc(PFE_BUF_SIZE, GFP_KERNEL | GFP_DMA_PFE);
++ }
++
++ if (pkt)
++ hif_shm->rx_buf_pool[i] = pkt + pfe_pkt_headroom;
++ else
++ goto err0;
++ }
++
++ return 0;
++
++err0:
++ pr_err("%s Low memory\n", __func__);
++ pfe_hif_shm_clean(hif_shm);
++ return -ENOMEM;
++}
++
++/*This function sends indication to HIF driver
++ *
++ * @param[in] hif hif context
++ */
++static void hif_lib_indicate_hif(struct pfe_hif *hif, int req, int data1, int
++ data2)
++{
++ hif_process_client_req(hif, req, data1, data2);
++}
++
++void hif_lib_indicate_client(int client_id, int event_type, int qno)
++{
++ struct hif_client_s *client = pfe->hif_client[client_id];
++
++ if (!client || (event_type >= HIF_EVENT_MAX) || (qno >=
++ HIF_CLIENT_QUEUES_MAX))
++ return;
++
++ if (!test_and_set_bit(qno, &client->queue_mask[event_type]))
++ client->event_handler(client->priv, event_type, qno);
++}
++
++/*This function releases Rx queue descriptors memory and pre-filled buffers
++ *
++ * @param[in] client hif_client context
++ */
++static void hif_lib_client_release_rx_buffers(struct hif_client_s *client)
++{
++ struct rx_queue_desc *desc;
++ int qno, ii;
++ void *buf;
++
++ for (qno = 0; qno < client->rx_qn; qno++) {
++ desc = client->rx_q[qno].base;
++
++ for (ii = 0; ii < client->rx_q[qno].size; ii++) {
++ buf = (void *)desc->data;
++ if (buf) {
++ buf -= pfe_pkt_headroom;
++
++ if (page_mode)
++ free_page((unsigned long)buf);
++ else
++ kfree(buf);
++
++ desc->ctrl = 0;
++ }
++
++ desc++;
++ }
++ }
++
++ kfree(client->rx_qbase);
++}
++
++/*This function allocates memory for the rxq descriptors and pre-fill rx queues
++ * with buffers.
++ * @param[in] client client context
++ * @param[in] q_size size of the rxQ, all queues are of same size
++ */
++static int hif_lib_client_init_rx_buffers(struct hif_client_s *client, int
++ q_size)
++{
++ struct rx_queue_desc *desc;
++ struct hif_client_rx_queue *queue;
++ int ii, qno;
++
++ /*Allocate memory for the client queues */
++ client->rx_qbase = kzalloc(client->rx_qn * q_size * sizeof(struct
++ rx_queue_desc), GFP_KERNEL);
++ if (!client->rx_qbase)
++ goto err;
++
++ for (qno = 0; qno < client->rx_qn; qno++) {
++ queue = &client->rx_q[qno];
++
++ queue->base = client->rx_qbase + qno * q_size * sizeof(struct
++ rx_queue_desc);
++ queue->size = q_size;
++ queue->read_idx = 0;
++ queue->write_idx = 0;
++
++ pr_debug("rx queue: %d, base: %p, size: %d\n", qno,
++ queue->base, queue->size);
++ }
++
++ for (qno = 0; qno < client->rx_qn; qno++) {
++ queue = &client->rx_q[qno];
++ desc = queue->base;
++
++ for (ii = 0; ii < queue->size; ii++) {
++ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) |
++ CL_DESC_OWN;
++ desc++;
++ }
++ }
++
++ return 0;
++
++err:
++ return 1;
++}
++
++
++static void hif_lib_client_cleanup_tx_queue(struct hif_client_tx_queue *queue)
++{
++ pr_debug("%s\n", __func__);
++
++ /*
++ * Check if there are any pending packets. Client must flush the tx
++ * queues before unregistering, by calling by calling
++ * hif_lib_tx_get_next_complete()
++ *
++ * Hif no longer calls since we are no longer registered
++ */
++ if (queue->tx_pending)
++ pr_err("%s: pending transmit packets\n", __func__);
++}
++
++static void hif_lib_client_release_tx_buffers(struct hif_client_s *client)
++{
++ int qno;
++
++ pr_debug("%s\n", __func__);
++
++ for (qno = 0; qno < client->tx_qn; qno++)
++ hif_lib_client_cleanup_tx_queue(&client->tx_q[qno]);
++
++ kfree(client->tx_qbase);
++}
++
++static int hif_lib_client_init_tx_buffers(struct hif_client_s *client, int
++ q_size)
++{
++ struct hif_client_tx_queue *queue;
++ int qno;
++
++ client->tx_qbase = kzalloc(client->tx_qn * q_size * sizeof(struct
++ tx_queue_desc), GFP_KERNEL);
++ if (!client->tx_qbase)
++ return 1;
++
++ for (qno = 0; qno < client->tx_qn; qno++) {
++ queue = &client->tx_q[qno];
++
++ queue->base = client->tx_qbase + qno * q_size * sizeof(struct
++ tx_queue_desc);
++ queue->size = q_size;
++ queue->read_idx = 0;
++ queue->write_idx = 0;
++ queue->tx_pending = 0;
++ queue->nocpy_flag = 0;
++ queue->prev_tmu_tx_pkts = 0;
++ queue->done_tmu_tx_pkts = 0;
++
++ pr_debug("tx queue: %d, base: %p, size: %d\n", qno,
++ queue->base, queue->size);
++ }
++
++ return 0;
++}
++
++static int hif_lib_event_dummy(void *priv, int event_type, int qno)
++{
++ return 0;
++}
++
++int hif_lib_client_register(struct hif_client_s *client)
++{
++ struct hif_shm *hif_shm;
++ struct hif_client_shm *client_shm;
++ int err, i;
++ /* int loop_cnt = 0; */
++
++ pr_debug("%s\n", __func__);
++
++ /*Allocate memory before spin_lock*/
++ if (hif_lib_client_init_rx_buffers(client, client->rx_qsize)) {
++ err = -ENOMEM;
++ goto err_rx;
++ }
++
++ if (hif_lib_client_init_tx_buffers(client, client->tx_qsize)) {
++ err = -ENOMEM;
++ goto err_tx;
++ }
++
++ spin_lock_bh(&pfe->hif.lock);
++ if (!(client->pfe) || (client->id >= HIF_CLIENTS_MAX) ||
++ (pfe->hif_client[client->id])) {
++ err = -EINVAL;
++ goto err;
++ }
++
++ hif_shm = client->pfe->hif.shm;
++
++ if (!client->event_handler)
++ client->event_handler = hif_lib_event_dummy;
++
++ /*Initialize client specific shared memory */
++ client_shm = (struct hif_client_shm *)&hif_shm->client[client->id];
++ client_shm->rx_qbase = (unsigned long int)client->rx_qbase;
++ client_shm->rx_qsize = client->rx_qsize;
++ client_shm->tx_qbase = (unsigned long int)client->tx_qbase;
++ client_shm->tx_qsize = client->tx_qsize;
++ client_shm->ctrl = (client->tx_qn << CLIENT_CTRL_TX_Q_CNT_OFST) |
++ (client->rx_qn << CLIENT_CTRL_RX_Q_CNT_OFST);
++ /* spin_lock_init(&client->rx_lock); */
++
++ for (i = 0; i < HIF_EVENT_MAX; i++) {
++ client->queue_mask[i] = 0; /*
++ * By default all events are
++ * unmasked
++ */
++ }
++
++ /*Indicate to HIF driver*/
++ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_REGISTER, client->id, 0);
++
++ pr_debug("%s: client: %p, client_id: %d, tx_qsize: %d, rx_qsize: %d\n",
++ __func__, client, client->id, client->tx_qsize,
++ client->rx_qsize);
++
++ client->cpu_id = -1;
++
++ pfe->hif_client[client->id] = client;
++ spin_unlock_bh(&pfe->hif.lock);
++
++ return 0;
++
++err:
++ spin_unlock_bh(&pfe->hif.lock);
++ hif_lib_client_release_tx_buffers(client);
++
++err_tx:
++ hif_lib_client_release_rx_buffers(client);
++
++err_rx:
++ return err;
++}
++
++int hif_lib_client_unregister(struct hif_client_s *client)
++{
++ struct pfe *pfe = client->pfe;
++ u32 client_id = client->id;
++
++ pr_info(
++ "%s : client: %p, client_id: %d, txQ_depth: %d, rxQ_depth: %d\n"
++ , __func__, client, client->id, client->tx_qsize,
++ client->rx_qsize);
++
++ spin_lock_bh(&pfe->hif.lock);
++ hif_lib_indicate_hif(&pfe->hif, REQUEST_CL_UNREGISTER, client->id, 0);
++
++ hif_lib_client_release_tx_buffers(client);
++ hif_lib_client_release_rx_buffers(client);
++ pfe->hif_client[client_id] = NULL;
++ spin_unlock_bh(&pfe->hif.lock);
++
++ return 0;
++}
++
++int hif_lib_event_handler_start(struct hif_client_s *client, int event,
++ int qno)
++{
++ struct hif_client_rx_queue *queue = &client->rx_q[qno];
++ struct rx_queue_desc *desc = queue->base + queue->read_idx;
++
++ if ((event >= HIF_EVENT_MAX) || (qno >= HIF_CLIENT_QUEUES_MAX)) {
++ pr_debug("%s: Unsupported event : %d queue number : %d\n",
++ __func__, event, qno);
++ return -1;
++ }
++
++ test_and_clear_bit(qno, &client->queue_mask[event]);
++
++ switch (event) {
++ case EVENT_RX_PKT_IND:
++ if (!(desc->ctrl & CL_DESC_OWN))
++ hif_lib_indicate_client(client->id,
++ EVENT_RX_PKT_IND, qno);
++ break;
++
++ case EVENT_HIGH_RX_WM:
++ case EVENT_TXDONE_IND:
++ default:
++ break;
++ }
++
++ return 0;
++}
++
++/*
++ * This function gets one packet from the specified client queue
++ * It also refill the rx buffer
++ */
++void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int
++ *ofst, unsigned int *rx_ctrl,
++ unsigned int *desc_ctrl, void **priv_data)
++{
++ struct hif_client_rx_queue *queue = &client->rx_q[qno];
++ struct rx_queue_desc *desc;
++ void *pkt = NULL;
++
++ /*
++ * Following lock is to protect rx queue access from,
++ * hif_lib_event_handler_start.
++ * In general below lock is not required, because hif_lib_xmit_pkt and
++ * hif_lib_event_handler_start are called from napi poll and which is
++ * not re-entrant. But if some client use in different way this lock is
++ * required.
++ */
++ /*spin_lock_irqsave(&client->rx_lock, flags); */
++ desc = queue->base + queue->read_idx;
++ if (!(desc->ctrl & CL_DESC_OWN)) {
++ pkt = desc->data - pfe_pkt_headroom;
++
++ *rx_ctrl = desc->client_ctrl;
++ *desc_ctrl = desc->ctrl;
++
++ if (desc->ctrl & CL_DESC_FIRST) {
++ u16 size = *rx_ctrl >> HIF_CTRL_RX_OFFSET_OFST;
++
++ if (size) {
++ size += PFE_PARSE_INFO_SIZE;
++ *len = CL_DESC_BUF_LEN(desc->ctrl) -
++ PFE_PKT_HEADER_SZ - size;
++ *ofst = pfe_pkt_headroom + PFE_PKT_HEADER_SZ
++ + size;
++ *priv_data = desc->data + PFE_PKT_HEADER_SZ;
++ } else {
++ *len = CL_DESC_BUF_LEN(desc->ctrl) -
++ PFE_PKT_HEADER_SZ - PFE_PARSE_INFO_SIZE;
++ *ofst = pfe_pkt_headroom
++ + PFE_PKT_HEADER_SZ
++ + PFE_PARSE_INFO_SIZE;
++ *priv_data = NULL;
++ }
++
++ } else {
++ *len = CL_DESC_BUF_LEN(desc->ctrl);
++ *ofst = pfe_pkt_headroom;
++ }
++
++ /*
++ * Needed so we don't free a buffer/page
++ * twice on module_exit
++ */
++ desc->data = NULL;
++
++ /*
++ * Ensure everything else is written to DDR before
++ * writing bd->ctrl
++ */
++ smp_wmb();
++
++ desc->ctrl = CL_DESC_BUF_LEN(pfe_pkt_size) | CL_DESC_OWN;
++ queue->read_idx = (queue->read_idx + 1) & (queue->size - 1);
++ }
++
++ /*spin_unlock_irqrestore(&client->rx_lock, flags); */
++ return pkt;
++}
++
++static inline void hif_hdr_write(struct hif_hdr *pkt_hdr, unsigned int
++ client_id, unsigned int qno,
++ u32 client_ctrl)
++{
++ /* Optimize the write since the destinaton may be non-cacheable */
++ if (!((unsigned long)pkt_hdr & 0x3)) {
++ ((u32 *)pkt_hdr)[0] = (client_ctrl << 16) | (qno << 8) |
++ client_id;
++ } else {
++ ((u16 *)pkt_hdr)[0] = (qno << 8) | (client_id & 0xFF);
++ ((u16 *)pkt_hdr)[1] = (client_ctrl & 0xFFFF);
++ }
++}
++
++/*This function puts the given packet in the specific client queue */
++void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void
++ *data, unsigned int len, u32 client_ctrl,
++ unsigned int flags, void *client_data)
++{
++ struct hif_client_tx_queue *queue = &client->tx_q[qno];
++ struct tx_queue_desc *desc = queue->base + queue->write_idx;
++
++ /* First buffer */
++ if (flags & HIF_FIRST_BUFFER) {
++ data -= sizeof(struct hif_hdr);
++ len += sizeof(struct hif_hdr);
++
++ hif_hdr_write(data, client->id, qno, client_ctrl);
++ }
++
++ desc->data = client_data;
++ desc->ctrl = CL_DESC_OWN | CL_DESC_FLAGS(flags);
++
++ __hif_xmit_pkt(&pfe->hif, client->id, qno, data, len, flags);
++
++ queue->write_idx = (queue->write_idx + 1) & (queue->size - 1);
++ queue->tx_pending++;
++ queue->jiffies_last_packet = jiffies;
++}
++
++void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno,
++ unsigned int *flags, int count)
++{
++ struct hif_client_tx_queue *queue = &client->tx_q[qno];
++ struct tx_queue_desc *desc = queue->base + queue->read_idx;
++
++ pr_debug("%s: qno : %d rd_indx: %d pending:%d\n", __func__, qno,
++ queue->read_idx, queue->tx_pending);
++
++ if (!queue->tx_pending)
++ return NULL;
++
++ if (queue->nocpy_flag && !queue->done_tmu_tx_pkts) {
++ u32 tmu_tx_pkts = be32_to_cpu(pe_dmem_read(TMU0_ID +
++ client->id, TMU_DM_TX_TRANS, 4));
++
++ if (queue->prev_tmu_tx_pkts > tmu_tx_pkts)
++ queue->done_tmu_tx_pkts = UINT_MAX -
++ queue->prev_tmu_tx_pkts + tmu_tx_pkts;
++ else
++ queue->done_tmu_tx_pkts = tmu_tx_pkts -
++ queue->prev_tmu_tx_pkts;
++
++ queue->prev_tmu_tx_pkts = tmu_tx_pkts;
++
++ if (!queue->done_tmu_tx_pkts)
++ return NULL;
++ }
++
++ if (desc->ctrl & CL_DESC_OWN)
++ return NULL;
++
++ queue->read_idx = (queue->read_idx + 1) & (queue->size - 1);
++ queue->tx_pending--;
++
++ *flags = CL_DESC_GET_FLAGS(desc->ctrl);
++
++ if (queue->done_tmu_tx_pkts && (*flags & HIF_LAST_BUFFER))
++ queue->done_tmu_tx_pkts--;
++
++ return desc->data;
++}
++
++static void hif_lib_tmu_credit_init(struct pfe *pfe)
++{
++ int i, q;
++
++ for (i = 0; i < NUM_GEMAC_SUPPORT; i++)
++ for (q = 0; q < emac_txq_cnt; q++) {
++ pfe->tmu_credit.tx_credit_max[i][q] = (q == 0) ?
++ DEFAULT_Q0_QDEPTH : DEFAULT_MAX_QDEPTH;
++ pfe->tmu_credit.tx_credit[i][q] =
++ pfe->tmu_credit.tx_credit_max[i][q];
++ }
++}
++
++/* __hif_lib_update_credit
++ *
++ * @param[in] client hif client context
++ * @param[in] queue queue number in match with TMU
++ */
++void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue)
++{
++ unsigned int tmu_tx_packets, tmp;
++
++ if (tx_qos) {
++ tmu_tx_packets = be32_to_cpu(pe_dmem_read(TMU0_ID +
++ client->id, (TMU_DM_TX_TRANS + (queue * 4)), 4));
++
++ /* tx_packets counter overflowed */
++ if (tmu_tx_packets >
++ pfe->tmu_credit.tx_packets[client->id][queue]) {
++ tmp = UINT_MAX - tmu_tx_packets +
++ pfe->tmu_credit.tx_packets[client->id][queue];
++
++ pfe->tmu_credit.tx_credit[client->id][queue] =
++ pfe->tmu_credit.tx_credit_max[client->id][queue] - tmp;
++ } else {
++ /* TMU tx <= pfe_eth tx, normal case or both OF since
++ * last time
++ */
++ pfe->tmu_credit.tx_credit[client->id][queue] =
++ pfe->tmu_credit.tx_credit_max[client->id][queue] -
++ (pfe->tmu_credit.tx_packets[client->id][queue] -
++ tmu_tx_packets);
++ }
++ }
++}
++
++int pfe_hif_lib_init(struct pfe *pfe)
++{
++ int rc;
++
++ pr_info("%s\n", __func__);
++
++ if (lro_mode) {
++ page_mode = 1;
++ pfe_pkt_size = min(PAGE_SIZE, MAX_PFE_PKT_SIZE);
++ pfe_pkt_headroom = 0;
++ } else {
++ page_mode = 0;
++ pfe_pkt_size = PFE_PKT_SIZE;
++ pfe_pkt_headroom = PFE_PKT_HEADROOM;
++ }
++
++ if (tx_qos)
++ emac_txq_cnt = EMAC_TXQ_CNT / 2;
++ else
++ emac_txq_cnt = EMAC_TXQ_CNT;
++
++ hif_lib_tmu_credit_init(pfe);
++ pfe->hif.shm = &ghif_shm;
++ rc = pfe_hif_shm_init(pfe->hif.shm);
++
++ return rc;
++}
++
++void pfe_hif_lib_exit(struct pfe *pfe)
++{
++ pr_info("%s\n", __func__);
++
++ pfe_hif_shm_clean(pfe->hif.shm);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h
+@@ -0,0 +1,229 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_HIF_LIB_H_
++#define _PFE_HIF_LIB_H_
++
++#include "pfe_hif.h"
++
++#define HIF_CL_REQ_TIMEOUT 10
++#define GFP_DMA_PFE 0
++#define PFE_PARSE_INFO_SIZE 16
++
++enum {
++ REQUEST_CL_REGISTER = 0,
++ REQUEST_CL_UNREGISTER,
++ HIF_REQUEST_MAX
++};
++
++enum {
++ /* Event to indicate that client rx queue is reached water mark level */
++ EVENT_HIGH_RX_WM = 0,
++ /* Event to indicate that, packet received for client */
++ EVENT_RX_PKT_IND,
++ /* Event to indicate that, packet tx done for client */
++ EVENT_TXDONE_IND,
++ HIF_EVENT_MAX
++};
++
++/*structure to store client queue info */
++
++/*structure to store client queue info */
++struct hif_client_rx_queue {
++ struct rx_queue_desc *base;
++ u32 size;
++ u32 read_idx;
++ u32 write_idx;
++};
++
++struct hif_client_tx_queue {
++ struct tx_queue_desc *base;
++ u32 size;
++ u32 read_idx;
++ u32 write_idx;
++ u32 tx_pending;
++ unsigned long jiffies_last_packet;
++ u32 nocpy_flag;
++ u32 prev_tmu_tx_pkts;
++ u32 done_tmu_tx_pkts;
++};
++
++struct hif_client_s {
++ int id;
++ int tx_qn;
++ int rx_qn;
++ void *rx_qbase;
++ void *tx_qbase;
++ int tx_qsize;
++ int rx_qsize;
++ int cpu_id;
++ struct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX];
++ struct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX];
++ int (*event_handler)(void *priv, int event, int data);
++ unsigned long queue_mask[HIF_EVENT_MAX];
++ struct pfe *pfe;
++ void *priv;
++};
++
++/*
++ * Client specific shared memory
++ * It contains number of Rx/Tx queues, base addresses and queue sizes
++ */
++struct hif_client_shm {
++ u32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */
++ unsigned long rx_qbase; /*Rx queue base address */
++ u32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */
++ unsigned long tx_qbase; /* Tx queue base address */
++ u32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */
++};
++
++/*Client shared memory ctrl bit description */
++#define CLIENT_CTRL_RX_Q_CNT_OFST 0
++#define CLIENT_CTRL_TX_Q_CNT_OFST 8
++#define CLIENT_CTRL_RX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) \
++ & 0xFF)
++#define CLIENT_CTRL_TX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) \
++ & 0xFF)
++
++/*
++ * Shared memory used to communicate between HIF driver and host/client drivers
++ * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be
++ * initialized with host buffers and buffers count in the pool.
++ * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT.
++ *
++ */
++struct hif_shm {
++ u32 rx_buf_pool_cnt; /*Number of rx buffers available*/
++ /*Rx buffers required to initialize HIF rx descriptors */
++ void *rx_buf_pool[HIF_RX_DESC_NT];
++ unsigned long g_client_status[2]; /*Global client status bit mask */
++ /* Client specific shared memory */
++ struct hif_client_shm client[HIF_CLIENTS_MAX];
++};
++
++#define CL_DESC_OWN BIT(31)
++/* This sets owner ship to HIF driver */
++#define CL_DESC_LAST BIT(30)
++/* This indicates last packet for multi buffers handling */
++#define CL_DESC_FIRST BIT(29)
++/* This indicates first packet for multi buffers handling */
++
++#define CL_DESC_BUF_LEN(x) ((x) & 0xFFFF)
++#define CL_DESC_FLAGS(x) (((x) & 0xF) << 16)
++#define CL_DESC_GET_FLAGS(x) (((x) >> 16) & 0xF)
++
++struct rx_queue_desc {
++ void *data;
++ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
++ u32 client_ctrl;
++};
++
++struct tx_queue_desc {
++ void *data;
++ u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
++};
++
++/* HIF Rx is not working properly for 2-byte aligned buffers and
++ * ip_header should be 4byte aligned for better iperformance.
++ * "ip_header = 64 + 6(hif_header) + 14 (MAC Header)" will be 4byte aligned.
++ */
++#define PFE_PKT_HEADER_SZ sizeof(struct hif_hdr)
++/* must be big enough for headroom, pkt size and skb shared info */
++#define PFE_BUF_SIZE 2048
++#define PFE_PKT_HEADROOM 128
++
++#define SKB_SHARED_INFO_SIZE SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
++#define PFE_PKT_SIZE (PFE_BUF_SIZE - PFE_PKT_HEADROOM \
++ - SKB_SHARED_INFO_SIZE)
++#define MAX_L2_HDR_SIZE 14 /* Not correct for VLAN/PPPoE */
++#define MAX_L3_HDR_SIZE 20 /* Not correct for IPv6 */
++#define MAX_L4_HDR_SIZE 60 /* TCP with maximum options */
++#define MAX_HDR_SIZE (MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE \
++ + MAX_L4_HDR_SIZE)
++/* Used in page mode to clamp packet size to the maximum supported by the hif
++ *hw interface (<16KiB)
++ */
++#define MAX_PFE_PKT_SIZE 16380UL
++
++extern unsigned int pfe_pkt_size;
++extern unsigned int pfe_pkt_headroom;
++extern unsigned int page_mode;
++extern unsigned int lro_mode;
++extern unsigned int tx_qos;
++extern unsigned int emac_txq_cnt;
++
++int pfe_hif_lib_init(struct pfe *pfe);
++void pfe_hif_lib_exit(struct pfe *pfe);
++int hif_lib_client_register(struct hif_client_s *client);
++int hif_lib_client_unregister(struct hif_client_s *client);
++void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void
++ *data, unsigned int len, u32 client_ctrl,
++ unsigned int flags, void *client_data);
++int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data,
++ unsigned int len, u32 client_ctrl, void *client_data);
++void hif_lib_indicate_client(int cl_id, int event, int data);
++int hif_lib_event_handler_start(struct hif_client_s *client, int event, int
++ data);
++int hif_lib_tmu_queue_start(struct hif_client_s *client, int qno);
++int hif_lib_tmu_queue_stop(struct hif_client_s *client, int qno);
++void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno,
++ unsigned int *flags, int count);
++void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int
++ *ofst, unsigned int *rx_ctrl,
++ unsigned int *desc_ctrl, void **priv_data);
++void __hif_lib_update_credit(struct hif_client_s *client, unsigned int queue);
++void hif_lib_set_rx_cpu_affinity(struct hif_client_s *client, int cpu_id);
++void hif_lib_set_tx_queue_nocpy(struct hif_client_s *client, int qno, int
++ enable);
++static inline int hif_lib_tx_avail(struct hif_client_s *client, unsigned int
++ qno)
++{
++ struct hif_client_tx_queue *queue = &client->tx_q[qno];
++
++ return (queue->size - queue->tx_pending);
++}
++
++static inline int hif_lib_get_tx_wr_index(struct hif_client_s *client, unsigned
++ int qno)
++{
++ struct hif_client_tx_queue *queue = &client->tx_q[qno];
++
++ return queue->write_idx;
++}
++
++static inline int hif_lib_tx_pending(struct hif_client_s *client, unsigned int
++ qno)
++{
++ struct hif_client_tx_queue *queue = &client->tx_q[qno];
++
++ return queue->tx_pending;
++}
++
++#define hif_lib_tx_credit_avail(pfe, id, qno) \
++ ((pfe)->tmu_credit.tx_credit[id][qno])
++
++#define hif_lib_tx_credit_max(pfe, id, qno) \
++ ((pfe)->tmu_credit.tx_credit_max[id][qno])
++
++/*
++ * Test comment
++ */
++#define hif_lib_tx_credit_use(pfe, id, qno, credit) \
++ ({ typeof(pfe) pfe_ = pfe; \
++ typeof(id) id_ = id; \
++ typeof(qno) qno_ = qno; \
++ typeof(credit) credit_ = credit; \
++ do { \
++ if (tx_qos) { \
++ (pfe_)->tmu_credit.tx_credit[id_][qno_]\
++ -= credit_; \
++ (pfe_)->tmu_credit.tx_packets[id_][qno_]\
++ += credit_; \
++ } \
++ } while (0); \
++ })
++
++#endif /* _PFE_HIF_LIB_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hw.c
+@@ -0,0 +1,164 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include "pfe_mod.h"
++#include "pfe_hw.h"
++
++/* Functions to handle most of pfe hw register initialization */
++int pfe_hw_init(struct pfe *pfe, int resume)
++{
++ struct class_cfg class_cfg = {
++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
++ .route_table_baseaddr = pfe->ddr_phys_baseaddr +
++ ROUTE_TABLE_BASEADDR,
++ .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
++ };
++
++ struct tmu_cfg tmu_cfg = {
++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
++ .llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR,
++ .llm_queue_len = TMU_LLM_QUEUE_LEN,
++ };
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ struct util_cfg util_cfg = {
++ .pe_sys_clk_ratio = PE_SYS_CLK_RATIO,
++ };
++#endif
++
++ struct BMU_CFG bmu1_cfg = {
++ .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR +
++ BMU1_LMEM_BASEADDR),
++ .count = BMU1_BUF_COUNT,
++ .size = BMU1_BUF_SIZE,
++ .low_watermark = 10,
++ .high_watermark = 15,
++ };
++
++ struct BMU_CFG bmu2_cfg = {
++ .baseaddr = DDR_PHYS_TO_PFE(pfe->ddr_phys_baseaddr +
++ BMU2_DDR_BASEADDR),
++ .count = BMU2_BUF_COUNT,
++ .size = BMU2_BUF_SIZE,
++ .low_watermark = 250,
++ .high_watermark = 253,
++ };
++
++ struct gpi_cfg egpi1_cfg = {
++ .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
++ .tmlf_txthres = EGPI1_TMLF_TXTHRES,
++ .aseq_len = EGPI1_ASEQ_LEN,
++ .mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC1_BASE_ADDR +
++ EMAC_TCNTRL_REG),
++ };
++
++ struct gpi_cfg egpi2_cfg = {
++ .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
++ .tmlf_txthres = EGPI2_TMLF_TXTHRES,
++ .aseq_len = EGPI2_ASEQ_LEN,
++ .mtip_pause_reg = CBUS_VIRT_TO_PFE(EMAC2_BASE_ADDR +
++ EMAC_TCNTRL_REG),
++ };
++
++ struct gpi_cfg hgpi_cfg = {
++ .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
++ .tmlf_txthres = HGPI_TMLF_TXTHRES,
++ .aseq_len = HGPI_ASEQ_LEN,
++ .mtip_pause_reg = 0,
++ };
++
++ pr_info("%s\n", __func__);
++
++#if !defined(LS1012A_PFE_RESET_WA)
++ /* LS1012A needs this to make PE work correctly */
++ writel(0x3, CLASS_PE_SYS_CLK_RATIO);
++ writel(0x3, TMU_PE_SYS_CLK_RATIO);
++ writel(0x3, UTIL_PE_SYS_CLK_RATIO);
++ usleep_range(10, 20);
++#endif
++
++ pr_info("CLASS version: %x\n", readl(CLASS_VERSION));
++ pr_info("TMU version: %x\n", readl(TMU_VERSION));
++
++ pr_info("BMU1 version: %x\n", readl(BMU1_BASE_ADDR +
++ BMU_VERSION));
++ pr_info("BMU2 version: %x\n", readl(BMU2_BASE_ADDR +
++ BMU_VERSION));
++
++ pr_info("EGPI1 version: %x\n", readl(EGPI1_BASE_ADDR +
++ GPI_VERSION));
++ pr_info("EGPI2 version: %x\n", readl(EGPI2_BASE_ADDR +
++ GPI_VERSION));
++ pr_info("HGPI version: %x\n", readl(HGPI_BASE_ADDR +
++ GPI_VERSION));
++
++ pr_info("HIF version: %x\n", readl(HIF_VERSION));
++ pr_info("HIF NOPCY version: %x\n", readl(HIF_NOCPY_VERSION));
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ pr_info("UTIL version: %x\n", readl(UTIL_VERSION));
++#endif
++ while (!(readl(TMU_CTRL) & ECC_MEM_INIT_DONE))
++ ;
++
++ hif_rx_disable();
++ hif_tx_disable();
++
++ bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
++
++ pr_info("bmu_init(1) done\n");
++
++ bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
++
++ pr_info("bmu_init(2) done\n");
++
++ class_cfg.resume = resume ? 1 : 0;
++
++ class_init(&class_cfg);
++
++ pr_info("class_init() done\n");
++
++ tmu_init(&tmu_cfg);
++
++ pr_info("tmu_init() done\n");
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ util_init(&util_cfg);
++
++ pr_info("util_init() done\n");
++#endif
++ gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
++
++ pr_info("gpi_init(1) done\n");
++
++ gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
++
++ pr_info("gpi_init(2) done\n");
++
++ gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
++
++ pr_info("gpi_init(hif) done\n");
++
++ bmu_enable(BMU1_BASE_ADDR);
++
++ pr_info("bmu_enable(1) done\n");
++
++ bmu_enable(BMU2_BASE_ADDR);
++
++ pr_info("bmu_enable(2) done\n");
++
++ return 0;
++}
++
++void pfe_hw_exit(struct pfe *pfe)
++{
++ pr_info("%s\n", __func__);
++
++ bmu_disable(BMU1_BASE_ADDR);
++ bmu_reset(BMU1_BASE_ADDR);
++
++ bmu_disable(BMU2_BASE_ADDR);
++ bmu_reset(BMU2_BASE_ADDR);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_hw.h
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_HW_H_
++#define _PFE_HW_H_
++
++#define PE_SYS_CLK_RATIO 1 /* SYS/AXI = 250MHz, HFE = 500MHz */
++
++int pfe_hw_init(struct pfe *pfe, int resume);
++void pfe_hw_exit(struct pfe *pfe);
++
++#endif /* _PFE_HW_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_ls1012a_platform.c
+@@ -0,0 +1,383 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/of.h>
++#include <linux/of_net.h>
++#include <linux/of_address.h>
++#include <linux/of_mdio.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/clk.h>
++#include <linux/mfd/syscon.h>
++#include <linux/regmap.h>
++
++#include "pfe_mod.h"
++
++extern bool pfe_use_old_dts_phy;
++struct ls1012a_pfe_platform_data pfe_platform_data;
++
++static int pfe_get_gemac_if_properties(struct device_node *gem,
++ int port,
++ struct ls1012a_pfe_platform_data *pdata)
++{
++ struct device_node *phy_node = NULL;
++ int size;
++ int phy_id = 0;
++ const u32 *addr;
++ int err;
++
++ addr = of_get_property(gem, "reg", &size);
++ if (addr)
++ port = be32_to_cpup(addr);
++ else
++ goto err;
++
++ pdata->ls1012a_eth_pdata[port].gem_id = port;
++
++ err = of_get_mac_address(gem, pdata->ls1012a_eth_pdata[port].mac_addr);
++
++ phy_node = of_parse_phandle(gem, "phy-handle", 0);
++ pdata->ls1012a_eth_pdata[port].phy_node = phy_node;
++ if (phy_node) {
++ pfe_use_old_dts_phy = false;
++ goto process_phynode;
++ } else if (of_phy_is_fixed_link(gem)) {
++ pfe_use_old_dts_phy = false;
++ if (of_phy_register_fixed_link(gem) < 0) {
++ pr_err("broken fixed-link specification\n");
++ goto err;
++ }
++ phy_node = of_node_get(gem);
++ pdata->ls1012a_eth_pdata[port].phy_node = phy_node;
++ } else if (of_get_property(gem, "fsl,pfe-phy-if-flags", &size)) {
++ pfe_use_old_dts_phy = true;
++ /* Use old dts properties for phy handling */
++ addr = of_get_property(gem, "fsl,pfe-phy-if-flags", &size);
++ pdata->ls1012a_eth_pdata[port].phy_flags = be32_to_cpup(addr);
++
++ addr = of_get_property(gem, "fsl,gemac-phy-id", &size);
++ if (!addr) {
++ pr_err("%s:%d Invalid gemac-phy-id....\n", __func__,
++ __LINE__);
++ } else {
++ phy_id = be32_to_cpup(addr);
++ pdata->ls1012a_eth_pdata[port].phy_id = phy_id;
++ pdata->ls1012a_mdio_pdata[0].phy_mask &= ~(1 << phy_id);
++ }
++
++ /* If PHY is enabled, read mdio properties */
++ if (pdata->ls1012a_eth_pdata[port].phy_flags & GEMAC_NO_PHY)
++ goto done;
++
++ } else {
++ pr_info("%s: No PHY or fixed-link\n", __func__);
++ return 0;
++ }
++
++process_phynode:
++ err = of_get_phy_mode(gem, &pdata->ls1012a_eth_pdata[port].mii_config);
++ if (err)
++ pr_err("%s:%d Incorrect Phy mode....\n", __func__,
++ __LINE__);
++
++ addr = of_get_property(gem, "fsl,mdio-mux-val", &size);
++ if (!addr) {
++ pr_err("%s: Invalid mdio-mux-val....\n", __func__);
++ } else {
++ phy_id = be32_to_cpup(addr);
++ pdata->ls1012a_eth_pdata[port].mdio_muxval = phy_id;
++ }
++
++ if (pdata->ls1012a_eth_pdata[port].phy_id < 32)
++ pfe->mdio_muxval[pdata->ls1012a_eth_pdata[port].phy_id] =
++ pdata->ls1012a_eth_pdata[port].mdio_muxval;
++
++
++ pdata->ls1012a_mdio_pdata[port].irq[0] = PHY_POLL;
++
++done:
++ return 0;
++
++err:
++ return -1;
++}
++
++/*
++ *
++ * pfe_platform_probe -
++ *
++ *
++ */
++static int pfe_platform_probe(struct platform_device *pdev)
++{
++ struct resource res;
++ int ii = 0, rc, interface_count = 0, size = 0;
++ const u32 *prop;
++ struct device_node *np, *gem = NULL;
++ struct clk *pfe_clk;
++
++ np = pdev->dev.of_node;
++
++ if (!np) {
++ pr_err("Invalid device node\n");
++ return -EINVAL;
++ }
++
++ pfe = kzalloc(sizeof(*pfe), GFP_KERNEL);
++ if (!pfe) {
++ rc = -ENOMEM;
++ goto err_alloc;
++ }
++
++ platform_set_drvdata(pdev, pfe);
++
++ if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
++ rc = -ENOMEM;
++ pr_err("unable to configure DMA mask.\n");
++ goto err_ddr;
++ }
++
++ if (of_address_to_resource(np, 1, &res)) {
++ rc = -ENOMEM;
++ pr_err("failed to get ddr resource\n");
++ goto err_ddr;
++ }
++
++ pfe->ddr_phys_baseaddr = res.start;
++ pfe->ddr_size = resource_size(&res);
++
++ pfe->ddr_baseaddr = memremap(res.start, resource_size(&res),
++ MEMREMAP_WB);
++ if (!pfe->ddr_baseaddr) {
++ pr_err("memremap() ddr failed\n");
++ rc = -ENOMEM;
++ goto err_ddr;
++ }
++
++ pfe->scfg =
++ syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
++ "fsl,pfe-scfg");
++ if (IS_ERR(pfe->scfg)) {
++ dev_err(&pdev->dev, "No syscfg phandle specified\n");
++ return PTR_ERR(pfe->scfg);
++ }
++
++ pfe->cbus_baseaddr = of_iomap(np, 0);
++ if (!pfe->cbus_baseaddr) {
++ rc = -ENOMEM;
++ pr_err("failed to get axi resource\n");
++ goto err_axi;
++ }
++
++ pfe->hif_irq = platform_get_irq(pdev, 0);
++ if (pfe->hif_irq < 0) {
++ pr_err("platform_get_irq for hif failed\n");
++ rc = pfe->hif_irq;
++ goto err_hif_irq;
++ }
++
++ pfe->wol_irq = platform_get_irq(pdev, 2);
++ if (pfe->wol_irq < 0) {
++ pr_err("platform_get_irq for WoL failed\n");
++ rc = pfe->wol_irq;
++ goto err_hif_irq;
++ }
++
++ /* Read interface count */
++ prop = of_get_property(np, "fsl,pfe-num-interfaces", &size);
++ if (!prop) {
++ pr_err("Failed to read number of interfaces\n");
++ rc = -ENXIO;
++ goto err_prop;
++ }
++
++ interface_count = be32_to_cpup(prop);
++ if (interface_count <= 0) {
++ pr_err("No ethernet interface count : %d\n",
++ interface_count);
++ rc = -ENXIO;
++ goto err_prop;
++ }
++
++ pfe_platform_data.ls1012a_mdio_pdata[0].phy_mask = 0xffffffff;
++
++ while ((gem = of_get_next_child(np, gem))) {
++ if (of_find_property(gem, "reg", &size)) {
++ pfe_get_gemac_if_properties(gem, ii,
++ &pfe_platform_data);
++ ii++;
++ }
++ }
++
++ if (interface_count != ii)
++ pr_info("missing some of gemac interface properties.\n");
++
++ pfe->dev = &pdev->dev;
++
++ pfe->dev->platform_data = &pfe_platform_data;
++
++ /* declare WoL capabilities */
++ device_init_wakeup(&pdev->dev, true);
++
++ /* find the clocks */
++ pfe_clk = devm_clk_get(pfe->dev, "pfe");
++ if (IS_ERR(pfe_clk))
++ return PTR_ERR(pfe_clk);
++
++ /* PFE clock is (platform clock / 2) */
++ /* save sys_clk value as KHz */
++ pfe->ctrl.sys_clk = clk_get_rate(pfe_clk) / (2 * 1000);
++
++ rc = pfe_probe(pfe);
++ if (rc < 0)
++ goto err_probe;
++
++ return 0;
++
++err_probe:
++err_prop:
++err_hif_irq:
++ iounmap(pfe->cbus_baseaddr);
++
++err_axi:
++ memunmap(pfe->ddr_baseaddr);
++
++err_ddr:
++ platform_set_drvdata(pdev, NULL);
++
++ kfree(pfe);
++
++err_alloc:
++ return rc;
++}
++
++/*
++ * pfe_platform_remove -
++ */
++static int pfe_platform_remove(struct platform_device *pdev)
++{
++ struct pfe *pfe = platform_get_drvdata(pdev);
++ int rc;
++
++ pr_info("%s\n", __func__);
++
++ rc = pfe_remove(pfe);
++
++ iounmap(pfe->cbus_baseaddr);
++
++ memunmap(pfe->ddr_baseaddr);
++
++ platform_set_drvdata(pdev, NULL);
++
++ kfree(pfe);
++
++ return rc;
++}
++
++#ifdef CONFIG_PM
++#ifdef CONFIG_PM_SLEEP
++int pfe_platform_suspend(struct device *dev)
++{
++ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev));
++ struct net_device *netdev;
++ int i;
++
++ pfe->wake = 0;
++
++ for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) {
++ netdev = pfe->eth.eth_priv[i]->ndev;
++
++ netif_device_detach(netdev);
++
++ if (netif_running(netdev))
++ if (pfe_eth_suspend(netdev))
++ pfe->wake = 1;
++ }
++
++ /* Shutdown PFE only if we're not waking up the system */
++ if (!pfe->wake) {
++#if defined(LS1012A_PFE_RESET_WA)
++ pfe_hif_rx_idle(&pfe->hif);
++#endif
++ pfe_ctrl_suspend(&pfe->ctrl);
++ pfe_firmware_exit(pfe);
++
++ pfe_hif_exit(pfe);
++ pfe_hif_lib_exit(pfe);
++
++ pfe_hw_exit(pfe);
++ }
++
++ return 0;
++}
++
++static int pfe_platform_resume(struct device *dev)
++{
++ struct pfe *pfe = platform_get_drvdata(to_platform_device(dev));
++ struct net_device *netdev;
++ int i;
++
++ if (!pfe->wake) {
++ pfe_hw_init(pfe, 1);
++ pfe_hif_lib_init(pfe);
++ pfe_hif_init(pfe);
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ util_enable();
++#endif
++ tmu_enable(0xf);
++ class_enable();
++ pfe_ctrl_resume(&pfe->ctrl);
++ }
++
++ for (i = 0; i < (NUM_GEMAC_SUPPORT); i++) {
++ netdev = pfe->eth.eth_priv[i]->ndev;
++
++ if (pfe->mdio.mdio_priv[i]->mii_bus)
++ pfe_eth_mdio_reset(pfe->mdio.mdio_priv[i]->mii_bus);
++
++ if (netif_running(netdev))
++ pfe_eth_resume(netdev);
++
++ netif_device_attach(netdev);
++ }
++ return 0;
++}
++#else
++#define pfe_platform_suspend NULL
++#define pfe_platform_resume NULL
++#endif
++
++static const struct dev_pm_ops pfe_platform_pm_ops = {
++ SET_SYSTEM_SLEEP_PM_OPS(pfe_platform_suspend, pfe_platform_resume)
++};
++#endif
++
++static const struct of_device_id pfe_match[] = {
++ {
++ .compatible = "fsl,pfe",
++ },
++ {},
++};
++MODULE_DEVICE_TABLE(of, pfe_match);
++
++static struct platform_driver pfe_platform_driver = {
++ .probe = pfe_platform_probe,
++ .remove = pfe_platform_remove,
++ .driver = {
++ .name = "pfe",
++ .of_match_table = pfe_match,
++#ifdef CONFIG_PM
++ .pm = &pfe_platform_pm_ops,
++#endif
++ },
++};
++
++module_platform_driver(pfe_platform_driver);
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("PFE Ethernet driver");
++MODULE_AUTHOR("NXP DNCPE");
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_mod.c
+@@ -0,0 +1,158 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/dma-mapping.h>
++#include "pfe_mod.h"
++#include "pfe_cdev.h"
++
++unsigned int us;
++module_param(us, uint, 0444);
++MODULE_PARM_DESC(us, "0: module enabled for kernel networking (DEFAULT)\n"
++ "1: module enabled for userspace networking\n");
++struct pfe *pfe;
++
++/*
++ * pfe_probe -
++ */
++int pfe_probe(struct pfe *pfe)
++{
++ int rc;
++
++ if (pfe->ddr_size < DDR_MAX_SIZE) {
++ pr_err("%s: required DDR memory (%x) above platform ddr memory (%x)\n",
++ __func__, (unsigned int)DDR_MAX_SIZE, pfe->ddr_size);
++ rc = -ENOMEM;
++ goto err_hw;
++ }
++
++ if (((int)(pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR) &
++ (8 * SZ_1M - 1)) != 0) {
++ pr_err("%s: BMU2 base address (0x%x) must be aligned on 8MB boundary\n",
++ __func__, (int)pfe->ddr_phys_baseaddr +
++ BMU2_DDR_BASEADDR);
++ rc = -ENOMEM;
++ goto err_hw;
++ }
++
++ pr_info("cbus_baseaddr: %lx, ddr_baseaddr: %lx, ddr_phys_baseaddr: %lx, ddr_size: %x\n",
++ (unsigned long)pfe->cbus_baseaddr,
++ (unsigned long)pfe->ddr_baseaddr,
++ pfe->ddr_phys_baseaddr, pfe->ddr_size);
++
++ pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr,
++ pfe->ddr_phys_baseaddr, pfe->ddr_size);
++
++ rc = pfe_hw_init(pfe, 0);
++ if (rc < 0)
++ goto err_hw;
++
++ if (us)
++ goto firmware_init;
++
++ rc = pfe_hif_lib_init(pfe);
++ if (rc < 0)
++ goto err_hif_lib;
++
++ rc = pfe_hif_init(pfe);
++ if (rc < 0)
++ goto err_hif;
++
++firmware_init:
++ rc = pfe_firmware_init(pfe);
++ if (rc < 0)
++ goto err_firmware;
++
++ rc = pfe_ctrl_init(pfe);
++ if (rc < 0)
++ goto err_ctrl;
++
++ rc = pfe_eth_init(pfe);
++ if (rc < 0)
++ goto err_eth;
++
++ rc = pfe_sysfs_init(pfe);
++ if (rc < 0)
++ goto err_sysfs;
++
++ rc = pfe_debugfs_init(pfe);
++ if (rc < 0)
++ goto err_debugfs;
++
++ if (us) {
++ /* Creating a character device */
++ rc = pfe_cdev_init();
++ if (rc < 0)
++ goto err_cdev;
++ }
++
++ return 0;
++
++err_cdev:
++ pfe_debugfs_exit(pfe);
++
++err_debugfs:
++ pfe_sysfs_exit(pfe);
++
++err_sysfs:
++ pfe_eth_exit(pfe);
++
++err_eth:
++ pfe_ctrl_exit(pfe);
++
++err_ctrl:
++ pfe_firmware_exit(pfe);
++
++err_firmware:
++ if (us)
++ goto err_hif_lib;
++
++ pfe_hif_exit(pfe);
++
++err_hif:
++ pfe_hif_lib_exit(pfe);
++
++err_hif_lib:
++ pfe_hw_exit(pfe);
++
++err_hw:
++ return rc;
++}
++
++/*
++ * pfe_remove -
++ */
++int pfe_remove(struct pfe *pfe)
++{
++ pr_info("%s\n", __func__);
++
++ if (us)
++ pfe_cdev_exit();
++
++ pfe_debugfs_exit(pfe);
++
++ pfe_sysfs_exit(pfe);
++
++ pfe_eth_exit(pfe);
++
++ pfe_ctrl_exit(pfe);
++
++#if defined(LS1012A_PFE_RESET_WA)
++ pfe_hif_rx_idle(&pfe->hif);
++#endif
++ pfe_firmware_exit(pfe);
++
++ if (us)
++ goto hw_exit;
++
++ pfe_hif_exit(pfe);
++
++ pfe_hif_lib_exit(pfe);
++
++hw_exit:
++ pfe_hw_exit(pfe);
++
++ return 0;
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_mod.h
+@@ -0,0 +1,103 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_MOD_H_
++#define _PFE_MOD_H_
++
++#include <linux/device.h>
++#include <linux/elf.h>
++
++extern unsigned int us;
++
++struct pfe;
++
++#include "pfe_hw.h"
++#include "pfe_firmware.h"
++#include "pfe_ctrl.h"
++#include "pfe_hif.h"
++#include "pfe_hif_lib.h"
++#include "pfe_eth.h"
++#include "pfe_sysfs.h"
++#include "pfe_perfmon.h"
++#include "pfe_debugfs.h"
++
++#define PHYID_MAX_VAL 32
++
++struct pfe_tmu_credit {
++ /* Number of allowed TX packet in-flight, matches TMU queue size */
++ unsigned int tx_credit[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
++ unsigned int tx_credit_max[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
++ unsigned int tx_packets[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
++};
++
++struct pfe {
++ struct regmap *scfg;
++ unsigned long ddr_phys_baseaddr;
++ void *ddr_baseaddr;
++ unsigned int ddr_size;
++ void *cbus_baseaddr;
++ void *apb_baseaddr;
++ unsigned long iram_phys_baseaddr;
++ void *iram_baseaddr;
++ unsigned long ipsec_phys_baseaddr;
++ void *ipsec_baseaddr;
++ int hif_irq;
++ int wol_irq;
++ int hif_client_irq;
++ struct device *dev;
++ struct dentry *dentry;
++ struct pfe_ctrl ctrl;
++ struct pfe_hif hif;
++ struct pfe_eth eth;
++ struct pfe_mdio mdio;
++ struct hif_client_s *hif_client[HIF_CLIENTS_MAX];
++#if defined(CFG_DIAGS)
++ struct pfe_diags diags;
++#endif
++ struct pfe_tmu_credit tmu_credit;
++ struct pfe_cpumon cpumon;
++ struct pfe_memmon memmon;
++ int wake;
++ int mdio_muxval[PHYID_MAX_VAL];
++ struct clk *hfe_clock;
++};
++
++extern struct pfe *pfe;
++
++int pfe_probe(struct pfe *pfe);
++int pfe_remove(struct pfe *pfe);
++
++/* DDR Mapping in reserved memory*/
++#define ROUTE_TABLE_BASEADDR 0
++#define ROUTE_TABLE_HASH_BITS 15 /* 32K entries */
++#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) \
++ * CLASS_ROUTE_SIZE)
++#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
++#define BMU2_BUF_COUNT (4096 - 256)
++/* This is to get a total DDR size of 12MiB */
++#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
++#define UTIL_CODE_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
++#define UTIL_CODE_SIZE (128 * SZ_1K)
++#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
++#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
++#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
++#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
++#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
++#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
++#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
++#define TMU_LLM_QUEUE_LEN (8 * 512)
++/* Must be power of two and at least 16 * 8 = 128 bytes */
++#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN)
++/* (4 TMU's x 16 queues x queue_len) */
++
++#define DDR_MAX_SIZE (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
++
++/* LMEM Mapping */
++#define BMU1_LMEM_BASEADDR 0
++#define BMU1_BUF_COUNT 256
++#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
++
++#endif /* _PFE_MOD_H */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_perfmon.h
+@@ -0,0 +1,26 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_PERFMON_H_
++#define _PFE_PERFMON_H_
++
++#include "pfe/pfe.h"
++
++#define CT_CPUMON_INTERVAL (1 * TIMER_TICKS_PER_SEC)
++
++struct pfe_cpumon {
++ u32 cpu_usage_pct[MAX_PE];
++ u32 class_usage_pct;
++};
++
++struct pfe_memmon {
++ u32 kernel_memory_allocated;
++};
++
++int pfe_perfmon_init(struct pfe *pfe);
++void pfe_perfmon_exit(struct pfe *pfe);
++
++#endif /* _PFE_PERFMON_H_ */
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c
+@@ -0,0 +1,840 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include "pfe_mod.h"
++
++#define PE_EXCEPTION_DUMP_ADDRESS 0x1fa8
++#define NUM_QUEUES 16
++
++static char register_name[20][5] = {
++ "EPC", "ECAS", "EID", "ED",
++ "r0", "r1", "r2", "r3",
++ "r4", "r5", "r6", "r7",
++ "r8", "r9", "r10", "r11",
++ "r12", "r13", "r14", "r15",
++};
++
++static char exception_name[14][20] = {
++ "Reset",
++ "HardwareFailure",
++ "NMI",
++ "InstBreakpoint",
++ "DataBreakpoint",
++ "Unsupported",
++ "PrivilegeViolation",
++ "InstBusError",
++ "DataBusError",
++ "AlignmentError",
++ "ArithmeticError",
++ "SystemCall",
++ "MemoryManagement",
++ "Interrupt",
++};
++
++static unsigned long class_do_clear;
++static unsigned long tmu_do_clear;
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++static unsigned long util_do_clear;
++#endif
++
++static ssize_t display_pe_status(char *buf, int id, u32 dmem_addr, unsigned long
++ do_clear)
++{
++ ssize_t len = 0;
++ u32 val;
++ char statebuf[5];
++ struct pfe_cpumon *cpumon = &pfe->cpumon;
++ u32 debug_indicator;
++ u32 debug[20];
++
++ if (id < CLASS0_ID || id >= MAX_PE)
++ return len;
++
++ *(u32 *)statebuf = pe_dmem_read(id, dmem_addr, 4);
++ dmem_addr += 4;
++
++ statebuf[4] = '\0';
++ len += sprintf(buf + len, "state=%4s ", statebuf);
++
++ val = pe_dmem_read(id, dmem_addr, 4);
++ dmem_addr += 4;
++ len += sprintf(buf + len, "ctr=%08x ", cpu_to_be32(val));
++
++ val = pe_dmem_read(id, dmem_addr, 4);
++ if (do_clear && val)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ dmem_addr += 4;
++ len += sprintf(buf + len, "rx=%u ", cpu_to_be32(val));
++
++ val = pe_dmem_read(id, dmem_addr, 4);
++ if (do_clear && val)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ dmem_addr += 4;
++ if (id >= TMU0_ID && id <= TMU_MAX_ID)
++ len += sprintf(buf + len, "qstatus=%x", cpu_to_be32(val));
++ else
++ len += sprintf(buf + len, "tx=%u", cpu_to_be32(val));
++
++ val = pe_dmem_read(id, dmem_addr, 4);
++ if (do_clear && val)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ dmem_addr += 4;
++ if (val)
++ len += sprintf(buf + len, " drop=%u", cpu_to_be32(val));
++
++ len += sprintf(buf + len, " load=%d%%", cpumon->cpu_usage_pct[id]);
++
++ len += sprintf(buf + len, "\n");
++
++ debug_indicator = pe_dmem_read(id, dmem_addr, 4);
++ dmem_addr += 4;
++ if (!strncmp((char *)&debug_indicator, "DBUG", 4)) {
++ int j, last = 0;
++
++ for (j = 0; j < 16; j++) {
++ debug[j] = pe_dmem_read(id, dmem_addr, 4);
++ if (debug[j]) {
++ if (do_clear)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ last = j + 1;
++ }
++ dmem_addr += 4;
++ }
++ for (j = 0; j < last; j++) {
++ len += sprintf(buf + len, "%08x%s",
++ cpu_to_be32(debug[j]),
++ (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
++ }
++ }
++
++ if (!strncmp(statebuf, "DEAD", 4)) {
++ u32 i, dump = PE_EXCEPTION_DUMP_ADDRESS;
++
++ len += sprintf(buf + len, "Exception details:\n");
++ for (i = 0; i < 20; i++) {
++ debug[i] = pe_dmem_read(id, dump, 4);
++ dump += 4;
++ if (i == 2)
++ len += sprintf(buf + len, "%4s = %08x (=%s) ",
++ register_name[i], cpu_to_be32(debug[i]),
++ exception_name[min((u32)
++ cpu_to_be32(debug[i]), (u32)13)]);
++ else
++ len += sprintf(buf + len, "%4s = %08x%s",
++ register_name[i], cpu_to_be32(debug[i]),
++ (i & 0x3) == 0x3 || i == 19 ? "\n" : " ");
++ }
++ }
++
++ return len;
++}
++
++static ssize_t class_phy_stats(char *buf, int phy)
++{
++ ssize_t len = 0;
++ int off1 = phy * 0x28;
++ int off2 = phy * 0x10;
++
++ if (phy == 3)
++ off1 = CLASS_PHY4_RX_PKTS - CLASS_PHY1_RX_PKTS;
++
++ len += sprintf(buf + len, "phy: %d\n", phy);
++ len += sprintf(buf + len,
++ " rx: %10u, tx: %10u, intf: %10u, ipv4: %10u, ipv6: %10u\n",
++ readl(CLASS_PHY1_RX_PKTS + off1),
++ readl(CLASS_PHY1_TX_PKTS + off1),
++ readl(CLASS_PHY1_INTF_MATCH_PKTS + off1),
++ readl(CLASS_PHY1_V4_PKTS + off1),
++ readl(CLASS_PHY1_V6_PKTS + off1));
++
++ len += sprintf(buf + len,
++ " icmp: %10u, igmp: %10u, tcp: %10u, udp: %10u\n",
++ readl(CLASS_PHY1_ICMP_PKTS + off2),
++ readl(CLASS_PHY1_IGMP_PKTS + off2),
++ readl(CLASS_PHY1_TCP_PKTS + off2),
++ readl(CLASS_PHY1_UDP_PKTS + off2));
++
++ len += sprintf(buf + len, " err\n");
++ len += sprintf(buf + len,
++ " lp: %10u, intf: %10u, l3: %10u, chcksum: %10u, ttl: %10u\n",
++ readl(CLASS_PHY1_LP_FAIL_PKTS + off1),
++ readl(CLASS_PHY1_INTF_FAIL_PKTS + off1),
++ readl(CLASS_PHY1_L3_FAIL_PKTS + off1),
++ readl(CLASS_PHY1_CHKSUM_ERR_PKTS + off1),
++ readl(CLASS_PHY1_TTL_ERR_PKTS + off1));
++
++ return len;
++}
++
++/* qm_read_drop_stat
++ * This function is used to read the drop statistics from the TMU
++ * hw drop counter. Since the hw counter is always cleared afer
++ * reading, this function maintains the previous drop count, and
++ * adds the new value to it. That value can be retrieved by
++ * passing a pointer to it with the total_drops arg.
++ *
++ * @param tmu TMU number (0 - 3)
++ * @param queue queue number (0 - 15)
++ * @param total_drops pointer to location to store total drops (or NULL)
++ * @param do_reset if TRUE, clear total drops after updating
++ */
++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)
++{
++ static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];
++ u32 val;
++
++ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
++ writel((tmu << 8) | queue, TMU_LLM_CTRL);
++ val = readl(TMU_TEQ_DROP_STAT);
++ qtotal[tmu][queue] += val;
++ if (total_drops)
++ *total_drops = qtotal[tmu][queue];
++ if (do_reset)
++ qtotal[tmu][queue] = 0;
++ return val;
++}
++
++static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)
++{
++ ssize_t len = 0;
++ u32 drops;
++
++ len += sprintf(buf + len, "%d-%02d, ", tmu, queue);
++
++ drops = qm_read_drop_stat(tmu, queue, NULL, 0);
++
++ /* Select queue */
++ writel((tmu << 8) | queue, TMU_TEQ_CTRL);
++ writel((tmu << 8) | queue, TMU_LLM_CTRL);
++
++ len += sprintf(buf + len,
++ "(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n",
++ drops, readl(TMU_TEQ_TRANS_STAT),
++ readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),
++ readl(TMU_LLM_QUE_DROPCNT));
++
++ return len;
++}
++
++static ssize_t tmu_queues(char *buf, int tmu)
++{
++ ssize_t len = 0;
++ int queue;
++
++ for (queue = 0; queue < 16; queue++)
++ len += tmu_queue_stats(buf + len, tmu, queue);
++
++ return len;
++}
++
++static ssize_t block_version(char *buf, void *addr)
++{
++ ssize_t len = 0;
++ u32 val;
++
++ val = readl(addr);
++ len += sprintf(buf + len, "revision: %x, version: %x, id: %x\n",
++ (val >> 24) & 0xff, (val >> 16) & 0xff, val & 0xffff);
++
++ return len;
++}
++
++static ssize_t bmu(char *buf, int id, void *base)
++{
++ ssize_t len = 0;
++
++ len += sprintf(buf + len, "%s: %d\n ", __func__, id);
++
++ len += block_version(buf + len, base + BMU_VERSION);
++
++ len += sprintf(buf + len, " buf size: %x\n", (1 << readl(base +
++ BMU_BUF_SIZE)));
++ len += sprintf(buf + len, " buf count: %x\n", readl(base +
++ BMU_BUF_CNT));
++ len += sprintf(buf + len, " buf rem: %x\n", readl(base +
++ BMU_REM_BUF_CNT));
++ len += sprintf(buf + len, " buf curr: %x\n", readl(base +
++ BMU_CURR_BUF_CNT));
++ len += sprintf(buf + len, " free err: %x\n", readl(base +
++ BMU_FREE_ERR_ADDR));
++
++ return len;
++}
++
++static ssize_t gpi(char *buf, int id, void *base)
++{
++ ssize_t len = 0;
++ u32 val;
++
++ len += sprintf(buf + len, "%s%d:\n ", __func__, id);
++ len += block_version(buf + len, base + GPI_VERSION);
++
++ len += sprintf(buf + len, " tx under stick: %x\n", readl(base +
++ GPI_FIFO_STATUS));
++ val = readl(base + GPI_FIFO_DEBUG);
++ len += sprintf(buf + len, " tx pkts: %x\n", (val >> 23) &
++ 0x3f);
++ len += sprintf(buf + len, " rx pkts: %x\n", (val >> 18) &
++ 0x3f);
++ len += sprintf(buf + len, " tx bytes: %x\n", (val >> 9) &
++ 0x1ff);
++ len += sprintf(buf + len, " rx bytes: %x\n", (val >> 0) &
++ 0x1ff);
++ len += sprintf(buf + len, " overrun: %x\n", readl(base +
++ GPI_OVERRUN_DROPCNT));
++
++ return len;
++}
++
++static ssize_t pfe_set_class(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ class_do_clear = kstrtoul(buf, 0, 0);
++ return count;
++}
++
++static ssize_t pfe_show_class(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ ssize_t len = 0;
++ int id;
++ u32 val;
++ struct pfe_cpumon *cpumon = &pfe->cpumon;
++
++ len += block_version(buf + len, CLASS_VERSION);
++
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++ len += sprintf(buf + len, "%d: ", id - CLASS0_ID);
++
++ val = readl(CLASS_PE0_DEBUG + id * 4);
++ len += sprintf(buf + len, "pc=1%04x ", val & 0xffff);
++
++ len += display_pe_status(buf + len, id, CLASS_DM_PESTATUS,
++ class_do_clear);
++ }
++ len += sprintf(buf + len, "aggregate load=%d%%\n\n",
++ cpumon->class_usage_pct);
++
++ len += sprintf(buf + len, "pe status: 0x%x\n",
++ readl(CLASS_PE_STATUS));
++ len += sprintf(buf + len, "max buf cnt: 0x%x afull thres: 0x%x\n",
++ readl(CLASS_MAX_BUF_CNT), readl(CLASS_AFULL_THRES));
++ len += sprintf(buf + len, "tsq max cnt: 0x%x tsq fifo thres: 0x%x\n",
++ readl(CLASS_TSQ_MAX_CNT), readl(CLASS_TSQ_FIFO_THRES));
++ len += sprintf(buf + len, "state: 0x%x\n", readl(CLASS_STATE));
++
++ len += class_phy_stats(buf + len, 0);
++ len += class_phy_stats(buf + len, 1);
++ len += class_phy_stats(buf + len, 2);
++ len += class_phy_stats(buf + len, 3);
++
++ return len;
++}
++
++static ssize_t pfe_set_tmu(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ tmu_do_clear = kstrtoul(buf, 0, 0);
++ return count;
++}
++
++static ssize_t pfe_show_tmu(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ ssize_t len = 0;
++ int id;
++ u32 val;
++
++ len += block_version(buf + len, TMU_VERSION);
++
++ for (id = TMU0_ID; id <= TMU_MAX_ID; id++) {
++ if (id == TMU2_ID)
++ continue;
++ len += sprintf(buf + len, "%d: ", id - TMU0_ID);
++
++ len += display_pe_status(buf + len, id, TMU_DM_PESTATUS,
++ tmu_do_clear);
++ }
++
++ len += sprintf(buf + len, "pe status: %x\n", readl(TMU_PE_STATUS));
++ len += sprintf(buf + len, "inq fifo cnt: %x\n",
++ readl(TMU_PHY_INQ_FIFO_CNT));
++ val = readl(TMU_INQ_STAT);
++ len += sprintf(buf + len, "inq wr ptr: %x\n", val & 0x3ff);
++ len += sprintf(buf + len, "inq rd ptr: %x\n", val >> 10);
++
++ return len;
++}
++
++static unsigned long drops_do_clear;
++static u32 class_drop_counter[CLASS_NUM_DROP_COUNTERS];
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++static u32 util_drop_counter[UTIL_NUM_DROP_COUNTERS];
++#endif
++
++char *class_drop_description[CLASS_NUM_DROP_COUNTERS] = {
++ "ICC",
++ "Host Pkt Error",
++ "Rx Error",
++ "IPsec Outbound",
++ "IPsec Inbound",
++ "EXPT IPsec Error",
++ "Reassembly",
++ "Fragmenter",
++ "NAT-T",
++ "Socket",
++ "Multicast",
++ "NAT-PT",
++ "Tx Disabled",
++};
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++char *util_drop_description[UTIL_NUM_DROP_COUNTERS] = {
++ "IPsec Outbound",
++ "IPsec Inbound",
++ "IPsec Rate Limiter",
++ "Fragmenter",
++ "Socket",
++ "Tx Disabled",
++ "Rx Error",
++};
++#endif
++
++static ssize_t pfe_set_drops(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ drops_do_clear = kstrtoul(buf, 0, 0);
++ return count;
++}
++
++static u32 tmu_drops[4][16];
++static ssize_t pfe_show_drops(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ ssize_t len = 0;
++ int id, dropnum;
++ int tmu, queue;
++ u32 val;
++ u32 dmem_addr;
++ int num_class_drops = 0, num_tmu_drops = 0, num_util_drops = 0;
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++ memset(class_drop_counter, 0, sizeof(class_drop_counter));
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++ if (drops_do_clear)
++ pe_sync_stop(ctrl, (1 << id));
++ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS;
++ dropnum++) {
++ dmem_addr = CLASS_DM_DROP_CNTR;
++ val = be32_to_cpu(pe_dmem_read(id, dmem_addr, 4));
++ class_drop_counter[dropnum] += val;
++ num_class_drops += val;
++ if (drops_do_clear)
++ pe_dmem_write(id, 0, dmem_addr, 4);
++ }
++ if (drops_do_clear)
++ pe_start(ctrl, (1 << id));
++ }
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ if (drops_do_clear)
++ pe_sync_stop(ctrl, (1 << UTIL_ID));
++ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) {
++ dmem_addr = UTIL_DM_DROP_CNTR;
++ val = be32_to_cpu(pe_dmem_read(UTIL_ID, dmem_addr, 4));
++ util_drop_counter[dropnum] = val;
++ num_util_drops += val;
++ if (drops_do_clear)
++ pe_dmem_write(UTIL_ID, 0, dmem_addr, 4);
++ }
++ if (drops_do_clear)
++ pe_start(ctrl, (1 << UTIL_ID));
++#endif
++ for (tmu = 0; tmu < 4; tmu++) {
++ for (queue = 0; queue < 16; queue++) {
++ qm_read_drop_stat(tmu, queue, &tmu_drops[tmu][queue],
++ drops_do_clear);
++ num_tmu_drops += tmu_drops[tmu][queue];
++ }
++ }
++
++ if (num_class_drops == 0 && num_util_drops == 0 && num_tmu_drops == 0)
++ len += sprintf(buf + len, "No PE drops\n\n");
++
++ if (num_class_drops > 0) {
++ len += sprintf(buf + len, "Class PE drops --\n");
++ for (dropnum = 0; dropnum < CLASS_NUM_DROP_COUNTERS;
++ dropnum++) {
++ if (class_drop_counter[dropnum] > 0)
++ len += sprintf(buf + len, " %s: %d\n",
++ class_drop_description[dropnum],
++ class_drop_counter[dropnum]);
++ }
++ len += sprintf(buf + len, "\n");
++ }
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ if (num_util_drops > 0) {
++ len += sprintf(buf + len, "Util PE drops --\n");
++ for (dropnum = 0; dropnum < UTIL_NUM_DROP_COUNTERS; dropnum++) {
++ if (util_drop_counter[dropnum] > 0)
++ len += sprintf(buf + len, " %s: %d\n",
++ util_drop_description[dropnum],
++ util_drop_counter[dropnum]);
++ }
++ len += sprintf(buf + len, "\n");
++ }
++#endif
++ if (num_tmu_drops > 0) {
++ len += sprintf(buf + len, "TMU drops --\n");
++ for (tmu = 0; tmu < 4; tmu++) {
++ for (queue = 0; queue < 16; queue++) {
++ if (tmu_drops[tmu][queue] > 0)
++ len += sprintf(buf + len,
++ " TMU%d-Q%d: %d\n"
++ , tmu, queue, tmu_drops[tmu][queue]);
++ }
++ }
++ len += sprintf(buf + len, "\n");
++ }
++
++ return len;
++}
++
++static ssize_t pfe_show_tmu0_queues(struct device *dev, struct device_attribute
++ *attr, char *buf)
++{
++ return tmu_queues(buf, 0);
++}
++
++static ssize_t pfe_show_tmu1_queues(struct device *dev, struct device_attribute
++ *attr, char *buf)
++{
++ return tmu_queues(buf, 1);
++}
++
++static ssize_t pfe_show_tmu2_queues(struct device *dev, struct device_attribute
++ *attr, char *buf)
++{
++ return tmu_queues(buf, 2);
++}
++
++static ssize_t pfe_show_tmu3_queues(struct device *dev, struct device_attribute
++ *attr, char *buf)
++{
++ return tmu_queues(buf, 3);
++}
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ util_do_clear = kstrtoul(buf, NULL, 0);
++ return count;
++}
++
++static ssize_t pfe_show_util(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ ssize_t len = 0;
++ struct pfe_ctrl *ctrl = &pfe->ctrl;
++
++ len += block_version(buf + len, UTIL_VERSION);
++
++ pe_sync_stop(ctrl, (1 << UTIL_ID));
++ len += display_pe_status(buf + len, UTIL_ID, UTIL_DM_PESTATUS,
++ util_do_clear);
++ pe_start(ctrl, (1 << UTIL_ID));
++
++ len += sprintf(buf + len, "pe status: %x\n", readl(UTIL_PE_STATUS));
++ len += sprintf(buf + len, "max buf cnt: %x\n",
++ readl(UTIL_MAX_BUF_CNT));
++ len += sprintf(buf + len, "tsq max cnt: %x\n",
++ readl(UTIL_TSQ_MAX_CNT));
++
++ return len;
++}
++#endif
++
++static ssize_t pfe_show_bmu(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ ssize_t len = 0;
++
++ len += bmu(buf + len, 1, BMU1_BASE_ADDR);
++ len += bmu(buf + len, 2, BMU2_BASE_ADDR);
++
++ return len;
++}
++
++static ssize_t pfe_show_hif(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ ssize_t len = 0;
++
++ len += sprintf(buf + len, "hif:\n ");
++ len += block_version(buf + len, HIF_VERSION);
++
++ len += sprintf(buf + len, " tx curr bd: %x\n",
++ readl(HIF_TX_CURR_BD_ADDR));
++ len += sprintf(buf + len, " tx status: %x\n",
++ readl(HIF_TX_STATUS));
++ len += sprintf(buf + len, " tx dma status: %x\n",
++ readl(HIF_TX_DMA_STATUS));
++
++ len += sprintf(buf + len, " rx curr bd: %x\n",
++ readl(HIF_RX_CURR_BD_ADDR));
++ len += sprintf(buf + len, " rx status: %x\n",
++ readl(HIF_RX_STATUS));
++ len += sprintf(buf + len, " rx dma status: %x\n",
++ readl(HIF_RX_DMA_STATUS));
++
++ len += sprintf(buf + len, "hif nocopy:\n ");
++ len += block_version(buf + len, HIF_NOCPY_VERSION);
++
++ len += sprintf(buf + len, " tx curr bd: %x\n",
++ readl(HIF_NOCPY_TX_CURR_BD_ADDR));
++ len += sprintf(buf + len, " tx status: %x\n",
++ readl(HIF_NOCPY_TX_STATUS));
++ len += sprintf(buf + len, " tx dma status: %x\n",
++ readl(HIF_NOCPY_TX_DMA_STATUS));
++
++ len += sprintf(buf + len, " rx curr bd: %x\n",
++ readl(HIF_NOCPY_RX_CURR_BD_ADDR));
++ len += sprintf(buf + len, " rx status: %x\n",
++ readl(HIF_NOCPY_RX_STATUS));
++ len += sprintf(buf + len, " rx dma status: %x\n",
++ readl(HIF_NOCPY_RX_DMA_STATUS));
++
++ return len;
++}
++
++static ssize_t pfe_show_gpi(struct device *dev, struct device_attribute *attr,
++ char *buf)
++{
++ ssize_t len = 0;
++
++ len += gpi(buf + len, 0, EGPI1_BASE_ADDR);
++ len += gpi(buf + len, 1, EGPI2_BASE_ADDR);
++ len += gpi(buf + len, 3, HGPI_BASE_ADDR);
++
++ return len;
++}
++
++static ssize_t pfe_show_pfemem(struct device *dev, struct device_attribute
++ *attr, char *buf)
++{
++ ssize_t len = 0;
++ struct pfe_memmon *memmon = &pfe->memmon;
++
++ len += sprintf(buf + len, "Kernel Memory: %d Bytes (%d KB)\n",
++ memmon->kernel_memory_allocated,
++ (memmon->kernel_memory_allocated + 1023) / 1024);
++
++ return len;
++}
++
++static ssize_t pfe_show_crc_revalidated(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ u64 crc_validated = 0;
++ ssize_t len = 0;
++ int id, phyid;
++
++ len += sprintf(buf + len, "FCS re-validated by PFE:\n");
++
++ for (phyid = 0; phyid < 2; phyid++) {
++ crc_validated = 0;
++ for (id = CLASS0_ID; id <= CLASS_MAX_ID; id++) {
++ crc_validated += be32_to_cpu(pe_dmem_read(id,
++ CLASS_DM_CRC_VALIDATED + (phyid * 4), 4));
++ }
++ len += sprintf(buf + len, "MAC %d:\n count:%10llu\n",
++ phyid, crc_validated);
++ }
++
++ return len;
++}
++
++#ifdef HIF_NAPI_STATS
++static ssize_t pfe_show_hif_napi_stats(struct device *dev,
++ struct device_attribute *attr,
++ char *buf)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct pfe *pfe = platform_get_drvdata(pdev);
++ ssize_t len = 0;
++
++ len += sprintf(buf + len, "sched: %u\n",
++ pfe->hif.napi_counters[NAPI_SCHED_COUNT]);
++ len += sprintf(buf + len, "poll: %u\n",
++ pfe->hif.napi_counters[NAPI_POLL_COUNT]);
++ len += sprintf(buf + len, "packet: %u\n",
++ pfe->hif.napi_counters[NAPI_PACKET_COUNT]);
++ len += sprintf(buf + len, "budget: %u\n",
++ pfe->hif.napi_counters[NAPI_FULL_BUDGET_COUNT]);
++ len += sprintf(buf + len, "desc: %u\n",
++ pfe->hif.napi_counters[NAPI_DESC_COUNT]);
++ len += sprintf(buf + len, "full: %u\n",
++ pfe->hif.napi_counters[NAPI_CLIENT_FULL_COUNT]);
++
++ return len;
++}
++
++static ssize_t pfe_set_hif_napi_stats(struct device *dev,
++ struct device_attribute *attr,
++ const char *buf, size_t count)
++{
++ struct platform_device *pdev = to_platform_device(dev);
++ struct pfe *pfe = platform_get_drvdata(pdev);
++
++ memset(pfe->hif.napi_counters, 0, sizeof(pfe->hif.napi_counters));
++
++ return count;
++}
++
++static DEVICE_ATTR(hif_napi_stats, 0644, pfe_show_hif_napi_stats,
++ pfe_set_hif_napi_stats);
++#endif
++
++static DEVICE_ATTR(class, 0644, pfe_show_class, pfe_set_class);
++static DEVICE_ATTR(tmu, 0644, pfe_show_tmu, pfe_set_tmu);
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++static DEVICE_ATTR(util, 0644, pfe_show_util, pfe_set_util);
++#endif
++static DEVICE_ATTR(bmu, 0444, pfe_show_bmu, NULL);
++static DEVICE_ATTR(hif, 0444, pfe_show_hif, NULL);
++static DEVICE_ATTR(gpi, 0444, pfe_show_gpi, NULL);
++static DEVICE_ATTR(drops, 0644, pfe_show_drops, pfe_set_drops);
++static DEVICE_ATTR(tmu0_queues, 0444, pfe_show_tmu0_queues, NULL);
++static DEVICE_ATTR(tmu1_queues, 0444, pfe_show_tmu1_queues, NULL);
++static DEVICE_ATTR(tmu2_queues, 0444, pfe_show_tmu2_queues, NULL);
++static DEVICE_ATTR(tmu3_queues, 0444, pfe_show_tmu3_queues, NULL);
++static DEVICE_ATTR(pfemem, 0444, pfe_show_pfemem, NULL);
++static DEVICE_ATTR(fcs_revalidated, 0444, pfe_show_crc_revalidated, NULL);
++
++int pfe_sysfs_init(struct pfe *pfe)
++{
++ if (device_create_file(pfe->dev, &dev_attr_class))
++ goto err_class;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu))
++ goto err_tmu;
++
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ if (device_create_file(pfe->dev, &dev_attr_util))
++ goto err_util;
++#endif
++
++ if (device_create_file(pfe->dev, &dev_attr_bmu))
++ goto err_bmu;
++
++ if (device_create_file(pfe->dev, &dev_attr_hif))
++ goto err_hif;
++
++ if (device_create_file(pfe->dev, &dev_attr_gpi))
++ goto err_gpi;
++
++ if (device_create_file(pfe->dev, &dev_attr_drops))
++ goto err_drops;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu0_queues))
++ goto err_tmu0_queues;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu1_queues))
++ goto err_tmu1_queues;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu2_queues))
++ goto err_tmu2_queues;
++
++ if (device_create_file(pfe->dev, &dev_attr_tmu3_queues))
++ goto err_tmu3_queues;
++
++ if (device_create_file(pfe->dev, &dev_attr_pfemem))
++ goto err_pfemem;
++
++ if (device_create_file(pfe->dev, &dev_attr_fcs_revalidated))
++ goto err_crc_revalidated;
++
++#ifdef HIF_NAPI_STATS
++ if (device_create_file(pfe->dev, &dev_attr_hif_napi_stats))
++ goto err_hif_napi_stats;
++#endif
++
++ return 0;
++
++#ifdef HIF_NAPI_STATS
++err_hif_napi_stats:
++ device_remove_file(pfe->dev, &dev_attr_fcs_revalidated);
++#endif
++
++err_crc_revalidated:
++ device_remove_file(pfe->dev, &dev_attr_pfemem);
++
++err_pfemem:
++ device_remove_file(pfe->dev, &dev_attr_tmu3_queues);
++
++err_tmu3_queues:
++ device_remove_file(pfe->dev, &dev_attr_tmu2_queues);
++
++err_tmu2_queues:
++ device_remove_file(pfe->dev, &dev_attr_tmu1_queues);
++
++err_tmu1_queues:
++ device_remove_file(pfe->dev, &dev_attr_tmu0_queues);
++
++err_tmu0_queues:
++ device_remove_file(pfe->dev, &dev_attr_drops);
++
++err_drops:
++ device_remove_file(pfe->dev, &dev_attr_gpi);
++
++err_gpi:
++ device_remove_file(pfe->dev, &dev_attr_hif);
++
++err_hif:
++ device_remove_file(pfe->dev, &dev_attr_bmu);
++
++err_bmu:
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ device_remove_file(pfe->dev, &dev_attr_util);
++
++err_util:
++#endif
++ device_remove_file(pfe->dev, &dev_attr_tmu);
++
++err_tmu:
++ device_remove_file(pfe->dev, &dev_attr_class);
++
++err_class:
++ return -1;
++}
++
++void pfe_sysfs_exit(struct pfe *pfe)
++{
++#ifdef HIF_NAPI_STATS
++ device_remove_file(pfe->dev, &dev_attr_hif_napi_stats);
++#endif
++ device_remove_file(pfe->dev, &dev_attr_fcs_revalidated);
++ device_remove_file(pfe->dev, &dev_attr_pfemem);
++ device_remove_file(pfe->dev, &dev_attr_tmu3_queues);
++ device_remove_file(pfe->dev, &dev_attr_tmu2_queues);
++ device_remove_file(pfe->dev, &dev_attr_tmu1_queues);
++ device_remove_file(pfe->dev, &dev_attr_tmu0_queues);
++ device_remove_file(pfe->dev, &dev_attr_drops);
++ device_remove_file(pfe->dev, &dev_attr_gpi);
++ device_remove_file(pfe->dev, &dev_attr_hif);
++ device_remove_file(pfe->dev, &dev_attr_bmu);
++#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
++ device_remove_file(pfe->dev, &dev_attr_util);
++#endif
++ device_remove_file(pfe->dev, &dev_attr_tmu);
++ device_remove_file(pfe->dev, &dev_attr_class);
++}
+--- /dev/null
++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.h
+@@ -0,0 +1,17 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Copyright 2015-2016 Freescale Semiconductor, Inc.
++ * Copyright 2017 NXP
++ */
++
++#ifndef _PFE_SYSFS_H_
++#define _PFE_SYSFS_H_
++
++#include <linux/proc_fs.h>
++
++u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset);
++
++int pfe_sysfs_init(struct pfe *pfe);
++void pfe_sysfs_exit(struct pfe *pfe);
++
++#endif /* _PFE_SYSFS_H_ */
--- /dev/null
+From 3823e4e1078a95e26b9a69e88c9bf862b0267e1c Mon Sep 17 00:00:00 2001
+From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+Date: Wed, 29 Nov 2017 15:27:57 +0530
+Subject: [PATCH] phy: Add 2.5G SGMII interface mode
+
+Add 2.5G SGMII interface mode(PHY_INTERFACE_MODE_2500SGMII)
+in existing phy_interface list
+
+Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
+---
+ drivers/net/phy/phy-core.c | 1 +
+ drivers/net/phy/phylink.c | 2 ++
+ include/linux/phy.h | 3 +++
+ 3 files changed, 6 insertions(+)
+
+--- a/drivers/net/phy/phy-core.c
++++ b/drivers/net/phy/phy-core.c
+@@ -138,6 +138,7 @@ int phy_interface_num_ports(phy_interfac
+ case PHY_INTERFACE_MODE_RXAUI:
+ case PHY_INTERFACE_MODE_XAUI:
+ case PHY_INTERFACE_MODE_1000BASEKX:
++ case PHY_INTERFACE_MODE_2500SGMII:
+ return 1;
+ case PHY_INTERFACE_MODE_QSGMII:
+ case PHY_INTERFACE_MODE_QUSGMII:
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -218,6 +218,7 @@ static int phylink_interface_max_speed(p
+ return SPEED_1000;
+
+ case PHY_INTERFACE_MODE_2500BASEX:
++ case PHY_INTERFACE_MODE_2500SGMII:
+ return SPEED_2500;
+
+ case PHY_INTERFACE_MODE_5GBASER:
+@@ -526,6 +527,7 @@ unsigned long phylink_get_capabilities(p
+ break;
+
+ case PHY_INTERFACE_MODE_2500BASEX:
++ case PHY_INTERFACE_MODE_2500SGMII:
+ caps |= MAC_2500FD;
+ break;
+
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -165,6 +165,7 @@ typedef enum {
+ PHY_INTERFACE_MODE_10GKR,
+ PHY_INTERFACE_MODE_QUSGMII,
+ PHY_INTERFACE_MODE_1000BASEKX,
++ PHY_INTERFACE_MODE_2500SGMII,
+ PHY_INTERFACE_MODE_MAX,
+ } phy_interface_t;
+
+@@ -286,6 +287,8 @@ static inline const char *phy_modes(phy_
+ return "100base-x";
+ case PHY_INTERFACE_MODE_QUSGMII:
+ return "qusgmii";
++ case PHY_INTERFACE_MODE_2500SGMII:
++ return "sgmii-2500";
+ default:
+ return "unknown";
+ }
--- /dev/null
+From 1dc3a2e216d99adc2df022ab37eab32f61d80e0e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 8 May 2023 19:26:48 +0200
+Subject: [PATCH] layerscape: 6.1: fix compilation warning for fsl ppfe driver
+
+Rework some desc dump and dummy pkt function to fix compilation warning.
+Fix compilation warning:
+drivers/staging/fsl_ppfe/pfe_hif.c: In function 'send_dummy_pkt_to_hif':
+drivers/staging/fsl_ppfe/pfe_hif.c:118:19: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
+ 118 | ddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL));
+ | ^
+drivers/staging/fsl_ppfe/pfe_hif.c:122:20: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
+ 122 | lmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL));
+ | ^
+drivers/staging/fsl_ppfe/pfe_hif.c: In function 'pfe_hif_desc_dump':
+drivers/staging/fsl_ppfe/pfe_hif.c:195:24: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
+ 195 | desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v +
+ | ^
+drivers/staging/fsl_ppfe/pfe_hif.c:195:36: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
+ 195 | desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v +
+ | ^
+drivers/staging/fsl_ppfe/pfe_hif.c:207:19: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
+ 207 | desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v +
+ | ^
+drivers/staging/fsl_ppfe/pfe_hif.c:207:31: error: cast from pointer to integer of different size [-Werror=pointer-to-int-cast]
+ 207 | desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v +
+ | ^
+cc1: all warnings being treated as errors
+
+In file included from ./include/linux/kernel.h:19,
+ from ./include/linux/list.h:9,
+ from ./include/linux/wait.h:7,
+ from ./include/linux/eventfd.h:13,
+ from drivers/staging/fsl_ppfe/pfe_cdev.c:11:
+drivers/staging/fsl_ppfe/pfe_cdev.c: In function 'pfe_cdev_read':
+./include/linux/kern_levels.h:5:25: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'int' [-Werror=format=]
+ 5 | #define KERN_SOH "\001" /* ASCII Start Of Header */
+ | ^~~~~~
+./include/linux/printk.h:422:25: note: in definition of macro 'printk_index_wrap'
+ 422 | _p_func(_fmt, ##__VA_ARGS__); \
+ | ^~~~
+./include/linux/printk.h:132:17: note: in expansion of macro 'printk'
+ 132 | printk(fmt, ##__VA_ARGS__); \
+ | ^~~~~~
+./include/linux/printk.h:580:9: note: in expansion of macro 'no_printk'
+ 580 | no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
+ | ^~~~~~~~~
+./include/linux/kern_levels.h:15:25: note: in expansion of macro 'KERN_SOH'
+ 15 | #define KERN_DEBUG KERN_SOH "7" /* debug-level messages */
+ | ^~~~~~~~
+./include/linux/printk.h:580:19: note: in expansion of macro 'KERN_DEBUG'
+ 580 | no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
+ | ^~~~~~~~~~
+drivers/staging/fsl_ppfe/pfe_cdev.c:42:17: note: in expansion of macro 'pr_debug'
+ 42 | pr_debug("%u %lu", link_states[ret].phy_id,
+ | ^~~~~~~~
+./include/linux/kern_levels.h:5:25: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
+ 5 | #define KERN_SOH "\001" /* ASCII Start Of Header */
+ | ^~~~~~
+./include/linux/printk.h:422:25: note: in definition of macro 'printk_index_wrap'
+ 422 | _p_func(_fmt, ##__VA_ARGS__); \
+ | ^~~~
+./include/linux/printk.h:493:9: note: in expansion of macro 'printk'
+ 493 | printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
+ | ^~~~~~
+./include/linux/kern_levels.h:11:25: note: in expansion of macro 'KERN_SOH'
+ 11 | #define KERN_ERR KERN_SOH "3" /* error conditions */
+ | ^~~~~~~~
+./include/linux/printk.h:493:16: note: in expansion of macro 'KERN_ERR'
+ 493 | printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
+ | ^~~~~~~~
+drivers/staging/fsl_ppfe/pfe_cdev.c:50:17: note: in expansion of macro 'pr_err'
+ 50 | pr_err("Failed to send (%d)bytes of (%lu) requested.\n",
+ | ^~~~~~
+./include/linux/kern_levels.h:5:25: error: format '%lu' expects argument of type 'long unsigned int', but argument 2 has type 'unsigned int' [-Werror=format=]
+ 5 | #define KERN_SOH "\001" /* ASCII Start Of Header */
+ | ^~~~~~
+./include/linux/printk.h:422:25: note: in definition of macro 'printk_index_wrap'
+ 422 | _p_func(_fmt, ##__VA_ARGS__); \
+ | ^~~~
+./include/linux/printk.h:132:17: note: in expansion of macro 'printk'
+ 132 | printk(fmt, ##__VA_ARGS__); \
+ | ^~~~~~
+./include/linux/printk.h:580:9: note: in expansion of macro 'no_printk'
+ 580 | no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
+ | ^~~~~~~~~
+./include/linux/kern_levels.h:15:25: note: in expansion of macro 'KERN_SOH'
+ 15 | #define KERN_DEBUG KERN_SOH "7" /* debug-level messages */
+ | ^~~~~~~~
+./include/linux/printk.h:580:19: note: in expansion of macro 'KERN_DEBUG'
+ 580 | no_printk(KERN_DEBUG pr_fmt(fmt), ##__VA_ARGS__)
+ | ^~~~~~~~~~
+drivers/staging/fsl_ppfe/pfe_cdev.c:57:9: note: in expansion of macro 'pr_debug'
+ 57 | pr_debug("Read of (%lu) bytes performed.\n", sizeof(link_states));
+ | ^~~~~~~~
+cc1: all warnings being treated as errors
+
+In file included from ./include/uapi/linux/posix_types.h:5,
+ from ./include/uapi/linux/types.h:14,
+ from ./include/linux/types.h:6,
+ from ./include/linux/list.h:5,
+ from ./include/linux/module.h:12,
+ from drivers/staging/fsl_ppfe/pfe_sysfs.c:7:
+drivers/staging/fsl_ppfe/pfe_sysfs.c: In function 'pfe_set_util':
+./include/linux/stddef.h:8:14: error: passing argument 2 of 'kstrtoul' makes integer from pointer without a cast [-Werror=int-conversion]
+ 8 | #define NULL ((void *)0)
+ | ^~~~~~~~~~~
+ | |
+ | void *
+drivers/staging/fsl_ppfe/pfe_sysfs.c:538:39: note: in expansion of macro 'NULL'
+ 538 | util_do_clear = kstrtoul(buf, NULL, 0);
+ | ^~~~
+In file included from ./include/linux/kernel.h:13,
+ from ./include/linux/list.h:9:
+./include/linux/kstrtox.h:30:69: note: expected 'unsigned int' but argument is of type 'void *'
+ 30 | static inline int __must_check kstrtoul(const char *s, unsigned int base, unsigned long *res)
+ | ~~~~~~~~~~~~~^~~~
+cc1: all warnings being treated as errors
+
+With UTIL compiled on, fix compilation warning:
+drivers/staging/fsl_ppfe/pfe_hal.c: In function 'pe_load_ddr_section':
+drivers/staging/fsl_ppfe/pfe_hal.c:617:19: error: 'else' without a previous 'if'
+ 617 | } else {
+ | ^~~~
+drivers/staging/fsl_ppfe/pfe_hal.c:622:17: error: break statement not within loop or switch
+ 622 | break;
+ | ^~~~~
+drivers/staging/fsl_ppfe/pfe_hal.c:624:9: error: case label not within a switch statement
+ 624 | case SHT_NOBITS:
+ | ^~~~
+drivers/staging/fsl_ppfe/pfe_hal.c:627:17: error: break statement not within loop or switch
+ 627 | break;
+ | ^~~~~
+drivers/staging/fsl_ppfe/pfe_hal.c:629:9: error: 'default' label not within a switch statement
+ 629 | default:
+ | ^~~~~~~
+drivers/staging/fsl_ppfe/pfe_hal.c: At top level:
+drivers/staging/fsl_ppfe/pfe_hal.c:635:9: error: expected identifier or '(' before 'return'
+ 635 | return 0;
+ | ^~~~~~
+drivers/staging/fsl_ppfe/pfe_hal.c:636:1: error: expected identifier or '(' before '}' token
+ 636 | }
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
+---
+ drivers/staging/fsl_ppfe/pfe_cdev.c | 6 +++---
+ drivers/staging/fsl_ppfe/pfe_hif.c | 14 +++++++-------
+ drivers/staging/fsl_ppfe/pfe_sysfs.c | 2 +-
+ 3 files changed, 11 insertions(+), 11 deletions(-)
+
+--- a/drivers/staging/fsl_ppfe/pfe_cdev.c
++++ b/drivers/staging/fsl_ppfe/pfe_cdev.c
+@@ -34,7 +34,7 @@ static ssize_t pfe_cdev_read(struct file
+ {
+ int ret = 0;
+
+- pr_info("PFE CDEV attempt copying (%lu) size of user.\n",
++ pr_info("PFE CDEV attempt copying (%zu) size of user.\n",
+ sizeof(link_states));
+
+ pr_debug("Dump link_state on screen before copy_to_user\n");
+@@ -47,14 +47,14 @@ static ssize_t pfe_cdev_read(struct file
+ /* Copy to user the value in buffer sized len */
+ ret = copy_to_user(buf, &link_states, sizeof(link_states));
+ if (ret != 0) {
+- pr_err("Failed to send (%d)bytes of (%lu) requested.\n",
++ pr_err("Failed to send (%d)bytes of (%zu) requested.\n",
+ ret, len);
+ return -EFAULT;
+ }
+
+ /* offset set back to 0 as there is contextual reading offset */
+ *off = 0;
+- pr_debug("Read of (%lu) bytes performed.\n", sizeof(link_states));
++ pr_debug("Read of (%zu) bytes performed.\n", sizeof(link_states));
+
+ return sizeof(link_states);
+ }
+--- a/drivers/staging/fsl_ppfe/pfe_hif.c
++++ b/drivers/staging/fsl_ppfe/pfe_hif.c
+@@ -115,11 +115,11 @@ static void send_dummy_pkt_to_hif(void)
+ 0x33221100, 0xa8c05544, 0x00000301, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0xbe86c51f };
+
+- ddr_ptr = (void *)((u64)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL));
++ ddr_ptr = (void *)((uintptr_t)readl(BMU2_BASE_ADDR + BMU_ALLOC_CTRL));
+ if (!ddr_ptr)
+ return;
+
+- lmem_ptr = (void *)((u64)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL));
++ lmem_ptr = (void *)((uintptr_t)readl(BMU1_BASE_ADDR + BMU_ALLOC_CTRL));
+ if (!lmem_ptr)
+ return;
+
+@@ -186,16 +186,16 @@ static void pfe_hif_free_descr(struct pf
+ void pfe_hif_desc_dump(struct pfe_hif *hif)
+ {
+ struct hif_desc *desc;
+- unsigned long desc_p;
++ u64 desc_p;
+ int ii = 0;
+
+ pr_info("%s\n", __func__);
+
+ desc = hif->rx_base;
+- desc_p = (u32)((u64)desc - (u64)hif->descr_baseaddr_v +
++ desc_p = ((void *)desc - hif->descr_baseaddr_v +
+ hif->descr_baseaddr_p);
+
+- pr_info("HIF Rx desc base %p physical %x\n", desc, (u32)desc_p);
++ pr_info("HIF Rx desc base %p physical %llx\n", desc, desc_p);
+ for (ii = 0; ii < hif->rx_ring_size; ii++) {
+ pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n",
+ readl(&desc->status), readl(&desc->ctrl),
+@@ -204,10 +204,10 @@ void pfe_hif_desc_dump(struct pfe_hif *h
+ }
+
+ desc = hif->tx_base;
+- desc_p = ((u64)desc - (u64)hif->descr_baseaddr_v +
++ desc_p = ((void *)desc - hif->descr_baseaddr_v +
+ hif->descr_baseaddr_p);
+
+- pr_info("HIF Tx desc base %p physical %x\n", desc, (u32)desc_p);
++ pr_info("HIF Tx desc base %p physical %llx\n", desc, desc_p);
+ for (ii = 0; ii < hif->tx_ring_size; ii++) {
+ pr_info("status: %08x, ctrl: %08x, data: %08x, next: %x\n",
+ readl(&desc->status), readl(&desc->ctrl),
+--- a/drivers/staging/fsl_ppfe/pfe_sysfs.c
++++ b/drivers/staging/fsl_ppfe/pfe_sysfs.c
+@@ -535,7 +535,7 @@ static ssize_t pfe_show_tmu3_queues(stru
+ static ssize_t pfe_set_util(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+ {
+- util_do_clear = kstrtoul(buf, NULL, 0);
++ util_do_clear = kstrtoul(buf, 0, 0);
+ return count;
+ }
+
INITRAMFS_EXTRA_FILES:=
FEATURES:=cpiogz ext4 ramdisk squashfs targz
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
include $(INCLUDE_DIR)/target.mk
+++ /dev/null
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_KEEP_MEMBLOCK=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_MMAP_RND_BITS_MAX=15
-CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
-CONFIG_ATA=y
-CONFIG_ATA_PIIX=y
-CONFIG_BLK_DEV_BSG=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOARD_SCACHE=y
-CONFIG_BOOT_ELF32=y
-CONFIG_BUILTIN_DTB=y
-CONFIG_CEVT_R4K=y
-CONFIG_CLKBLD_I8253=y
-CONFIG_CLKEVT_I8253=y
-CONFIG_CLKSRC_I8253=y
-CONFIG_CLKSRC_MIPS_GIC=y
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPAT_32BIT_TIME=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CPU_GENERIC_DUMP_TLB=y
-CONFIG_CPU_HAS_PREFETCH=y
-# CONFIG_CPU_HAS_SMARTMIPS is not set
-CONFIG_CPU_HAS_SYNC=y
-# CONFIG_CPU_MICROMIPS is not set
-# CONFIG_CPU_MIPS32 is not set
-# CONFIG_CPU_MIPS32_3_5_FEATURES is not set
-# CONFIG_CPU_MIPS32_R1 is not set
-# CONFIG_CPU_MIPS32_R2 is not set
-# CONFIG_CPU_MIPS32_R5 is not set
-# CONFIG_CPU_MIPS32_R5_FEATURES is not set
-# CONFIG_CPU_MIPS32_R6 is not set
-# CONFIG_CPU_MIPS64_R1 is not set
-# CONFIG_CPU_MIPS64_R2 is not set
-# CONFIG_CPU_MIPS64_R6 is not set
-# CONFIG_CPU_MIPSR1 is not set
-# CONFIG_CPU_MIPSR2 is not set
-# CONFIG_CPU_MIPSR2_IRQ_EI is not set
-# CONFIG_CPU_MIPSR2_IRQ_VI is not set
-CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
-# CONFIG_CPU_NEVADA is not set
-CONFIG_CPU_R4K_CACHE_TLB=y
-# CONFIG_CPU_RM7000 is not set
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
-CONFIG_CPU_SUPPORTS_HIGHMEM=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CSRC_R4K=y
-CONFIG_DMA_NONCOHERENT=y
-CONFIG_DNOTIFY=y
-CONFIG_DTC=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_GENERIC_ATOMIC64=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_FIND_FIRST_BIT=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_CHIP=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_LIB_ASHLDI3=y
-CONFIG_GENERIC_LIB_ASHRDI3=y
-CONFIG_GENERIC_LIB_CMPDI2=y
-CONFIG_GENERIC_LIB_LSHRDI3=y
-CONFIG_GENERIC_LIB_UCMPDI2=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SCHED_CLOCK=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GLOB=y
-CONFIG_HANDLE_DOMAIN_IRQ=y
-CONFIG_HARDWARE_WATCHPOINTS=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HW_CONSOLE=y
-CONFIG_I8253=y
-CONFIG_I8253_LOCK=y
-CONFIG_I8259=y
-CONFIG_INPUT=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_IRQCHIP=y
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_MIPS_CPU=y
-CONFIG_IRQ_WORK=y
-CONFIG_ISA_DMA_API=y
-CONFIG_JBD2=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_KALLSYMS=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_XZ is not set
-CONFIG_LIBFDT=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-CONFIG_MD=y
-CONFIG_MEMFD_CREATE=y
-CONFIG_MFD_SYSCON=y
-CONFIG_MIGRATION=y
-CONFIG_MIPS=y
-CONFIG_MIPS_ASID_BITS=8
-CONFIG_MIPS_ASID_SHIFT=0
-CONFIG_MIPS_BONITO64=y
-CONFIG_MIPS_CLOCK_VSYSCALL=y
-CONFIG_MIPS_CM=y
-CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
-CONFIG_MIPS_CPC=y
-CONFIG_MIPS_CPU_SCACHE=y
-CONFIG_MIPS_EBPF_JIT=y
-CONFIG_MIPS_EXTERNAL_TIMER=y
-CONFIG_MIPS_GIC=y
-CONFIG_MIPS_L1_CACHE_SHIFT=6
-CONFIG_MIPS_L1_CACHE_SHIFT_6=y
-CONFIG_MIPS_LD_CAN_LINK_VDSO=y
-CONFIG_MIPS_MALTA=y
-CONFIG_MIPS_MSC=y
-CONFIG_MIPS_MT=y
-CONFIG_MIPS_MT_FPAFF=y
-CONFIG_MIPS_MT_SMP=y
-CONFIG_MIPS_NO_APPENDED_DTB=y
-CONFIG_MIPS_NR_CPU_NR_MAP=2
-CONFIG_MIPS_PERF_SHARED_TC_COUNTERS=y
-CONFIG_MODULES_USE_ELF_REL=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MTD_CFI_STAA=y
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NLS=y
-CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
-CONFIG_NO_HZ=y
-CONFIG_NO_HZ_COMMON=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_NR_CPUS=2
-CONFIG_NVMEM=y
-CONFIG_OF=y
-CONFIG_OF_ADDRESS=y
-CONFIG_OF_EARLY_FLATTREE=y
-CONFIG_OF_FLATTREE=y
-CONFIG_OF_IRQ=y
-CONFIG_OF_KOBJ=y
-CONFIG_PADATA=y
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_PATA_LEGACY=y
-CONFIG_PATA_TIMINGS=y
-CONFIG_PCI=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_DRIVERS_LEGACY=y
-CONFIG_PCI_GT64XXX_PCI0=y
-CONFIG_PCSPKR_PLATFORM=y
-CONFIG_PERF_USE_VMALLOC=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_PIIX4_POWEROFF=y
-CONFIG_POWER_RESET_SYSCON=y
-CONFIG_PRINT_QUOTA_WARNING=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-CONFIG_QFMT_V2=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_QUOTA=y
-CONFIG_QUOTACTL=y
-CONFIG_QUOTA_TREE=y
-CONFIG_RATIONAL=y
-CONFIG_REGMAP=y
-CONFIG_REGMAP_MMIO=y
-CONFIG_RELAY=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SATA_HOST=y
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SECCOMP=y
-CONFIG_SECCOMP_FILTER=y
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-CONFIG_SMP=y
-CONFIG_SMP_UP=y
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SRCU=y
-CONFIG_SWAP_IO_SPACE=y
-CONFIG_SYNC_R4K=y
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
-CONFIG_SYS_HAS_CPU_MIPS32_R2=y
-CONFIG_SYS_HAS_CPU_MIPS32_R3_5=y
-CONFIG_SYS_HAS_CPU_MIPS32_R5=y
-CONFIG_SYS_HAS_CPU_MIPS32_R6=y
-CONFIG_SYS_HAS_CPU_MIPS64_R1=y
-CONFIG_SYS_HAS_CPU_MIPS64_R2=y
-CONFIG_SYS_HAS_CPU_MIPS64_R6=y
-CONFIG_SYS_HAS_CPU_NEVADA=y
-CONFIG_SYS_HAS_CPU_RM7000=y
-CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
-CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
-CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
-CONFIG_SYS_SUPPORTS_HIGHMEM=y
-CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
-CONFIG_SYS_SUPPORTS_MICROMIPS=y
-CONFIG_SYS_SUPPORTS_MIPS16=y
-CONFIG_SYS_SUPPORTS_MIPS_CMP=y
-CONFIG_SYS_SUPPORTS_MIPS_CPS=y
-CONFIG_SYS_SUPPORTS_MULTITHREADING=y
-CONFIG_SYS_SUPPORTS_RELOCATABLE=y
-CONFIG_SYS_SUPPORTS_SCHED_SMT=y
-CONFIG_SYS_SUPPORTS_SMARTMIPS=y
-CONFIG_SYS_SUPPORTS_SMP=y
-CONFIG_SYS_SUPPORTS_VPE_LOADER=y
-CONFIG_SYS_SUPPORTS_ZBOOT=y
-CONFIG_TARGET_ISA_REV=1
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TIMER_OF=y
-CONFIG_TIMER_PROBE=y
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USE_OF=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-CONFIG_VXFS_FS=y
-CONFIG_WAR_ICACHE_REFILLS=y
-CONFIG_XPS=y
-CONFIG_ZBOOT_LOAD_ADDRESS=0x0
compatible = "cudy,m3000-v1", "mediatek,mt7981-spim-snand-rfb";
aliases {
- ethernet0 = &gmac0;
label-mac-device = &gmac0;
led-boot = &led_status;
led-failsafe = &led_status;
phy-mode = "2500base-x";
phy-handle = <&rtl8221b_phy>;
- /* the MAC address assignment using nvmem-cells doesn't work, so it's done through 02_network */
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_bdinfo_de00 1>;
};
gmac1: mac@1 {
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+#include "mt7981.dtsi"
+
+/ {
+ model = "OpenWrt One";
+ compatible = "openwrt,one", "mediatek,mt7981";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ serial0 = &uart0;
+ led-boot = &led_status_white;
+ led-failsafe = &led_status_red;
+ led-running = &led_status_green;
+ led-upgrade = &led_status_green;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ rootdisk = <&ubi_fit_volume>;
+ };
+
+ memory {
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ user {
+ label = "user";
+ linux,code = <BTN_0>;
+ gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ led_status_white: led-0 {
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_STATUS;
+ pwms = <&pwm 0 10000>;
+ linux,default-trigger = "pattern";
+ led-pattern = <0 500 25 500>;
+ };
+
+ led_status_green: led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ pwms = <&pwm 1 10000>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ led_status_red: led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&pio 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_AMBER>;
+ gpios = <&pio 34 GPIO_ACTIVE_LOW>;
+ };
+
+ led-2 {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ gpios = <&pio 35 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-export {
+ compatible = "gpio-export";
+
+ gpio-0 {
+ gpio-export,name = "mikrobus-reset";
+ gpio-export,output = <1>;
+ gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-1 {
+ gpio-export,name = "watchdog-enable";
+ gpio-export,output = <1>;
+ gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ gpio-2 {
+ gpio-export,name = "usb-enable";
+ gpio-export,output = <1>;
+ gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ gpio-watchdog {
+ compatible = "linux,wdt-gpio";
+ gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+ hw_algo = "toggle";
+ hw_margin_ms = <25000>;
+ always-running;
+ };
+};
+
+ð {
+ status = "okay";
+
+ gmac0: mac@0 {
+ compatible = "mediatek,eth-mac";
+ reg = <0>;
+ phy-handle = <&phy15>;
+ phy-mode = "2500base-x";
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_factory_4>;
+ };
+
+ gmac1: mac@1 {
+ compatible = "mediatek,eth-mac";
+ reg = <1>;
+ phy-mode = "gmii";
+ phy-handle = <&int_gbe_phy>;
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&macaddr_factory_a>;
+ };
+};
+
+&mdio_bus {
+ phy15: phy@f {
+ reg = <0xf>;
+
+ airoha,pnswap-rx;
+
+ interrupt-parent = <&pio>;
+ interrupts = <38 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&pio 39 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <20000>;
+
+ phy-mode = "2500base-x";
+ full-duplex;
+ pause;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_AMBER>;
+ };
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+ };
+ };
+};
+
+&crypto {
+ status = "okay";
+};
+
+&pio {
+ spi0_flash_pins: spi0-pins {
+ mux {
+ function = "spi";
+ groups = "spi0", "spi0_wp_hold";
+ };
+
+ conf-pu {
+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
+ };
+
+ spi1_flash_pins: spi1-pins {
+ mux {
+ function = "spi";
+ groups = "spi1_1";
+ };
+
+ conf-pu {
+ pins = "SPI1_CS";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
+ };
+
+ spi2_flash_pins: spi2-pins {
+ mux {
+ function = "spi";
+ groups = "spi2";
+ };
+
+ conf-pu {
+ pins = "SPI2_CS", "SPI2_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+ };
+
+ conf-pd {
+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+ };
+ };
+
+ i2c_pins: i2c-pins {
+ mux {
+ function = "i2c";
+ groups = "i2c0_0";
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2_0_tx_rx";
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0_0", "pwm1_1";
+ };
+ };
+
+ pcie_pins: pcie-pins {
+ mux {
+ function = "pcie";
+ groups = "pcie_pereset";
+ };
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c_pins>;
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ cs-gpios = <0>, <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <52000000>;
+
+ spi-cal-enable;
+ spi-cal-mode = "read-data";
+ spi-cal-datalen = <7>;
+ spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
+ spi-cal-addrlen = <5>;
+ spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@580000 {
+ label = "ubi";
+ reg = <0x100000 0x7F00000>;
+ compatible = "linux,ubi";
+
+ volumes {
+ ubi_fit_volume: ubi-volume-fit {
+ volname = "fit";
+ };
+ };
+ };
+ };
+ };
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_flash_pins>;
+ status = "okay";
+};
+
+&spi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2_flash_pins>;
+ status = "okay";
+
+ flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+
+ spi-max-frequency = <52000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2-nor";
+ reg = <0x00000 0x40000>;
+ };
+
+ partition@40000 {
+ label = "factory";
+ reg = <0x40000 0xc0000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory_0: eeprom@0 {
+ reg = <0x0 0x1000>;
+ };
+
+ macaddr_factory_4: macaddr@4 {
+ compatible = "mac-base";
+ reg = <0x24 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ macaddr_factory_a: macaddr@a {
+ compatible = "mac-base";
+ reg = <0x2a 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ partition@100000 {
+ label = "fip-nor";
+ reg = <0x100000 0x80000>;
+ };
+
+ partition@180000 {
+ label = "recovery";
+ reg = <0x180000 0xc80000>;
+ };
+ };
+ };
+};
+
+&xhci {
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ vusb33-supply = <®_3p3v>;
+ vbus-supply = <®_5v>;
+ mediatek,u3p-dis-msk = <0x01>;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+};
+
+&usb_phy {
+ status = "okay";
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&wifi {
+ nvmem-cells = <&eeprom_factory_0>;
+ nvmem-cell-names = "eeprom";
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie_pins>;
+ status = "okay";
+};
+
+&sgmiisys0 {
+ /delete-node/ mediatek,pnswap;
+};
model = "YunCore AX835";
aliases {
- ethernet0 = &gmac0;
led-boot = &led_system;
led-failsafe = &led_system;
led-running = &led_system;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 SmartRG Inc.
+ * Author: Chad Monroe <chad.monroe@smartrg.com>
+ */
+
+#include "mt7988a-smartrg-mt-stuart.dtsi"
+
+/ {
+ model = "SmartRG SDG-8733";
+ compatible = "smartrg,sdg-8733", "mediatek,mt7988a";
+};
+
+&gmac1 {
+ phy-connection-type = "usxgmii";
+ phy = <&phy0>;
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 SmartRG Inc.
+ * Author: Chad Monroe <chad.monroe@smartrg.com>
+ */
+
+#include "mt7988a-smartrg-mt-stuart.dtsi"
+
+/ {
+ model = "SmartRG SDG-8734";
+ compatible = "smartrg,sdg-8734", "mediatek,mt7988a";
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ sfp_green {
+ color = <LED_COLOR_ID_GREEN>;
+ function = "sfp";
+ gpios = <&pio 69 GPIO_ACTIVE_HIGH>;
+ };
+
+ sfp_red {
+ color = <LED_COLOR_ID_RED>;
+ function = "sfp";
+ gpios = <&pio 70 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ i2c_sfp1: i2c-gpio-0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sfp_i2c_pins>;
+
+ compatible = "i2c-gpio";
+ sda-gpios = <&pio 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ scl-gpios = <&pio 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ i2c-gpio,delay-us = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ sfp1: sfp1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&i2c_sfp1>;
+ los-gpios = <&pio 32 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpios = <&pio 35 GPIO_ACTIVE_LOW>;
+ rate-select0-gpios = <&pio 34 GPIO_ACTIVE_HIGH>;
+ rate-select1-gpios = <&pio 33 GPIO_ACTIVE_HIGH>;
+ tx-disable-gpios = <&pio 36 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpios = <&pio 37 GPIO_ACTIVE_HIGH>;
+ maximum-power-milliwatt = <4000>;
+ };
+};
+
+&gmac1 {
+ sfp = <&sfp1>;
+ managed = "in-band-status";
+};
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 SmartRG Inc.
+ * Author: Chad Monroe <chad.monroe@smartrg.com>
+ */
+
+/dts-v1/;
+#include "mt7988a.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+#include <dt-bindings/regulator/richtek,rt5190a-regulator.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ led-boot = &led_sys_green;
+ led-failsafe = &led_sys_blue;
+ led-running = &led_sys_white;
+ led-upgrade = &led_sys_red;
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ bootargs = "console=ttyS0,115200n1 loglevel=8 pci=pcie_bus_perf root=PARTLABEL=rootfs";
+ };
+
+ memory {
+ reg = <0x0 0x40000000 0x0 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /delete-node/ramoops@42ff0000;
+
+ bootdata@45000000 {
+ no-map;
+ reg = <0x0 0x45000000 0x0 0x00001000>;
+ };
+
+ ramoops_reserved: ramoops@45001000 {
+ no-map;
+ compatible = "ramoops";
+ reg = <0x0 0x45001000 0x0 0x00140000>;
+ ftrace-size = <0x20000>;
+ record-size = <0x20000>;
+ console-size = <0x20000>;
+ pmsg-size = <0x80000>;
+ };
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&button_pins>;
+
+ factory {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&pio 13 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "sync";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&pio 14 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio-export {
+ compatible = "gpio-export";
+
+ bluetooth_reset {
+ gpio-export,name = "bt_reset";
+ gpio-export,direction_may_change;
+ gpios = <&pio 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ bluetooth_txrx_ctl {
+ gpio-export,name = "bt_txrx_ctl";
+ gpio-export,direction_may_change;
+ gpios = <&pio 74 GPIO_ACTIVE_HIGH>;
+ };
+
+ gps_enable {
+ gpio-export,name = "gps_enable";
+ gpio-export,output = <1>;
+ gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ slic_interrupt {
+ gpio-export,name = "slic_interrupt";
+ gpio-export,direction_may_change;
+ gpios = <&pio 54 GPIO_ACTIVE_HIGH>;
+ };
+
+ slic_reset {
+ gpio-export,name = "slic_reset";
+ gpio-export,output = <0>;
+ gpios = <&pio 72 GPIO_ACTIVE_HIGH>;
+ };
+
+ usb_enable {
+ gpio-export,name = "usb_enable";
+ gpio-export,output = <1>;
+ gpios = <&pio 63 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+&cpu0 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu1 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu2 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu3 {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cci {
+ proc-supply = <&rt5190_buck3>;
+};
+
+&cpu_thermal {
+ /delete-node/cooling-maps;
+ /delete-node/trips;
+
+ trips {
+ cpu_trip_crit: crit {
+ temperature = <125000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+
+ cpu_trip_hot: hot {
+ temperature = <120000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ cpu_trip_active_high: active-high {
+ temperature = <110000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_med: active-med {
+ temperature = <80000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_low: active-low {
+ temperature = <60000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_trip_active_silent: active-silent {
+ temperature = <40000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ cpu-active-high {
+ /* active: set fan to cooling level 3 */
+ cooling-device = <&fan 3 3>;
+ trip = <&cpu_trip_active_high>;
+ };
+
+ cpu-active-med {
+ /* active: set fan to cooling level 2 */
+ cooling-device = <&fan 2 2>;
+ trip = <&cpu_trip_active_med>;
+ };
+
+ cpu-active-low {
+ /* active: set fan to cooling level 1 */
+ cooling-device = <&fan 1 1>;
+ trip = <&cpu_trip_active_low>;
+ };
+
+ cpu-active-silent {
+ /* active: set fan to cooling level 0 */
+ cooling-device = <&fan 0 0>;
+ trip = <&cpu_trip_active_silent>;
+ };
+ };
+};
+
+ð {
+ pinctrl-0 = <&mdio0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&fan {
+ pwms = <&pwm 0 40000 0>;
+
+ /**
+ * set fan speed
+ *
+ * 0 = off
+ * 61 = 24% duty cycle
+ * 77 = 30% duty cycle
+ * 102 = 40% duty cycle
+ * 128 - 50% duty cycle
+ * 255 = 100% duty cycle
+ */
+ cooling-levels = <61 77 102 128>;
+
+ interrupt-parent = <&pio>;
+ interrupts = <21 IRQ_TYPE_EDGE_FALLING>;
+ pulses-per-revolution = <2>;
+
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+};
+
+&gmac1 {
+ label = "wan";
+ status = "okay";
+ phy-mode = "usxgmii";
+};
+
+&gmac2 {
+ label = "lan1";
+ status = "okay";
+ phy-mode = "usxgmii";
+ phy-connection-type = "usxgmii";
+ phy = <&phy8>;
+};
+
+&gsw_phy0 {
+ status = "disabled";
+};
+
+&gsw_phy1 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe1_led0_pins>, <&gbe1_led1_pins>;
+};
+
+&gsw_phy1_led0 {
+ status = "okay";
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy1_led1 {
+ status = "okay";
+ color = <LED_COLOR_ID_AMBER>;
+};
+
+&gsw_phy2 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe2_led0_pins>, <&gbe2_led1_pins>;
+};
+
+&gsw_phy2_led0 {
+ status = "okay";
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy2_led1 {
+ status = "okay";
+ color = <LED_COLOR_ID_AMBER>;
+};
+
+&gsw_phy3 {
+ pinctrl-names = "gbe-led";
+ pinctrl-0 = <&gbe3_led0_pins>, <&gbe3_led1_pins>;
+};
+
+&gsw_phy3_led0 {
+ status = "okay";
+ color = <LED_COLOR_ID_GREEN>;
+};
+
+&gsw_phy3_led1 {
+ status = "okay";
+ color = <LED_COLOR_ID_AMBER>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+
+ rt5190a_64: rt5190a@64 {
+ compatible = "richtek,rt5190a";
+ reg = <0x64>;
+ /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
+ vin2-supply = <&rt5190_buck1>;
+ vin3-supply = <&rt5190_buck1>;
+ vin4-supply = <&rt5190_buck1>;
+
+ regulators {
+ rt5190_buck1: buck1 {
+ regulator-name = "rt5190a-buck1";
+ regulator-min-microvolt = <5090000>;
+ regulator-max-microvolt = <5090000>;
+ regulator-allowed-modes =
+ <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ buck2 {
+ regulator-name = "vcore";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ rt5190_buck3: buck3 {
+ regulator-name = "vproc";
+ regulator-min-microvolt = <600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ };
+ buck4 {
+ regulator-name = "rt5190a-buck4";
+ regulator-min-microvolt = <850000>;
+ regulator-max-microvolt = <850000>;
+ regulator-allowed-modes =
+ <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ ldo {
+ regulator-name = "rt5190a-ldo";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ status = "okay";
+
+ system-leds {
+ compatible = "srg,sysled";
+ reg = <0x30>;
+
+ led_sys_red: system_red {
+ label = "red";
+ reg = <1>;
+ };
+
+ led_sys_green: system_green {
+ label = "green";
+ reg = <2>;
+ };
+
+ led_sys_blue: system_blue {
+ label = "blue";
+ reg = <3>;
+ };
+
+ led_sys_white: system_white {
+ label = "white";
+ reg = <4>;
+ };
+ };
+};
+
+&mdio_bus {
+ phy0: ethernet-phy@0 {
+ /* AQR113C */
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+
+ reset-gpios = <&pio 62 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <100000>;
+ reset-deassert-us = <1000000>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_ORANGE>;
+ };
+
+ led@2 {
+ reg = <2>;
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_WHITE>;
+ active-low;
+ };
+ };
+ };
+
+ phy8: ethernet-phy@8 {
+ /* AQR113C */
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+
+ reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <100000>;
+ reset-deassert-us = <1000000>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led@1 {
+ reg = <1>;
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_ORANGE>;
+ };
+
+ led@2 {
+ reg = <2>;
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_WHITE>;
+ active-low;
+ };
+ };
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_emmc_51>;
+ pinctrl-1 = <&mmc0_pins_emmc_51>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ hs400-ds-delay = <0x12814>;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ card@0 {
+ #address-cells = <0>;
+ #size-cells = <0>;
+ compatible = "mmc-card";
+ reg = <0>;
+
+ block {
+ compatible = "block-device";
+
+ partitions {
+ block-partition-factory {
+ partname = "factory";
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory_0: eeprom@0 {
+ reg = <0x0 0x1e00>;
+ };
+ };
+ };
+ };
+ };
+ };
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_1_pins>;
+ reset-gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+
+ mt7996@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cells = <&eeprom_factory_0>;
+ nvmem-cell-names = "eeprom";
+ ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>, <5945000 7125000>;
+ };
+ };
+};
+
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_pins>;
+ status = "okay";
+};
+
+&pcie2 {
+ status = "disabled";
+};
+
+&pcie3 {
+ status = "disabled";
+};
+
+&pio {
+ button_pins: button-pins {
+ pins = "GPIO_RESET", "GPIO_WPS";
+ mediatek,pull-down-adv = <0>; /* bias-disable */
+ };
+
+ pcie0_1_pins: pcie0-pins-g1 {
+ mux {
+ function = "pcie";
+ groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0";
+ };
+ };
+
+ pwm_pins: pwm-pins {
+ mux {
+ function = "pwm";
+ groups = "pwm0", "pwm1";
+ };
+ };
+
+ sfp_i2c_pins: sfp-i2c-pins {
+ conf-scl {
+ pins = "LED_A";
+ drive-strength = <8>;
+ mediatek,pull-up-adv = <1>;
+ };
+ conf-sda {
+ pins = "LED_E";
+ drive-strength = <8>;
+ mediatek,pull-up-adv = <0>;
+ };
+ };
+
+ uart1_pins: uart1-pins {
+ mux {
+ function = "uart";
+ groups = "uart1_2";
+ };
+ };
+
+ uart2_pins: uart2-pins {
+ mux {
+ function = "uart";
+ groups = "uart2";
+ };
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_flash_pins>;
+ status = "disabled";
+
+ spi_nand: spi_nand@0 {
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+ spi-tx-buswidth = <4>;
+ spi-rx-buswidth = <4>;
+ };
+
+};
+
+&ssusb0 {
+ status = "okay";
+};
+
+&ssusb1 {
+ status = "okay";
+};
+
+&switch {
+ status = "okay";
+
+ ports {
+ port@0 {
+ status = "disabled";
+ };
+
+ port@1 {
+ label = "lan2";
+ };
+
+ port@2 {
+ label = "lan3";
+ };
+
+ port@3 {
+ label = "lan4";
+ };
+ };
+};
+
+&tphy {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+
+ /* Airoha AG3352 GPS */
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "okay";
+
+ /* DA14531MOD Bluetooth */
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&xphy {
+ status = "okay";
+};
pcie: pcie@11280000 {
compatible = "mediatek,mt7981-pcie",
- "mediatek,mt7986-pcie";
+ "mediatek,mt8192-pcie";
reg = <0 0x11280000 0 0x4000>;
reg-names = "pcie-mac";
ranges = <0x82000000 0 0x20000000
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
+ firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
reset-gpios = <&pio 72 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
phy8: ethernet-phy@8 {
reg = <8>;
compatible = "ethernet-phy-ieee802.3-c45";
+ firmware-name = "AQR-G4_v5.7.0-AQR_EVB_Generic_X3410_StdCfg_MDISwap_USX_ID46316_VER2140.cld";
reset-gpios = <&pio 71 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
reset-deassert-us = <221000>;
--- /dev/null
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ compatible = "mediatek,mt7988a-rfb", "mediatek,mt7988a";
+
+ fragment@0 {
+ target = <&ubi_part>;
+
+ __overlay__ {
+ volumes {
+ ubi_factory: ubi-volume-factory {
+ volname = "factory";
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_wmac: eeprom@0 {
+ reg = <0x0 0x1e00>;
+ };
+
+ gmac2_mac: eeprom@fffee {
+ reg = <0xfffee 0x6>;
+ };
+
+ gmac1_mac: eeprom@ffff4 {
+ reg = <0xffff4 0x6>;
+ };
+
+ gmac0_mac: eeprom@ffffa {
+ reg = <0xffffa 0x6>;
+ };
+ };
+ };
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&pcie0>;
+ __overlay__ {
+ pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+
+ wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cell-names = "eeprom";
+ nvmem-cells = <&eeprom_wmac>;
+ };
+ };
+ };
+ };
+
+ fragment@2 {
+ target = <&gmac0>;
+ __overlay__ {
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&gmac0_mac>;
+ };
+ };
+
+ fragment@3 {
+ target = <&gmac1>;
+ __overlay__ {
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&gmac1_mac>;
+ };
+ };
+
+ fragment@4 {
+ target = <&gmac2>;
+ __overlay__ {
+ nvmem-cell-names = "mac-address";
+ nvmem-cells = <&gmac2_mac>;
+ };
+ };
+};
spi-max-frequency = <52000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
- mediatek,nmbm;
- mediatek,bmt-max-ratio = <1>;
- mediatek,bmt-max-reserved-blocks = <64>;
partitions {
compatible = "fixed-partitions";
partition@0 {
label = "BL2";
- reg = <0x00000 0x0100000>;
+ reg = <0x00000 0x0200000>;
read-only;
};
- partition@100000 {
- label = "u-boot-env";
- reg = <0x0100000 0x0080000>;
- };
+ ubi_part: partition@200000 {
+ label = "ubi";
+ reg = <0x0200000 0x7e00000>;
+ compatible = "linux,ubi";
- partition@180000 {
- label = "Factory";
- reg = <0x180000 0x0400000>;
- };
+ volumes {
+ ubi-volume-ubootenv {
+ volname = "ubootenv";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool-layout";
+ };
+ };
- partition@580000 {
- label = "FIP";
- reg = <0x580000 0x0200000>;
- };
+ ubi-volume-ubootenv2 {
+ volname = "ubootenv2";
+ nvmem-layout {
+ compatible = "u-boot,env-redundant-bool-layout";
+ };
+ };
- partition@780000 {
- label = "ubi";
- reg = <0x780000 0x7080000>;
+ ubi_root: ubi-volume-fit {
+ volname = "fit";
+ };
+
+ };
};
};
};
};
};
+
+ fragment@1 {
+ target-path = "/chosen";
+ __overlay__ {
+ rootdisk-spim-nand = <&ubi_root>;
+ };
+ };
};
ucidef_set_led_netdev "lanact" "LANACT" "green:lan" "eth1" "rx tx"
ucidef_set_led_netdev "lanlink" "LANLINK" "amber:lan" "eth1" "link"
;;
+openwrt,one)
+ ucidef_set_led_netdev "wanact" "WANACT" "mdio-bus:0f:green:wan" "eth0" "rx tx"
+ ucidef_set_led_netdev "wanlink" "WANLINK" "mdio-bus:0f:amber:wan" "eth0" "link"
+ ucidef_set_led_netdev "lanact" "LANACT" "green:lan" "eth1" "rx tx"
+ ucidef_set_led_netdev "lanlink" "LANLINK" "amber:lan" "eth1" "link"
+ ;;
routerich,ax3000)
ucidef_set_led_netdev "lan-1" "lan-1" "blue:lan-1" "lan1" "link tx rx"
ucidef_set_led_netdev "lan-2" "lan-2" "blue:lan-2" "lan2" "link tx rx"
ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" "link tx rx"
ucidef_set_led_netdev "wan-off" "wan-off" "red:wan" "wan" "link"
;;
+smartrg,sdg-8733|\
+smartrg,sdg-8734)
+ ucidef_set_led_netdev "lan-1-green" "LAN1" "mdio-bus:08:green:lan" "lan1" "link_2500 link_5000"
+ ucidef_set_led_netdev "lan-1-orange" "LAN1" "mdio-bus:08:orange:lan" "lan1" "link_100 link_1000"
+ ucidef_set_led_netdev "lan-1-white" "LAN1" "mdio-bus:08:white:lan" "lan1" "link_10000"
+ ucidef_set_led_netdev "lan-2-green" "LAN2" "mt7530-0:01:green:lan" "lan2" "link_1000"
+ ucidef_set_led_netdev "lan-2-amber" "LAN2" "mt7530-0:01:amber:lan" "lan2" "link_100 link_10"
+ ucidef_set_led_netdev "lan-3-green" "LAN3" "mt7530-0:02:green:lan" "lan3" "link_1000"
+ ucidef_set_led_netdev "lan-3-amber" "LAN3" "mt7530-0:02:amber:lan" "lan3" "link_100 link_10"
+ ucidef_set_led_netdev "lan-4-green" "LAN4" "mt7530-0:03:green:lan" "lan4" "link_1000"
+ ucidef_set_led_netdev "lan-4-amber" "LAN4" "mt7530-0:03:amber:lan" "lan4" "link_100 link_10"
+ ucidef_set_led_netdev "wan-green" "WAN" "mdio-bus:00:green:wan" "wan" "link_2500 link_5000"
+ ucidef_set_led_netdev "wan-orange" "WAN" "mdio-bus:00:orange:wan" "wan" "link_100 link_1000"
+ ucidef_set_led_netdev "wan-white" "WAN" "mdio-bus:00:white:wan" "wan" "link_10000"
+ ;;
xiaomi,mi-router-wr30u-stock|\
xiaomi,mi-router-wr30u-ubootmod)
ucidef_set_led_netdev "wan" "wan" "blue:wan" "wan" "link tx rx"
glinet,gl-mt3000|\
glinet,gl-x3000|\
glinet,gl-xe3000|\
- openembed,som7981)
+ openembed,som7981|\
+ openwrt,one)
ucidef_set_interfaces_lan_wan eth1 eth0
;;
dlink,aquila-pro-ai-m30-a1)
;;
esac
;;
- cudy,m3000-v1)
- wan_mac=$(macaddr_add $(cat /sys/class/net/eth1/address) 1)
- ;;
h3c,magic-nx30-pro)
wan_mac=$(mtd_get_mac_ascii pdt_data_1 ethaddr)
lan_mac=$(macaddr_add "$wan_mac" 1)
smartrg,sdg-8612|\
smartrg,sdg-8614|\
smartrg,sdg-8622|\
- smartrg,sdg-8632)
+ smartrg,sdg-8632|\
+ smartrg,sdg-8733|\
+ smartrg,sdg-8734)
label_mac=$(mmc_get_mac_ascii mfginfo MFG_MAC)
wan_mac=$label_mac
lan_mac=$(macaddr_add "$label_mac" 1)
;;
esac
;;
+ openwrt,one)
+ caldata_extract "factory" 0x0 0x1000
+ ;;
ubnt,unifi-6-plus)
caldata_extract_mmc "factory" 0x0 0x1000
;;
[ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "2" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress
;;
+ smartrg,sdg-8733|\
+ smartrg,sdg-8634)
+ addr=$(mmc_get_mac_ascii mfginfo MFG_MAC)
+ [ "$PHYNBR" = "0" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress
+ [ "$PHYNBR" = "1" ] && macaddr_add $addr a > /sys${DEVPATH}/macaddress
+ [ "$PHYNBR" = "2" ] && macaddr_add $addr 6 > /sys${DEVPATH}/macaddress
+ ;;
tplink,tl-xdr4288|\
tplink,tl-xdr6086|\
tplink,tl-xdr6088)
for dir in /sys/class/net/*; do
[ -r "$dir/of_node/label" ] || continue
- label="$(cat "$dir/of_node/label")"
- netdev="$(basename $dir)"
+ read -r label < "$dir/of_node/label"
+ netdev="${dir##*/}"
[ "$netdev" = "$label" ] && continue
ip link set "$netdev" name "$label"
done
ip link set dev eth1 address "$(macaddr_add $addr 1)"
;;
smartrg,sdg-8612|\
- smartrg,sdg-8614)
+ smartrg,sdg-8614|\
+ smartrg,sdg-8733|\
+ smartrg,sdg-8734)
addr=$(mmc_get_mac_ascii mfginfo MFG_MAC)
lan_addr=$(macaddr_add $addr 1)
ip link set dev wan address "$addr"
smartrg,sdg-8612|\
smartrg,sdg-8614|\
smartrg,sdg-8622|\
- smartrg,sdg-8632)
+ smartrg,sdg-8632|\
+ smartrg,sdg-8733|\
+ smartrg,sdg-8734)
CI_KERNPART="kernel"
CI_ROOTPART="rootfs"
emmc_do_upgrade "$1"
bananapi,bpi-r3-mini|\
bananapi,bpi-r4|\
bananapi,bpi-r4-poe|\
+ mediatek,mt7988a-rfb|\
jdcloud,re-cp-03|\
+ openwrt,one|\
tplink,tl-xdr4288|\
tplink,tl-xdr6086|\
tplink,tl-xdr6088|\
glinet,gl-x3000|\
glinet,gl-xe3000|\
jdcloud,re-cp-03|\
+ smartrg,sdg-8612|\
+ smartrg,sdg-8614|\
+ smartrg,sdg-8622|\
+ smartrg,sdg-8632|\
+ smartrg,sdg-8733|\
+ smartrg,sdg-8734|\
ubnt,unifi-6-plus)
emmc_copy_config
;;
CONFIG_IRQ_WORK=y
CONFIG_JBD2=y
CONFIG_JUMP_LABEL=y
+CONFIG_LEDS_PWM=y
CONFIG_LEDS_SMARTRG_LED=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
SUBTARGET:=filogic
BOARDNAME:=Filogic 8x0 (MT798x)
CPU_TYPE:=cortex-a53
-DEFAULT_PACKAGES += fitblk kmod-phy-aquantia kmod-crypto-hw-safexcel kmod-mt7915e wpad-basic-mbedtls uboot-envtools
+DEFAULT_PACKAGES += fitblk kmod-phy-aquantia kmod-crypto-hw-safexcel wpad-basic-mbedtls uboot-envtools
KERNELNAME:=Image dtbs
define Target/Description
DEVICE_MODEL := EW-7886CAX
DEVICE_DTS := mt7986a-acelink-ew-7886cax
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS := mt7986a-acer-predator-w6
DEVICE_DTS_DIR := ../dts
DEVICE_DTS_LOADADDR := 0x47000000
- DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware kmod-mt7916-firmware mt7986-wo-firmware e2fsprogs f2fsck mkf2fs
+ DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7916-firmware kmod-mt7986-firmware mt7986-wo-firmware e2fsprogs f2fsck mkf2fs
IMAGES := sysupgrade.bin
KERNEL := kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
KERNEL_INITRAMFS := kernel-bin | lzma | \
define Device/adtran_smartrg
DEVICE_VENDOR := Adtran
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-hwmon-pwmfan \
- kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-hwmon-pwmfan
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
$(call Device/adtran_smartrg)
DEVICE_MODEL := SDG-8612
DEVICE_DTS := mt7986a-smartrg-SDG-8612
+ DEVICE_PACKAGES += kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
endef
TARGET_DEVICES += smartrg_sdg-8612
$(call Device/adtran_smartrg)
DEVICE_MODEL := SDG-8614
DEVICE_DTS := mt7986a-smartrg-SDG-8614
+ DEVICE_PACKAGES += kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
endef
TARGET_DEVICES += smartrg_sdg-8614
$(call Device/adtran_smartrg)
DEVICE_MODEL := SDG-8622
DEVICE_DTS := mt7986a-smartrg-SDG-8622
- DEVICE_PACKAGES += kmod-mt7915-firmware
+ DEVICE_PACKAGES += kmod-mt7915e kmod-mt7915-firmware kmod-mt7986-firmware mt7986-wo-firmware
endef
TARGET_DEVICES += smartrg_sdg-8622
$(call Device/adtran_smartrg)
DEVICE_MODEL := SDG-8632
DEVICE_DTS := mt7986a-smartrg-SDG-8632
- DEVICE_PACKAGES += kmod-mt7915-firmware
+ DEVICE_PACKAGES += kmod-mt7915e kmod-mt7915-firmware kmod-mt7986-firmware mt7986-wo-firmware
endef
TARGET_DEVICES += smartrg_sdg-8632
+define Device/smartrg_sdg-8733
+$(call Device/adtran_smartrg)
+ DEVICE_MODEL := SDG-8733
+ DEVICE_DTS := mt7988a-smartrg-SDG-8733
+ DEVICE_PACKAGES += kmod-mt7996-firmware kmod-phy-aquantia kmod-usb3
+endef
+TARGET_DEVICES += smartrg_sdg-8733
+
+define Device/smartrg_sdg-8734
+$(call Device/adtran_smartrg)
+ DEVICE_MODEL := SDG-8734
+ DEVICE_DTS := mt7988a-smartrg-SDG-8734
+ DEVICE_PACKAGES += kmod-mt7996-firmware kmod-phy-aquantia kmod-sfp kmod-usb3
+endef
+TARGET_DEVICES += smartrg_sdg-8734
+
define Device/asus_rt-ax59u
DEVICE_VENDOR := ASUS
DEVICE_MODEL := RT-AX59U
DEVICE_DTS := mt7986a-asus-rt-ax59u
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
TARGET_DEVICES += asus_rt-ax59u
DEVICE_DTS := mt7986a-asus-tuf-ax4200
DEVICE_DTS_DIR := ../dts
DEVICE_DTS_LOADADDR := 0x47000000
- DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
IMAGES := sysupgrade.bin
KERNEL := kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
DEVICE_DTS := mt7986a-asus-tuf-ax6000
DEVICE_DTS_DIR := ../dts
DEVICE_DTS_LOADADDR := 0x47000000
- DEVICE_PACKAGES := kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
IMAGES := sysupgrade.bin
KERNEL := kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
mt7986a-bananapi-bpi-r3-respeaker-2mics
DEVICE_DTS_DIR := $(DTS_DIR)/
DEVICE_DTS_LOADADDR := 0x43f00000
- DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7986-firmware kmod-sfp kmod-usb3 \
+ DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-i2c-gpio kmod-mt7915e kmod-mt7986-firmware kmod-sfp kmod-usb3 \
e2fsprogs f2fsck mkf2fs mt7986-wo-firmware
IMAGES := sysupgrade.itb
KERNEL_LOADADDR := 0x44000000
DEVICE_DTS_CONFIG := config-mt7986a-bananapi-bpi-r3-mini
DEVICE_DTS_DIR := ../dts
DEVICE_DTS_LOADADDR := 0x43f00000
- DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-mt7986-firmware kmod-phy-airoha-en8811h \
+ DEVICE_PACKAGES := kmod-hwmon-pwmfan kmod-mt7915e kmod-mt7986-firmware kmod-phy-airoha-en8811h \
kmod-usb3 e2fsprogs f2fsck mkf2fs mt7986-wo-firmware
KERNEL_LOADADDR := 0x44000000
KERNEL := kernel-bin | gzip
DEVICE_DTS := mt7981b-cetron-ct3003
DEVICE_DTS_DIR := ../dts
SUPPORTED_DEVICES += mediatek,mt7981-spim-snand-rfb
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_DTS_DIR := ../dts
DEVICE_DTC_FLAGS := --pad 4096
DEVICE_DTS_LOADADDR := 0x43f00000
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 \
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 \
e2fsprogs f2fsck mkf2fs
KERNEL_LOADADDR := 0x44000000
KERNEL := kernel-bin | gzip
DEVICE_DTS_DIR := ../dts
DEVICE_DTC_FLAGS := --pad 4096
DEVICE_DTS_LOADADDR := 0x43f00000
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
KERNEL_LOADADDR := 0x44000000
KERNEL = kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
IMAGE_SIZE := 65536k
KERNEL_IN_UBI := 1
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
- DEVICE_PACKAGES := kmod-usb3 kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
endef
TARGET_DEVICES += confiabits_mt7981
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
endef
TARGET_DEVICES += cudy_m3000-v1
KERNEL_INITRAMFS := kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
endef
TARGET_DEVICES += cudy_re3000-v1
IMAGE_SIZE := 65536k
KERNEL_IN_UBI := 1
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
- DEVICE_PACKAGES := kmod-usb3 kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
endef
TARGET_DEVICES += cudy_tr3000-v1
KERNEL_INITRAMFS := kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
endef
TARGET_DEVICES += cudy_wr3000-v1
DEVICE_VARIANT := A1
DEVICE_DTS := mt7981b-dlink-aquila-pro-ai-m30-a1
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-leds-gca230718 kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-leds-gca230718 kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
KERNEL_IN_UBI := 1
IMAGES += recovery.bin
IMAGE_SIZE := 51200k
IMAGES := sysupgrade.bin factory.bin
IMAGE/factory.bin := append-ubi | check-size $$$$(IMAGE_SIZE)
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
endef
TARGET_DEVICES += edgecore_eap111
DEVICE_DTS := mt7981b-glinet-gl-mt2500
DEVICE_DTS_DIR := ../dts
DEVICE_DTS_LOADADDR := 0x47000000
- DEVICE_PACKAGES := -kmod-mt7915e -wpad-basic-mbedtls e2fsprogs f2fsck mkf2fs kmod-usb3
+ DEVICE_PACKAGES := -wpad-basic-mbedtls e2fsprogs f2fsck mkf2fs kmod-usb3
SUPPORTED_DEVICES += glinet,mt2500-emmc
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata
DEVICE_DTS := mt7981b-glinet-gl-mt3000
DEVICE_DTS_DIR := ../dts
SUPPORTED_DEVICES += glinet,mt3000-snand
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-hwmon-pwmfan kmod-usb3
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-hwmon-pwmfan kmod-usb3
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_MODEL := GL-MT6000
DEVICE_DTS := mt7986a-glinet-gl-mt6000
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
IMAGES += factory.bin
IMAGE/factory.bin := append-kernel | pad-to 32M | append-rootfs
IMAGE/sysupgrade.bin := sysupgrade-tar | append-gl-metadata
define Device/glinet_gl-x3000-xe3000-common
DEVICE_VENDOR := GL.iNet
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware mkf2fs \
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware mkf2fs \
kmod-fs-f2fs kmod-hwmon-pwmfan kmod-usb3 kmod-usb-serial-option \
kmod-usb-storage kmod-usb-net-qmi-wwan uqmi
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.itb := append-kernel | \
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
ARTIFACTS := preloader.bin bl31-uboot.fip
ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3
ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot h3c_magic-nx30-pro
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.itb := append-kernel | \
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
ARTIFACTS := preloader.bin bl31-uboot.fip
ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3
ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot jcg_q30-pro
DEVICE_DTS_DIR := ../dts
DEVICE_DTC_FLAGS := --pad 4096
DEVICE_DTS_LOADADDR := 0x43f00000
- DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware \
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware \
e2fsprogs f2fsck mkf2fs
KERNEL_LOADADDR := 0x44000000
KERNEL := kernel-bin | gzip
DEVICE_DTS_DIR := $(DTS_DIR)/
DEVICE_DTC_FLAGS := --pad 4096
DEVICE_DTS_LOADADDR := 0x43f00000
- DEVICE_PACKAGES := kmod-mt7981-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs mt7981-wo-firmware
KERNEL_LOADADDR := 0x44000000
KERNEL := kernel-bin | gzip
KERNEL_INITRAMFS := kernel-bin | lzma | \
DEVICE_MODEL := MT7986 rfba AP (NAND)
DEVICE_DTS := mt7986a-rfb-spim-nand
DEVICE_DTS_DIR := $(DTS_DIR)/
- DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
SUPPORTED_DEVICES := mediatek,mt7986a-rfb-snand
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
DEVICE_MODEL := MTK7986 rfbb AP
DEVICE_DTS := mt7986b-rfb
DEVICE_DTS_DIR := $(DTS_DIR)/
- DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
SUPPORTED_DEVICES := mediatek,mt7986b-rfb
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
mt7988a-rfb-sd \
mt7988a-rfb-snfi-nand \
mt7988a-rfb-spim-nand \
+ mt7988a-rfb-spim-nand-factory \
mt7988a-rfb-spim-nor \
mt7988a-rfb-eth1-aqr \
mt7988a-rfb-eth1-i2p5g-phy \
ARTIFACT/emmc-bl31-uboot.fip := mt7988-bl31-uboot rfb-emmc
ARTIFACT/nor-preloader.bin := mt7988-bl2 nor-comb
ARTIFACT/nor-bl31-uboot.fip := mt7988-bl31-uboot rfb-nor
- ARTIFACT/snand-preloader.bin := mt7988-bl2 spim-nand-comb
+ ARTIFACT/snand-preloader.bin := mt7988-bl2 spim-nand-ubi-comb
ARTIFACT/snand-bl31-uboot.fip := mt7988-bl31-uboot rfb-snand
ARTIFACT/sdcard.img.gz := mt798x-gpt sdmmc |\
pad-to 17k | mt7988-bl2 sdmmc-comb |\
DEVICE_MODEL := MR90X v1
DEVICE_DTS := mt7986b-mercusys-mr90x-v1
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.itb := append-kernel | \
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
- DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
ARTIFACTS := preloader.bin bl31-uboot.fip
ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr3
ARTIFACT/bl31-uboot.fip := mt7986-bl31-uboot netcore_n60
DEVICE_DTS_DIR := ../dts
NETGEAR_ENC_MODEL := WAX220
NETGEAR_ENC_REGION := US
- DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
KERNEL_INITRAMFS_SUFFIX := -recovery.itb
IMAGE_SIZE := 32768k
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
DEVICE_MODEL := SOM7981
DEVICE_DTS := mt7981b-openembed-som7981
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
endef
TARGET_DEVICES += openembed_som7981
+define Build/append-openwrt-one-eeprom
+ dd if=$(STAGING_DIR_IMAGE)/mt7981_eeprom_mt7976_dbdc.bin >> $@
+endef
+
+define Device/openwrt_one
+ DEVICE_VENDOR := OpenWrt
+ DEVICE_MODEL := One
+ DEVICE_DTS := mt7981b-openwrt-one
+ DEVICE_DTS_DIR := ../dts
+ DEVICE_DTC_FLAGS := --pad 4096
+ DEVICE_DTS_LOADADDR := 0x43f00000
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-rtc-pcf8563 kmod-usb3 kmod-nvme kmod-phy-airoha-en8811h
+ KERNEL_LOADADDR := 0x44000000
+ KERNEL := kernel-bin | gzip
+ KERNEL_INITRAMFS := kernel-bin | lzma | \
+ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
+ KERNEL_INITRAMFS_SUFFIX := .itb
+ KERNEL_IN_UBI := 1
+ UBOOTENV_IN_UBI := 1
+ IMAGES := sysupgrade.itb
+ IMAGE_SIZE := $$(shell expr 64 + $$(CONFIG_TARGET_ROOTFS_PARTSIZE))m
+ IMAGE/sysupgrade.itb := append-kernel | fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | pad-rootfs | append-metadata
+ ARTIFACTS := \
+ nor-preloader.bin nor-bl31-uboot.fip \
+ snand-preloader.bin snand-bl31-uboot.fip \
+ factory.ubi snand-factory.bin nor-factory.bin
+ ARTIFACT/nor-preloader.bin := mt7981-bl2 nor-ddr4
+ ARTIFACT/nor-bl31-uboot.fip := mt7981-bl31-uboot openwrt_one-nor
+ ARTIFACT/snand-preloader.bin := mt7981-bl2 spim-nand-ubi-ddr4
+ ARTIFACT/snand-bl31-uboot.fip := mt7981-bl31-uboot openwrt_one-snand
+ ARTIFACT/factory.ubi := ubinize-image fit squashfs-sysupgrade.itb
+ ARTIFACT/snand-factory.bin := mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 256k | \
+ mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 512k | \
+ mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 768k | \
+ mt7981-bl2 spim-nand-ubi-ddr4 | pad-to 1024k | \
+ ubinize-image fit squashfs-sysupgrade.itb
+ ARTIFACT/nor-factory.bin := mt7981-bl2 nor-ddr4 | pad-to 256k | \
+ append-openwrt-one-eeprom | pad-to 1024k | \
+ mt7981-bl31-uboot openwrt_one-nor | pad-to 512k | \
+ append-image-stage initramfs.itb
+ UBINIZE_OPTS := -E 5
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
+ UBINIZE_PARTS := fip=:$(STAGING_DIR_IMAGE)/mt7981_openwrt_one-snand-u-boot.fip recovery=:$(KDIR)/tmp/openwrt-mediatek-filogic-openwrt_one-initramfs.itb \
+ $(if $(wildcard $(TOPDIR)/openwrt-mediatek-filogic-openwrt_one-calibration.itb), calibration=:$(TOPDIR)/openwrt-mediatek-filogic-openwrt_one-calibration.itb)
+endef
+TARGET_DEVICES += openwrt_one
+
define Device/qihoo_360t7
DEVICE_VENDOR := Qihoo
DEVICE_MODEL := 360T7
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.itb := append-kernel | \
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-static-with-rootfs | append-metadata
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
ARTIFACTS := preloader.bin bl31-uboot.fip
ARTIFACT/preloader.bin := mt7981-bl2 spim-nand-ddr3
ARTIFACT/bl31-uboot.fip := mt7981-bl31-uboot qihoo_360t7
DEVICE_MODEL := AX3000
DEVICE_DTS := mt7981b-routerich-ax3000
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
SUPPORTED_DEVICES += mediatek,mt7981-spim-snand-rfb
endef
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.itb := append-kernel | \
fit gzip $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb external-with-rootfs | append-metadata
- DEVICE_PACKAGES := fitblk kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := fitblk kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
ARTIFACTS := preloader.bin bl31-uboot.fip
ARTIFACT/preloader.bin := mt7986-bl2 spim-nand-ddr3
endef
DEVICE_MODEL := UniFi 6 Plus
DEVICE_DTS := mt7981a-ubnt-unifi-6-plus
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware e2fsprogs f2fsck mkf2fs fdisk partx-utils
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware e2fsprogs f2fsck mkf2fs fdisk partx-utils
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
TARGET_DEVICES += ubnt_unifi-6-plus
DEVICE_VENDOR := Unielec
DEVICE_MODEL := U7981-01
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs fdisk partx-utils
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 e2fsprogs f2fsck mkf2fs fdisk partx-utils
IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
endef
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
ARTIFACTS := initramfs-factory.ubi
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
KERNEL_IN_UBI := 1
UBOOTENV_IN_UBI := 1
IMAGES := sysupgrade.itb
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
ARTIFACTS := initramfs-factory.ubi
ARTIFACT/initramfs-factory.ubi := append-image-stage initramfs-kernel.bin | ubinize-kernel
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
KERNEL_IN_UBI := 1
UBOOTENV_IN_UBI := 1
IMAGES := sysupgrade.itb
DEVICE_MODEL := Redmi Router AX6000 (stock layout)
DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000-stock
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_MODEL := Redmi Router AX6000 (OpenWrt U-Boot layout)
DEVICE_DTS := mt7986a-xiaomi-redmi-router-ax6000-ubootmod
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-leds-ws2812b kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
KERNEL_INITRAMFS_SUFFIX := -recovery.itb
IMAGES := sysupgrade.itb
UBINIZE_OPTS := -E 5
KERNEL_INITRAMFS := kernel-bin | lzma | \
fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
IMAGE/sysupgrade.bin := append-kernel | pad-to 128k | append-rootfs | pad-rootfs | check-size | append-metadata
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
endef
TARGET_DEVICES += yuncore_ax835
DEVICE_MODEL := ZBT-Z8102AX
DEVICE_DTS := mt7981b-zbtlink-zbt-z8102ax
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 kmod-usb-net-qmi-wwan kmod-usb-serial-option
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware kmod-usb3 kmod-usb-net-qmi-wwan kmod-usb-serial-option
KERNEL_IN_UBI := 1
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
DEVICE_MODEL := ZBT-Z8103AX
DEVICE_DTS := mt7981b-zbtlink-zbt-z8103ax
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
KERNEL_IN_UBI := 1
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
DEVICE_VARIANT := (stock layout)
DEVICE_DTS := mt7986a-zyxel-ex5601-t0-stock
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3
SUPPORTED_DEVICES := mediatek,mt7986a-rfb-snand
UBINIZE_OPTS := -E 5
BLOCKSIZE := 256k
DEVICE_VARIANT := (OpenWrt U-Boot layout)
DEVICE_DTS := mt7986a-zyxel-ex5601-t0-ubootmod
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware kmod-usb3
KERNEL_INITRAMFS_SUFFIX := -recovery.itb
IMAGES := sysupgrade.itb
UBINIZE_OPTS := -E 5
DEVICE_MODEL := EX5700 (Telenor)
DEVICE_DTS := mt7986a-zyxel-ex5700-telenor
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7916-firmware kmod-ubootenv-nvram kmod-usb3 kmod-mt7986-firmware mt7986-wo-firmware
+ DEVICE_PACKAGES := kmod-ubootenv-nvram kmod-usb3 kmod-mt7915e kmod-mt7916-firmware kmod-mt7986-firmware mt7986-wo-firmware
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
PAGESIZE := 2048
DEVICE_MODEL := NWA50AX Pro
DEVICE_DTS := mt7981b-zyxel-nwa50ax-pro
DEVICE_DTS_DIR := ../dts
- DEVICE_PACKAGES := kmod-mt7981-firmware mt7981-wo-firmware zyxel-bootconfig
+ DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware zyxel-bootconfig
DEVICE_DTS_LOADADDR := 0x44000000
UBINIZE_OPTS := -E 5
BLOCKSIZE := 128k
{
struct reserved_mem *rmem;
struct device_node *np;
-@@ -321,7 +321,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+@@ -325,7 +325,7 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
if (index < 0)
continue;
--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -34,12 +34,23 @@ static struct mtk_wed_wo_memory_region m
+@@ -32,14 +32,25 @@ static struct mtk_wed_wo_memory_region m
+ },
+ };
- static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
+-static u32 wo_r32(u32 reg)
++static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
{
- return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
+ u32 val;
+ return val;
}
- static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
+-static void wo_w32(u32 reg, u32 val)
++static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
{
- writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
+ if (wo->boot_regmap)
}
static struct sk_buff *
-@@ -313,6 +324,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+@@ -317,6 +328,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
u32 val, boot_cr;
int ret, i;
/* load firmware region metadata */
for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
int index = of_property_match_string(wo->hw->node,
-@@ -321,6 +335,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+@@ -325,6 +339,9 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
if (index < 0)
continue;
ret = mtk_wed_get_reserved_memory_region(wo->hw, index, &mem_region[i]);
if (ret)
return ret;
+@@ -373,13 +390,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ boot_cr = MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR;
+ else
+ boot_cr = MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
+- wo_w32(boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
++ wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
+ /* wo firmware reset */
+- wo_w32(MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
++ wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
+
+- val = wo_r32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
++ val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
+ MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
+- wo_w32(MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
++ wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
+ out:
+ release_firmware(fw);
+
--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
@@ -231,6 +231,7 @@ struct mtk_wed_wo_queue {
--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
-@@ -316,6 +316,39 @@ next:
+@@ -320,6 +320,39 @@ next:
}
static int
mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
{
const struct mtk_wed_fw_trailer *trailer;
-@@ -324,14 +357,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+@@ -328,14 +361,20 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
u32 val, boot_cr;
int ret, i;
--- a/drivers/net/ethernet/mediatek/mtk_wed.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1320,6 +1320,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1322,6 +1322,24 @@ mtk_wed_rro_alloc(struct mtk_wed_device
struct device_node *np;
int index;
index = of_property_match_string(dev->hw->node, "memory-region-names",
"wo-dlm");
if (index < 0)
-@@ -1336,6 +1354,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
+@@ -1338,6 +1356,7 @@ mtk_wed_rro_alloc(struct mtk_wed_device
return -ENODEV;
dev->rro.miod_phys = rmem->base;
+++ /dev/null
-From: Lorenzo Bianconi <lorenzo@kernel.org>
-Date: Thu, 2 Nov 2023 16:47:07 +0100
-Subject: [PATCH net-next 1/2] net: ethernet: mediatek: split tx and rx fields
- in mtk_soc_data struct
-
-Split tx and rx fields in mtk_soc_data struct. This is a preliminary
-patch to roll back to QDMA for MT7986 SoC in order to fix a hw hang
-if the device receives a corrupted packet.
-
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 210 ++++++++++++--------
- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 29 +--
- 2 files changed, 139 insertions(+), 100 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1281,7 +1281,7 @@ static int mtk_init_fq_dma(struct mtk_et
- eth->scratch_ring = eth->sram_base;
- else
- eth->scratch_ring = dma_alloc_coherent(eth->dma_dev,
-- cnt * soc->txrx.txd_size,
-+ cnt * soc->tx.desc_size,
- ð->phy_scratch_ring,
- GFP_KERNEL);
- if (unlikely(!eth->scratch_ring))
-@@ -1297,16 +1297,16 @@ static int mtk_init_fq_dma(struct mtk_et
- if (unlikely(dma_mapping_error(eth->dma_dev, dma_addr)))
- return -ENOMEM;
-
-- phy_ring_tail = eth->phy_scratch_ring + soc->txrx.txd_size * (cnt - 1);
-+ phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
-
- for (i = 0; i < cnt; i++) {
- struct mtk_tx_dma_v2 *txd;
-
-- txd = eth->scratch_ring + i * soc->txrx.txd_size;
-+ txd = eth->scratch_ring + i * soc->tx.desc_size;
- txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
- if (i < cnt - 1)
- txd->txd2 = eth->phy_scratch_ring +
-- (i + 1) * soc->txrx.txd_size;
-+ (i + 1) * soc->tx.desc_size;
-
- txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
- txd->txd4 = 0;
-@@ -1555,7 +1555,7 @@ static int mtk_tx_map(struct sk_buff *sk
- if (itxd == ring->last_free)
- return -ENOMEM;
-
-- itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+ itx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
- memset(itx_buf, 0, sizeof(*itx_buf));
-
- txd_info.addr = dma_map_single(eth->dma_dev, skb->data, txd_info.size,
-@@ -1596,7 +1596,7 @@ static int mtk_tx_map(struct sk_buff *sk
-
- memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
- txd_info.size = min_t(unsigned int, frag_size,
-- soc->txrx.dma_max_len);
-+ soc->tx.dma_max_len);
- txd_info.qid = queue;
- txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
- !(frag_size - txd_info.size);
-@@ -1609,7 +1609,7 @@ static int mtk_tx_map(struct sk_buff *sk
- mtk_tx_set_dma_desc(dev, txd, &txd_info);
-
- tx_buf = mtk_desc_to_tx_buf(ring, txd,
-- soc->txrx.txd_size);
-+ soc->tx.desc_size);
- if (new_desc)
- memset(tx_buf, 0, sizeof(*tx_buf));
- tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
-@@ -1652,7 +1652,7 @@ static int mtk_tx_map(struct sk_buff *sk
- } else {
- int next_idx;
-
-- next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->txrx.txd_size),
-+ next_idx = NEXT_DESP_IDX(txd_to_idx(ring, txd, soc->tx.desc_size),
- ring->dma_size);
- mtk_w32(eth, next_idx, MT7628_TX_CTX_IDX0);
- }
-@@ -1661,7 +1661,7 @@ static int mtk_tx_map(struct sk_buff *sk
-
- err_dma:
- do {
-- tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->txrx.txd_size);
-+ tx_buf = mtk_desc_to_tx_buf(ring, itxd, soc->tx.desc_size);
-
- /* unmap dma */
- mtk_tx_unmap(eth, tx_buf, NULL, false);
-@@ -1686,7 +1686,7 @@ static int mtk_cal_txd_req(struct mtk_et
- for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
- frag = &skb_shinfo(skb)->frags[i];
- nfrags += DIV_ROUND_UP(skb_frag_size(frag),
-- eth->soc->txrx.dma_max_len);
-+ eth->soc->tx.dma_max_len);
- }
- } else {
- nfrags += skb_shinfo(skb)->nr_frags;
-@@ -1827,7 +1827,7 @@ static struct mtk_rx_ring *mtk_get_rx_ri
-
- ring = ð->rx_ring[i];
- idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
-- rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+ rxd = ring->dma + idx * eth->soc->rx.desc_size;
- if (rxd->rxd2 & RX_DMA_DONE) {
- ring->calc_idx_update = true;
- return ring;
-@@ -1995,7 +1995,7 @@ static int mtk_xdp_submit_frame(struct m
- }
- htxd = txd;
-
-- tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->txrx.txd_size);
-+ tx_buf = mtk_desc_to_tx_buf(ring, txd, soc->tx.desc_size);
- memset(tx_buf, 0, sizeof(*tx_buf));
- htx_buf = tx_buf;
-
-@@ -2014,7 +2014,7 @@ static int mtk_xdp_submit_frame(struct m
- goto unmap;
-
- tx_buf = mtk_desc_to_tx_buf(ring, txd,
-- soc->txrx.txd_size);
-+ soc->tx.desc_size);
- memset(tx_buf, 0, sizeof(*tx_buf));
- n_desc++;
- }
-@@ -2052,7 +2052,7 @@ static int mtk_xdp_submit_frame(struct m
- } else {
- int idx;
-
-- idx = txd_to_idx(ring, txd, soc->txrx.txd_size);
-+ idx = txd_to_idx(ring, txd, soc->tx.desc_size);
- mtk_w32(eth, NEXT_DESP_IDX(idx, ring->dma_size),
- MT7628_TX_CTX_IDX0);
- }
-@@ -2063,7 +2063,7 @@ static int mtk_xdp_submit_frame(struct m
-
- unmap:
- while (htxd != txd) {
-- tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->txrx.txd_size);
-+ tx_buf = mtk_desc_to_tx_buf(ring, htxd, soc->tx.desc_size);
- mtk_tx_unmap(eth, tx_buf, NULL, false);
-
- htxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
-@@ -2194,7 +2194,7 @@ static int mtk_poll_rx(struct napi_struc
- goto rx_done;
-
- idx = NEXT_DESP_IDX(ring->calc_idx, ring->dma_size);
-- rxd = ring->dma + idx * eth->soc->txrx.rxd_size;
-+ rxd = ring->dma + idx * eth->soc->rx.desc_size;
- data = ring->data[idx];
-
- if (!mtk_rx_get_desc(eth, &trxd, rxd))
-@@ -2329,7 +2329,7 @@ static int mtk_poll_rx(struct napi_struc
- rxdcsum = &trxd.rxd4;
- }
-
-- if (*rxdcsum & eth->soc->txrx.rx_dma_l4_valid)
-+ if (*rxdcsum & eth->soc->rx.dma_l4_valid)
- skb->ip_summed = CHECKSUM_UNNECESSARY;
- else
- skb_checksum_none_assert(skb);
-@@ -2453,7 +2453,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
- break;
-
- tx_buf = mtk_desc_to_tx_buf(ring, desc,
-- eth->soc->txrx.txd_size);
-+ eth->soc->tx.desc_size);
- if (!tx_buf->data)
- break;
-
-@@ -2504,7 +2504,7 @@ static int mtk_poll_tx_pdma(struct mtk_e
- }
- mtk_tx_unmap(eth, tx_buf, &bq, true);
-
-- desc = ring->dma + cpu * eth->soc->txrx.txd_size;
-+ desc = ring->dma + cpu * eth->soc->tx.desc_size;
- ring->last_free = desc;
- atomic_inc(&ring->free_count);
-
-@@ -2594,7 +2594,7 @@ static int mtk_napi_rx(struct napi_struc
- do {
- int rx_done;
-
-- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask,
-+ mtk_w32(eth, eth->soc->rx.irq_done_mask,
- reg_map->pdma.irq_status);
- rx_done = mtk_poll_rx(napi, budget - rx_done_total, eth);
- rx_done_total += rx_done;
-@@ -2610,10 +2610,10 @@ static int mtk_napi_rx(struct napi_struc
- return budget;
-
- } while (mtk_r32(eth, reg_map->pdma.irq_status) &
-- eth->soc->txrx.rx_irq_done_mask);
-+ eth->soc->rx.irq_done_mask);
-
- if (napi_complete_done(napi, rx_done_total))
-- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
-
- return rx_done_total;
- }
-@@ -2622,7 +2622,7 @@ static int mtk_tx_alloc(struct mtk_eth *
- {
- const struct mtk_soc_data *soc = eth->soc;
- struct mtk_tx_ring *ring = ð->tx_ring;
-- int i, sz = soc->txrx.txd_size;
-+ int i, sz = soc->tx.desc_size;
- struct mtk_tx_dma_v2 *txd;
- int ring_size;
- u32 ofs, val;
-@@ -2745,14 +2745,14 @@ static void mtk_tx_clean(struct mtk_eth
- }
- if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && ring->dma) {
- dma_free_coherent(eth->dma_dev,
-- ring->dma_size * soc->txrx.txd_size,
-+ ring->dma_size * soc->tx.desc_size,
- ring->dma, ring->phys);
- ring->dma = NULL;
- }
-
- if (ring->dma_pdma) {
- dma_free_coherent(eth->dma_dev,
-- ring->dma_size * soc->txrx.txd_size,
-+ ring->dma_size * soc->tx.desc_size,
- ring->dma_pdma, ring->phys_pdma);
- ring->dma_pdma = NULL;
- }
-@@ -2807,15 +2807,15 @@ static int mtk_rx_alloc(struct mtk_eth *
- if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SRAM) ||
- rx_flag != MTK_RX_FLAGS_NORMAL) {
- ring->dma = dma_alloc_coherent(eth->dma_dev,
-- rx_dma_size * eth->soc->txrx.rxd_size,
-- &ring->phys, GFP_KERNEL);
-+ rx_dma_size * eth->soc->rx.desc_size,
-+ &ring->phys, GFP_KERNEL);
- } else {
- struct mtk_tx_ring *tx_ring = ð->tx_ring;
-
- ring->dma = tx_ring->dma + tx_ring_size *
-- eth->soc->txrx.txd_size * (ring_no + 1);
-+ eth->soc->tx.desc_size * (ring_no + 1);
- ring->phys = tx_ring->phys + tx_ring_size *
-- eth->soc->txrx.txd_size * (ring_no + 1);
-+ eth->soc->tx.desc_size * (ring_no + 1);
- }
-
- if (!ring->dma)
-@@ -2826,7 +2826,7 @@ static int mtk_rx_alloc(struct mtk_eth *
- dma_addr_t dma_addr;
- void *data;
-
-- rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+ rxd = ring->dma + i * eth->soc->rx.desc_size;
- if (ring->page_pool) {
- data = mtk_page_pool_get_buff(ring->page_pool,
- &dma_addr, GFP_KERNEL);
-@@ -2917,7 +2917,7 @@ static void mtk_rx_clean(struct mtk_eth
- if (!ring->data[i])
- continue;
-
-- rxd = ring->dma + i * eth->soc->txrx.rxd_size;
-+ rxd = ring->dma + i * eth->soc->rx.desc_size;
- if (!rxd->rxd1)
- continue;
-
-@@ -2934,7 +2934,7 @@ static void mtk_rx_clean(struct mtk_eth
-
- if (!in_sram && ring->dma) {
- dma_free_coherent(eth->dma_dev,
-- ring->dma_size * eth->soc->txrx.rxd_size,
-+ ring->dma_size * eth->soc->rx.desc_size,
- ring->dma, ring->phys);
- ring->dma = NULL;
- }
-@@ -3297,7 +3297,7 @@ static void mtk_dma_free(struct mtk_eth
- netdev_reset_queue(eth->netdev[i]);
- if (!MTK_HAS_CAPS(soc->caps, MTK_SRAM) && eth->scratch_ring) {
- dma_free_coherent(eth->dma_dev,
-- MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
-+ MTK_QDMA_RING_SIZE * soc->tx.desc_size,
- eth->scratch_ring, eth->phy_scratch_ring);
- eth->scratch_ring = NULL;
- eth->phy_scratch_ring = 0;
-@@ -3347,7 +3347,7 @@ static irqreturn_t mtk_handle_irq_rx(int
-
- eth->rx_events++;
- if (likely(napi_schedule_prep(ð->rx_napi))) {
-- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- __napi_schedule(ð->rx_napi);
- }
-
-@@ -3373,9 +3373,9 @@ static irqreturn_t mtk_handle_irq(int ir
- const struct mtk_reg_map *reg_map = eth->soc->reg_map;
-
- if (mtk_r32(eth, reg_map->pdma.irq_mask) &
-- eth->soc->txrx.rx_irq_done_mask) {
-+ eth->soc->rx.irq_done_mask) {
- if (mtk_r32(eth, reg_map->pdma.irq_status) &
-- eth->soc->txrx.rx_irq_done_mask)
-+ eth->soc->rx.irq_done_mask)
- mtk_handle_irq_rx(irq, _eth);
- }
- if (mtk_r32(eth, reg_map->tx_irq_mask) & MTK_TX_DONE_INT) {
-@@ -3393,10 +3393,10 @@ static void mtk_poll_controller(struct n
- struct mtk_eth *eth = mac->hw;
-
- mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
-- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- mtk_handle_irq_rx(eth->irq[2], dev);
- mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
-- mtk_rx_irq_enable(eth, eth->soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_enable(eth, eth->soc->rx.irq_done_mask);
- }
- #endif
-
-@@ -3563,7 +3563,7 @@ static int mtk_open(struct net_device *d
- napi_enable(ð->tx_napi);
- napi_enable(ð->rx_napi);
- mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
-- mtk_rx_irq_enable(eth, soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_enable(eth, soc->rx.irq_done_mask);
- refcount_set(ð->dma_refcnt, 1);
- }
- else
-@@ -3647,7 +3647,7 @@ static int mtk_stop(struct net_device *d
- mtk_gdm_config(eth, MTK_GDMA_DROP_ALL);
-
- mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
-- mtk_rx_irq_disable(eth, eth->soc->txrx.rx_irq_done_mask);
-+ mtk_rx_irq_disable(eth, eth->soc->rx.irq_done_mask);
- napi_disable(ð->tx_napi);
- napi_disable(ð->rx_napi);
-
-@@ -4126,9 +4126,9 @@ static int mtk_hw_init(struct mtk_eth *e
-
- /* FE int grouping */
- mtk_w32(eth, MTK_TX_DONE_INT, reg_map->pdma.int_grp);
-- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->pdma.int_grp + 4);
-+ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->pdma.int_grp + 4);
- mtk_w32(eth, MTK_TX_DONE_INT, reg_map->qdma.int_grp);
-- mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
-+ mtk_w32(eth, eth->soc->rx.irq_done_mask, reg_map->qdma.int_grp + 4);
- mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
-
- if (mtk_is_netsys_v3_or_greater(eth)) {
-@@ -5305,11 +5305,15 @@ static const struct mtk_soc_data mt2701_
- .required_clks = MT7623_CLKS_BITMAP,
- .required_pctl = true,
- .version = 1,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
-@@ -5325,11 +5329,15 @@ static const struct mtk_soc_data mt7621_
- .offload_version = 1,
- .hash_offset = 2,
- .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
-@@ -5347,11 +5355,15 @@ static const struct mtk_soc_data mt7622_
- .hash_offset = 2,
- .has_accounting = true,
- .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
-@@ -5368,11 +5380,15 @@ static const struct mtk_soc_data mt7623_
- .hash_offset = 2,
- .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
- .disable_pll_modes = true,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
-@@ -5387,11 +5403,15 @@ static const struct mtk_soc_data mt7629_
- .required_pctl = false,
- .has_accounting = true,
- .version = 1,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
-@@ -5409,11 +5429,15 @@ static const struct mtk_soc_data mt7981_
- .hash_offset = 4,
- .has_accounting = true,
- .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma_v2),
-- .rxd_size = sizeof(struct mtk_rx_dma_v2),
-- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma_v2),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+ .dma_len_offset = 8,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma_v2),
-+ .irq_done_mask = MTK_RX_DONE_INT_V2,
-+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- .dma_len_offset = 8,
- },
-@@ -5431,11 +5455,15 @@ static const struct mtk_soc_data mt7986_
- .hash_offset = 4,
- .has_accounting = true,
- .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma_v2),
-- .rxd_size = sizeof(struct mtk_rx_dma_v2),
-- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma_v2),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+ .dma_len_offset = 8,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma_v2),
-+ .irq_done_mask = MTK_RX_DONE_INT_V2,
-+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- .dma_len_offset = 8,
- },
-@@ -5453,11 +5481,15 @@ static const struct mtk_soc_data mt7988_
- .hash_offset = 4,
- .has_accounting = true,
- .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma_v2),
-- .rxd_size = sizeof(struct mtk_rx_dma_v2),
-- .rx_irq_done_mask = MTK_RX_DONE_INT_V2,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID_V2,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma_v2),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-+ .dma_len_offset = 8,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma_v2),
-+ .irq_done_mask = MTK_RX_DONE_INT_V2,
-+ .dma_l4_valid = RX_DMA_L4_VALID_V2,
- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
- .dma_len_offset = 8,
- },
-@@ -5470,11 +5502,15 @@ static const struct mtk_soc_data rt5350_
- .required_clks = MT7628_CLKS_BITMAP,
- .required_pctl = false,
- .version = 1,
-- .txrx = {
-- .txd_size = sizeof(struct mtk_tx_dma),
-- .rxd_size = sizeof(struct mtk_rx_dma),
-- .rx_irq_done_mask = MTK_RX_DONE_INT,
-- .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA,
-+ .tx = {
-+ .desc_size = sizeof(struct mtk_tx_dma),
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
-+ },
-+ .rx = {
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
-+ .dma_l4_valid = RX_DMA_L4_VALID_PDMA,
- .dma_max_len = MTK_TX_DMA_BUF_LEN,
- .dma_len_offset = 16,
- },
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -327,8 +327,8 @@
- /* QDMA descriptor txd3 */
- #define TX_DMA_OWNER_CPU BIT(31)
- #define TX_DMA_LS0 BIT(30)
--#define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len)
-+#define TX_DMA_PLEN0(x) (((x) & eth->soc->tx.dma_max_len) << eth->soc->tx.dma_len_offset)
-+#define TX_DMA_PLEN1(x) ((x) & eth->soc->tx.dma_max_len)
- #define TX_DMA_SWC BIT(14)
- #define TX_DMA_PQID GENMASK(3, 0)
- #define TX_DMA_ADDR64_MASK GENMASK(3, 0)
-@@ -348,8 +348,8 @@
- /* QDMA descriptor rxd2 */
- #define RX_DMA_DONE BIT(31)
- #define RX_DMA_LSO BIT(30)
--#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
--#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
-+#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->rx.dma_max_len) << eth->soc->rx.dma_len_offset)
-+#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->rx.dma_len_offset) & eth->soc->rx.dma_max_len)
- #define RX_DMA_VTAG BIT(15)
- #define RX_DMA_ADDR64_MASK GENMASK(3, 0)
- #if IS_ENABLED(CONFIG_64BIT)
-@@ -1209,10 +1209,9 @@ struct mtk_reg_map {
- * @foe_entry_size Foe table entry size.
- * @has_accounting Bool indicating support for accounting of
- * offloaded flows.
-- * @txd_size Tx DMA descriptor size.
-- * @rxd_size Rx DMA descriptor size.
-- * @rx_irq_done_mask Rx irq done register mask.
-- * @rx_dma_l4_valid Rx DMA valid register mask.
-+ * @desc_size Tx/Rx DMA descriptor size.
-+ * @irq_done_mask Rx irq done register mask.
-+ * @dma_l4_valid Rx DMA valid register mask.
- * @dma_max_len Max DMA tx/rx buffer length.
- * @dma_len_offset Tx/Rx DMA length field offset.
- */
-@@ -1230,13 +1229,17 @@ struct mtk_soc_data {
- bool has_accounting;
- bool disable_pll_modes;
- struct {
-- u32 txd_size;
-- u32 rxd_size;
-- u32 rx_irq_done_mask;
-- u32 rx_dma_l4_valid;
-+ u32 desc_size;
- u32 dma_max_len;
- u32 dma_len_offset;
-- } txrx;
-+ } tx;
-+ struct {
-+ u32 desc_size;
-+ u32 irq_done_mask;
-+ u32 dma_l4_valid;
-+ u32 dma_max_len;
-+ u32 dma_len_offset;
-+ } rx;
- };
-
- #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000)
+++ /dev/null
-From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 10 Oct 2023 21:06:43 +0200
-Subject: [PATCH net-next 2/2] net: ethernet: mediatek: use QDMA instead of
- ADMAv2 on MT7981 and MT7986
-
-ADMA is plagued by RX hangs which can't easily detected and happen upon
-receival of a corrupted package.
-Use QDMA just like on netsys v1 which is also still present and usable, and
-doesn't suffer from that problem.
-
-Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 46 ++++++++++-----------
- 1 file changed, 23 insertions(+), 23 deletions(-)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -113,16 +113,16 @@ static const struct mtk_reg_map mt7986_r
- .tx_irq_mask = 0x461c,
- .tx_irq_status = 0x4618,
- .pdma = {
-- .rx_ptr = 0x6100,
-- .rx_cnt_cfg = 0x6104,
-- .pcrx_ptr = 0x6108,
-- .glo_cfg = 0x6204,
-- .rst_idx = 0x6208,
-- .delay_irq = 0x620c,
-- .irq_status = 0x6220,
-- .irq_mask = 0x6228,
-- .adma_rx_dbg0 = 0x6238,
-- .int_grp = 0x6250,
-+ .rx_ptr = 0x4100,
-+ .rx_cnt_cfg = 0x4104,
-+ .pcrx_ptr = 0x4108,
-+ .glo_cfg = 0x4204,
-+ .rst_idx = 0x4208,
-+ .delay_irq = 0x420c,
-+ .irq_status = 0x4220,
-+ .irq_mask = 0x4228,
-+ .adma_rx_dbg0 = 0x4238,
-+ .int_grp = 0x4250,
- },
- .qdma = {
- .qtx_cfg = 0x4400,
-@@ -1249,7 +1249,7 @@ static bool mtk_rx_get_desc(struct mtk_e
- rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
- rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
- rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
-- if (mtk_is_netsys_v2_or_greater(eth)) {
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
- rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
- rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
- }
-@@ -2201,7 +2201,7 @@ static int mtk_poll_rx(struct napi_struc
- break;
-
- /* find out which mac the packet come from. values start at 1 */
-- if (mtk_is_netsys_v2_or_greater(eth)) {
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
- u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5);
-
- switch (val) {
-@@ -2313,7 +2313,7 @@ static int mtk_poll_rx(struct napi_struc
- skb->dev = netdev;
- bytes += skb->len;
-
-- if (mtk_is_netsys_v2_or_greater(eth)) {
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
- reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
- hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
- if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -2863,7 +2863,7 @@ static int mtk_rx_alloc(struct mtk_eth *
-
- rxd->rxd3 = 0;
- rxd->rxd4 = 0;
-- if (mtk_is_netsys_v2_or_greater(eth)) {
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
- rxd->rxd5 = 0;
- rxd->rxd6 = 0;
- rxd->rxd7 = 0;
-@@ -4072,7 +4072,7 @@ static int mtk_hw_init(struct mtk_eth *e
- else
- mtk_hw_reset(eth);
-
-- if (mtk_is_netsys_v2_or_greater(eth)) {
-+ if (mtk_is_netsys_v3_or_greater(eth)) {
- /* Set FE to PDMAv2 if necessary */
- val = mtk_r32(eth, MTK_FE_GLO_MISC);
- mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC);
-@@ -5435,11 +5435,11 @@ static const struct mtk_soc_data mt7981_
- .dma_len_offset = 8,
- },
- .rx = {
-- .desc_size = sizeof(struct mtk_rx_dma_v2),
-- .irq_done_mask = MTK_RX_DONE_INT_V2,
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
- .dma_l4_valid = RX_DMA_L4_VALID_V2,
-- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-- .dma_len_offset = 8,
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
- },
- };
-
-@@ -5461,11 +5461,11 @@ static const struct mtk_soc_data mt7986_
- .dma_len_offset = 8,
- },
- .rx = {
-- .desc_size = sizeof(struct mtk_rx_dma_v2),
-- .irq_done_mask = MTK_RX_DONE_INT_V2,
-+ .desc_size = sizeof(struct mtk_rx_dma),
-+ .irq_done_mask = MTK_RX_DONE_INT,
- .dma_l4_valid = RX_DMA_L4_VALID_V2,
-- .dma_max_len = MTK_TX_DMA_BUF_LEN_V2,
-- .dma_len_offset = 8,
-+ .dma_max_len = MTK_TX_DMA_BUF_LEN,
-+ .dma_len_offset = 16,
- },
- };
-
ucidef_set_led_netdev "lan1" "LAN1" "green:lan1" "eth1"
ucidef_set_led_netdev "lan2" "LAN2" "green:lan2" "eth0"
;;
+hpe,msm460)
+ ucidef_set_led_netdev "lan" "LAN" "green:lan" "eth0"
+ ;;
esac
board_config_flush
enterasys,ws-ap3715i)
ucidef_set_interfaces_lan_wan "eth1" "eth0"
;;
+hpe,msm460)
+ ucidef_set_interface_lan "eth0"
+ ;;
ocedo,panda)
ucidef_set_interface_wan "eth1"
ucidef_add_switch "switch0" \
extreme-networks,ws-ap3825i)
mtd_get_mac_ascii cfg2 RADIOADDR${PHYNBR} > /sys${DEVPATH}/macaddress
;;
+hpe,msm460)
+ wifi_mac=$(mtd_get_mac_binary colubris-bid 0x1f9bd)
+ [ "$PHYNBR" -eq 0 ] && echo "$wifi_mac" > /sys${DEVPATH}/macaddress
+ [ "$PHYNBR" -eq 1 ] && echo "$(macaddr_add $wifi_mac 16)" > /sys${DEVPATH}/macaddress
+ ;;
ocedo,panda)
mtd_get_mac_ascii uboot-env0 wmac$(($PHYNBR + 1)) > /sys${DEVPATH}/macaddress
;;
local board=$(board_name)
case "$board" in
+ hpe,msm460|\
ocedo,panda|\
sophos,red-15w-rev1|\
watchguard,firebox-t10)
# CONFIG_MPIC_MSGR is not set
CONFIG_MPIC_TIMER=y
CONFIG_MPILIB=y
+# CONFIG_MSM460 is not set
# CONFIG_MTD_CFI is not set
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
# CONFIG_MPIC_MSGR is not set
CONFIG_MPIC_TIMER=y
CONFIG_MPILIB=y
+# CONFIG_MSM460 is not set
# CONFIG_MTD_CFI is not set
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later or MIT
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+ model = "Hewlett-Packard MSM460";
+ compatible = "hpe,msm460";
+
+ aliases {
+ led-boot = &system_green;
+ led-failsafe = &system_green;
+ led-running = &system_green;
+ led-upgrade = &system_green;
+ label-mac-device = &enet0;
+ };
+
+ chosen {
+ /* Needed for initramfs */
+ bootargs-override = "console=ttyS0,115200 ubi.mtd=5,2048";
+ stdout-path = &serial0;
+ };
+
+ memory {
+ device_type = "memory";
+ };
+
+ lbc: localbus@ffe05000 {
+ reg = <0 0xffe05000 0 0x1000>;
+ ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+ 0x1 0x0 0x0 0xff800000 0x00040000
+ 0x2 0x0 0x0 0xffa00000 0x00020000
+ 0x3 0x0 0x0 0xffb00000 0x00020000>;
+
+ nand@1,0 {
+ compatible = "fsl,p1020-fcm-nand", "fsl,elbc-fcm-nand";
+ reg = <0x1 0x0 0x40000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x0 0xc0000>;
+ label = "u-boot";
+ read-only;
+ };
+
+ partition@c0000 {
+ reg = <0xc0000 0x40000>;
+ label = "colubris-bid";
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_hwinfo_1f822: macaddr@1f822 {
+ /* ETH */
+ compatible = "mac-base";
+ reg = <0x1f822 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+
+ macaddr_hwinfo_1f9bd: macaddr@1f9bd {
+ /* WLAN */
+ compatible = "mac-base";
+ reg = <0x1f9bd 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ /* uenv{0,1} and ubi occupy kernel and slash partitions */
+
+ partition@100000 {
+ reg = <0x100000 0x80000>;
+ label = "uboot-env0";
+ };
+
+ partition@180000 {
+ reg = <0x180000 0x80000>;
+ label = "uboot-env1";
+ };
+
+ partition@200000 {
+ reg = <0x200000 0x300000>;
+ label = "reserved";
+ };
+
+ partition@500000 {
+ reg = <0x500000 0x5f00000>;
+ label = "ubi";
+ };
+
+ partition@6500000 {
+ reg = <0x6500000 0x400000>;
+ label = "pool";
+ read-only;
+ };
+
+ partition@6900000 {
+ reg = <0x6900000 0x15e0000>;
+ label = "flash";
+ read-only;
+ };
+
+ partition@7ee0000 {
+ reg = <0x7ee0000 0x20000>;
+ label = "pf";
+ read-only;
+ };
+
+ /* BBT is at the end of the flash - 100000@7f00000 */
+ };
+ };
+ };
+
+ soc: soc@ffe00000 {
+ ranges = <0x0 0x0 0xffe00000 0x100000>;
+
+ i2c@3000 {
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller@fc00 {
+ };
+
+ mdio@24000 {
+ phy0: ethernet-phy@0 {
+ reg = <0x0>;
+ reset-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ };
+ };
+
+ enet0: ethernet@b0000 {
+ phy-connection-type = "rgmii-id";
+ phy-handle = <&phy0>;
+ nvmem-cells = <&macaddr_hwinfo_1f822 0>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ enet1: ethernet@b1000 {
+ status = "disabled";
+ };
+
+ enet2: ethernet@b2000 {
+ status = "disabled";
+ };
+
+ usb@22000 {
+ status = "disabled";
+ };
+
+ usb@23000 {
+ status = "disabled";
+ };
+ };
+
+ pci0: pcie@ffe09000 {
+ ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
+ reg = <0 0xffe09000 0 0x1000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0xa0000000
+ 0x2000000 0x0 0xa0000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ pci1: pcie@ffe0a000 {
+ reg = <0 0xffe0a000 0 0x1000>;
+ ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
+ 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
+ pcie@0 {
+ ranges = <0x2000000 0x0 0x80000000
+ 0x2000000 0x0 0x80000000
+ 0x0 0x20000000
+
+ 0x1000000 0x0 0x0
+ 0x1000000 0x0 0x0
+ 0x0 0x100000>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ system_green: power {
+ gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ default-state = "on";
+ };
+
+ lan {
+ gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ };
+
+ radio1 {
+ gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
+ function-enumerator = <1>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ radio2 {
+ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN;
+ function-enumerator = <2>;
+ linux,default-trigger = "phy1tpt";
+ };
+ };
+
+ buttons {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset-btn";
+ gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_RESTART>;
+ };
+ };
+};
+/include/ "fsl/p1020si-post.dtsi"
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * HPE MSM460 Board Setup
+ *
+ * Copyright (C) 2022 David Bauer <mail@david-bauer.net>
+ *
+ * Based on:
+ * mpc85xx_rdb.c:
+ * MPC85xx RDB Board Setup
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/stddef.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/of_platform.h>
+
+#include <asm/time.h>
+#include <asm/machdep.h>
+#include <asm/pci-bridge.h>
+#include <mm/mmu_decl.h>
+#include <asm/prom.h>
+#include <asm/udbg.h>
+#include <asm/mpic.h>
+
+#include <sysdev/fsl_soc.h>
+#include <sysdev/fsl_pci.h>
+#include "smp.h"
+
+#include "mpc85xx.h"
+
+void __init msm_pic_init(void)
+{
+ struct mpic *mpic;
+
+ mpic = mpic_alloc(NULL, 0,
+ MPIC_BIG_ENDIAN |
+ MPIC_SINGLE_DEST_CPU,
+ 0, 256, " OpenPIC ");
+
+ BUG_ON(mpic == NULL);
+ mpic_init(mpic);
+}
+
+/*
+ * Setup the architecture
+ */
+static void __init msm_setup_arch(void)
+{
+ if (ppc_md.progress)
+ ppc_md.progress("msm_setup_arch()", 0);
+
+ mpc85xx_smp_init();
+
+ fsl_pci_assign_primary();
+
+ pr_info("MSM460 board from HPE\n");
+}
+
+machine_arch_initcall(msm, mpc85xx_common_publish_devices);
+
+/*
+ * Called very early, device-tree isn't unflattened
+ */
+static int __init msm_probe(void)
+{
+ if (of_machine_is_compatible("hpe,msm460"))
+ return 1;
+ return 0;
+}
+
+define_machine(msm) {
+ .name = "P1020 RDB",
+ .probe = msm_probe,
+ .setup_arch = msm_setup_arch,
+ .init_IRQ = msm_pic_init,
+#ifdef CONFIG_PCI
+ .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+ .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
+#endif
+ .get_irq = mpic_get_irq,
+ .calibrate_decr = generic_calibrate_decr,
+ .progress = udbg_progress,
+};
endef
TARGET_DEVICES += extreme-networks_ws-ap3825i
+define Device/hpe_msm460
+ DEVICE_VENDOR := Hewlett-Packard
+ DEVICE_MODEL := MSM460
+ KERNEL = kernel-bin | fit none $(KDIR)/image-$$(DEVICE_DTS).dtb
+ KERNEL_NAME := zImage.la3000000
+ KERNEL_ENTRY := 0x3000000
+ KERNEL_LOADADDR := 0x3000000
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
+ SUBPAGESIZE := 2048
+ KERNEL_IN_UBI := 1
+ UBINIZE_OPTS := -E 5
+ IMAGES := factory.bin sysupgrade.bin
+ IMAGE/factory.bin := append-ubi
+ IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += hpe_msm460
+
define Device/ocedo_panda
DEVICE_VENDOR := OCEDO
DEVICE_MODEL := Panda
IMAGE/fdt.bin := append-dtb
endef
TARGET_DEVICES += ocedo_panda
-
CONFIG_HAVE_RCU_TABLE_FREE=y
CONFIG_HIVEAP_330=y
CONFIG_PANDA=y
+CONFIG_MSM460=y
CONFIG_I2C_CHARDEV=y
CONFIG_LEDS_LP5521=y
CONFIG_LEDS_LP55XX_COMMON=y
BOARDNAME:=P1020
-KERNEL_IMAGES:=simpleImage.ws-ap3710i simpleImage.ws-ap3825i simpleImage.hiveap-330
+KERNEL_IMAGES:=simpleImage.ws-ap3710i simpleImage.ws-ap3825i simpleImage.hiveap-330 zImage.la3000000
define Target/Description
Build firmware images for Freescale P1020 based boards.
--- /dev/null
+From b30ba76a980b3a9282f309c23e3bb0b0eb2c72cd Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 30 May 2024 02:55:38 +0200
+Subject: [PATCH] powerpc: add compressed zImage for mpc85xx
+
+Add a universal zImage which can be loaded by mpc85xx boards at
+load address 0x3000000. This allows boards to boot kernels larger than
+16MB even if the image is loaded temporarily from NAND at offset
+0x1000000 which some bootloaders do by default.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/powerpc/boot/Makefile | 1 +
+ arch/powerpc/boot/wrapper | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -345,6 +345,7 @@ image-$(CONFIG_MPC836x_MDS) += cuImage.
+ image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
+
+ # Board ports in arch/powerpc/platform/85xx/Kconfig
++image-y += zImage.la3000000
+ image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
+ image-$(CONFIG_MPC8560_ADS) += cuImage.mpc8560ads
+ image-$(CONFIG_MPC85xx_CDS) += cuImage.mpc8541cds \
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -254,6 +254,11 @@ if [ -n "$esm_blob" -a "$platform" != "p
+ fi
+
+ case "$platform" in
++la3000000)
++ binary=y
++ platformo="$object/fixed-head.o $object/of.o $object/epapr.o"
++ link_address='0x3000000'
++ ;;
+ of)
+ platformo="$object/of.o $object/epapr.o"
+ make_space=n
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -359,7 +360,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
+@@ -360,7 +361,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
image-$(CONFIG_TQM8555) += cuImage.tqm8555
image-$(CONFIG_TQM8560) += cuImage.tqm8560
image-$(CONFIG_KSI8560) += cuImage.ksi8560
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -341,6 +341,11 @@ adder875-redboot)
+@@ -346,6 +346,11 @@ adder875-redboot)
platformo="$object/fixed-head.o $object/redboot-8xx.o"
binary=y
;;
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -360,6 +361,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
+@@ -361,6 +362,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
image-$(CONFIG_TQM8555) += cuImage.tqm8555
image-$(CONFIG_TQM8560) += cuImage.tqm8560
image-$(CONFIG_KSI8560) += cuImage.ksi8560
image-$(CONFIG_MVME7100) += dtbImage.mvme7100
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -341,6 +341,7 @@ adder875-redboot)
+@@ -346,6 +346,7 @@ adder875-redboot)
platformo="$object/fixed-head.o $object/redboot-8xx.o"
binary=y
;;
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -363,6 +364,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
+@@ -364,6 +365,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
image-$(CONFIG_KSI8560) += cuImage.ksi8560
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -342,7 +342,8 @@ adder875-redboot)
+@@ -347,7 +347,8 @@ adder875-redboot)
binary=y
;;
simpleboot-hiveap-330|\
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -365,6 +366,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
+@@ -366,6 +367,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -343,7 +343,8 @@ adder875-redboot)
+@@ -348,7 +348,8 @@ adder875-redboot)
;;
simpleboot-hiveap-330|\
simpleboot-tl-wdr4900-v1|\
src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -366,6 +367,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
+@@ -367,6 +368,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
-@@ -364,6 +365,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
+@@ -365,6 +366,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
image-$(CONFIG_TQM8555) += cuImage.tqm8555
image-$(CONFIG_TQM8560) += cuImage.tqm8560
image-$(CONFIG_KSI8560) += cuImage.ksi8560
image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -341,6 +341,7 @@ adder875-redboot)
+@@ -346,6 +346,7 @@ adder875-redboot)
platformo="$object/fixed-head.o $object/redboot-8xx.o"
binary=y
;;
--- /dev/null
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -114,6 +114,17 @@ config FIREBOX_T10
+ This board is a VPN Gateway-Router with a
+ Freescale P1010 SoC.
+
++config MSM460
++ bool "HPE MSM460"
++ select DEFAULT_UIMAGE
++ select ARCH_REQUIRE_GPIOLIB
++ select GPIO_MPC8XXX
++ help
++ This option enables support for the HPE MSM460 board.
++
++ This board is a Concurrent Dual-Band wireless access point with a
++ Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ bool "Freescale MPC8540 ADS"
+ select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -21,6 +21,7 @@ obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.
+ obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
+ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
++obj-$(CONFIG_MSM460) += msm460.o
+ obj-$(CONFIG_P1010_RDB) += p1010rdb.o
+ obj-$(CONFIG_P1022_DS) += p1022_ds.o
+ obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
#
-@@ -430,15 +429,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
+@@ -431,15 +430,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
$(obj)/vmlinux.strip: vmlinux
$(STRIP) -s -R .comment $< -o $@
--- /dev/null
+From b30ba76a980b3a9282f309c23e3bb0b0eb2c72cd Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Thu, 30 May 2024 02:55:38 +0200
+Subject: [PATCH] powerpc: add compressed zImage for mpc85xx
+
+Add a universal zImage which can be loaded by mpc85xx boards at
+load address 0x3000000. This allows boards to boot kernels larger than
+16MB even if the image is loaded temporarily from NAND at offset
+0x1000000 which some bootloaders do by default.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ arch/powerpc/boot/Makefile | 1 +
+ arch/powerpc/boot/wrapper | 5 +++++
+ 2 files changed, 6 insertions(+)
+
+--- a/arch/powerpc/boot/Makefile
++++ b/arch/powerpc/boot/Makefile
+@@ -342,6 +342,7 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.
+ image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
+
+ # Board ports in arch/powerpc/platform/85xx/Kconfig
++image-y += zImage.la3000000
+ image-$(CONFIG_MPC85xx_MDS) += cuImage.mpc8568mds
+ image-$(CONFIG_MPC85xx_DS) += cuImage.mpc8544ds \
+ cuImage.mpc8572ds
+--- a/arch/powerpc/boot/wrapper
++++ b/arch/powerpc/boot/wrapper
+@@ -258,6 +258,11 @@ if [ -n "$esm_blob" -a "$platform" != "p
+ fi
+
+ case "$platform" in
++la3000000)
++ binary=y
++ platformo="$object/fixed-head.o $object/of.o $object/epapr.o"
++ link_address='0x3000000'
++ ;;
+ of)
+ platformo="$object/of.o $object/epapr.o"
+ make_space=n
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -351,7 +352,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
+@@ -352,7 +353,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
image-$(CONFIG_TQM8555) += cuImage.tqm8555
image-$(CONFIG_TQM8560) += cuImage.tqm8560
image-$(CONFIG_KSI8560) += cuImage.ksi8560
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -345,6 +345,11 @@ adder875-redboot)
+@@ -350,6 +350,11 @@ adder875-redboot)
platformo="$object/fixed-head.o $object/redboot-8xx.o"
binary=y
;;
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -352,6 +353,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
+@@ -353,6 +354,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
image-$(CONFIG_TQM8555) += cuImage.tqm8555
image-$(CONFIG_TQM8560) += cuImage.tqm8560
image-$(CONFIG_KSI8560) += cuImage.ksi8560
image-$(CONFIG_MVME7100) += dtbImage.mvme7100
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -345,6 +345,7 @@ adder875-redboot)
+@@ -350,6 +350,7 @@ adder875-redboot)
platformo="$object/fixed-head.o $object/redboot-8xx.o"
binary=y
;;
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -355,6 +356,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
+@@ -356,6 +357,7 @@ image-$(CONFIG_TQM8560) += cuImage.tqm
image-$(CONFIG_KSI8560) += cuImage.ksi8560
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -346,7 +346,8 @@ adder875-redboot)
+@@ -351,7 +351,8 @@ adder875-redboot)
binary=y
;;
simpleboot-hiveap-330|\
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -357,6 +358,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
+@@ -358,6 +359,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -347,7 +347,8 @@ adder875-redboot)
+@@ -352,7 +352,8 @@ adder875-redboot)
;;
simpleboot-hiveap-330|\
simpleboot-tl-wdr4900-v1|\
src-plat-$(CONFIG_WS_AP3825I) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_PPC_MICROWATT) += fixed-head.S microwatt.c
-@@ -358,6 +359,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
+@@ -359,6 +360,7 @@ image-$(CONFIG_KSI8560) += cuImage.ksi
image-$(CONFIG_HIVEAP_330) += simpleImage.hiveap-330
image-$(CONFIG_TL_WDR4900_V1) += simpleImage.tl-wdr4900-v1
image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
src-plat-$(CONFIG_HIVEAP_330) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_TL_WDR4900_V1) += simpleboot.c fixed-head.S
src-plat-$(CONFIG_WS_AP3710I) += simpleboot.c fixed-head.S
-@@ -356,6 +357,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
+@@ -357,6 +358,7 @@ image-$(CONFIG_TQM8548) += cuImage.tqm
image-$(CONFIG_TQM8555) += cuImage.tqm8555
image-$(CONFIG_TQM8560) += cuImage.tqm8560
image-$(CONFIG_KSI8560) += cuImage.ksi8560
image-$(CONFIG_WS_AP3710I) += simpleImage.ws-ap3710i
--- a/arch/powerpc/boot/wrapper
+++ b/arch/powerpc/boot/wrapper
-@@ -345,6 +345,7 @@ adder875-redboot)
+@@ -350,6 +350,7 @@ adder875-redboot)
platformo="$object/fixed-head.o $object/redboot-8xx.o"
binary=y
;;
--- /dev/null
+--- a/arch/powerpc/platforms/85xx/Kconfig
++++ b/arch/powerpc/platforms/85xx/Kconfig
+@@ -114,6 +114,17 @@ config FIREBOX_T10
+ This board is a VPN Gateway-Router with a
+ Freescale P1010 SoC.
+
++config MSM460
++ bool "HPE MSM460"
++ select DEFAULT_UIMAGE
++ select ARCH_REQUIRE_GPIOLIB
++ select GPIO_MPC8XXX
++ help
++ This option enables support for the HPE MSM460 board.
++
++ This board is a Concurrent Dual-Band wireless access point with a
++ Freescale P1020 SoC.
++
+ config MPC8540_ADS
+ bool "Freescale MPC8540 ADS"
+ select DEFAULT_UIMAGE
+--- a/arch/powerpc/platforms/85xx/Makefile
++++ b/arch/powerpc/platforms/85xx/Makefile
+@@ -19,6 +19,7 @@ obj8259-$(CONFIG_PPC_I8259) += mpc85xx
+ obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o $(obj8259-y)
+ obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
+ obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
++obj-$(CONFIG_MSM460) += msm460.o
+ obj-$(CONFIG_P1010_RDB) += p1010rdb.o
+ obj-$(CONFIG_P1022_DS) += p1022_ds.o
+ obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
image-$(CONFIG_EPAPR_BOOT) += zImage.epapr
#
-@@ -421,15 +420,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
+@@ -422,15 +421,6 @@ $(obj)/dtbImage.%: vmlinux $(wrapperbits
$(obj)/vmlinux.strip: vmlinux
$(STRIP) -s -R .comment $< -o $@
linksys,wrt32x)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
;;
- fortinet,fg-50e)
+ fortinet,fg-50e|\
+ fortinet,fg-51e|\
+ fortinet,fg-52e|\
+ fortinet,fwf-50e-2r|\
+ fortinet,fwf-51e)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" "eth1 eth2"
;;
iij,sa-w2)
legacy_sdcard_do_upgrade "$1"
;;
fortinet,fg-30e|\
- fortinet,fg-50e)
+ fortinet,fg-50e|\
+ fortinet,fg-51e|\
+ fortinet,fg-52e|\
+ fortinet,fwf-50e-2r|\
+ fortinet,fwf-51e)
fortinet_do_upgrade "$1"
;;
iij,sa-w2)
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include "armada-385-fortinet-fg-x0e.dtsi"
+#include "armada-385-fortinet-fg-3xe.dtsi"
/ {
model = "Fortinet FortiGate 30E";
compatible = "fortinet,fg-30e", "marvell,armada385", "marvell,armada380";
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x40000000>; /* 1GB */
- };
-};
-
-&gpio_leds {
- led-14 {
- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_SPEED_WAN;
- linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
- };
-
- led-15 {
- gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_SPEED_WAN;
- linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
- };
-};
-
-&pinctrl {
- pmx_switch_pins: switch-pins {
- marvell,pins = "mpp19";
- marvell,function = "gpio";
- };
-};
-
-&mdio {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>, <&pmx_switch_pins>;
-
- /* Marvell 88E6176 */
- switch@2 {
- compatible = "marvell,mv88e6085";
- reg = <0x2>;
- reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "wan";
- nvmem-cells = <&macaddr_bdinfo_d880 1>;
- nvmem-cell-names = "mac-address";
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- nvmem-cells = <&macaddr_bdinfo_d880 5>;
- nvmem-cell-names = "mac-address";
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- nvmem-cells = <&macaddr_bdinfo_d880 4>;
- nvmem-cell-names = "mac-address";
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- nvmem-cells = <&macaddr_bdinfo_d880 3>;
- nvmem-cell-names = "mac-address";
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- nvmem-cells = <&macaddr_bdinfo_d880 2>;
- nvmem-cell-names = "mac-address";
- };
-
- port@6 {
- reg = <6>;
- ethernet = <ð0>;
- phy-connection-type = "rgmii-id";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-xxe.dtsi"
+
+/ {
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>; /* 1GB */
+ };
+};
+
+&gpio_leds {
+ led-14 {
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_WAN;
+ linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
+ };
+
+ led-15 {
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_WAN;
+ linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
+ };
+};
+
+&pinctrl {
+ pmx_switch_pins: switch-pins {
+ marvell,pins = "mpp19";
+ marvell,function = "gpio";
+ };
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>, <&pmx_switch_pins>;
+
+ /* Marvell 88E6176 */
+ switch@2 {
+ compatible = "marvell,mv88e6085";
+ reg = <0x2>;
+ reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "wan";
+ nvmem-cells = <&macaddr_bdinfo_d880 1>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan4";
+ nvmem-cells = <&macaddr_bdinfo_d880 5>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ nvmem-cells = <&macaddr_bdinfo_d880 4>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ nvmem-cells = <&macaddr_bdinfo_d880 3>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan1";
+ nvmem-cells = <&macaddr_bdinfo_d880 2>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port@6 {
+ reg = <6>;
+ ethernet = <ð0>;
+ phy-connection-type = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-#include "armada-385-fortinet-fg-x0e.dtsi"
+#include "armada-385-fortinet-fg-5xe.dtsi"
/ {
model = "Fortinet FortiGate 50E";
compatible = "fortinet,fg-50e", "marvell,armada385", "marvell,armada380";
-
- memory@0 {
- device_type = "memory";
- reg = <0x00000000 0x80000000>; /* 2GB */
- };
-};
-
-&gpio_leds {
- led-14 {
- gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_SPEED_WAN;
- function-enumerator = <1>;
- linux,default-trigger = "f1072004.mdio-mii:00:1Gbps";
- };
-
- led-15 {
- gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_SPEED_WAN;
- function-enumerator = <2>;
- linux,default-trigger = "f1072004.mdio-mii:01:1Gbps";
- };
-
- led-16 {
- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_SPEED_LAN;
- function-enumerator = <5>;
- linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
- };
-
- led-17 {
- gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_SPEED_LAN;
- function-enumerator = <5>;
- linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
- };
-};
-
-&pinctrl {
- pmx_phy_switch_pins: phy-switch-pins {
- marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41";
- marvell,function = "gpio";
- };
-};
-
-ð1 {
- status = "okay";
-
- phy-handle = <ðphy0>;
- phy-connection-type = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
- nvmem-cells = <&macaddr_bdinfo_d880 1>;
- nvmem-cell-names = "mac-address";
-};
-
-ð2 {
- status = "okay";
-
- phy-handle = <ðphy1>;
- phy-connection-type = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <3>;
- nvmem-cells = <&macaddr_bdinfo_d880 2>;
- nvmem-cell-names = "mac-address";
-};
-
-&mdio {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>;
-
- /* Marvell 88E1512 */
- ethphy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id0141,0dd1",
- "ethernet-phy-ieee802.3-c22";
- reg = <0>;
- interrupt-parent = <&gpio0>;
- interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <10000>;
- /*
- * LINK/ACT (Green): LED[0], Active Low
- * SPEED 100M (Amber): LED[1], Active High
- */
- marvell,reg-init = <3 16 0 0x71>,
- <3 17 0 0x4>;
- };
-
- /* Marvell 88E1512 */
- ethphy1: ethernet-phy@1 {
- compatible = "ethernet-phy-id0141,0dd1",
- "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&gpio1>;
- interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
- reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
- reset-assert-us = <10000>;
- reset-deassert-us = <10000>;
- /*
- * LINK/ACT (Green): LED[0], Active Low
- * SPEED 100M (Amber): LED[1], Active High
- */
- marvell,reg-init = <3 16 0 0x71>,
- <3 17 0 0x4>;
- };
-
- /* Marvell 88E6176 */
- switch@2 {
- compatible = "marvell,mv88e6085";
- reg = <0x2>;
- reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- label = "lan5";
- nvmem-cells = <&macaddr_bdinfo_d880 7>;
- nvmem-cell-names = "mac-address";
- };
-
- port@1 {
- reg = <1>;
- label = "lan4";
- nvmem-cells = <&macaddr_bdinfo_d880 6>;
- nvmem-cell-names = "mac-address";
- };
-
- port@2 {
- reg = <2>;
- label = "lan3";
- nvmem-cells = <&macaddr_bdinfo_d880 5>;
- nvmem-cell-names = "mac-address";
- };
-
- port@3 {
- reg = <3>;
- label = "lan2";
- nvmem-cells = <&macaddr_bdinfo_d880 4>;
- nvmem-cell-names = "mac-address";
- };
-
- port@4 {
- reg = <4>;
- label = "lan1";
- nvmem-cells = <&macaddr_bdinfo_d880 3>;
- nvmem-cell-names = "mac-address";
- };
-
- port@6 {
- reg = <6>;
- ethernet = <ð0>;
- phy-connection-type = "rgmii-id";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- };
- };
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-5xe.dtsi"
+
+/ {
+ model = "Fortinet FortiGate 51E";
+ compatible = "fortinet,fg-51e", "marvell,armada385", "marvell,armada380";
+};
+
+&ahci0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-5xe.dtsi"
+
+/ {
+ model = "Fortinet FortiGate 52E";
+ compatible = "fortinet,fg-52e", "marvell,armada385", "marvell,armada380";
+};
+
+&ahci0 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-xxe.dtsi"
+
+/ {
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x80000000>; /* 2GB */
+ };
+};
+
+&gpio_leds {
+ led-14 {
+ gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_WAN;
+ function-enumerator = <1>;
+ linux,default-trigger = "f1072004.mdio-mii:00:1Gbps";
+ };
+
+ led-15 {
+ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_WAN;
+ function-enumerator = <2>;
+ linux,default-trigger = "f1072004.mdio-mii:01:1Gbps";
+ };
+
+ led-16 {
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <5>;
+ linux,default-trigger = "mv88e6xxx-1:00:100Mbps";
+ };
+
+ led-17 {
+ gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <5>;
+ linux,default-trigger = "mv88e6xxx-1:00:1Gbps";
+ };
+};
+
+&pinctrl {
+ pmx_phy_switch_pins: phy-switch-pins {
+ marvell,pins = "mpp19", "mpp20", "mpp23", "mpp34", "mpp41";
+ marvell,function = "gpio";
+ };
+};
+
+ð1 {
+ status = "okay";
+
+ phy-handle = <ðphy0>;
+ phy-connection-type = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <2>;
+ nvmem-cells = <&macaddr_bdinfo_d880 1>;
+ nvmem-cell-names = "mac-address";
+};
+
+ð2 {
+ status = "okay";
+
+ phy-handle = <ðphy1>;
+ phy-connection-type = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <3>;
+ nvmem-cells = <&macaddr_bdinfo_d880 2>;
+ nvmem-cell-names = "mac-address";
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>, <&pmx_phy_switch_pins>;
+
+ /* Marvell 88E1512 */
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0141,0dd1",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ /*
+ * LINK/ACT (Green): LED[0], Active Low
+ * SPEED 100M (Amber): LED[1], Active High
+ */
+ marvell,reg-init = <3 16 0 0x71>,
+ <3 17 0 0x4>;
+ };
+
+ /* Marvell 88E1512 */
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-id0141,0dd1",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ reset-deassert-us = <10000>;
+ /*
+ * LINK/ACT (Green): LED[0], Active Low
+ * SPEED 100M (Amber): LED[1], Active High
+ */
+ marvell,reg-init = <3 16 0 0x71>,
+ <3 17 0 0x4>;
+ };
+
+ /* Marvell 88E6176 */
+ switch@2 {
+ compatible = "marvell,mv88e6085";
+ reg = <0x2>;
+ reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan5";
+ nvmem-cells = <&macaddr_bdinfo_d880 7>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan4";
+ nvmem-cells = <&macaddr_bdinfo_d880 6>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ nvmem-cells = <&macaddr_bdinfo_d880 5>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan2";
+ nvmem-cells = <&macaddr_bdinfo_d880 4>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "lan1";
+ nvmem-cells = <&macaddr_bdinfo_d880 3>;
+ nvmem-cell-names = "mac-address";
+ };
+
+ port@6 {
+ reg = <6>;
+ ethernet = <ð0>;
+ phy-connection-type = "rgmii-id";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+ };
+};
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
-
-/dts-v1/;
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/leds/common.h>
-#include "armada-385.dtsi"
-
-/ {
- aliases {
- led-boot = &led_status_green;
- led-failsafe = &led_status_red;
- led-running = &led_status_green;
- led-upgrade = &led_status_green;
- label-mac-device = ð0;
- };
-
- chosen {
- stdout-path = "serial0:9600n8";
- };
-
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
- MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
- MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
- MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_gpio_keys_pins>;
-
- reset {
- label = "reset";
- linux,code = <KEY_RESTART>;
- gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
- };
- };
-
- gpio_leds: gpio-leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_gpio_leds_pins>;
-
- led-0 {
- gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_ALARM;
- };
-
- led-1 {
- gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_RED>;
- function = "ha";
- };
-
- led_status_green: led-2 {
- gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_STATUS;
- };
-
- led-3 {
- gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = "ha";
- };
-
- led-4 {
- gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_ALARM;
- };
-
- led_status_red: led-5 {
- gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_RED>;
- function = LED_FUNCTION_STATUS;
- };
-
- led-6 {
- gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_SPEED_LAN;
- function-enumerator = <4>;
- linux,default-trigger = "mv88e6xxx-1:01:1Gbps";
- };
-
- led-7 {
- gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_SPEED_LAN;
- function-enumerator = <4>;
- linux,default-trigger = "mv88e6xxx-1:01:100Mbps";
- };
-
- led-8 {
- gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_SPEED_LAN;
- function-enumerator = <3>;
- linux,default-trigger = "mv88e6xxx-1:02:100Mbps";
- };
-
- led-9 {
- gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_SPEED_LAN;
- function-enumerator = <3>;
- linux,default-trigger = "mv88e6xxx-1:02:1Gbps";
- };
-
- led-10 {
- gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_SPEED_LAN;
- function-enumerator = <1>;
- linux,default-trigger = "mv88e6xxx-1:04:1Gbps";
- };
-
- led-11 {
- gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_SPEED_LAN;
- function-enumerator = <1>;
- linux,default-trigger = "mv88e6xxx-1:04:100Mbps";
- };
-
- led-12 {
- gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_GREEN>;
- function = LED_FUNCTION_SPEED_LAN;
- function-enumerator = <2>;
- linux,default-trigger = "mv88e6xxx-1:03:1Gbps";
- };
-
- led-13 {
- gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
- color = <LED_COLOR_ID_AMBER>;
- function = LED_FUNCTION_SPEED_LAN;
- function-enumerator = <2>;
- linux,default-trigger = "mv88e6xxx-1:03:100Mbps";
- };
- };
-
- reg_usb_vbus: regulator-usb-vbus {
- compatible = "fixed-regulator";
- regulator-name = "usb-vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
- regulator-always-on;
- };
-};
-
-&i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
-
- gpio2: gpio@24 {
- compatible = "nxp,pca9555";
- reg = <0x24>;
- gpio-controller;
- #gpio-cells = <0x2>;
- };
-
- hwmon@28 {
- compatible = "nuvoton,nct7802";
- reg = <0x28>;
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
-};
-
-&pinctrl {
- pmx_gpio_leds_pins: gpio-leds-pins {
- marvell,pins = "mpp30", "mpp32", "mpp33", "mpp35",
- "mpp45", "mpp47";
- marvell,function = "gpio";
- };
-
- pmx_usb_pins: usb-pins {
- marvell,pins = "mpp53";
- marvell,function = "gpio";
- };
-
- pmx_gpio_keys_pins: gpio-keys-pins {
- marvell,pins = "mpp54";
- marvell,function = "gpio";
- };
-};
-
-&bm {
- status = "okay";
-};
-
-&bm_bppi {
- status = "okay";
-};
-
-ð0 {
- pinctrl-names = "default";
- pinctrl-0 = <&ge0_rgmii_pins>;
- status = "okay";
-
- phy-connection-type = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <0>;
- bm,pool-short = <1>;
- nvmem-cells = <&macaddr_bdinfo_d880 0>;
- nvmem-cell-names = "mac-address";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
-};
-
-&usb3_0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pmx_usb_pins>;
- status = "okay";
-
- vbus-supply = <®_usb_vbus>;
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spi1_pins>;
- status = "okay";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <50000000>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- reg = <0x0 0x1c0000>;
- label = "u-boot";
- read-only;
- };
-
- partition@1c0000 {
- reg = <0x1c0000 0x10000>;
- label = "firmware-info";
-
- /*
- * 0x10 - 0x2f : image name (image1)
- * 0x30 - 0x4f : image name (image2)
- * 0x170 (1byte): active image (0x0/0x1)
- * 0x184 - 0x185: kernel block count (image1)
- * 0x18c - 0x18d: rootfs block count (image1)
- * 0x194 - 0x195: kernel block count (image2)
- * 0x19c - 0x19d: rootfs block count (image2)
- * 0x1be (1byte): bit7 -> active flag (image1)?
- * 0x1ce (1byte): bit7 -> active flag (image2)?
- *
- * Note: block size --> 0x200 (512 bytes)
- */
- };
-
- partition@1d0000 {
- reg = <0x1d0000 0x10000>;
- label = "dtb";
- read-only;
- };
-
- partition@1e0000 {
- reg = <0x1e0000 0x10000>;
- label = "u-boot-env";
- read-only;
- };
-
- partition@1f0000 {
- reg = <0x1f0000 0x10000>;
- label = "board-info";
- read-only;
-
- nvmem-layout {
- compatible = "fixed-layout";
- #address-cells = <1>;
- #size-cells = <1>;
-
- macaddr_bdinfo_d880: macaddr@d880 {
- compatible = "mac-base";
- reg = <0xd880 0x6>;
- #nvmem-cell-cells = <1>;
- };
- };
- };
-
- partition@200000 {
- reg = <0x200000 0x600000>;
- label = "kernel";
- };
-
- partition@800000 {
- reg = <0x800000 0x1800000>;
- label = "rootfs";
- };
-
- partition@2000000 {
- reg = <0x2000000 0x600000>;
- label = "kn2";
- read-only;
- };
-
- partition@2600000 {
- reg = <0x2600000 0x1800000>;
- label = "rfs2";
- read-only;
- };
-
- partition@3e00000 {
- reg = <0x3e00000 0x1200000>;
- label = "part1";
- read-only;
- };
-
- partition@5000000 {
- reg = <0x5000000 0x1200000>;
- label = "part2";
- read-only;
- };
-
- partition@6200000 {
- reg = <0x6200000 0x1e00000>;
- label = "config";
- read-only;
- };
- };
- };
-};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include "armada-385.dtsi"
+
+/ {
+ aliases {
+ led-boot = &led_status_green;
+ led-failsafe = &led_status_red;
+ led-running = &led_status_green;
+ led-upgrade = &led_status_green;
+ label-mac-device = ð0;
+ };
+
+ chosen {
+ stdout-path = "serial0:9600n8";
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmx_gpio_keys_pins>;
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ gpio_leds: gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmx_gpio_leds_pins>;
+
+ led-0 {
+ gpios = <&gpio0 30 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_ALARM;
+ };
+
+ led-1 {
+ gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = "ha";
+ };
+
+ led_status_green: led-2 {
+ gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led-3 {
+ gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = "ha";
+ };
+
+ led-4 {
+ gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_ALARM;
+ };
+
+ led_status_red: led-5 {
+ gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led-6 {
+ gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <4>;
+ linux,default-trigger = "mv88e6xxx-1:01:1Gbps";
+ };
+
+ led-7 {
+ gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <4>;
+ linux,default-trigger = "mv88e6xxx-1:01:100Mbps";
+ };
+
+ led-8 {
+ gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <3>;
+ linux,default-trigger = "mv88e6xxx-1:02:100Mbps";
+ };
+
+ led-9 {
+ gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <3>;
+ linux,default-trigger = "mv88e6xxx-1:02:1Gbps";
+ };
+
+ led-10 {
+ gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <1>;
+ linux,default-trigger = "mv88e6xxx-1:04:1Gbps";
+ };
+
+ led-11 {
+ gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <1>;
+ linux,default-trigger = "mv88e6xxx-1:04:100Mbps";
+ };
+
+ led-12 {
+ gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <2>;
+ linux,default-trigger = "mv88e6xxx-1:03:1Gbps";
+ };
+
+ led-13 {
+ gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_SPEED_LAN;
+ function-enumerator = <2>;
+ linux,default-trigger = "mv88e6xxx-1:03:100Mbps";
+ };
+ };
+
+ reg_usb_vbus: regulator-usb-vbus {
+ compatible = "fixed-regulator";
+ regulator-name = "usb-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
+ regulator-always-on;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+
+ gpio2: gpio@24 {
+ compatible = "nxp,pca9555";
+ reg = <0x24>;
+ gpio-controller;
+ #gpio-cells = <0x2>;
+ };
+
+ hwmon@28 {
+ compatible = "nuvoton,nct7802";
+ reg = <0x28>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&pinctrl {
+ pmx_gpio_leds_pins: gpio-leds-pins {
+ marvell,pins = "mpp30", "mpp32", "mpp33", "mpp35",
+ "mpp45", "mpp47";
+ marvell,function = "gpio";
+ };
+
+ pmx_usb_pins: usb-pins {
+ marvell,pins = "mpp53";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_keys_pins: gpio-keys-pins {
+ marvell,pins = "mpp54";
+ marvell,function = "gpio";
+ };
+};
+
+&bm {
+ status = "okay";
+};
+
+&bm_bppi {
+ status = "okay";
+};
+
+ð0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ status = "okay";
+
+ phy-connection-type = "rgmii-id";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+ nvmem-cells = <&macaddr_bdinfo_d880 0>;
+ nvmem-cell-names = "mac-address";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&usb3_0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmx_usb_pins>;
+ status = "okay";
+
+ vbus-supply = <®_usb_vbus>;
+};
+
+&spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x0 0x1c0000>;
+ label = "u-boot";
+ read-only;
+ };
+
+ partition@1c0000 {
+ reg = <0x1c0000 0x10000>;
+ label = "firmware-info";
+
+ /*
+ * 0x10 - 0x2f : image name (image1)
+ * 0x30 - 0x4f : image name (image2)
+ * 0x170 (1byte): active image (0x0/0x1)
+ * 0x184 - 0x185: kernel block count (image1)
+ * 0x18c - 0x18d: rootfs block count (image1)
+ * 0x194 - 0x195: kernel block count (image2)
+ * 0x19c - 0x19d: rootfs block count (image2)
+ * 0x1be (1byte): bit7 -> active flag (image1)?
+ * 0x1ce (1byte): bit7 -> active flag (image2)?
+ *
+ * Note: block size --> 0x200 (512 bytes)
+ */
+ };
+
+ partition@1d0000 {
+ reg = <0x1d0000 0x10000>;
+ label = "dtb";
+ read-only;
+ };
+
+ partition@1e0000 {
+ reg = <0x1e0000 0x10000>;
+ label = "u-boot-env";
+ read-only;
+ };
+
+ partition@1f0000 {
+ reg = <0x1f0000 0x10000>;
+ label = "board-info";
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_bdinfo_d880: macaddr@d880 {
+ compatible = "mac-base";
+ reg = <0xd880 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ partition@200000 {
+ reg = <0x200000 0x600000>;
+ label = "kernel";
+ };
+
+ partition@800000 {
+ reg = <0x800000 0x1800000>;
+ label = "rootfs";
+ };
+
+ partition@2000000 {
+ reg = <0x2000000 0x600000>;
+ label = "kn2";
+ read-only;
+ };
+
+ partition@2600000 {
+ reg = <0x2600000 0x1800000>;
+ label = "rfs2";
+ read-only;
+ };
+
+ partition@3e00000 {
+ reg = <0x3e00000 0x1200000>;
+ label = "part1";
+ read-only;
+ };
+
+ partition@5000000 {
+ reg = <0x5000000 0x1200000>;
+ label = "part2";
+ read-only;
+ };
+
+ partition@6200000 {
+ reg = <0x6200000 0x1e00000>;
+ label = "config";
+ read-only;
+ };
+ };
+ };
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-5xe.dtsi"
+
+/ {
+ model = "Fortinet FortiWiFi 50E-2R";
+ compatible = "fortinet,fwf-50e-2r", "marvell,armada385", "marvell,armada380";
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "armada-385-fortinet-fg-5xe.dtsi"
+
+/ {
+ model = "Fortinet FortiWiFi 51E";
+ compatible = "fortinet,fwf-51e", "marvell,armada385", "marvell,armada380";
+};
+
+&ahci0 {
+ status = "okay";
+};
+
+&pciec {
+ status = "okay";
+};
+
+&pcie2 {
+ status = "okay";
+};
gpios = <&cp0_gpio2 4 GPIO_ACTIVE_LOW>;
};
};
+
+ thermal-zones {
+ chassis0-thermal {
+ thermal-sensors = <&puzzle_hwmon 0>;
+ PUZZLE_FAN_CHASSIS_THERMAL(chassis0, &chassis_fan_group0);
+ };
+
+ chassis1-thermal {
+ thermal-sensors = <&puzzle_hwmon 1>;
+ PUZZLE_FAN_CHASSIS_THERMAL(chassis1, &chassis_fan_group0);
+ };
+
+ cp0-phy0-thermal {
+ thermal-sensors = <&cp0_nbaset_phy0>;
+ PUZZLE_FAN_THERMAL(cp0_phy0, &chassis_fan_group0);
+ };
+
+ cp0-phy1-thermal {
+ thermal-sensors = <&cp0_nbaset_phy1>;
+ PUZZLE_FAN_THERMAL(cp0_phy1, &chassis_fan_group0);
+ };
+
+ cp0-phy2-thermal {
+ thermal-sensors = <&cp0_nbaset_phy2>;
+ PUZZLE_FAN_THERMAL(cp0_phy2, &chassis_fan_group0);
+ };
+
+ cp1-phy0-thermal {
+ thermal-sensors = <&cp1_nbaset_phy0>;
+ PUZZLE_FAN_THERMAL(cp1_phy0, &chassis_fan_group0);
+ };
+
+ cp1-phy1-thermal {
+ thermal-sensors = <&cp1_nbaset_phy1>;
+ PUZZLE_FAN_THERMAL(cp1_phy1, &chassis_fan_group0);
+ };
+
+ cp1-phy2-thermal {
+ thermal-sensors = <&cp1_nbaset_phy2>;
+ PUZZLE_FAN_THERMAL(cp1_phy2, &chassis_fan_group0);
+ };
+ };
};
&uart0 {
};
};
- hwmon {
+ puzzle_hwmon: hwmon {
compatible = "iei,wt61p803-puzzle-hwmon";
#address-cells = <1>;
#size-cells = <0>;
+ #thermal-sensor-cells = <1>;
chassis_fan_group0: fan-group@0 {
#cooling-cells = <2>;
};
};
-&ap_thermal_ic {
- PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
-};
-
-&cp0_thermal_ic {
- PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
-};
-
/* on-board eMMC - U9 */
&ap_sdhci0 {
pinctrl-names = "default";
cp0_nbaset_phy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
+ #thermal-sensor-cells = <0>;
};
cp0_nbaset_phy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
+ #thermal-sensor-cells = <0>;
};
cp0_nbaset_phy2: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
+ #thermal-sensor-cells = <0>;
};
};
cp1_nbaset_phy0: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
+ #thermal-sensor-cells = <0>;
};
cp1_nbaset_phy1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
+ #thermal-sensor-cells = <0>;
};
cp1_nbaset_phy2: ethernet-phy@5 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
+ #thermal-sensor-cells = <0>;
};
};
};
};
-&cp1_thermal_ic {
- PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
-};
-
&cp1_usb3_1 {
status = "okay";
phys = <&cp1_comphy3 1>;
tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
+
+ thermal-zones {
+ chassis0-thermal {
+ thermal-sensors = <&puzzle_hwmon 0>;
+ PUZZLE_FAN_CHASSIS_THERMAL(chassis0, &chassis_fan_group0);
+ };
+
+ chassis1-thermal {
+ thermal-sensors = <&puzzle_hwmon 1>;
+ PUZZLE_FAN_CHASSIS_THERMAL(chassis1, &chassis_fan_group0);
+ };
+
+ cp0-phy0-thermal {
+ thermal-sensors = <&cp0_nbaset_phy0>;
+ PUZZLE_FAN_THERMAL(cp0_phy0, &chassis_fan_group0);
+ };
+
+ cp0-phy1-thermal {
+ thermal-sensors = <&cp0_nbaset_phy1>;
+ PUZZLE_FAN_THERMAL(cp0_phy1, &chassis_fan_group0);
+ };
+
+ cp0-phy2-thermal {
+ thermal-sensors = <&cp0_nbaset_phy2>;
+ PUZZLE_FAN_THERMAL(cp0_phy2, &chassis_fan_group0);
+ };
+
+ cp1-phy0-thermal {
+ thermal-sensors = <&cp1_nbaset_phy0>;
+ PUZZLE_FAN_THERMAL(cp1_phy0, &chassis_fan_group0);
+ };
+
+ cp1-phy1-thermal {
+ thermal-sensors = <&cp1_nbaset_phy1>;
+ PUZZLE_FAN_THERMAL(cp1_phy1, &chassis_fan_group0);
+ };
+
+ cp1-phy2-thermal {
+ thermal-sensors = <&cp1_nbaset_phy2>;
+ PUZZLE_FAN_THERMAL(cp1_phy2, &chassis_fan_group0);
+ };
+
+ cp2-phy0-thermal {
+ thermal-sensors = <&cp2_nbaset_phy0>;
+ PUZZLE_FAN_THERMAL(cp2_phy0, &chassis_fan_group0);
+ };
+
+ cp2-phy1-thermal {
+ thermal-sensors = <&cp2_nbaset_phy1>;
+ PUZZLE_FAN_THERMAL(cp2_phy1, &chassis_fan_group0);
+ };
+
+ cp2-phy2-thermal {
+ thermal-sensors = <&cp2_nbaset_phy2>;
+ PUZZLE_FAN_THERMAL(cp2_phy2, &chassis_fan_group0);
+ };
+ };
+
};
&uart0 {
};
};
- hwmon {
+ puzzle_hwmon: hwmon {
compatible = "iei,wt61p803-puzzle-hwmon";
#address-cells = <1>;
#size-cells = <0>;
+ #thermal-sensor-cells = <1>;
chassis_fan_group0: fan-group@0 {
#cooling-cells = <2>;
};
};
-&ap_thermal_ic {
- PUZZLE_FAN_THERMAL(ic, &chassis_fan_group0);
-};
-
-&cp0_thermal_ic {
- PUZZLE_FAN_THERMAL(cp0, &chassis_fan_group0);
-};
-
-
/* on-board eMMC - U9 */
&ap_sdhci0 {
pinctrl-names = "default";
&cp0_xmdio {
status = "okay";
- cp0_nbaset_phy0: ethernet-phy@0 {
+ cp0_nbaset_phy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
+ #thermal-sensor-cells = <0>;
};
- cp0_nbaset_phy1: ethernet-phy@1 {
+ cp0_nbaset_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
+ #thermal-sensor-cells = <0>;
};
- cp0_nbaset_phy2: ethernet-phy@2 {
+ cp0_nbaset_phy2: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
+ #thermal-sensor-cells = <0>;
};
};
&cp1_xmdio {
status = "okay";
- cp1_nbaset_phy0: ethernet-phy@3 {
+ cp1_nbaset_phy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
+ #thermal-sensor-cells = <0>;
};
- cp1_nbaset_phy1: ethernet-phy@4 {
+ cp1_nbaset_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
+ #thermal-sensor-cells = <0>;
};
- cp1_nbaset_phy2: ethernet-phy@5 {
+ cp1_nbaset_phy2: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
+ #thermal-sensor-cells = <0>;
};
};
};
};
-&cp1_thermal_ic {
- PUZZLE_FAN_THERMAL(cp1, &chassis_fan_group0);
-};
-
/*
* Instantiate the second connected CP115
*/
&cp2_xmdio {
status = "okay";
- cp2_nbaset_phy0: ethernet-phy@6 {
+ cp2_nbaset_phy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <2>;
+ #thermal-sensor-cells = <0>;
};
- cp2_nbaset_phy1: ethernet-phy@7 {
+ cp2_nbaset_phy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
+ #thermal-sensor-cells = <0>;
};
cp2_nbaset_phy2: ethernet-phy@8 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <8>;
+ #thermal-sensor-cells = <0>;
};
};
};
};
};
-
-&cp2_thermal_ic {
- PUZZLE_FAN_THERMAL(cp2, &chassis_fan_group0);
-};
-#define PUZZLE_FAN_THERMAL(_cname, _fan) \
- polling-delay-passive = <500>; \
- polling-delay = <1000>; \
- \
- trips { \
- cpu-hot { \
- temperature = <75000>; \
- hysteresis = <5000>; \
- type = "hot"; \
- }; \
- _cname##_active_full: cpu-active-full { \
- temperature = <70000>; \
- hysteresis = <5000>; \
- type = "active"; \
- }; \
- _cname##_active_high: cpu-active-high { \
- temperature = <65000>; \
- hysteresis = <5000>; \
- type = "active"; \
- }; \
- _cname##_active_med: cpu-active-med { \
- temperature = <62500>; \
- hysteresis = <3000>; \
- type = "active"; \
- }; \
- _cname##_active_low: cpu-active-low { \
- temperature = <60000>; \
- hysteresis = <3000>; \
- type = "active"; \
- }; \
- _cname##_active_min: cpu-active-min { \
- temperature = <55000>; \
- hysteresis = <5000>; \
- type = "active"; \
- }; \
- _cname##_active_idle: cpu-active-idle { \
- temperature = <50000>; \
- hysteresis = <5000>; \
- type = "active"; \
- }; \
- }; \
- cooling-maps { \
- cpu-active-full { \
- trip = <&_cname##_active_full>; \
- cooling-device = <_fan THERMAL_NO_LIMIT \
- THERMAL_NO_LIMIT>; \
- }; \
- cpu-active-high { \
- trip = <&_cname##_active_high>; \
- cooling-device = <_fan 4 5>; \
- }; \
- cpu-active-med { \
- trip = <&_cname##_active_med>; \
- cooling-device = <_fan 3 4>; \
- }; \
- cpu-active-low { \
- trip = <&_cname##_active_low>; \
- cooling-device = <_fan 2 3>; \
- }; \
- cpu-active-min { \
- trip = <&_cname##_active_min>; \
- cooling-device = <_fan 1 2>; \
- }; \
- cpu-active-idle { \
- trip = <&_cname##_active_idle>; \
- cooling-device = <_fan 0 0>; \
- }; \
+#define PUZZLE_FAN_THERMAL(_cname, _fan) \
+ polling-delay-passive = <0>; \
+ polling-delay = <1000>; \
+ \
+ trips { \
+ _cname##_active_full: trip-point5 { \
+ temperature = <70000>; \
+ hysteresis = <3000>; \
+ type = "active"; \
+ }; \
+ _cname##_active_very_high: trip-point4 { \
+ temperature = <67500>; \
+ hysteresis = <3000>; \
+ type = "active"; \
+ }; \
+ _cname##_active_high: trip-point3 { \
+ temperature = <65000>; \
+ hysteresis = <5000>; \
+ type = "active"; \
+ }; \
+ _cname##_active_med: trip-point2 { \
+ temperature = <62500>; \
+ hysteresis = <3000>; \
+ type = "active"; \
+ }; \
+ _cname##_active_low: trip-point1 { \
+ temperature = <60000>; \
+ hysteresis = <3000>; \
+ type = "active"; \
+ }; \
+ _cname##_active_min: trip-point0 { \
+ temperature = <55000>; \
+ hysteresis = <5000>; \
+ type = "active"; \
+ }; \
+ }; \
+ cooling-maps { \
+ map5 { \
+ trip = <&_cname##_active_full>; \
+ cooling-device = <_fan 6 6>; \
+ }; \
+ map4 { \
+ trip = <&_cname##_active_very_high>; \
+ cooling-device = <_fan 5 5>; \
+ }; \
+ map3 { \
+ trip = <&_cname##_active_high>; \
+ cooling-device = <_fan 4 4>; \
+ }; \
+ map2 { \
+ trip = <&_cname##_active_med>; \
+ cooling-device = <_fan 3 3>; \
+ }; \
+ map1 { \
+ trip = <&_cname##_active_low>; \
+ cooling-device = <_fan 2 2>; \
+ }; \
+ map0 { \
+ trip = <&_cname##_active_min>; \
+ cooling-device = <_fan 1 1>; \
+ }; \
+ }
+
+#define PUZZLE_FAN_CHASSIS_THERMAL(_cname, _fan) \
+ polling-delay-passive = <0>; \
+ polling-delay = <5000>; \
+ \
+ trips { \
+ _cname##_active_full: trip-point2 { \
+ temperature = <70000>; \
+ hysteresis = <3000>; \
+ type = "active"; \
+ }; \
+ _cname##_active_med: trip-point1 { \
+ temperature = <62500>; \
+ hysteresis = <3000>; \
+ type = "active"; \
+ }; \
+ _cname##_active_min: trip-point0 { \
+ temperature = <55000>; \
+ hysteresis = <5000>; \
+ type = "active"; \
+ }; \
+ }; \
+ cooling-maps { \
+ map2 { \
+ trip = <&_cname##_active_full>; \
+ cooling-device = <_fan 6 6>; \
+ }; \
+ map1 { \
+ trip = <&_cname##_active_med>; \
+ cooling-device = <_fan 3 3>; \
+ }; \
+ map0 { \
+ trip = <&_cname##_active_min>; \
+ cooling-device = <_fan 1 1>; \
+ }; \
}
endef
TARGET_DEVICES += cznic_turris-omnia
-define Device/fortinet_fg-30e
+define Device/fortinet
DEVICE_VENDOR := Fortinet
- DEVICE_MODEL := FortiGate 30E
SOC := armada-385
KERNEL := kernel-bin | append-dtb
- KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
- gzip-filename FGT30E
KERNEL_SIZE := 6144k
- DEVICE_DTS := armada-385-fortinet-fg-30e
IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | \
sysupgrade-tar rootfs=$$$$@ | append-metadata
DEVICE_PACKAGES := kmod-hwmon-nct7802
endef
+
+define Device/fortinet_fg-30e
+ $(Device/fortinet)
+ DEVICE_MODEL := FortiGate 30E
+ DEVICE_DTS := armada-385-fortinet-fg-30e
+ KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
+ gzip-filename FGT30E
+endef
TARGET_DEVICES += fortinet_fg-30e
define Device/fortinet_fg-50e
- DEVICE_VENDOR := Fortinet
+ $(Device/fortinet)
DEVICE_MODEL := FortiGate 50E
- SOC := armada-385
- KERNEL := kernel-bin | append-dtb
+ DEVICE_DTS := armada-385-fortinet-fg-50e
KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
gzip-filename FGT50E
- KERNEL_SIZE := 6144k
- DEVICE_DTS := armada-385-fortinet-fg-50e
- IMAGE/sysupgrade.bin := append-rootfs | pad-rootfs | \
- sysupgrade-tar rootfs=$$$$@ | append-metadata
- DEVICE_PACKAGES := kmod-hwmon-nct7802
endef
TARGET_DEVICES += fortinet_fg-50e
+define Device/fortinet_fg-51e
+ $(Device/fortinet)
+ DEVICE_MODEL := FortiGate 51E
+ DEVICE_DTS := armada-385-fortinet-fg-51e
+ KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
+ gzip-filename FGT51E
+endef
+TARGET_DEVICES += fortinet_fg-51e
+
+define Device/fortinet_fg-52e
+ $(Device/fortinet)
+ DEVICE_MODEL := FortiGate 52E
+ DEVICE_DTS := armada-385-fortinet-fg-52e
+ KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
+ gzip-filename FGT52E
+endef
+TARGET_DEVICES += fortinet_fg-52e
+
+define Device/fortinet_fwf-50e-2r
+ $(Device/fortinet)
+ DEVICE_MODEL := FortiWiFi 50E-2R
+ DEVICE_DTS := armada-385-fortinet-fwf-50e-2r
+ KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
+ gzip-filename FW502R
+ DEVICE_PACKAGES += kmod-ath10k-ct ath10k-firmware-qca988x-ct \
+ wpad-basic-mbedtls
+endef
+TARGET_DEVICES += fortinet_fwf-50e-2r
+
+define Device/fortinet_fwf-51e
+ $(Device/fortinet)
+ DEVICE_MODEL := FortiWiFi 51E
+ DEVICE_DTS := armada-385-fortinet-fwf-51e
+ KERNEL_INITRAMFS := kernel-bin | append-dtb | fortigate-header | \
+ gzip-filename FWF51E
+ DEVICE_PACKAGES += kmod-ath9k wpad-basic-mbedtls
+endef
+TARGET_DEVICES += fortinet_fwf-51e
+
define Device/globalscale_mirabox
$(Device/NAND-512K)
DEVICE_VENDOR := Globalscale
--- /dev/null
+From 9685ce100f0d302501117113ef0a526ad1acca1d Mon Sep 17 00:00:00 2001
+From: Ram Chandrasekar <rkumbako@codeaurora.org>
+Date: Mon, 7 May 2018 11:54:08 -0600
+Subject: [PATCH] drivers: thermal: step_wise: add support for hysteresis
+
+Step wise governor increases the mitigation level when the temperature
+goes above a threshold and will decrease the mitigation when the
+temperature falls below the threshold. If it were a case, where the
+temperature hovers around a threshold, the mitigation will be applied
+and removed at every iteration. This reaction to the temperature is
+inefficient for performance.
+
+The use of hysteresis temperature could avoid this ping-pong of
+mitigation by relaxing the mitigation to happen only when the
+temperature goes below this lower hysteresis value.
+
+Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
+Signed-off-by: Lina Iyer <ilina@codeaurora.org>
+[forward-ported for Linux 6.6, as stop-gap downstream solution]
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/thermal/gov_step_wise.c | 23 ++++++++++++++++-------
+ 1 file changed, 16 insertions(+), 7 deletions(-)
+
+--- a/drivers/thermal/gov_step_wise.c
++++ b/drivers/thermal/gov_step_wise.c
+@@ -86,22 +86,31 @@ static void thermal_zone_trip_update(str
+ struct thermal_instance *instance;
+ bool throttle = false;
+ int old_target;
++ int hyst_temp;
+
+ trend = get_tz_trend(tz, trip_id);
+
+- if (tz->temperature >= trip->temperature) {
+- throttle = true;
+- trace_thermal_zone_trip(tz, trip_id, trip->type);
+- }
+-
+- dev_dbg(&tz->device, "Trip%d[type=%d,temp=%d]:trend=%d,throttle=%d\n",
+- trip_id, trip->type, trip->temperature, trend, throttle);
++ hyst_temp = trip->temperature - trip->hysteresis;
++ dev_dbg(&tz->device, "Trip%d[type=%d,temp=%d,hyst=%d]:trend=%d,throttle=%d\n",
++ trip_id, trip->type, trip->temperature, hyst_temp, trend, throttle);
+
+ list_for_each_entry(instance, &tz->thermal_instances, tz_node) {
+ if (instance->trip != trip)
+ continue;
+
+ old_target = instance->target;
++ throttle = false;
++ /*
++ * Lower the mitigation only if the temperature
++ * goes below the hysteresis temperature.
++ */
++ if (tz->temperature >= trip->temperature ||
++ (tz->temperature >= hyst_temp &&
++ old_target != THERMAL_NO_TARGET)) {
++ throttle = true;
++ trace_thermal_zone_trip(tz, trip_id, trip->type);
++ }
++
+ instance->target = get_target_state(instance, trend, throttle);
+ dev_dbg(&instance->cdev->device, "old_target=%d, target=%d\n",
+ old_target, (int)instance->target);
--- /dev/null
+--- a/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
++++ b/drivers/hwmon/iei-wt61p803-puzzle-hwmon.c
+@@ -251,6 +251,7 @@ static const struct hwmon_ops iei_wt61p8
+ };
+
+ static const struct hwmon_channel_info *iei_wt61p803_puzzle_info[] = {
++ HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
+ HWMON_CHANNEL_INFO(pwm,
+ HWMON_PWM_INPUT,
+ HWMON_PWM_INPUT),
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
# CONFIG_KPSS_XCC is not set
+CONFIG_LEDS_TLC591XX=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
# CONFIG_REGULATOR_CPR3 is not set
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include "ipq8074-ess.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ model = "Linksys MX8500";
+ compatible = "linksys,mx8500", "qcom,ipq8074";
+
+ aliases {
+ serial0 = &blsp1_uart5;
+ serial1 = &blsp1_uart3;
+ led-boot = &led_system_blue;
+ led-running = &led_system_blue;
+ led-failsafe = &led_system_red;
+ led-upgrade = &led_system_green;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
+ };
+
+ gpio_export {
+ compatible = "gpio-export";
+ #size-cells = <0>;
+
+ bt_pwr {
+ gpio-export,name = "bt_pwr";
+ gpio-export,output = <1>;
+ gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&button_pins>;
+ pinctrl-names = "default";
+
+ reset-button {
+ label = "reset";
+ gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps-button {
+ label = "wps";
+ gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+};
+
+&tlmm {
+ button_pins: button-state {
+ pins = "gpio64", "gpio67";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio_pins: mdio-state {
+ mdc-pins {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio-pins {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+};
+
+&blsp1_uart3 {
+ status = "okay";
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ /*
+ * Bootloader will find the NAND DT node by the compatible and
+ * then "fixup" it by adding the partitions from the SMEM table
+ * using the legacy bindings thus making it impossible for us
+ * to change the partition table or utilize NVMEM for calibration.
+ * So add a dummy partitions node that bootloader will populate
+ * and set it as disabled so the kernel ignores it instead of
+ * printing warnings due to the broken way bootloader adds the
+ * partitions.
+ */
+ partitions {
+ status = "disabled";
+ };
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "0:mibib";
+ reg = <0x100000 0x100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "0:bootconfig";
+ reg = <0x200000 0x80000>;
+ read-only;
+ };
+
+ partition@280000 {
+ label = "0:bootconfig1";
+ reg = <0x280000 0x80000>;
+ read-only;
+ };
+
+ partition@300000 {
+ label = "0:qsee";
+ reg = <0x300000 0x300000>;
+ read-only;
+ };
+
+ partition@600000 {
+ label = "0:qsee_1";
+ reg = <0x600000 0x300000>;
+ read-only;
+ };
+
+ partition@900000 {
+ label = "0:devcfg";
+ reg = <0x900000 0x80000>;
+ read-only;
+ };
+
+ partition@980000 {
+ label = "0:devcfg_1";
+ reg = <0x980000 0x80000>;
+ read-only;
+ };
+
+ partition@a00000 {
+ label = "0:apdp";
+ reg = <0xa00000 0x80000>;
+ read-only;
+ };
+
+ partition@a80000 {
+ label = "0:apdp_1";
+ reg = <0xa80000 0x80000>;
+ read-only;
+ };
+
+ partition@b00000 {
+ label = "0:rpm";
+ reg = <0xb00000 0x80000>;
+ read-only;
+ };
+
+ partition@b80000 {
+ label = "0:rpm_1";
+ reg = <0xb80000 0x80000>;
+ read-only;
+ };
+
+ partition@c00000 {
+ label = "0:cdt";
+ reg = <0xc00000 0x80000>;
+ read-only;
+ };
+
+ partition@c80000 {
+ label = "0:cdt_1";
+ reg = <0xc80000 0x80000>;
+ read-only;
+ };
+
+ partition@d00000 {
+ label = "0:appsblenv";
+ reg = <0xd00000 0x80000>;
+ };
+
+ partition@d80000 {
+ label = "0:appsbl";
+ reg = <0xd80000 0x100000>;
+ read-only;
+ };
+
+ partition@e80000 {
+ label = "0:appsbl_1";
+ reg = <0xe80000 0x100000>;
+ read-only;
+ };
+
+ partition@f80000 {
+ label = "0:art";
+ reg = <0xf80000 0x80000>;
+ read-only;
+ };
+
+ partition@1000000 {
+ label = "u_env";
+ reg = <0x1000000 0x40000>;
+ };
+
+ partition@1040000 {
+ label = "s_env";
+ reg = <0x1040000 0x20000>;
+ };
+
+ partition@1060000 {
+ label = "devinfo";
+ reg = <0x1060000 0x20000>;
+ read-only;
+ };
+
+ partition@1080000 {
+ label = "kernel";
+ reg = <0x1080000 0x9600000>;
+ };
+
+ partition@1680000 {
+ label = "rootfs";
+ reg = <0x1680000 0x9000000>;
+ };
+
+ partition@a680000 {
+ label = "alt_kernel";
+ reg = <0xa680000 0x9600000>;
+ };
+
+ partition@ac80000 {
+ label = "alt_rootfs";
+ reg = <0xac80000 0x9000000>;
+ };
+
+ partition@13c80000 {
+ label = "sysdiag";
+ reg = <0x13c80000 0x200000>;
+ read-only;
+ };
+
+ partition@13e80000 {
+ label = "0:ethphyfw";
+ reg = <0x13e80000 0x100000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ aqr_fw: firmware@0 {
+ /* Skip the QCOM MBN Header of 40 bytes */
+ reg = <0x28 0x60002>;
+ };
+ };
+ };
+
+ partition@13f80000 {
+ label = "syscfg";
+ reg = <0x13f80000 0xb180000>;
+ read-only;
+ };
+
+ partition@1f100000 {
+ label = "app_data";
+ reg = <0x1f100000 0x500000>;
+ read-only;
+ };
+
+ partition@1f600000 {
+ label = "0:wififw";
+ reg = <0x1f600000 0xa00000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&blsp1_i2c2 {
+ status = "okay";
+
+ led-controller@62 {
+ compatible = "nxp,pca9633";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x62>;
+ nxp,hw-blink;
+
+ led_system_red: led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led_system_green: led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ };
+
+ led_system_blue: led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ ethernet-phy-package@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "qcom,qca8075-package";
+ reg = <0>;
+
+ qcom,package-mode = "qsgmii";
+
+ qca8075_0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+ };
+
+ aqr114c: ethernet-phy@8 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <8>;
+ reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ firmware-name = "marvell/AQR-G4_v5.6.5-AQR_WNC_SAQA-L2_GT_ID45287_VER24005.cld";
+ nvmem-cells = <&aqr_fw>;
+ nvmem-cell-names = "firmware";
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_lan_bmp = <(ESS_PORT1 | ESS_PORT2 | ESS_PORT3 | ESS_PORT4)>; /* lan port bitmap */
+ switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
+ switch_mac_mode = <MAC_MODE_QSGMII>; /* mac mode for uniphy instance0*/
+ switch_mac_mode2 = <MAC_MODE_USXGMII>; /* mac mode for uniphy instance2*/
+
+ qcom,port_phyinfo {
+ port@1 {
+ port_id = <1>;
+ phy_address = <0>;
+ };
+
+ port@2 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+
+ port@3 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+
+ port@4 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+
+ port@6 {
+ port_id = <6>;
+ phy_address = <8>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ ethernet-phy-ieee802.3-c45;
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp1 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_0>;
+ label = "lan1";
+};
+
+&dp2 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_1>;
+ label = "lan2";
+};
+
+&dp3 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_2>;
+ label = "lan3";
+};
+
+&dp4 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&qca8075_3>;
+ label = "lan4";
+};
+
+&dp6_syn {
+ status = "okay";
+ phy-mode = "usxgmii";
+ phy-handle = <&aqr114c>;
+ label = "wan";
+};
+
+&ssphy_0 {
+ status = "okay";
+};
+
+&qusb_phy_0 {
+ status = "okay";
+};
+
+&usb_0 {
+ status = "okay";
+};
+
+&pcie_qmp0 {
+ status = "okay";
+};
+
+&pcie0 {
+ status = "okay";
+
+ perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
+
+ bridge@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+
+ wifi@1,0 {
+ status = "okay";
+
+ /* ath11k has no DT compatible for PCI cards */
+ compatible = "pci17cb,1104";
+ reg = <0x00010000 0 0 0 0>;
+
+ qcom,ath11k-calibration-variant = "Linksys-MX8500";
+ };
+ };
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Linksys-MX8500";
+};
compatible = "ethernet-phy-id004d.d101";
reg = <28>;
reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
+ reset-deassert-us = <10000>;
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2021, Flole <flole@flole.de>
+ * Copyright (c) 2023, Andrew Smith <gul.code@outlook.com>
+ */
+
+/dts-v1/;
+
+#include "ipq8074.dtsi"
+#include "ipq8074-ess.dtsi"
+#include "ipq8074-hk-cpu.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ serial0 = &blsp1_uart5;
+ led-boot = &led_front_blue;
+ led-failsafe = &led_front_red;
+ led-running = &led_front_green;
+ led-upgrade = &led_front_white;
+ label-mac-device = &dp2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs-append = " ubi.mtd=rootfs root=/dev/ubiblock0_0";
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_front_blue: front-blue {
+ function = LED_FUNCTION_STATUS;
+ gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_BLUE>;
+ };
+
+ led_front_green: front-green {
+ function = LED_FUNCTION_STATUS;
+ gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ };
+
+ led_front_red: front-red {
+ function = LED_FUNCTION_STATUS;
+ gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ };
+
+ led_front_white: front-white {
+ function = LED_FUNCTION_STATUS;
+ gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_WHITE>;
+ };
+
+ led_power_green: power-green {
+ function = LED_FUNCTION_POWER;
+ gpios = <&tlmm 21 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "on";
+ };
+
+ led_power_red: power-red {
+ function = LED_FUNCTION_POWER;
+ gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ panic-indicator;
+ };
+ };
+};
+
+&tlmm {
+ mdio_pins: mdio-pins {
+ mdc {
+ pins = "gpio68";
+ function = "mdc";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+
+ mdio {
+ pins = "gpio69";
+ function = "mdio";
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ };
+
+ leds_pins: leds_pinmux {
+ led_power_green {
+ pins = "gpio21";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ led_power_red {
+ pins = "gpio22";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ led_white {
+ pins = "gpio26";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ led_green {
+ pins = "gpio29";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ led_red {
+ pins = "gpio31";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+
+ led_blue {
+ pins = "gpio33";
+ function = "gpio";
+ drive-strength = <8>;
+ bias-pull-down;
+ };
+ };
+};
+
+&blsp1_uart5 {
+ status = "okay";
+};
+
+&blsp1_i2c2 {
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+
+ tlc59208f@27 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "ti,tlc59108";
+ reg = <0x27>;
+
+ led@0 {
+ label = "rgb:led0";
+ reg = <0>;
+ linux,default-trigger = "default-off";
+ };
+
+ led@1 {
+ label = "rgb:led1";
+ reg = <1>;
+ linux,default-trigger = "default-off";
+ };
+
+ led@2 {
+ label = "rgb:led2";
+ reg = <2>;
+ linux,default-trigger = "default-off";
+ };
+
+ led@3 {
+ label = "rgb:led3";
+ reg = <3>;
+ linux,default-trigger = "default-off";
+ };
+ };
+};
+
+&prng {
+ status = "okay";
+};
+
+&cryptobam {
+ status = "okay";
+};
+
+&crypto {
+ status = "okay";
+};
+
+&qpic_bam {
+ status = "okay";
+};
+
+&qpic_nand {
+ status = "okay";
+
+ /*
+ * Bootloader will find the NAND DT node by the compatible and
+ * then "fixup" it by adding the partitions from the SMEM table
+ * using the legacy bindings thus making it impossible for us
+ * to change the partition table or utilize NVMEM for calibration.
+ * So add a dummy partitions node that bootloader will populate
+ * and set it as disabled so the kernel ignores it instead of
+ * printing warnings due to the broken way bootloader adds the
+ * partitions.
+ */
+ partitions {
+ status = "disabled";
+ };
+
+ nand@0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "0:sbl1";
+ reg = <0x00 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "0:mibib";
+ reg = <0x100000 0x100000>;
+ read-only;
+ };
+
+ partition@200000 {
+ label = "0:bootconfig";
+ reg = <0x200000 0x80000>;
+ read-only;
+ };
+
+ partition@280000 {
+ label = "0:bootconfig_1";
+ reg = <0x280000 0x80000>;
+ read-only;
+ };
+
+ partition@300000 {
+ label = "0:qsee";
+ reg = <0x300000 0x300000>;
+ read-only;
+ };
+
+ partition@600000 {
+ label = "0:qsee_1";
+ reg = <0x600000 0x300000>;
+ read-only;
+ };
+
+ partition@900000 {
+ label = "0:devcfg";
+ reg = <0x900000 0x80000>;
+ read-only;
+ };
+
+ partition@980000 {
+ label = "0:devcfg_1";
+ reg = <0x980000 0x80000>;
+ read-only;
+ };
+
+ partition@a00000 {
+ label = "0:apdp";
+ reg = <0xa00000 0x80000>;
+ read-only;
+ };
+
+ partition@a80000 {
+ label = "0:apdp_1";
+ reg = <0xa80000 0x80000>;
+ read-only;
+ };
+
+ partition@b00000 {
+ label = "0:rpm";
+ reg = <0xb00000 0x80000>;
+ read-only;
+ };
+
+ partition@b80000 {
+ label = "0:rpm_1";
+ reg = <0xb80000 0x80000>;
+ read-only;
+ };
+
+ partition@c00000 {
+ label = "0:cdt";
+ reg = <0xc00000 0x80000>;
+ read-only;
+ };
+
+ partition@c80000 {
+ label = "0:cdt_1";
+ reg = <0xc80000 0x80000>;
+ read-only;
+ };
+
+ partition@d00000 {
+ label = "0:appsblenv";
+ reg = <0xd00000 0x80000>;
+ };
+
+ partition@d80000 {
+ label = "0:appsbl";
+ reg = <0xd80000 0x100000>;
+ read-only;
+ };
+
+ partition@e80000 {
+ label = "0:appsbl_1";
+ reg = <0xe80000 0x100000>;
+ read-only;
+ };
+
+ partition@f80000 {
+ label = "0:art";
+ reg = <0xf80000 0x80000>;
+ read-only;
+ };
+
+ partition@1000000 {
+ label = "0:art.bak";
+ reg = <0x1000000 0x80000>;
+ read-only;
+ };
+
+ partition@1080000 {
+ label = "config";
+ reg = <0x1080000 0x100000>;
+ };
+
+ partition@1180000 {
+ label = "boarddata1";
+ reg = <0x1180000 0x100000>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_boarddata1_0: macaddr@0 {
+ reg = <0x0 0x6>;
+ };
+
+ macaddr_boarddata1_6: macaddr@6 {
+ reg = <0x6 0x6>;
+ };
+ };
+ };
+
+ partition@1280000 {
+ label = "boarddata2";
+ reg = <0x1280000 0x100000>;
+ };
+
+ partition@1380000 {
+ label = "pot";
+ reg = <0x1380000 0x100000>;
+ read-only;
+ };
+
+ partition@1480000 {
+ label = "dnidata";
+ reg = <0x1480000 0x500000>;
+ read-only;
+ };
+
+ partition@1980000 {
+ label = "kernel";
+ reg = <0x1980000 0x620000>;
+ };
+
+ partition@1fa0000 {
+ label = "rootfs";
+ reg = <0x1fa0000 0x66e0000>;
+ };
+
+ partition@8680000 {
+ label = "kernel2";
+ reg = <0x8680000 0x620000>;
+ read-only;
+ };
+
+ partition@8ca0000 {
+ label = "rootfs2";
+ reg = <0x8ca0000 0x66e0000>;
+ read-only;
+ };
+ };
+ };
+};
+
+&mdio {
+ status = "okay";
+
+ pinctrl-0 = <&mdio_pins>;
+ pinctrl-names = "default";
+ reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
+
+ ethernet-phy-package@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ compatible = "qcom,qca8075-package";
+
+ qca8075_1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+
+ qca8075_2: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ };
+
+ qca8075_3: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ };
+
+ qca8075_4: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <4>;
+ };
+ };
+
+ qca8081_28: ethernet-phy@28 {
+ compatible = "ethernet-phy-id004d.d101";
+ reg = <28>;
+ reset-deassert-us = <10000>;
+ reset-gpios = <&tlmm 25 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&switch {
+ status = "okay";
+
+ switch_lan_bmp = <(ESS_PORT2 | ESS_PORT3 | ESS_PORT4 | ESS_PORT5)>; /* lan port bitmap */
+ switch_wan_bmp = <ESS_PORT6>; /* wan port bitmap */
+ switch_mac_mode = <MAC_MODE_PSGMII>; /* mac mode for uniphy instance0*/
+ switch_mac_mode2 = <MAC_MODE_SGMII_PLUS>; /* mac mode for uniphy instance2*/
+
+ qcom,port_phyinfo {
+ port@2 {
+ port_id = <2>;
+ phy_address = <1>;
+ };
+ port@3 {
+ port_id = <3>;
+ phy_address = <2>;
+ };
+ port@4 {
+ port_id = <4>;
+ phy_address = <3>;
+ };
+ port@5 {
+ port_id = <5>;
+ phy_address = <4>;
+ };
+ port@6 {
+ port_id = <6>;
+ phy_address = <28>;
+ port_mac_sel = "QGMAC_PORT";
+ };
+ };
+};
+
+&edma {
+ status = "okay";
+};
+
+&dp2 {
+ status = "okay";
+ phy-handle = <&qca8075_1>;
+ label = "lan2";
+ nvmem-cells = <&macaddr_boarddata1_0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp3 {
+ status = "okay";
+ phy-handle = <&qca8075_2>;
+ label = "lan3";
+ nvmem-cells = <&macaddr_boarddata1_0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp4 {
+ status = "okay";
+ phy-handle = <&qca8075_3>;
+ label = "lan4";
+ nvmem-cells = <&macaddr_boarddata1_0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp5 {
+ status = "okay";
+ phy-handle = <&qca8075_4>;
+ label = "lan5";
+ nvmem-cells = <&macaddr_boarddata1_0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&dp6 {
+ status = "okay";
+ phy-handle = <&qca8081_28>;
+ label = "wan";
+ nvmem-cells = <&macaddr_boarddata1_6>;
+ nvmem-cell-names = "mac-address";
+};
+
+&wifi {
+ status = "okay";
+
+ qcom,ath11k-calibration-variant = "Netgear-SXK80";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Flole <flole@flole.de> */
+
+/dts-v1/;
+
+#include "ipq8074-sxk80.dtsi"
+
+/ {
+ model = "Netgear SXR80";
+ compatible = "netgear,sxr80", "qcom,ipq8074";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/* Copyright (c) 2021, Flole <flole@flole.de> */
+
+/dts-v1/;
+
+#include "ipq8074-sxk80.dtsi"
+
+/ {
+ model = "Netgear SXS80";
+ compatible = "netgear,sxs80", "qcom,ipq8074";
+};
endef
TARGET_DEVICES += edimax_cax1800
-define Device/linksys_mx4200v1
+define Device/linksys_mx
$(call Device/FitImage)
DEVICE_VENDOR := Linksys
- DEVICE_MODEL := MX4200
- DEVICE_VARIANT := v1
BLOCKSIZE := 128k
PAGESIZE := 2048
KERNEL_SIZE := 6144k
IMAGE_SIZE := 147456k
NAND_SIZE := 512m
- SOC := ipq8174
+ SOC := ipq8072
IMAGES += factory.bin
- IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MX4200
- DEVICE_PACKAGES := kmod-leds-pca963x ipq-wifi-linksys_mx4200 kmod-bluetooth
+ IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=$$$$(DEVICE_MODEL)
+ DEVICE_PACKAGES := kmod-leds-pca963x
+endef
+
+define Device/linksys_mx4200v1
+ $(call Device/linksys_mx)
+ DEVICE_MODEL := MX4200
+ DEVICE_VARIANT := v1
+ SOC := ipq8174
+ DEVICE_PACKAGES += ipq-wifi-linksys_mx4200 kmod-bluetooth
endef
TARGET_DEVICES += linksys_mx4200v1
TARGET_DEVICES += linksys_mx4200v2
define Device/linksys_mx5300
- $(call Device/FitImage)
- DEVICE_VENDOR := Linksys
+ $(call Device/linksys_mx)
DEVICE_MODEL := MX5300
- BLOCKSIZE := 128k
- PAGESIZE := 2048
- KERNEL_SIZE := 6144k
- IMAGE_SIZE := 147456k
- NAND_SIZE := 512m
- SOC := ipq8072
- IMAGES += factory.bin
- IMAGE/factory.bin := append-kernel | pad-to $$$$(KERNEL_SIZE) | append-ubi | linksys-image type=MX5300
- DEVICE_PACKAGES := kmod-leds-pca963x kmod-rtc-ds1307 \
- ipq-wifi-linksys_mx5300 kmod-ath10k-ct ath10k-firmware-qca9984-ct
+ DEVICE_PACKAGES += kmod-rtc-ds1307 ipq-wifi-linksys_mx5300 \
+ kmod-ath10k-ct ath10k-firmware-qca9984-ct
endef
TARGET_DEVICES += linksys_mx5300
+define Device/linksys_mx8500
+ $(call Device/linksys_mx)
+ DEVICE_MODEL := MX8500
+ DEVICE_PACKAGES += ipq-wifi-linksys_mx8500 kmod-ath11k-pci \
+ ath11k-firmware-qcn9074 kmod-bluetooth
+endef
+TARGET_DEVICES += linksys_mx8500
+
define Device/netgear_rax120v2
$(call Device/FitImage)
$(call Device/UbiFit)
endef
TARGET_DEVICES += netgear_rax120v2
+define Device/netgear_sxk80
+ $(call Device/FitImage)
+ $(call Device/UbiFit)
+ DEVICE_PACKAGES += ipq-wifi-netgear_sxk80
+ DEVICE_VENDOR := Netgear
+ BLOCKSIZE := 128k
+ PAGESIZE := 2048
+ DEVICE_DTS_CONFIG := config@hk01
+ SOC := ipq8074
+ KERNEL_SIZE := 6272k
+ NETGEAR_HW_ID := 29766265+0+512+1024+4x4+4x4+4x4
+endef
+
+define Device/netgear_sxr80
+ $(call Device/netgear_sxk80)
+ DEVICE_MODEL := SXR80
+ NETGEAR_BOARD_ID := SXR80
+endef
+TARGET_DEVICES += netgear_sxr80
+
+define Device/netgear_sxs80
+ $(call Device/netgear_sxk80)
+ DEVICE_MODEL := SXS80
+ NETGEAR_BOARD_ID := SXS80
+endef
+TARGET_DEVICES += netgear_sxs80
+
define Device/netgear_wax218
$(call Device/FitImage)
$(call Device/UbiFit)
buffalo,wxr-5950ax12|\
dynalink,dl-wrx36|\
linksys,mx5300|\
+ linksys,mx8500|\
xiaomi,ax9000|\
zbtlink,zbt-z800ax)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" "wan"
netgear,rax120v2)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4 lan5" "wan"
;;
+ netgear,sxr80|\
+ netgear,sxs80)
+ ucidef_set_interfaces_lan_wan "lan2 lan3 lan4 lan5" "wan"
+ ;;
netgear,wax218|\
netgear,wax620)
ucidef_set_interface_lan "lan" "dhcp"
done
[ "$(mtd_get_mac_ascii u_env eth2addr)" != "$label_mac" ] && wan_mac=$label_mac
;;
+ linksys,mx8500)
+ label_mac=$(mtd_get_mac_ascii devinfo hw_mac_addr)
+ lan_mac=$(macaddr_add $label_mac 1)
+ wan_mac=$label_mac
+ ;;
esac
[ -n "$lan_mac" ] && ucidef_set_interface_macaddr "lan" $lan_mac
edgecore,eap102|\
edimax,cax1800|\
linksys,mx5300|\
+ netgear,sxr80|\
+ netgear,sxs80|\
netgear,wax218|\
netgear,wax620|\
netgear,wax630|\
xiaomi,ax3600|\
xiaomi,ax9000|\
yuncore,ax880|\
- zbtlink,zbt-z800ax|\
zte,mf269)
caldata_extract "0:art" 0x1000 0x20000
;;
- linksys,mx4200v1)
+ linksys,mx4200v1|\
+ linksys,mx8500)
caldata_extract "0:art" 0x1000 0x20000
ath11k_remove_regdomain
;;
spectrum,sax1v1k)
caldata_extract_mmc "0:ART" 0x1000 0x20000
;;
+ zbtlink,zbt-z800ax)
+ caldata_extract "0:art" 0x1000 0x20000
+ label_mac=$(get_mac_label)
+ ath11k_patch_mac $(macaddr_add $label_mac -1) 0
+ ath11k_patch_mac $(macaddr_add $label_mac -2) 1
+ ath11k_set_macflag
+ ;;
zyxel,nbg7815)
caldata_extract "0:art" 0x1000 0x20000
label_mac=$(get_mac_label)
"ath11k/QCN9074/hw1.0/cal-pci-0000:01:00.0.bin"|\
"ath11k/QCN9074/hw1.0/cal-pci-0001:01:00.0.bin")
case "$board" in
+ linksys,mx8500)
+ caldata_extract "0:art" 0x26800 0x20000
+ ath11k_remove_regdomain
+ ;;
prpl,haze)
caldata_extract_mmc "0:ART" 0x26800 0x20000
;;
[ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) 2 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) 3 > /sys${DEVPATH}/macaddress
;;
- zbtlink,zbt-z800ax)
- [ "$PHYNBR" = "0" ] && macaddr_add $(get_mac_label) -1 > /sys${DEVPATH}/macaddress
- [ "$PHYNBR" = "1" ] && macaddr_add $(get_mac_label) -2 > /sys${DEVPATH}/macaddress
+ netgear,sxr80|\
+ netgear,sxs80)
+ [ "$PHYNBR" = "0" ] && mtd_get_mac_binary boarddata1 0x0c > /sys${DEVPATH}/macaddress
+ #boarddata1 doesn't have a MAC for the 2G interface
+ [ "$PHYNBR" = "1" ] && macaddr_setbit_la $(get_mac_label) > /sys${DEVPATH}/macaddress
+ [ "$PHYNBR" = "2" ] && mtd_get_mac_binary boarddata1 0x12 > /sys${DEVPATH}/macaddress
;;
esac
;;
linksys,mx4200v1|\
linksys,mx4200v2|\
- linksys,mx5300)
+ linksys,mx5300|\
+ linksys,mx8500)
mtd resetbc s_env || true
;;
esac
dynalink,dl-wrx36|\
edimax,cax1800|\
netgear,rax120v2|\
+ netgear,sxr80|\
+ netgear,sxs80|\
netgear,wax218|\
netgear,wax620|\
netgear,wax630|\
;;
linksys,mx4200v1|\
linksys,mx4200v2|\
- linksys,mx5300)
+ linksys,mx5300|\
+ linksys,mx8500)
boot_part="$(fw_printenv -n boot_part)"
if [ "$boot_part" -eq "1" ]; then
fw_setenv boot_part 2
--- /dev/null
+From 5f78d9213ae753e2242b0f6a5d4a5e98e55ddc76 Mon Sep 17 00:00:00 2001
+From: Paweł Owoc <frut3k7@gmail.com>
+Date: Wed, 13 Mar 2024 11:27:06 +0100
+Subject: [PATCH] arm64: dts: qcom: ipq8074: Remove unused gpio from QPIC pins
+
+gpio16 will only be used for LCD support, as its NAND/LCDC data[8]
+so its bit 9 of the parallel QPIC interface, and ONFI NAND is only 8
+or 16-bit with only 8-bit one being supported in our case so that pin
+is unused.
+
+It should be dropped from the default NAND pinctrl configuration
+as its unused and only needed for LCD.
+
+Signed-off-by: Paweł Owoc <frut3k7@gmail.com>
+Reviewed-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
+Link: https://lore.kernel.org/r/20240313102713.1727458-1-frut3k7@gmail.com
+Signed-off-by: Bjorn Andersson <andersson@kernel.org>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -372,7 +372,7 @@
+ "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio10", "gpio11",
+ "gpio12", "gpio13", "gpio14",
+- "gpio15", "gpio16", "gpio17";
++ "gpio15", "gpio17";
+ function = "qpic";
+ drive-strength = <8>;
+ bias-disable;
};
gdma: gdma@2800 {
- compatible = "ralink,mt7620a-gdma", "ralink,rt3883-gdma";
+ compatible = "ralink,rt3883-gdma";
reg = <0x2800 0x800>;
resets = <&sysc 14>;
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621_dlink_dir_nand_128m.dtsi"
+
+/ {
+ compatible = "dlink,dir-2055-a1", "mediatek,mt7621-soc";
+ model = "D-Link DIR-2055 A1";
+};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7621.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "elecom,wrc-x1800gs", "mediatek,mt7621-soc";
+ model = "ELECOM WRC-X1800GS";
+
+ aliases {
+ led-boot = &led_power_green;
+ led-failsafe = &led_power_red;
+ led-running = &led_power_green;
+ led-upgrade = &led_power_green;
+ label-mac-device = &gmac0;
+ };
+
+ chosen {
+ bootargs-override = "console=ttyS0,115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ /* available on 1st HW rev. */
+ led-0 {
+ gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_2GHZ;
+ function-enumerator = <1>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ led_power_green: led-1 {
+ gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_POWER;
+ };
+
+ led_power_red: led-2 {
+ gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ };
+
+ led-3 {
+ gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_WLAN_2GHZ;
+ };
+
+ led-4 {
+ gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_WPS;
+ };
+
+ led-5 {
+ gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_5GHZ;
+ linux,default-trigger = "phy1tpt";
+ };
+
+ /* available on 2nd HW rev. */
+ led-6 {
+ gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WLAN_2GHZ;
+ function-enumerator = <2>;
+ linux,default-trigger = "phy0tpt";
+ };
+
+ led-7 {
+ gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_WLAN_5GHZ;
+ };
+
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ button-reset {
+ label = "reset";
+ gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ switch-ap {
+ label = "ap";
+ gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_0>;
+ };
+
+ switch-router {
+ label = "router";
+ gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_1>;
+ };
+
+ button-wps {
+ label = "wps";
+ gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WPS_BUTTON>;
+ };
+ };
+};
+
+&nand {
+ status = "okay";
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x0 0x100000>;
+ label = "u-boot";
+ read-only;
+ };
+
+ partition@100000 {
+ reg = <0x100000 0x100000>;
+ label = "u-boot-env";
+ };
+
+ partition@200000 {
+ reg = <0x200000 0x1c0000>;
+ label = "factory";
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_factory_0: eeprom@0 {
+ reg = <0x0 0xe00>;
+ };
+
+ precal_factory_e10: precal@e10 {
+ reg = <0xe10 0x19c10>;
+ };
+
+ macaddr_factory_1fdf4: macaddr@1fdf4 {
+ reg = <0x1fdf4 0x6>;
+ };
+
+ macaddr_factory_1fdfa: macaddr@1fdfa {
+ reg = <0x1fdfa 0x6>;
+ };
+ };
+ };
+
+ /* "RAS1" on stock fw */
+ partition@3c0000 {
+ compatible = "fixed-partitions";
+ reg = <0x3c0000 0x3240000>;
+ label = "firmware";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ reg = <0x0 0x800000>;
+ label = "kernel";
+ };
+
+ partition@800000 {
+ reg = <0x800000 0x2a40000>;
+ label = "ubi";
+ };
+ };
+
+ partition@3600000 {
+ reg = <0x3600000 0x100000>;
+ label = "Config";
+ read-only;
+ };
+
+ /* "RAS2" on stock fw */
+ partition@3700000 {
+ reg = <0x3700000 0x3240000>;
+ label = "firmware2";
+ };
+
+ partition@6940000 {
+ reg = <0x6940000 0x100000>;
+ label = "Config_2";
+ read-only;
+ };
+
+ partition@6a40000 {
+ reg = <0x6a40000 0x100000>;
+ label = "persist";
+ };
+
+ partition@6b40000 {
+ reg = <0x6b40000 0x100000>;
+ label = "mesh";
+ read-only;
+ };
+
+ partition@6c40000 {
+ reg = <0x6c40000 0x1340000>;
+ label = "backup";
+ read-only;
+ };
+ };
+};
+
+&gmac0 {
+ nvmem-cells = <&macaddr_factory_1fdfa>;
+ nvmem-cell-names = "mac-address";
+};
+
+&gmac1 {
+ status = "okay";
+ label = "wan";
+ phy-handle = <ðphy0>;
+
+ nvmem-cells = <&macaddr_factory_1fdf4>;
+ nvmem-cell-names = "mac-address";
+};
+
+ðphy0 {
+ /delete-property/ interrupts;
+};
+
+&pcie {
+ status = "okay";
+};
+
+&pcie1 {
+ wifi@0,0 {
+ compatible = "mediatek,mt76";
+ reg = <0x0000 0 0 0 0>;
+ nvmem-cells = <&eeprom_factory_0>, <&precal_factory_e10>;
+ nvmem-cell-names = "eeprom", "precal";
+ mediatek,disable-radar-background;
+ };
+};
+
+&pcie2 {
+ status = "disabled";
+};
+
+&switch0 {
+ ports {
+ port@1 {
+ status = "okay";
+ label = "lan2";
+ };
+
+ port@2 {
+ status = "okay";
+ label = "lan1";
+ };
+ };
+};
+
+&state_default {
+ gpio {
+ groups = "i2c", "uart3", "jtag", "wdt";
+ function = "gpio";
+ };
+};
+
+&uartlite {
+ pinctrl-0 = <&uart1_pins>;
+ pinctrl-names = "default";
+};
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
+ ieee80211-freq-limit = <2400000 2500000>;
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "mt7628an.dtsi"
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+
+/ {
+ compatible = "tplink,archer-mr200-v5", "mediatek,mt7628an-soc";
+ model = "TP-Link Archer MR200 v5";
+
+ aliases {
+ led-boot = &led_power;
+ led-failsafe = &led_power;
+ led-running = &led_power;
+ led-upgrade = &led_power;
+ label-mac-device = ðernet;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ lan {
+ function = LED_FUNCTION_LAN;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
+ };
+
+ wan {
+ function = LED_FUNCTION_WAN;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
+ };
+
+ led_power: power {
+ function = LED_FUNCTION_POWER;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpio 39 GPIO_ACTIVE_LOW>;
+ };
+
+ signal1 {
+ label = "white:signal1";
+ gpios = <&gpio 41 GPIO_ACTIVE_LOW>;
+ };
+
+ signal2 {
+ label = "white:signal2";
+ gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
+ };
+
+ signal3 {
+ label = "white:signal3";
+ gpios = <&gpio 43 GPIO_ACTIVE_LOW>;
+ };
+
+ wlan {
+ function = LED_FUNCTION_WLAN;
+ color = <LED_COLOR_ID_WHITE>;
+ gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "phy0tpt";
+ };
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RESTART>;
+ };
+
+ rfkill {
+ label = "rfkill";
+ gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_RFKILL>;
+ };
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <104000000>;
+ m25p,fast-read;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x20000>;
+ read-only;
+ };
+
+ partition@20000 {
+ compatible = "tplink,firmware";
+ label = "firmware";
+ reg = <0x20000 0x7b0000>;
+ };
+
+ partition@7d0000 {
+ label = "config";
+ reg = <0x7d0000 0x10000>;
+ read-only;
+ };
+
+ partition@7e0000 {
+ label = "romfile";
+ reg = <0x7e0000 0x10000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ macaddr_romfile_f100: macaddr@f100 {
+ compatible = "mac-base";
+ reg = <0xf100 0x6>;
+ #nvmem-cell-cells = <1>;
+ };
+ };
+ };
+
+ partition@7f0000 {
+ label = "radio";
+ reg = <0x7f0000 0x10000>;
+ read-only;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ eeprom_radio_0: eeprom@0 {
+ reg = <0x0 0x400>;
+ };
+
+ eeprom_radio_8000: eeprom@8000 {
+ reg = <0x8000 0x200>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&state_default {
+ gpio {
+ groups = "i2c", "p0led_an", "p1led_an", "p2led_an", "p3led_an", "p4led_an", "uart1", "wdt";
+ function = "gpio";
+ };
+};
+
+&wmac {
+ nvmem-cells = <&eeprom_radio_0>, <&macaddr_romfile_f100 0>;
+ nvmem-cell-names = "eeprom", "mac-address";
+ status = "okay";
+};
+
+&esw {
+ mediatek,portdisable = <0x30>;
+};
+
+ðernet {
+ nvmem-cells = <&macaddr_romfile_f100 0>;
+ nvmem-cell-names = "mac-address";
+};
+
+&pcie {
+ status = "okay";
+};
+
+&pcie0 {
+ mt76@0,0 {
+ reg = <0x0000 0 0 0 0>;
+ ieee80211-freq-limit = <5000000 6000000>;
+ nvmem-cells = <&eeprom_radio_8000>, <&macaddr_romfile_f100 (-1)>;
+ nvmem-cell-names = "eeprom", "mac-address";
+ };
+};
};
&wmac {
- nvmem-cells = <&macaddr_factory_1f100>;
- nvmem-cell-names = "mac-address";
+ status = "okay";
+
+ nvmem-cells = <&eeprom_factory_20000>, <&macaddr_factory_1f100 0>;
+ nvmem-cell-names = "eeprom", "mac-address";
};
ðernet {
- nvmem-cells = <&macaddr_factory_1f100>;
+ nvmem-cells = <&macaddr_factory_1f100 0>;
nvmem-cell-names = "mac-address";
};
#size-cells = <1>;
macaddr_factory_1f100: macaddr@1f100 {
+ compatible = "mac-base";
reg = <0x1f100 0x6>;
+ #nvmem-cell-cells = <1>;
};
};
};
};
&wmac {
- nvmem-cells = <&macaddr_factory_1f100>;
- nvmem-cell-names = "mac-address";
+ status = "okay";
+
+ nvmem-cells = <&eeprom_factory_20000>, <&macaddr_factory_1f100 0>;
+ nvmem-cell-names = "eeprom", "mac-address";
};
ðernet {
- nvmem-cells = <&macaddr_factory_1f100>;
+ nvmem-cells = <&macaddr_factory_1f100 0>;
nvmem-cell-names = "mac-address";
};
#size-cells = <1>;
macaddr_factory_1f100: macaddr@1f100 {
+ compatible = "mac-base";
reg = <0x1f100 0x6>;
+ #nvmem-cell-cells = <1>;
};
};
};
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * GDMA4740 DMAC support
+ */
+
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/irq.h>
+#include <linux/of_dma.h>
+#include <linux/reset.h>
+#include <linux/of_device.h>
+
+#include "virt-dma.h"
+
+#define GDMA_REG_SRC_ADDR(x) (0x00 + (x) * 0x10)
+#define GDMA_REG_DST_ADDR(x) (0x04 + (x) * 0x10)
+
+#define GDMA_REG_CTRL0(x) (0x08 + (x) * 0x10)
+#define GDMA_REG_CTRL0_TX_MASK 0xffff
+#define GDMA_REG_CTRL0_TX_SHIFT 16
+#define GDMA_REG_CTRL0_CURR_MASK 0xff
+#define GDMA_REG_CTRL0_CURR_SHIFT 8
+#define GDMA_REG_CTRL0_SRC_ADDR_FIXED BIT(7)
+#define GDMA_REG_CTRL0_DST_ADDR_FIXED BIT(6)
+#define GDMA_REG_CTRL0_BURST_MASK 0x7
+#define GDMA_REG_CTRL0_BURST_SHIFT 3
+#define GDMA_REG_CTRL0_DONE_INT BIT(2)
+#define GDMA_REG_CTRL0_ENABLE BIT(1)
+#define GDMA_REG_CTRL0_SW_MODE BIT(0)
+
+#define GDMA_REG_CTRL1(x) (0x0c + (x) * 0x10)
+#define GDMA_REG_CTRL1_SEG_MASK 0xf
+#define GDMA_REG_CTRL1_SEG_SHIFT 22
+#define GDMA_REG_CTRL1_REQ_MASK 0x3f
+#define GDMA_REG_CTRL1_SRC_REQ_SHIFT 16
+#define GDMA_REG_CTRL1_DST_REQ_SHIFT 8
+#define GDMA_REG_CTRL1_NEXT_MASK 0x1f
+#define GDMA_REG_CTRL1_NEXT_SHIFT 3
+#define GDMA_REG_CTRL1_COHERENT BIT(2)
+#define GDMA_REG_CTRL1_FAIL BIT(1)
+#define GDMA_REG_CTRL1_MASK BIT(0)
+
+#define GDMA_REG_UNMASK_INT 0x200
+#define GDMA_REG_DONE_INT 0x204
+
+#define GDMA_REG_GCT 0x220
+#define GDMA_REG_GCT_CHAN_MASK 0x3
+#define GDMA_REG_GCT_CHAN_SHIFT 3
+#define GDMA_REG_GCT_VER_MASK 0x3
+#define GDMA_REG_GCT_VER_SHIFT 1
+#define GDMA_REG_GCT_ARBIT_RR BIT(0)
+
+#define GDMA_REG_REQSTS 0x2a0
+#define GDMA_REG_ACKSTS 0x2a4
+#define GDMA_REG_FINSTS 0x2a8
+
+/* for RT305X gdma registers */
+#define GDMA_RT305X_CTRL0_REQ_MASK 0xf
+#define GDMA_RT305X_CTRL0_SRC_REQ_SHIFT 12
+#define GDMA_RT305X_CTRL0_DST_REQ_SHIFT 8
+
+#define GDMA_RT305X_CTRL1_FAIL BIT(4)
+#define GDMA_RT305X_CTRL1_NEXT_MASK 0x7
+#define GDMA_RT305X_CTRL1_NEXT_SHIFT 1
+
+#define GDMA_RT305X_STATUS_INT 0x80
+#define GDMA_RT305X_STATUS_SIGNAL 0x84
+#define GDMA_RT305X_GCT 0x88
+
+/* for MT7621 gdma registers */
+#define GDMA_REG_PERF_START(x) (0x230 + (x) * 0x8)
+#define GDMA_REG_PERF_END(x) (0x234 + (x) * 0x8)
+
+enum gdma_dma_transfer_size {
+ GDMA_TRANSFER_SIZE_4BYTE = 0,
+ GDMA_TRANSFER_SIZE_8BYTE = 1,
+ GDMA_TRANSFER_SIZE_16BYTE = 2,
+ GDMA_TRANSFER_SIZE_32BYTE = 3,
+ GDMA_TRANSFER_SIZE_64BYTE = 4,
+};
+
+struct gdma_dma_sg {
+ dma_addr_t src_addr;
+ dma_addr_t dst_addr;
+ u32 len;
+};
+
+struct gdma_dma_desc {
+ struct virt_dma_desc vdesc;
+
+ enum dma_transfer_direction direction;
+ bool cyclic;
+
+ u32 residue;
+ unsigned int num_sgs;
+ struct gdma_dma_sg sg[];
+};
+
+struct gdma_dmaengine_chan {
+ struct virt_dma_chan vchan;
+ unsigned int id;
+ unsigned int slave_id;
+
+ dma_addr_t fifo_addr;
+ enum gdma_dma_transfer_size burst_size;
+
+ struct gdma_dma_desc *desc;
+ unsigned int next_sg;
+};
+
+struct gdma_dma_dev {
+ struct dma_device ddev;
+ struct device_dma_parameters dma_parms;
+ struct gdma_data *data;
+ void __iomem *base;
+ struct tasklet_struct task;
+ volatile unsigned long chan_issued;
+ atomic_t cnt;
+
+ struct gdma_dmaengine_chan chan[];
+};
+
+struct gdma_data {
+ int chancnt;
+ u32 done_int_reg;
+ void (*init)(struct gdma_dma_dev *dma_dev);
+ int (*start_transfer)(struct gdma_dmaengine_chan *chan);
+};
+
+static struct gdma_dma_dev *gdma_dma_chan_get_dev(
+ struct gdma_dmaengine_chan *chan)
+{
+ return container_of(chan->vchan.chan.device, struct gdma_dma_dev,
+ ddev);
+}
+
+static struct gdma_dmaengine_chan *to_gdma_dma_chan(struct dma_chan *c)
+{
+ return container_of(c, struct gdma_dmaengine_chan, vchan.chan);
+}
+
+static struct gdma_dma_desc *to_gdma_dma_desc(struct virt_dma_desc *vdesc)
+{
+ return container_of(vdesc, struct gdma_dma_desc, vdesc);
+}
+
+static inline uint32_t gdma_dma_read(struct gdma_dma_dev *dma_dev,
+ unsigned int reg)
+{
+ return readl(dma_dev->base + reg);
+}
+
+static inline void gdma_dma_write(struct gdma_dma_dev *dma_dev,
+ unsigned int reg, uint32_t val)
+{
+ writel(val, dma_dev->base + reg);
+}
+
+static enum gdma_dma_transfer_size gdma_dma_maxburst(u32 maxburst)
+{
+ if (maxburst < 2)
+ return GDMA_TRANSFER_SIZE_4BYTE;
+ else if (maxburst < 4)
+ return GDMA_TRANSFER_SIZE_8BYTE;
+ else if (maxburst < 8)
+ return GDMA_TRANSFER_SIZE_16BYTE;
+ else if (maxburst < 16)
+ return GDMA_TRANSFER_SIZE_32BYTE;
+ else
+ return GDMA_TRANSFER_SIZE_64BYTE;
+}
+
+static int gdma_dma_config(struct dma_chan *c,
+ struct dma_slave_config *config)
+{
+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
+
+ if (config->device_fc) {
+ dev_err(dma_dev->ddev.dev, "not support flow controller\n");
+ return -EINVAL;
+ }
+
+ switch (config->direction) {
+ case DMA_MEM_TO_DEV:
+ if (config->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) {
+ dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n");
+ return -EINVAL;
+ }
+ chan->fifo_addr = config->dst_addr;
+ chan->burst_size = gdma_dma_maxburst(config->dst_maxburst);
+ break;
+ case DMA_DEV_TO_MEM:
+ if (config->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) {
+ dev_err(dma_dev->ddev.dev, "only support 4 byte buswidth\n");
+ return -EINVAL;
+ }
+ chan->fifo_addr = config->src_addr;
+ chan->burst_size = gdma_dma_maxburst(config->src_maxburst);
+ break;
+ default:
+ dev_err(dma_dev->ddev.dev, "direction type %d error\n",
+ config->direction);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int gdma_dma_terminate_all(struct dma_chan *c)
+{
+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
+ unsigned long flags, timeout;
+ LIST_HEAD(head);
+ int i = 0;
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ chan->desc = NULL;
+ clear_bit(chan->id, &dma_dev->chan_issued);
+ vchan_get_all_descriptors(&chan->vchan, &head);
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+ vchan_dma_desc_free_list(&chan->vchan, &head);
+
+ /* wait dma transfer complete */
+ timeout = jiffies + msecs_to_jiffies(5000);
+ while (gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id)) &
+ GDMA_REG_CTRL0_ENABLE) {
+ if (time_after_eq(jiffies, timeout)) {
+ dev_err(dma_dev->ddev.dev, "chan %d wait timeout\n",
+ chan->id);
+ /* restore to init value */
+ gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), 0);
+ break;
+ }
+ cpu_relax();
+ i++;
+ }
+
+ if (i)
+ dev_dbg(dma_dev->ddev.dev, "terminate chan %d loops %d\n",
+ chan->id, i);
+
+ return 0;
+}
+
+static void rt305x_dump_reg(struct gdma_dma_dev *dma_dev, int id)
+{
+ dev_dbg(dma_dev->ddev.dev, "chan %d, src %08x, dst %08x, ctr0 %08x, ctr1 %08x, intr %08x, signal %08x\n",
+ id,
+ gdma_dma_read(dma_dev, GDMA_REG_SRC_ADDR(id)),
+ gdma_dma_read(dma_dev, GDMA_REG_DST_ADDR(id)),
+ gdma_dma_read(dma_dev, GDMA_REG_CTRL0(id)),
+ gdma_dma_read(dma_dev, GDMA_REG_CTRL1(id)),
+ gdma_dma_read(dma_dev, GDMA_RT305X_STATUS_INT),
+ gdma_dma_read(dma_dev, GDMA_RT305X_STATUS_SIGNAL));
+}
+
+static int rt305x_gdma_start_transfer(struct gdma_dmaengine_chan *chan)
+{
+ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
+ dma_addr_t src_addr, dst_addr;
+ struct gdma_dma_sg *sg;
+ u32 ctrl0, ctrl1;
+
+ /* verify chan is already stopped */
+ ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
+ if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) {
+ dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n",
+ chan->id, ctrl0);
+ rt305x_dump_reg(dma_dev, chan->id);
+ return -EINVAL;
+ }
+
+ sg = &chan->desc->sg[chan->next_sg];
+ if (chan->desc->direction == DMA_MEM_TO_DEV) {
+ src_addr = sg->src_addr;
+ dst_addr = chan->fifo_addr;
+ ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED |
+ (8 << GDMA_RT305X_CTRL0_SRC_REQ_SHIFT) |
+ (chan->slave_id << GDMA_RT305X_CTRL0_DST_REQ_SHIFT);
+ } else if (chan->desc->direction == DMA_DEV_TO_MEM) {
+ src_addr = chan->fifo_addr;
+ dst_addr = sg->dst_addr;
+ ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED |
+ (chan->slave_id << GDMA_RT305X_CTRL0_SRC_REQ_SHIFT) |
+ (8 << GDMA_RT305X_CTRL0_DST_REQ_SHIFT);
+ } else if (chan->desc->direction == DMA_MEM_TO_MEM) {
+ /*
+ * TODO: memcpy function have bugs. sometime it will copy
+ * more 8 bytes data when using dmatest verify.
+ */
+ src_addr = sg->src_addr;
+ dst_addr = sg->dst_addr;
+ ctrl0 = GDMA_REG_CTRL0_SW_MODE |
+ (8 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
+ (8 << GDMA_REG_CTRL1_DST_REQ_SHIFT);
+ } else {
+ dev_err(dma_dev->ddev.dev, "direction type %d error\n",
+ chan->desc->direction);
+ return -EINVAL;
+ }
+
+ ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) |
+ (chan->burst_size << GDMA_REG_CTRL0_BURST_SHIFT) |
+ GDMA_REG_CTRL0_DONE_INT | GDMA_REG_CTRL0_ENABLE;
+ ctrl1 = chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
+
+ chan->next_sg++;
+ gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
+ gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
+ gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
+
+ /* make sure next_sg is update */
+ wmb();
+ gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
+
+ return 0;
+}
+
+static void rt3883_dump_reg(struct gdma_dma_dev *dma_dev, int id)
+{
+ dev_dbg(dma_dev->ddev.dev, "chan %d, src %08x, dst %08x, ctr0 %08x, ctr1 %08x, unmask %08x, done %08x, req %08x, ack %08x, fin %08x\n",
+ id,
+ gdma_dma_read(dma_dev, GDMA_REG_SRC_ADDR(id)),
+ gdma_dma_read(dma_dev, GDMA_REG_DST_ADDR(id)),
+ gdma_dma_read(dma_dev, GDMA_REG_CTRL0(id)),
+ gdma_dma_read(dma_dev, GDMA_REG_CTRL1(id)),
+ gdma_dma_read(dma_dev, GDMA_REG_UNMASK_INT),
+ gdma_dma_read(dma_dev, GDMA_REG_DONE_INT),
+ gdma_dma_read(dma_dev, GDMA_REG_REQSTS),
+ gdma_dma_read(dma_dev, GDMA_REG_ACKSTS),
+ gdma_dma_read(dma_dev, GDMA_REG_FINSTS));
+}
+
+static int rt3883_gdma_start_transfer(struct gdma_dmaengine_chan *chan)
+{
+ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
+ dma_addr_t src_addr, dst_addr;
+ struct gdma_dma_sg *sg;
+ u32 ctrl0, ctrl1;
+
+ /* verify chan is already stopped */
+ ctrl0 = gdma_dma_read(dma_dev, GDMA_REG_CTRL0(chan->id));
+ if (unlikely(ctrl0 & GDMA_REG_CTRL0_ENABLE)) {
+ dev_err(dma_dev->ddev.dev, "chan %d is start(%08x).\n",
+ chan->id, ctrl0);
+ rt3883_dump_reg(dma_dev, chan->id);
+ return -EINVAL;
+ }
+
+ sg = &chan->desc->sg[chan->next_sg];
+ if (chan->desc->direction == DMA_MEM_TO_DEV) {
+ src_addr = sg->src_addr;
+ dst_addr = chan->fifo_addr;
+ ctrl0 = GDMA_REG_CTRL0_DST_ADDR_FIXED;
+ ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
+ (chan->slave_id << GDMA_REG_CTRL1_DST_REQ_SHIFT);
+ } else if (chan->desc->direction == DMA_DEV_TO_MEM) {
+ src_addr = chan->fifo_addr;
+ dst_addr = sg->dst_addr;
+ ctrl0 = GDMA_REG_CTRL0_SRC_ADDR_FIXED;
+ ctrl1 = (chan->slave_id << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
+ (32 << GDMA_REG_CTRL1_DST_REQ_SHIFT) |
+ GDMA_REG_CTRL1_COHERENT;
+ } else if (chan->desc->direction == DMA_MEM_TO_MEM) {
+ src_addr = sg->src_addr;
+ dst_addr = sg->dst_addr;
+ ctrl0 = GDMA_REG_CTRL0_SW_MODE;
+ ctrl1 = (32 << GDMA_REG_CTRL1_SRC_REQ_SHIFT) |
+ (32 << GDMA_REG_CTRL1_DST_REQ_SHIFT) |
+ GDMA_REG_CTRL1_COHERENT;
+ } else {
+ dev_err(dma_dev->ddev.dev, "direction type %d error\n",
+ chan->desc->direction);
+ return -EINVAL;
+ }
+
+ ctrl0 |= (sg->len << GDMA_REG_CTRL0_TX_SHIFT) |
+ (chan->burst_size << GDMA_REG_CTRL0_BURST_SHIFT) |
+ GDMA_REG_CTRL0_DONE_INT | GDMA_REG_CTRL0_ENABLE;
+ ctrl1 |= chan->id << GDMA_REG_CTRL1_NEXT_SHIFT;
+
+ chan->next_sg++;
+ gdma_dma_write(dma_dev, GDMA_REG_SRC_ADDR(chan->id), src_addr);
+ gdma_dma_write(dma_dev, GDMA_REG_DST_ADDR(chan->id), dst_addr);
+ gdma_dma_write(dma_dev, GDMA_REG_CTRL1(chan->id), ctrl1);
+
+ /* make sure next_sg is update */
+ wmb();
+ gdma_dma_write(dma_dev, GDMA_REG_CTRL0(chan->id), ctrl0);
+
+ return 0;
+}
+
+static inline int gdma_start_transfer(struct gdma_dma_dev *dma_dev,
+ struct gdma_dmaengine_chan *chan)
+{
+ return dma_dev->data->start_transfer(chan);
+}
+
+static int gdma_next_desc(struct gdma_dmaengine_chan *chan)
+{
+ struct virt_dma_desc *vdesc;
+
+ vdesc = vchan_next_desc(&chan->vchan);
+ if (!vdesc) {
+ chan->desc = NULL;
+ return 0;
+ }
+ chan->desc = to_gdma_dma_desc(vdesc);
+ chan->next_sg = 0;
+
+ return 1;
+}
+
+static void gdma_dma_chan_irq(struct gdma_dma_dev *dma_dev,
+ struct gdma_dmaengine_chan *chan)
+{
+ struct gdma_dma_desc *desc;
+ unsigned long flags;
+ int chan_issued;
+
+ chan_issued = 0;
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ desc = chan->desc;
+ if (desc) {
+ if (desc->cyclic) {
+ vchan_cyclic_callback(&desc->vdesc);
+ if (chan->next_sg == desc->num_sgs)
+ chan->next_sg = 0;
+ chan_issued = 1;
+ } else {
+ desc->residue -= desc->sg[chan->next_sg - 1].len;
+ if (chan->next_sg == desc->num_sgs) {
+ list_del(&desc->vdesc.node);
+ vchan_cookie_complete(&desc->vdesc);
+ chan_issued = gdma_next_desc(chan);
+ } else {
+ chan_issued = 1;
+ }
+ }
+ } else {
+ dev_dbg(dma_dev->ddev.dev, "chan %d no desc to complete\n",
+ chan->id);
+ }
+ if (chan_issued)
+ set_bit(chan->id, &dma_dev->chan_issued);
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+}
+
+static irqreturn_t gdma_dma_irq(int irq, void *devid)
+{
+ struct gdma_dma_dev *dma_dev = devid;
+ u32 done, done_reg;
+ unsigned int i;
+
+ done_reg = dma_dev->data->done_int_reg;
+ done = gdma_dma_read(dma_dev, done_reg);
+ if (unlikely(!done))
+ return IRQ_NONE;
+
+ /* clean done bits */
+ gdma_dma_write(dma_dev, done_reg, done);
+
+ i = 0;
+ while (done) {
+ if (done & 0x1) {
+ gdma_dma_chan_irq(dma_dev, &dma_dev->chan[i]);
+ atomic_dec(&dma_dev->cnt);
+ }
+ done >>= 1;
+ i++;
+ }
+
+ /* start only have work to do */
+ if (dma_dev->chan_issued)
+ tasklet_schedule(&dma_dev->task);
+
+ return IRQ_HANDLED;
+}
+
+static void gdma_dma_issue_pending(struct dma_chan *c)
+{
+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+ struct gdma_dma_dev *dma_dev = gdma_dma_chan_get_dev(chan);
+ unsigned long flags;
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ if (vchan_issue_pending(&chan->vchan) && !chan->desc) {
+ if (gdma_next_desc(chan)) {
+ set_bit(chan->id, &dma_dev->chan_issued);
+ tasklet_schedule(&dma_dev->task);
+ } else {
+ dev_dbg(dma_dev->ddev.dev, "chan %d no desc to issue\n",
+ chan->id);
+ }
+ }
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+}
+
+static struct dma_async_tx_descriptor *gdma_dma_prep_slave_sg(
+ struct dma_chan *c, struct scatterlist *sgl,
+ unsigned int sg_len, enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+ struct gdma_dma_desc *desc;
+ struct scatterlist *sg;
+ unsigned int i;
+
+ desc = kzalloc(struct_size(desc, sg, sg_len), GFP_ATOMIC);
+ if (!desc) {
+ dev_err(c->device->dev, "alloc sg decs error\n");
+ return NULL;
+ }
+ desc->residue = 0;
+
+ for_each_sg(sgl, sg, sg_len, i) {
+ if (direction == DMA_MEM_TO_DEV) {
+ desc->sg[i].src_addr = sg_dma_address(sg);
+ } else if (direction == DMA_DEV_TO_MEM) {
+ desc->sg[i].dst_addr = sg_dma_address(sg);
+ } else {
+ dev_err(c->device->dev, "direction type %d error\n",
+ direction);
+ goto free_desc;
+ }
+
+ if (unlikely(sg_dma_len(sg) > GDMA_REG_CTRL0_TX_MASK)) {
+ dev_err(c->device->dev, "sg len too large %d\n",
+ sg_dma_len(sg));
+ goto free_desc;
+ }
+ desc->sg[i].len = sg_dma_len(sg);
+ desc->residue += sg_dma_len(sg);
+ }
+
+ desc->num_sgs = sg_len;
+ desc->direction = direction;
+ desc->cyclic = false;
+
+ return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
+
+free_desc:
+ kfree(desc);
+ return NULL;
+}
+
+static struct dma_async_tx_descriptor *gdma_dma_prep_dma_memcpy(
+ struct dma_chan *c, dma_addr_t dest, dma_addr_t src,
+ size_t len, unsigned long flags)
+{
+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+ struct gdma_dma_desc *desc;
+ unsigned int num_periods, i;
+ size_t xfer_count;
+
+ if (len <= 0)
+ return NULL;
+
+ chan->burst_size = gdma_dma_maxburst(len >> 2);
+
+ xfer_count = GDMA_REG_CTRL0_TX_MASK;
+ num_periods = DIV_ROUND_UP(len, xfer_count);
+
+ desc = kzalloc(struct_size(desc, sg, num_periods), GFP_ATOMIC);
+ if (!desc) {
+ dev_err(c->device->dev, "alloc memcpy decs error\n");
+ return NULL;
+ }
+ desc->residue = len;
+
+ for (i = 0; i < num_periods; i++) {
+ desc->sg[i].src_addr = src;
+ desc->sg[i].dst_addr = dest;
+ if (len > xfer_count)
+ desc->sg[i].len = xfer_count;
+ else
+ desc->sg[i].len = len;
+ src += desc->sg[i].len;
+ dest += desc->sg[i].len;
+ len -= desc->sg[i].len;
+ }
+
+ desc->num_sgs = num_periods;
+ desc->direction = DMA_MEM_TO_MEM;
+ desc->cyclic = false;
+
+ return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
+}
+
+static struct dma_async_tx_descriptor *gdma_dma_prep_dma_cyclic(
+ struct dma_chan *c, dma_addr_t buf_addr, size_t buf_len,
+ size_t period_len, enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+ struct gdma_dma_desc *desc;
+ unsigned int num_periods, i;
+
+ if (buf_len % period_len)
+ return NULL;
+
+ if (period_len > GDMA_REG_CTRL0_TX_MASK) {
+ dev_err(c->device->dev, "cyclic len too large %d\n",
+ period_len);
+ return NULL;
+ }
+
+ num_periods = buf_len / period_len;
+ desc = kzalloc(struct_size(desc, sg, num_periods), GFP_ATOMIC);
+ if (!desc) {
+ dev_err(c->device->dev, "alloc cyclic decs error\n");
+ return NULL;
+ }
+ desc->residue = buf_len;
+
+ for (i = 0; i < num_periods; i++) {
+ if (direction == DMA_MEM_TO_DEV) {
+ desc->sg[i].src_addr = buf_addr;
+ } else if (direction == DMA_DEV_TO_MEM) {
+ desc->sg[i].dst_addr = buf_addr;
+ } else {
+ dev_err(c->device->dev, "direction type %d error\n",
+ direction);
+ goto free_desc;
+ }
+ desc->sg[i].len = period_len;
+ buf_addr += period_len;
+ }
+
+ desc->num_sgs = num_periods;
+ desc->direction = direction;
+ desc->cyclic = true;
+
+ return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
+
+free_desc:
+ kfree(desc);
+ return NULL;
+}
+
+static enum dma_status gdma_dma_tx_status(struct dma_chan *c,
+ dma_cookie_t cookie,
+ struct dma_tx_state *state)
+{
+ struct gdma_dmaengine_chan *chan = to_gdma_dma_chan(c);
+ struct virt_dma_desc *vdesc;
+ enum dma_status status;
+ unsigned long flags;
+ struct gdma_dma_desc *desc;
+
+ status = dma_cookie_status(c, cookie, state);
+ if (status == DMA_COMPLETE || !state)
+ return status;
+
+ spin_lock_irqsave(&chan->vchan.lock, flags);
+ desc = chan->desc;
+ if (desc && (cookie == desc->vdesc.tx.cookie)) {
+ /*
+ * We never update edesc->residue in the cyclic case, so we
+ * can tell the remaining room to the end of the circular
+ * buffer.
+ */
+ if (desc->cyclic)
+ state->residue = desc->residue -
+ ((chan->next_sg - 1) * desc->sg[0].len);
+ else
+ state->residue = desc->residue;
+ } else {
+ vdesc = vchan_find_desc(&chan->vchan, cookie);
+ if (vdesc)
+ state->residue = to_gdma_dma_desc(vdesc)->residue;
+ }
+ spin_unlock_irqrestore(&chan->vchan.lock, flags);
+
+ dev_dbg(c->device->dev, "tx residue %d bytes\n", state->residue);
+
+ return status;
+}
+
+static void gdma_dma_free_chan_resources(struct dma_chan *c)
+{
+ vchan_free_chan_resources(to_virt_chan(c));
+}
+
+static void gdma_dma_desc_free(struct virt_dma_desc *vdesc)
+{
+ kfree(container_of(vdesc, struct gdma_dma_desc, vdesc));
+}
+
+static void gdma_dma_tasklet(struct tasklet_struct *t)
+{
+ struct gdma_dma_dev *dma_dev = from_tasklet(dma_dev, t, task);
+ struct gdma_dmaengine_chan *chan;
+ static unsigned int last_chan;
+ unsigned int i, chan_mask;
+
+ /* record last chan to round robin all chans */
+ i = last_chan;
+ chan_mask = dma_dev->data->chancnt - 1;
+ do {
+ /*
+ * on mt7621. when verify with dmatest with all
+ * channel is enable. we need to limit only two
+ * channel is working at the same time. otherwise the
+ * data will have problem.
+ */
+ if (atomic_read(&dma_dev->cnt) >= 2) {
+ last_chan = i;
+ break;
+ }
+
+ if (test_and_clear_bit(i, &dma_dev->chan_issued)) {
+ chan = &dma_dev->chan[i];
+ if (chan->desc) {
+ atomic_inc(&dma_dev->cnt);
+ gdma_start_transfer(dma_dev, chan);
+ } else {
+ dev_dbg(dma_dev->ddev.dev,
+ "chan %d no desc to issue\n",
+ chan->id);
+ }
+ if (!dma_dev->chan_issued)
+ break;
+ }
+
+ i = (i + 1) & chan_mask;
+ } while (i != last_chan);
+}
+
+static void rt305x_gdma_init(struct gdma_dma_dev *dma_dev)
+{
+ u32 gct;
+
+ /* all chans round robin */
+ gdma_dma_write(dma_dev, GDMA_RT305X_GCT, GDMA_REG_GCT_ARBIT_RR);
+
+ gct = gdma_dma_read(dma_dev, GDMA_RT305X_GCT);
+ dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n",
+ (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
+ 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
+ GDMA_REG_GCT_CHAN_MASK));
+}
+
+static void rt3883_gdma_init(struct gdma_dma_dev *dma_dev)
+{
+ u32 gct;
+
+ /* all chans round robin */
+ gdma_dma_write(dma_dev, GDMA_REG_GCT, GDMA_REG_GCT_ARBIT_RR);
+
+ gct = gdma_dma_read(dma_dev, GDMA_REG_GCT);
+ dev_info(dma_dev->ddev.dev, "revision: %d, channels: %d\n",
+ (gct >> GDMA_REG_GCT_VER_SHIFT) & GDMA_REG_GCT_VER_MASK,
+ 8 << ((gct >> GDMA_REG_GCT_CHAN_SHIFT) &
+ GDMA_REG_GCT_CHAN_MASK));
+}
+
+static struct gdma_data rt305x_gdma_data = {
+ .chancnt = 8,
+ .done_int_reg = GDMA_RT305X_STATUS_INT,
+ .init = rt305x_gdma_init,
+ .start_transfer = rt305x_gdma_start_transfer,
+};
+
+static struct gdma_data rt3883_gdma_data = {
+ .chancnt = 16,
+ .done_int_reg = GDMA_REG_DONE_INT,
+ .init = rt3883_gdma_init,
+ .start_transfer = rt3883_gdma_start_transfer,
+};
+
+static const struct of_device_id gdma_of_match_table[] = {
+ { .compatible = "ralink,rt305x-gdma", .data = &rt305x_gdma_data },
+ { .compatible = "ralink,rt3883-gdma", .data = &rt3883_gdma_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, gdma_of_match_table);
+
+static int gdma_dma_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ struct gdma_dmaengine_chan *chan;
+ struct gdma_dma_dev *dma_dev;
+ struct dma_device *dd;
+ unsigned int i;
+ int ret;
+ int irq;
+ void __iomem *base;
+ struct gdma_data *data;
+
+ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+ if (ret)
+ return ret;
+
+ match = of_match_device(gdma_of_match_table, &pdev->dev);
+ if (!match)
+ return -EINVAL;
+ data = (struct gdma_data *)match->data;
+
+ dma_dev = devm_kzalloc(&pdev->dev,
+ struct_size(dma_dev, chan, data->chancnt),
+ GFP_KERNEL);
+ if (!dma_dev)
+ return -EINVAL;
+ dma_dev->data = data;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+ dma_dev->base = base;
+ tasklet_setup(&dma_dev->task, gdma_dma_tasklet);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return -EINVAL;
+ ret = devm_request_irq(&pdev->dev, irq, gdma_dma_irq,
+ 0, dev_name(&pdev->dev), dma_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request irq\n");
+ return ret;
+ }
+
+ ret = device_reset(&pdev->dev);
+ if (ret)
+ dev_err(&pdev->dev, "failed to reset: %d\n", ret);
+
+ dd = &dma_dev->ddev;
+ dma_cap_set(DMA_MEMCPY, dd->cap_mask);
+ dma_cap_set(DMA_SLAVE, dd->cap_mask);
+ dma_cap_set(DMA_CYCLIC, dd->cap_mask);
+ dd->device_free_chan_resources = gdma_dma_free_chan_resources;
+ dd->device_prep_dma_memcpy = gdma_dma_prep_dma_memcpy;
+ dd->device_prep_slave_sg = gdma_dma_prep_slave_sg;
+ dd->device_prep_dma_cyclic = gdma_dma_prep_dma_cyclic;
+ dd->device_config = gdma_dma_config;
+ dd->device_terminate_all = gdma_dma_terminate_all;
+ dd->device_tx_status = gdma_dma_tx_status;
+ dd->device_issue_pending = gdma_dma_issue_pending;
+
+ dd->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+ dd->dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
+ dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
+ dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
+
+ dd->dev = &pdev->dev;
+ dd->dev->dma_parms = &dma_dev->dma_parms;
+ dma_set_max_seg_size(dd->dev, GDMA_REG_CTRL0_TX_MASK);
+ INIT_LIST_HEAD(&dd->channels);
+
+ for (i = 0; i < data->chancnt; i++) {
+ chan = &dma_dev->chan[i];
+ chan->id = i;
+ chan->vchan.desc_free = gdma_dma_desc_free;
+ vchan_init(&chan->vchan, dd);
+ }
+
+ /* init hardware */
+ data->init(dma_dev);
+
+ ret = dma_async_device_register(dd);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register dma device\n");
+ return ret;
+ }
+
+ ret = of_dma_controller_register(pdev->dev.of_node,
+ of_dma_xlate_by_chan_id, dma_dev);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to register of dma controller\n");
+ goto err_unregister;
+ }
+
+ platform_set_drvdata(pdev, dma_dev);
+
+ return 0;
+
+err_unregister:
+ dma_async_device_unregister(dd);
+ return ret;
+}
+
+static int gdma_dma_remove(struct platform_device *pdev)
+{
+ struct gdma_dma_dev *dma_dev = platform_get_drvdata(pdev);
+
+ tasklet_kill(&dma_dev->task);
+ of_dma_controller_free(pdev->dev.of_node);
+ dma_async_device_unregister(&dma_dev->ddev);
+
+ return 0;
+}
+
+static struct platform_driver gdma_dma_driver = {
+ .probe = gdma_dma_probe,
+ .remove = gdma_dma_remove,
+ .driver = {
+ .name = "gdma-rt2880",
+ .of_match_table = gdma_of_match_table,
+ },
+};
+module_platform_driver(gdma_dma_driver);
+
+MODULE_DESCRIPTION("Ralink/MTK DMA driver");
+MODULE_LICENSE("GPL v2");
define Build/znet-header
$(eval version=$(word 1,$(1)))
+ $(eval magic=$(if $(word 2,$(1)),$(word 2,$(1)),ZNET))
+ $(eval hdrlen=$(if $(word 3,$(1)),$(word 3,$(1)),0x30))
( \
data_size_crc="$$(dd if=$@ 2>/dev/null | gzip -c | \
tail -c 8 | od -An -N4 -tx4 --endian big | tr -d ' \n')"; \
payload_len="$$(dd if=$@ bs=4 count=1 skip=1 2>/dev/null | od -An -tdI --endian big | tr -d ' \n')"; \
payload_size_crc="$$(dd if=$@ ibs=1 count=$$payload_len 2>/dev/null | gzip -c | \
tail -c 8 | od -An -N4 -tx4 --endian big | tr -d ' \n')"; \
- echo -ne "\x5A\x4E\x45\x54" | dd bs=4 count=1 conv=sync 2>/dev/null; \
+ echo -ne "$(magic)" | dd bs=4 count=1 conv=sync 2>/dev/null; \
echo -ne "$$(printf '%08x' $$(stat -c%s $@) | fold -s2 | xargs -I {} echo \\x{} | tac | tr -d '\n')" | \
dd bs=4 count=1 conv=sync 2>/dev/null; \
echo -ne "$$(echo $$data_size_crc | sed 's/../\\x&/g')" | \
dd bs=4 count=1 conv=sync 2>/dev/null; \
echo -ne "\x12\x34\x56\x78" | dd bs=4 count=1 conv=sync 2>/dev/null; \
echo -ne "$(version)" | dd bs=28 count=1 conv=sync 2>/dev/null; \
- dd if=/dev/zero bs=262096 count=1 conv=sync 2>/dev/null | tr "\000" "\377"; \
+ dd if=/dev/zero bs=$$((0x40000 - $(hdrlen))) count=1 conv=sync 2>/dev/null | tr "\000" "\377"; \
cat $@; \
) > $@.new
mv $@.new $@
endef
TARGET_DEVICES += dlink_dir-1960-a1
+define Device/dlink_dir-2055-a1
+ $(Device/dlink_dir_nand_128m)
+ DEVICE_PACKAGES += -kmod-usb-ledtrig-usbport
+ DEVICE_MODEL := DIR-2055
+ DEVICE_VARIANT := A1
+endef
+TARGET_DEVICES += dlink_dir-2055-a1
+
define Device/dlink_dir-2150-a1
$(Device/dlink_dir_nand_128m)
DEVICE_MODEL := DIR-2150
endef
TARGET_DEVICES += elecom_wrc-2533gst2
+define Device/elecom_wrc-x1800gs
+ $(Device/nand)
+ DEVICE_VENDOR := ELECOM
+ DEVICE_MODEL := WRC-X1800GS
+ KERNEL := kernel-bin | lzma | \
+ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb | \
+ znet-header 4.04(XVF.1)b90 COMC 0x68 | elecom-product-header WRC-X1800GS
+ KERNEL_INITRAMFS := kernel-bin | lzma | \
+ fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
+ KERNEL_SIZE := 8192k
+ IMAGE_SIZE := 51456k
+ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
+ ARTIFACTS := initramfs-factory.bin
+ ARTIFACT/initramfs-factory.bin := append-image-stage initramfs-kernel.bin | \
+ znet-header 4.04(XVF.1)b90 COMC 0x68 | elecom-product-header WRC-X1800GS | \
+ check-size
+endif
+ DEVICE_PACKAGES := kmod-mt7915-firmware
+endef
+TARGET_DEVICES += elecom_wrc-x1800gs
+
define Device/etisalat_s3
$(Device/sercomm_dxx)
IMAGE_SIZE := 32768k
endef
TARGET_DEVICES += tplink_archer-c50-v6
+define Device/tplink_archer-mr200-v5
+ $(Device/tplink-v2)
+ IMAGE_SIZE := 7872k
+ DEVICE_MODEL := Archer MR200
+ DEVICE_VARIANT := v5
+ TPLINK_FLASHLAYOUT := 8MLmtk
+ TPLINK_HWID := 0x20000005
+ TPLINK_HWREV := 0x5
+ TPLINK_HWREVADD := 0x5
+ DEVICE_PACKAGES := kmod-mt76x0e uqmi kmod-usb2 kmod-usb-serial-option
+ IMAGES := sysupgrade.bin tftp-recovery.bin
+ IMAGE/tftp-recovery.bin := pad-extra 128k | $$(IMAGE/factory.bin)
+endef
+TARGET_DEVICES += tplink_archer-mr200-v5
+
define Device/tplink_re200-v2
$(Device/tplink-safeloader)
IMAGE_SIZE := 7808k
define KernelPackage/dma-ralink
SUBMENU:=Other modules
TITLE:=Ralink GDMA Engine
- DEPENDS:=@TARGET_ramips
+ DEPENDS:=@TARGET_ramips @!TARGET_ramips_rt288x
KCONFIG:= \
CONFIG_DMADEVICES=y \
- CONFIG_DW_DMAC_PCI=n \
- CONFIG_DMA_RALINK
+ CONFIG_RALINK_GDMA
FILES:= \
$(LINUX_DIR)/drivers/dma/virt-dma.ko \
- $(LINUX_DIR)/drivers/staging/ralink-gdma/ralink-gdma.ko
+ $(LINUX_DIR)/drivers/dma/ralink-gdma.ko
AUTOLOAD:=$(call AutoLoad,52,ralink-gdma)
endef
define KernelPackage/dma-ralink/description
- Kernel modules for enable ralink dma engine.
+ Kernel modules for enable ralink gdma engine.
endef
$(eval $(call KernelPackage,dma-ralink))
DEPENDS:=@TARGET_ramips @TARGET_ramips_mt7621
KCONFIG:= \
CONFIG_DMADEVICES=y \
- CONFIG_DW_DMAC_PCI=n \
CONFIG_MTK_HSDMA
FILES:= \
$(LINUX_DIR)/drivers/dma/virt-dma.ko \
CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_RALINK=y
+# CONFIG_RALINK_GDMA is not set
CONFIG_RALINK_WDT=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
ucidef_set_led_rssi "rssihigh" "RSSIHIGH" "green:rssihigh" "wlan1" "76" "100"
;;
dlink,dir-1960-a1|\
+dlink,dir-2055-a1|\
dlink,dir-2150-a1|\
dlink,dir-2640-a1|\
dlink,dir-2660-a1)
asiarf,ap7621-nv1|\
beeline,smartbox-flash|\
beeline,smartbox-giga|\
+ elecom,wrc-x1800gs|\
glinet,gl-mt1300|\
iodata,wn-deax1800gr|\
iptime,a3002mesh|\
--- /dev/null
+set_netdev_labels() {
+ local dir
+ local label
+ local netdev
+
+ for dir in /sys/class/net/*; do
+ [ -r "$dir/of_node/label" ] || continue
+ read -r label < "$dir/of_node/label"
+ netdev="${dir##*/}"
+ [ "$netdev" = "$label" ] && continue
+ ip link set "$netdev" name "$label"
+ done
+}
+
+boot_hook_add preinit_main set_netdev_labels
dlink,covr-x1860-a1|\
dlink,dap-x1860-a1|\
dlink,dir-1960-a1|\
+ dlink,dir-2055-a1|\
dlink,dir-2150-a1|\
dlink,dir-2640-a1|\
dlink,dir-2660-a1|\
zyxel,nwa55axe)
nand_do_upgrade "$1"
;;
+ elecom,wrc-x1800gs)
+ [ "$(fw_printenv -n bootmenu_delay)" != "0" ] || \
+ fw_setenv bootmenu_delay 3
+ iodata_mstc_set_flag "bootnum" "persist" "0x4" "1,2" "1"
+ nand_do_upgrade "$1"
+ ;;
iodata,wn-ax1167gr2|\
iodata,wn-ax2033gr|\
iodata,wn-dx1167r|\
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RALINK=y
+# CONFIG_RALINK_GDMA is not set
# CONFIG_RALINK_WDT is not set
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
ucidef_set_led_wlan "wlan2g" "wlan2g" "green:wlan2g" "phy0tpt"
ucidef_set_led_wlan "wlan5g" "wlan5g" "green:wlan5g" "phy1tpt"
;;
+tplink,archer-mr200-v5)
+ ucidef_set_led_netdev "lan" "lan" "white:lan" "eth0"
+ ucidef_set_led_netdev "wan" "wan" "white:wan" "wwan0"
+ ;;
tplink,re200-v2|\
tplink,re200-v3|\
tplink,re200-v4|\
ucidef_add_switch "switch0" \
"0:wan" "1:lan" "2:lan" "3:lan" "4:lan" "6t@eth0"
;;
+ tplink,archer-mr200-v5)
+ ucidef_add_switch "switch0" \
+ "0:lan" "1:lan" "2:lan" "3:lan" "6t@eth0"
+ ucidef_set_interface "wan" device "/dev/cdc-wdm0" protocol "qmi"
+ ;;
tplink,tl-mr3020-v3)
ucidef_add_switch "switch0" \
"0:lan" "6@eth0"
CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_RALINK=y
+# CONFIG_RALINK_GDMA is not set
# CONFIG_RALINK_WDT is not set
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
+++ /dev/null
-From bd0f89de5476ca25e73fae829ba3e1dafae1d90d Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= <opensource@vdorst.com>
-Date: Fri, 21 Jun 2019 10:04:05 +0200
-Subject: [PATCH] net: ethernet: mediatek: support net-labels
-
-With this patch, device name can be set within dts file in the same way as dsa
-port can.
-Add: label = "wan"; to GMAC node.
-
-Signed-off-by: René van Dorst <opensource@vdorst.com>
----
- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
---- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4662,6 +4662,7 @@ static const struct net_device_ops mtk_n
-
- static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
- {
-+ const char *name = of_get_property(np, "label", NULL);
- const __be32 *_id = of_get_property(np, "reg", NULL);
- struct device_node *pcs_np;
- phy_interface_t phy_mode;
-@@ -4875,6 +4876,9 @@ static int mtk_add_mac(struct mtk_eth *e
- NETDEV_XDP_ACT_NDO_XMIT |
- NETDEV_XDP_ACT_NDO_XMIT_SG;
-
-+ if (name)
-+ strlcpy(eth->netdev[id]->name, name, IFNAMSIZ);
-+
- return 0;
-
- free_netdev:
--- /dev/null
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 27 Jul 2014 09:38:50 +0100
+Subject: [PATCH] NET: multi phy support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/phy/phy_device.c | 2 +-
+ include/linux/phy.h | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1075,7 +1075,7 @@ static void phy_link_change(struct phy_d
+
+ if (up)
+ netif_carrier_on(netdev);
+- else
++ else if (!phydev->no_auto_carrier_off)
+ netif_carrier_off(netdev);
+ phydev->adjust_link(netdev);
+ if (phydev->mii_ts && phydev->mii_ts->link_state)
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -659,6 +659,7 @@ struct phy_device {
+ unsigned downshifted_rate:1;
+ unsigned is_on_sfp_module:1;
+ unsigned mac_managed_pm:1;
++ unsigned no_auto_carrier_off:1;
+ unsigned wol_enabled:1;
+
+ unsigned autoneg:1;
+++ /dev/null
-From ffbb1b37a3e1ce1a5c574a6bd4f5aede8bc468ac Mon Sep 17 00:00:00 2001
-From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
-Date: Sat, 27 Feb 2021 20:20:07 -0800
-Subject: [PATCH] Revert "net: phy: simplify phy_link_change arguments"
-
-This reverts commit a307593a644443db12888f45eed0dafb5869e2cc.
-
-This brings back the do_carrier flags used by the (hacky) next patch,
-still required by target/linux/ramips/files/drivers/net/ethernet/ralink/mdio.c
----
- drivers/net/phy/phy.c | 12 ++++++------
- drivers/net/phy/phy_device.c | 12 +++++++-----
- drivers/net/phy/phylink.c | 3 ++-
- include/linux/phy.h | 2 +-
- 4 files changed, 16 insertions(+), 13 deletions(-)
-
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -72,13 +72,13 @@ static void phy_process_state_change(str
-
- static void phy_link_up(struct phy_device *phydev)
- {
-- phydev->phy_link_change(phydev, true);
-+ phydev->phy_link_change(phydev, true, true);
- phy_led_trigger_change_speed(phydev);
- }
-
--static void phy_link_down(struct phy_device *phydev)
-+static void phy_link_down(struct phy_device *phydev, bool do_carrier)
- {
-- phydev->phy_link_change(phydev, false);
-+ phydev->phy_link_change(phydev, false, do_carrier);
- phy_led_trigger_change_speed(phydev);
- WRITE_ONCE(phydev->link_down_events, phydev->link_down_events + 1);
- }
-@@ -823,7 +823,7 @@ int phy_start_cable_test(struct phy_devi
- goto out;
-
- /* Mark the carrier down until the test is complete */
-- phy_link_down(phydev);
-+ phy_link_down(phydev, true);
-
- netif_testing_on(dev);
- err = phydev->drv->cable_test_start(phydev);
-@@ -894,7 +894,7 @@ int phy_start_cable_test_tdr(struct phy_
- goto out;
-
- /* Mark the carrier down until the test is complete */
-- phy_link_down(phydev);
-+ phy_link_down(phydev, true);
-
- netif_testing_on(dev);
- err = phydev->drv->cable_test_tdr_start(phydev, config);
-@@ -966,7 +966,7 @@ static int phy_check_link_status(struct
- phy_link_up(phydev);
- } else if (!phydev->link && phydev->state != PHY_NOLINK) {
- phydev->state = PHY_NOLINK;
-- phy_link_down(phydev);
-+ phy_link_down(phydev, true);
- }
-
- return 0;
-@@ -1485,7 +1485,7 @@ void phy_state_machine(struct work_struc
- case PHY_ERROR:
- if (phydev->link) {
- phydev->link = 0;
-- phy_link_down(phydev);
-+ phy_link_down(phydev, true);
- }
- do_suspend = true;
- break;
---- a/drivers/net/phy/phy_device.c
-+++ b/drivers/net/phy/phy_device.c
-@@ -1069,14 +1069,16 @@ struct phy_device *phy_find_first(struct
- }
- EXPORT_SYMBOL(phy_find_first);
-
--static void phy_link_change(struct phy_device *phydev, bool up)
-+static void phy_link_change(struct phy_device *phydev, bool up, bool do_carrier)
- {
- struct net_device *netdev = phydev->attached_dev;
-
-- if (up)
-- netif_carrier_on(netdev);
-- else
-- netif_carrier_off(netdev);
-+ if (do_carrier) {
-+ if (up)
-+ netif_carrier_on(netdev);
-+ else
-+ netif_carrier_off(netdev);
-+ }
- phydev->adjust_link(netdev);
- if (phydev->mii_ts && phydev->mii_ts->link_state)
- phydev->mii_ts->link_state(phydev->mii_ts, phydev);
---- a/drivers/net/phy/phylink.c
-+++ b/drivers/net/phy/phylink.c
-@@ -1724,7 +1724,8 @@ bool phylink_expects_phy(struct phylink
- }
- EXPORT_SYMBOL_GPL(phylink_expects_phy);
-
--static void phylink_phy_change(struct phy_device *phydev, bool up)
-+static void phylink_phy_change(struct phy_device *phydev, bool up,
-+ bool do_carrier)
- {
- struct phylink *pl = phydev->phylink;
- bool tx_pause, rx_pause;
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -758,7 +758,7 @@ struct phy_device {
-
- unsigned int link_down_events;
-
-- void (*phy_link_change)(struct phy_device *phydev, bool up);
-+ void (*phy_link_change)(struct phy_device *, bool up, bool do_carrier);
- void (*adjust_link)(struct net_device *dev);
-
- #if IS_ENABLED(CONFIG_MACSEC)
+++ /dev/null
-From 0b6eb1e68290243d439ee330ea8d0b239a5aec69 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 27 Jul 2014 09:38:50 +0100
-Subject: [PATCH 34/53] NET: multi phy support
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/phy/phy.c | 9 ++++++---
- include/linux/phy.h | 1 +
- 2 files changed, 7 insertions(+), 3 deletions(-)
-
---- a/drivers/net/phy/phy.c
-+++ b/drivers/net/phy/phy.c
-@@ -966,7 +966,10 @@ static int phy_check_link_status(struct
- phy_link_up(phydev);
- } else if (!phydev->link && phydev->state != PHY_NOLINK) {
- phydev->state = PHY_NOLINK;
-- phy_link_down(phydev, true);
-+ if (!phydev->no_auto_carrier_off)
-+ phy_link_down(phydev, true);
-+ else
-+ phy_link_down(phydev, false);
- }
-
- return 0;
-@@ -1485,7 +1488,10 @@ void phy_state_machine(struct work_struc
- case PHY_ERROR:
- if (phydev->link) {
- phydev->link = 0;
-- phy_link_down(phydev, true);
-+ if (!phydev->no_auto_carrier_off)
-+ phy_link_down(phydev, true);
-+ else
-+ phy_link_down(phydev, false);
- }
- do_suspend = true;
- break;
---- a/include/linux/phy.h
-+++ b/include/linux/phy.h
-@@ -659,6 +659,7 @@ struct phy_device {
- unsigned downshifted_rate:1;
- unsigned is_on_sfp_module:1;
- unsigned mac_managed_pm:1;
-+ unsigned no_auto_carrier_off:1;
- unsigned wol_enabled:1;
-
- unsigned autoneg:1;
--- /dev/null
+From: Shiji Yang <yangshiji66@outlook.com>
+Date: Mon, 27 May 2024 08:25:57 +0000
+Subject: [PATCH] dma: ralink: add back gdma driver
+
+The upstream staging driver has been removed[1] since kernel v5.17.
+
+[1] 5bfc10690c6c ("staging: ralink-gdma: remove driver from tree")
+
+Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
+---
+ drivers/dma/Kconfig | 6 ++++++
+ drivers/dma/Makefile | 1 +
+ 2 files changed, 7 insertions(+)
+
+--- a/drivers/dma/Kconfig
++++ b/drivers/dma/Kconfig
+@@ -532,6 +532,12 @@ config PLX_DMA
+ These are exposed via extra functions on the switch's
+ upstream port. Each function exposes one DMA channel.
+
++config RALINK_GDMA
++ tristate "RALINK GDMA support"
++ depends on RALINK && !SOC_RT288X
++ select DMA_ENGINE
++ select DMA_VIRTUAL_CHANNELS
++
+ config STE_DMA40
+ bool "ST-Ericsson DMA40 support"
+ depends on ARCH_U8500
+--- a/drivers/dma/Makefile
++++ b/drivers/dma/Makefile
+@@ -64,6 +64,7 @@ obj-$(CONFIG_PL330_DMA) += pl330.o
+ obj-$(CONFIG_PLX_DMA) += plx_dma.o
+ obj-$(CONFIG_PPC_BESTCOMM) += bestcomm/
+ obj-$(CONFIG_PXA_DMA) += pxa_dma.o
++obj-$(CONFIG_RALINK_GDMA) += ralink-gdma.o
+ obj-$(CONFIG_RENESAS_DMA) += sh/
+ obj-$(CONFIG_SF_PDMA) += sf-pdma/
+ obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_RALINK=y
+# CONFIG_RALINK_GDMA is not set
# CONFIG_RALINK_ILL_ACC is not set
CONFIG_RALINK_WDT=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_RALINK=y
+# CONFIG_RALINK_GDMA is not set
CONFIG_RALINK_WDT=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
SUBTARGETS := generic
KERNEL_PATCHVER := 5.15
+KERNEL_TESTING_PATCHVER := 6.6
include $(INCLUDE_DIR)/target.mk
CONFIG_DNOTIFY=y
CONFIG_DRM=y
CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_DP_AUX_BUS=y
CONFIG_DRM_FBDEV_EMULATION=y
CONFIG_DRM_FBDEV_OVERALLOC=100
CONFIG_DRM_KMS_HELPER=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=0
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_ARCH_TOPOLOGY=y
CONFIG_NLS=y
CONFIG_NR_CPUS=4
CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_SND=y
# CONFIG_SND_COMPRESS_OFFLOAD is not set
CONFIG_SND_DMAENGINE_PCM=y
-# CONFIG_SND_DRIVERS is not set
# CONFIG_SND_HDA_TEGRA is not set
CONFIG_SND_JACK=y
CONFIG_SND_JACK_INPUT_DEV=y
--- /dev/null
+CONFIG_AC97_BUS=y
+# CONFIG_AHCI_TEGRA is not set
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_ARCH_32BIT_OFF_T=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_KEEP_MEMBLOCK=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
+CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_STACKWALK=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_TEGRA=y
+# CONFIG_ARCH_TEGRA_114_SOC is not set
+# CONFIG_ARCH_TEGRA_124_SOC is not set
+CONFIG_ARCH_TEGRA_2x_SOC=y
+# CONFIG_ARCH_TEGRA_3x_SOC is not set
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_HAS_GROUP_RELOCS=y
+CONFIG_ARM_HEAVY_MB=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_PL172_MPMC is not set
+# CONFIG_ARM_SMMU is not set
+# CONFIG_ARM_TEGRA124_CPUFREQ is not set
+CONFIG_ARM_TEGRA20_CPUFREQ=y
+CONFIG_ARM_TEGRA_CPUIDLE=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ASN1=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_BSG_COMMON=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLK_PM=y
+CONFIG_BOUNCE=y
+CONFIG_BUFFER_HEAD=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
+CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
+CONFIG_CC_NO_ARRAY_BOUNDS=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SYSFS is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_CONTEXT_TRACKING=y
+CONFIG_CONTEXT_TRACKING_IDLE=y
+CONFIG_CONTIG_ALLOC=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_STAT is not set
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_CPU_MITIGATIONS=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_SPECTRE=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AES_ARM=y
+CONFIG_CRYPTO_CRC32=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_GENIV=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
+CONFIG_CRYPTO_LIB_GF128MUL=y
+CONFIG_CRYPTO_LIB_SHA1=y
+CONFIG_CRYPTO_LIB_SHA256=y
+CONFIG_CRYPTO_LIB_UTILS=y
+CONFIG_CRYPTO_LZ4=y
+CONFIG_CRYPTO_LZ4HC=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SEQIV=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA512_ARM=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DDR=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+CONFIG_DEVFREQ_THERMAL=y
+# CONFIG_DEVPORT is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OPS=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DNOTIFY=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_DISPLAY_DP_HELPER=y
+CONFIG_DRM_DISPLAY_HDMI_HELPER=y
+CONFIG_DRM_DISPLAY_HELPER=y
+CONFIG_DRM_DP_AUX_BUS=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FBDEV_OVERALLOC=100
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_MIPI_DSI=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_BRIDGE=y
+CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
+CONFIG_DRM_TEGRA=y
+# CONFIG_DRM_TEGRA_DEBUG is not set
+# CONFIG_DRM_TEGRA_STAGING is not set
+CONFIG_DTC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EXCLUSIVE_SYSTEM_RAM=y
+CONFIG_EXT4_FS=y
+CONFIG_EXTCON=y
+CONFIG_F2FS_FS=y
+CONFIG_FB=y
+CONFIG_FB_CORE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DMAMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS=y
+CONFIG_FB_SYSMEM_HELPERS_DEFERRED=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FUNCTION_ALIGNMENT=0
+CONFIG_FW_LOADER_PAGED_BUF=y
+CONFIG_FW_LOADER_SYSFS=y
+CONFIG_GCC10_NO_ARRAY_BOUNDS=y
+CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ARCH_TOPOLOGY=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CPU_VULNERABILITIES=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_GETTIMEOFDAY=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_PINCTRL_GROUPS=y
+CONFIG_GENERIC_PINMUX_FUNCTIONS=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_VDSO_32=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_CDEV=y
+CONFIG_GPIO_TEGRA=y
+CONFIG_HARDEN_BRANCH_PREDICTOR=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_IOPORT_MAP=y
+CONFIG_HAVE_SMP=y
+CONFIG_HDMI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HOTPLUG_CORE_SYNC=y
+CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
+CONFIG_HOTPLUG_CPU=y
+CONFIG_HWMON=y
+CONFIG_HZ_FIXED=0
+CONFIG_HZ_PERIODIC=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_TEGRA=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_VIVALDIFMAP=y
+CONFIG_INTERCONNECT=y
+# CONFIG_IOMMUFD is not set
+CONFIG_IOMMU_API=y
+# CONFIG_IOMMU_DEBUGFS is not set
+# CONFIG_IOMMU_DEFAULT_DMA_LAZY is not set
+CONFIG_IOMMU_DEFAULT_DMA_STRICT=y
+# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
+CONFIG_IOMMU_IOVA=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IRQCHIP=y
+CONFIG_IRQSTACKS=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+CONFIG_JBD2=y
+CONFIG_KCMP=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KMAP_LOCAL=y
+CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
+CONFIG_LIBFDT=y
+CONFIG_LOCK_DEBUGGING_SUPPORT=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LZ4HC_COMPRESS=y
+CONFIG_LZ4_COMPRESS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_MEDIA_CONTROLLER_REQUEST_API=y
+CONFIG_MEDIA_PLATFORM_DRIVERS=y
+CONFIG_MEDIA_PLATFORM_SUPPORT=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_SUPPORT_FILTER=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+# CONFIG_MFD_ACER_A500_EC is not set
+# CONFIG_MFD_NVEC is not set
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_CQHCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_MMU_LAZY_TLB_REFCOUNT=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_MPILIB=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_SRCU_NMI_SAFE=y
+# CONFIG_NEON is not set
+CONFIG_NET_EGRESS=y
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_XGRESS=y
+CONFIG_NLS=y
+CONFIG_NR_CPUS=4
+CONFIG_NVMEM=y
+CONFIG_NVMEM_LAYOUTS=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_KOBJ=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PADATA=y
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PAGE_POOL=y
+CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
+CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
+CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_TEGRA=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=2
+CONFIG_PHY_TEGRA_XUSB=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_TEGRA=y
+CONFIG_PINCTRL_TEGRA20=y
+CONFIG_PINCTRL_TEGRA_XUSB=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PL353_SMC=y
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_GENERIC_DOMAINS=y
+CONFIG_PM_GENERIC_DOMAINS_OF=y
+CONFIG_PM_OPP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PREEMPT_NONE_BUILD=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PTP_1588_CLOCK_OPTIONAL=y
+CONFIG_PWM=y
+CONFIG_PWM_SYSFS=y
+CONFIG_PWM_TEGRA=y
+CONFIG_RANDSTRUCT_NONE=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_TEGRA=y
+CONFIG_RTC_I2C_AND_SPI=y
+CONFIG_RTC_NVMEM=y
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_SCSI=y
+CONFIG_SCSI_COMMON=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_TEGRA=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_TEGRA=y
+CONFIG_SERIO=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SGL_ALLOC=y
+CONFIG_SG_POOL=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SND=y
+CONFIG_SND_AUDIO_GRAPH_CARD=y
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+CONFIG_SND_DMAENGINE_PCM=y
+# CONFIG_SND_HDA_TEGRA is not set
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+# CONFIG_SND_PCI is not set
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_ELD=y
+CONFIG_SND_PCM_IEC958=y
+# CONFIG_SND_PROC_FS is not set
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SIMPLE_CARD_UTILS=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_HDMI_CODEC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_TEGRA=y
+# CONFIG_SND_SOC_TEGRA186_ASRC is not set
+# CONFIG_SND_SOC_TEGRA186_DSPK is not set
+CONFIG_SND_SOC_TEGRA20_AC97=y
+CONFIG_SND_SOC_TEGRA20_DAS=y
+CONFIG_SND_SOC_TEGRA20_I2S=y
+CONFIG_SND_SOC_TEGRA20_SPDIF=y
+# CONFIG_SND_SOC_TEGRA210_ADMAIF is not set
+# CONFIG_SND_SOC_TEGRA210_ADX is not set
+# CONFIG_SND_SOC_TEGRA210_AHUB is not set
+# CONFIG_SND_SOC_TEGRA210_AMX is not set
+# CONFIG_SND_SOC_TEGRA210_DMIC is not set
+# CONFIG_SND_SOC_TEGRA210_I2S is not set
+# CONFIG_SND_SOC_TEGRA210_MIXER is not set
+# CONFIG_SND_SOC_TEGRA210_MVC is not set
+# CONFIG_SND_SOC_TEGRA210_OPE is not set
+# CONFIG_SND_SOC_TEGRA210_SFC is not set
+# CONFIG_SND_SOC_TEGRA30_AHUB is not set
+# CONFIG_SND_SOC_TEGRA30_I2S is not set
+# CONFIG_SND_SOC_TEGRA_ALC5632 is not set
+# CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD is not set
+CONFIG_SND_SOC_TEGRA_MACHINE_DRV=y
+# CONFIG_SND_SOC_TEGRA_MAX98088 is not set
+# CONFIG_SND_SOC_TEGRA_MAX98090 is not set
+# CONFIG_SND_SOC_TEGRA_RT5631 is not set
+# CONFIG_SND_SOC_TEGRA_RT5640 is not set
+# CONFIG_SND_SOC_TEGRA_RT5677 is not set
+# CONFIG_SND_SOC_TEGRA_SGTL5000 is not set
+CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
+# CONFIG_SND_SOC_TEGRA_WM8753 is not set
+# CONFIG_SND_SOC_TEGRA_WM8903 is not set
+# CONFIG_SND_SOC_TEGRA_WM9712 is not set
+CONFIG_SND_SOC_TLV320AIC23=y
+CONFIG_SND_SOC_TLV320AIC23_I2C=y
+# CONFIG_SND_USB is not set
+CONFIG_SOCK_RX_QUEUE_MAPPING=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_TEGRA20_VOLTAGE_COUPLER=y
+CONFIG_SOC_TEGRA_FLOWCTRL=y
+CONFIG_SOC_TEGRA_FUSE=y
+CONFIG_SOC_TEGRA_PMC=y
+CONFIG_SOFTIRQ_ON_OWN_STACK=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_MEM=y
+# CONFIG_SPI_TEGRA114 is not set
+CONFIG_SPI_TEGRA20_SFLASH=y
+CONFIG_SPI_TEGRA20_SLINK=y
+# CONFIG_SPI_TEGRA210_QUAD is not set
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SRAM=y
+CONFIG_SRAM_EXEC=y
+CONFIG_SWP_EMULATE=y
+CONFIG_SYNC_FILE=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+# CONFIG_TEGRA186_TIMER is not set
+CONFIG_TEGRA20_APB_DMA=y
+CONFIG_TEGRA20_EMC=y
+# CONFIG_TEGRA210_ADMA is not set
+# CONFIG_TEGRA_ACONNECT is not set
+CONFIG_TEGRA_AHB=y
+CONFIG_TEGRA_GMI=y
+CONFIG_TEGRA_HOST1X=y
+CONFIG_TEGRA_HOST1X_CONTEXT_BUS=y
+CONFIG_TEGRA_HOST1X_FIREWALL=y
+CONFIG_TEGRA_IOMMU_GART=y
+# CONFIG_TEGRA_IOMMU_SMMU is not set
+# CONFIG_TEGRA_IVC is not set
+CONFIG_TEGRA_MC=y
+CONFIG_TEGRA_SOCTHERM=y
+CONFIG_TEGRA_TIMER=y
+CONFIG_TEGRA_WATCHDOG=y
+CONFIG_THREAD_INFO_IN_TASK=y
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TIMER_OF=y
+CONFIG_TIMER_PROBE=y
+CONFIG_TREE_RCU=y
+CONFIG_TREE_SRCU=y
+# CONFIG_UCLAMP_TASK is not set
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNWINDER_ARM=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_TEGRA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_CONN_GPIO=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_PHY=y
+CONFIG_USB_ROLE_SWITCH=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_TEGRA_PHY=y
+# CONFIG_USB_TEGRA_XUDC is not set
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_BUS=y
+CONFIG_USB_ULPI_VIEWPORT=y
+# CONFIG_USB_XHCI_TEGRA is not set
+CONFIG_USE_OF=y
+CONFIG_V4L2_H264=y
+CONFIG_V4L2_MEM2MEM_DEV=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VIDEOBUF2_CORE=y
+CONFIG_VIDEOBUF2_DMA_CONTIG=y
+CONFIG_VIDEOBUF2_DMA_SG=y
+CONFIG_VIDEOBUF2_MEMOPS=y
+CONFIG_VIDEOBUF2_V4L2=y
+CONFIG_VIDEO_CMDLINE=y
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_NOMODESET=y
+CONFIG_VIDEO_TEGRA_VDE=y
+CONFIG_VIDEO_V4L2_I2C=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
mkdir -p $@.boot
$(CP) $(KDIR)/$(KERNEL_NAME) $@.boot
$(if $(DEVICE_DTS),\
- $(foreach dtb,$(DEVICE_DTS),$(CP) $(DTS_DIR)/$(dtb).dtb $@.boot), \
- $(CP) $(DTS_DIR)/*.dtb $@.boot)
+ $(foreach dtb,$(DEVICE_DTS),$(CP) $(DEVICE_DTS_DIR)/$(dtb).dtb $@.boot), \
+ $(CP) $(DEVICE_DTS_DIR)/*.dtb $@.boot)
mkimage -A arm -O linux -T script -C none -a 0 -e 0 \
-n '$(DEVICE_TITLE) OpenWrt bootscript' \
-d $(BOOT_SCRIPT) \
$@.boot/boot.scr
+ $(CP) $@ $@.rootfs
SIGNATURE="$(IMG_PART_SIGNATURE)" \
$(SCRIPT_DIR)/gen_image_generic.sh \
$@ \
$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
- $(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
+ $(CONFIG_TARGET_ROOTFS_PARTSIZE) $@.rootfs \
2048
$(if $(UBOOT),dd if=$(STAGING_DIR_IMAGE)/$(UBOOT).img of=$@ bs=512 skip=1 seek=1 conv=notrunc)
define Device/Default
BOOT_SCRIPT := generic-bootscript
+ifeq ($(KERNEL),6.6)
+ DEVICE_DTS_DIR := $$(DTS_DIR)/nvidia
+else
+ DEVICE_DTS_DIR := $$(DTS_DIR)
+endif
IMAGES := sdcard.img.gz
- IMAGE/sdcard.img.gz := tegra-sdcard | gzip | append-metadata
+ IMAGE/sdcard.img.gz := append-rootfs | pad-extra 128k | tegra-sdcard | gzip | append-metadata
KERNEL_NAME := zImage
KERNEL := kernel-bin
PROFILES := Default
DEVICE_VENDOR := CompuLab
DEVICE_MODEL := TrimSlice
DEVICE_DTS := tegra20-trimslice
- DEVICE_PACKAGES := kmod-r8169 kmod-rt2800-usb kmod-rtc-em3027 \
- kmod-usb-storage wpad-basic-mbedtls
+ DEVICE_PACKAGES := kmod-leds-gpio kmod-r8169 kmod-rt2800-usb \
+ kmod-rtc-em3027 kmod-usb-hid kmod-usb-storage wpad-basic-mbedtls
UBOOT := trimslice-mmc
endef
TARGET_DEVICES += compulab_trimslice
part uuid ${devtype} ${devnum}:2 ptuuid
-setenv bootargs "root=PARTUUID=${ptuuid} rw rootwait console=ttyS0,115200 console=tty0"
+setenv bootargs "root=PARTUUID=${ptuuid} rw rootwait"
load ${devtype} ${devnum}:${bootpart} ${kernel_addr_r} zImage
load ${devtype} ${devnum}:${bootpart} ${fdt_addr_r} ${soc}-${board}.dtb
--- /dev/null
+--- a/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts
++++ b/arch/arm/boot/dts/nvidia/tegra20-trimslice.dts
+@@ -201,16 +201,17 @@
+ conf_ata {
+ nvidia,pins = "ata", "atc", "atd", "ate",
+ "crtp", "dap2", "dap3", "dap4", "dta",
+- "dtb", "dtc", "dtd", "dte", "gmb",
+- "gme", "i2cp", "pta", "slxc", "slxd",
+- "spdi", "spdo", "uda";
++ "dtb", "dtc", "dtd", "gmb", "gme",
++ "i2cp", "pta", "slxc", "slxd", "spdi",
++ "spdo", "uda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ };
+ conf_atb {
+ nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
+- "gma", "gmc", "gmd", "gpu", "gpu7",
+- "gpv", "sdio1", "slxa", "slxk", "uac";
++ "dte", "gma", "gmc", "gmd", "gpu",
++ "gpu7", "gpv", "sdio1", "slxa", "slxk",
++ "uac";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+@@ -408,6 +409,20 @@
+ };
+ };
+
++ gpio-leds {
++ compatible = "gpio-leds";
++
++ ds2 {
++ label = "trimslice:green:right";
++ gpios = <&gpio TEGRA_GPIO(D, 2) GPIO_ACTIVE_LOW>;
++ };
++
++ ds3 {
++ label = "trimslice:green:left";
++ gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_LOW>;
++ };
++ };
++
+ poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
+++ /dev/null
-CONFIG_64BIT=y
-# CONFIG_ACER_WMI is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_AC=y
-CONFIG_ACPI_BATTERY=y
-# CONFIG_ACPI_BGRT is not set
-CONFIG_ACPI_BUTTON=y
-# CONFIG_ACPI_CMPC is not set
-CONFIG_ACPI_CONTAINER=y
-CONFIG_ACPI_CPPC_LIB=y
-CONFIG_ACPI_CPU_FREQ_PSS=y
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_DEBUGGER is not set
-# CONFIG_ACPI_DOCK is not set
-# CONFIG_ACPI_DPTF is not set
-# CONFIG_ACPI_EC_DEBUGFS is not set
-CONFIG_ACPI_FAN=y
-# CONFIG_ACPI_FPDT is not set
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_HOTPLUG_IOAPIC=y
-# CONFIG_ACPI_I2C_OPREGION is not set
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-CONFIG_ACPI_LPIT=y
-CONFIG_ACPI_PCC=y
-# CONFIG_ACPI_PCI_SLOT is not set
-# CONFIG_ACPI_PFRUT is not set
-CONFIG_ACPI_PRMT=y
-CONFIG_ACPI_PROCESSOR=y
-# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
-CONFIG_ACPI_PROCESSOR_CSTATE=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_SBS is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-# CONFIG_ACPI_TAD is not set
-CONFIG_ACPI_THERMAL=y
-# CONFIG_ACPI_TOSHIBA is not set
-CONFIG_ACPI_VIDEO=y
-# CONFIG_ACPI_WMI is not set
-# CONFIG_ACRN_GUEST is not set
-# CONFIG_ADV_SWBUTTON is not set
-CONFIG_AGP=y
-# CONFIG_AGP_AMD64 is not set
-CONFIG_AGP_INTEL=y
-# CONFIG_AGP_SIS is not set
-# CONFIG_AGP_VIA is not set
-# CONFIG_AMD_HSMP is not set
-CONFIG_AMD_IOMMU=y
-CONFIG_AMD_IOMMU_V2=y
-# CONFIG_AMD_PMC is not set
-# CONFIG_AMD_PMF is not set
-# CONFIG_AMD_PTDMA is not set
-# CONFIG_AMD_SFH_HID is not set
-CONFIG_ARCH_CPUIDLE_HALTPOLL=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-CONFIG_ARCH_MMAP_RND_BITS=28
-CONFIG_ARCH_MMAP_RND_BITS_MAX=32
-CONFIG_ARCH_MMAP_RND_BITS_MIN=28
-CONFIG_ARCH_NR_GPIO=1024
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_ARCH_WANTS_THP_SWAP=y
-# CONFIG_ASUS_TF103C_DOCK is not set
-# CONFIG_ASUS_WMI is not set
-CONFIG_AUDIT_ARCH=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_BLK_DEV_BSGLIB=y
-CONFIG_BLK_DEV_BSG_COMMON=y
-CONFIG_BLK_DEV_INTEGRITY=y
-CONFIG_BLK_DEV_INTEGRITY_T10=y
-CONFIG_BLK_DEV_NVME=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_PM=y
-# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
-CONFIG_BTT=y
-CONFIG_CDROM=y
-CONFIG_CONNECTOR=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-CONFIG_CPU_IBPB_ENTRY=y
-CONFIG_CPU_IBRS_ENTRY=y
-# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
-CONFIG_CPU_RMAP=y
-CONFIG_CPU_SRSO=y
-CONFIG_CPU_UNRET_ENTRY=y
-CONFIG_CRC_T10DIF=y
-CONFIG_CRYPTO_AES_NI_INTEL=y
-# CONFIG_CRYPTO_ARIA_AESNI_AVX_X86_64 is not set
-CONFIG_CRYPTO_BLAKE2S_X86=y
-# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set
-# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set
-# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set
-# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set
-# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set
-# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set
-CONFIG_CRYPTO_CRCT10DIF=y
-# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set
-CONFIG_CRYPTO_CRYPTD=y
-# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
-CONFIG_CRYPTO_LRW=y
-# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set
-# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set
-# CONFIG_CRYPTO_POLYVAL_CLMUL_NI is not set
-# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set
-# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set
-# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set
-# CONFIG_CRYPTO_SHA1_SSSE3 is not set
-# CONFIG_CRYPTO_SHA256_SSSE3 is not set
-# CONFIG_CRYPTO_SHA512_SSSE3 is not set
-CONFIG_CRYPTO_SIMD=y
-# CONFIG_CRYPTO_SM3_AVX_X86_64 is not set
-# CONFIG_CRYPTO_SM4_AESNI_AVX_X86_64 is not set
-# CONFIG_CRYPTO_SM4_AESNI_AVX2_X86_64 is not set
-# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set
-# CONFIG_CRYPTO_TWOFISH_X86_64 is not set
-# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set
-CONFIG_CRYPTO_XTS=y
-# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
-CONFIG_DMA_ACPI=y
-CONFIG_DMA_OPS=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DRM=y
-CONFIG_DRM_BOCHS=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-# CONFIG_DRM_HYPERV is not set
-CONFIG_DRM_I915=y
-CONFIG_DRM_I915_CAPTURE_ERROR=y
-CONFIG_DRM_I915_COMPRESS_ERROR=y
-# CONFIG_DRM_I915_DEBUG is not set
-# CONFIG_DRM_I915_DEBUG_GUC is not set
-# CONFIG_DRM_I915_DEBUG_MMIO is not set
-# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
-# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
-CONFIG_DRM_I915_FENCE_TIMEOUT=10000
-CONFIG_DRM_I915_FORCE_PROBE=""
-CONFIG_DRM_I915_GVT=y
-CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
-# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
-CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
-CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
-CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
-# CONFIG_DRM_I915_SELFTEST is not set
-CONFIG_DRM_I915_STOP_TIMEOUT=100
-# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
-# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
-CONFIG_DRM_I915_TIMESLICE_DURATION=1
-CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
-CONFIG_DRM_I915_USERPTR=y
-# CONFIG_DRM_I915_WERROR is not set
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_TTM=y
-CONFIG_DRM_TTM_HELPER=y
-CONFIG_DRM_VIRTIO_GPU=y
-CONFIG_DRM_VRAM_HELPER=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=m
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_COCO_SECRET is not set
-# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-# CONFIG_EFI_FAKE_MEMMAP is not set
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-# CONFIG_EFI_MIXED is not set
-# CONFIG_EFI_PGT_DUMP is not set
-# CONFIG_EFI_RCI2_TABLE is not set
-CONFIG_EFI_RUNTIME_MAP=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-# CONFIG_EFI_SECRET is not set
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-# CONFIG_EFI_VARS is not set
-CONFIG_FAILOVER=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_EFI=y
-CONFIG_FB_HYPERV=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-CONFIG_FB_TILEBLITTING=y
-# CONFIG_FB_VESA is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FREEZER=y
-CONFIG_FUSION_SAS=y
-CONFIG_FW_CACHE=y
-CONFIG_GART_IOMMU=y
-CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
-CONFIG_GENERIC_CPU=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_PENDING_IRQ=y
-# CONFIG_GIGABYTE_WMI is not set
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_ICH=y
-CONFIG_GPIO_SCH=y
-CONFIG_HALTPOLL_CPUIDLE=y
-CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y
-CONFIG_HDMI=y
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HID_GENERIC=y
-CONFIG_HID_HYPERV_MOUSE=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_PCIE is not set
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-CONFIG_HOTPLUG_SMT=y
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-# CONFIG_HP_ACCEL is not set
-# CONFIG_HUAWEI_WMI is not set
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_IRQ=y
-CONFIG_HVC_XEN=y
-CONFIG_HVC_XEN_FRONTEND=y
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=y
-CONFIG_HW_RANDOM_AMD=y
-CONFIG_HW_RANDOM_INTEL=y
-CONFIG_HW_RANDOM_VIRTIO=y
-CONFIG_HYPERV=y
-CONFIG_HYPERVISOR_GUEST=y
-CONFIG_HYPERV_BALLOON=y
-CONFIG_HYPERV_IOMMU=y
-CONFIG_HYPERV_KEYBOARD=y
-CONFIG_HYPERV_NET=y
-CONFIG_HYPERV_STORAGE=y
-# CONFIG_HYPERV_TESTING is not set
-CONFIG_HYPERV_TIMER=y
-CONFIG_HYPERV_UTILS=y
-# CONFIG_HYPERV_VSOCKETS is not set
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_HID_ACPI is not set
-# CONFIG_I2C_MULTI_INSTANTIATE is not set
-# CONFIG_I8K is not set
-# CONFIG_IA32_EMULATION is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
-CONFIG_INTEL_GTT=y
-CONFIG_INTEL_IDLE=y
-# CONFIG_INTEL_IDXD is not set
-# CONFIG_INTEL_IDXD_COMPAT is not set
-CONFIG_INTEL_IOMMU=y
-# CONFIG_INTEL_IOMMU_DEFAULT_ON is not set
-CONFIG_INTEL_IOMMU_FLOPPY_WA=y
-CONFIG_INTEL_IOMMU_PERF_EVENTS=y
-# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set
-# CONFIG_INTEL_IOMMU_SVM is not set
-# CONFIG_INTEL_IPS is not set
-# CONFIG_INTEL_MEI_HDCP is not set
-# CONFIG_INTEL_MEI_PXP is not set
-# CONFIG_INTEL_MENLOW is not set
-CONFIG_INTEL_PCH_THERMAL=y
-# CONFIG_INTEL_SAR_INT1092 is not set
-# CONFIG_INTEL_SCU_PLATFORM is not set
-CONFIG_INTEL_SOC_DTS_IOSF_CORE=y
-CONFIG_INTEL_SOC_DTS_THERMAL=y
-# CONFIG_INTEL_SPEED_SELECT_INTERFACE is not set
-CONFIG_INTEL_TDX_GUEST=y
-# CONFIG_INTEL_TURBO_MAX_3 is not set
-# CONFIG_INTEL_TXT is not set
-# CONFIG_INTEL_UNCORE_FREQ_CONTROL is not set
-# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
-# CONFIG_INTEL_WMI_THUNDERBOLT is not set
-CONFIG_INTERVAL_TREE=y
-CONFIG_IOASID=y
-CONFIG_IOMMU_API=y
-# CONFIG_IOMMU_DEBUG is not set
-# CONFIG_IOMMU_DEBUGFS is not set
-CONFIG_IOMMU_DEFAULT_DMA_LAZY=y
-# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set
-# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set
-CONFIG_IOMMU_DMA=y
-CONFIG_IOMMU_HELPER=y
-CONFIG_IOMMU_IOVA=y
-CONFIG_IOMMU_SUPPORT=y
-CONFIG_IOSF_MBI=y
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_IRQ_MSI_IOMMU=y
-CONFIG_IRQ_REMAP=y
-# CONFIG_ISCSI_IBFT is not set
-CONFIG_ISO9660_FS=y
-CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y
-CONFIG_KCMP=y
-CONFIG_KVM_GUEST=y
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEGACY_VSYSCALL_EMULATE is not set
-CONFIG_LEGACY_VSYSCALL_NONE=y
-# CONFIG_LEGACY_VSYSCALL_XONLY is not set
-# CONFIG_LG_LAPTOP is not set
-CONFIG_LIBNVDIMM=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-CONFIG_LPC_ICH=y
-CONFIG_LPC_SCH=y
-CONFIG_MAILBOX=y
-# CONFIG_MAXSMP is not set
-CONFIG_MEMORY_BALLOON=y
-CONFIG_MEMREGION=y
-# CONFIG_MERAKI_MX100 is not set
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_INTEL_LPSS_ACPI is not set
-# CONFIG_MFD_INTEL_PMC_BXT is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_ACPI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=y
-# CONFIG_MMC_SDHCI_PLTFM is not set
-# CONFIG_MMC_WBSD is not set
-CONFIG_MMU_NOTIFIER=y
-CONFIG_MODULES_USE_ELF_RELA=y
-# CONFIG_MPSC is not set
-# CONFIG_MSI_WMI is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-# CONFIG_MXM_WMI is not set
-CONFIG_ND_BLK=y
-CONFIG_ND_BTT=y
-CONFIG_ND_CLAIM=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-# CONFIG_NITRO_ENCLAVES is not set
-CONFIG_NR_CPUS=512
-CONFIG_NR_CPUS_DEFAULT=64
-CONFIG_NR_CPUS_RANGE_BEGIN=2
-CONFIG_NR_CPUS_RANGE_END=512
-# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
-CONFIG_NVME_CORE=y
-CONFIG_NVME_HWMON=y
-CONFIG_NVME_MULTIPATH=y
-CONFIG_OUTPUT_FORMAT="elf64-x86-64"
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_PAGE_TABLE_ISOLATION=y
-CONFIG_PARAVIRT=y
-CONFIG_PARAVIRT_CLOCK=y
-# CONFIG_PARAVIRT_DEBUG is not set
-CONFIG_PARAVIRT_SPINLOCKS=y
-CONFIG_PARAVIRT_XXL=y
-CONFIG_PATA_AMD=y
-CONFIG_PATA_ATIIXP=y
-CONFIG_PATA_MPIIX=y
-CONFIG_PATA_OLDPIIX=y
-CONFIG_PATA_PLATFORM=y
-CONFIG_PATA_TIMINGS=y
-CONFIG_PATA_VIA=y
-CONFIG_PCC=y
-# CONFIG_PCENGINES_APU2 is not set
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_HYPERV=y
-CONFIG_PCI_HYPERV_INTERFACE=y
-# CONFIG_PCI_MMCONFIG is not set
-CONFIG_PCI_XEN=y
-# CONFIG_PEAQ_WMI is not set
-CONFIG_PGTABLE_LEVELS=4
-CONFIG_PHYSICAL_ALIGN=0x1000000
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ALDERLAKE=y
-CONFIG_PINCTRL_BAYTRAIL=y
-CONFIG_PINCTRL_BROXTON=y
-CONFIG_PINCTRL_CANNONLAKE=y
-CONFIG_PINCTRL_CHERRYVIEW=y
-CONFIG_PINCTRL_DENVERTON=y
-CONFIG_PINCTRL_ELKHARTLAKE=y
-CONFIG_PINCTRL_EMMITSBURG=y
-CONFIG_PINCTRL_GEMINILAKE=y
-CONFIG_PINCTRL_INTEL=y
-CONFIG_PINCTRL_JASPERLAKE=y
-CONFIG_PINCTRL_LAKEFIELD=y
-CONFIG_PINCTRL_LEWISBURG=y
-CONFIG_PINCTRL_LYNXPOINT=y
-CONFIG_PINCTRL_METEORLAKE=y
-CONFIG_PINCTRL_SUNRISEPOINT=y
-CONFIG_PINCTRL_TIGERLAKE=y
-CONFIG_PM=y
-# CONFIG_PMIC_OPREGION is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PNP=y
-CONFIG_PNPACPI=y
-CONFIG_PNP_DEBUG_MESSAGES=y
-CONFIG_PPS=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_KVM=y
-CONFIG_PTP_1588_CLOCK_VMW=y
-CONFIG_PVH=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-CONFIG_RELAY=y
-CONFIG_RELOCATABLE=y
-CONFIG_RESET_ATTACK_MITIGATION=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SAMSUNG_Q10 is not set
-CONFIG_SATA_AHCI=y
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_MC=y
-CONFIG_SCHED_MC_PRIO=y
-CONFIG_SCHED_SMT=y
-CONFIG_SCSI_SAS_ATTRS=y
-CONFIG_SCSI_VIRTIO=y
-# CONFIG_SENSORS_ASUS_EC is not set
-# CONFIG_SENSORS_ASUS_WMI is not set
-CONFIG_SENSORS_CORETEMP=y
-CONFIG_SENSORS_FAM15H_POWER=y
-CONFIG_SENSORS_I5500=y
-CONFIG_SENSORS_K8TEMP=y
-CONFIG_SENSORS_K10TEMP=y
-CONFIG_SENSORS_VIA_CPUTEMP=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
-CONFIG_SLS=y
-CONFIG_SMP=y
-# CONFIG_SND_HDA_CTL_DEV_ID is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
-# CONFIG_SND_SOC_AMD_ACP6x is not set
-# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
-# CONFIG_SND_SOC_AMD_PS is not set
-# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
-# CONFIG_SND_SOC_INTEL_AVS is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-CONFIG_SPARSEMEM=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPARSEMEM_MANUAL=y
-# CONFIG_SPARSEMEM_VMEMMAP is not set
-CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
-CONFIG_STACK_VALIDATION=y
-# CONFIG_SURFACE_PLATFORMS is not set
-CONFIG_SWIOTLB=y
-CONFIG_SWIOTLB_XEN=y
-CONFIG_SYNC_FILE=y
-# CONFIG_SYSTEM76_ACPI is not set
-CONFIG_SYS_HYPERVISOR=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-# CONFIG_THINKPAD_LMI is not set
-# CONFIG_TOSHIBA_BT_RFKILL is not set
-# CONFIG_TOSHIBA_WMI is not set
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UACCE is not set
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UCS2_STRING=y
-# CONFIG_UNWINDER_ORC is not set
-CONFIG_USB_STORAGE=y
-# CONFIG_VIDEO_IPU3_CIO2 is not set
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
-CONFIG_VIRTIO_IOMMU=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_PCI_LIB=y
-# CONFIG_VIRTIO_PMEM is not set
-# CONFIG_VIRTIO_VSOCKETS is not set
-CONFIG_VIRTIO_VSOCKETS_COMMON=y
-CONFIG_VIRT_DRIVERS=y
-CONFIG_VMAP_PFN=y
-CONFIG_VMAP_STACK=y
-# CONFIG_VMD is not set
-CONFIG_VMGENID=y
-CONFIG_VMWARE_BALLOON=y
-CONFIG_VMWARE_PVSCSI=y
-CONFIG_VMWARE_VMCI=y
-CONFIG_VMWARE_VMCI_VSOCKETS=y
-CONFIG_VMXNET3=y
-CONFIG_VSOCKETS=y
-CONFIG_VSOCKETS_LOOPBACK=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WIRELESS_HOTKEY is not set
-# CONFIG_WMI_BMOF is not set
-# CONFIG_X86_5LEVEL is not set
-CONFIG_X86_64=y
-CONFIG_X86_64_SMP=y
-CONFIG_X86_ACPI_CPUFREQ=y
-# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
-CONFIG_X86_AMD_FREQ_SENSITIVITY=y
-CONFIG_X86_AMD_PLATFORM_DEVICE=y
-CONFIG_X86_AMD_PSTATE=y
-# CONFIG_X86_AMD_PSTATE_UT is not set
-CONFIG_X86_CPUID=y
-CONFIG_X86_DIRECT_GBPAGES=y
-CONFIG_X86_HV_CALLBACK_VECTOR=y
-CONFIG_X86_INTEL_LPSS=y
-# CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set
-CONFIG_X86_INTEL_PSTATE=y
-# CONFIG_X86_KERNEL_IBT is not set
-CONFIG_X86_MINIMUM_CPU_FAMILY=64
-# CONFIG_X86_PCC_CPUFREQ is not set
-CONFIG_X86_PKG_TEMP_THERMAL=y
-# CONFIG_X86_PMEM_LEGACY is not set
-CONFIG_X86_PM_TIMER=y
-# CONFIG_X86_POWERNOW_K8 is not set
-# CONFIG_X86_VSYSCALL_EMULATION is not set
-CONFIG_X86_X2APIC=y
-# CONFIG_X86_X32 is not set
-# CONFIG_X86_X32_ABI is not set
-CONFIG_XEN=y
-CONFIG_XENFS=y
-CONFIG_XEN_512GB=y
-CONFIG_XEN_ACPI=y
-CONFIG_XEN_ACPI_PROCESSOR=y
-CONFIG_XEN_AUTO_XLATE=y
-# CONFIG_XEN_BACKEND is not set
-CONFIG_XEN_BALLOON=y
-CONFIG_XEN_BLKDEV_FRONTEND=y
-CONFIG_XEN_COMPAT_XENFS=y
-CONFIG_XEN_DEBUG_FS=y
-CONFIG_XEN_DEV_EVTCHN=y
-CONFIG_XEN_DOM0=y
-CONFIG_XEN_EFI=y
-CONFIG_XEN_FBDEV_FRONTEND=y
-CONFIG_XEN_GNTDEV=y
-CONFIG_XEN_GRANT_DEV_ALLOC=y
-CONFIG_XEN_HAVE_PVMMU=y
-CONFIG_XEN_HAVE_VPMU=y
-# CONFIG_XEN_MCE_LOG is not set
-CONFIG_XEN_NETDEV_FRONTEND=y
-CONFIG_XEN_PCIDEV_FRONTEND=y
-CONFIG_XEN_PRIVCMD=y
-CONFIG_XEN_PV=y
-CONFIG_XEN_PVH=y
-CONFIG_XEN_PVHVM=y
-CONFIG_XEN_PVHVM_GUEST=y
-CONFIG_XEN_PVHVM_SMP=y
-CONFIG_XEN_PV_DOM0=y
-CONFIG_XEN_PV_MSR_SAFE=y
-CONFIG_XEN_PV_SMP=y
-CONFIG_XEN_SAVE_RESTORE=y
-CONFIG_XEN_SCSI_FRONTEND=y
-CONFIG_XEN_SYMS=y
-CONFIG_XEN_SYS_HYPERVISOR=y
-CONFIG_XEN_VIRTIO=y
-# CONFIG_XEN_VIRTIO_FORCE_GRANT is not set
-CONFIG_XEN_WDT=y
-CONFIG_XEN_XENBUS_FRONTEND=y
-# CONFIG_XIAOMI_WMI is not set
-CONFIG_XPS=y
-# CONFIG_YOGABOOK_WMI is not set
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_ZONE_DMA32=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CORE=y
CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
CONFIG_FB_EFI=y
CONFIG_FB_HYPERV=y
CONFIG_FB_IOMEM_HELPERS=y
FEATURES:=squashfs ext4 vdi vmdk vhdx pcmcia targz fpu boot-part rootfs-part
SUBTARGETS:=generic legacy geode 64
-KERNEL_PATCHVER:=6.1
-KERNEL_TESTING_PATCHVER:=6.6
+KERNEL_PATCHVER:=6.6
KERNELNAME:=bzImage
+++ /dev/null
-# CONFIG_60XX_WDT is not set
-# CONFIG_64BIT is not set
-# CONFIG_ACPI is not set
-# CONFIG_ACQUIRE_WDT is not set
-# CONFIG_ADVANTECH_WDT is not set
-# CONFIG_ALIM1535_WDT is not set
-# CONFIG_ALIX is not set
-CONFIG_AMD_NB=y
-CONFIG_ARCH_32BIT_OFF_T=y
-CONFIG_ARCH_CLOCKSOURCE_INIT=y
-CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
-CONFIG_ARCH_HIBERNATION_POSSIBLE=y
-CONFIG_ARCH_MAY_HAVE_PC_FDC=y
-CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y
-CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
-CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y
-CONFIG_ARCH_NR_GPIO=512
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SPLIT_ARG64=y
-CONFIG_ARCH_STACKWALK=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_ARCH_USES_PG_UNCACHED=y
-CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y
-CONFIG_ARCH_WANTS_NO_INSTR=y
-CONFIG_ATA=y
-CONFIG_ATA_GENERIC=y
-CONFIG_ATA_PIIX=y
-# CONFIG_BARCO_P50_GPIO is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_MQ_PCI=y
-CONFIG_BOUNCE=y
-CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
-CONFIG_CC_NO_ARRAY_BOUNDS=y
-CONFIG_CLKBLD_I8253=y
-CONFIG_CLKEVT_I8253=y
-CONFIG_CLKSRC_I8253=y
-CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y
-CONFIG_CLOCKSOURCE_WATCHDOG=y
-CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100
-CONFIG_CLONE_BACKWARDS=y
-CONFIG_COMMON_CLK=y
-CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
-CONFIG_COMPAT_32=y
-CONFIG_COMPAT_32BIT_TIME=y
-# CONFIG_COMPAT_VDSO is not set
-CONFIG_CONSOLE_TRANSLATIONS=y
-# CONFIG_CPU5_WDT is not set
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
-CONFIG_CPU_FREQ_GOV_ATTR_SET=y
-CONFIG_CPU_FREQ_GOV_COMMON=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_STAT=y
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_SUP_AMD=y
-CONFIG_CPU_SUP_CENTAUR=y
-CONFIG_CPU_SUP_CYRIX_32=y
-CONFIG_CPU_SUP_HYGON=y
-CONFIG_CPU_SUP_INTEL=y
-CONFIG_CPU_SUP_TRANSMETA_32=y
-CONFIG_CPU_SUP_UMC_32=y
-CONFIG_CPU_SUP_VORTEX_32=y
-CONFIG_CPU_SUP_ZHAOXIN=y
-CONFIG_CRASH_CORE=y
-CONFIG_CRC16=y
-CONFIG_CRYPTO_CRC32=y
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_CRC32_PCLMUL is not set
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
-CONFIG_CRYPTO_LIB_SHA1=y
-CONFIG_CRYPTO_LIB_UTILS=y
-CONFIG_CRYPTO_RNG2=y
-# CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
-# CONFIG_CX_ECAT is not set
-CONFIG_DCACHE_WORD_ACCESS=y
-# CONFIG_DEBUG_BOOT_PARAMS is not set
-# CONFIG_DEBUG_ENTRY is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_DEBUG_MISC=y
-# CONFIG_DEBUG_NMI_SELFTEST is not set
-# CONFIG_DEBUG_TLBFLUSH is not set
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DMADEVICES=y
-CONFIG_DMI=y
-CONFIG_DMIID=y
-CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y
-CONFIG_DMI_SYSFS=y
-# CONFIG_DM_AUDIT is not set
-CONFIG_DNOTIFY=y
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_DYNAMIC_SIGFRAME=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EARLY_PRINTK_DBGP is not set
-CONFIG_EDAC_ATOMIC_SCRUB=y
-CONFIG_EDAC_SUPPORT=y
-# CONFIG_EDD is not set
-CONFIG_EFI_HANDOVER_PROTOCOL=y
-# CONFIG_EISA is not set
-# CONFIG_EUROTECH_WDT is not set
-# CONFIG_EXAR_WDT is not set
-CONFIG_EXCLUSIVE_SYSTEM_RAM=y
-CONFIG_EXT4_FS=y
-CONFIG_F2FS_FS=y
-# CONFIG_F71808E_WDT is not set
-CONFIG_FIRMWARE_MEMMAP=y
-CONFIG_FIX_EARLYCON_MEM=y
-CONFIG_FRAME_POINTER=y
-CONFIG_FS_IOMAP=y
-CONFIG_FS_MBCACHE=y
-CONFIG_FUSION=y
-# CONFIG_FUSION_CTL is not set
-# CONFIG_FUSION_LOGGING is not set
-CONFIG_FUSION_MAX_SGE=128
-CONFIG_FUSION_SPI=y
-CONFIG_FW_LOADER_PAGED_BUF=y
-CONFIG_FW_LOADER_SYSFS=y
-CONFIG_GCC11_NO_ARRAY_BOUNDS=y
-# CONFIG_GDS_FORCE_MITIGATION is not set
-CONFIG_GENERIC_ALLOCATOR=y
-CONFIG_GENERIC_BUG=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
-CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y
-CONFIG_GENERIC_CMOS_UPDATE=y
-CONFIG_GENERIC_CPU_AUTOPROBE=y
-CONFIG_GENERIC_CPU_VULNERABILITIES=y
-CONFIG_GENERIC_EARLY_IOREMAP=y
-CONFIG_GENERIC_ENTRY=y
-CONFIG_GENERIC_GETTIMEOFDAY=y
-CONFIG_GENERIC_IOMAP=y
-CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y
-CONFIG_GENERIC_IRQ_RESERVATION_MODE=y
-CONFIG_GENERIC_IRQ_SHOW=y
-CONFIG_GENERIC_ISA_DMA=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
-CONFIG_GENERIC_PCI_IOMAP=y
-CONFIG_GENERIC_SMP_IDLE_THREAD=y
-CONFIG_GENERIC_STRNCPY_FROM_USER=y
-CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GENERIC_TIME_VSYSCALL=y
-CONFIG_GENERIC_VDSO_32=y
-# CONFIG_GEOS is not set
-CONFIG_GLOB=y
-CONFIG_GPIO_CDEV=y
-# CONFIG_HANGCHECK_TIMER is not set
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_HAS_DMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT_MAP=y
-CONFIG_HID=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHMEM4G=y
-# CONFIG_HIGHMEM64G is not set
-CONFIG_HIGHPTE=y
-CONFIG_HPET_EMULATE_RTC=y
-CONFIG_HPET_TIMER=y
-CONFIG_HW_CONSOLE=y
-CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_GEODE=y
-CONFIG_HW_RANDOM_VIA=y
-# CONFIG_HYPERVISOR_GUEST is not set
-CONFIG_HZ_PERIODIC=y
-CONFIG_I8253_LOCK=y
-CONFIG_IA32_FEAT_CTL=y
-# CONFIG_IB700_WDT is not set
-# CONFIG_IBMASR is not set
-# CONFIG_IBM_RTL is not set
-# CONFIG_IE6XX_WDT is not set
-CONFIG_ILLEGAL_POINTER_VALUE=0
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_INPUT=y
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_INPUT_VIVALDIFMAP=y
-CONFIG_INSTRUCTION_DECODER=y
-# CONFIG_INTEL_HFI_THERMAL is not set
-# CONFIG_INTEL_LDMA is not set
-# CONFIG_INTEL_PCH_THERMAL is not set
-# CONFIG_INTEL_POWERCLAMP is not set
-# CONFIG_INTEL_SCU_PCI is not set
-# CONFIG_INTEL_TCC_COOLING is not set
-# CONFIG_INTEL_VSEC is not set
-# CONFIG_IOSF_MBI is not set
-CONFIG_IO_DELAY_0X80=y
-# CONFIG_IO_DELAY_0XED is not set
-# CONFIG_IO_DELAY_NONE is not set
-# CONFIG_IO_DELAY_UDELAY is not set
-CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
-CONFIG_IRQ_FORCED_THREADING=y
-CONFIG_IRQ_WORK=y
-# CONFIG_ISA is not set
-CONFIG_ISA_DMA_API=y
-# CONFIG_IT8712F_WDT is not set
-# CONFIG_IT87_WDT is not set
-# CONFIG_ITCO_WDT is not set
-CONFIG_JBD2=y
-CONFIG_KALLSYMS=y
-CONFIG_KEXEC=y
-CONFIG_KEXEC_CORE=y
-CONFIG_KEYBOARD_ATKBD=y
-CONFIG_KMAP_LOCAL=y
-CONFIG_LOCK_DEBUGGING_SUPPORT=y
-# CONFIG_M486 is not set
-# CONFIG_M486SX is not set
-# CONFIG_M586 is not set
-# CONFIG_M586MMX is not set
-# CONFIG_M586TSC is not set
-CONFIG_M686=y
-# CONFIG_MACHZ_WDT is not set
-# CONFIG_MATOM is not set
-# CONFIG_MCORE2 is not set
-# CONFIG_MCRUSOE is not set
-# CONFIG_MCYRIXIII is not set
-# CONFIG_MEFFICEON is not set
-# CONFIG_MELAN is not set
-CONFIG_MEMFD_CREATE=y
-# CONFIG_MFD_INTEL_LPSS_PCI is not set
-# CONFIG_MGEODEGX1 is not set
-# CONFIG_MGEODE_LX is not set
-CONFIG_MICROCODE=y
-CONFIG_MICROCODE_AMD=y
-CONFIG_MICROCODE_INTEL=y
-CONFIG_MICROCODE_LATE_LOADING=y
-CONFIG_MIGRATION=y
-CONFIG_MITIGATION_RFDS=y
-CONFIG_MITIGATION_SPECTRE_BHI=y
-# CONFIG_MK6 is not set
-# CONFIG_MK7 is not set
-# CONFIG_MK8 is not set
-CONFIG_MMU_GATHER_MERGE_VMAS=y
-# CONFIG_MODIFY_LDT_SYSCALL is not set
-CONFIG_MODULES_TREE_LOOKUP=y
-CONFIG_MODULES_USE_ELF_REL=y
-# CONFIG_MPENTIUM4 is not set
-# CONFIG_MPENTIUMII is not set
-# CONFIG_MPENTIUMIII is not set
-# CONFIG_MPENTIUMM is not set
-# CONFIG_MTD is not set
-CONFIG_MTRR=y
-# CONFIG_MTRR_SANITIZER is not set
-# CONFIG_MVIAC3_2 is not set
-# CONFIG_MVIAC7 is not set
-# CONFIG_MWINCHIP3D is not set
-# CONFIG_MWINCHIPC6 is not set
-CONFIG_NAMESPACES=y
-CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
-CONFIG_NEED_PER_CPU_KM=y
-CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
-CONFIG_NEED_SG_DMA_LENGTH=y
-# CONFIG_NET5501 is not set
-# CONFIG_NET_NS is not set
-CONFIG_NLS=y
-# CONFIG_NOHIGHMEM is not set
-CONFIG_NR_CPUS=1
-CONFIG_NR_CPUS_DEFAULT=1
-CONFIG_NR_CPUS_RANGE_BEGIN=1
-CONFIG_NR_CPUS_RANGE_END=1
-# CONFIG_NSC_GPIO is not set
-CONFIG_NVRAM=y
-# CONFIG_OF is not set
-CONFIG_OLD_SIGACTION=y
-CONFIG_OLD_SIGSUSPEND3=y
-# CONFIG_OLPC is not set
-CONFIG_OUTPUT_FORMAT="elf32-i386"
-# CONFIG_P2SB is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
-CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
-CONFIG_PC104=y
-# CONFIG_PC8736x_GPIO is not set
-# CONFIG_PC87413_WDT is not set
-# CONFIG_PCENGINES_APU2 is not set
-CONFIG_PCI=y
-CONFIG_PCI_ATS=y
-CONFIG_PCI_BIOS=y
-CONFIG_PCI_DIRECT=y
-CONFIG_PCI_DOMAINS=y
-CONFIG_PCI_GOANY=y
-# CONFIG_PCI_GOBIOS is not set
-# CONFIG_PCI_GODIRECT is not set
-# CONFIG_PCI_GOMMCONFIG is not set
-CONFIG_PCI_IOV=y
-CONFIG_PCI_LABEL=y
-CONFIG_PCI_LOCKLESS_CONFIG=y
-CONFIG_PCI_MSI=y
-CONFIG_PCI_MSI_IRQ_DOMAIN=y
-CONFIG_PCSPKR_PLATFORM=y
-CONFIG_PERF_EVENTS=y
-# CONFIG_PERF_EVENTS_AMD_BRS is not set
-# CONFIG_PERF_EVENTS_AMD_UNCORE is not set
-CONFIG_PERF_EVENTS_INTEL_CSTATE=y
-CONFIG_PERF_EVENTS_INTEL_RAPL=y
-CONFIG_PERF_EVENTS_INTEL_UNCORE=y
-CONFIG_PGTABLE_LEVELS=2
-CONFIG_PHYSICAL_ALIGN=0x100000
-CONFIG_PHYSICAL_START=0x1000000
-# CONFIG_PHY_INTEL_LGM_EMMC is not set
-CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_PREEMPT_NONE_BUILD=y
-# CONFIG_PROCESSOR_SELECT is not set
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_PROC_PID_ARCH_STATUS=y
-# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set
-CONFIG_PTP_1588_CLOCK_OPTIONAL=y
-# CONFIG_PUNIT_ATOM_DEBUG is not set
-CONFIG_RANDSTRUCT_NONE=y
-CONFIG_RATIONAL=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_GZIP=y
-CONFIG_RETHUNK=y
-CONFIG_RETPOLINE=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_MC146818_LIB=y
-CONFIG_SATA_HOST=y
-# CONFIG_SBC7240_WDT is not set
-# CONFIG_SBC8360_WDT is not set
-# CONFIG_SBC_EPX_C3_WATCHDOG is not set
-# CONFIG_SC1200_WDT is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_COMMON=y
-CONFIG_SCSI_SPI_ATTRS=y
-CONFIG_SCx200=y
-CONFIG_SCx200HR_TIMER=y
-# CONFIG_SCx200_GPIO is not set
-# CONFIG_SCx200_WDT is not set
-CONFIG_SERIAL_8250_PCI=y
-# CONFIG_SERIAL_LANTIQ is not set
-CONFIG_SERIAL_MCTRL_GPIO=y
-CONFIG_SERIO=y
-CONFIG_SERIO_I8042=y
-CONFIG_SERIO_LIBPS2=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SG_POOL=y
-# CONFIG_SIEMENS_SIMATIC_IPC is not set
-# CONFIG_SMSC37B787_WDT is not set
-# CONFIG_SMSC_SCH311X_WDT is not set
-CONFIG_SOFTIRQ_ON_OWN_STACK=y
-CONFIG_SPARSEMEM_STATIC=y
-CONFIG_SPARSE_IRQ=y
-CONFIG_SPECULATION_MITIGATIONS=y
-CONFIG_SRCU=y
-# CONFIG_STATIC_CALL_SELFTEST is not set
-# CONFIG_STRICT_SIGALTSTACK_SIZE is not set
-CONFIG_SYSCTL_EXCEPTION_TRACE=y
-# CONFIG_SYSFB_SIMPLEFB is not set
-# CONFIG_TELCLOCK is not set
-# CONFIG_TEST_FPU is not set
-CONFIG_THERMAL=y
-CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
-CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
-CONFIG_THERMAL_GOV_STEP_WISE=y
-CONFIG_THREAD_INFO_IN_TASK=y
-CONFIG_TICK_CPU_ACCOUNTING=y
-CONFIG_TINY_SRCU=y
-# CONFIG_TOSHIBA is not set
-# CONFIG_TQMX86_WDT is not set
-CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y
-CONFIG_UNWINDER_FRAME_POINTER=y
-# CONFIG_UNWINDER_GUESS is not set
-CONFIG_UP_LATE_INIT=y
-CONFIG_USB=y
-CONFIG_USB_COMMON=y
-CONFIG_USB_EHCI_HCD=y
-# CONFIG_USB_EHCI_HCD_PLATFORM is not set
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_HID=y
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_OHCI_HCD_PCI=y
-# CONFIG_USB_OHCI_HCD_PLATFORM is not set
-CONFIG_USB_PCI=y
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_UHCI_HCD=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_PCI=y
-# CONFIG_USB_XHCI_PLATFORM is not set
-# CONFIG_USER_NS is not set
-CONFIG_USER_STACKTRACE_SUPPORT=y
-CONFIG_VGA_CONSOLE=y
-# CONFIG_VIA_WDT is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_WAFER_WDT is not set
-# CONFIG_WINMATE_FM07_KEYS is not set
-CONFIG_X86=y
-CONFIG_X86_32=y
-# CONFIG_X86_32_IRIS is not set
-# CONFIG_X86_ANCIENT_MCE is not set
-# CONFIG_X86_CHECK_BIOS_CORRUPTION is not set
-CONFIG_X86_CMOV=y
-CONFIG_X86_CMPXCHG64=y
-# CONFIG_X86_CPA_STATISTICS is not set
-# CONFIG_X86_CPUFREQ_NFORCE2 is not set
-# CONFIG_X86_CPUID is not set
-# CONFIG_X86_CPU_RESCTRL is not set
-CONFIG_X86_DEBUGCTLMSR=y
-# CONFIG_X86_DEBUG_FPU is not set
-# CONFIG_X86_DECODER_SELFTEST is not set
-# CONFIG_X86_EXTENDED_PLATFORM is not set
-CONFIG_X86_FEATURE_NAMES=y
-CONFIG_X86_GENERIC=y
-# CONFIG_X86_GX_SUSPMOD is not set
-# CONFIG_X86_INTEL_PSTATE is not set
-# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set
-CONFIG_X86_INTEL_TSX_MODE_OFF=y
-# CONFIG_X86_INTEL_TSX_MODE_ON is not set
-CONFIG_X86_INTEL_USERCOPY=y
-CONFIG_X86_INTERNODE_CACHE_SHIFT=6
-CONFIG_X86_IOPL_IOPERM=y
-CONFIG_X86_IO_APIC=y
-CONFIG_X86_L1_CACHE_SHIFT=6
-# CONFIG_X86_LEGACY_VM86 is not set
-CONFIG_X86_LOCAL_APIC=y
-# CONFIG_X86_LONGRUN is not set
-CONFIG_X86_MCE=y
-# CONFIG_X86_MCELOG_LEGACY is not set
-CONFIG_X86_MCE_AMD=y
-# CONFIG_X86_MCE_INJECT is not set
-CONFIG_X86_MCE_INTEL=y
-CONFIG_X86_MCE_THRESHOLD=y
-CONFIG_X86_MINIMUM_CPU_FAMILY=6
-CONFIG_X86_MPPARSE=y
-CONFIG_X86_MSR=y
-# CONFIG_X86_P4_CLOCKMOD is not set
-CONFIG_X86_PAT=y
-CONFIG_X86_PLATFORM_DEVICES=y
-# CONFIG_X86_PLATFORM_DRIVERS_DELL is not set
-# CONFIG_X86_PLATFORM_DRIVERS_HP is not set
-# CONFIG_X86_POWERNOW_K6 is not set
-# CONFIG_X86_POWERNOW_K7 is not set
-# CONFIG_X86_REBOOTFIXUPS is not set
-CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
-# CONFIG_X86_SPEEDSTEP_CENTRINO is not set
-# CONFIG_X86_SPEEDSTEP_ICH is not set
-# CONFIG_X86_SPEEDSTEP_SMI is not set
-CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y
-CONFIG_X86_THERMAL_VECTOR=y
-CONFIG_X86_TSC=y
-CONFIG_X86_UMIP=y
-CONFIG_X86_UP_APIC=y
-CONFIG_X86_UP_IOAPIC=y
-CONFIG_X86_USE_PPRO_CHECKSUM=y
-CONFIG_X86_VERBOSE_BOOTUP=y
-CONFIG_X86_VMX_FEATURE_NAMES=y
-CONFIG_XZ_DEC_BCJ=y
-CONFIG_XZ_DEC_X86=y
-CONFIG_ZLIB_INFLATE=y
+++ /dev/null
-# CONFIG_3C515 is not set
-# CONFIG_ACER_WMI is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_AC=y
-CONFIG_ACPI_BATTERY=y
-# CONFIG_ACPI_BGRT is not set
-CONFIG_ACPI_BUTTON=y
-# CONFIG_ACPI_CMPC is not set
-CONFIG_ACPI_CONTAINER=y
-CONFIG_ACPI_CPU_FREQ_PSS=y
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_DEBUGGER is not set
-# CONFIG_ACPI_DOCK is not set
-# CONFIG_ACPI_DPTF is not set
-# CONFIG_ACPI_EC_DEBUGFS is not set
-# CONFIG_ACPI_FAN is not set
-CONFIG_ACPI_HOTPLUG_CPU=y
-CONFIG_ACPI_HOTPLUG_IOAPIC=y
-# CONFIG_ACPI_I2C_OPREGION is not set
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-# CONFIG_ACPI_PCI_SLOT is not set
-CONFIG_ACPI_PROCESSOR=y
-# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
-CONFIG_ACPI_PROCESSOR_CSTATE=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_SBS is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-CONFIG_ACPI_TAD=y
-CONFIG_ACPI_THERMAL=y
-# CONFIG_ACPI_TOSHIBA is not set
-CONFIG_ACPI_VIDEO=y
-# CONFIG_ACPI_WMI is not set
-# CONFIG_ADV_SWBUTTON is not set
-CONFIG_AGP=y
-# CONFIG_AGP_ALI is not set
-# CONFIG_AGP_AMD is not set
-# CONFIG_AGP_AMD64 is not set
-# CONFIG_AGP_ATI is not set
-# CONFIG_AGP_EFFICEON is not set
-CONFIG_AGP_INTEL=y
-# CONFIG_AGP_NVIDIA is not set
-# CONFIG_AGP_SIS is not set
-# CONFIG_AGP_SWORKS is not set
-# CONFIG_AGP_VIA is not set
-# CONFIG_AMD_PMC is not set
-# CONFIG_AMD_PMF is not set
-# CONFIG_APM is not set
-CONFIG_ARCH_CPUIDLE_HALTPOLL=y
-CONFIG_ARCH_DMA_ADDR_T_64BIT=y
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-# CONFIG_ASUS_TF103C_DOCK is not set
-# CONFIG_ASUS_WMI is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BALLOON_COMPACTION=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_BLK_MQ_VIRTIO=y
-CONFIG_BLK_PM=y
-# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set
-CONFIG_BTT=y
-CONFIG_CDROM=y
-CONFIG_CONNECTOR=y
-CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
-CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
-# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CPU_RMAP=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-# CONFIG_CS89x0_ISA is not set
-# CONFIG_DEBUG_HOTPLUG_CPU0 is not set
-CONFIG_DMA_ACPI=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DRM=y
-CONFIG_DRM_BOCHS=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_GEM_SHMEM_HELPER=y
-# CONFIG_DRM_HYPERV is not set
-CONFIG_DRM_I915=y
-CONFIG_DRM_I915_CAPTURE_ERROR=y
-CONFIG_DRM_I915_COMPRESS_ERROR=y
-# CONFIG_DRM_I915_DEBUG is not set
-# CONFIG_DRM_I915_DEBUG_GUC is not set
-# CONFIG_DRM_I915_DEBUG_MMIO is not set
-# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
-# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
-CONFIG_DRM_I915_FENCE_TIMEOUT=10000
-CONFIG_DRM_I915_FORCE_PROBE=""
-CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
-# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
-CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
-CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
-CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
-# CONFIG_DRM_I915_SELFTEST is not set
-CONFIG_DRM_I915_STOP_TIMEOUT=100
-# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
-# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
-CONFIG_DRM_I915_TIMESLICE_DURATION=1
-CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
-CONFIG_DRM_I915_USERPTR=y
-# CONFIG_DRM_I915_WERROR is not set
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_TTM=y
-CONFIG_DRM_TTM_HELPER=y
-CONFIG_DRM_VIRTIO_GPU=y
-CONFIG_DRM_VRAM_HELPER=y
-CONFIG_EFI=y
-CONFIG_EFIVAR_FS=m
-# CONFIG_EFI_BOOTLOADER_CONTROL is not set
-# CONFIG_EFI_CAPSULE_LOADER is not set
-# CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH is not set
-# CONFIG_EFI_COCO_SECRET is not set
-# CONFIG_EFI_CUSTOM_SSDT_OVERLAYS is not set
-# CONFIG_EFI_DISABLE_PCI_DMA is not set
-# CONFIG_EFI_DISABLE_RUNTIME is not set
-CONFIG_EFI_DXE_MEM_ATTRIBUTES=y
-CONFIG_EFI_EARLYCON=y
-CONFIG_EFI_ESRT=y
-# CONFIG_EFI_FAKE_MEMMAP is not set
-CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y
-# CONFIG_EFI_PGT_DUMP is not set
-# CONFIG_EFI_RCI2_TABLE is not set
-CONFIG_EFI_RUNTIME_MAP=y
-CONFIG_EFI_RUNTIME_WRAPPERS=y
-CONFIG_EFI_STUB=y
-# CONFIG_EFI_TEST is not set
-# CONFIG_EFI_VARS is not set
-# CONFIG_EL3 is not set
-CONFIG_FAILOVER=y
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-CONFIG_FB_EFI=y
-CONFIG_FB_HYPERV=y
-# CONFIG_FB_I810 is not set
-CONFIG_FB_SIMPLE=y
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-# CONFIG_FB_VESA is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FREEZER=y
-CONFIG_FW_CACHE=y
-CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
-CONFIG_GENERIC_IRQ_MIGRATION=y
-CONFIG_GENERIC_PENDING_IRQ=y
-CONFIG_GENERIC_PINCONF=y
-# CONFIG_GIGABYTE_WMI is not set
-CONFIG_GPIOLIB_IRQCHIP=y
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GUP_GET_PTE_LOW_HIGH=y
-CONFIG_HALTPOLL_CPUIDLE=y
-CONFIG_HDMI=y
-CONFIG_HIBERNATE_CALLBACKS=y
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_HID_GENERIC=y
-CONFIG_HID_HYPERV_MOUSE=y
-# CONFIG_HIGHMEM4G is not set
-CONFIG_HIGHMEM64G=y
-CONFIG_HOTPLUG_CPU=y
-CONFIG_HOTPLUG_PCI=y
-CONFIG_HOTPLUG_PCI_ACPI=y
-# CONFIG_HOTPLUG_PCI_ACPI_IBM is not set
-# CONFIG_HOTPLUG_PCI_COMPAQ is not set
-# CONFIG_HOTPLUG_PCI_CPCI is not set
-# CONFIG_HOTPLUG_PCI_IBM is not set
-CONFIG_HOTPLUG_PCI_PCIE=y
-# CONFIG_HOTPLUG_PCI_SHPC is not set
-CONFIG_HOTPLUG_SMT=y
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-# CONFIG_HP_ACCEL is not set
-# CONFIG_HUAWEI_WMI is not set
-CONFIG_HVC_DRIVER=y
-CONFIG_HVC_IRQ=y
-CONFIG_HVC_XEN=y
-CONFIG_HVC_XEN_FRONTEND=y
-CONFIG_HWMON=y
-CONFIG_HWMON_VID=y
-CONFIG_HW_RANDOM_VIRTIO=y
-CONFIG_HYPERV=y
-CONFIG_HYPERVISOR_GUEST=y
-CONFIG_HYPERV_BALLOON=y
-CONFIG_HYPERV_KEYBOARD=y
-CONFIG_HYPERV_NET=y
-CONFIG_HYPERV_STORAGE=y
-# CONFIG_HYPERV_TESTING is not set
-CONFIG_HYPERV_TIMER=y
-CONFIG_HYPERV_UTILS=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_HID_ACPI is not set
-# CONFIG_I2C_MULTI_INSTANTIATE is not set
-# CONFIG_I8K is not set
-# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
-CONFIG_INTEL_GTT=y
-CONFIG_INTEL_IDLE=y
-# CONFIG_INTEL_IPS is not set
-# CONFIG_INTEL_MEI_HDCP is not set
-# CONFIG_INTEL_MEI_PXP is not set
-# CONFIG_INTEL_MENLOW is not set
-CONFIG_INTEL_PCH_THERMAL=y
-# CONFIG_INTEL_SAR_INT1092 is not set
-# CONFIG_INTEL_SCU_PLATFORM is not set
-CONFIG_INTEL_SOC_DTS_IOSF_CORE=y
-CONFIG_INTEL_SOC_DTS_THERMAL=y
-# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
-# CONFIG_INTEL_WMI_THUNDERBOLT is not set
-CONFIG_INTERVAL_TREE=y
-CONFIG_IOSF_MBI=y
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_IRQ_BYPASS_MANAGER=y
-CONFIG_ISA=y
-CONFIG_ISAPNP=y
-CONFIG_ISA_BUS_API=y
-# CONFIG_ISCSI_IBFT is not set
-CONFIG_ISO9660_FS=y
-# CONFIG_JOLIET is not set
-CONFIG_KCMP=y
-CONFIG_KVM=y
-CONFIG_KVM_AMD=y
-CONFIG_KVM_ASYNC_PF=y
-CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
-CONFIG_KVM_GUEST=y
-CONFIG_KVM_INTEL=y
-CONFIG_KVM_MMIO=y
-CONFIG_KVM_VFIO=y
-# CONFIG_KVM_XEN is not set
-CONFIG_KVM_XFER_TO_GUEST_WORK=y
-# CONFIG_LANCE is not set
-# CONFIG_LG_LAPTOP is not set
-CONFIG_LIBNVDIMM=y
-CONFIG_LOCK_SPIN_ON_OWNER=y
-# CONFIG_M686 is not set
-# CONFIG_MDA_CONSOLE is not set
-CONFIG_MEMORY_BALLOON=y
-CONFIG_MEMREGION=y
-CONFIG_MFD_CORE=y
-CONFIG_MFD_INTEL_LPSS=y
-CONFIG_MFD_INTEL_LPSS_ACPI=y
-# CONFIG_MFD_INTEL_PMC_BXT is not set
-# CONFIG_MIXCOMWD is not set
-CONFIG_MMC=y
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_CQHCI=y
-CONFIG_MMC_RICOH_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_IO_ACCESSORS=y
-CONFIG_MMC_SDHCI_PCI=y
-# CONFIG_MMC_SDHCI_PLTFM is not set
-# CONFIG_MMC_WBSD is not set
-CONFIG_MMU_NOTIFIER=y
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_CYAPA is not set
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-# CONFIG_MOUSE_PS2_BYD is not set
-# CONFIG_MOUSE_PS2_CYPRESS is not set
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_PS2_VMMOUSE is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-CONFIG_MPENTIUM4=y
-# CONFIG_MSI_WMI is not set
-CONFIG_MUTEX_SPIN_ON_OWNER=y
-# CONFIG_MXM_WMI is not set
-CONFIG_ND_BLK=y
-CONFIG_ND_BTT=y
-CONFIG_ND_CLAIM=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_NET_FAILOVER=y
-CONFIG_NET_FLOW_LIMIT=y
-CONFIG_NET_PTP_CLASSIFY=y
-CONFIG_NO_HZ=y
-CONFIG_NR_CPUS=4
-CONFIG_NR_CPUS_DEFAULT=8
-CONFIG_NR_CPUS_RANGE_BEGIN=2
-CONFIG_NR_CPUS_RANGE_END=8
-# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
-CONFIG_PADATA=y
-CONFIG_PAGE_POOL=y
-CONFIG_PAGE_REPORTING=y
-CONFIG_PAGE_TABLE_ISOLATION=y
-CONFIG_PARAVIRT=y
-CONFIG_PARAVIRT_CLOCK=y
-# CONFIG_PARAVIRT_DEBUG is not set
-CONFIG_PARAVIRT_SPINLOCKS=y
-CONFIG_PATA_AMD=y
-CONFIG_PATA_ATIIXP=y
-CONFIG_PATA_MPIIX=y
-CONFIG_PATA_OLDPIIX=y
-CONFIG_PATA_PLATFORM=y
-CONFIG_PATA_SC1200=y
-CONFIG_PATA_TIMINGS=y
-CONFIG_PATA_VIA=y
-# CONFIG_PCENGINES_APU2 is not set
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIE_PME=y
-CONFIG_PCI_MMCONFIG=y
-CONFIG_PCI_XEN=y
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_PEAQ_WMI is not set
-CONFIG_PGTABLE_LEVELS=3
-CONFIG_PHYS_ADDR_T_64BIT=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_ALDERLAKE=y
-CONFIG_PINCTRL_BAYTRAIL=y
-CONFIG_PINCTRL_BROXTON=y
-CONFIG_PINCTRL_CANNONLAKE=y
-CONFIG_PINCTRL_CHERRYVIEW=y
-CONFIG_PINCTRL_DENVERTON=y
-CONFIG_PINCTRL_ELKHARTLAKE=y
-CONFIG_PINCTRL_EMMITSBURG=y
-CONFIG_PINCTRL_GEMINILAKE=y
-CONFIG_PINCTRL_INTEL=y
-CONFIG_PINCTRL_JASPERLAKE=y
-CONFIG_PINCTRL_LAKEFIELD=y
-CONFIG_PINCTRL_LEWISBURG=y
-CONFIG_PINCTRL_LYNXPOINT=y
-CONFIG_PINCTRL_METEORLAKE=y
-CONFIG_PINCTRL_SUNRISEPOINT=y
-CONFIG_PINCTRL_TIGERLAKE=y
-CONFIG_PM=y
-# CONFIG_PMIC_OPREGION is not set
-CONFIG_PM_CLK=y
-CONFIG_PM_SLEEP=y
-CONFIG_PM_SLEEP_SMP=y
-CONFIG_PNP=y
-CONFIG_PNPACPI=y
-# CONFIG_PNPBIOS is not set
-CONFIG_PNP_DEBUG_MESSAGES=y
-CONFIG_PPS=y
-CONFIG_PREEMPT_NOTIFIERS=y
-CONFIG_PROC_EVENTS=y
-CONFIG_PTP_1588_CLOCK=y
-CONFIG_PTP_1588_CLOCK_KVM=y
-CONFIG_PTP_1588_CLOCK_VMW=y
-CONFIG_PVH=y
-CONFIG_QUEUED_RWLOCKS=y
-CONFIG_QUEUED_SPINLOCKS=y
-CONFIG_RAS=y
-CONFIG_RELAY=y
-CONFIG_RELOCATABLE=y
-CONFIG_RESET_ATTACK_MITIGATION=y
-CONFIG_RFS_ACCEL=y
-CONFIG_RPS=y
-CONFIG_RTC_I2C_AND_SPI=y
-CONFIG_RWSEM_SPIN_ON_OWNER=y
-# CONFIG_SAMSUNG_Q10 is not set
-CONFIG_SATA_AHCI=y
-CONFIG_SATA_VIA=y
-# CONFIG_SCHED_CORE is not set
-CONFIG_SCHED_INFO=y
-CONFIG_SCHED_SMT=y
-# CONFIG_SCSI_FDOMAIN_ISA is not set
-CONFIG_SCSI_VIRTIO=y
-# CONFIG_SENSORS_ASUS_EC is not set
-# CONFIG_SENSORS_ASUS_WMI is not set
-CONFIG_SENSORS_CORETEMP=y
-CONFIG_SENSORS_FAM15H_POWER=y
-CONFIG_SENSORS_I5500=y
-CONFIG_SENSORS_K8TEMP=y
-CONFIG_SENSORS_K10TEMP=y
-CONFIG_SENSORS_VIA_CPUTEMP=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
-CONFIG_SMP=y
-# CONFIG_SND_HDA_CTL_DEV_ID is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
-# CONFIG_SND_SOC_AMD_ACP6x is not set
-# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
-# CONFIG_SND_SOC_AMD_PS is not set
-# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
-# CONFIG_SND_SOC_INTEL_AVS is not set
-CONFIG_SOCK_RX_QUEUE_MAPPING=y
-# CONFIG_SURFACE_PLATFORMS is not set
-CONFIG_SWIOTLB=y
-CONFIG_SYNC_FILE=y
-# CONFIG_SYSTEM76_ACPI is not set
-CONFIG_SYS_HYPERVISOR=y
-CONFIG_TASKSTATS=y
-CONFIG_TASK_DELAY_ACCT=y
-CONFIG_THERMAL_GOV_USER_SPACE=y
-CONFIG_THERMAL_HWMON=y
-CONFIG_THERMAL_WRITABLE_TRIPS=y
-# CONFIG_THINKPAD_LMI is not set
-# CONFIG_TOSHIBA_BT_RFKILL is not set
-# CONFIG_TOSHIBA_WMI is not set
-CONFIG_TREE_RCU=y
-CONFIG_TREE_SRCU=y
-# CONFIG_UCLAMP_TASK is not set
-CONFIG_UCS2_STRING=y
-CONFIG_USB_STORAGE=y
-CONFIG_USER_RETURN_NOTIFIER=y
-CONFIG_VHOST=y
-CONFIG_VHOST_IOTLB=y
-CONFIG_VHOST_NET=y
-# CONFIG_VIDEO_IPU3_CIO2 is not set
-CONFIG_VIRTIO=y
-CONFIG_VIRTIO_BALLOON=y
-CONFIG_VIRTIO_BLK=y
-CONFIG_VIRTIO_CONSOLE=y
-CONFIG_VIRTIO_DMA_SHARED_BUFFER=y
-CONFIG_VIRTIO_INPUT=y
-CONFIG_VIRTIO_MMIO=y
-CONFIG_VIRTIO_NET=y
-CONFIG_VIRTIO_PCI=y
-CONFIG_VIRTIO_PCI_LEGACY=y
-CONFIG_VIRTIO_PCI_LIB=y
-# CONFIG_VIRTIO_PMEM is not set
-CONFIG_VIRTUALIZATION=y
-CONFIG_VMAP_PFN=y
-CONFIG_VT_CONSOLE_SLEEP=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WDT is not set
-# CONFIG_WIRELESS_HOTKEY is not set
-# CONFIG_WMI_BMOF is not set
-CONFIG_X86_32_SMP=y
-CONFIG_X86_ACPI_CPUFREQ=y
-# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
-CONFIG_X86_AMD_FREQ_SENSITIVITY=y
-CONFIG_X86_AMD_PLATFORM_DEVICE=y
-CONFIG_X86_AMD_PSTATE=y
-# CONFIG_X86_AMD_PSTATE_UT is not set
-# CONFIG_X86_BIGSMP is not set
-CONFIG_X86_CPUID=y
-# CONFIG_X86_E_POWERSAVER is not set
-CONFIG_X86_HV_CALLBACK_VECTOR=y
-CONFIG_X86_INTEL_LPSS=y
-CONFIG_X86_INTEL_PSTATE=y
-CONFIG_X86_INTERNODE_CACHE_SHIFT=7
-CONFIG_X86_L1_CACHE_SHIFT=7
-# CONFIG_X86_LONGHAUL is not set
-CONFIG_X86_NEED_RELOCS=y
-CONFIG_X86_PAE=y
-# CONFIG_X86_PCC_CPUFREQ is not set
-CONFIG_X86_PKG_TEMP_THERMAL=y
-# CONFIG_X86_PMEM_LEGACY is not set
-CONFIG_X86_PM_TIMER=y
-# CONFIG_X86_POWERNOW_K8 is not set
-CONFIG_XEN=y
-CONFIG_XENFS=y
-CONFIG_XEN_ACPI=y
-CONFIG_XEN_AUTO_XLATE=y
-# CONFIG_XEN_BACKEND is not set
-CONFIG_XEN_BALLOON=y
-CONFIG_XEN_BLKDEV_FRONTEND=y
-CONFIG_XEN_COMPAT_XENFS=y
-CONFIG_XEN_DEBUG_FS=y
-CONFIG_XEN_DEV_EVTCHN=y
-CONFIG_XEN_FBDEV_FRONTEND=y
-CONFIG_XEN_GNTDEV=y
-CONFIG_XEN_GRANT_DEV_ALLOC=y
-CONFIG_XEN_NETDEV_FRONTEND=y
-CONFIG_XEN_PRIVCMD=y
-CONFIG_XEN_PVH=y
-CONFIG_XEN_PVHVM=y
-CONFIG_XEN_PVHVM_GUEST=y
-CONFIG_XEN_PVHVM_SMP=y
-CONFIG_XEN_SAVE_RESTORE=y
-CONFIG_XEN_SCSI_FRONTEND=y
-CONFIG_XEN_SYS_HYPERVISOR=y
-CONFIG_XEN_VIRTIO=y
-# CONFIG_XEN_VIRTIO_FORCE_GRANT is not set
-CONFIG_XEN_WDT=y
-CONFIG_XEN_XENBUS_FRONTEND=y
-# CONFIG_XIAOMI_WMI is not set
-CONFIG_XPS=y
-# CONFIG_YOGABOOK_WMI is not set
-CONFIG_ZLIB_DEFLATE=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CORE=y
CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
CONFIG_FB_EFI=y
CONFIG_FB_HYPERV=y
# CONFIG_FB_I810 is not set
+++ /dev/null
-# CONFIG_3C515 is not set
-CONFIG_8139CP=y
-CONFIG_8139TOO=y
-CONFIG_8139TOO_8129=y
-CONFIG_8139TOO_PIO=y
-# CONFIG_8139TOO_TUNE_TWISTER is not set
-# CONFIG_8139_OLD_RX_RESET is not set
-# CONFIG_ACER_WMI is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_AC=y
-# CONFIG_ACPI_BATTERY is not set
-# CONFIG_ACPI_CMPC is not set
-# CONFIG_ACPI_CONTAINER is not set
-CONFIG_ACPI_CPU_FREQ_PSS=y
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_DEBUGGER is not set
-# CONFIG_ACPI_DOCK is not set
-# CONFIG_ACPI_DPTF is not set
-# CONFIG_ACPI_EC_DEBUGFS is not set
-CONFIG_ACPI_FAN=y
-CONFIG_ACPI_HOTPLUG_IOAPIC=y
-CONFIG_ACPI_I2C_OPREGION=y
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-# CONFIG_ACPI_PCI_SLOT is not set
-CONFIG_ACPI_PROCESSOR=y
-# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
-CONFIG_ACPI_PROCESSOR_CSTATE=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_SBS is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-CONFIG_ACPI_THERMAL=y
-# CONFIG_ACPI_TINY_POWER_BUTTON is not set
-# CONFIG_ACPI_WMI is not set
-# CONFIG_ADV_SWBUTTON is not set
-CONFIG_ALIX=y
-# CONFIG_AMD_PMC is not set
-# CONFIG_AMD_PMF is not set
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-# CONFIG_ASUS_TF103C_DOCK is not set
-# CONFIG_ATA_PIIX is not set
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-CONFIG_CS5535_CLOCK_EVENT_SRC=y
-CONFIG_CS5535_MFGPT=y
-CONFIG_CS5535_MFGPT_DEFAULT_IRQ=7
-# CONFIG_CS89x0_ISA is not set
-CONFIG_DMA_ACPI=y
-# CONFIG_EL3 is not set
-CONFIG_GEODE_WDT=y
-CONFIG_GEOS=y
-# CONFIG_GIGABYTE_WMI is not set
-CONFIG_GPIO_ACPI=y
-CONFIG_GPIO_CDEV=y
-CONFIG_GPIO_CS5535=y
-# CONFIG_HPET is not set
-# CONFIG_HP_ACCEL is not set
-CONFIG_HWMON=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-CONFIG_I2C_ALGOPCA=y
-CONFIG_I2C_ALGOPCF=y
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_HID_ACPI is not set
-# CONFIG_I2C_MULTI_INSTANTIATE is not set
-# CONFIG_I8K is not set
-# CONFIG_INTEL_IPS is not set
-# CONFIG_INTEL_MENLOW is not set
-# CONFIG_INTEL_SAR_INT1092 is not set
-# CONFIG_INTEL_SCU_PLATFORM is not set
-# CONFIG_INTEL_SOC_DTS_THERMAL is not set
-# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
-# CONFIG_INTEL_WMI_THUNDERBOLT is not set
-CONFIG_IOSF_MBI=y
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_ISA=y
-# CONFIG_ISAPNP is not set
-CONFIG_ISA_BUS_API=y
-# CONFIG_ISCSI_IBFT is not set
-# CONFIG_LANCE is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_M686 is not set
-# CONFIG_MDA_CONSOLE is not set
-CONFIG_MFD_CORE=y
-CONFIG_MFD_CS5535=y
-# CONFIG_MFD_INTEL_LPSS_ACPI is not set
-# CONFIG_MFD_INTEL_PMC_BXT is not set
-CONFIG_MGEODEGX1=y
-# CONFIG_MIXCOMWD is not set
-# CONFIG_MSI_WMI is not set
-# CONFIG_MXM_WMI is not set
-CONFIG_NATSEMI=y
-CONFIG_NET5501=y
-CONFIG_NSC_GPIO=y
-# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
-CONFIG_PATA_CS5520=y
-CONFIG_PATA_CS5530=y
-CONFIG_PATA_CS5535=y
-CONFIG_PATA_CS5536=y
-CONFIG_PATA_SC1200=y
-CONFIG_PC8736x_GPIO=y
-# CONFIG_PCENGINES_APU2 is not set
-CONFIG_PCI_MMCONFIG=y
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_PEAQ_WMI is not set
-CONFIG_PINCTRL=y
-# CONFIG_PINCTRL_ALDERLAKE is not set
-# CONFIG_PINCTRL_BAYTRAIL is not set
-# CONFIG_PINCTRL_BROXTON is not set
-# CONFIG_PINCTRL_CANNONLAKE is not set
-# CONFIG_PINCTRL_CHERRYVIEW is not set
-# CONFIG_PINCTRL_DENVERTON is not set
-# CONFIG_PINCTRL_ELKHARTLAKE is not set
-# CONFIG_PINCTRL_EMMITSBURG is not set
-# CONFIG_PINCTRL_GEMINILAKE is not set
-# CONFIG_PINCTRL_JASPERLAKE is not set
-# CONFIG_PINCTRL_LAKEFIELD is not set
-# CONFIG_PINCTRL_LEWISBURG is not set
-# CONFIG_PINCTRL_LYNXPOINT is not set
-# CONFIG_PINCTRL_METEORLAKE is not set
-# CONFIG_PINCTRL_SUNRISEPOINT is not set
-# CONFIG_PINCTRL_TIGERLAKE is not set
-# CONFIG_PMIC_OPREGION is not set
-CONFIG_PNP=y
-CONFIG_PNPACPI=y
-# CONFIG_PNPBIOS is not set
-CONFIG_PNP_DEBUG_MESSAGES=y
-CONFIG_RTC_I2C_AND_SPI=y
-# CONFIG_SAMSUNG_Q10 is not set
-CONFIG_SC1200_WDT=y
-# CONFIG_SCSI_FDOMAIN_ISA is not set
-CONFIG_SCx200_ACB=y
-CONFIG_SCx200_WDT=y
-# CONFIG_SENSORS_ASUS_EC is not set
-# CONFIG_SENSORS_ASUS_WMI is not set
-CONFIG_SENSORS_LM90=y
-CONFIG_SERIAL_8250_PNP=y
-CONFIG_SERIAL_MCTRL_GPIO=y
-# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
-# CONFIG_SND_HDA_CTL_DEV_ID is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
-# CONFIG_SND_SOC_AMD_ACP6x is not set
-# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
-# CONFIG_SND_SOC_AMD_PS is not set
-# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
-# CONFIG_SND_SOC_INTEL_AVS is not set
-# CONFIG_SURFACE_PLATFORMS is not set
-# CONFIG_SYSTEM76_ACPI is not set
-# CONFIG_THINKPAD_LMI is not set
-# CONFIG_TOSHIBA_BT_RFKILL is not set
-# CONFIG_TOSHIBA_WMI is not set
-# CONFIG_USB_UHCI_HCD is not set
-CONFIG_VIA_RHINE=y
-CONFIG_VIA_RHINE_MMIO=y
-CONFIG_WATCHDOG_CORE=y
-# CONFIG_WDT is not set
-# CONFIG_WIRELESS_HOTKEY is not set
-# CONFIG_WMI_BMOF is not set
-# CONFIG_X86_ACPI_CPUFREQ is not set
-CONFIG_X86_ALIGNMENT_16=y
-# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
-# CONFIG_X86_AMD_PSTATE is not set
-# CONFIG_X86_AMD_PSTATE_UT is not set
-CONFIG_X86_CPUID=y
-# CONFIG_X86_E_POWERSAVER is not set
-CONFIG_X86_INTEL_LPSS=y
-# CONFIG_X86_LONGHAUL is not set
-# CONFIG_X86_MCE is not set
-CONFIG_X86_MINIMUM_CPU_FAMILY=5
-# CONFIG_X86_PCC_CPUFREQ is not set
-CONFIG_X86_PM_TIMER=y
-CONFIG_X86_REBOOTFIXUPS=y
-# CONFIG_XIAOMI_WMI is not set
-# CONFIG_YOGABOOK_WMI is not set
+++ /dev/null
-# CONFIG_3C515 is not set
-# CONFIG_ACER_WMI is not set
-CONFIG_ACPI=y
-CONFIG_ACPI_AC=y
-CONFIG_ACPI_BATTERY=y
-CONFIG_ACPI_BUTTON=y
-# CONFIG_ACPI_CMPC is not set
-# CONFIG_ACPI_CONTAINER is not set
-CONFIG_ACPI_CPU_FREQ_PSS=y
-# CONFIG_ACPI_DEBUG is not set
-# CONFIG_ACPI_DEBUGGER is not set
-# CONFIG_ACPI_DOCK is not set
-# CONFIG_ACPI_DPTF is not set
-# CONFIG_ACPI_EC_DEBUGFS is not set
-# CONFIG_ACPI_FAN is not set
-CONFIG_ACPI_HOTPLUG_IOAPIC=y
-# CONFIG_ACPI_I2C_OPREGION is not set
-CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y
-# CONFIG_ACPI_PCI_SLOT is not set
-CONFIG_ACPI_PROCESSOR=y
-# CONFIG_ACPI_PROCESSOR_AGGREGATOR is not set
-CONFIG_ACPI_PROCESSOR_CSTATE=y
-CONFIG_ACPI_PROCESSOR_IDLE=y
-CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y
-# CONFIG_ACPI_SBS is not set
-CONFIG_ACPI_SPCR_TABLE=y
-CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y
-CONFIG_ACPI_THERMAL=y
-# CONFIG_ACPI_TOSHIBA is not set
-CONFIG_ACPI_VIDEO=y
-# CONFIG_ACPI_WMI is not set
-# CONFIG_ADV_SWBUTTON is not set
-CONFIG_AGP=y
-# CONFIG_AGP_ALI is not set
-# CONFIG_AGP_AMD is not set
-# CONFIG_AGP_AMD64 is not set
-# CONFIG_AGP_ATI is not set
-# CONFIG_AGP_EFFICEON is not set
-CONFIG_AGP_INTEL=y
-# CONFIG_AGP_NVIDIA is not set
-# CONFIG_AGP_SIS is not set
-# CONFIG_AGP_SWORKS is not set
-# CONFIG_AGP_VIA is not set
-# CONFIG_AMD_PMC is not set
-# CONFIG_AMD_PMF is not set
-CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y
-# CONFIG_ASUS_TF103C_DOCK is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BLK_DEV_SR=y
-CONFIG_CDROM=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
-# CONFIG_CS89x0_ISA is not set
-CONFIG_DMA_ACPI=y
-CONFIG_DMA_SHARED_BUFFER=y
-CONFIG_DRM=y
-CONFIG_DRM_AMDGPU=y
-# CONFIG_DRM_AMD_DC is not set
-CONFIG_DRM_BOCHS=y
-CONFIG_DRM_BRIDGE=y
-CONFIG_DRM_FBDEV_EMULATION=y
-CONFIG_DRM_FBDEV_OVERALLOC=100
-CONFIG_DRM_I915=y
-CONFIG_DRM_I915_CAPTURE_ERROR=y
-CONFIG_DRM_I915_COMPRESS_ERROR=y
-# CONFIG_DRM_I915_DEBUG is not set
-# CONFIG_DRM_I915_DEBUG_GUC is not set
-# CONFIG_DRM_I915_DEBUG_MMIO is not set
-# CONFIG_DRM_I915_DEBUG_RUNTIME_PM is not set
-# CONFIG_DRM_I915_DEBUG_VBLANK_EVADE is not set
-CONFIG_DRM_I915_FENCE_TIMEOUT=10000
-CONFIG_DRM_I915_FORCE_PROBE=""
-CONFIG_DRM_I915_HEARTBEAT_INTERVAL=2500
-# CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS is not set
-CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000
-CONFIG_DRM_I915_PREEMPT_TIMEOUT=640
-CONFIG_DRM_I915_REQUEST_TIMEOUT=20000
-# CONFIG_DRM_I915_SELFTEST is not set
-CONFIG_DRM_I915_STOP_TIMEOUT=100
-# CONFIG_DRM_I915_SW_FENCE_CHECK_DAG is not set
-# CONFIG_DRM_I915_SW_FENCE_DEBUG_OBJECTS is not set
-CONFIG_DRM_I915_TIMESLICE_DURATION=1
-CONFIG_DRM_I915_USERFAULT_AUTOSUSPEND=250
-CONFIG_DRM_I915_USERPTR=y
-# CONFIG_DRM_I915_WERROR is not set
-CONFIG_DRM_KMS_HELPER=y
-CONFIG_DRM_MIPI_DSI=y
-CONFIG_DRM_PANEL=y
-CONFIG_DRM_PANEL_BRIDGE=y
-CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
-CONFIG_DRM_RADEON=y
-CONFIG_DRM_SCHED=y
-CONFIG_DRM_TTM=y
-CONFIG_DRM_TTM_HELPER=y
-CONFIG_DRM_VRAM_HELPER=y
-# CONFIG_EL3 is not set
-CONFIG_FB=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_CMDLINE=y
-CONFIG_FB_DEFERRED_IO=y
-# CONFIG_FB_I810 is not set
-CONFIG_FB_SYS_COPYAREA=y
-CONFIG_FB_SYS_FILLRECT=y
-CONFIG_FB_SYS_FOPS=y
-CONFIG_FB_SYS_IMAGEBLIT=y
-# CONFIG_FB_VESA is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_FONT_SUPPORT=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_GIGABYTE_WMI is not set
-CONFIG_HDMI=y
-CONFIG_HID_BATTERY_STRENGTH=y
-# CONFIG_HIGHMEM4G is not set
-CONFIG_HPET=y
-CONFIG_HPET_MMAP=y
-# CONFIG_HP_ACCEL is not set
-# CONFIG_HUAWEI_WMI is not set
-CONFIG_HWMON=y
-CONFIG_I2C=y
-CONFIG_I2C_ALGOBIT=y
-# CONFIG_I2C_AMD_MP2 is not set
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_HID_ACPI is not set
-# CONFIG_I2C_MULTI_INSTANTIATE is not set
-# CONFIG_I8K is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-CONFIG_INTEL_GTT=y
-CONFIG_INTEL_IDLE=y
-# CONFIG_INTEL_IPS is not set
-# CONFIG_INTEL_MEI_HDCP is not set
-# CONFIG_INTEL_MEI_PXP is not set
-# CONFIG_INTEL_MENLOW is not set
-# CONFIG_INTEL_SAR_INT1092 is not set
-# CONFIG_INTEL_SCU_PLATFORM is not set
-# CONFIG_INTEL_SOC_DTS_THERMAL is not set
-# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set
-# CONFIG_INTEL_WMI_THUNDERBOLT is not set
-CONFIG_INTERVAL_TREE=y
-CONFIG_IOSF_MBI=y
-# CONFIG_IOSF_MBI_DEBUG is not set
-CONFIG_ISA=y
-CONFIG_ISAPNP=y
-CONFIG_ISA_BUS_API=y
-# CONFIG_ISCSI_IBFT is not set
-CONFIG_ISO9660_FS=y
-# CONFIG_JOLIET is not set
-CONFIG_KCMP=y
-# CONFIG_LANCE is not set
-# CONFIG_LG_LAPTOP is not set
-CONFIG_M586MMX=y
-# CONFIG_M686 is not set
-# CONFIG_MDA_CONSOLE is not set
-CONFIG_MFD_CORE=y
-CONFIG_MFD_INTEL_LPSS=y
-CONFIG_MFD_INTEL_LPSS_ACPI=y
-# CONFIG_MFD_INTEL_PMC_BXT is not set
-# CONFIG_MIXCOMWD is not set
-CONFIG_MMU_NOTIFIER=y
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_CYAPA is not set
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-# CONFIG_MOUSE_PS2_BYD is not set
-# CONFIG_MOUSE_PS2_CYPRESS is not set
-# CONFIG_MOUSE_PS2_ELANTECH is not set
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SMBUS=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_MSI_WMI is not set
-# CONFIG_MXM_WMI is not set
-CONFIG_NOHIGHMEM=y
-CONFIG_NO_HZ=y
-# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set
-CONFIG_PATA_AMD=y
-CONFIG_PATA_ATIIXP=y
-CONFIG_PATA_LEGACY=y
-CONFIG_PATA_MPIIX=y
-CONFIG_PATA_OLDPIIX=y
-CONFIG_PATA_PLATFORM=y
-CONFIG_PATA_SC1200=y
-CONFIG_PATA_SIS=y
-CONFIG_PATA_TIMINGS=y
-CONFIG_PATA_VIA=y
-CONFIG_PCIEAER=y
-CONFIG_PCIEASPM=y
-CONFIG_PCIEASPM_DEFAULT=y
-# CONFIG_PCIEASPM_PERFORMANCE is not set
-# CONFIG_PCIEASPM_POWERSAVE is not set
-# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCI_MMCONFIG=y
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_PEAQ_WMI is not set
-# CONFIG_PMIC_OPREGION is not set
-CONFIG_PNP=y
-CONFIG_PNPACPI=y
-# CONFIG_PNPBIOS is not set
-CONFIG_PNP_DEBUG_MESSAGES=y
-CONFIG_RAS=y
-CONFIG_RELAY=y
-CONFIG_RTC_I2C_AND_SPI=y
-# CONFIG_SAMSUNG_Q10 is not set
-CONFIG_SATA_AHCI=y
-# CONFIG_SCSI_FDOMAIN_ISA is not set
-# CONFIG_SENSORS_ASUS_EC is not set
-# CONFIG_SENSORS_ASUS_WMI is not set
-CONFIG_SERIAL_8250_PNP=y
-# CONFIG_SERIAL_MULTI_INSTANTIATE is not set
-# CONFIG_SND_HDA_CTL_DEV_ID is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_I2C is not set
-# CONFIG_SND_HDA_SCODEC_CS35L41_SPI is not set
-# CONFIG_SND_SOC_AMD_ACP6x is not set
-# CONFIG_SND_SOC_AMD_ACP_COMMON is not set
-# CONFIG_SND_SOC_AMD_PS is not set
-# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set
-# CONFIG_SND_SOC_INTEL_AVS is not set
-# CONFIG_SURFACE_PLATFORMS is not set
-CONFIG_SYNC_FILE=y
-# CONFIG_SYSTEM76_ACPI is not set
-# CONFIG_THINKPAD_LMI is not set
-# CONFIG_TOSHIBA_BT_RFKILL is not set
-# CONFIG_TOSHIBA_WMI is not set
-CONFIG_USB_STORAGE=y
-# CONFIG_VIDEO_IPU3_CIO2 is not set
-CONFIG_VMAP_PFN=y
-# CONFIG_WDT is not set
-# CONFIG_WIRELESS_HOTKEY is not set
-# CONFIG_WMI_BMOF is not set
-CONFIG_X86_ACPI_CPUFREQ=y
-# CONFIG_X86_ACPI_CPUFREQ_CPB is not set
-CONFIG_X86_ALIGNMENT_16=y
-# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set
-# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
-# CONFIG_X86_AMD_PSTATE is not set
-# CONFIG_X86_AMD_PSTATE_UT is not set
-# CONFIG_X86_E_POWERSAVER is not set
-CONFIG_X86_F00F_BUG=y
-# CONFIG_X86_INTEL_LPSS is not set
-# CONFIG_X86_LONGHAUL is not set
-CONFIG_X86_MINIMUM_CPU_FAMILY=5
-# CONFIG_X86_PAE is not set
-# CONFIG_X86_PCC_CPUFREQ is not set
-CONFIG_X86_PM_TIMER=y
-# CONFIG_X86_POWERNOW_K8 is not set
-# CONFIG_XIAOMI_WMI is not set
-# CONFIG_YOGABOOK_WMI is not set
-CONFIG_ZLIB_DEFLATE=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CORE=y
CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_DEVICE=y
# CONFIG_FB_I810 is not set
CONFIG_FB_IOMEM_HELPERS=y
CONFIG_FB_SYSMEM_HELPERS=y
+++ /dev/null
---- a/drivers/clocksource/timer-cs5535.c
-+++ b/drivers/clocksource/timer-cs5535.c
-@@ -127,7 +127,9 @@ static irqreturn_t mfgpt_tick(int irq, v
- cs5535_mfgpt_write(cs5535_event_clock, MFGPT_REG_SETUP,
- MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
-
-- cs5535_clockevent.event_handler(&cs5535_clockevent);
-+ if (cs5535_clockevent.event_handler)
-+ cs5535_clockevent.event_handler(&cs5535_clockevent);
-+
- return IRQ_HANDLED;
- }
-
+++ /dev/null
-From 970d9af9015a387bb81841faf05dcc1a171eb97a Mon Sep 17 00:00:00 2001
-From: Philip Prindeville <philipp@redfish-solutions.com>
-Date: Sun, 1 Jan 2023 15:25:04 -0700
-Subject: [PATCH v3 1/1] x86: Support APU5 in PCEngines platform driver
-To: platform-driver-x86@vger.kernel.org, linux-x86_64@vger.kernel.org
-Cc: Ed Wildgoose <lists@wildgooses.com>, Andres Salomon <dilinger@queued.net>, Andreas Eberlein <foodeas@aeberlein.de>, Paul Spooren <paul@spooren.de>
-
-PCEngines make a number of SBC. APU5 has 5 mpcie slots + MSATA.
-It also has support for 3x LTE modems with 6x SIM slots (pairs with a
-SIM switch device). Each mpcie slot for modems has a reset GPIO
-
-To ensure that the naming is sane between APU2-6 the GPIOS are
-renamed to be modem1-reset, modem2-reset, etc. This is significant
-because the slots that can be reset change between APU2 and APU3/4
-
-GPIO for simswap is moved to the end of the list as it could be dropped
-for APU2 boards (but causes no harm to leave it in, hardware could be
-added to a future rev of the board).
-
-Structure of the GPIOs for APU5 is extremely similar to APU2-4, but
-many lines are moved around and there are simply more
-modems/resets/sim-swap lines to breakout.
-
-Also added APU6, which is essentially APU4 with a different ethernet
-interface and SFP cage on eth0.
-
-Revision history:
-
-v1: originally titled, "apu6: add apu6 variation to apu2 driver family"
-this dealt only with detecting the APUv6, which is otherwise identical
-to the v4 excepting the SFP cage on eth0.
-
-v2: at Ed's request, merged with his previous pull-request titled
-"x86: Support APU5 in PCEngines platform driver", and some cleanup
-to that changeset (including dropping the table "apu5_driver_data"
-which did not have a defined type "struct apu_driver_data"), but got
-mistitled when the Subject of that commit got accidentally dropped.
-
-v3: retitled to match Ed's previous pull-request.
-
-Cc: platform-driver-x86@vger.kernel.org
-Cc: linux-x86_64@vger.kernel.org
-Reviewed-by: Andreas Eberlein <foodeas@aeberlein.de>
-Reviewed-by: Paul Spooren <paul@spooren.de>
-Signed-off-by: Ed Wildgoose <lists@wildgooses.com>
-Sighed-off-by: Philip Prindeville <philipp@redfish-solutions.com>
----
- drivers/leds/leds-apu.c | 2 +-
- drivers/platform/x86/Kconfig | 4 +-
- drivers/platform/x86/pcengines-apuv2.c | 118 ++++++++++++++++++++++---
- 3 files changed, 107 insertions(+), 17 deletions(-)
-
---- a/drivers/leds/leds-apu.c
-+++ b/drivers/leds/leds-apu.c
-@@ -183,7 +183,7 @@ static int __init apu_led_init(void)
-
- if (!(dmi_match(DMI_SYS_VENDOR, "PC Engines") &&
- (dmi_match(DMI_PRODUCT_NAME, "APU") || dmi_match(DMI_PRODUCT_NAME, "apu1")))) {
-- pr_err("No PC Engines APUv1 board detected. For APUv2,3 support, enable CONFIG_PCENGINES_APU2\n");
-+ pr_err("No PC Engines APUv1 board detected. For APUv2,3,4,5,6 support, enable CONFIG_PCENGINES_APU2\n");
- return -ENODEV;
- }
-
---- a/drivers/platform/x86/Kconfig
-+++ b/drivers/platform/x86/Kconfig
-@@ -698,7 +698,7 @@ config XO1_RFKILL
- laptop.
-
- config PCENGINES_APU2
-- tristate "PC Engines APUv2/3 front button and LEDs driver"
-+ tristate "PC Engines APUv2/3/4/5/6 front button and LEDs driver"
- depends on INPUT && INPUT_KEYBOARD && GPIOLIB
- depends on LEDS_CLASS
- select GPIO_AMD_FCH
-@@ -706,7 +706,7 @@ config PCENGINES_APU2
- select LEDS_GPIO
- help
- This driver provides support for the front button and LEDs on
-- PC Engines APUv2/APUv3 board.
-+ PC Engines APUv2/APUv3/APUv4/APUv5/APUv6 board.
-
- To compile this driver as a module, choose M here: the module
- will be called pcengines-apuv2.
---- a/drivers/platform/x86/pcengines-apuv2.c
-+++ b/drivers/platform/x86/pcengines-apuv2.c
-@@ -1,10 +1,12 @@
- // SPDX-License-Identifier: GPL-2.0+
-
- /*
-- * PC-Engines APUv2/APUv3 board platform driver
-+ * PC-Engines APUv2-6 board platform driver
- * for GPIO buttons and LEDs
- *
- * Copyright (C) 2018 metux IT consult
-+ * Copyright (C) 2022 Ed Wildgoose <lists@wildgooses.com>
-+ * Copyright (C) 2022 Philip Prindeville <philipp@redfish-solutions.com>
- * Author: Enrico Weigelt <info@metux.net>
- */
-
-@@ -22,38 +24,70 @@
- #include <linux/platform_data/gpio/gpio-amd-fch.h>
-
- /*
-- * NOTE: this driver only supports APUv2/3 - not APUv1, as this one
-+ * NOTE: this driver only supports APUv2-6 - not APUv1, as this one
- * has completely different register layouts.
- */
-
-+/*
-+ * There are a number of APU variants, with differing features
-+ * APU2 has SIM slots 1/2 mapping to mPCIe sockets 1/2
-+ * APU3/4 moved SIM slot 1 to mPCIe socket 3, ie logically reversed
-+ * However, most APU3/4 have a SIM switch which we default on to reverse
-+ * the order and keep physical SIM order matching physical modem order
-+ * APU6 is approximately the same as APU4 with different ethernet layout
-+ *
-+ * APU5 has 3x SIM sockets, all with a SIM switch
-+ * several GPIOs are shuffled (see schematic), including MODESW
-+ */
-+
- /* Register mappings */
- #define APU2_GPIO_REG_LED1 AMD_FCH_GPIO_REG_GPIO57
- #define APU2_GPIO_REG_LED2 AMD_FCH_GPIO_REG_GPIO58
- #define APU2_GPIO_REG_LED3 AMD_FCH_GPIO_REG_GPIO59_DEVSLP1
- #define APU2_GPIO_REG_MODESW AMD_FCH_GPIO_REG_GPIO32_GE1
- #define APU2_GPIO_REG_SIMSWAP AMD_FCH_GPIO_REG_GPIO33_GE2
--#define APU2_GPIO_REG_MPCIE2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
--#define APU2_GPIO_REG_MPCIE3 AMD_FCH_GPIO_REG_GPIO51
-+#define APU2_GPIO_REG_RESETM1 AMD_FCH_GPIO_REG_GPIO51
-+#define APU2_GPIO_REG_RESETM2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
-+
-+#define APU5_GPIO_REG_MODESW AMT_FCH_GPIO_REG_GEVT22
-+#define APU5_GPIO_REG_SIMSWAP1 AMD_FCH_GPIO_REG_GPIO68
-+#define APU5_GPIO_REG_SIMSWAP2 AMD_FCH_GPIO_REG_GPIO32_GE1
-+#define APU5_GPIO_REG_SIMSWAP3 AMD_FCH_GPIO_REG_GPIO33_GE2
-+#define APU5_GPIO_REG_RESETM1 AMD_FCH_GPIO_REG_GPIO51
-+#define APU5_GPIO_REG_RESETM2 AMD_FCH_GPIO_REG_GPIO55_DEVSLP0
-+#define APU5_GPIO_REG_RESETM3 AMD_FCH_GPIO_REG_GPIO64
-
- /* Order in which the GPIO lines are defined in the register list */
- #define APU2_GPIO_LINE_LED1 0
- #define APU2_GPIO_LINE_LED2 1
- #define APU2_GPIO_LINE_LED3 2
- #define APU2_GPIO_LINE_MODESW 3
--#define APU2_GPIO_LINE_SIMSWAP 4
--#define APU2_GPIO_LINE_MPCIE2 5
--#define APU2_GPIO_LINE_MPCIE3 6
-+#define APU2_GPIO_LINE_RESETM1 4
-+#define APU2_GPIO_LINE_RESETM2 5
-+#define APU2_GPIO_LINE_SIMSWAP 6
-+
-+#define APU5_GPIO_LINE_LED1 0
-+#define APU5_GPIO_LINE_LED2 1
-+#define APU5_GPIO_LINE_LED3 2
-+#define APU5_GPIO_LINE_MODESW 3
-+#define APU5_GPIO_LINE_RESETM1 4
-+#define APU5_GPIO_LINE_RESETM2 5
-+#define APU5_GPIO_LINE_RESETM3 6
-+#define APU5_GPIO_LINE_SIMSWAP1 7
-+#define APU5_GPIO_LINE_SIMSWAP2 8
-+#define APU5_GPIO_LINE_SIMSWAP3 9
-+
-
--/* GPIO device */
-+/* GPIO device - APU2/3/4/6 */
-
- static int apu2_gpio_regs[] = {
- [APU2_GPIO_LINE_LED1] = APU2_GPIO_REG_LED1,
- [APU2_GPIO_LINE_LED2] = APU2_GPIO_REG_LED2,
- [APU2_GPIO_LINE_LED3] = APU2_GPIO_REG_LED3,
- [APU2_GPIO_LINE_MODESW] = APU2_GPIO_REG_MODESW,
-+ [APU2_GPIO_LINE_RESETM1] = APU2_GPIO_REG_RESETM1,
-+ [APU2_GPIO_LINE_RESETM2] = APU2_GPIO_REG_RESETM2,
- [APU2_GPIO_LINE_SIMSWAP] = APU2_GPIO_REG_SIMSWAP,
-- [APU2_GPIO_LINE_MPCIE2] = APU2_GPIO_REG_MPCIE2,
-- [APU2_GPIO_LINE_MPCIE3] = APU2_GPIO_REG_MPCIE3,
- };
-
- static const char * const apu2_gpio_names[] = {
-@@ -61,9 +95,9 @@ static const char * const apu2_gpio_name
- [APU2_GPIO_LINE_LED2] = "front-led2",
- [APU2_GPIO_LINE_LED3] = "front-led3",
- [APU2_GPIO_LINE_MODESW] = "front-button",
-+ [APU2_GPIO_LINE_RESETM1] = "modem1-reset",
-+ [APU2_GPIO_LINE_RESETM2] = "modem2-reset",
- [APU2_GPIO_LINE_SIMSWAP] = "simswap",
-- [APU2_GPIO_LINE_MPCIE2] = "mpcie2_reset",
-- [APU2_GPIO_LINE_MPCIE3] = "mpcie3_reset",
- };
-
- static const struct amd_fch_gpio_pdata board_apu2 = {
-@@ -72,6 +106,40 @@ static const struct amd_fch_gpio_pdata b
- .gpio_names = apu2_gpio_names,
- };
-
-+/* GPIO device - APU5 */
-+
-+static int apu5_gpio_regs[] = {
-+ [APU5_GPIO_LINE_LED1] = APU2_GPIO_REG_LED1,
-+ [APU5_GPIO_LINE_LED2] = APU2_GPIO_REG_LED2,
-+ [APU5_GPIO_LINE_LED3] = APU2_GPIO_REG_LED3,
-+ [APU5_GPIO_LINE_MODESW] = APU5_GPIO_REG_MODESW,
-+ [APU5_GPIO_LINE_RESETM1] = APU5_GPIO_REG_RESETM1,
-+ [APU5_GPIO_LINE_RESETM2] = APU5_GPIO_REG_RESETM2,
-+ [APU5_GPIO_LINE_RESETM3] = APU5_GPIO_REG_RESETM3,
-+ [APU5_GPIO_LINE_SIMSWAP1] = APU5_GPIO_REG_SIMSWAP1,
-+ [APU5_GPIO_LINE_SIMSWAP2] = APU5_GPIO_REG_SIMSWAP2,
-+ [APU5_GPIO_LINE_SIMSWAP3] = APU5_GPIO_REG_SIMSWAP3,
-+};
-+
-+static const char * const apu5_gpio_names[] = {
-+ [APU5_GPIO_LINE_LED1] = "front-led1",
-+ [APU5_GPIO_LINE_LED2] = "front-led2",
-+ [APU5_GPIO_LINE_LED3] = "front-led3",
-+ [APU5_GPIO_LINE_MODESW] = "front-button",
-+ [APU5_GPIO_LINE_RESETM1] = "modem1-reset",
-+ [APU5_GPIO_LINE_RESETM2] = "modem2-reset",
-+ [APU5_GPIO_LINE_RESETM3] = "modem3-reset",
-+ [APU5_GPIO_LINE_SIMSWAP1] = "simswap1",
-+ [APU5_GPIO_LINE_SIMSWAP2] = "simswap2",
-+ [APU5_GPIO_LINE_SIMSWAP3] = "simswap3",
-+};
-+
-+static const struct amd_fch_gpio_pdata board_apu5 = {
-+ .gpio_num = ARRAY_SIZE(apu5_gpio_regs),
-+ .gpio_reg = apu5_gpio_regs,
-+ .gpio_names = apu5_gpio_names,
-+};
-+
- /* GPIO LEDs device */
-
- static const struct gpio_led apu2_leds[] = {
-@@ -215,6 +283,24 @@ static const struct dmi_system_id apu_gp
- },
- .driver_data = (void *)&board_apu2,
- },
-+ /* APU5 w/ mainline BIOS */
-+ {
-+ .ident = "apu5",
-+ .matches = {
-+ DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
-+ DMI_MATCH(DMI_BOARD_NAME, "apu5")
-+ },
-+ .driver_data = (void *)&board_apu5,
-+ },
-+ /* APU6 w/ mainline BIOS */
-+ {
-+ .ident = "apu6",
-+ .matches = {
-+ DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
-+ DMI_MATCH(DMI_BOARD_NAME, "apu6")
-+ },
-+ .driver_data = (void *)&board_apu2,
-+ },
- {}
- };
-
-@@ -249,7 +335,7 @@ static int __init apu_board_init(void)
-
- id = dmi_first_match(apu_gpio_dmi_table);
- if (!id) {
-- pr_err("failed to detect APU board via DMI\n");
-+ pr_err("No APU board detected via DMI\n");
- return -ENODEV;
- }
-
-@@ -288,8 +374,12 @@ module_init(apu_board_init);
- module_exit(apu_board_exit);
-
- MODULE_AUTHOR("Enrico Weigelt, metux IT consult <info@metux.net>");
--MODULE_DESCRIPTION("PC Engines APUv2/APUv3 board GPIO/LEDs/keys driver");
-+MODULE_DESCRIPTION("PC Engines APUv2-6 board GPIO/LEDs/keys driver");
- MODULE_LICENSE("GPL");
- MODULE_DEVICE_TABLE(dmi, apu_gpio_dmi_table);
- MODULE_ALIAS("platform:pcengines-apuv2");
-+MODULE_ALIAS("platform:pcengines-apuv3");
-+MODULE_ALIAS("platform:pcengines-apuv4");
-+MODULE_ALIAS("platform:pcengines-apuv5");
-+MODULE_ALIAS("platform:pcengines-apuv6");
- MODULE_SOFTDEP("pre: platform:" AMD_FCH_GPIO_DRIVER_NAME " platform:leds-gpio platform:gpio_keys_polled");
default "11.3.0" if GCC_VERSION_11
default "12.3.0" if GCC_VERSION_12
default "14.1.0" if GCC_VERSION_14
- default "13.2.0"
+ default "13.3.0"
config GCC_USE_DEFAULT_VERSION
bool
PKG_HASH:=949a5d4f99e786421a93b532b22ffab5578de7321369975b91aec97adfda8c3b
endif
-ifeq ($(PKG_VERSION),13.2.0)
- PKG_HASH:=e275e76442a6067341a27f04c5c6b83d8613144004c0413528863dc6b5c743da
+ifeq ($(PKG_VERSION),13.3.0)
+ PKG_HASH:=0845e9621c9543a13f484e94584a49ffc0129970e9914624235fc1d061a0c083
endif
ifeq ($(PKG_VERSION),14.1.0)
+++ /dev/null
-From 9970b576b7e4ae337af1268395ff221348c4b34a Mon Sep 17 00:00:00 2001
-From: Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
-Date: Thu, 7 Mar 2024 14:36:03 +0100
-Subject: [PATCH] Include safe-ctype.h after C++ standard headers, to avoid
- over-poisoning
-
-When building gcc's C++ sources against recent libc++, the poisoning of
-the ctype macros due to including safe-ctype.h before including C++
-standard headers such as <list>, <map>, etc, causes many compilation
-errors, similar to:
-
- In file included from /home/dim/src/gcc/master/gcc/gensupport.cc:23:
- In file included from /home/dim/src/gcc/master/gcc/system.h:233:
- In file included from /usr/include/c++/v1/vector:321:
- In file included from
- /usr/include/c++/v1/__format/formatter_bool.h:20:
- In file included from
- /usr/include/c++/v1/__format/formatter_integral.h:32:
- In file included from /usr/include/c++/v1/locale:202:
- /usr/include/c++/v1/__locale:546:5: error: '__abi_tag__' attribute
- only applies to structs, variables, functions, and namespaces
- 546 | _LIBCPP_INLINE_VISIBILITY
- | ^
- /usr/include/c++/v1/__config:813:37: note: expanded from macro
- '_LIBCPP_INLINE_VISIBILITY'
- 813 | # define _LIBCPP_INLINE_VISIBILITY _LIBCPP_HIDE_FROM_ABI
- | ^
- /usr/include/c++/v1/__config:792:26: note: expanded from macro
- '_LIBCPP_HIDE_FROM_ABI'
- 792 |
- __attribute__((__abi_tag__(_LIBCPP_TOSTRING(
- _LIBCPP_VERSIONED_IDENTIFIER))))
- | ^
- In file included from /home/dim/src/gcc/master/gcc/gensupport.cc:23:
- In file included from /home/dim/src/gcc/master/gcc/system.h:233:
- In file included from /usr/include/c++/v1/vector:321:
- In file included from
- /usr/include/c++/v1/__format/formatter_bool.h:20:
- In file included from
- /usr/include/c++/v1/__format/formatter_integral.h:32:
- In file included from /usr/include/c++/v1/locale:202:
- /usr/include/c++/v1/__locale:547:37: error: expected ';' at end of
- declaration list
- 547 | char_type toupper(char_type __c) const
- | ^
- /usr/include/c++/v1/__locale:553:48: error: too many arguments
- provided to function-like macro invocation
- 553 | const char_type* toupper(char_type* __low, const
- char_type* __high) const
- | ^
- /home/dim/src/gcc/master/gcc/../include/safe-ctype.h:146:9: note:
- macro 'toupper' defined here
- 146 | #define toupper(c) do_not_use_toupper_with_safe_ctype
- | ^
-
-This is because libc++ uses different transitive includes than
-libstdc++, and some of those transitive includes pull in various ctype
-declarations (typically via <locale>).
-
-There was already a special case for including <string> before
-safe-ctype.h, so move the rest of the C++ standard header includes to
-the same location, to fix the problem.
-
-gcc/ChangeLog:
-
- * system.h: Include safe-ctype.h after C++ standard headers.
-
-Signed-off-by: Dimitry Andric <dimitry@andric.com>
----
- gcc/system.h | 39 ++++++++++++++++++---------------------
- 1 file changed, 18 insertions(+), 21 deletions(-)
-
-diff --git a/gcc/system.h b/gcc/system.h
-index b0edab02885..ab29fc19776 100644
---- a/gcc/system.h
-+++ b/gcc/system.h
-@@ -194,27 +194,8 @@ extern int fprintf_unlocked (FILE *, const char *, ...);
- #undef fread_unlocked
- #undef fwrite_unlocked
-
--/* Include <string> before "safe-ctype.h" to avoid GCC poisoning
-- the ctype macros through safe-ctype.h */
--
--#ifdef __cplusplus
--#ifdef INCLUDE_STRING
--# include <string>
--#endif
--#endif
--
--/* There are an extraordinary number of issues with <ctype.h>.
-- The last straw is that it varies with the locale. Use libiberty's
-- replacement instead. */
--#include "safe-ctype.h"
--
--#include <sys/types.h>
--
--#include <errno.h>
--
--#if !defined (errno) && defined (HAVE_DECL_ERRNO) && !HAVE_DECL_ERRNO
--extern int errno;
--#endif
-+/* Include C++ standard headers before "safe-ctype.h" to avoid GCC
-+ poisoning the ctype macros through safe-ctype.h */
-
- #ifdef __cplusplus
- #if defined (INCLUDE_ALGORITHM) || !defined (HAVE_SWAP_IN_UTILITY)
-@@ -229,6 +210,9 @@ extern int errno;
- #ifdef INCLUDE_SET
- # include <set>
- #endif
-+#ifdef INCLUDE_STRING
-+# include <string>
-+#endif
- #ifdef INCLUDE_VECTOR
- # include <vector>
- #endif
-@@ -245,6 +229,19 @@ extern int errno;
- # include <type_traits>
- #endif
-
-+/* There are an extraordinary number of issues with <ctype.h>.
-+ The last straw is that it varies with the locale. Use libiberty's
-+ replacement instead. */
-+#include "safe-ctype.h"
-+
-+#include <sys/types.h>
-+
-+#include <errno.h>
-+
-+#if !defined (errno) && defined (HAVE_DECL_ERRNO) && !HAVE_DECL_ERRNO
-+extern int errno;
-+#endif
-+
- /* Some of glibc's string inlines cause warnings. Plus we'd rather
- rely on (and therefore test) GCC's string builtins. */
- #define __NO_STRING_INLINES
---
-2.39.3
-
+++ /dev/null
-From 5213047b1d50af63dfabb5e5649821a6cb157e33 Mon Sep 17 00:00:00 2001
-From: Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
-Date: Sat, 16 Mar 2024 09:50:00 +0100
-Subject: [PATCH] libcc1: fix <vector> include
-
-Use INCLUDE_VECTOR before including system.h, instead of directly
-including <vector>, to avoid running into poisoned identifiers.
-
-Signed-off-by: Dimitry Andric <dimitry@andric.com>
-
-libcc1/ChangeLog:
-
- PR middle-end/111632
- * libcc1plugin.cc: Fix include.
- * libcp1plugin.cc: Fix include.
----
- libcc1/libcc1plugin.cc | 3 +--
- libcc1/libcp1plugin.cc | 3 +--
- 2 files changed, 2 insertions(+), 4 deletions(-)
-
-diff --git a/libcc1/libcc1plugin.cc b/libcc1/libcc1plugin.cc
-index 72d17c3b81c..e64847466f4 100644
---- a/libcc1/libcc1plugin.cc
-+++ b/libcc1/libcc1plugin.cc
-@@ -32,6 +32,7 @@
- #undef PACKAGE_VERSION
-
- #define INCLUDE_MEMORY
-+#define INCLUDE_VECTOR
- #include "gcc-plugin.h"
- #include "system.h"
- #include "coretypes.h"
-@@ -69,8 +70,6 @@
- #include "gcc-c-interface.h"
- #include "context.hh"
-
--#include <vector>
--
- using namespace cc1_plugin;
-
- \f
-diff --git a/libcc1/libcp1plugin.cc b/libcc1/libcp1plugin.cc
-index 0eff7c68d29..da68c5d0ac1 100644
---- a/libcc1/libcp1plugin.cc
-+++ b/libcc1/libcp1plugin.cc
-@@ -33,6 +33,7 @@
- #undef PACKAGE_VERSION
-
- #define INCLUDE_MEMORY
-+#define INCLUDE_VECTOR
- #include "gcc-plugin.h"
- #include "system.h"
- #include "coretypes.h"
-@@ -71,8 +72,6 @@
- #include "rpc.hh"
- #include "context.hh"
-
--#include <vector>
--
- using namespace cc1_plugin;
-
- \f
---
-2.39.3
-
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
-@@ -20213,7 +20213,7 @@ mips_option_override (void)
+@@ -20219,7 +20219,7 @@ mips_option_override (void)
flag_pcc_struct_return = 0;
/* Decide which rtx_costs structure to use. */
+++ /dev/null
-From a80c68a08604b0ac625ac7fc59eae40b551b1176 Mon Sep 17 00:00:00 2001
-From: Peng Fan <fanpeng@loongson.cn>
-Date: Wed, 19 Apr 2023 16:23:42 +0800
-Subject: [PATCH] LoongArch: Fix MUSL_DYNAMIC_LINKER
-
-The system based on musl has no '/lib64', so change it.
-
-https://wiki.musl-libc.org/guidelines-for-distributions.html,
-"Multilib/multi-arch" section of this introduces it.
-
-gcc/
- * config/loongarch/gnu-user.h (MUSL_DYNAMIC_LINKER): Redefine.
-
-Signed-off-by: Peng Fan <fanpeng@loongson.cn>
-Suggested-by: Xi Ruoyao <xry111@xry111.site>
----
- gcc/config/loongarch/gnu-user.h | 7 ++++++-
- 1 file changed, 6 insertions(+), 1 deletion(-)
-
-diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h
-index aecaa02a199..fa1a5211419 100644
---- a/gcc/config/loongarch/gnu-user.h
-+++ b/gcc/config/loongarch/gnu-user.h
-@@ -33,9 +33,14 @@ along with GCC; see the file COPYING3. If not see
- #define GLIBC_DYNAMIC_LINKER \
- "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1"
-
-+#define MUSL_ABI_SPEC \
-+ "%{mabi=lp64d:-lp64d}" \
-+ "%{mabi=lp64f:-lp64f}" \
-+ "%{mabi=lp64s:-lp64s}"
-+
- #undef MUSL_DYNAMIC_LINKER
- #define MUSL_DYNAMIC_LINKER \
-- "/lib" ABI_GRLEN_SPEC "/ld-musl-loongarch-" ABI_SPEC ".so.1"
-+ "/lib/ld-musl-loongarch" ABI_GRLEN_SPEC MUSL_ABI_SPEC ".so.1"
-
- #undef GNU_USER_TARGET_LINK_SPEC
- #define GNU_USER_TARGET_LINK_SPEC \
---
-2.39.3
+++ /dev/null
-From 8bccee51f0deac64b79cd9ad75df599422f4c8ff Mon Sep 17 00:00:00 2001
-From: Lulu Cheng <chenglulu@loongson.cn>
-Date: Sat, 18 Nov 2023 11:04:42 +0800
-Subject: [PATCH] LoongArch: Modify MUSL_DYNAMIC_LINKER.
-
-Use no suffix at all in the musl dynamic linker name for hard
-float ABI. Use -sf and -sp suffixes in musl dynamic linker name
-for soft float and single precision ABIs. The following table
-outlines the musl interpreter names for the LoongArch64 ABI names.
-
-musl interpreter | LoongArch64 ABI
---------------------------- | -----------------
-ld-musl-loongarch64.so.1 | loongarch64-lp64d
-ld-musl-loongarch64-sp.so.1 | loongarch64-lp64f
-ld-musl-loongarch64-sf.so.1 | loongarch64-lp64s
-
-gcc/ChangeLog:
-
- * config/loongarch/gnu-user.h (MUSL_ABI_SPEC): Modify suffix.
----
- gcc/config/loongarch/gnu-user.h | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/gcc/config/loongarch/gnu-user.h b/gcc/config/loongarch/gnu-user.h
-index 9616d6e8a0b..e9f4bcef1d4 100644
---- a/gcc/config/loongarch/gnu-user.h
-+++ b/gcc/config/loongarch/gnu-user.h
-@@ -34,9 +34,9 @@ along with GCC; see the file COPYING3. If not see
- "/lib" ABI_GRLEN_SPEC "/ld-linux-loongarch-" ABI_SPEC ".so.1"
-
- #define MUSL_ABI_SPEC \
-- "%{mabi=lp64d:-lp64d}" \
-- "%{mabi=lp64f:-lp64f}" \
-- "%{mabi=lp64s:-lp64s}"
-+ "%{mabi=lp64d:}" \
-+ "%{mabi=lp64f:-sp}" \
-+ "%{mabi=lp64s:-sf}"
-
- #undef MUSL_DYNAMIC_LINKER
- #define MUSL_DYNAMIC_LINKER \
---
-2.39.3
-
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
-@@ -1185,7 +1185,7 @@ extern enum aarch64_code_model aarch64_c
+@@ -1195,7 +1195,7 @@ extern enum aarch64_code_model aarch64_c
/* Extra specs when building a native AArch64-hosted compiler.
Option rewriting rules based on host system. */
---- elftosb-10.12.01/makefile.rules 2012-03-15 11:01:44.979020178 -0400
-+++ elftosb-10.12.01/makefile.rules 2012-03-15 11:01:16.332761989 -0400
-@@ -101,7 +101,7 @@
+--- a/makefile.rules
++++ b/makefile.rules
+@@ -101,7 +101,7 @@ OBJ_FILES_KEYGEN = \
keygen.o
This patch makes the types a relative path, and allows the system
to use whatever include paths it feels are correct.
-diff -Naurp elftosb-10.12.01-orig/common/stdafx.h elftosb-10.12.01/common/stdafx.h
---- elftosb-10.12.01-orig/common/stdafx.h 2012-07-12 13:30:10.990249396 -0400
-+++ elftosb-10.12.01/common/stdafx.h 2012-07-12 13:30:06.858249391 -0400
+--- a/common/stdafx.h
++++ b/common/stdafx.h
@@ -27,7 +27,7 @@
// For Linux systems only, types.h only defines the signed
// integer types. This is not professional code.
PKG_FIXUP:=autoreconf
PKG_INSTALL:=1
+PKG_PROGRAMS:=elflint findtextrel elfcmp unstrip stack elfcompress elfclassify srcfiles
+
PKG_SUBDIRS := \
libgnu \
config \
libebl \
libdwelf \
libdwfl \
- libdw
+ libdw \
+ src
PKG_GNULIB_BASE:=libgnu
PKG_GNULIB_MODS = \
argp \
+ fnmatch-gnu \
fts \
obstack \
progname \
include $(INCLUDE_DIR)/host-build.mk
+export $(PKG_GNULIB_BASE)=$(HOST_BUILD_DIR)/$(PKG_GNULIB_BASE)/$(PKG_GNULIB_BASE).la
+export $(PKG_GNULIB_BASE)_tsearch=$(HOST_BUILD_DIR)/$(PKG_GNULIB_BASE)/$(PKG_GNULIB_BASE)_la-tsearch.lo
+
+HOST_MAKE_FLAGS += \
+ AM_LDFLAGS='$$$$(STACK_USAGE_NO_ERROR)' \
+ LIBS+='$$$$(if $$$$(findstring $(lastword $(PKG_SUBDIRS)),$$$$(subdir)), $$$$($(PKG_GNULIB_BASE)))' \
+ LIBS+='$$$$(wildcard $$$$($(PKG_GNULIB_BASE)_tsearch))' \
+ REPLACE_FCNTL=0 REPLACE_FREE=0 REPLACE_FSTAT=0 REPLACE_OPEN=0 \
+ bin_PROGRAMS='$(PKG_PROGRAMS)' EXEEXT=
+
ifeq ($(HOST_OS),Darwin)
HOST_CFLAGS += -I/opt/homebrew/include
endif
HOST_CFLAGS += -Wno-error -fPIC
+HOST_CXXFLAGS += -O2
HOST_CONFIGURE_ARGS += \
--without-libintl-prefix \
pkginclude_HEADERS = elf-knowledge.h
-libelf_a_SOURCES = elf_version.c elf_hash.c elf_error.c elf_fill.c \
-+libelf_la_LIBADD = ../libgnu/libgnu.la ../lib/libeu.la -lz $(zstd_LIBS) -lpthread
++libelf_la_LIBADD = ../lib/libeu.la -lz $(zstd_LIBS) -lpthread
+libelf_la_SOURCES = elf_version.c elf_hash.c elf_error.c \
elf_begin.c elf_next.c elf_rand.c elf_end.c elf_kind.c \
gelf_getclass.c elf_getbase.c elf_getident.c \
#include <stddef.h>
+--- a/libebl/eblopenbackend.c
++++ b/libebl/eblopenbackend.c
+@@ -198,8 +198,6 @@ static bool default_object_note (const c
+ uint32_t descsz, const char *desc);
+ static bool default_debugscn_p (const char *name);
+ static bool default_copy_reloc_p (int reloc);
+-static bool default_none_reloc_p (int reloc);
+-static bool default_relative_reloc_p (int reloc);
+ static bool default_check_special_symbol (Elf *elf,
+ const GElf_Sym *sym,
+ const char *name,
+@@ -251,8 +249,8 @@ fill_defaults (Ebl *result)
+ result->object_note = default_object_note;
+ result->debugscn_p = default_debugscn_p;
+ result->copy_reloc_p = default_copy_reloc_p;
+- result->none_reloc_p = default_none_reloc_p;
+- result->relative_reloc_p = default_relative_reloc_p;
++ result->none_reloc_p = default_copy_reloc_p;
++ result->relative_reloc_p = default_copy_reloc_p;
+ result->check_special_symbol = default_check_special_symbol;
+ result->data_marker_symbol = default_data_marker_symbol;
+ result->check_st_other_bits = default_check_st_other_bits;
+@@ -634,8 +632,6 @@ default_copy_reloc_p (int reloc __attrib
+ {
+ return false;
+ }
+-strong_alias (default_copy_reloc_p, default_none_reloc_p)
+-strong_alias (default_copy_reloc_p, default_relative_reloc_p)
+
+ static bool
+ default_check_special_symbol (Elf *elf __attribute__ ((unused)),
+--- a/src/srcfiles.cxx
++++ b/src/srcfiles.cxx
+@@ -78,7 +78,9 @@ ARGP_PROGRAM_VERSION_HOOK_DEF = print_ve
+ /* Bug report address. */
+ ARGP_PROGRAM_BUG_ADDRESS_DEF = PACKAGE_BUGREPORT;
+
++#ifdef HAVE_LIBARCHIVE
+ constexpr size_t BUFFER_SIZE = 8192;
++#endif
+
+ /* Definitions of arguments for argp functions. */
+ static const struct argp_option options[] =
--- /dev/null
+--- /dev/null
++++ b/lib/fts.h
+@@ -0,0 +1,6 @@
++#ifdef __APPLE__
++# define _FTS_H_ 1
++# include <fts_.h>
++#else
++# include_next <fts.h>
++#endif
+--- a/modules/fts
++++ b/modules/fts
+@@ -2,6 +2,7 @@ Description:
+ Traverse a file hierarchy.
+
+ Files:
++lib/fts.h
+ lib/fts_.h
+ lib/fts.c
+ lib/fts-cycle.c
---- a/CMakeLists.txt 2022-11-28 06:34:39.171209779 -0800
-+++ b/CMakeLists.txt 2022-11-28 06:33:13.368239757 -0800
-@@ -51,8 +51,11 @@
+--- a/CMakeLists.txt
++++ b/CMakeLists.txt
+@@ -51,8 +51,11 @@ endif()
project(lzo VERSION 2.10 LANGUAGES C)
# configuration options
if(NOT ENABLE_STATIC AND NOT ENABLE_SHARED)
set(ENABLE_STATIC ON)
endif()
-@@ -127,14 +130,20 @@
+@@ -127,14 +130,20 @@ macro(lzo_add_executable t)
endif()
endmacro()
# main test driver
# some boring internal test programs
if(0)
lzo_add_executable(align tests/align.c)
-@@ -144,7 +153,7 @@
+@@ -144,7 +153,7 @@ if(0)
endif()
# miniLZO
add_executable(testmini minilzo/testmini.c minilzo/minilzo.c)
target_include_directories(testmini PRIVATE "${CMAKE_CURRENT_SOURCE_DIR}/include/lzo") # needed for "lzoconf.h"
endif()
-@@ -263,8 +272,10 @@
+@@ -263,8 +272,10 @@ add_test(NAME lzotest-03 COMMAND lzotest
if(DEFINED CMAKE_INSTALL_FULL_LIBDIR)
set(f include/lzo/lzo1.h include/lzo/lzo1a.h include/lzo/lzo1b.h
include/lzo/lzo1c.h include/lzo/lzo1f.h include/lzo/lzo1x.h
-@@ -285,7 +296,7 @@
+@@ -285,7 +296,7 @@ if(ENABLE_SHARED)
)
endif()
+++ /dev/null
-+++ a/programs/Makefile 2022-08-15 15:45:31.000000000 -0700
---- b/programs/Makefile 2022-11-28 16:34:21.315593784 -0800
-@@ -66,6 +66,7 @@
- MD2ROFF = ronn
- MD2ROFF_FLAGS = --roff --warnings --manual="User Commands" --organization="lz4 $(LZ4_VERSION)"
-
-+ENABLE_DOCS ?= 1
-
- default: lz4-release
-
-@@ -120,6 +121,7 @@
- lz4c32 : $(SRCFILES)
- $(CC) $(FLAGS) $^ -o $@$(EXT)
-
-+ifeq ($(ENABLE_DOCS),1)
- lz4.1: lz4.1.md $(LIBVER_SRC)
- cat $< | $(MD2ROFF) $(MD2ROFF_FLAGS) | $(SED) -n '/^\.\\\".*/!p' > $@
-
-@@ -130,6 +132,7 @@
-
- preview-man: clean-man man
- man ./lz4.1
-+endif
-
- clean:
- ifeq ($(WINBASED),yes)
-@@ -172,16 +175,19 @@
-
- install: lz4
- @echo Installing binaries in $(DESTDIR)$(bindir)
-- $(INSTALL_DIR) $(DESTDIR)$(bindir)/ $(DESTDIR)$(man1dir)/
-+ $(INSTALL_DIR) $(DESTDIR)$(bindir)/
- $(INSTALL_PROGRAM) lz4$(EXT) $(DESTDIR)$(bindir)/lz4$(EXT)
- $(LN_SF) lz4$(EXT) $(DESTDIR)$(bindir)/lz4c$(EXT)
- $(LN_SF) lz4$(EXT) $(DESTDIR)$(bindir)/lz4cat$(EXT)
- $(LN_SF) lz4$(EXT) $(DESTDIR)$(bindir)/unlz4$(EXT)
-+ifeq ($(ENABLE_DOCS),1)
- @echo Installing man pages in $(DESTDIR)$(man1dir)
-+ $(INSTALL_DIR) $(DESTDIR)$(man1dir)/
- $(INSTALL_DATA) lz4.1 $(DESTDIR)$(man1dir)/lz4.1
- $(LN_SF) lz4.1 $(DESTDIR)$(man1dir)/lz4c.1
- $(LN_SF) lz4.1 $(DESTDIR)$(man1dir)/lz4cat.1
- $(LN_SF) lz4.1 $(DESTDIR)$(man1dir)/unlz4.1
-+endif
- @echo lz4 installation completed
-
- uninstall:
-@@ -189,10 +195,12 @@
- $(RM) $(DESTDIR)$(bindir)/unlz4$(EXT)
- $(RM) $(DESTDIR)$(bindir)/lz4$(EXT)
- $(RM) $(DESTDIR)$(bindir)/lz4c$(EXT)
-+ifeq ($(ENABLE_DOCS),1)
- $(RM) $(DESTDIR)$(man1dir)/lz4.1
- $(RM) $(DESTDIR)$(man1dir)/lz4c.1
- $(RM) $(DESTDIR)$(man1dir)/lz4cat.1
- $(RM) $(DESTDIR)$(man1dir)/unlz4.1
-+endif
- @echo lz4 programs successfully uninstalled
-
- endif
+++ /dev/null
-diff -ur a/lib/Makefile b/lib/Makefile
---- a/lib/Makefile 2022-12-04 23:49:06.336839263 -0800
-+++ b/lib/Makefile 2022-12-05 00:00:59.172307488 -0800
-@@ -195,8 +195,8 @@
- $(INSTALL_PROGRAM) dll/$(LIBLZ4_EXP) $(DESTDIR)$(libdir)
- else
- $(INSTALL_PROGRAM) liblz4.$(SHARED_EXT_VER) $(DESTDIR)$(libdir)
-- $(LN_SF) liblz4.$(SHARED_EXT_VER) $(DESTDIR)$(libdir)/liblz4.$(SHARED_EXT_MAJOR)
-- $(LN_SF) liblz4.$(SHARED_EXT_VER) $(DESTDIR)$(libdir)/liblz4.$(SHARED_EXT)
-+ (cd $(DESTDIR)$(libdir) && $(LN_SF) liblz4.$(SHARED_EXT_VER) liblz4.$(SHARED_EXT_MAJOR))
-+ (cd $(DESTDIR)$(libdir) && $(LN_SF) liblz4.$(SHARED_EXT_MAJOR) liblz4.$(SHARED_EXT))
- endif
- endif
- @echo Installing headers in $(DESTDIR)$(includedir)
-diff -ur a/Makefile b/Makefile
---- a/Makefile 2022-12-04 23:49:06.336839263 -0800
-+++ b/Makefile 2022-12-04 23:42:09.693836654 -0800
-@@ -77,12 +77,12 @@
-
- .PHONY: clean
- clean:
-- $(MAKE) -C $(LZ4DIR) $@ > $(VOID)
-- $(MAKE) -C $(PRGDIR) $@ > $(VOID)
-- $(MAKE) -C $(TESTDIR) $@ > $(VOID)
-- $(MAKE) -C $(EXDIR) $@ > $(VOID)
-- $(MAKE) -C $(FUZZDIR) $@ > $(VOID)
-- $(MAKE) -C contrib/gen_manual $@ > $(VOID)
-+ $(MAKE) -C $(LZ4DIR) $@
-+ $(MAKE) -C $(PRGDIR) $@
-+ $(MAKE) -C $(TESTDIR) $@
-+ $(MAKE) -C $(EXDIR) $@
-+ $(MAKE) -C $(FUZZDIR) $@
-+ $(MAKE) -C contrib/gen_manual $@
- $(RM) lz4$(EXT)
- $(RM) -r $(CMAKE_BUILD_DIR)
- @echo Cleaning completed
-diff -ur a/programs/Makefile b/programs/Makefile
---- a/programs/Makefile 2022-12-04 23:49:06.336839263 -0800
-+++ b/programs/Makefile 2022-12-04 23:42:30.849582910 -0800
-@@ -138,7 +138,7 @@
- ifeq ($(WINBASED),yes)
- $(RM) *.rc
- endif
-- $(MAKE) -C $(LZ4DIR) $@ > $(VOID)
-+ $(MAKE) -C $(LZ4DIR) $@
- $(RM) core *.o *.test tmp* \
- lz4$(EXT) lz4c$(EXT) lz4c32$(EXT) lz4-wlib$(EXT) \
- unlz4$(EXT) lz4cat$(EXT)
-@@ -177,16 +177,16 @@
- @echo Installing binaries in $(DESTDIR)$(bindir)
- $(INSTALL_DIR) $(DESTDIR)$(bindir)/
- $(INSTALL_PROGRAM) lz4$(EXT) $(DESTDIR)$(bindir)/lz4$(EXT)
-- $(LN_SF) lz4$(EXT) $(DESTDIR)$(bindir)/lz4c$(EXT)
-- $(LN_SF) lz4$(EXT) $(DESTDIR)$(bindir)/lz4cat$(EXT)
-- $(LN_SF) lz4$(EXT) $(DESTDIR)$(bindir)/unlz4$(EXT)
-+ (cd $(DESTDIR)$(bindir) && $(LN_SF) lz4$(EXT) lz4c$(EXT))
-+ (cd $(DESTDIR)$(bindir) && $(LN_SF) lz4$(EXT) lz4cat$(EXT))
-+ (cd $(DESTDIR)$(bindir) && $(LN_SF) lz4$(EXT) unlz4$(EXT))
- ifeq ($(ENABLE_DOCS),1)
- @echo Installing man pages in $(DESTDIR)$(man1dir)
- $(INSTALL_DIR) $(DESTDIR)$(man1dir)/
- $(INSTALL_DATA) lz4.1 $(DESTDIR)$(man1dir)/lz4.1
-- $(LN_SF) lz4.1 $(DESTDIR)$(man1dir)/lz4c.1
-- $(LN_SF) lz4.1 $(DESTDIR)$(man1dir)/lz4cat.1
-- $(LN_SF) lz4.1 $(DESTDIR)$(man1dir)/unlz4.1
-+ (cd $(DESTDIR)$(man1dir) && $(LN_SF) lz4.1 lz4c.1)
-+ (cd $(DESTDIR)$(man1dir) && $(LN_SF) lz4.1 lz4cat.1)
-+ (cd $(DESTDIR)$(man1dir) && $(LN_SF) lz4.1 unlz4.1)
- endif
- @echo lz4 installation completed
-
-Index: lzma-4.65/CPP/7zip/Compress/LZMA_Alone/makefile.gcc
-===================================================================
---- lzma-4.65.orig/CPP/7zip/Compress/LZMA_Alone/makefile.gcc 2009-05-15 23:33:51.000000000 +0200
-+++ lzma-4.65/CPP/7zip/Compress/LZMA_Alone/makefile.gcc 2009-06-01 22:00:54.000000000 +0200
-@@ -3,7 +3,7 @@
+--- a/CPP/7zip/Compress/LZMA_Alone/makefile.gcc
++++ b/CPP/7zip/Compress/LZMA_Alone/makefile.gcc
+@@ -3,7 +3,7 @@ CXX = g++ -O2 -Wall
CXX_C = gcc -O2 -Wall
LIB = -lm
RM = rm -f
-Index: lzma-4.65/CPP/7zip/Compress/LZMA_Alone/lzmp.cpp
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ lzma-4.65/CPP/7zip/Compress/LZMA_Alone/lzmp.cpp 2009-06-01 22:01:10.000000000 +0200
+--- /dev/null
++++ b/CPP/7zip/Compress/LZMA_Alone/lzmp.cpp
@@ -0,0 +1,895 @@
+/*
+ * LZMA command line tool similar to gzip to encode and decode LZMA files.
+ return STATUS_OK;
+}
+
-Index: lzma-4.65/CPP/7zip/Compress/LZMA_Alone/Exception.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ lzma-4.65/CPP/7zip/Compress/LZMA_Alone/Exception.h 2009-06-01 22:01:10.000000000 +0200
+--- /dev/null
++++ b/CPP/7zip/Compress/LZMA_Alone/Exception.h
@@ -0,0 +1,45 @@
+/* A couple of exceptions for lzmp.
+ *
+
+#endif
+
-Index: lzma-4.65/CPP/7zip/Compress/LZMA_Alone/makefile.gcc
-===================================================================
---- lzma-4.65.orig/CPP/7zip/Compress/LZMA_Alone/makefile.gcc 2009-06-01 22:00:54.000000000 +0200
-+++ lzma-4.65/CPP/7zip/Compress/LZMA_Alone/makefile.gcc 2009-06-01 22:06:13.000000000 +0200
+--- a/CPP/7zip/Compress/LZMA_Alone/makefile.gcc
++++ b/CPP/7zip/Compress/LZMA_Alone/makefile.gcc
@@ -1,9 +1,10 @@
-PROG = lzma
+PROG = lzma_alone
ifdef SystemDrive
IS_MINGW = 1
-@@ -45,12 +46,35 @@
+@@ -45,12 +46,35 @@ OBJS = \
Lzma86Dec.o \
Lzma86Enc.o \
LzmaAlone.o: LzmaAlone.cpp
$(CXX) $(CFLAGS) LzmaAlone.cpp
-@@ -131,5 +153,5 @@
+@@ -131,5 +155,5 @@ Lzma86Enc.o: ../../../../C/LzmaUtil/Lzma
$(CXX_C) $(CFLAGS) ../../../../C/LzmaUtil/Lzma86Enc.c
clean:
- -$(RM) $(PROG) $(OBJS)
+ -$(RM) $(PROG) $(PROG2) $(OBJS)
-Index: lzma-4.65/CPP/7zip/Compress/LZMA_Alone/lzma_version.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ lzma-4.65/CPP/7zip/Compress/LZMA_Alone/lzma_version.h 2009-06-01 22:01:10.000000000 +0200
+--- /dev/null
++++ b/CPP/7zip/Compress/LZMA_Alone/lzma_version.h
@@ -0,0 +1,31 @@
+#ifndef LZMA_VERSION_H
+#define LZMA_VERSION_H
+ "named COPYING.\n";
+
+#endif /* ifndef LZMA_VERSION_H */
-Index: lzma-4.65/CPP/Common/C_FileIO.h
-===================================================================
---- lzma-4.65.orig/CPP/Common/C_FileIO.h 2009-05-15 23:33:51.000000000 +0200
-+++ lzma-4.65/CPP/Common/C_FileIO.h 2009-06-01 22:06:56.000000000 +0200
-@@ -24,6 +24,7 @@
+--- a/CPP/Common/C_FileIO.h
++++ b/CPP/Common/C_FileIO.h
+@@ -24,6 +24,7 @@ public:
bool Close();
bool GetLength(UInt64 &length) const;
off_t Seek(off_t distanceToMove, int moveMethod) const;
-diff -urN lzma-4.65/CPP/7zip/Common/FileStreams.h lzma-4.65.new/CPP/7zip/Common/FileStreams.h
---- lzma-4.65/CPP/7zip/Common/FileStreams.h 2009-05-15 23:33:51.000000000 +0200
-+++ lzma-4.65.new/CPP/7zip/Common/FileStreams.h 2009-06-01 22:30:01.000000000 +0200
-@@ -72,6 +72,7 @@
+--- a/CPP/7zip/Common/FileStreams.h
++++ b/CPP/7zip/Common/FileStreams.h
+@@ -72,6 +72,7 @@ class COutFileStream:
public IOutStream,
public CMyUnknownImp
{
#ifdef USE_WIN_FILE
NWindows::NFile::NIO::COutFile File;
#else
-diff -urN lzma-4.65/CPP/Common/MyWindows.h lzma-4.65.new/CPP/Common/MyWindows.h
---- lzma-4.65/CPP/Common/MyWindows.h 2009-05-15 23:33:51.000000000 +0200
-+++ lzma-4.65.new/CPP/Common/MyWindows.h 2009-06-01 22:29:26.000000000 +0200
-@@ -101,8 +101,11 @@
+--- a/CPP/Common/MyWindows.h
++++ b/CPP/Common/MyWindows.h
+@@ -101,8 +101,11 @@ typedef LONG SCODE;
#ifdef __cplusplus
---- a/CMakeLists.txt 2017-08-10 04:19:45.000000000 -0700
-+++ b/CMakeLists.txt 2022-11-28 17:21:03.453548350 -0800
-@@ -50,6 +50,9 @@
+--- a/CMakeLists.txt
++++ b/CMakeLists.txt
+@@ -50,6 +50,9 @@ endif()
project(lzop VERSION 1.04 LANGUAGES C)
# install directories
if(NOT CMAKE_INSTALL_PREFIX)
message(FATAL_ERROR "ERROR: CMAKE_INSTALL_PREFIX is not defined.")
-@@ -186,9 +189,11 @@
+@@ -186,9 +189,11 @@ if(DEFINED CMAKE_INSTALL_FULL_LIBDIR)
install(TARGETS lzop DESTINATION "${CMAKE_INSTALL_FULL_BINDIR}")
define Host/Install
$(INSTALL_DIR) $(STAGING_DIR_HOST)/share/aclocal
- $(INSTALL_DATA) ./src/m4/*.m4 $(STAGING_DIR_HOST)/share/aclocal/
+ $(INSTALL_DATA) $(HOST_BUILD_DIR)/m4/*.m4 $(STAGING_DIR_HOST)/share/aclocal/
$(INSTALL_DIR) $(STAGING_DIR_HOST)/bin
- $(INSTALL_BIN) ./src/bin/* $(STAGING_DIR_HOST)/bin/
+ $(INSTALL_BIN) $(HOST_BUILD_DIR)/bin/* $(STAGING_DIR_HOST)/bin/
$(LN) makeinfo $(STAGING_DIR_HOST)/bin/texi2any
$(LN) makeinfo $(STAGING_DIR_HOST)/bin/texi2pdf
$(LN) makeinfo $(STAGING_DIR_HOST)/bin/texi2dvi
include $(TOPDIR)/rules.mk
PKG_NAME:=mkimage
-PKG_VERSION:=2024.01
+PKG_VERSION:=2024.04
PKG_SOURCE:=u-boot-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:= \
https://mirror.cyberbits.eu/u-boot \
https://ftp.denx.de/pub/u-boot \
ftp://ftp.denx.de/pub/u-boot
-PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3
+PKG_HASH:=18a853fe39fad7ad03a90cc2d4275aeaed6da69735defac3492b80508843dd4a
HOST_BUILD_DIR:=$(BUILD_DIR_HOST)/u-boot-$(PKG_VERSION)
" -a ==> set load address to 'addr' (hex)\n"
" -e ==> set entry point to 'ep' (hex)\n"
" -n ==> set image name to 'name'\n"
-@@ -159,7 +161,7 @@ static int add_content(int type, const c
+@@ -160,7 +162,7 @@ static int add_content(int type, const c
}
static const char optstring[] =
static const struct option longopts[] = {
{ "load-address", required_argument, NULL, 'a' },
-@@ -302,6 +304,14 @@ static void process_args(int argc, char
+@@ -303,6 +305,14 @@ static void process_args(int argc, char
case 'l':
params.lflag = 1;
break;
--- a/tools/Kconfig
+++ b/tools/Kconfig
-@@ -31,7 +31,7 @@ config TOOLS_FIT
+@@ -36,7 +36,7 @@ config TOOLS_FIT
Enable FIT support in the tools builds.
config TOOLS_FIT_FULL_CHECK
include $(INCLUDE_DIR)/host-build.mk
define Host/Prepare
- mkdir -p $(HOST_BUILD_DIR)
- $(CP) ./src/* $(HOST_BUILD_DIR)/
+ $(call Host/Prepare/Default)
find $(HOST_BUILD_DIR) -name .svn | $(XARGS) rm -rf
endef
src/util.c | 14 +++++++++++---
2 files changed, 21 insertions(+), 5 deletions(-)
-diff --git a/src/inp.c b/src/inp.c
-index 32d0919..22d7473 100644
--- a/src/inp.c
+++ b/src/inp.c
@@ -238,8 +238,13 @@ plan_a (char const *filename)
|| ! (ifp = fdopen (ifd, binary_transput ? "rb" : "r")))
pfatal ("Can't open file %s", quotearg (filename));
if (TMPINNAME_needs_removal)
-diff --git a/src/util.c b/src/util.c
-index 1cc08ba..fb38307 100644
--- a/src/util.c
+++ b/src/util.c
-@@ -388,7 +388,7 @@ create_backup (char const *to, const struct stat *to_st, bool leave_original)
+@@ -388,7 +388,7 @@ create_backup (char const *to, const str
try_makedirs_errno = ENOENT;
safe_unlink (bakname);
{
if (errno != try_makedirs_errno)
pfatal ("Can't create file %s", quotearg (bakname));
-@@ -579,10 +579,13 @@ create_file (char const *file, int open_flags, mode_t mode,
+@@ -579,10 +579,13 @@ create_file (char const *file, int open_
static void
copy_to_fd (const char *from, int tofd)
{
pfatal ("Can't reopen file %s", quotearg (from));
while ((i = read (fromfd, buf, bufsize)) != 0)
{
-@@ -625,6 +628,8 @@ copy_file (char const *from, char const *to, struct stat *tost,
+@@ -625,6 +628,8 @@ copy_file (char const *from, char const
else
{
assert (S_ISREG (mode));
tofd = create_file (to, O_WRONLY | O_BINARY | to_flags, mode,
to_dir_known_to_exist);
copy_to_fd (from, tofd);
-@@ -640,9 +645,12 @@ copy_file (char const *from, char const *to, struct stat *tost,
+@@ -640,9 +645,12 @@ copy_file (char const *from, char const
void
append_to_file (char const *from, char const *to)
{
pfatal ("Can't reopen file %s", quotearg (to));
copy_to_fd (from, tofd);
if (close (tofd) != 0)
---
-cgit v1.0-41-gc330
-
src/pch.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
-diff --git a/src/pch.c b/src/pch.c
-index 4fd5a05..16e001a 100644
--- a/src/pch.c
+++ b/src/pch.c
-@@ -2459,9 +2459,6 @@ do_ed_script (char const *inname, char const *outname,
+@@ -2459,9 +2459,6 @@ do_ed_script (char const *inname, char c
*outname_needs_removal = true;
copy_file (inname, outname, 0, exclusive, instat.st_mode, true);
}
fflush (stdout);
pid = fork();
-@@ -2470,7 +2467,8 @@ do_ed_script (char const *inname, char const *outname,
+@@ -2470,7 +2467,8 @@ do_ed_script (char const *inname, char c
else if (pid == 0)
{
dup2 (tmpfd, 0);
_exit (2);
}
else
---
-cgit v1.0-41-gc330
-
projects / openwrt / staging / pepe2k.git / commitdiff