target/linux/mediatek/patches-5.15/811-pwm-mediatek-Add-support-for-MT7981.patch

   1 From 73d20ebc21c562fbe79d02fa0fa38e095e716fa9 Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Wed, 19 Apr 2023 20:25:51 +0100
   4 Subject: [PATCH] pwm: mediatek: Add support for MT7981
   5
   6 The PWM unit on MT7981 uses different register offsets than previous
   7 MediaTek PWM units. Add support for these new offsets and add support
   8 for PWM on MT7981 which has 3 PWM channels, one of them is typically
   9 used for a temperature controlled fan.
  10
  11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  12 ---
  13  drivers/pwm/pwm-mediatek.c | 41 ++++++++++++++++++++++++++++++--------
  14  1 file changed, 33 insertions(+), 8 deletions(-)
  15
  16 --- a/drivers/pwm/pwm-mediatek.c
  17 +++ b/drivers/pwm/pwm-mediatek.c
  18 @@ -38,6 +38,7 @@ struct pwm_mediatek_of_data {
  19         unsigned int num_pwms;
  20         bool pwm45_fixup;
  21         bool has_ck_26m_sel;
  22 +       const unsigned int *reg_offset;
  23  };
  24
  25  /**
  26 @@ -59,10 +60,14 @@ struct pwm_mediatek_chip {
  27         const struct pwm_mediatek_of_data *soc;
  28  };
  29
  30 -static const unsigned int pwm_mediatek_reg_offset[] = {
  31 +static const unsigned int mtk_pwm_reg_offset_v1[] = {
  32         0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220
  33  };
  34
  35 +static const unsigned int mtk_pwm_reg_offset_v2[] = {
  36 +       0x0080, 0x00c0, 0x0100, 0x0140, 0x0180, 0x01c0, 0x0200, 0x0240
  37 +};
  38 +
  39  static inline struct pwm_mediatek_chip *
  40  to_pwm_mediatek_chip(struct pwm_chip *chip)
  41  {
  42 @@ -111,7 +116,7 @@ static inline void pwm_mediatek_writel(s
  43                                        unsigned int num, unsigned int offset,
  44                                        u32 value)
  45  {
  46 -       writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset);
  47 +       writel(value, chip->regs + chip->soc->reg_offset[num] + offset);
  48  }
  49
  50  static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm,
  51 @@ -270,48 +275,63 @@ static const struct pwm_mediatek_of_data
  52         .num_pwms = 8,
  53         .pwm45_fixup = false,
  54         .has_ck_26m_sel = false,
  55 +       .reg_offset = mtk_pwm_reg_offset_v1,
  56  };
  57
  58  static const struct pwm_mediatek_of_data mt7622_pwm_data = {
  59         .num_pwms = 6,
  60         .pwm45_fixup = false,
  61         .has_ck_26m_sel = true,
  62 +       .reg_offset = mtk_pwm_reg_offset_v1,
  63  };
  64
  65  static const struct pwm_mediatek_of_data mt7623_pwm_data = {
  66         .num_pwms = 5,
  67         .pwm45_fixup = true,
  68         .has_ck_26m_sel = false,
  69 +       .reg_offset = mtk_pwm_reg_offset_v1,
  70  };
  71
  72  static const struct pwm_mediatek_of_data mt7628_pwm_data = {
  73         .num_pwms = 4,
  74         .pwm45_fixup = true,
  75         .has_ck_26m_sel = false,
  76 +       .reg_offset = mtk_pwm_reg_offset_v1,
  77  };
  78
  79  static const struct pwm_mediatek_of_data mt7629_pwm_data = {
  80         .num_pwms = 1,
  81         .pwm45_fixup = false,
  82         .has_ck_26m_sel = false,
  83 +       .reg_offset = mtk_pwm_reg_offset_v1,
  84  };
  85
  86  static const struct pwm_mediatek_of_data mt8183_pwm_data = {
  87         .num_pwms = 4,
  88         .pwm45_fixup = false,
  89         .has_ck_26m_sel = true,
  90 +       .reg_offset = mtk_pwm_reg_offset_v1,
  91 +};
  92 +
  93 +static const struct pwm_mediatek_of_data mt7981_pwm_data = {
  94 +       .num_pwms = 3,
  95 +       .pwm45_fixup = false,
  96 +       .has_ck_26m_sel = true,
  97 +       .reg_offset = mtk_pwm_reg_offset_v2,
  98  };
  99
 100  static const struct pwm_mediatek_of_data mt7986_pwm_data = {
 101         .num_pwms = 2,
 102         .pwm45_fixup = false,
 103         .has_ck_26m_sel = true,
 104 +       .reg_offset = mtk_pwm_reg_offset_v1,
 105  };
 106
 107  static const struct pwm_mediatek_of_data mt8516_pwm_data = {
 108         .num_pwms = 5,
 109         .pwm45_fixup = false,
 110         .has_ck_26m_sel = true,
 111 +       .reg_offset = mtk_pwm_reg_offset_v1,
 112  };
 113
 114  static const struct of_device_id pwm_mediatek_of_match[] = {
 115 @@ -320,6 +340,7 @@ static const struct of_device_id pwm_med
 116         { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data },
 117         { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data },
 118         { .compatible = "mediatek,mt7629-pwm", .data = &mt7629_pwm_data },
 119 +       { .compatible = "mediatek,mt7981-pwm", .data = &mt7981_pwm_data },
 120         { .compatible = "mediatek,mt7986-pwm", .data = &mt7986_pwm_data },
 121         { .compatible = "mediatek,mt8183-pwm", .data = &mt8183_pwm_data },
 122         { .compatible = "mediatek,mt8516-pwm", .data = &mt8516_pwm_data },