ipq40xx: use NVMEM-on-UBI for ASUS RT-AC58U
[openwrt/openwrt.git] / target / linux / lantiq / patches-6.1 / 0002-MIPS-pci-lantiq-restore-reset-gpio-polarity.patch
1 From f038380835033e376d89c72516f087254792bbad Mon Sep 17 00:00:00 2001
2 From: Martin Schiller <ms@dev.tdt.de>
3 Date: Mon, 6 May 2024 09:41:42 +0200
4 Subject: [PATCH] MIPS: pci: lantiq: restore reset gpio polarity
5
6 Commit 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API") not
7 only switched to the gpiod API, but also inverted / changed the polarity
8 of the GPIO.
9
10 According to the PCI specification, the RST# pin is an active-low
11 signal. However, most of the device trees that have been widely used for
12 a long time (mainly in the openWrt project) define this GPIO as
13 active-high and the old driver code inverted the signal internally.
14
15 Apparently there are actually boards where the reset gpio must be
16 operated inverted. For this reason, we cannot use the GPIOD_OUT_LOW/HIGH
17 flag for initialization. Instead, we must explicitly set the gpio to
18 value 1 in order to take into account any "GPIO_ACTIVE_LOW" flag that
19 may have been set.
20
21 In order to remain compatible with all these existing device trees, we
22 should therefore keep the logic as it was before the commit.
23
24 Fixes: 90c2d2eb7ab5 ("MIPS: pci: lantiq: switch to using gpiod API")
25 Cc: stable@vger.kernel.org
26 Signed-off-by: Martin Schiller <ms@dev.tdt.de>
27 ---
28 arch/mips/pci/pci-lantiq.c | 8 ++++----
29 1 file changed, 4 insertions(+), 4 deletions(-)
30
31 --- a/arch/mips/pci/pci-lantiq.c
32 +++ b/arch/mips/pci/pci-lantiq.c
33 @@ -124,14 +124,14 @@ static int ltq_pci_startup(struct platfo
34 clk_disable(clk_external);
35
36 /* setup reset gpio used by pci */
37 - reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset",
38 - GPIOD_OUT_LOW);
39 + reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_ASIS);
40 error = PTR_ERR_OR_ZERO(reset_gpio);
41 if (error) {
42 dev_err(&pdev->dev, "failed to request gpio: %d\n", error);
43 return error;
44 }
45 gpiod_set_consumer_name(reset_gpio, "pci_reset");
46 + gpiod_direction_output(reset_gpio, 1);
47
48 /* enable auto-switching between PCI and EBU */
49 ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
50 @@ -194,10 +194,10 @@ static int ltq_pci_startup(struct platfo
51
52 /* toggle reset pin */
53 if (reset_gpio) {
54 - gpiod_set_value_cansleep(reset_gpio, 1);
55 + gpiod_set_value_cansleep(reset_gpio, 0);
56 wmb();
57 mdelay(1);
58 - gpiod_set_value_cansleep(reset_gpio, 0);
59 + gpiod_set_value_cansleep(reset_gpio, 1);
60 }
61 return 0;
62 }