1 From c9ecd920324a647bf1f2b47f771c8f599cc7b551 Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Sat, 22 Feb 2020 18:02:17 +0100
4 Subject: [PATCH 2/8] Documentation: cpufreq: add qcom,krait-cache bindings
6 Document dedicated cpufreq for Krait CPUs.
8 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
10 .../bindings/cpufreq/qcom-cpufreq-krait.yaml | 221 ++++++++++++++++++
11 1 file changed, 221 insertions(+)
12 create mode 100644 Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml
14 diff --git a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml
16 index 000000000000..f6bcca863d9a
18 +++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-krait.yaml
20 +# SPDX-License-Identifier: GPL-2.0
23 +$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-krait.yaml#
24 +$schema: http://devicetree.org/meta-schemas/core.yaml#
26 +title: CPU Frequency scaling driver for Krait SoCs
29 + - Ansuel Smith <ansuelsmth@gmail.com>
32 + The krait cpufreq driver is a dedicated frequency scaling driver
33 + based on cpufreq-dt generic driver that scale L2 cache and the
36 + The L2 cache is scaled based on the max clk across all cores and
37 + the clock is decided based on the opp-level set in the device tree.
39 + Different core freq can be linked to a specific l2 freq and the driver
40 + on frequency change will scale the core and the l2 clk based of the
43 + On Krait SoC is present a bug and on every L2 clk change the driver
44 + needs to set the clk to the idle freq before changing it to the new value.
46 + This requires the qcom cpufreq nvmem driver to parse the different opp
47 + core clk and an additional opp table for the l2 scaling.
49 + If the driver detect broken config (for example missing opp-level) the
50 + cpufreq driver skips the l2 scaling
52 + Referring to this example opp-level can be used to link a range of cpu freq
53 + to a specific l2 freq:
54 + cpu opp freq 384000000 has opp-level 0
55 + l2 opp freq 384000000 has opp-level 0
56 + The driver will scale l2 to 384000000
58 + cpu opp freq 600000000-1000000000 has opp-level 1
59 + l2 opp freq 1000000000 has opp-level 1
60 + The driver will scale l2 to 1000000000
63 + - $ref: /schemas/cache-controller.yaml#
78 + - const: qcom,krait-cache
92 + operating-points-v2: true
100 + - operating-points-v2
102 +additionalProperties: false
107 + #address-cells = <1>;
111 + compatible = "qcom,krait";
112 + enable-method = "qcom,kpss-acc-v1";
113 + device_type = "cpu";
115 + next-level-cache = <&L2>;
116 + qcom,acc = <&acc0>;
117 + qcom,saw = <&saw0>;
118 + clocks = <&kraitcc 0>, <&kraitcc 4>;
119 + clock-names = "cpu", "l2";
120 + clock-latency = <100000>;
121 + cpu-supply = <&smb208_s2a>;
122 + operating-points-v2 = <&opp_table0>;
123 + voltage-tolerance = <5>;
124 + cooling-min-state = <0>;
125 + cooling-max-state = <10>;
126 + #cooling-cells = <2>;
127 + cpu-idle-states = <&CPU_SPC>;
134 + opp_table0: opp_table0 {
135 + compatible = "operating-points-v2-kryo-cpu";
136 + nvmem-cells = <&speedbin_efuse>;
139 + opp-hz = /bits/ 64 <384000000>;
140 + opp-microvolt-speed0-pvs0-v0 = <1000000>;
141 + opp-microvolt-speed0-pvs1-v0 = <925000>;
142 + opp-microvolt-speed0-pvs2-v0 = <875000>;
143 + opp-microvolt-speed0-pvs3-v0 = <800000>;
144 + opp-supported-hw = <0x1>;
145 + clock-latency-ns = <100000>;
150 + opp-hz = /bits/ 64 <600000000>;
151 + opp-microvolt-speed0-pvs0-v0 = <1050000>;
152 + opp-microvolt-speed0-pvs1-v0 = <975000>;
153 + opp-microvolt-speed0-pvs2-v0 = <925000>;
154 + opp-microvolt-speed0-pvs3-v0 = <850000>;
155 + opp-supported-hw = <0x1>;
156 + clock-latency-ns = <100000>;
161 + opp-hz = /bits/ 64 <800000000>;
162 + opp-microvolt-speed0-pvs0-v0 = <1100000>;
163 + opp-microvolt-speed0-pvs1-v0 = <1025000>;
164 + opp-microvolt-speed0-pvs2-v0 = <995000>;
165 + opp-microvolt-speed0-pvs3-v0 = <900000>;
166 + opp-supported-hw = <0x1>;
167 + clock-latency-ns = <100000>;
172 + opp-hz = /bits/ 64 <1000000000>;
173 + opp-microvolt-speed0-pvs0-v0 = <1150000>;
174 + opp-microvolt-speed0-pvs1-v0 = <1075000>;
175 + opp-microvolt-speed0-pvs2-v0 = <1025000>;
176 + opp-microvolt-speed0-pvs3-v0 = <950000>;
177 + opp-supported-hw = <0x1>;
178 + clock-latency-ns = <100000>;
183 + opp-hz = /bits/ 64 <1200000000>;
184 + opp-microvolt-speed0-pvs0-v0 = <1200000>;
185 + opp-microvolt-speed0-pvs1-v0 = <1125000>;
186 + opp-microvolt-speed0-pvs2-v0 = <1075000>;
187 + opp-microvolt-speed0-pvs3-v0 = <1000000>;
188 + opp-supported-hw = <0x1>;
189 + clock-latency-ns = <100000>;
194 + opp-hz = /bits/ 64 <1400000000>;
195 + opp-microvolt-speed0-pvs0-v0 = <1250000>;
196 + opp-microvolt-speed0-pvs1-v0 = <1175000>;
197 + opp-microvolt-speed0-pvs2-v0 = <1125000>;
198 + opp-microvolt-speed0-pvs3-v0 = <1050000>;
199 + opp-supported-hw = <0x1>;
200 + clock-latency-ns = <100000>;
205 + opp_table_l2: opp_table_l2 {
206 + compatible = "operating-points-v2";
209 + opp-hz = /bits/ 64 <384000000>;
210 + opp-microvolt = <1100000>;
211 + clock-latency-ns = <100000>;
215 + opp-hz = /bits/ 64 <1000000000>;
216 + opp-microvolt = <1100000>;
217 + clock-latency-ns = <100000>;
221 + opp-hz = /bits/ 64 <1200000000>;
222 + opp-microvolt = <1150000>;
223 + clock-latency-ns = <100000>;
230 + compatible = "qcom,krait-cache", "cache";
233 + clocks = <&kraitcc 4>;
234 + clock-names = "l2";
235 + l2-supply = <&smb208_s1a>;
236 + operating-points-v2 = <&opp_table_l2>;