target/linux/bcm27xx/patches-6.1/950-1241-drm-vc4-Add-2712-support-to-vc4_plane_async_set_fb.patch

   1 From a14da0fdb0e052a672c269df7f18c9de698bd827 Mon Sep 17 00:00:00 2001
   2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
   3 Date: Thu, 4 Jan 2024 15:02:42 +0000
   4 Subject: [PATCH] drm/vc4: Add 2712 support to vc4_plane_async_set_fb
   5
   6 vc4_plane_async_set_fb directly overwrites the plane address in
   7 the dlist entry, but hadn't been updated for the GEN6 / 2712
   8 dlist format, corrupting the address in the process.
   9
  10 Add support for the 2712 dlist format to the function.
  11
  12 Fixes: 1ab1fbbb7e76 ("drm/vc4: hvs: Support BCM2712 HVS")
  13 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  14 ---
  15  drivers/gpu/drm/vc4/vc4_plane.c | 46 +++++++++++++++++++++++----------
  16  1 file changed, 33 insertions(+), 13 deletions(-)
  17
  18 --- a/drivers/gpu/drm/vc4/vc4_plane.c
  19 +++ b/drivers/gpu/drm/vc4/vc4_plane.c
  20 @@ -1865,7 +1865,7 @@ static int vc6_plane_mode_set(struct drm
  21                                  * The UPM buffer will be allocated in
  22                                  * vc6_plane_allocate_upm().
  23                                  */
  24 -                               VC4_SET_FIELD(upper_32_bits(paddr) & 0xf,
  25 +                               VC4_SET_FIELD(upper_32_bits(paddr) & 0xff,
  26                                               SCALER6_PTR0_UPPER_ADDR));
  27
  28                 /* Pointer Word 1 */
  29 @@ -2068,7 +2068,8 @@ void vc4_plane_async_set_fb(struct drm_p
  30  {
  31         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
  32         struct drm_gem_dma_object *bo = drm_fb_dma_get_gem_obj(fb, 0);
  33 -       uint32_t addr;
  34 +       struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
  35 +       dma_addr_t dma_addr = bo->dma_addr + fb->offsets[0];
  36         int idx;
  37
  38         if (!drm_dev_enter(plane->dev, &idx))
  39 @@ -2078,19 +2079,38 @@ void vc4_plane_async_set_fb(struct drm_p
  40          * because this is only called on the primary plane.
  41          */
  42         WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
  43 -       addr = bo->dma_addr + fb->offsets[0];
  44
  45 -       /* Write the new address into the hardware immediately.  The
  46 -        * scanout will start from this address as soon as the FIFO
  47 -        * needs to refill with pixels.
  48 -        */
  49 -       writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
  50 +       if (vc4->gen == VC4_GEN_6) {
  51 +               u32 value;
  52
  53 -       /* Also update the CPU-side dlist copy, so that any later
  54 -        * atomic updates that don't do a new modeset on our plane
  55 -        * also use our updated address.
  56 -        */
  57 -       vc4_state->dlist[vc4_state->ptr0_offset[0]] = addr;
  58 +               value = vc4_state->dlist[vc4_state->ptr0_offset[0]] &
  59 +                                       ~SCALER6_PTR0_UPPER_ADDR_MASK;
  60 +               value |= VC4_SET_FIELD(upper_32_bits(dma_addr) & 0xff,
  61 +                                      SCALER6_PTR0_UPPER_ADDR);
  62 +
  63 +               writel(value, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
  64 +               vc4_state->dlist[vc4_state->ptr0_offset[0]] = value;
  65 +
  66 +               value = lower_32_bits(dma_addr);
  67 +               writel(value, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0] + 1]);
  68 +               vc4_state->dlist[vc4_state->ptr0_offset[0] + 1] = value;
  69 +       } else {
  70 +               u32 addr;
  71 +
  72 +               addr = (u32)dma_addr;
  73 +
  74 +               /* Write the new address into the hardware immediately.  The
  75 +                * scanout will start from this address as soon as the FIFO
  76 +                * needs to refill with pixels.
  77 +                */
  78 +               writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset[0]]);
  79 +
  80 +               /* Also update the CPU-side dlist copy, so that any later
  81 +                * atomic updates that don't do a new modeset on our plane
  82 +                * also use our updated address.
  83 +                */
  84 +               vc4_state->dlist[vc4_state->ptr0_offset[0]] = addr;
  85 +       }
  86
  87         drm_dev_exit(idx);
  88  }