From: Rafał Miłecki Date: Fri, 24 Dec 2021 12:15:12 +0000 (+0100) Subject: Add Broadcom's code for bcm63xx support X-Git-Url: http://git.openwrt.org/ubox.git?a=commitdiff_plain;p=project%2Fbcm63xx%2Fatf.git Add Broadcom's code for bcm63xx support This includes all bcm63xx families (some of them don't follow that naming schema - like BCM4908). All that code has been extracted from the RAXE500_RAXE450-V1.0.8.70_GPL_release.zip . Signed-off-by: Rafał Miłecki --- diff --git a/Makefile b/Makefile index 721246d5..fa7fb8c6 100644 --- a/Makefile +++ b/Makefile @@ -268,8 +268,9 @@ ifeq ($(findstring clang,$(notdir $(CC))),) # not using clang WARNINGS += -Wunused-but-set-variable \ -Wmaybe-uninitialized \ - -Wpacked-bitfield-compat \ - -Wshift-overflow=2 + -Wpacked-bitfield-compat +# BRCM_PATCH: Conflicts with toolchain +# -Wshift-overflow=2 else # using clang WARNINGS += -Wshift-overflow -Wshift-sign-overflow @@ -283,10 +284,16 @@ CPPFLAGS = ${DEFINES} ${INCLUDES} ${MBEDTLS_INC} -nostdinc \ -Wmissing-include-dirs $(ERRORS) $(WARNINGS) ASFLAGS += $(CPPFLAGS) $(ASFLAGS_$(ARCH)) \ -ffreestanding -Wa,--fatal-warnings +# BRCM_PATCH: Code optimization for Cortex-A9 brings instability +ifeq ($(strip $(BRCM_CHIP)),63138) +TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ + -ffreestanding -fno-builtin -Wall -std=gnu99 \ + -O0 -ffunction-sections -fdata-sections +else TF_CFLAGS += $(CPPFLAGS) $(TF_CFLAGS_$(ARCH)) \ -ffreestanding -fno-builtin -Wall -std=gnu99 \ -Os -ffunction-sections -fdata-sections - +endif ifeq (${SANITIZE_UB},on) TF_CFLAGS += -fsanitize=undefined -fno-sanitize-recover endif @@ -364,7 +371,7 @@ INCLUDE_TBBR_MK := 1 ifneq (${SPD},none) ifeq (${ARCH},aarch32) - $(error "Error: SPD is incompatible with AArch32.") +# $(error "Error: SPD is incompatible with AArch32.") endif ifdef EL3_PAYLOAD_BASE $(warning "SPD and EL3_PAYLOAD_BASE are incompatible build options.") @@ -718,7 +725,9 @@ endif # This is done after including the platform specific makefile to allow the # platform to overwrite the default options ################################################################################ - +# BRCM_PATCH: Need to add Broadcom SoC specific platform profiles +$(eval $(call add_define,PLATFORM_FLAVOR_${BRCM_CHIP})) +$(eval $(call add_define,_BCM9${BRCM_CHIP}_)) $(eval $(call add_define,ARM_ARCH_MAJOR)) $(eval $(call add_define,ARM_ARCH_MINOR)) $(eval $(call add_define,COLD_BOOT_SINGLE_CPU)) diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 1ad26e4f..2d4a5536 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -12,6 +12,7 @@ #include #include #include +#include .globl bl31_entrypoint .globl bl31_warm_entrypoint @@ -129,6 +130,13 @@ func bl31_entrypoint sub x1, x1, x0 bl clean_dcache_range +/* BRCM_PATCH: Save the CTX_PMCR_EL0 configured by boot loader +*/ + msr spsel, #MODE_SP_ELX + mrs x17, pmcr_el0 + str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] + msr spsel, #MODE_SP_EL0 + b el3_exit endfunc bl31_entrypoint @@ -138,6 +146,7 @@ endfunc bl31_entrypoint * warmboot entrypoint * -------------------------------------------------------------------- */ + .align 8 func bl31_warm_entrypoint #if ENABLE_RUNTIME_INSTRUMENTATION diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index 0a684754..132495e0 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -153,6 +153,13 @@ func sp_min_entrypoint /* r0 points to `smc_ctx_t` */ /* The PSCI cpu_context registers have been copied to `smc_ctx_t` */ + /* BRCM_PATCH: PMCR passed from boot loader needs to be saved to initial ATF context. + * Othewise, PMCR setting will be lost, when ATF returns to next stage boot loader. + */ + push {r1} + ldcopr r1, PMCR + str r1, [r0, #SMC_CTX_PMCR] + pop {r1} b sp_min_exit endfunc sp_min_entrypoint @@ -285,12 +292,24 @@ func sp_min_warm_entrypoint #else mov r0, #DISABLE_DCACHE #endif + /* BRCM_PATCH: BCM63138 (Cortex-A9) does not support long MMU descriptor. + * Need to use A9 specific short MMU descriptor. + */ +#if defined(PLATFORM_FLAVOR_63138) + bl a9_l1cache_inval_d + bl a9_bl32_plat_enable_mmu +#else bl bl32_plat_enable_mmu +#endif #if SP_MIN_WITH_SECURE_FIQ route_fiq_to_sp_min r0 #endif +#if defined(SPD_opteed) + bl opteed_setup +#endif + bl sp_min_warm_boot bl smc_get_next_ctx /* r0 points to `smc_ctx_t` */ diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 7559de44..da71fc90 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -100,8 +100,16 @@ * --------------------------------------------------------------------- */ #if ((ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_VFP)) && !(__SOFTFP__) + /* BRCM_PATCH: BCM63138 does not have NEON in 2nd CPU */ +#if defined (PLATFORM_FLAVOR_63138) + bl plat_my_core_pos + cmp r0, #0 + ldreq r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT) + vmsreq FPEXC, r0 +#else ldr r0, =(FPEXC_RESET_VAL | FPEXC_EN_BIT) vmsr FPEXC, r0 +#endif isb #endif @@ -146,7 +154,9 @@ #else ldr r0, =(PMCR_RESET_VAL | PMCR_DP_BIT) #endif + /* BRCM_PATCH: Do not overwrite the setting done by BRCM boot loaders stcopr r0, PMCR + */ /* * If Data Independent Timing (DIT) functionality is implemented, diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 378e827c..c2946a85 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -155,9 +155,9 @@ mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \ PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \ ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT)) - + /* BRCM_PATCH: Do not overwrite the setting done by BRCM boot loaders msr pmcr_el0, x0 - + */ /* --------------------------------------------------------------------- * Enable External Aborts and SError Interrupts now that the exception * vectors have been setup. diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 896a03f0..c713b482 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -26,8 +26,9 @@ * Constants to identify the location of a memory region in a given memory * layout. ******************************************************************************/ -#define TOP U(0x1) -#define BOTTOM U(0x0) +/* BRCM_PATCH: Avoid symbol conflict with Broadcom */ +#define ATF_TOP U(0x1) +#define ATF_BOTTOM U(0x0) /******************************************************************************* * Constants to indicate type of exception to the common exception handler. diff --git a/include/lib/cpus/aarch64/cortex_a53.h b/include/lib/cpus/aarch64/cortex_a53.h index 6fe67a9f..d2886516 100644 --- a/include/lib/cpus/aarch64/cortex_a53.h +++ b/include/lib/cpus/aarch64/cortex_a53.h @@ -11,6 +11,7 @@ /* Cortex-A53 midr for revision 0 */ #define CORTEX_A53_MIDR U(0x410FD030) +#define CORTEX_B53_MIDR U(0x420F1000) /* Retention timer tick definitions */ #define RETENTION_ENTRY_TICKS_2 U(0x1) diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S index 6d2ec1c5..7c9c23ad 100644 --- a/lib/aarch32/misc_helpers.S +++ b/lib/aarch32/misc_helpers.S @@ -7,6 +7,7 @@ #include #include #include +.arch_extension sec .globl smc .globl zeromem diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index b105de26..290c561d 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -388,7 +388,7 @@ func cortex_a53_cpu_reg_dump ret endfunc cortex_a53_cpu_reg_dump -declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \ +declare_cpu_ops cortex_a53, CORTEX_B53_MIDR, \ cortex_a53_reset_func, \ cortex_a53_core_pwr_dwn, \ cortex_a53_cluster_pwr_dwn diff --git a/make_helpers/armv7-a-cpus.mk b/make_helpers/armv7-a-cpus.mk index 5571ab0f..8b35b15a 100644 --- a/make_helpers/armv7-a-cpus.mk +++ b/make_helpers/armv7-a-cpus.mk @@ -50,6 +50,14 @@ $(eval $(call add_define,ARMV7_SUPPORTS_GENERIC_TIMER)) $(eval $(call add_define,ARMV7_SUPPORTS_VFP)) endif +# BRCM_PATCH: 1. BCM63138 (Cortex-A9) does have NEON. +# 2. Even though A9 does not support LARGE_PAGE_ADDRESSING +# needed to enable it to get compilation going. +ifeq ($(filter yes,$(ARM_CORTEX_A9)),yes) +$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING)) +$(eval $(call add_define,ARMV7_SUPPORTS_VFP)) +endif + ifeq ($(ARM_CORTEX_A5),yes) $(eval $(call add_define,ARM_CORTEX_A5)) endif diff --git a/plat/bcm/aarch32/cortexa9_mmu.S b/plat/bcm/aarch32/cortexa9_mmu.S new file mode 100644 index 00000000..81c25dc9 --- /dev/null +++ b/plat/bcm/aarch32/cortexa9_mmu.S @@ -0,0 +1,232 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#include +#include +#include + + .globl a9_mmu_set_ttbr + .globl a9_mmu_invalidate_tlb + .globl a9_mmu_set_scn + .globl a9_mmu_enable + .globl a9_l1cache_enable_d + .globl a9_l1cache_enable_i + .globl a9_gic_secure_init + .globl a9_l1cache_inval_d + +func a9_mmu_set_ttbr + push {r0-r12,r14} + // Set the access control to client so AP is checked with tlb entry + ldr r1, =0x55555555 + mcr p15, 0, r1, c3, c0, 0 // Write Domain Access Control Register + + // Set Translation Table base address. r0 must be preserved + mcr p15, 0, r0, c2, c0, 0 // Write Translation Table Base Register 0 + isb + dsb + pop {r0-r12,r14} + mov pc,lr +endfunc a9_mmu_set_ttbr + +func a9_mmu_invalidate_tlb + push {r0-r12,r14} + mov r0,#0 + mcr p15,0,r0,c8,c7,0 /* Invalidate TLB */ + isb + dsb + pop {r0-r12,r14} + mov pc,lr +endfunc a9_mmu_invalidate_tlb + + + +/* + map_set_scn - sets number (SCN_RNG) of L1 table entries. Operates on 1 MB sections + r0 - L1 table paddr + r1 - virtual address start + r2 - address range in Megabytes + r3 - Sections' attributes + r4 - mapped physical start address + Table max size 16K (4K*4) +*/ + +#define WORD_SIZE 4 /* bytes */ +#define WORD_BITLEN 32 /*bitlen or shift*/ +#define WORD_ALGN 2 /* word alignment shift*/ +#define SCN_BITLEN 20 /*bitlen or shift */ + +#define L1TBL_PA r0 /* */ +#define SCN_VA r1 +#define SCN_RNG r2 +#define SCN_ATTR r3 +#define SCN_PA r4 +#define SCN_ENTRY r5 +#define L1TBL_LEN r6 +/* NN (not nested) - meaning there are no calls to subroutine. LR is not preserved + registers r0-r6 are not preserved and must not be relied upon +*/ +func a9_mmu_set_scn + push {r0-r12,r14} + mov SCN_ENTRY,#0 + /* adjust virt/phys addresses for the loop increment */ + lsr SCN_VA, SCN_VA, #(SCN_BITLEN) + lsr SCN_PA, SCN_PA, #(SCN_BITLEN) + /* clear 12 msb of the section attribute */ + bfc SCN_ATTR, #SCN_BITLEN, #(WORD_BITLEN-SCN_BITLEN) + /* set max range not exceeding 0xfff */ + add SCN_RNG, SCN_VA, SCN_RNG + cmp SCN_RNG, L1TBL_LEN + blt 1f + mov SCN_RNG, L1TBL_LEN +1: + orr SCN_ENTRY, SCN_ATTR, SCN_PA, lsl #(SCN_BITLEN) + str SCN_ENTRY, [L1TBL_PA, SCN_VA, lsl #(WORD_ALGN)] + add SCN_PA, SCN_PA, #1 + add SCN_VA, SCN_VA, #1 + cmp SCN_VA, SCN_RNG + bne 1b + pop {r0-r12,r14} + mov pc,lr +endfunc a9_mmu_set_scn + +/* + * CR1 bits (CP#15 CR1) + */ +#define CR_M (1 << 0) /* MMU enable */ +#define CR_C (1 << 2) /* Dcache enable */ +#define CR_Z (1 << 11) /* Program Flow Prediction */ +#define CR_I (1 << 12) /* Icache enable */ + + +func a9_mmu_enable + push {r0-r12,r14} + mrc p15, 0, r0, c1, c0, 0 // Read CP15 System Control register + orr r0, r0, #CR_M // Set M bit 0 to enable MMU + mcr p15, 0, r0, c1, c0, 0 // Write CP15 System Control register + isb + pop {r0-r12,r14} + mov pc, lr +endfunc a9_mmu_enable + + +func a9_l1cache_enable_i + push {r0-r12,r14} + mrc p15, 0, r0, c1, c0, 0 // Read Control Register configuration data + orr r0, r0, #CR_I // Enable I Cache + orr r0, r0, #CR_Z // Enable Prediction + mcr p15, 0, r0, c1, c0, 0 // Write Control Register configuration data + isb + pop {r0-r12,r14} + mov pc, lr +endfunc a9_l1cache_enable_i + + +func a9_l1cache_enable_d + push {r0-r12,r14} + mrc p15, 0, r0, c1, c0, 0 // Read Control Register configuration data + orr r0, r0, #CR_C // Enable D Cache + mcr p15, 0, r0, c1, c0, 0 // Write Control Register configuration data + isb + pop {r0-r12,r14} + mov pc, lr +endfunc a9_l1cache_enable_d + +func a9_gic_secure_init + push {r0-r12,r14} + /* setup the GIC for non secure world. group 0 secure state, group 1 non secure state */ + /* enable interrupt for both groups */ + ldr r0, =GICD_BASE + ldr r1, =0x3 + str r1, [r0, #GICD_CTLR_OFFSET] + + /* assign all the interrupt to group 1 */ + ldr r2, [r0, #GICD_TYPER_OFFSET] + and r2, r2, #0x1f + add r2, r2, #1 + ldr r1, =0xffffffff + add r0, r0, #GICD_IGROUPR0_OFFSET +setgroup: + str r1, [r0] + add r0, #4 + subs r2, r2, #1 + bne setgroup + + /* enable both group interrupt in the cpu interface */ + ldr r0, =GICC_BASE + ldr r1, [r0, #GICC_CTLR_OFFSET] + orr r1, #0x3 + str r1, [r0] + + /* set cpu priority mask view for nonsecure */ + mov r1, #0x80 + str r1, [r0, #GICC_PMR_OFFSET] + pop {r0-r12,r14} + mov pc, lr +endfunc a9_gic_secure_init + + +func a9_l1cache_inval_d + push {r0-r12,r14} + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq invfinished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +invloop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt invskip @ skip if no cache, or just i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +invloop2: + mov r9, r4 @ create working copy of max way size +invloop3: + orr r6, r10, r9, lsl r5 @ factor way and cache number into r6 + orr r6, r6, r7, lsl r2 @ factor index number into r6 + mcr p15, 0, r6, c7, c6, 2 @ invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge invloop3 + subs r7, r7, #1 @ decrement the index + bge invloop2 +invskip: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt invloop1 +invfinished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + isb + pop {r0-r12,r14} + mov pc, lr +endfunc a9_l1cache_inval_d diff --git a/plat/bcm/aarch32/opteed_helper.S b/plat/bcm/aarch32/opteed_helper.S new file mode 100644 index 00000000..c10c0639 --- /dev/null +++ b/plat/bcm/aarch32/opteed_helper.S @@ -0,0 +1,263 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ +#if defined(SPD_opteed) +#include + +.global save_atf_sysreg +.global restore_atf_sysreg + + .macro read_sctlr reg + mrc p15, 0, \reg, c1, c0, 0 + .endm + + .macro write_sctlr reg + mcr p15, 0, \reg, c1, c0, 0 + .endm + + .macro read_scr reg + mrc p15, 0, \reg, c1, c1, 0 + .endm + + .macro write_scr reg + mcr p15, 0, \reg, c1, c1, 0 + .endm + + .macro write_ttbr0 reg + mcr p15, 0, \reg, c2, c0, 0 + .endm + + .macro read_ttbr0 reg + mrc p15, 0, \reg, c2, c0, 0 + .endm + + .macro write_ttbr1 reg + mcr p15, 0, \reg, c2, c0, 1 + .endm + + .macro read_ttbr1 reg + mrc p15, 0, \reg, c2, c0, 1 + .endm + + .macro write_ttbcr reg + mcr p15, 0, \reg, c2, c0, 2 + .endm + + .macro read_ttbcr reg + mrc p15, 0, \reg, c2, c0, 2 + .endm + + .macro write_dacr reg + mcr p15, 0, \reg, c3, c0, 0 + .endm + + .macro read_dacr reg + mrc p15, 0, \reg, c3, c0, 0 + .endm + + .macro read_vbar reg + mrc p15, 0, \reg, c12, c0, 0 + .endm + + .macro write_vbar reg + mcr p15, 0, \reg, c12, c0, 0 + .endm + + .macro write_mvbar reg + mcr p15, 0, \reg, c12, c0, 1 + .endm + + .macro read_mvbar reg + mrc p15, 0, \reg, c12, c0, 1 + .endm + + .macro write_mair0 reg + mcr p15, 0, \reg, c10, c2, 0 + .endm + + .macro read_mair0 reg + mrc p15, 0, \reg, c10, c2, 0 + .endm + + .macro write_mair1 reg + mcr p15, 0, \reg, c10, c2, 1 + .endm + + .macro read_mair1 reg + mrc p15, 0, \reg, c10, c2, 1 + .endm + + .macro read_cpsr reg + mrs \reg, cpsr + .endm + + .macro write_cpsr reg + msr cpsr_fsxc, \reg + .endm + + .macro invalidate_tlb reg + mov \reg, #0 + mcr p15, 0, \reg, c8, c5, 0 + mcr p15, 0, \reg, c8, c6, 0 + mcr p15, 0, \reg, c8, c7, 0 + isb + dsb + .endm + +/* + * + */ +func save_atf_sysreg + push {r1, r4,r5} + + mrc p15, 0, r1, c0, c0, 5 + and r1, r1, #0xff + lsl r1, r1, #2 + + read_sctlr r4 + bic r4, r4, #0x5 + ldr r5, =atf_sctlr + add r5, r5, r1 + str r4, [r5] + read_cpsr r4 + ldr r5, =atf_cpsr + add r5, r5, r1 + str r4, [r5] + + read_scr r4 + ldr r5, =atf_scr + str r4, [r5] + read_vbar r4 + ldr r5, =atf_vbar + str r4, [r5] + read_mair0 r4 + ldr r5, =atf_mair0 + str r4, [r5] + read_mair1 r4 + ldr r5, =atf_mair1 + str r4, [r5] + read_dacr r4 + ldr r5, =atf_dacr + str r4, [r5] + read_ttbcr r4 + ldr r5, =atf_ttbcr + str r4, [r5] + read_mvbar r4 + ldr r5, =atf_mvbar + str r4, [r5] + read_ttbr0 r4 + ldr r5, =atf_ttbr0 + str r4, [r5] + read_ttbr1 r4 + ldr r5, =atf_ttbr1 + str r4, [r5] + pop {r1, r4,r5} + bx lr +endfunc save_atf_sysreg + + +/* + * + */ +func restore_atf_sysreg + push {r1,r9,r10} + + mrc p15, 0, r1, c0, c0, 5 + and r1, r1, #0xff + lsl r1, r1, #2 + + ldr r9, =atf_sctlr + add r9, r9, r1 + ldr r10, [r9] + write_sctlr r10 + ldr r9, =atf_cpsr + add r9, r9, r1 + ldr r10, [r9] + write_cpsr r10 + + ldr r9, =atf_scr + ldr r10, [r9] + write_scr r10 + ldr r9, =atf_vbar + ldr r10, [r9] + write_vbar r10 + ldr r9, =atf_mair0 + ldr r10, [r9] + write_mair0 r10 + ldr r9, =atf_mair1 + ldr r10, [r9] + write_mair1 r10 + ldr r9, =atf_dacr + ldr r10, [r9] + write_dacr r10 + ldr r9, =atf_ttbcr + ldr r10, [r9] + write_ttbcr r10 + ldr r9, =atf_mvbar + ldr r10, [r9] + write_mvbar r10 + ldr r9, =atf_ttbr0 + ldr r10, [r9] + write_ttbr0 r10 + ldr r9, =atf_ttbr1 + ldr r10, [r9] + write_ttbr1 r10 + + invalidate_tlb r10 + + pop {r1,r9,r10} + bx lr +endfunc restore_atf_sysreg + + +.section .data +atf_cpsr: +.word 0x1234 +.word 0x1234 +.word 0x1234 +.word 0x1234 +atf_sctlr: +.word 0x1234 +.word 0x1234 +.word 0x1234 +.word 0x1234 + +atf_scr: +.word 0x1234 +atf_vbar: +.word 0x1234 +atf_mair0: +.word 0x1234 +atf_mair1: +.word 0x1234 +atf_dacr: +.word 0x1234 +atf_ttbcr: +.word 0x1234 +atf_mvbar: +.word 0x1234 +atf_ttbr0: +.word 0x1234 +atf_ttbr1: +.word 0x1234 + +#endif diff --git a/plat/bcm/aarch32/pl310_a32.S b/plat/bcm/aarch32/pl310_a32.S new file mode 100644 index 00000000..4787490b --- /dev/null +++ b/plat/bcm/aarch32/pl310_a32.S @@ -0,0 +1,252 @@ +/* SPDX-License-Identifier: BSD-2-Clause */ +/* + * Copyright (c) 2014, STMicroelectronics International N.V. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ +#include +#include +#include + +#define PL310_LOCKDOWN_NBREGS 8 +#define PL310_LOCKDOWN_SZREG 4 + +#define PL310_8WAYS_MASK 0x00FF +#define PL310_16WAYS_UPPERMASK 0xFF00 + + .globl arm_cl2_lockallways + .globl arm_cl2_cleaninvbyway + .globl arm_cl2_invbyway + .globl arm_cl2_cleanbyway + .globl arm_cl2_cleanbypa + .globl arm_cl2_invbypa + .globl arm_cl2_cleaninvbypa +/* + * void arm_cl2_lockallways(vaddr_t base) + * + * lock all L2 caches ways for data and instruction + */ +func arm_cl2_lockallways + add r1, r0, #PL310_DCACHE_LOCKDOWN_BASE + ldr r2, [r0, #PL310_AUX_CTRL] + tst r2, #PL310_AUX_16WAY_BIT + mov r2, #PL310_8WAYS_MASK + orrne r2, #PL310_16WAYS_UPPERMASK + mov r0, #PL310_LOCKDOWN_NBREGS +1: /* lock Dcache and Icache */ + str r2, [r1], #PL310_LOCKDOWN_SZREG + str r2, [r1], #PL310_LOCKDOWN_SZREG + subs r0, r0, #1 + bne 1b + + mov pc, lr +endfunc arm_cl2_lockallways + +/* + * Set sync operation mask according to ways associativity. + * Preserve r0 = pl310 iomem base address + */ +.macro syncbyway_set_mask reg + ldr \reg, [r0, #PL310_AUX_CTRL] + tst \reg, #PL310_AUX_16WAY_BIT + mov \reg, #PL310_8WAYS_MASK + orrne \reg, \reg, #PL310_16WAYS_UPPERMASK +.endm + +/* + * void arm_cl2_cleaninvbyway(vaddr_t base) + * clean & invalidate the whole L2 cache. + */ +func arm_cl2_cleaninvbyway + + syncbyway_set_mask r1 + str r1, [r0, #PL310_FLUSH_BY_WAY] + + /* Wait for all cache ways to be cleaned and invalidated */ +loop_cli_way_done: + ldr r2, [r0, #PL310_FLUSH_BY_WAY] + and r2, r2, r1 + cmp r2, #0 + bne loop_cli_way_done + + /* Cache Sync */ + + /* + * Wait for writing cache sync + * To PL310, Cache sync is atomic opertion, no need to check + * the status. For PL220, this check is needed. Keeping the loop + * for PL310 is no harm for PL310. + */ +loop_cli_sync: + ldr r1, [r0, #PL310_SYNC] + cmp r1, #0 + bne loop_cli_sync + + mov r1, #0 + str r1, [r0, #PL310_SYNC] + +loop_cli_sync_done: + ldr r1, [r0, #PL310_SYNC] + cmp r1, #0 + bne loop_cli_sync_done + + mov pc, lr +endfunc arm_cl2_cleaninvbyway + +/* void arm_cl2_invbyway(vaddr_t base) */ +func arm_cl2_invbyway + + syncbyway_set_mask r1 + str r1, [r0, #PL310_INV_BY_WAY] + +loop_inv_way_done: + ldr r2, [r0, #PL310_INV_BY_WAY] + and r2, r2, r1 + cmp r2, #0 + bne loop_inv_way_done + +loop_inv_way_sync: + ldr r1, [r0, #PL310_SYNC] + cmp r1, #0 + bne loop_inv_way_sync + + mov r1, #0 + str r1, [r0, #PL310_SYNC] + +loop_inv_way_sync_done: + ldr r1, [r0, #PL310_SYNC] + cmp r1, #0 + bne loop_inv_way_sync_done + + mov pc, lr +endfunc arm_cl2_invbyway + +/* void arm_cl2_cleanbyway(vaddr_t base) */ +func arm_cl2_cleanbyway + + syncbyway_set_mask r1 + str r1, [r0, #PL310_CLEAN_BY_WAY] + +loop_cl_way_done: + ldr r2, [r0, #PL310_CLEAN_BY_WAY] + and r2, r2, r1 + cmp r2, #0 + bne loop_cl_way_done + +loop_cl_way_sync: + ldr r1, [r0, #PL310_SYNC] + cmp r1, #0 + bne loop_cl_way_sync + + mov r1, #0 + str r1, [r0, #PL310_SYNC] + +loop_cl_way_sync_done: + ldr r1, [r0, #PL310_SYNC] + cmp r1, #0 + bne loop_cl_way_sync_done + + mov pc, lr +endfunc arm_cl2_cleanbyway + +/* + * void _arm_cl2_xxxbypa(vaddr_t pl310_base, paddr_t start, paddr_t end, + * int pl310value); + * pl310value is one of PL310_CLEAN_BY_PA, PL310_INV_BY_PA or PL310_FLUSH_BY_PA + */ +func _arm_cl2_xxxbypa + /* Align start address on PL310 line size */ + and r1, #(~(PL310_LINE_SIZE - 1)) +#ifdef SCU_BASE + /* + * ARM ERRATA #764369 + * Undocummented SCU Diagnostic Control Register + */ + /* + * NOTE: + * We're assuming that if mmu is enabled PL310_BASE and SCU_BASE + * still have the same relative offsets from each other. + */ + sub r0, r0, #(PL310_BASE - SCU_BASE) + mov r12, #1 + str r12, [r0, #SCU_ERRATA744369] + dsb + add r0, r0, #(PL310_BASE - SCU_BASE) +#endif +loop_cl2_xxxbypa: + str r1, [r0, r3] + +loop_xxx_pa_done: + ldr r12, [r0, r3] + and r12, r12, r1 + cmp r12, #0 + bne loop_xxx_pa_done + + add r1, r1, #PL310_LINE_SIZE + cmp r2, r1 + bpl loop_cl2_xxxbypa + +loop_xxx_pa_sync: + ldr r12, [r0, #PL310_SYNC] + cmp r12, #0 + bne loop_xxx_pa_sync + + mov r12, #0 + str r12, [r0, #PL310_SYNC] + +loop_xxx_pa_sync_done: + ldr r12, [r0, #PL310_SYNC] + cmp r12, #0 + bne loop_xxx_pa_sync_done + + mov pc, lr +endfunc _arm_cl2_xxxbypa + +/* + * void _arm_cl2_cleanbypa(vaddr_t pl310_base, paddr_t start, paddr_t end); + * clean L2 cache by physical address range. + */ +func arm_cl2_cleanbypa + mov r3, #PL310_CLEAN_BY_PA + b _arm_cl2_xxxbypa +endfunc arm_cl2_cleanbypa + +/* + * void arm_cl2_invbypa(vaddr_t pl310_base, paddr_t start, paddr_t end); + * invalidate L2 cache by physical address range. + */ +func arm_cl2_invbypa + mov r3, #PL310_INV_BY_PA + b _arm_cl2_xxxbypa +endfunc arm_cl2_invbypa + +/* + * void arm_cl2_cleaninvbypa(vaddr_t pl310_base, paddr_t start, paddr_t end); + * clean and invalidate L2 cache by physical address range. + */ +func arm_cl2_cleaninvbypa + mov r3, #PL310_FLUSH_BY_PA + b _arm_cl2_xxxbypa +endfunc arm_cl2_cleaninvbypa + diff --git a/plat/bcm/aarch32/plat_helpers.S b/plat/bcm/aarch32/plat_helpers.S new file mode 100644 index 00000000..6b7447a5 --- /dev/null +++ b/plat/bcm/aarch32/plat_helpers.S @@ -0,0 +1,115 @@ +#include +#include +#include + + .globl plat_is_my_cpu_primary + .globl plat_secondary_cold_boot_setup + +#define NSACR_SMP (1 << 18) +#define CORTEX_A15_ACTLR_INV_BTB_BIT (U(1) << 0) + +func cortex_a9_errata_report + bx lr +endfunc cortex_a9_errata_report + +func cortex_a7_errata_report + bx lr +endfunc cortex_a7_errata_report + +func cortex_a15_errata_report + bx lr +endfunc cortex_a15_errata_report + +func plat_is_my_cpu_primary + mov r0, #1 + isb + nop + bx lr +endfunc plat_is_my_cpu_primary + +func plat_secondary_cold_boot_setup + b . + bx lr +endfunc plat_secondary_cold_boot_setup + +func cortex_reset_func +#define SCTLR_M (1 << 0) +#define SCTLR_A (1 << 1) +#define SCTLR_D (1 << 2) +#define SCTLR_I (1 << 12) + mrc p15, 0, r0, c1, c0, 0 + mov r1, #SCTLR_I + orr r1, r1, #SCTLR_A + orr r1, r1, #SCTLR_D + orr r1, r1, #SCTLR_M + bic r0, r0, r1 + mcr p15, 0, r0, c1, c0, 0 + isb + + // Invalidate TLB, ICache and Branch predictor + mcr p15, 0, r0, c8, c7, 0 + mcr p15, 0, r0, c7, c5, 0 + mcr p15, 0, r0, c7, c5, 6 + + // set non-secure ACR. Allow SMP, L2ERR, CP10 and CP11 and Enable Neon/VFP bit for non-secure mode + movw r0, #0x0c00 + movt r0, #0x0006 + mcr p15, 0, r0, c1, c1, 2 + // Allow non-secure access to ACR + ldr r1,=NSACR_SMP +#if defined(PLATFORM_FLAVOR_63138) + // Cortex A9 specific quirks +#define PLEAUR_EN (1 << 0) +#define NSACR_PLE (1 << 16) + mov r2, #PLEAUR_EN + mcr p15, 0, r2, c11, c1, 0 + orr r1, r1, #NSACR_PLE +#endif + ldcopr r0, NSACR + orr r0, r0, r1 + stcopr r0, NSACR + + mrc p15, 0, r1, c1, c0, 1 +#if defined(PLATFORM_FLAVOR_63138) + /* Enable SMP and FW */ + orr r1, r1, #0x41 +#else + /* Enable SMP */ + orr r1, r1, #0x40 +#endif + mcr p15, 0, r1, c1, c0, 1 + isb +#if defined(PLATFORM_FLAVOR_63148) + ldcopr r1, ACTLR + orr r1, #CORTEX_A15_ACTLR_INV_BTB_BIT + stcopr r1, ACTLR +#endif + bx lr +endfunc cortex_reset_func + + +func cortex_core_pwr_dwn + bx lr +endfunc cortex_core_pwr_dwn + +func cortex_cluster_pwr_dwn + bx lr +endfunc cortex_cluster_pwr_dwn + +#if defined(PLATFORM_FLAVOR_63138) +declare_cpu_ops cortex_a9, 0x4100C090, \ + cortex_reset_func, \ + cortex_core_pwr_dwn, \ + cortex_cluster_pwr_dwn +#elif defined(PLATFORM_FLAVOR_63148) +declare_cpu_ops cortex_a15, 0x420000F0, \ + cortex_reset_func, \ + cortex_core_pwr_dwn, \ + cortex_cluster_pwr_dwn +#else +declare_cpu_ops cortex_a7, 0x4100C070, \ + cortex_reset_func, \ + cortex_core_pwr_dwn, \ + cortex_cluster_pwr_dwn +#endif + diff --git a/plat/bcm/aarch64/plat_helpers.S b/plat/bcm/aarch64/plat_helpers.S new file mode 100644 index 00000000..3614559c --- /dev/null +++ b/plat/bcm/aarch64/plat_helpers.S @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include + + .globl plat_my_core_pos + .globl plat_get_my_entrypoint + .globl platform_mem_init + .globl plat_bcm_calc_core_pos + .globl plat_crash_console_init + .globl plat_crash_console_putc + .globl plat_secondary_cold_boot_setup + .globl plat_get_my_entrypoint + .globl plat_is_my_cpu_primary + .globl plat_crash_console_flush + + +func console_core_init + ret +endfunc console_core_init + +func console_core_putc + ret +endfunc console_core_putc + +func plat_crash_console_flush + ret +endfunc plat_crash_console_flush + + +func plat_my_core_pos + mrs x0, mpidr_el1 + b plat_bcm_calc_core_pos +endfunc plat_my_core_pos + +/* + * unsigned int plat_bcm_calc_core_pos(u_register_t mpidr); + * With this function: CorePos = (ClusterId * 4) + CoreId + */ +func plat_bcm_calc_core_pos + and x1, x0, #MPIDR_CPU_MASK + and x0, x0, #MPIDR_CLUSTER_MASK + add x0, x1, x0, LSR #6 + ret +endfunc plat_bcm_calc_core_pos + + /* ----------------------------------------------------- + * unsigned int plat_is_my_cpu_primary (void); + * + * Find out whether the current cpu is the primary + * cpu. + * ----------------------------------------------------- + */ +func plat_is_my_cpu_primary + mrs x0, mpidr_el1 + and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK) + cmp x0, #BRCM_PRIMARY_CPU + cset w0, eq + ret +endfunc plat_is_my_cpu_primary + + /* ----------------------------------------------------- + * void plat_secondary_cold_boot_setup (void); + * + * This function performs any platform specific actions + * needed for a secondary cpu after a cold reset e.g + * mark the cpu's presence, mechanism to place it in a + * holding pen etc. + * ----------------------------------------------------- + */ +func plat_secondary_cold_boot_setup + ret +endfunc plat_secondary_cold_boot_setup + +func plat_get_my_entrypoint + /* TODO support warm boot */ + mov x0, #0 + ret +endfunc plat_get_my_entrypoint + +func platform_mem_init + ret +endfunc platform_mem_init + + /* --------------------------------------------- + * int plat_crash_console_init(void) + * Function to initialize the crash console + * without a C Runtime to print crash report. + * Clobber list : x0, x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_init + mov_imm x0, PLAT_BCM_CRASH_UART_BASE + mov_imm x1, PLAT_BCM_CRASH_UART_CLK_IN_HZ + mov_imm x2, PLAT_BCM_CONSOLE_BAUDRATE + b console_core_init +endfunc plat_crash_console_init + + /* --------------------------------------------- + * int plat_crash_console_putc(int c) + * Function to print a character on the crash + * console without a C Runtime. + * Clobber list : x1, x2 + * --------------------------------------------- + */ +func plat_crash_console_putc + mov_imm x1, PLAT_BCM_CRASH_UART_BASE + b console_core_putc +endfunc plat_crash_console_putc + + diff --git a/plat/bcm/bcm_gic.c b/plat/bcm/bcm_gic.c new file mode 100644 index 00000000..57edbc21 --- /dev/null +++ b/plat/bcm/bcm_gic.c @@ -0,0 +1,85 @@ +/* +<:copyright-BRCM:2012:DUAL/GPL:standard + + Copyright (c) 2012 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#include +#include +#include +#include + +uint32_t plat_ic_get_pending_interrupt_id(void) +{ + return gicv2_get_pending_interrupt_id(); +} + +uint32_t plat_ic_get_pending_interrupt_type(void) +{ + return gicv2_get_pending_interrupt_type(); +} + +uint32_t plat_ic_acknowledge_interrupt(void) +{ + return gicv2_acknowledge_interrupt(); +} + +uint32_t plat_ic_get_interrupt_type(uint32_t id) +{ + uint32_t group; + + group = gicv2_get_interrupt_group(id); + + /* Assume that all secure interrupts are S-EL1 interrupts */ + if (!group) + return INTR_TYPE_S_EL1; + else + return INTR_TYPE_NS; + +} + +void plat_ic_end_of_interrupt(uint32_t id) +{ + gicv2_end_of_interrupt(id); +} + +uint32_t plat_interrupt_type_to_line(uint32_t type, + uint32_t security_state) +{ + assert(type == INTR_TYPE_S_EL1 || + type == INTR_TYPE_EL3 || + type == INTR_TYPE_NS); + + assert(sec_state_is_valid(security_state)); + + /* Non-secure interrupts are signalled on the IRQ line always */ + if (type == INTR_TYPE_NS) + return __builtin_ctz(SCR_IRQ_BIT); + + /* + * Secure interrupts are signalled using the IRQ line if the FIQ_EN + * bit is not set else they are signalled using the FIQ line. + */ + if (gicv2_is_fiq_enabled()) + return __builtin_ctz(SCR_FIQ_BIT); + else + return __builtin_ctz(SCR_IRQ_BIT); +} + diff --git a/plat/bcm/bcm_private.h b/plat/bcm/bcm_private.h new file mode 100644 index 00000000..d32e9820 --- /dev/null +++ b/plat/bcm/bcm_private.h @@ -0,0 +1,37 @@ +/* +<:copyright-BRCM:2012:DUAL/GPL:standard + + Copyright (c) 2012 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef __BCM_PRIVATE_H +#define __BCM_PRIVATE_H + +void bcm_configure_mmu_el3(unsigned long total_base, unsigned long total_size, + unsigned long ro_start, unsigned long ro_limit, + unsigned long coh_start, unsigned long coh_limit); + +void plat_bcm_io_setup(void); +unsigned int plat_bcm_calc_core_pos(u_register_t mpidr); + +int dt_add_psci_node(void *fdt); +int dt_add_psci_cpu_enable_methods(void *fdt); + +#endif /*__BCM_PRIVATE_H*/ diff --git a/plat/bcm/brcm_bl31_setup.c b/plat/bcm/brcm_bl31_setup.c new file mode 100644 index 00000000..9cb44d13 --- /dev/null +++ b/plat/bcm/brcm_bl31_setup.c @@ -0,0 +1,286 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define BL31_END (uintptr_t)(&__BL31_END__) + +#define MAP_BL31_TOTAL MAP_REGION_FLAT( \ + BL31_BASE, \ + BL31_END - BL31_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) + +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +/* + * Placeholder variables for copying the arguments that have been passed to + * BL31 from BL2. + */ +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +static uintptr_t ns_entry_point; + +#define DEVICE_BASE 0x80000000 +#define DEVICE_SIZE 0x00010000 + +const mmap_region_t plat_arm_mmap[] = { + MAP_REGION_FLAT(DEVICE_BASE, DEVICE_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(GICD_BASE, DEVICE_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(UART0_BASE, UART0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#if defined(BIUCFG_BASE) + MAP_REGION_FLAT(BIUCFG_BASE, BIUCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#elif defined(BIUCTRL_BASE) + MAP_REGION_FLAT(BIUCTRL_BASE, BIUCTRL_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#endif + MAP_REGION_FLAT(BOOTLUT_BASE, BOOTLUT_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#if defined(WDTIMR0_BASE) + MAP_REGION_FLAT(WDTIMR_BASE, WDTIMR_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#endif + MAP_REGION_FLAT(PMC_BASE, PMC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + {0} +}; + + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for the + * security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(sec_state_is_valid(type)); + next_image_info = (type == NON_SECURE) + ? &bl33_image_ep_info : &bl32_image_ep_info; + /* + * None of the images on the ARM development platforms can have 0x0 + * as the entrypoint + */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * Obtain ns entry point + ******************************************************************************/ +uintptr_t plat_get_ns_image_entrypoint(void) +{ + return ns_entry_point; +} + +/******************************************************************************* + * Set ns-entry point + ******************************************************************************/ +void plat_set_ns_image_entrypoint(uintptr_t entry_point) +{ + ns_entry_point = entry_point; +} + + +struct atf_image_info { + struct param_header h; + uintptr_t image_base; /* physical address of base of image */ + uint32_t image_size; /* bytes read from image file */ +}; + +struct atf_entry_point_info { + struct param_header h; + uintptr_t pc; + uint32_t spsr; + struct aapcs64_params args; +}; + +typedef struct bl31_params { + param_header_t h; + struct atf_image_info *bl31_image_info; + struct atf_entry_point_info *bl32_ep_info; + struct atf_image_info *bl32_image_info; + struct atf_entry_point_info *bl33_ep_info; + struct atf_image_info *bl33_image_info; +} bl31_params_t; + +/******************************************************************************* + * Perform any BL31 early platform setup common to ARM standard platforms. + * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 + * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be + * done before the MMU is initialized so that the memory layout can be used + * while creating page tables. BL2 has flushed this information to memory, so + * we are guaranteed to pick up good data. + ******************************************************************************/ +void arm_bl31_early_platform_setup(void *param0, uintptr_t plat_params_from_bl2, uintptr_t arg2, void * arg43) +{ + bl31_params_t *from_bl2 = (bl31_params_t *)param0; + +#ifdef BL32_BASE + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry(); + /* Provide boot parameters to OPTEE */ + memset(&bl32_image_ep_info.args, 0, sizeof(aapcs64_params_t)); + bl32_image_ep_info.args.arg0 = MODE_RW_64; + bl32_image_ep_info.args.arg2 = (u_register_t)plat_params_from_bl2; +#endif /* BL32_BASE */ + + /* Populate entry point information for BL33 */ + SET_PARAM_HEAD(&bl33_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + + /* Configure ns entry point */ + plat_set_ns_image_entrypoint(from_bl2->bl33_ep_info->pc); + + /* + * Tell BL31 where the non-trusted software image + * is located and the entry state information + */ + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + + bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + + /* + * Provide Linux DTB address + */ + bl33_image_ep_info.args.arg0 = (u_register_t)from_bl2; + bl33_image_ep_info.args.arg1 = (u_register_t)plat_get_ns_image_entrypoint(); +} + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, + u_register_t arg3) +{ + arm_bl31_early_platform_setup((void*)arg0, (uintptr_t)arg1, arg2, (void*)arg3); +} + +#define PLATFORM_G1S_PROPS(grp) \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL) + + +static const interrupt_prop_t irq_sec_array[] = { + PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0) +}; + +static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; + +static const struct gicv2_driver_data plat_gicv2_driver_data = { + .gicd_base = GICD_BASE, + .gicc_base = GICC_BASE, + .interrupt_props = irq_sec_array, + .interrupt_props_num = ARRAY_SIZE(irq_sec_array), + .target_masks = target_mask_array, + .target_masks_num = ARRAY_SIZE(target_mask_array), +}; + +/******************************************************************************* + * Perform any BL31 platform setup common to ARM standard platforms + ******************************************************************************/ +void arm_bl31_platform_setup(void) +{ + /* Initialize the gic cpu and distributor interfaces */ + gicv2_driver_init(&plat_gicv2_driver_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +} + +/******************************************************************************* + * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM + * standard platforms + ******************************************************************************/ +void arm_bl31_plat_runtime_setup(void) +{ + /* Initialize the runtime functions */ +} + +void bl31_platform_setup(void) +{ + arm_bl31_platform_setup(); +} + +void bl31_plat_runtime_setup(void) +{ + arm_bl31_plat_runtime_setup(); +} + +/******************************************************************************* + * Perform the very early platform specific architectural setup shared between + * ARM standard platforms. This only does basic initialization. Later + * architectural setup (bl31_arch_setup()) does not do anything platform + * specific. + ******************************************************************************/ +void arm_bl31_plat_arch_setup(void) +{ + const mmap_region_t bl_regions[] = { + MAP_BL31_TOTAL, + ARM_MAP_BL_RO, +#if USE_COHERENT_MEM + ARM_MAP_BL_COHERENT_RAM, +#endif + {0} + }; + + setup_page_tables(bl_regions, plat_arm_get_mmap()); + + generic_delay_timer_init(); + + enable_mmu_el3(0); +} + +void bl31_plat_arch_setup(void) +{ + arm_bl31_plat_arch_setup(); +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} diff --git a/plat/bcm/brcm_bl32_setup.c b/plat/bcm/brcm_bl32_setup.c new file mode 100644 index 00000000..c86fe1b6 --- /dev/null +++ b/plat/bcm/brcm_bl32_setup.c @@ -0,0 +1,485 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \ + BL32_BASE, \ + BL32_END - BL32_BASE, \ + MT_MEMORY | MT_RW | MT_SECURE) + +#define ARM_MAP_BL_RO MAP_REGION_FLAT( \ + BL_CODE_BASE, \ + BL_CODE_END - BL_CODE_BASE, \ + MT_CODE | MT_SECURE) + +#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ + BL_COHERENT_RAM_BASE, \ + BL_COHERENT_RAM_END \ + - BL_COHERENT_RAM_BASE, \ + MT_DEVICE | MT_RW | MT_SECURE) + +struct atf_image_info { + struct param_header h; + uintptr_t image_base; /* physical address of base of image */ + uint32_t image_size; /* bytes read from image file */ +}; + +struct atf_entry_point_info { + struct param_header h; + uintptr_t pc; + uint32_t spsr; + struct aapcs64_params args; +}; + +typedef struct bl31_params { + param_header_t h; + struct atf_image_info *bl31_image_info; + struct atf_entry_point_info *bl32_ep_info; + struct atf_image_info *bl32_image_info; + struct atf_entry_point_info *bl33_ep_info; + struct atf_image_info *bl33_image_info; +} bl31_params_t; + + +#define BL32_END (uintptr_t)(&__BL32_END__) +#define DEVICE_BASE 0x80000000 +#define DEVICE_SIZE 0x00010000 + + +#define DESC_DOMAIN(x) ((x << 5) & 0x000001E0) +// section descriptor definitions +#define SECTION_AP 0xc00 +#define SECTION_XN 0x10 +#define SECTION_PXN 0x1 +/* A9 does not support PXN */ +#define SECTION_XN_ALL (SECTION_XN) +#define SECTION_SHAREABLE (1 << 16) +#define SECTION_SUPER_DESC (1 << 18) +#define SECTION_DESC_NS (1 << 19) +// TEX[2] = 1 +#define SECTION_OUTER_NC_INNER_WBWA 0x00004006 +#define SECTION_OUTER_WBNWA_INNER_WBWA 0x00007006 +#define SECTION_OUTER_WTNWA_INNER_WBWA 0x00006006 +#define SECTION_OUTER_WBWA_INNER_NC 0x00005002 +// TEX[2] = 0, OUTER & INNER are same all the time +#define SECTION_OUTER_WBWA_INNER_WBWA 0x0000100E +#define SECTION_OUTER_NSD_INNER_NSD 0x00002002 +#define SECTION_OUTER_NC_INNER_NC 0x00001002 +#define SECTION_OUTER_WTNWA_INNER_WTNWA 0x0000000A +#define SECTION_OUTER_WBNWA_INNER_WBNWA 0x0000000E +#define SECTION_OUTER_SO_INNER_SO 0x00000002 +#define SECTION_OUTER_SD_INNER_SD 0x00000006 + +// definition for common section attribute +#define SECTION_ATTR_INVALID 0x0 +#define SECTION_ATTR_CACHED_MEM \ + (SECTION_OUTER_WBWA_INNER_WBWA|SECTION_AP|DESC_DOMAIN(0)|SECTION_SHAREABLE) +#define SECTION_ATTR_NONCACHED_MEM \ + (SECTION_OUTER_NC_INNER_NC|SECTION_AP|DESC_DOMAIN(0)) +#define SECTION_ATTR_DEVICE \ + (SECTION_OUTER_NSD_INNER_NSD|SECTION_AP|SECTION_XN_ALL|DESC_DOMAIN(0)) +#define SECTION_ATTR_DEVICE_EXEC \ + (SECTION_OUTER_NSD_INNER_NSD|SECTION_AP|DESC_DOMAIN(0)) + +#define SCU_INV_CTRL_INIT 0xFFFF +#define SCU_SAC_CTRL_INIT 0xF +#define SCU_NSAC_CTRL_INIT 0xFFF +#define SCU_INV_SEC 0x0C +#define SCU_SAC 0x50 +#define SCU_NSAC 0x54 +#define SCU_CTRL 0x0 + +extern void a9_mmu_invalidate_tlb(void); +extern void a9_mmu_enable(void); +extern void a9_l1cache_enable_i(void); +extern void a9_l1cache_enable_d(void); +extern void a9_mmu_set_ttbr(char* table_base); +extern void a9_gic_secure_init(void); +extern void arm_cl2_invbyway(uint32_t); +/* + * Placeholder variables for copying the arguments that have been passed to + * BL31 from BL2. + */ +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; +static uintptr_t ns_entry_point; + +#if defined (PLATFORM_FLAVOR_63138) +char mmu_table[1024*16] __attribute__((aligned(4096*4))); +#endif + +const mmap_region_t plat_arm_mmap[] = { + MAP_REGION_FLAT(DEVICE_BASE, DEVICE_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + MAP_REGION_FLAT(GICD_BASE, DEVICE_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#if UART0_BASE + MAP_REGION_FLAT(UART0_BASE, UART0_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#endif +#if defined(BIUCFG_BASE) + MAP_REGION_FLAT(BIUCFG_BASE, BIUCFG_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#elif defined(BIUCTRL_BASE) + MAP_REGION_FLAT(BIUCTRL_BASE, BIUCTRL_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#endif +#if defined(BOOTLUT_BASE) + MAP_REGION_FLAT(BOOTLUT_BASE, BOOTLUT_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#endif +#if defined(PL310_BASE) + MAP_REGION_FLAT(PL310_BASE, PL310_MAP_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#endif +#if defined(B15_CTRL_BASE) + MAP_REGION_FLAT(B15_CTRL_BASE, B15_CTRL_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#endif +#if defined(TIMR_BASE) + MAP_REGION_FLAT(TIMR_BASE, TIMR_SIZE, MT_DEVICE | MT_RW | MT_SECURE), +#endif + MAP_REGION_FLAT(PMC_BASE, PMC_SIZE, MT_DEVICE | MT_RW | MT_SECURE), + {0} +}; + + +#if defined(PL310_BASE) +void a9_cl2_config(void) +{ + /* Disable PL310 */ + uint32_t pl310_base = PL310_BASE; + mmio_write_32(pl310_base + PL310_CTRL, 0); + mmio_write_32(pl310_base + PL310_DATA_RAM_CTRL, PL310_DATA_RAM_CTRL_INIT); + mmio_write_32(pl310_base + PL310_AUX_CTRL, PL310_AUX_CTRL_INIT); + + /* invalidate all cache ways */ + arm_cl2_invbyway(pl310_base); +} +#endif + + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for the + * security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) +{ + entry_point_info_t *next_image_info; + + assert(sec_state_is_valid(type)); + next_image_info = (type == NON_SECURE) + ? &bl33_image_ep_info : &bl32_image_ep_info; + /* + * None of the images on the ARM development platforms can have 0x0 + * as the entrypoint + */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + +/******************************************************************************* + * Obtain ns entry point + ******************************************************************************/ +uintptr_t plat_get_ns_image_entrypoint(void) +{ + return ns_entry_point; +} + +/******************************************************************************* + * Set ns-entry point + ******************************************************************************/ +void plat_set_ns_image_entrypoint(uintptr_t entry_point) +{ + ns_entry_point = entry_point; +} + +/******************************************************************************* + * Return a pointer to the 'entry_point_info' structure of the next image for the + * security state specified. BL33 corresponds to the non-secure image type + * while BL32 corresponds to the secure image type. A NULL pointer is returned + * if the image does not exist. + ******************************************************************************/ +entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) +{ + entry_point_info_t *next_image_info; + + next_image_info = &bl33_image_ep_info; + + /* + * None of the images on the ARM development platforms can have 0x0 + * as the entrypoint + */ + if (next_image_info->pc) + return next_image_info; + else + return NULL; +} + + +void arm_sp_min_early_platform_setup ( void *plat_params, uintptr_t tos_fw_config, + uintptr_t hw_config, void *plat_params_from_bl2 ) +{ + bl31_params_t *from_bl2 = (bl31_params_t*)plat_params; + + if (plat_my_core_pos() != 0){ + plat_panic_handler(); + } + +#if defined(SCU_BASE) + mmio_write_32(SCU_BASE + SCU_INV_SEC, SCU_INV_CTRL_INIT); + mmio_write_32(SCU_BASE + SCU_SAC, SCU_SAC_CTRL_INIT); + mmio_write_32(SCU_BASE + SCU_NSAC, SCU_NSAC_CTRL_INIT); + /* SCU enable */ + mmio_write_32(SCU_BASE + SCU_CTRL, 0x1); +#endif + +#if defined(PL310_BASE) + a9_cl2_config(); +#endif + + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL322_BASE; + bl32_image_ep_info.spsr = MODE32_svc << MODE32_SHIFT; + /* Provide boot parameters to OPTEE */ + memset(&bl32_image_ep_info.args, 0, sizeof(aapcs32_params_t)); + bl32_image_ep_info.args.arg0 = (u_register_t)plat_params_from_bl2; + + /* Populate entry point information for BL33 */ + SET_PARAM_HEAD(&bl33_image_ep_info, + PARAM_EP, + VERSION_1, + 0); + + /* Configure ns entry point */ + plat_set_ns_image_entrypoint(from_bl2->bl33_ep_info->pc); + + /* + * Tell SP_MIN where the non-trusted software image + * is located and the entry state information + */ + bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); + bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry() & ~(MODE32_MASK << MODE32_SHIFT); + /* Always enter in non-secure SVC mode */ + bl33_image_ep_info.spsr |= MODE32_svc << MODE32_SHIFT; + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); +} + +void sp_min_early_platform_setup(void *from_bl2, + void *plat_params_from_bl2) +{ + arm_sp_min_early_platform_setup(from_bl2, 0, 0, plat_params_from_bl2); +} + + +void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + sp_min_early_platform_setup((void *)arg0, (void *)arg1); +} + +#define PLATFORM_G1S_PROPS(grp) \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(BRCM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL) + +static const interrupt_prop_t irq_sec_array[] = { + PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0) +}; + +static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; + +const struct gicv2_driver_data plat_gicv2_driver_data = { + .gicd_base = GICD_BASE, + .gicc_base = GICC_BASE, + .interrupt_props = irq_sec_array, + .interrupt_props_num = ARRAY_SIZE(irq_sec_array), + .target_masks = target_mask_array, + .target_masks_num = ARRAY_SIZE(target_mask_array), +}; + +/******************************************************************************* + * Perform any BL32 platform setup common to ARM standard platforms + ******************************************************************************/ +void arm_bl32_platform_setup(void) +{ +#if defined (PLATFORM_FLAVOR_63138) + a9_gic_secure_init(); +#else + /* Initialize the gic cpu and distributor interfaces */ + gicv2_driver_init(&plat_gicv2_driver_data); + gicv2_distif_init(); + gicv2_pcpu_distif_init(); + gicv2_cpuif_enable(); +#endif +} + +/******************************************************************************* + * Perform any BL32 platform runtime setup prior to ARM standard platforms + ******************************************************************************/ +void arm_bl32_plat_runtime_setup(void) +{ + /* Initialize the runtime functions */ +} + +void sp_min_platform_setup(void) +{ + arm_bl32_platform_setup(); +} + +void sp_min_runtime_setup(void) +{ + arm_bl32_plat_runtime_setup(); +} + +#if defined (PLATFORM_FLAVOR_63138) +void a9_mmu_setup_region(uint32_t mem_addr, uint32_t mem_size, uint32_t mem_attr) +{ +#define size_mb(s) ((s + 0xFFFFF) / 0x100000) + register uint32_t table_base = (uint32_t)mmu_table; + register uint32_t table_size = sizeof(mmu_table); + + /* Align the address to MB and then adjust the size */ + mem_size += mem_addr & 0xFFFFF; + mem_addr &= ~0xFFFFF; + /* Convert the mem size in MB */ + mem_size = size_mb(mem_size); + + __asm__ volatile ("mov r0, %0" : : "r" (table_size) : "r0"); + __asm__ volatile ("push {r0}"); + __asm__ volatile ("mov r0, %0" : : "r" (mem_addr) : "r0"); + __asm__ volatile ("push {r0}"); + __asm__ volatile ("mov r0, %0" : : "r" (mem_attr) : "r0"); + __asm__ volatile ("push {r0}"); + __asm__ volatile ("mov r0, %0" : : "r" (mem_size) : "r0"); + __asm__ volatile ("push {r0}"); + __asm__ volatile ("mov r0, %0" : : "r" (mem_addr) : "r0"); + __asm__ volatile ("push {r0}"); + __asm__ volatile ("mov r0, %0" : : "r" (table_base) : "r0"); + __asm__ volatile ("push {r0}"); + __asm__ volatile ("pop {r0-r4,r6}"); + + __asm__ volatile ("bl a9_mmu_set_scn" ::: "lr"); +} + +void a9_bl32_plat_map_mmu(void) +{ + int i = 0; + int region_cnt = sizeof(plat_arm_mmap) / sizeof(mmap_region_t); + /* Initialize the mmu table */ + memset(mmu_table, 0, sizeof(mmu_table)); + /* Map the code/data section of ATF */ + a9_mmu_setup_region(BL32_BASE, BL32_END - BL32_BASE, SECTION_ATTR_CACHED_MEM); + for (i = 0; i < region_cnt - 1; i++ ){ + a9_mmu_setup_region((uint32_t)plat_arm_mmap[i].base_pa, plat_arm_mmap[i].size, SECTION_ATTR_DEVICE); + } +} + +void a9_bl32_plat_enable_mmu(void) +{ + a9_mmu_invalidate_tlb(); + a9_mmu_set_ttbr (mmu_table); + a9_mmu_enable(); + a9_l1cache_enable_i(); + a9_l1cache_enable_d(); + if (plat_my_core_pos() != 0){ + mmio_write_32(PL310_BASE + PL310_CTRL, 1); + } +} +#endif + +/******************************************************************************* + * Perform the very early platform specific architectural setup shared between + * ARM standard platforms. This only does basic initialization. Later + * architectural setup (bl31_arch_setup()) does not do anything platform + * specific. + ******************************************************************************/ +void arm_bl32_plat_arch_setup(void) +{ +#if defined (PLATFORM_FLAVOR_63138) + a9_bl32_plat_map_mmu(); + a9_bl32_plat_enable_mmu(); +#else + const mmap_region_t bl_regions[] = { + MAP_BL_SP_MIN_TOTAL, + ARM_MAP_BL_RO, +#if USE_COHERENT_MEM + ARM_MAP_BL_COHERENT_RAM, +#endif + {0} + }; + + generic_delay_timer_init(); + + setup_page_tables(bl_regions, plat_arm_get_mmap()); + + enable_mmu_svc_mon(0); +#endif + +#if defined(BIUCFG_BASE) && !(defined (PLATFORM_FLAVOR_63138) || defined (PLATFORM_FLAVOR_63148)) + /* Enable BUS access control for non-secure Linux */ + *(unsigned int*)(BIUCFG_BASE + 0x300) = 0xFF; +#endif +} + +void sp_min_plat_arch_setup(void) +{ + arm_bl32_plat_arch_setup(); +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return SYS_COUNTER_FREQ_IN_TICKS; +} + +int plat_bcm_calc_core_pos(int mpidr) +{ + return plat_arm_calc_core_pos(mpidr); +} diff --git a/plat/bcm/brcm_pm.c b/plat/bcm/brcm_pm.c new file mode 100644 index 00000000..5a207f8b --- /dev/null +++ b/plat/bcm/brcm_pm.c @@ -0,0 +1,261 @@ +/* +<:copyright-BRCM:2018:DUAL/GPL:standard + + Copyright (c) 2018 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern int pmc_cpu_core_power_up(int cpu); +extern int pmc_cpu_core_power_down(int cpu); +extern void pmc_initmode(void); +extern void udelay(uint32_t); +extern void sp_min_warm_entrypoint(void); +extern void gicv2_pcpu_distif_init(void); +extern void gicv2_cpuif_enable(void); +extern void a9_gic_secure_init(void); + +/* + * set specified CPU start address in the BIUCFG address space. + */ +#if defined (PLATFORM_FLAVOR_6858) && defined(BIUCFG_BASE) +#define BIUCFG_EP_LO(i) ((void*)BIUCFG_BASE + 0x120 + (i) * 4) +#else +#define BIUCFG_EP_LO(i) ((void*)BIUCFG_BASE + 0x120 + (i) * 8) +#define BIUCFG_EP_HI(i) ((void*)BIUCFG_BASE + 0x124 + (i) * 8) +#endif + +static void biu_set_cpu_ep(int cpu, long ep) +{ +#if defined(BIUCFG_BASE) +#if defined (PLATFORM_FLAVOR_6858) + writel(((u32)ep) >> 8, BIUCFG_EP_LO(cpu)); +#else + writeq(ep, BIUCFG_EP_LO(cpu)); +#endif +#elif defined(BIUCTRL_BASE) + BIUCTRL->power_cfg |= 1 << (cpu + BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON_SHIFT); + BIUCTRL->reset_cfg &= ~(0x1 << cpu); +#endif + +#if (!defined (PLATFORM_FLAVOR_6858) && !defined (PLATFORM_FLAVOR_6856)) +#if defined(BOOT_LUT) + BOOT_LUT->bootLutRst = (u32)ep; +#endif + +#if defined(BOOTLUT_BASE) + writel((u32)ep, (u32*)(BOOTLUT_BASE+0x20)); +#endif +#endif +} + +/******************************************************************************* + * Platform handler called to check the validity of the power state + * parameter. The power state parameter has to be a composite power state. + ******************************************************************************/ +static int brcm_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Platform handler called to check the validity of the non secure + * entrypoint. + ******************************************************************************/ +static int brcm_validate_ns_entrypoint(uintptr_t entrypoint) +{ + /* + * Check if the non secure entrypoint lies within the non + * secure DRAM. + */ + return PSCI_E_SUCCESS; +} + +/******************************************************************************* + * Platform handler called when a CPU is about to enter standby. + ******************************************************************************/ +static void brcm_cpu_standby(plat_local_state_t cpu_state) +{ + + assert(cpu_state == PLAT_LOCAL_STATE_RET); + + /* + * Enter standby state + * dsb is good practice before using wfi to enter low power states + */ + dsb(); + wfi(); +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned on. The + * mpidr determines the CPU to be turned on. + ******************************************************************************/ +static int brcm_pwr_domain_on(u_register_t mpidr) +{ + int rc = PSCI_E_SUCCESS; + + /* + * here it is assumed that CFE didn't start the CPUs. Set the + * CPU entry point and power the CPU up. + */ +#ifdef AARCH32 + biu_set_cpu_ep(mpidr & 0xff, (long)sp_min_warm_entrypoint); +#else + biu_set_cpu_ep(mpidr & 0xff, (long)bl31_warm_entrypoint); +#endif + if (pmc_cpu_core_power_up(mpidr & 0xff) < 0) + rc = PSCI_E_INTERN_FAIL; + return rc; +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void brcm_pwr_domain_off(const psci_power_state_t *target_state) +{ +#if defined (PLATFORM_FLAVOR_63138) + assert(0); +#else + gicv2_cpuif_disable(); +#endif +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be suspended. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +void brcm_pwr_domain_suspend(const psci_power_state_t *target_state) +{ + assert(0); +} + +/******************************************************************************* + * Platform handler called when a power domain has just been powered on after + * being turned off earlier. The target_state encodes the low power state that + * each level has woken up from. + ******************************************************************************/ +void brcm_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == + PLAT_LOCAL_STATE_OFF); + +#if defined (PLATFORM_FLAVOR_63138) + a9_gic_secure_init(); +#else + /* TODO: This setup is needed only after a cold boot */ + gicv2_pcpu_distif_init(); + + /* Enable the gic cpu interface */ + gicv2_cpuif_enable(); +#endif +} + +/******************************************************************************* + * Platform handler called when a power domain has just been powered on after + * having been suspended earlier. The target_state encodes the low power state + * that each level has woken up from. + ******************************************************************************/ +void brcm_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +{ + assert(0); +} + +/******************************************************************************* + * Platform handler called when a power domain is about to be turned off. The + * target_state encodes the power state that each level should transition to. + ******************************************************************************/ +__dead2 void brcm_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) +{ + int idx = plat_my_core_pos(); + + pmc_cpu_core_power_down(idx); + psci_power_down_wfi(); + + panic(); +} + +/******************************************************************************* + * Platform handlers to shutdown/reboot the system + ******************************************************************************/ +static void __dead2 brcm_system_off(void) +{ + ERROR("BRCM System Off: operation not handled.\n"); + panic(); +} + +static void __dead2 brcm_system_reset(void) +{ +#if defined(WDTIMR0_BASE) + INFO("performing system reset from PSCI.\n"); + +#if defined(AARCH32) && ! defined(PLATFORM_FLAVOR_6846) + WDTIMER0->WDTimerCtl = SOFT_RESET; +#else + WDTIMER0->SoftRst = SOFT_RESET; +#endif + /* + * delay 1 second before assuming reset has failed. + */ + udelay(1000 * 1000); + ERROR("watchdog system reset failed."); + panic(); +#elif defined(TIMR_BASE) + ((volatile Timer * const) (TIMR_BASE + TIMR_OFFSET))->SoftRst |= SOFT_RESET; +#endif + while(1); +} + +static const plat_psci_ops_t plat_brcm_psci_pm_ops = { + .cpu_standby = brcm_cpu_standby, + .pwr_domain_on = brcm_pwr_domain_on, + .pwr_domain_off = brcm_pwr_domain_off, + .pwr_domain_suspend = brcm_pwr_domain_suspend, + .pwr_domain_on_finish = brcm_pwr_domain_on_finish, + .pwr_domain_suspend_finish = brcm_pwr_domain_suspend_finish, + .pwr_domain_pwr_down_wfi = brcm_pwr_domain_pwr_down_wfi, + .system_off = brcm_system_off, + .system_reset = brcm_system_reset, + .validate_power_state = brcm_validate_power_state, + .validate_ns_entrypoint = brcm_validate_ns_entrypoint +}; + +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ +#if defined(PLATFORM_FLAVOR_63138) || defined (PMB_ADDR_ORION_CPU0) + pmc_initmode(); +#endif + + *psci_ops = &plat_brcm_psci_pm_ops; + + return 0; +} diff --git a/plat/bcm/drivers/io.h b/plat/bcm/drivers/io.h new file mode 100644 index 00000000..cc01b888 --- /dev/null +++ b/plat/bcm/drivers/io.h @@ -0,0 +1,80 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ +/* + * io.h for atf + * Created by on Thu Apr 18 19:26:20 2019 + */ + +#pragma once + +#include + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +static inline u64 readq(void *mem) +{ + return mmio_read_64((uintptr_t)mem); +} + +static inline u32 readl(void *mem) +{ + return mmio_read_32((uintptr_t)mem); +} + +static inline u16 readw(void *mem) +{ + return mmio_read_16((uintptr_t)mem); +} + +static inline u8 readb(void *mem) +{ + return mmio_read_8((uintptr_t)mem); +} + +static inline void writeq(u64 v, void *mem) +{ + return mmio_write_64((uintptr_t)mem, v); +} + +static inline void writel(u32 v, void *mem) +{ + return mmio_write_32((uintptr_t)mem, v); +} + +static inline void writew(u16 v, void *mem) +{ + return mmio_write_16((uintptr_t)mem, v); +} + +static inline void writeb(u8 v, void *mem) +{ + return mmio_write_8((uintptr_t)mem, v); +} diff --git a/plat/bcm/drivers/pmc_cpu_core.c b/plat/bcm/drivers/pmc_cpu_core.c new file mode 100644 index 00000000..992021ef --- /dev/null +++ b/plat/bcm/drivers/pmc_cpu_core.c @@ -0,0 +1,917 @@ +/* +<:copyright-BRCM:2020:DUAL/GPL:standard + + Copyright (c) 2020 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ +#include +#include +#include +#include "pmc_drv.h" +#include "pmc_cpu_core.h" +#include "BPCM.h" + +void udelay(uint32_t usec); + +#if defined (PLATFORM_FLAVOR_63138) +/* this power up function is implemented with assumption that cpu#0 will always + * be the first one that's powered up. */ +int pmc_cpu_core_power_up(unsigned cpu) +{ + int ret; + ARM_CONTROL_REG arm_ctrl; + ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl; + + if (cpu == 0) { + /* in 63138, cpu#0 should've been powered on either by default or by PMC ROM. + * This code is for the future if PMC can shut down all the CPUs in + * hibernation and power them back up from other blocks. */ + + /* 1) Power on PLL */ + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + &arm_ctrl.Reg32); + if (ret) + return ret; + arm_ctrl.Bits.pll_ldo_pwr_on = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + + /* wait at least 1.0 usec */ + udelay(2); + + arm_ctrl.Bits.pll_pwr_on = 1; + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + + /* 2) Power up CPU0 */ + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + arm_pwr_ctrl.Bits.pwr_on = 0xf; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.pwr_on_status != 0xf); + + arm_pwr_ctrl.Bits.pwr_ok = 0xf; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.pwr_ok_status != 0xf); + + arm_ctrl.Bits.pll_clamp_on = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + + arm_pwr_ctrl.Bits.clamp_on = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + /* 3) Power up CPU0 RAM */ + arm_pwr_ctrl.Bits.mem_pda &= 0xe; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + arm_pwr_ctrl.Bits.mem_pwr_on = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_on_status == 0); + + arm_pwr_ctrl.Bits.mem_pwr_ok = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_ok_status == 0); + + arm_pwr_ctrl.Bits.mem_clamp_on = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + /* 4) Power up L2 cache */ + pmc_cpu_l2cache_power_up(); + + /* 5) de-assert CPU0 reset */ + arm_ctrl.Bits.cpu0_reset_n = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + } else if (cpu == 1) { + /* check whether CPU1 is up and running already. + * Assuming once cpu1_reset_n is set, cpu1 is powered on + * and running */ + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + &arm_ctrl.Reg32); + if (ret) + return ret; + if (arm_ctrl.Bits.cpu1_reset_n == 1) + return 0; + + /* 1) Power up CPU1 */ + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + arm_pwr_ctrl.Bits.pwr_on |= 0x3; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while ((arm_pwr_ctrl.Bits.pwr_on_status & 0x3) != 0x3); + + arm_pwr_ctrl.Bits.pwr_ok |= 0x3; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while ((arm_pwr_ctrl.Bits.pwr_ok_status & 0x3) != 0x3); + + arm_pwr_ctrl.Bits.clamp_on = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + /* 2) Power up CPU1 RAM */ + arm_pwr_ctrl.Bits.mem_pda &= 0xe; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + arm_pwr_ctrl.Bits.mem_pwr_on = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_on_status == 0); + + arm_pwr_ctrl.Bits.mem_pwr_ok = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_ok_status == 0); + + arm_pwr_ctrl.Bits.mem_clamp_on = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + /* 3) de-assert reset to CPU1 */ + arm_ctrl.Bits.cpu1_reset_n = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + } else { + printk("error in %s: we do not have CPU#%d\n", __func__, cpu); + return -1; + } + + return 0; +} + +/* this power_down function is implemented with assumption that CPU#0 will + * always be the last one to be powered down */ +/* Note: all the power_down codes have never been tested in 63138 */ +int pmc_cpu_core_power_down(unsigned cpu) +{ + int ret; + ARM_CONTROL_REG arm_ctrl; + ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl; + + if (cpu == 0) { + /* 1) assert reset to CPU0 */ + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + &arm_ctrl.Reg32); + if (ret) + return ret; + arm_ctrl.Bits.cpu0_reset_n = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + + /* 2) power down L2 cache */ + pmc_cpu_l2cache_power_down(); + + /* 3) power down CPU0 RAM */ + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + arm_pwr_ctrl.Bits.mem_clamp_on = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + arm_pwr_ctrl.Bits.mem_pwr_ok = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_ok_status == 0); + + arm_pwr_ctrl.Bits.mem_pwr_on = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_on_status == 0); + + arm_pwr_ctrl.Bits.mem_pda |= 0x1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + /* 4) Power down CPU0 */ + + arm_pwr_ctrl.Bits.clamp_on = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + arm_ctrl.Bits.pll_clamp_on = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + + arm_pwr_ctrl.Bits.pwr_ok = 0x0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.pwr_ok_status != 0xf); + + arm_pwr_ctrl.Bits.pwr_on = 0x0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_0), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.pwr_on_status != 0xf); + + /* 5) power down PLL */ + arm_ctrl.Bits.pll_pwr_on = 0; + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + + /* wait at least 1.0 usec */ + udelay(2); + + arm_ctrl.Bits.pll_ldo_pwr_on = 0; + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + } else if (cpu == 1) { + /* 1) assert reset to CPU1 */ + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + &arm_ctrl.Reg32); + if (ret) + return ret; + arm_ctrl.Bits.cpu1_reset_n = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + + /* 2) Power down RAM CPU1 */ + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + arm_pwr_ctrl.Bits.mem_clamp_on = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + arm_pwr_ctrl.Bits.mem_pwr_ok = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_ok_status == 0); + + arm_pwr_ctrl.Bits.mem_pwr_on = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_on_status == 0); + + arm_pwr_ctrl.Bits.mem_pda |= 0x1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + /* 3) Power Down CPU1 */ + arm_pwr_ctrl.Bits.clamp_on = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + arm_pwr_ctrl.Bits.pwr_ok &= 0xc; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while ((arm_pwr_ctrl.Bits.pwr_ok_status & 0x3) != 0x3); + + arm_pwr_ctrl.Bits.pwr_on &= 0xc; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_pwr_ctrl_1), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while ((arm_pwr_ctrl.Bits.pwr_on_status & 0x3) != 0x3); + } else { + printk("error in %s: we do not have CPU#%d\n", __func__, cpu); + return -1; + } + + return 0; +} + +int pmc_cpu_l2cache_power_up(void) +{ + int ret; + ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl; + + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + /* check if L2 cache is already power on. If it is, then just return 0 */ + if ((arm_pwr_ctrl.Bits.mem_clamp_on == 0) && + (arm_pwr_ctrl.Bits.mem_clamp_on == 0) && + (arm_pwr_ctrl.Bits.mem_pwr_ok == 0x1) && + (arm_pwr_ctrl.Bits.mem_pwr_on == 0x1)) + return 0; + + arm_pwr_ctrl.Bits.mem_pda = 0x0; /* set 0 to bit#8:11 */ + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + arm_pwr_ctrl.Bits.mem_pwr_on = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_on_status == 0); + + arm_pwr_ctrl.Bits.mem_pwr_ok = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_ok_status == 0); + + arm_pwr_ctrl.Bits.mem_clamp_on = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + return 0; +} + +int pmc_cpu_l2cache_power_down(void) +{ + int ret; + ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl; + + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + arm_pwr_ctrl.Bits.mem_clamp_on = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + arm_pwr_ctrl.Bits.mem_pwr_ok = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_ok_status == 0); + + arm_pwr_ctrl.Bits.mem_pwr_on = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while (arm_pwr_ctrl.Bits.mem_pwr_on_status == 0); + + arm_pwr_ctrl.Bits.mem_pda = 0xf; /* set 0xf to bit#8:11 */ + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + return 0; +} + +int pmc_cpu_neon_power_up(unsigned cpu) +{ + int ret; + ARM_CONTROL_REG arm_ctrl; + ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl; + + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + &arm_ctrl.Reg32); + if (ret) + return ret; + + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + /* check if neon is on and running aready. */ + if ((arm_ctrl.Bits.neon_reset_n == 1) && + (arm_pwr_ctrl.Bits.clamp_on == 0) && + (arm_pwr_ctrl.Bits.pwr_ok & 0x1) && + (arm_pwr_ctrl.Bits.pwr_on & 0x1)) + return 0; + + /* 1) Power up Neon */ + arm_pwr_ctrl.Bits.pwr_on |= 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while ((arm_pwr_ctrl.Bits.pwr_on_status & 0x1) == 0); + + arm_pwr_ctrl.Bits.pwr_ok |= 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while ((arm_pwr_ctrl.Bits.pwr_ok_status & 0x1) == 0); + + arm_pwr_ctrl.Bits.clamp_on = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + /* 2) De-assert reset to Neon */ + arm_ctrl.Bits.neon_reset_n = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + + return 0; +} + +int pmc_cpu_neon_power_down(unsigned cpu) +{ + int ret; + ARM_CONTROL_REG arm_ctrl; + ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl; + + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + &arm_ctrl.Reg32); + if (ret) + return ret; + + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + /* 1) assert reset to Neon */ + arm_ctrl.Bits.neon_reset_n = 0; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_control), + arm_ctrl.Reg32); + if (ret) + return ret; + + /* 2) Power down Neon */ + arm_pwr_ctrl.Bits.clamp_on = 1; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + arm_pwr_ctrl.Bits.pwr_ok &= 0xe; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while ((arm_pwr_ctrl.Bits.pwr_ok_status & 0x1) == 1); + + arm_pwr_ctrl.Bits.pwr_on &= 0xe; + + ret = WriteBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + arm_pwr_ctrl.Reg32); + if (ret) + return ret; + + do { + ret = ReadBPCMRegister(PMB_ADDR_AIP, + ARMBPCMRegOffset(arm_neon_l2), + &arm_pwr_ctrl.Reg32); + if (ret) + return ret; + } while ((arm_pwr_ctrl.Bits.pwr_on_status & 0x1) == 1); + + return 0; +} + +#else + +#if defined (PMB_ADDR_ORION_CPU0) +static uint32_t pmb_cpu_id[] = { + PMB_ADDR_ORION_CPU0, + PMB_ADDR_ORION_CPU1, +#if defined(PMB_ADDR_ORION_CPU2) + PMB_ADDR_ORION_CPU2, +#endif +#if defined(PMB_ADDR_ORION_CPU3) + PMB_ADDR_ORION_CPU3 +#endif +}; +#endif + +int pmc_cpu_core_power_up(unsigned cpu) +{ +#if defined (PLATFORM_FLAVOR_63148) + B15CTRL->cpu_ctrl.cpu1_pwr_zone_ctrl |= 0x400; + B15CTRL->cpu_ctrl.reset_cfg &= 0xfffffffd; +#elif defined (PMB_ADDR_ORION_CPU0) || defined (PLATFORM_FLAVOR_6846) + int error; + uint32_t arm_control; + +#if defined (PMB_ADDR_ORION_CPU0) + error = ResetDevice(pmb_cpu_id[cpu]); + if (error) { + ERROR("unable to power on CPU%d\n", cpu); + return error; + } +#endif + + error = ReadBPCMRegister(PMB_ADDR_BIU_BPCM, + ARMBPCMRegOffset(arm_control), + &arm_control); + if (error) { + ERROR("unable to release CPU%d reset.\n", cpu); + return error; + } + arm_control &= ~(1 << cpu); + error = WriteBPCMRegister(PMB_ADDR_BIU_BPCM, + ARMBPCMRegOffset(arm_control), + arm_control); + if (error) { + ERROR("unable to release CPU%d reset.\n", cpu); + return error; + } + udelay(100); // wait for cpu to come out of reset + INFO("pmc_cpu: powered up CPU%d\n", cpu); +#elif defined (BIUCTRL_BASE) + if (BIUCTRL->cpu_pwr_zone_ctrl[cpu] & BIU_CPU_CTRL_PWR_ZONE_CTRL_ZONE_RESET) { + BIUCTRL->power_cfg |= BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON << cpu; + BIUCTRL->cpu_pwr_zone_ctrl[cpu] = BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_UP_REQ | + (BIUCTRL->cpu_pwr_zone_ctrl[cpu] & ~BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_DN_REQ); + + udelay(100); // wait for cpu to come out of reset + } +#endif + return 0; +} + +int pmc_cpu_core_power_down(unsigned cpu) +{ +#if defined (BIUCTRL_BASE) + BIUCTRL->power_cfg &= ~(BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON << cpu); + BIUCTRL->cpu_pwr_zone_ctrl[cpu] = BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_DN_REQ | + (BIUCTRL->cpu_pwr_zone_ctrl[cpu] & ~BIU_CPU_CTRL_PWR_ZONE_CTRL_PWR_UP_REQ); +#endif + return 0; +} +#endif /* PLATFORM_FLAVOR_63138 */ diff --git a/plat/bcm/drivers/pmc_drv.c b/plat/bcm/drivers/pmc_drv.c new file mode 100644 index 00000000..0718e0c7 --- /dev/null +++ b/plat/bcm/drivers/pmc_drv.c @@ -0,0 +1,510 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2019 Broadcom Ltd. + */ +/* +<:copyright-BRCM:2013:DUAL/GPL:standard + + Copyright (c) 2013 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#include +#include +#include +#include "pmc_drv.h" +#include "BPCM.h" +#include "command.h" + +#if IS_BCMCHIP(6858) || defined(PMC_IMPL_3_X) +#include "clk_rst.h" +#endif + +int pmc_mode = PMC_MODE_DQM; + +static int SendAndWait(TCommand * cmd, TCommand * rsp) +{ +#if defined(PMC_ON_HOSTCPU) + rsp->u.cmdGenericParams.params[0] = 0; + rsp->u.cmdGenericParams.params[1] = 0; + return 0; +#else +#if IS_BCMCHIP(63138) + /* translate new cmdID into old cmdID that the pmc will understand NB: + * requires cmdIDs below to be the new versions + */ + + static const unsigned char newToOldcmdIDMap[] = { + [cmdSetRunState] = 64, // cmdSetRunState, + [cmdSetPowerState] = 65, // cmdSetPowerState, + [cmdShutdownAllowed] = 66, // cmdShutdownAllowed, + [cmdGetSelect0] = 67, // cmdGetSelect0, + [cmdGetSelect3] = 68, // cmdGetSelect3, + [cmdGetAvsDisableState] = 69, // cmdGetAvsDisableState, + [cmdGetPVT] = 70, // cmdGetPVT, + [cmdPowerDevOnOff] = 129, // cmdPowerDevOnOff, + [cmdPowerZoneOnOff] = 130, // cmdPowerZoneOnOff, + [cmdResetDevice] = 131, // cmdResetDevice, + [cmdResetZone] = 132, // cmdResetZone, + [cmdAllocateG2UDQM] = 133, // cmdAllocateG2UDQM, + [cmdQSMAvailable] = 134, // cmdQSMAvailable, + [cmdRevision] = 135, // cmdRevision, + }; + + static int pmc_remap = 0; +#endif + static uint32_t reqdID = 1; + int status = kPMC_COMMAND_TIMEOUT; + TCommand dummy; + +#if defined(BOOT_MEMC_SRAM) + reqdID = 1; +#endif + pmc_spin_lock(); + + /* clear previous rsp data if any */ + while (PMC->dqm.notEmptySts & PMC_DQM_RPL_STS) { + if (!rsp) + rsp = &dummy; + + rsp->word0.Reg32 = PMC->dqmQData[PMC_DQM_RPL_NUM].word[0]; + rsp->word1.Reg32 = PMC->dqmQData[PMC_DQM_RPL_NUM].word[1]; + rsp->u.cmdGenericParams.params[0] = + PMC->dqmQData[PMC_DQM_RPL_NUM].word[2]; + rsp->u.cmdGenericParams.params[1] = + PMC->dqmQData[PMC_DQM_RPL_NUM].word[3]; + + printk + ("PMC reqdID=%d previous rsp.word[0-3]=0x[%08x %08x %08x %08x] status=%d\n", + reqdID, rsp->word0.Reg32, rsp->word1.Reg32, + rsp->u.cmdGenericParams.params[0], + rsp->u.cmdGenericParams.params[1], rsp->word0.Bits.error); + } + +#if IS_BCMCHIP(63138) + if (pmc_remap && cmd->word0.Bits.cmdID < sizeof newToOldcmdIDMap && + newToOldcmdIDMap[cmd->word0.Bits.cmdID]) + cmd->word0.Bits.cmdID = newToOldcmdIDMap[cmd->word0.Bits.cmdID]; +#endif + +#ifdef PMC_LOG_IN_DTCM + if (cmd->word0.Bits.cmdID == cmdCloseAVS) + PMC->ctrl.hostMboxOut = 1; // request sync dtcm log +#endif + + cmd->word0.Bits.msgID = reqdID; + + /* send the command */ + PMC->dqmQData[PMC_DQM_REQ_NUM].word[0] = cmd->word0.Reg32; + PMC->dqmQData[PMC_DQM_REQ_NUM].word[1] = cmd->word1.Reg32; + PMC->dqmQData[PMC_DQM_REQ_NUM].word[2] = + cmd->u.cmdGenericParams.params[0]; + PMC->dqmQData[PMC_DQM_REQ_NUM].word[3] = + cmd->u.cmdGenericParams.params[1]; + +#ifdef CONFIG_BRCM_IKOS + /* We do not enable PMC TIMER here for IKOS, or it will wait forever */ + while (!(PMC->dqm.notEmptySts & PMC_DQM_RPL_STS)) ; +#elif defined(PMC_IMPL_3_X) +#ifdef PMC_LOG_IN_DTCM + if (cmd->word0.Bits.cmdID == cmdCloseAVS) { + while (!(PMC->dqm.notEmptySts & PMC_DQM_RPL_STS)) + pmc_show_log_item(); + + PMC->ctrl.hostMboxOut = 0; // ignore dtcm log + } + else +#endif // #ifdef PMC_LOG_IN_DTCM + { + PMC->ctrl.gpTmr0Ctl = ((1 << 31) | (1 << 29) | + ((400000 << 1) & 0x1fffffff)); // 400ms + + while (!(PMC->dqm.notEmptySts & PMC_DQM_RPL_STS) && + (PMC->ctrl.gpTmr0Ctl & (1 << 31))) ; + } +#else + PMC->ctrl.gpTmr2Ctl = ((1 << 31) | (1 << 29) | 400000); // 400ms + + while (!(PMC->dqm.notEmptySts & PMC_DQM_RPL_STS) && + (PMC->ctrl.gpTmr2Ctl & (1 << 31))) { +#if !defined(_CFE_) && (IS_BCMCHIP(63148) || IS_BCMCHIP(4908)) + /* Do not tight poll the PMC registers for longer command */ + if (cmd->word0.Bits.cmdID == cmdCloseAVS) + udelay(1000); +#endif + } +#endif /* CONFIG_BRCM_IKOS */ + + if (PMC->dqm.notEmptySts & PMC_DQM_RPL_STS) { + if (!rsp) + rsp = &dummy; + + /* command didn't timeout, fill in the response */ + rsp->word0.Reg32 = PMC->dqmQData[PMC_DQM_RPL_NUM].word[0]; + rsp->word1.Reg32 = PMC->dqmQData[PMC_DQM_RPL_NUM].word[1]; + rsp->u.cmdGenericParams.params[0] = + PMC->dqmQData[PMC_DQM_RPL_NUM].word[2]; + rsp->u.cmdGenericParams.params[1] = + PMC->dqmQData[PMC_DQM_RPL_NUM].word[3]; + + if (rsp->word0.Bits.msgID == reqdID) + status = rsp->word0.Bits.error; + else + status = kPMC_MESSAGE_ID_MISMATCH; + + if (status != kPMC_NO_ERROR) + printk + ("PMC reqdID=%d error=%d rsp.word[0-3]=0x[%08x %08x %08x %08x]\n", + reqdID, status, rsp->word0.Reg32, rsp->word1.Reg32, + rsp->u.cmdGenericParams.params[0], + rsp->u.cmdGenericParams.params[1]); + } + + reqdID = (reqdID + 1) & 0xff; + + pmc_spin_unlock(); + + return status; +#endif +} + +static int SendCmd(TCommand * cmd, int cmdID, int devAddr, int zone, int island, + TCommand * rsp) +{ + cmd->word0.Reg32 = 0; + cmd->word0.Bits.cmdID = cmdID; + cmd->word1.Reg32 = 0; + cmd->word1.Bits.devAddr = devAddr; + cmd->word1.Bits.zoneIdx = zone; + cmd->word1.Bits.island = island; + + return SendAndWait(cmd, rsp); +} + +int SendCommand(int cmdID, int devAddr, int zone, int island, uint32_t word2, + uint32_t word3, TCommand * rsp) +{ + TCommand cmd; + + cmd.u.cmdGenericParams.params[0] = word2; + cmd.u.cmdGenericParams.params[1] = word3; + + return SendCmd(&cmd, cmdID, devAddr, zone, island, rsp); +} + + +#if defined(PMC_IMPL_3_X) || defined(PMC_ON_HOSTCPU) +#ifdef PMC_ON_HOSTCPU +#define KEYHOLE_IDX 1 +#else +#define KEYHOLE_IDX 0 +#endif +int read_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t * value) +{ + int status = kPMC_NO_ERROR; + int bus = (devAddr >> PMB_BUS_ID_SHIFT) & 0x3; + uint32_t address, ctlSts; + volatile PMB_keyhole_reg *keyhole = &PMB->keyhole[KEYHOLE_IDX]; + + + address = + ((devAddr & 0xff) * + ((PMB-> + config >> PMB_NUM_REGS_SHIFT) & PMB_NUM_REGS_MASK)) | + (wordOffset); + + keyhole->control = + PMC_PMBM_START | (bus << PMC_PMBM_BUS_SHIFT) | (PMC_PMBM_Read) | + address; + ctlSts = keyhole->control; + while (ctlSts & PMC_PMBM_BUSY) + ctlSts = keyhole->control; /*wait for completion */ + + if (ctlSts & PMC_PMBM_TIMEOUT) + status = kPMC_COMMAND_TIMEOUT; + else + *value = keyhole->rd_data; + + return status; +} + +int write_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t value) +{ + int status = kPMC_NO_ERROR; + int bus = (devAddr >> PMB_BUS_ID_SHIFT) & 0x3; + uint32_t address, ctlSts; + volatile PMB_keyhole_reg *keyhole = &PMB->keyhole[KEYHOLE_IDX]; + + address = + ((devAddr & 0xff) * + ((PMB-> + config >> PMB_NUM_REGS_SHIFT) & PMB_NUM_REGS_MASK)) | + (wordOffset); + keyhole->wr_data = value; + keyhole->control = + PMC_PMBM_START | (bus << PMC_PMBM_BUS_SHIFT) | (PMC_PMBM_Write) | + address; + + ctlSts = keyhole->control; + while (ctlSts & PMC_PMBM_BUSY) + ctlSts = keyhole->control; /*wait for completion */ + + if (ctlSts & PMC_PMBM_TIMEOUT) + status = kPMC_COMMAND_TIMEOUT; + + return status; +} + + +#else // #if defined(PMC_IMPL_3_X) || defined(PMC_ON_HOSTCPU) +int read_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t * value) +{ + int status = kPMC_NO_ERROR; + int bus = (devAddr >> PMB_BUS_ID_SHIFT) & 0x3; + volatile PMBMaster *pmbm_ptr; + + if (bus >= PMB_BUS_MAX) + return kPMC_INVALID_BUS; + + pmbm_ptr = &(PROCMON->PMBM[bus]); + + /* Make sure PMBM is not busy */ + + pmbm_ptr->ctrl = PMC_PMBM_START | PMC_PMBM_Read | + ((devAddr & 0xff) << 12) | wordOffset; + + while (pmbm_ptr->ctrl & PMC_PMBM_START) ; + + if (pmbm_ptr->ctrl & PMC_PMBM_TIMEOUT) + status = kPMC_COMMAND_TIMEOUT; + else + *value = pmbm_ptr->rd_data; + + return status; +} + +int write_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t value) +{ + int bus = (devAddr >> PMB_BUS_ID_SHIFT) & 0x3; + int status = kPMC_NO_ERROR; + volatile PMBMaster *pmbm_ptr; + if (bus >= PMB_BUS_MAX) + return kPMC_INVALID_BUS; + + pmbm_ptr = &(PROCMON->PMBM[bus]); + + pmbm_ptr->wr_data = value; + pmbm_ptr->ctrl = PMC_PMBM_START | PMC_PMBM_Write | + ((devAddr & 0xff) << 12) | wordOffset; + + while (pmbm_ptr->ctrl & PMC_PMBM_START) ; + + if (pmbm_ptr->ctrl & PMC_PMBM_TIMEOUT) + status = kPMC_COMMAND_TIMEOUT; + + return status; +} +#endif // #if defined(PMC_IMPL_3_X) || defined(PMC_ON_HOSTCPU) + +/* note: all the [Read|Write][BPCM|Zone]Register functions are different from + * how they are defined in firmware code. In the driver code, it takes in + * wordOffset as the argument, but in the firmware code, it uses byteOffset */ +int ReadBPCMRegister(int devAddr, int wordOffset, uint32_t * value) +{ + int status = kPMC_INVALID_STATE; + + if (PMC_ACCESS_BPCM_DIRECT || pmc_mode == PMC_MODE_PMB_DIRECT) { + pmc_spin_lock(); + status = read_bpcm_reg_direct(devAddr, wordOffset, value); + pmc_spin_unlock(); + } else if (pmc_mode == PMC_MODE_DQM) { + TCommand rsp; + status = + SendCommand(cmdReadBpcmReg, devAddr, 0, 0, wordOffset, 0, + &rsp); + + if (status == kPMC_NO_ERROR) + *value = rsp.u.cmdResponse.word2; + } + + return status; +} + +int WriteBPCMRegister(int devAddr, int wordOffset, uint32_t value) +{ + int status = kPMC_INVALID_STATE; + + if (PMC_ACCESS_BPCM_DIRECT || pmc_mode == PMC_MODE_PMB_DIRECT) { + pmc_spin_lock(); + status = write_bpcm_reg_direct(devAddr, wordOffset, value); + pmc_spin_unlock(); + } else if (pmc_mode == PMC_MODE_DQM) { + status = + SendCommand(cmdWriteBpcmReg, devAddr, 0, 0, wordOffset, + value, 0); + } + + return status; +} + + +int PowerOnZone(int devAddr, int zone) +{ + BPCM_PWR_ZONE_N_CONTROL reg; + int status; + +#if IS_BCMCHIP(6858) + /* Do not use DQM command cmdPowerZoneOnOff for non 6858 because this command is only available if a + PMC application has been uploaded to expand the PMC boot rom functionality */ + if (pmc_mode == PMC_MODE_DQM) { + TCommand cmd = {0}; + cmd.u.cmdStateOnlyParam.state = 1; + return SendCmd(&cmd, cmdPowerZoneOnOff, devAddr, zone, 0, 0); + } +#endif + + status = + ReadBPCMRegister(devAddr, BPCMRegOffset(zones[zone].control), + ®.Reg32); + if (status == kPMC_NO_ERROR && reg.Bits.pwr_on_state == 0) { + reg.Bits.pwr_dn_req = 0; + reg.Bits.dpg_ctl_en = 1; + reg.Bits.pwr_up_req = 1; + reg.Bits.mem_pwr_ctl_en = 1; + reg.Bits.blk_reset_assert = 1; + status = + WriteBPCMRegister(devAddr, + BPCMRegOffset(zones[zone].control), + reg.Reg32); + } + return status; +} + +int PowerOnDevice(int devAddr) +{ + if (PMC_ACCESS_BPCM_DIRECT || pmc_mode == PMC_MODE_PMB_DIRECT) { + int ix, status; + BPCM_CAPABILITES_REG capabilities; + + status = + ReadBPCMRegister(devAddr, BPCMRegOffset(capabilities), + &capabilities.Reg32); + for (ix = 0; + (ix < capabilities.Bits.num_zones) + && (status == kPMC_NO_ERROR); ix++) { + status = PowerOnZone(devAddr, ix); + } + + return status; + } + + if (pmc_mode == PMC_MODE_DQM) { + TCommand cmd = {0}; + cmd.u.cmdPowerDevice.state = 1; + return SendCmd(&cmd, cmdPowerDevOnOff, devAddr, 0, 0, 0); + } + + return kPMC_INVALID_STATE; +} + +int PowerOffDevice(int devAddr, int repower) +{ + if (PMC_ACCESS_BPCM_DIRECT || pmc_mode == PMC_MODE_PMB_DIRECT) { + /* we can power off the entire device by powering off the 0th zone. */ + BPCM_PWR_ZONE_N_CONTROL reg; + int status; + + status = + ReadBPCMRegister(devAddr, BPCMRegOffset(zones[0].control), + ®.Reg32); + + if (status == kPMC_NO_ERROR && reg.Bits.pwr_off_state == 0) { + reg.Bits.pwr_dn_req = 1; + WriteBPCMRegister(devAddr, + BPCMRegOffset(zones[0].control), + reg.Reg32); + } + + return status; + } + + if (pmc_mode == PMC_MODE_DQM) { + TCommand cmd = {0}; + cmd.u.cmdPowerDevice.state = 0; + cmd.u.cmdPowerDevice.restore = repower; + return SendCmd(&cmd, cmdPowerDevOnOff, devAddr, 0, 0, 0); + } + + return kPMC_INVALID_STATE; +} + +int ResetDevice(int devAddr) +{ + /* all zones had their blk_reset_assert bits set at initial config time */ + BPCM_PWR_ZONE_N_CONTROL reg; + int status; + +#if IS_BCMCHIP(6858) + /* Do not use DQM command cmdResetDevice for non 6858 because this command is only available if a + PMC application has been uploaded to expand the PMC boot rom functionality */ + if (pmc_mode == PMC_MODE_DQM) + return SendCommand(cmdResetDevice, devAddr, 0, 0, 0, 0, 0); +#endif + + status = PowerOffDevice(devAddr, 0); + do { + status = + ReadBPCMRegister(devAddr, BPCMRegOffset(zones[0].control), + ®.Reg32); + } while ((reg.Bits.pwr_off_state != 1) && (status == kPMC_NO_ERROR)); + if (status == kPMC_NO_ERROR) + status = PowerOnDevice(devAddr); + return status; +} + +// initalize pmc_mode (possibly) before printk available +void pmc_initmode(void) +{ +#if defined MISC_STRAP_BUS_PMC_ROM_BOOT + /* read the strap pin and based on the strap pin, choose the mode */ + if ((MISC->miscStrapBus & MISC_STRAP_BUS_PMC_ROM_BOOT) == 0) + pmc_mode = PMC_MODE_PMB_DIRECT; +#else // #if defined MISC_STRAP_BUS_PMC_ROM_BOOT +#if IS_BCMCHIP(6858) + pmc_mode = PMC_MODE_DQM; +#else + pmc_mode = PMC_MODE_PMB_DIRECT; +#ifdef CFG_RAMAPP +#if IS_BCMCHIP(63158) + /* MIPS based PMC */ + if (PMC->ctrl.softResets == 0) + pmc_mode = PMC_MODE_DQM; +#elif defined(PMC_IMPL_3_X) + /* Maestro based PMC) */ + if (PROCMON->maestroReg.coreCtrl.coreEnable == 1) + pmc_mode = PMC_MODE_DQM; +#endif // #if IS_BCMCHIP(63158) +#endif // #ifdef CFG_RAMAPP +#endif // #if IS_BCMCHIP(6858) +#endif // #if defined MISC_STRAP_BUS_PMC_ROM_BOOT +} + + + + diff --git a/plat/bcm/dt.c b/plat/bcm/dt.c new file mode 100644 index 00000000..f732a6d5 --- /dev/null +++ b/plat/bcm/dt.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include +#include +#include "qemu_private.h" +#include + +static int append_psci_compatible(void *fdt, int offs, const char *str) +{ + return fdt_appendprop(fdt, offs, "compatible", str, strlen(str) + 1); +} + +int dt_add_psci_node(void *fdt) +{ + int offs; + + if (fdt_path_offset(fdt, "/psci") >= 0) { + WARN("PSCI Device Tree node already exists!\n"); + return 0; + } + + offs = fdt_path_offset(fdt, "/"); + if (offs < 0) + return -1; + offs = fdt_add_subnode(fdt, offs, "psci"); + if (offs < 0) + return -1; + if (append_psci_compatible(fdt, offs, "arm,psci-1.0")) + return -1; + if (append_psci_compatible(fdt, offs, "arm,psci-0.2")) + return -1; + if (append_psci_compatible(fdt, offs, "arm,psci")) + return -1; + if (fdt_setprop_string(fdt, offs, "method", "smc")) + return -1; + if (fdt_setprop_u32(fdt, offs, "cpu_suspend", PSCI_CPU_SUSPEND_AARCH64)) + return -1; + if (fdt_setprop_u32(fdt, offs, "cpu_off", PSCI_CPU_OFF)) + return -1; + if (fdt_setprop_u32(fdt, offs, "cpu_on", PSCI_CPU_ON_AARCH64)) + return -1; + if (fdt_setprop_u32(fdt, offs, "sys_poweroff", PSCI_SYSTEM_OFF)) + return -1; + if (fdt_setprop_u32(fdt, offs, "sys_reset", PSCI_SYSTEM_RESET)) + return -1; + return 0; +} + +static int check_node_compat_prefix(void *fdt, int offs, const char *prefix) +{ + const size_t prefix_len = strlen(prefix); + size_t l; + int plen; + const char *prop; + + prop = fdt_getprop(fdt, offs, "compatible", &plen); + if (!prop) + return -1; + + while (plen > 0) { + if (memcmp(prop, prefix, prefix_len) == 0) + return 0; /* match */ + + l = strlen(prop) + 1; + prop += l; + plen -= l; + } + + return -1; +} + +int dt_add_psci_cpu_enable_methods(void *fdt) +{ + int offs = 0; + + while (1) { + offs = fdt_next_node(fdt, offs, NULL); + if (offs < 0) + break; + if (fdt_getprop(fdt, offs, "enable-method", NULL)) + continue; /* already set */ + if (check_node_compat_prefix(fdt, offs, "arm,cortex-a")) + continue; /* no compatible */ + if (fdt_setprop_string(fdt, offs, "enable-method", "psci")) + return -1; + /* Need to restart scanning as offsets may have changed */ + offs = 0; + } + return 0; +} diff --git a/plat/bcm/include/BPCM.h b/plat/bcm/include/BPCM.h new file mode 100644 index 00000000..41df3f11 --- /dev/null +++ b/plat/bcm/include/BPCM.h @@ -0,0 +1,2511 @@ +/* +<:copyright-BRCM:2013:DUAL/GPL:standard + + Copyright (c) 2013 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ +#ifndef BPCM_H +#define BPCM_H + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#ifndef _TYPEDEFS_H_ +#ifndef _UINT32_T_DECLARED +typedef unsigned int uint32_t; +#define _UINT32_T_DECLARED +#endif +#ifndef _UINT64_T_DECLARED +typedef unsigned long long uint64_t; +#define _UINT64_T_DECLARED +#endif +#endif + +#ifndef IS_BCMCHIP +#define IS_BCMCHIP(num) (defined(_BCM9##num##_)||defined(CONFIG_BCM9##num)||\ + defined(CONFIG_BCM##num)) +#endif + +typedef union { + struct { +#if IS_BCMCHIP(6846) || IS_BCMCHIP(6856) || IS_BCMCHIP(63178) || IS_BCMCHIP(6878) || IS_BCMCHIP(63146)\ + || IS_BCMCHIP(4912) || IS_BCMCHIP(6855) + uint32_t pmbAddr:12; // [11:00] + uint32_t map_rev:4; // [15:12] always non-zero for AVS3 devices (see CLASSIC_BPCM_ID_REG below) + uint32_t island:4; // [19:16] + uint32_t devType:4; // [23:20] see enum above + uint32_t hw_rev:8; // [31:24] +#else +#ifdef PMC_LITTLE_ENDIAN + uint32_t pmb_Addr:8; + uint32_t hw_rev:8; + uint32_t sw_strap:16; +#else + uint32_t sw_strap:16; + uint32_t hw_rev:8; + uint32_t pmb_Addr:8; +#endif +#endif + } Bits; + uint32_t Reg32; +} BPCM_ID_REG; + +#if IS_BCMCHIP(6846) || IS_BCMCHIP(6856) + +typedef union { + struct { + uint32_t pmb_Addr:8; // [07:00] + uint32_t hw_rev:4; // [11:08] + uint32_t map_rev:4; // [15:12] always zero for classic devices (technically upper 4-bits of hw_rev) + uint32_t sw_strap:16; // [31:16] + } Bits; + uint32_t Reg32; +} CLASSIC_BPCM_ID_REG; +#endif + +#if !IS_BCMCHIP(6878) && !IS_BCMCHIP(6855) +// types of PMB devices +enum { + kPMB_BPCM = 0, + kPMB_MIPS_PLL = 1, + kPMB_GEN_PLL = 2, + kPMB_LC_PLL = 3, + // 4..15 reserved +}; +#else +enum { + kPMB_NO_DEVICE = 0, + kPMB_BPCM = 1, // in AVS3, this structure does not contain ARS registers (except for "classic" BPCM devices) + kPMB_MIPS_PLL = 2, + kPMB_GEN_PLL = 3, + kPMB_LC_PLL = 4, + kPMB_CLKRST = 5, + kPMB_PVTMON = 6, // used in in AVS3 when PVT is wrapped in a BPCM structure + kPMB_TMON_INTERNAL = 7, // ditto - used when TMON thermistor is on-die + kPMB_TMON_EXTERNAL = 8, // ditto - used when thermistor is off-die + kPMB_ARS = 9, // AVS Remote Sensors - remote oscillators and Power-Watchdog + // 10..15 reserved +}; +#endif + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN +#if IS_BCMCHIP(63146) || IS_BCMCHIP(4912) + uint32_t num_zones:6; + uint32_t reserved0:2; +#else + uint32_t num_zones:8; +#endif + uint32_t num_sr_bits:8; + uint32_t devType:4; // see enum above + uint32_t reserved1:12; +#else + uint32_t reserved1:12; + uint32_t devType:4; // see enum above + uint32_t num_sr_bits:8; +#if IS_BCMCHIP(63146) || IS_BCMCHIP(4912) + uint32_t reserved0:2; + uint32_t num_zones:6; +#else + uint32_t num_zones:8; +#endif +#endif + } Bits; + uint32_t Reg32; +} BPCM_CAPABILITES_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t pwd_alert:1; + uint32_t reserved:31; +#else + uint32_t reserved:31; + uint32_t pwd_alert:1; +#endif + } Bits; + uint32_t Reg32; +} BPCM_STATUS_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t ro_en_s:1; + uint32_t ro_en_h:1; + uint32_t ectr_en_s:1; + uint32_t ectr_en_h:1; + uint32_t thresh_en_s:1; + uint32_t thresh_en_h:1; + uint32_t continuous_s:1; + uint32_t continuous_h:1; + uint32_t reserved:4; + uint32_t valid_s:1; + uint32_t alert_s:1; + uint32_t valid_h:1; + uint32_t alert_h:1; + uint32_t interval:16; +#else + uint32_t interval:16; + uint32_t alert_h:1; + uint32_t valid_h:1; + uint32_t alert_s:1; + uint32_t valid_s:1; + uint32_t reserved:4; + uint32_t continuous_h:1; + uint32_t continuous_s:1; + uint32_t thresh_en_h:1; + uint32_t thresh_en_s:1; + uint32_t ectr_en_h:1; + uint32_t ectr_en_s:1; + uint32_t ro_en_h:1; + uint32_t ro_en_s:1; +#endif + } Bits; + uint32_t Reg32; +} BPCM_AVS_ROSC_CONTROL_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t thresh_lo:16; + uint32_t thresh_hi:16; +#else + uint32_t thresh_hi:16; + uint32_t thresh_lo:16; +#endif + } Bits; + uint32_t Reg32; +} BPCM_AVS_ROSC_THRESHOLD; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t count_s:16; + uint32_t count_h:16; +#else + uint32_t count_h:16; + uint32_t count_s:16; +#endif + } Bits; + uint32_t Reg32; +} BPCM_AVS_ROSC_COUNT; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t pwd_en:1; + uint32_t pwd_alert_sel:1; + uint32_t start:6; + uint32_t pwd_tm_en:1; + uint32_t reserved2:6; + uint32_t alert:1; + uint32_t ccfg:8; + uint32_t rsel:3; + uint32_t clr_cfg:3; + uint32_t reserved1:2; +#else + uint32_t reserved1:2; + uint32_t clr_cfg:3; + uint32_t rsel:3; + uint32_t ccfg:8; + uint32_t alert:1; + uint32_t reserved2:6; + uint32_t pwd_tm_en:1; + uint32_t start:6; + uint32_t pwd_alert_sel:1; + uint32_t pwd_en:1; +#endif + } Bits; + uint32_t Reg32; +} BPCM_AVS_PWD_CONTROL; + +typedef union { + struct { + uint32_t tbd:32; + } Bits; + uint32_t Reg32; +} BPCM_PWD_ACCUM_CONTROL; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t sr:8; + uint32_t gp:24; +#else + uint32_t gp:24; + uint32_t sr:8; +#endif + } Bits; +#if IS_BCMCHIP(6858) + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t wan_main_rst_n:1; + uint32_t wan_top_bb_rst_n:1; + uint32_t epon_core_rst_n:1; + uint32_t epon_rx_rclk16_sw_reset_n:1; + uint32_t epon_rx_rbc125_sw_reset_n:1; + uint32_t epon_tx_tclk16_sw_reset_n:1; + uint32_t epon_tx_clk125_sw_reset_n:1; + uint32_t gpon_main_rst_n:1; + uint32_t gpon_rx_rst_n:1; + uint32_t gpon_tx_rst_n:1; + uint32_t gpon_8khz_rst_n:1; + uint32_t ngpon_main_rst_n:1; + uint32_t ngpon_rx_rst_n:1; + uint32_t ngpon_tx_rst_n:1; + uint32_t ngpon_8khz_rst_n:1; + uint32_t gpon_nco_rst_n:1; + uint32_t apm_rst_n:1; + uint32_t reserved:15; +#else + uint32_t reserved:15; + uint32_t apm_rst_n:1; + uint32_t gpon_nco_rst_n:1; + uint32_t ngpon_8khz_rst_n:1; + uint32_t ngpon_tx_rst_n:1; + uint32_t ngpon_rx_rst_n:1; + uint32_t ngpon_main_rst_n:1; + uint32_t gpon_8khz_rst_n:1; + uint32_t gpon_tx_rst_n:1; + uint32_t gpon_rx_rst_n:1; + uint32_t gpon_main_rst_n:1; + uint32_t epon_tx_clk125_sw_reset_n:1; + uint32_t epon_tx_tclk16_sw_reset_n:1; + uint32_t epon_rx_rbc125_sw_reset_n:1; + uint32_t epon_rx_rclk16_sw_reset_n:1; + uint32_t epon_core_rst_n:1; + uint32_t wan_top_bb_rst_n:1; + uint32_t wan_main_rst_n:1; +#endif + } Bits_Wantop; +#endif +#if IS_BCMCHIP(63158) + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t wan_main_rst_n:1; + uint32_t wan_top_bb_rst_n:1; + uint32_t rbus_rst_n:1; + uint32_t reserved1:2; + uint32_t core_soft_rst_n:1; + uint32_t i_zn_sw_init:1; + uint32_t reserved2:1; + uint32_t epon_main_rst_n:1; + uint32_t epon_rx_rst_n:1; + uint32_t epon_tx_rst_n:1; + uint32_t epon_core_rst_n:1; + uint32_t ae_rx_rclk16_sw_reset_n:1; + uint32_t ae_rx_rbc125_sw_reset_n:1; /* for B0 */ + uint32_t ae_tx_tclk16_sw_reset_n:1; /* for B0 */ + uint32_t ae_tx_clk125_sw_reset_n:1; + uint32_t gpon_main_rst_n:1; + uint32_t gpon_rx_rst_n:1; + uint32_t gpon_tx_rst_n:1; + uint32_t gpon_8khz_rst_n:1; + uint32_t ngpon_main_rst_n:1; + uint32_t ngpon_rx_rst_n:1; + uint32_t ngpon_tx_rst_n:1; + uint32_t ngpon_8khz_rst_n:1; + uint32_t reserved3:2; + uint32_t gpon_nco_rst_n:1; + uint32_t epon_rx_rclk16_sw_reset_n:1; /* for B0 */ + uint32_t epon_rx_rbc125_sw_reset_n:1; /* for B0 */ + uint32_t epon_tx_tclk16_sw_reset_n:1; /* for B0 */ + uint32_t epon_tx_clk125_sw_reset_n:1; /* for B0 */ + uint32_t reserved4:1; +#else + uint32_t reserved4:1; + uint32_t epon_tx_clk125_sw_reset_n:1; /* for B0 */ + uint32_t epon_tx_tclk16_sw_reset_n:1; /* for B0 */ + uint32_t epon_rx_rbc125_sw_reset_n:1; /* for B0 */ + uint32_t epon_rx_rclk16_sw_reset_n:1; /* for B0 */ + uint32_t gpon_nco_rst_n:1; + uint32_t reserved3:2; + uint32_t ngpon_8khz_rst_n:1; + uint32_t ngpon_tx_rst_n:1; + uint32_t ngpon_rx_rst_n:1; + uint32_t ngpon_main_rst_n:1; + uint32_t gpon_8khz_rst_n:1; + uint32_t gpon_tx_rst_n:1; + uint32_t gpon_rx_rst_n:1; + uint32_t gpon_main_rst_n:1; + uint32_t ae_tx_clk125_sw_reset_n:1; + uint32_t ae_tx_tclk16_sw_reset_n:1; /* for B0 */ + uint32_t ae_rx_rbc125_sw_reset_n:1; /* for B0 */ + uint32_t ae_rx_rclk16_sw_reset_n:1; + uint32_t epon_core_rst_n:1; + uint32_t epon_tx_rst_n:1; + uint32_t epon_rx_rst_n:1; + uint32_t epon_main_rst_n:1; + uint32_t reserved2:1; + uint32_t i_zn_sw_init:1; + uint32_t core_soft_rst_n:1; + uint32_t reserved1:2; + uint32_t rbus_rst_n:1; + uint32_t wan_top_bb_rst_n:1; + uint32_t wan_main_rst_n:1; +#endif + } Bits_Wantop; +#endif +#if IS_BCMCHIP(63158) || IS_BCMCHIP(63178) + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t vdsl_bpcm_early_reset:1; + uint32_t vdsl_bpcm_reset:1; + uint32_t mips_ubus_soft_reset_bpcm_reset:1; + uint32_t qproc_1_bpcm_reset:1; + uint32_t qproc_2_bpcm_reset:1; + uint32_t sar_bpcm_soft_reset:1; + uint32_t vdsl_ubus_soft_bpcm_reset:1; + uint32_t reserved1:1; + uint32_t gp:24; +#else + uint32_t gp:24; + uint32_t reserved1:1; + uint32_t vdsl_ubus_soft_bpcm_reset:1; + uint32_t sar_bpcm_soft_reset:1; + uint32_t qproc_2_bpcm_reset:1; + uint32_t qproc_1_bpcm_reset:1; + uint32_t mips_ubus_soft_reset_bpcm_reset:1; + uint32_t vdsl_bpcm_reset:1; + uint32_t vdsl_bpcm_early_reset:1; +#endif + } Bits_vdsl; +#endif + uint32_t Reg32; +} BPCM_SR_CONTROL; + +typedef union{ + struct { + uint32_t tbd:32; + } Bits; + uint32_t Reg32; + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t vdsl_arm_por_reset_n:1; + uint32_t vdsl_arm_reset_n:1; + uint32_t vdsl_arm_debug_reset_n:1; + uint32_t vdsl_arm_l2_reset_n:1; + uint32_t vdsl_arm_cdbgrstreq_en:1; + uint32_t vdsl_arm_niden_a7_b0:1; + uint32_t vdsl_arm_spniden_a7_b0:1; + uint32_t vdsl_arm_nsocdbgreset_a7:1; + uint32_t axi4_ubus4_pass_through_disable:1; + uint32_t vdsl_arm_dbgen_a7_b0:1; + uint32_t vdsl_arm_spiden_a7_b0:1; + uint32_t vdsl_arm_scratch_reg:21; +#else + uint32_t vdsl_arm_scratch_reg:21; + uint32_t vdsl_arm_spiden_a7_b0:1; + uint32_t vdsl_arm_dbgen_a7_b0:1; + uint32_t axi4_ubus4_pass_through_disable:1; + uint32_t vdsl_arm_nsocdbgreset_a7:1; + uint32_t vdsl_arm_spniden_a7_b0:1; + uint32_t vdsl_arm_niden_a7_b0:1; + uint32_t vdsl_arm_cdbgrstreq_en:1; + uint32_t vdsl_arm_l2_reset_n:1; + uint32_t vdsl_arm_debug_reset_n:1; + uint32_t vdsl_arm_reset_n:1; + uint32_t vdsl_arm_por_reset_n:1; +#endif + } Bits_vdsl; +} BPCM_VDSL_ARM_RST_CTL; + +#if IS_BCMCHIP(63138) || IS_BCMCHIP(4908) || IS_BCMCHIP(63158) +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t z2_p_wan_phy_sel:3; /* 0-2 */ + uint32_t reserved0:1; /* 3 */ + uint32_t z2_switch_p3_phy_sel:3; /* 4-6 */ + uint32_t reserved1:1; /* 7 */ + uint32_t z2_switch_p4_phy_sel:3; /* 8-10 */ + uint32_t reserved2:1; /* 11 */ + uint32_t z0_mux_sel:1; /* 12 */ + uint32_t z1_gphy_mux_sel:1; /* 13 */ + uint32_t z2_gphy_mux_sel:1; /* 14 */ + uint32_t z2_crossbar_mux_sel:1; /* 15 */ + uint32_t reserved3:1; /* 16 */ + uint32_t z1_pda_en:1; /* 17 */ + uint32_t z1_ck250_clk_en:1; /* 18 */ + uint32_t z1_ck25_clk_dis:1; /* 19 */ + uint32_t reserved4:2; /* 20-21 */ + uint32_t z2_ck250_clk_en:1; /* 22 */ + uint32_t z2_ck25_clk_dis:1; /* 23 */ + uint32_t z2_serdes_clk_en:1; /* 24 */ + uint32_t z2_serdes_reset_mdioregs:1; /* 25 */ + uint32_t z2_sedes_reset_pll:1; /* 26 */ + uint32_t z2_serdes_reset:1; /* 27 */ + uint32_t z2_serdes_mux_sel:1; /* 28 */ + uint32_t reserved5:1; /* 29 */ + uint32_t z1_gphy_reset:1; /* 30 */ + uint32_t z2_gphy_reset:1; /* 31 */ +#else + uint32_t z2_gphy_reset:1; /* 31 */ + uint32_t z1_gphy_reset:1; /* 30 */ + uint32_t reserved5:1; /* 29 */ + uint32_t z2_serdes_mux_sel:1; /* 28 */ + uint32_t z2_serdes_reset:1; /* 27 */ + uint32_t z2_sedes_reset_pll:1; /* 26 */ + uint32_t z2_serdes_reset_mdioregs:1; /* 25 */ + uint32_t z2_serdes_clk_en:1; /* 24 */ + uint32_t z2_ck25_clk_dis:1; /* 23 */ + uint32_t z2_ck250_clk_en:1; /* 22 */ + uint32_t reserved4:2; /* 20-21 */ + uint32_t z1_ck25_clk_dis:1; /* 19 */ + uint32_t z1_ck250_clk_en:1; /* 18 */ + uint32_t z1_pda_en:1; /* 17 */ + uint32_t reserved3:1; /* 16 */ + uint32_t z2_crossbar_mux_sel:1; /* 15 */ + uint32_t z2_gphy_mux_sel:1; /* 14 */ + uint32_t z1_gphy_mux_sel:1; /* 13 */ + uint32_t z0_mux_sel:1; /* 12 */ + uint32_t reserved2:1; /* 11 */ + uint32_t z2_switch_p4_phy_sel:3; /* 8-10 */ + uint32_t reserved1:1; /* 7 */ + uint32_t z2_switch_p3_phy_sel:3; /* 4-6 */ + uint32_t reserved0:1; /* 3 */ + uint32_t z2_p_wan_phy_sel:3; /* 0-2 */ +#endif + } Bits; + uint32_t Reg32; +} BPCM_GLOBAL_CNTL; + +#elif IS_BCMCHIP(6858) || IS_BCMCHIP(6846) || IS_BCMCHIP(6856) || \ + IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(6878) || \ + IS_BCMCHIP(63146) || IS_BCMCHIP(6855) || IS_BCMCHIP(4912) || \ + IS_BCMCHIP(6756) + +typedef union { + struct { + uint32_t tbd:32; + } Bits; + uint32_t Reg32; +} BPCM_GLOBAL_CNTL; +#else +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t z0_mux_sel:1; /* 0 */ + uint32_t reserved0:4; /* 1-4 */ + uint32_t z1_gphy_reset:1; /* 5 */ + uint32_t reserved1:3; /* 6-8 */ + uint32_t z1_ck25_clk_dis:1; /* 9 */ + uint32_t z1_ck250_clk_en:1; /* 10 */ + uint32_t reserved2:1; /* 11 */ + uint32_t z1_gphy_mux_sel:1; /* 12 */ + uint32_t z1_pda_en:1; /* 13 */ + uint32_t reserved3:3; /* 14-16 */ + uint32_t z2_gphy_reset:1; /* 17 */ + uint32_t z2_serdes_reset:1; /* 18 */ + uint32_t z2_serdes_reset_mdioregs:1; /* 19 */ + uint32_t z2_sedes_reset_pll:1; /* 20 */ + uint32_t z2_ck250_clk_en:1; /* 21 */ + uint32_t z2_ck25_clk_dis:1; /* 22 */ + uint32_t z2_serdes_clk_en:1; /* 23 */ + uint32_t reserved4:1; /* 24 */ + uint32_t z2_serdes_mux_sel:1; /* 25 */ + uint32_t z2_gphy_mux_sel:1; /* 26 */ + uint32_t z2_crossbar_mux_sel:1; /* 27 */ + uint32_t z2_p_wan_phy_sel:2; /* 28-29 */ + uint32_t z2_switch_phy_sel:2; /* 30-31 */ +#else + uint32_t z2_switch_phy_sel:2; /* 30-31 */ + uint32_t z2_p_wan_phy_sel:2; /* 28-29 */ + uint32_t z2_crossbar_mux_sel:1; /* 27 */ + uint32_t z2_gphy_mux_sel:1; /* 26 */ + uint32_t z2_serdes_mux_sel:1; /* 25 */ + uint32_t reserved4:1; /* 24 */ + uint32_t z2_serdes_clk_en:1; /* 23 */ + uint32_t z2_ck25_clk_dis:1; /* 22 */ + uint32_t z2_ck250_clk_en:1; /* 21 */ + uint32_t z2_sedes_reset_pll:1; /* 20 */ + uint32_t z2_serdes_reset_mdioregs:1; /* 19 */ + uint32_t z2_serdes_reset:1; /* 18 */ + uint32_t z2_gphy_reset:1; /* 17 */ + uint32_t reserved3:3; /* 14-16 */ + uint32_t z1_pda_en:1; /* 13 */ + uint32_t z1_gphy_mux_sel:1; /* 12 */ + uint32_t reserved2:1; /* 11 */ + uint32_t z1_ck250_clk_en:1; /* 10 */ + uint32_t z1_ck25_clk_dis:1; /* 9 */ + uint32_t reserved1:3; /* 6-8 */ + uint32_t z1_gphy_reset:1; /* 5 */ + uint32_t reserved0:4; /* 1-4 */ + uint32_t z0_mux_sel:1; /* 0 */ +#endif + } Bits; + uint32_t Reg32; +} BPCM_GLOBAL_CNTL; +#endif + +#if IS_BCMCHIP(63158) +typedef union { + struct { + +#ifdef PMC_LITTLE_ENDIAN + uint32_t z0_mux_sel:1; // = r_Z0_GLOBAL_CNTL[0]; + uint32_t reserverd_1:1; // unused + uint32_t z3_pda_en:1; // = r_Z0_GLOBAL_CNTL[2]; + uint32_t rx_sys_clk_en:1; // = r_Z0_GLOBAL_CNTL[3]; + uint32_t tx_sys_clk_en:1; // = r_Z0_GLOBAL_CNTL[4]; + uint32_t gmii_rx_clk_en:1; // = r_Z0_GLOBAL_CNTL[5]; + uint32_t gmii_tx_clk_en:1; // = r_Z0_GLOBAL_CNTL[6]; + uint32_t rsrvd:25; +#else + uint32_t rsrvd:25; + uint32_t gmii_tx_clk_en:1; // = r_Z0_GLOBAL_CNTL[6]; + uint32_t gmii_rx_clk_en:1; // = r_Z0_GLOBAL_CNTL[5]; + uint32_t tx_sys_clk_en:1; // = r_Z0_GLOBAL_CNTL[4]; + uint32_t rx_sys_clk_en:1; // = r_Z0_GLOBAL_CNTL[3]; + uint32_t z3_pda_en:1; // = r_Z0_GLOBAL_CNTL[2]; + uint32_t reserverd_1:1; // unused + uint32_t z0_mux_sel:1; // = r_Z0_GLOBAL_CNTL[0]; +#endif + + } Bits; + uint32_t Reg32; + +} BPCM_GLOBAL_CNTL_0; + +typedef union { + struct { + +#ifdef PMC_LITTLE_ENDIAN + uint32_t z1_pda_en:1; //= r_Z1_GLOBAL_CNTL[0]; + uint32_t reserved:2; + uint32_t z1_ck250_clk_en:1; //= r_Z1_GLOBAL_CNTL[3]; + uint32_t z1_ref_clk_dis:1; //= r_Z1_GLOBAL_CNTL[4]; + uint32_t z1_mux_sel:1; //= r_Z1_GLOBAL_CNTL[5]; + uint32_t z1_gphy_reset:1; //= r_Z1_GLOBAL_CNTL[6]; + uint32_t z1_gphy_iddq_global_pwr:1; //= r_Z1_GLOBAL_CNTL[7]; + uint32_t z1_gphy_force_dll_en:1; //= r_Z1_GLOBAL_CNTL[8]; + uint32_t z1_gphy_ext_pwr_down:4; //= r_Z1_GLOBAL_CNTL[12:9]; + uint32_t z1_gphy_iddq_bias:1; //= r_Z1_GLOBAL_CNTL[13]; + uint32_t z1_switch_p3_phy_sel:1; //= r_Z1_GLOBAL_CNTL[14]; + uint32_t z1_switch_p8_sel:1; //= r_Z1_GLOBAL_CNTL[15]; + uint32_t rsrvd:16; +#else + uint32_t rsrvd:16; + uint32_t z1_switch_p8_sel:1; //= r_Z1_GLOBAL_CNTL[15]; + uint32_t z1_switch_p3_phy_sel:1; //= r_Z1_GLOBAL_CNTL[14]; + uint32_t z1_gphy_iddq_bias:1; //= r_Z1_GLOBAL_CNTL[13]; + uint32_t z1_gphy_ext_pwr_down:4; //= r_Z1_GLOBAL_CNTL[12:9]; + uint32_t z1_gphy_force_dll_en:1; //= r_Z1_GLOBAL_CNTL[8]; + uint32_t z1_gphy_iddq_global_pwr:1; //= r_Z1_GLOBAL_CNTL[7]; + uint32_t z1_gphy_reset:1; //= r_Z1_GLOBAL_CNTL[6]; + uint32_t z1_mux_sel:1; //= r_Z1_GLOBAL_CNTL[5]; + uint32_t z1_ref_clk_dis:1; //= r_Z1_GLOBAL_CNTL[4]; + uint32_t z1_ck250_clk_en:1; //= r_Z1_GLOBAL_CNTL[3]; + uint32_t reserved:2; + uint32_t z1_pda_en:1; //= r_Z1_GLOBAL_CNTL[0]; +#endif + + } Bits; + uint32_t Reg32; + +} BPCM_GLOBAL_CNTL_1; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t z2_pda_en:1; //= r_Z2_GLOBAL_CNTL[0]; + uint32_t reserved:1; + uint32_t z2_ck250_clk_en:1; //= r_Z2_GLOBAL_CNTL[2]; + uint32_t z2_ref_clk_dis:1; //= r_Z2_GLOBAL_CNTL[3]; + uint32_t z2_serdes_clk_en:1; //= r_Z2_GLOBAL_CNTL[4]; + uint32_t z2_gphy_mux_sel:1; //= r_Z2_GLOBAL_CNTL[5]; + uint32_t z2_gphy_reset:1; //= r_Z2_GLOBAL_CNTL[6]; + uint32_t z2_gphy_iddq_global_pwr:1; //= r_Z2_GLOBAL_CNTL[7]; + uint32_t z2_gphy_force_dll_en:1; //= r_Z2_GLOBAL_CNTL[8]; + uint32_t z2_gphy_ext_pwr_down:1; //= r_Z2_GLOBAL_CNTL[9]; + uint32_t z2_gphy_iddq_bias:1; //= r_Z2_GLOBAL_CNTL[10]; + uint32_t z2_crossbar_mux_sel:1; //= r_Z2_GLOBAL_CNTL[11]; + uint32_t z2_p_wan_phy_sel:2; //= r_Z2_GLOBAL_CNTL[13:12]; + uint32_t z2_switch_p4_phy_sel:2; //= r_Z2_GLOBAL_CNTL[15:14]; + uint32_t z2_switch_p6_phy_sel:2; //= r_Z2_GLOBAL_CNTL[17:16]; + uint32_t z2_serdes_mux_sel:1; //= r_Z2_GLOBAL_CNTL[18]; + uint32_t z2_serdes_iddq:1; //= r_Z2_GLOBAL_CNTL[19]; + uint32_t z2_serdes_pwrdwn:1; //= r_Z2_GLOBAL_CNTL[20]; + uint32_t z2_serdes_reset:1; //= r_Z2_GLOBAL_CNTL[21]; + uint32_t z2_serdes_reset_mdioregs:1; //= r_Z2_GLOBAL_CNTL[22]; + uint32_t z2_serdes_reset_pll:1; //= r_Z2_GLOBAL_CNTL[23]; + uint32_t z2_serdes_refclk_sel:3; //= r_Z2_GLOBAL_CNTL[26:24]; + uint32_t z2_pll_clk125_250_sel:1; //= r_Z2_GLOBAL_CNTL[27]; + uint32_t z2_pll_mux_clk250_sel:1; //= r_Z2_GLOBAL_CNTL[28]; + uint32_t rsrvd:3; +#else + uint32_t rsrvd:3; + uint32_t z2_pll_mux_clk250_sel:1; //= r_Z2_GLOBAL_CNTL[28]; + uint32_t z2_pll_clk125_250_sel:1; //= r_Z2_GLOBAL_CNTL[27]; + uint32_t z2_serdes_refclk_sel:3; //= r_Z2_GLOBAL_CNTL[26:24]; + uint32_t z2_serdes_reset_pll:1; //= r_Z2_GLOBAL_CNTL[23]; + uint32_t z2_serdes_reset_mdioregs:1; //= r_Z2_GLOBAL_CNTL[22]; + uint32_t z2_serdes_reset:1; //= r_Z2_GLOBAL_CNTL[21]; + uint32_t z2_serdes_pwrdwn:1; //= r_Z2_GLOBAL_CNTL[20]; + uint32_t z2_serdes_iddq:1; //= r_Z2_GLOBAL_CNTL[19]; + uint32_t z2_serdes_mux_sel:1; //= r_Z2_GLOBAL_CNTL[18]; + uint32_t z2_switch_p6_phy_sel:2; //= r_Z2_GLOBAL_CNTL[17:16]; + uint32_t z2_switch_p4_phy_sel:2; //= r_Z2_GLOBAL_CNTL[15:14]; + uint32_t z2_p_wan_phy_sel:2; //= r_Z2_GLOBAL_CNTL[13:12]; + uint32_t z2_crossbar_mux_sel:1; //= r_Z2_GLOBAL_CNTL[11]; + uint32_t z2_gphy_iddq_bias:1; //= r_Z2_GLOBAL_CNTL[10]; + uint32_t z2_gphy_ext_pwr_down:1; //= r_Z2_GLOBAL_CNTL[9]; + uint32_t z2_gphy_force_dll_en:1; //= r_Z2_GLOBAL_CNTL[8]; + uint32_t z2_gphy_iddq_global_pwr:1; //= r_Z2_GLOBAL_CNTL[7]; + uint32_t z2_gphy_reset:1; //= r_Z2_GLOBAL_CNTL[6]; + uint32_t z2_gphy_mux_sel:1; //= r_Z2_GLOBAL_CNTL[5]; + uint32_t z2_serdes_clk_en:1; //= r_Z2_GLOBAL_CNTL[4]; + uint32_t z2_ref_clk_dis:1; //= r_Z2_GLOBAL_CNTL[3]; + uint32_t z2_ck250_clk_en:1; //= r_Z2_GLOBAL_CNTL[2]; + uint32_t reserved:1; + uint32_t z2_pda_en:1; //= r_Z2_GLOBAL_CNTL[0]; +#endif + + } Bits; + uint32_t Reg32; + +} BPCM_GLOBAL_CNTL_2; +#endif + +typedef union { + struct { + uint32_t ctl; + } Bits_sata_gp; + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t iddq_bias:1; /* 0 */ + uint32_t ext_pwr_down:4; /* 1-4 */ + uint32_t force_dll_en:1; /* 5 */ + uint32_t iddq_global_pwr:1; /* 6 */ + uint32_t reserved:25; +#else + uint32_t reserved:25; + uint32_t iddq_global_pwr:1; /* 6 */ + uint32_t force_dll_en:1; /* 5 */ + uint32_t ext_pwr_down:4; /* 1-4 */ + uint32_t iddq_bias:1; /* 0 */ +#endif + } Bits_switch_z1_qgphy; + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t iddq_bias:1; /* 0 */ + uint32_t ext_pwr_down:1; /* 1 */ + uint32_t force_dll_en:1; /* 2 */ + uint32_t iddq_global_pwd:1; /* 3 */ + uint32_t ck25_dis:1; /* 4 */ + uint32_t phy_reset:1; /* 5 */ + uint32_t reserved0:2; + uint32_t phy_ad:5; /* 8-12 */ + uint32_t reserved1:18; + uint32_t ctrl_en:1; /* 31 */ +#else + uint32_t ctrl_en:1; /* 31 */ + uint32_t reserved1:18; + uint32_t phy_ad:5; /* 8-12 */ + uint32_t reserved0:2; + uint32_t phy_reset:1; /* 5 */ + uint32_t ck25_dis:1; /* 4 */ + uint32_t iddq_global_pwd:1; /* 3 */ + uint32_t force_dll_en:1; /* 2 */ + uint32_t ext_pwr_down:1; /* 1 */ + uint32_t iddq_bias:1; /* 0 */ +#endif + } Bits_egphy_1port; + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t iddq_bias:1; /* 0 */ + uint32_t ext_pwr_down:4; /* 1-4 */ + uint32_t force_dll_en:1; /* 5 */ + uint32_t iddq_global_pwd:1; /* 6 */ + uint32_t ck25_dis:1; /* 7 */ + uint32_t phy_reset:1; /* 8 */ + uint32_t reserved0:3; + uint32_t phy_ad:5; /* 12-16 */ + uint32_t reserved1:14; + uint32_t ctrl_en:1; /* 31 */ +#else + uint32_t ctrl_en:1; /* 31 */ + uint32_t reserved1:14; + uint32_t phy_ad:5; /* 12-16 */ + uint32_t reserved0:3; + uint32_t phy_reset:1; /* 8 */ + uint32_t ck25_dis:1; /* 7 */ + uint32_t iddq_global_pwd:1; /* 6 */ + uint32_t force_dll_en:1; /* 5 */ + uint32_t ext_pwr_down:4; /* 1-4 */ + uint32_t iddq_bias:1; /* 0 */ +#endif + } Bits_egphy_4port; + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t iddq_bias:1; /* 0 */ + uint32_t ext_pwr_down:4; /* 1-4 */ + uint32_t force_dll_en:1; /* 5 */ + uint32_t iddq_global_pwr:1; /* 6 */ + uint32_t reserved0:25; /* 7-31 */ +#else + uint32_t reserved0:25; /* 7-31 */ + uint32_t iddq_global_pwr:1; /* 6 */ + uint32_t force_dll_en:1; /* 5 */ + uint32_t ext_pwr_down:4; /* 1-4 */ + uint32_t iddq_bias:1; /* 0 */ +#endif + } Bits_qgphy_cntl; + struct { + uint32_t ctl; + } Bits_vdsl_phy; + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t alt_bfc_vector:12; /* 00-11 */ + uint32_t reserved0:3; + uint32_t alt_bfc_en:1; /* 15 */ + uint32_t reset_dly_cfg:2; /* 16-17 */ + uint32_t reserved1:8; + uint32_t ext_mclk_en_reset:1; /* 26 */ + uint32_t ext_mclk_en:1; /* 27 */ + uint32_t por_reset_n_ctl:1; /* 28 */ + uint32_t reset_n_ctl:1; /* 29 */ + uint32_t reserved2:1; + uint32_t clken:1; /* 31 */ +#else + uint32_t clken:1; /* 31 */ + uint32_t reserved2:1; + uint32_t reset_n_ctl:1; /* 29 */ + uint32_t por_reset_n_ctl:1; /* 28 */ + uint32_t ext_mclk_en:1; /* 27 */ + uint32_t ext_mclk_en_reset:1; /* 26 */ + uint32_t reserved1:8; + uint32_t reset_dly_cfg:2; /* 16-17 */ + uint32_t alt_bfc_en:1; /* 15 */ + uint32_t reserved0:3; + uint32_t alt_bfc_vector:12; /* 00-11 */ +#endif + } Bits_vdsl_mips; + uint32_t Reg32; +} BPCM_MISC_CONTROL; + +typedef union { + struct { + uint32_t field; + } Bits_qgphy_status; + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t alt_bfc_vector:12; /* 00-11 */ + uint32_t reserved0:3; + uint32_t alt_bfc_en:1; /* 15 */ + uint32_t reset_dly_cfg:2; /* 16-17 */ + uint32_t reserved1:8; + uint32_t ext_mclk_en_reset:1; /* 26 */ + uint32_t ext_mclk_en:1; /* 27 */ + uint32_t por_reset_n_ctl:1; /* 28 */ + uint32_t reset_n_ctl:1; /* 29 */ + uint32_t reserved2:1; + uint32_t clken:1; /* 31 */ +#else + uint32_t clken:1; /* 31 */ + uint32_t reserved2:1; + uint32_t reset_n_ctl:1; /* 29 */ + uint32_t por_reset_n_ctl:1; /* 28 */ + uint32_t ext_mclk_en:1; /* 27 */ + uint32_t ext_mclk_en_reset:1; /* 26 */ + uint32_t reserved1:8; + uint32_t reset_dly_cfg:2; /* 16-17 */ + uint32_t alt_bfc_en:1; /* 15 */ + uint32_t reserved0:3; + uint32_t alt_bfc_vector:12; /* 00-11 */ +#endif + } Bits_vdsl_mips; /* second PHY MIPS core */ + uint32_t Reg32; +} BPCM_MISC_CONTROL2; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t gphy_iddq_bias:1; /* 00 */ + uint32_t gphy_ext_pwr_down:1; /* 01 */ + uint32_t gphy_force_dll_en:1; /* 02 */ + uint32_t gphy_iddq_global_pwr:1; /* 03 */ + uint32_t serdes_iddq:1; /* 04 */ + uint32_t serdes_pwrdwn:1; /* 05 */ + uint32_t reserved0:2; /* 07:06 */ + uint32_t serdes_refclk_sel:3; /* 10:08 */ + uint32_t reserved1:5; /* 15:11 */ + uint32_t pll_clk125_250_sel:1; /* 16 */ + uint32_t pll_mux_clk_250_sel:1; /* 17 */ + uint32_t reserved2:14; /* 31:18 */ +#else + uint32_t reserved2:14; /* 31:18 */ + uint32_t pll_mux_clk_250_sel:1; /* 17 */ + uint32_t pll_clk125_250_sel:1; /* 16 */ + uint32_t reserved1:5; /* 15:11 */ + uint32_t serdes_refclk_sel:3; /* 10:08 */ + uint32_t reserved0:2; /* 07:06 */ + uint32_t serdes_pwrdwn:1; /* 05 */ + uint32_t serdes_iddq:1; /* 04 */ + uint32_t gphy_iddq_global_pwr:1; /* 03 */ + uint32_t gphy_force_dll_en:1; /* 02 */ + uint32_t gphy_ext_pwr_down:1; /* 01 */ + uint32_t gphy_iddq_bias:1; /* 00 */ +#endif + } Bits; + uint32_t Reg32; +} BPCM_SGPHY_CNTL; + +typedef union { + struct { + uint32_t field; + } Bits; + uint32_t Reg32; +} BPCM_SGPHY_STATUS; + +typedef union { + struct { +#if IS_BCMCHIP(63138) +#ifdef PMC_LITTLE_ENDIAN + uint32_t core_pwr_ctrl:2; // 01:00 R/W + uint32_t reserved2:6; // 07:02 R/W + uint32_t pll_pwr_on:1; // 08:08 R/W + uint32_t pll_ldo_pwr_on:1; // 09:09 R/W + uint32_t pll_clamp_on:1; // 10:10 R/W + uint32_t reserved1:2; // 12:11 R/O + uint32_t cpu0_reset_n:1; // 13:13 R/W + uint32_t cpu1_reset_n:1; // 14:14 R/W + uint32_t neon_reset_n:1; // 15:15 R/W + uint32_t reserved0:12; // 27:16 R/O + uint32_t pwr_ctrl_sts:2; // 29:28 R/O + uint32_t power_down:2; // 31:30 R/O +#else + uint32_t power_down:2; // 31:30 R/O + uint32_t pwr_ctrl_sts:2; // 29:28 R/O + uint32_t reserved0:12; // 27:16 R/O + uint32_t neon_reset_n:1; // 15:15 R/W + uint32_t cpu1_reset_n:1; // 14:14 R/W + uint32_t cpu0_reset_n:1; // 13:13 R/W + uint32_t reserved1:2; // 12:11 R/O + uint32_t pll_clamp_on:1; // 10:10 R/W + uint32_t pll_ldo_pwr_on:1; // 09:09 R/W + uint32_t pll_pwr_on:1; // 08:08 R/W + uint32_t reserved2:6; // 07:02 R/W + uint32_t core_pwr_ctrl:2; // 01:00 R/W +#endif +#elif IS_BCMCHIP(63148) +#ifdef PMC_LITTLE_ENDIAN + uint32_t cpu0_reset_n:1; // 00:00 R/W + uint32_t power_down:1; // 01:01 R/W + uint32_t reserved:30; // 31:02 R/O +#else + uint32_t reserved:30; // 31:02 R/O + uint32_t power_down:1; // 01:01 R/W + uint32_t cpu0_reset_n:1; // 00:00 R/W +#endif +#elif IS_BCMCHIP(6858) || IS_BCMCHIP(63158) || IS_BCMCHIP(6846) || \ + IS_BCMCHIP(6856) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || \ + IS_BCMCHIP(6878) || IS_BCMCHIP(63146) || IS_BCMCHIP(4912) || \ + IS_BCMCHIP(6855) || IS_BCMCHIP(6756) +#ifdef PMC_LITTLE_ENDIAN + uint32_t cpu_reset_n:8; // 07:00 R/W + uint32_t c0l2_reset:1; // 08:08 R/W + uint32_t c1l2_reset:1; // 09:09 R/W + uint32_t reserved0:6; // 15:10 R/O + uint32_t cpu_bpcm_init_on:8; // 23:16 R/W + uint32_t c0l2_bpcm_init_on:1; // 24:24 R/W + uint32_t c1l2_bpcm_init_on:1; // 25:25 R/W + uint32_t ubus_sr:1; // 26:26 R/W + uint32_t cci_sr:1; // 27:27 R/W + uint32_t webcores_sr:1; // 28:28 R/W + uint32_t hw_done:1; // 29:29 R/O + uint32_t sw_done:1; // 30:30 R/W + uint32_t start:1; // 31:31 R/W +#else + uint32_t start:1; // 31:31 R/W + uint32_t sw_done:1; // 30:30 R/W + uint32_t hw_done:1; // 29:29 R/O + uint32_t webcores_sr:1; // 28:28 R/W + uint32_t cci_sr:1; // 27:27 R/W + uint32_t ubus_sr:1; // 26:26 R/W + uint32_t c1l2_bpcm_init_on:1; // 25:25 R/W + uint32_t c0l2_bpcm_init_on:1; // 24:24 R/W + uint32_t cpu_bpcm_init_on:8; // 23:16 R/W + uint32_t reserved0:6; // 15:10 R/O + uint32_t c1l2_reset:1; // 09:09 R/W + uint32_t c0l2_reset:1; // 08:08 R/W + uint32_t cpu_reset_n:8; // 07:00 R/W +#endif +#endif + } Bits; + uint32_t Reg32; +} ARM_CONTROL_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t mem_pwr_ok:1; // 00:00 R/W + uint32_t mem_pwr_on:1; // 01:01 R/W + uint32_t mem_clamp_on:1; // 02:02 R/W + uint32_t reserved2:1; // 03:03 R/W + uint32_t mem_pwr_ok_status:1; // 04:04 R/O + uint32_t mem_pwr_on_status:1; // 05:05 R/O + uint32_t reserved1:2; // 07:06 R/W + uint32_t mem_pda:4; // 11:08 R/W only LS bit for CPU0/1, all four bits for neon_l2 + uint32_t reserved0:3; // 14:12 R/W + uint32_t clamp_on:1; // 15:15 R/W + uint32_t pwr_ok:4; // 19:16 R/W ditto + uint32_t pwr_on:4; // 23:20 R/W ditto + uint32_t pwr_ok_status:4; // 27:24 R/O ditto + uint32_t pwr_on_status:4; // 31:28 R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2 +#else + uint32_t pwr_on_status:4; // 31:28 R/O only LS 2-bits for CPU1, only LS 1 bit for neon_l2 + uint32_t pwr_ok_status:4; // 27:24 R/O ditto + uint32_t pwr_on:4; // 23:20 R/W ditto + uint32_t pwr_ok:4; // 19:16 R/W ditto + uint32_t clamp_on:1; // 15:15 R/W + uint32_t reserved0:3; // 14:12 R/W + uint32_t mem_pda:4; // 11:08 R/W only LS bit for CPU0/1, all four bits for neon_l2 + uint32_t reserved1:2; // 07:06 R/W + uint32_t mem_pwr_on_status:1; // 05:05 R/O + uint32_t mem_pwr_ok_status:1; // 04:04 R/O + uint32_t reserved2:1; // 03:03 R/W + uint32_t mem_clamp_on:1; // 02:02 R/W + uint32_t mem_pwr_on:1; // 01:01 R/W + uint32_t mem_pwr_ok:1; // 00:00 R/W +#endif + } Bits; + uint32_t Reg32; +} ARM_CPUx_PWR_CTRL_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t resetb:1; // 00:00 + uint32_t post_resetb:1; // 01:01 + uint32_t pwrdwn:1; // 02:02 + uint32_t master_reset:1; // 03:03 + uint32_t pwrdwn_ldo:1; // 04:04 + uint32_t iso:1; // 05:05 // only used in afepll + uint32_t reserved0:2; // 07:06 + uint32_t ldo_ctrl:6; // 13:08 + uint32_t reserved1:1; // 14:14 + uint32_t hold_ch_all:1; // 15:15 + uint32_t reserved2:4; // 16:19 + uint32_t byp_wait:1; // 20:20 // only used in b15pll + uint32_t reserved3:11; // 21:31 +#else + uint32_t reserved3:11; // 21:31 + uint32_t byp_wait:1; // 20:20 // only used in b15pll + uint32_t reserved2:4; // 16:19 + uint32_t hold_ch_all:1; // 15:15 + uint32_t reserved1:1; // 14:14 + uint32_t ldo_ctrl:6; // 13:08 + uint32_t reserved0:2; // 07:06 + uint32_t iso:1; // 05:05 // only used in afepll + uint32_t pwrdwn_ldo:1; // 04:04 + uint32_t master_reset:1; // 03:03 + uint32_t pwrdwn:1; // 02:02 + uint32_t post_resetb:1; // 01:01 + uint32_t resetb:1; // 00:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_CTRL_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t fb_offset:12; // 11:00 + uint32_t fb_phase_en:1; // 12:12 + uint32_t _8phase_en:1; // 13:13 + uint32_t sr:18; // 31:14 +#else + uint32_t sr:18; // 31:14 + uint32_t _8phase_en:1; // 13:13 + uint32_t fb_phase_en:1; // 12:12 + uint32_t fb_offset:12; // 11:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_PHASE_REG; + +#if IS_BCMCHIP(63146) || IS_BCMCHIP(4912) +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t ndiv_int:10; // 09:00 + uint32_t reserved0:2; // 11:10 + uint32_t fref_eff_info:8; // 19:12 + uint32_t auto_cnfg_dsbl:8; // 27:20 + uint32_t reserved1:3; // 30:28 + uint32_t ndiv_override:1; // 31 +#else + uint32_t ndiv_override:1; // 31 + uint32_t reserved1:3; // 30:28 + uint32_t auto_cnfg_dsbl:8; // 27:20 + uint32_t fref_eff_info:8; // 19:12 + uint32_t reserved0:2; // 11:10 + uint32_t ndiv_int:10; // 09:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_NDIV_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t pdiv:4; // 03:00 + uint32_t ndiv_frac:24; // 27:04 + uint32_t reserved0:3; // 30:28 + uint32_t ndiv_pdiv_override:1; // 31:31 +#else + uint32_t ndiv_pdiv_override:1; // 31:31 + uint32_t reserved0:3; // 30:28 + uint32_t ndiv_frac:24; // 27:04 + uint32_t pdiv:4; // 03:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_PDIV_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t mdiv0:9; // 08:00 + uint32_t enableb_ch0:1; // 09:09 + uint32_t hold_ch0:1; // 10:10 + uint32_t mdel0:1; // 11:11 + uint32_t reserved0:3; // 14:12 + uint32_t mdiv_override0:1; // 15:15 + uint32_t mdiv1:9; // 24:16 + uint32_t enableb_ch1:1; // 25:25 + uint32_t hold_ch1:1; // 26:26 + uint32_t mdel1:1; // 27:27 + uint32_t reserved1:3; // 30:28 + uint32_t mdiv_override1:1; // 31:31 +#else + uint32_t mdiv_override1:1; // 31:31 + uint32_t reserved1:3; // 30:28 + uint32_t mdel1:1; // 27:27 + uint32_t hold_ch1:1; // 26:26 + uint32_t enableb_ch1:1; // 25:25 + uint32_t mdiv1:9; // 24:16 + uint32_t mdiv_override0:1; // 15:15 + uint32_t reserved0:3; // 14:12 + uint32_t mdel0:1; // 11:11 + uint32_t hold_ch0:1; // 10:10 + uint32_t enableb_ch0:1; // 09:09 + uint32_t mdiv0:9; // 08:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_CHCFG_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t reserved0:8; // 07:00 + uint32_t stat_select:3; // 10:08 + uint32_t pq_mode:1; // 11:11 + uint32_t stat_mode:2; // 13:12 + uint32_t stat_reset:1; // 14:14 + uint32_t stat_update:1; // 15:15 + uint32_t ssc_step:16; // 31:16 +#else + uint32_t ssc_step:16; // 31:16 + uint32_t stat_update:1; // 15:15 + uint32_t stat_reset:1; // 14:14 + uint32_t stat_mode:2; // 13:12 + uint32_t pq_mode:1; // 11:11 + uint32_t stat_select:3; // 10:08 + uint32_t reserved0:8; // 07:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_LOOP0_REG; + +#else +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t ndiv_int:10; // 09:00 + uint32_t ndiv_frac:20; // 29:10 + uint32_t reserved0:1; // 30 + uint32_t ndiv_override:1; // 31 +#else + uint32_t ndiv_override:1; // 31 + uint32_t reserved0:1; // 30 + uint32_t ndiv_frac:20; // 29:10 + uint32_t ndiv_int:10; // 09:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_NDIV_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t pdiv:3; // 02:00 + uint32_t reserved0:28; // 30:03 + uint32_t ndiv_pdiv_override:1; // 31:31 +#else + uint32_t ndiv_pdiv_override:1; // 31:31 + uint32_t reserved0:28; // 30:03 + uint32_t pdiv:3; // 02:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_PDIV_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t mdiv0:8; // 07:00 + uint32_t enableb_ch0:1; // 08:08 + uint32_t hold_ch0:1; // 09:09 + uint32_t load_en_ch0:1; // 10:10 + uint32_t mdel0:1; // 11:11 + uint32_t reserved0:3; // 14:12 + uint32_t mdiv_override0:1; // 15:15 + uint32_t mdiv1:8; // 23:16 + uint32_t enableb_ch1:1; // 24:24 + uint32_t hold_ch1:1; // 25:25 + uint32_t load_en_ch1:1; // 26:26 + uint32_t mdel1:1; // 27:27 + uint32_t reserved1:3; // 30:28 + uint32_t mdiv_override1:1; // 31:31 +#else + uint32_t mdiv_override1:1; // 31:31 + uint32_t reserved1:3; // 30:28 + uint32_t mdel1:1; // 27:27 + uint32_t load_en_ch1:1; // 26:26 + uint32_t hold_ch1:1; // 25:25 + uint32_t enableb_ch1:1; // 24:24 + uint32_t mdiv1:8; // 23:16 + uint32_t mdiv_override0:1; // 15:15 + uint32_t reserved0:3; // 14:12 + uint32_t mdel0:1; // 11:11 + uint32_t load_en_ch0:1; // 10:10 + uint32_t hold_ch0:1; // 09:09 + uint32_t enableb_ch0:1; // 08:08 + uint32_t mdiv0:8; // 07:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_CHCFG_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t reserved0:4; // 03:00 + uint32_t ka:3; // 06:04 + uint32_t reserved1:1; // 07:07 + uint32_t ki:3; // 10:08 + uint32_t reserved2:1; // 11:11 + uint32_t kp:4; // 15:12 + uint32_t ssc_step:16; // 31:16 +#else + uint32_t ssc_step:16; // 31:16 + uint32_t kp:4; // 15:12 + uint32_t reserved2:1; // 11:11 + uint32_t ki:3; // 10:08 + uint32_t reserved1:1; // 07:07 + uint32_t ka:3; // 06:04 + uint32_t reserved0:4; // 03:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_LOOP0_REG; + +#endif + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t ssc_limit:22; // 21:00 + uint32_t reserved0:2; // 23:22 + uint32_t ssc_clkdiv:4; // 27:24 + uint32_t ssc_status:1; // 28:28 + uint32_t reserved1:2; // 30:29 + uint32_t ssc_mode:1; // 31:31 +#else + uint32_t ssc_mode:1; // 31:31 + uint32_t reserved1:2; // 30:29 + uint32_t ssc_status:1; // 28:28 + uint32_t ssc_clkdiv:4; // 27:24 + uint32_t reserved0:2; // 23:22 + uint32_t ssc_limit:22; // 21:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_LOOP1_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t fdco_ctrl_bypass:16; // 15:00 + uint32_t fdco_bypass_en:1; // 16:16 + uint32_t fdco_dac_sel:1; // 17:17 + uint32_t state_reset:1; // 18:18 + uint32_t state_mode:2; // 20:19 + uint32_t state_sel:3; // 23:21 + uint32_t state_update:1; // 24:24 + uint32_t dco_en:1; // 25:25 + uint32_t dco_div2_div4:1; // 26:26 + uint32_t dco_bias_boost:1; // 27:27 + uint32_t bb_en:1; // 28:28 + uint32_t t2d_offset:3; // 31:29 +#else + uint32_t t2d_offset:3; // 31:29 + uint32_t bb_en:1; // 28:28 + uint32_t dco_bias_boost:1; // 27:27 + uint32_t dco_div2_div4:1; // 26:26 + uint32_t dco_en:1; // 25:25 + uint32_t state_update:1; // 24:24 + uint32_t state_sel:3; // 23:21 + uint32_t state_mode:2; // 20:19 + uint32_t state_reset:1; // 18:18 + uint32_t fdco_dac_sel:1; // 17:17 + uint32_t fdco_bypass_en:1; // 16:16 + uint32_t fdco_ctrl_bypass:16; // 15:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_CFG0_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t t2d_offset_msb:1; // 00:00 + uint32_t t2d_clk_enable:1; // 01:01 + uint32_t t2d_clk_sel:1; // 02:02 + uint32_t kpp:4; // 06:03 + uint32_t pwm_ctrl:2; // 08:07 + uint32_t port_reset_mode:2; // 10:09 + uint32_t byp2_en:1; // 11:11 + uint32_t byp1_en:1; // 12:12 + uint32_t ref_diff_sel:1; // 13:13 + uint32_t ki_startlow:1; // 14:14 + uint32_t en_500ohm:1; // 15:15 + uint32_t refd2c_bias:3; // 18:16 + uint32_t post_div2_div3:1; // 19:19 + uint32_t ki_boost:1; // 20:20 + uint32_t reserved0:11; // 31:21 +#else + uint32_t reserved0:11; // 31:21 + uint32_t ki_boost:1; // 20:20 + uint32_t post_div2_div3:1; // 19:19 + uint32_t refd2c_bias:3; // 18:16 + uint32_t en_500ohm:1; // 15:15 + uint32_t ki_startlow:1; // 14:14 + uint32_t ref_diff_sel:1; // 13:13 + uint32_t byp1_en:1; // 12:12 + uint32_t byp2_en:1; // 11:11 + uint32_t port_reset_mode:2; // 10:09 + uint32_t pwm_ctrl:2; // 08:07 + uint32_t kpp:4; // 06:03 + uint32_t t2d_clk_sel:1; // 02:02 + uint32_t t2d_clk_enable:1; // 01:01 + uint32_t t2d_offset_msb:1; // 00:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_CFG1_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t en_cml:3; // 02:00 + uint32_t tri_en:1; // 03:03 + uint32_t test_sel:3; // 06:04 + uint32_t test_en:1; // 07:07 + uint32_t reserved0:24; +#else + uint32_t reserved0:24; + uint32_t test_en:1; // 07:07 + uint32_t test_sel:3; // 06:04 + uint32_t tri_en:1; // 03:03 + uint32_t en_cml:3; // 02:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_OCTRL_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t out:12; // 11:00 + uint32_t reserved:19; // 30:12 + uint32_t lock:1; // 31:31 +#else + uint32_t lock:1; // 31:31 + uint32_t reserved:19; // 30:12 + uint32_t out:12; // 11:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_STAT_REG; + +#if IS_BCMCHIP(6858) || IS_BCMCHIP(63158) || IS_BCMCHIP(6846) || \ + IS_BCMCHIP(6856) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || \ + IS_BCMCHIP(6878) || IS_BCMCHIP(6855) || IS_BCMCHIP(6756) +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t ndiv_int:10; // 09:00 + uint32_t reserved0:2; // 11:10 + uint32_t ndiv_frac:20; // 31:12 +#else + uint32_t ndiv_frac:20; // 31:12 + uint32_t reserved0:2; // 11:10 + uint32_t ndiv_int:10; // 09:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_DECNDIV_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t pdiv:4; // 03:00 + uint32_t reserved0:12; // 15:04 + uint32_t mdiv0:8; // 23:16 + uint32_t mdiv1:8; // 31:24 +#else + uint32_t mdiv1:8; // 31:24 + uint32_t mdiv0:8; // 23:16 + uint32_t reserved0:12; // 15:04 + uint32_t pdiv:4; // 03:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_DECPDIV_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t mdiv2:8; // 07:00 + uint32_t mdiv3:8; // 15:08 + uint32_t mdiv4:8; // 23:16 + uint32_t mdiv5:8; // 31:24 +#else + uint32_t mdiv5:8; // 31:24 + uint32_t mdiv4:8; // 23:16 + uint32_t mdiv3:8; // 15:08 + uint32_t mdiv2:8; // 07:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_DECCH25_REG; +#elif IS_BCMCHIP(63146) || IS_BCMCHIP(4912) +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t ndiv_int:10; // 9:0 + uint32_t ndiv_frac:22; // 31:10 + +#else + uint32_t ndiv_frac:22; // 31:10 + uint32_t ndiv_int:10; // 9:0 +#endif + } Bits; + uint32_t Reg32; +} PLL_DECNDIV_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t pdiv:4; // 03:00 + uint32_t mdiv5:9; // 12:04 + uint32_t mdiv0:9; // 21:13 + uint32_t mdiv1:9; // 30:22 + uint32_t reserved0:1; // 31:31 +#else + uint32_t reserved0:1; // 31:31 + uint32_t mdiv1:9; // 30:22 + uint32_t mdiv0:9; // 21:13 + uint32_t mdiv5:9; // 12:04 + uint32_t pdiv:4; // 03:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_DECPDIV_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t mdiv2:9; // 08:00 + uint32_t mdiv3:9; // 17:09 + uint32_t mdiv4:9; // 26:18 + uint32_t reserved0:5; // 31:27 +#else + uint32_t reserved0:5; // 31:27 + uint32_t mdiv4:9; // 26:18 + uint32_t mdiv3:9; // 17:09 + uint32_t mdiv2:9; // 08:00 +#endif + } Bits; + uint32_t Reg32; +} PLL_DECCH25_REG; +#endif + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t manual_clk_en:1; + uint32_t manual_reset_ctl:1; + uint32_t freq_scale_used:1; // R/O + uint32_t dpg_capable:1; // R/O + uint32_t manual_mem_pwr:2; + uint32_t manual_iso_ctl:1; + uint32_t manual_ctl:1; + uint32_t dpg_ctl_en:1; + uint32_t pwr_dn_req:1; + uint32_t pwr_up_req:1; + uint32_t mem_pwr_ctl_en:1; + uint32_t blk_reset_assert:1; + uint32_t mem_stby:1; + uint32_t reserved:5; + uint32_t pwr_cntl_state:5; + uint32_t freq_scalar_dyn_sel:1; // R/O + uint32_t pwr_off_state:1; // R/O + uint32_t pwr_on_state:1; // R/O + uint32_t pwr_good:1; // R/O + uint32_t dpg_pwr_state:1; // R/O + uint32_t mem_pwr_state:1; // R/O + uint32_t iso_state:1; // R/O + uint32_t reset_state:1; // R/O +#else + uint32_t reset_state:1; // R/O 31:31 + uint32_t iso_state:1; // R/O + uint32_t mem_pwr_state:1; // R/O + uint32_t dpg_pwr_state:1; // R/O + uint32_t pwr_good:1; // R/O + uint32_t pwr_on_state:1; // R/O + uint32_t pwr_off_state:1; // R/O + uint32_t freq_scalar_dyn_sel:1; // R/O + uint32_t pwr_cntl_state:5; + uint32_t reserved:5; + uint32_t mem_stby:1; + uint32_t blk_reset_assert:1; // 12:12 + uint32_t mem_pwr_ctl_en:1; + uint32_t pwr_up_req:1; + uint32_t pwr_dn_req:1; + uint32_t dpg_ctl_en:1; + uint32_t manual_ctl:1; + uint32_t manual_iso_ctl:1; + uint32_t manual_mem_pwr:2; + uint32_t dpg_capable:1; // R/O + uint32_t freq_scale_used:1; // R/O + uint32_t manual_reset_ctl:1; + uint32_t manual_clk_en:1; +#endif + } Bits; + uint32_t Reg32; +} BPCM_PWR_ZONE_N_CONTROL; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t pwr_ok_delay_sel:3; + uint32_t pwk_ok_thresh:2; + uint32_t reserved:3; + uint32_t iso_on_delay:4; + uint32_t iso_off_delay:4; + uint32_t clock_on_delay:4; + uint32_t clock_off_delay:4; + uint32_t reset_on_delay:4; + uint32_t reset_off_delay:4; +#else + uint32_t reset_off_delay:4; // 31:28 + uint32_t reset_on_delay:4; + uint32_t clock_off_delay:4; + uint32_t clock_on_delay:4; + uint32_t iso_off_delay:4; + uint32_t iso_on_delay:4; + uint32_t reserved:3; + uint32_t pwk_ok_thresh:2; + uint32_t pwr_ok_delay_sel:3; +#endif + } Bits; + uint32_t Reg32; +} BPCM_PWR_ZONE_N_CONFIG1; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t delay_prescale_sel:3; + uint32_t slew_prescale_sel:3; + uint32_t reserved:6; + uint32_t dpgn_on_delay:4; + uint32_t dpg1_on_delay:4; + uint32_t dpg_off_delay:4; + uint32_t mem_on_delay:4; + uint32_t mem_off_delay:4; +#else + uint32_t mem_off_delay:4; // 31:28 + uint32_t mem_on_delay:4; + uint32_t dpg_off_delay:4; + uint32_t dpg1_on_delay:4; + uint32_t dpgn_on_delay:4; + uint32_t reserved:6; + uint32_t slew_prescale_sel:3; + uint32_t delay_prescale_sel:3; +#endif + } Bits; + uint32_t Reg32; +} BPCM_PWR_ZONE_N_CONFIG2; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t fs_bypass_en:1; + uint32_t gear_sel:1; + uint32_t use_dyn_gear_sel:1; + uint32_t reserved2:1; + uint32_t low_gear_div:3; + uint32_t high_gear_div:3; + uint32_t reserved:22; +#else + uint32_t reserved:22; // 31:10 + uint32_t high_gear_div:3; + uint32_t low_gear_div:3; + uint32_t reserved2:1; + uint32_t use_dyn_gear_sel:1; + uint32_t gear_sel:1; + uint32_t fs_bypass_en:1; +#endif + } Bits; + uint32_t Reg32; +} BPCM_ZONE_N_FREQ_SCALAR_CONTROL; + +typedef struct { + BPCM_PWR_ZONE_N_CONTROL control; + BPCM_PWR_ZONE_N_CONFIG1 config1; + BPCM_PWR_ZONE_N_CONFIG2 config2; +#if IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(6878) || IS_BCMCHIP(63146)\ + || IS_BCMCHIP(4912) || IS_BCMCHIP(6855) || IS_BCMCHIP(6756) + uint32_t reserved0; + uint32_t timer_control; + uint32_t timer_status; + uint32_t reserved1[2]; +#else + BPCM_ZONE_N_FREQ_SCALAR_CONTROL freq_scalar_control; +#endif +#if IS_BCMCHIP(6846) || IS_BCMCHIP(6856) + uint32_t reserved[4]; +#endif +} BPCM_ZONE; + +#define BPCMZoneOffset(reg) offsetof(BPCM_ZONE,reg) +#define BPCMZoneRegOffset(reg) (BPCMZoneOffset(reg) >> 2) + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t pmb_Addr:8; + uint32_t hw_rev:8; + uint32_t module_id:16; +#else + uint32_t module_id:16; + uint32_t hw_rev:8; + uint32_t pmb_Addr:8; +#endif + } Bits; + uint32_t Reg32; +} BPCM_UBUS_ID_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t num_zones:8; + uint32_t sr_reg_bits:8; + uint32_t pllType:2; + uint32_t reserved0:1; + uint32_t ubus:1; + uint32_t reserved1:12; +#else + uint32_t reserved1:12; + uint32_t ubus:1; + uint32_t reserved0:1; + uint32_t pllType:2; + uint32_t sr_reg_bits:8; + uint32_t num_zones:8; +#endif + } Bits; + uint32_t Reg32; +} BPCM_UBUS_CAPABILITES_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t ctrl_eswap:4; + uint32_t reserved0:4; + uint32_t ctrl_cd:4; + uint32_t reserved1:4; + uint32_t ctrl_seclev:8; + uint32_t reqout_seclev:8; +#else + uint32_t reqout_seclev:8; + uint32_t ctrl_seclev:8; + uint32_t reserved1:4; + uint32_t ctrl_cd:4; + uint32_t reserved0:4; + uint32_t ctrl_eswap:4; +#endif + } Bits; + uint32_t Reg32; +} BPCM_UBUS_CTRL_REG; + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint64_t addr_in:24; + uint64_t addr_out:24; + uint64_t pid:8; + uint64_t size:5; + uint64_t cmddta:1; + uint64_t en:2; +#else + uint64_t en:2; + uint64_t cmddta:1; + uint64_t size:5; + uint64_t pid:8; + uint64_t addr_out:24; + uint64_t addr_in:24; +#endif + } Bits; + struct { + uint32_t word0; + uint32_t word1; + } Regs32; + uint64_t Reg64; +} BPCM_UBUS_CFG_REG; + +#if IS_BCMCHIP(63178) +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t counter:8; + uint32_t reserved2:7; + uint32_t enable:1; + uint32_t reserved1:16; +#else + uint32_t reserved1:16; + uint32_t enable:1; + uint32_t reserved2:7; + uint32_t counter:8; +#endif + } Bits; + uint32_t Reg32; +} BPCM_CLKRST_VREG_CONTROL; +#endif +#if IS_BCMCHIP(63146) +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t ubus_soft_reset:1; + uint32_t alt_ubus_clk_sel:1; + uint32_t observe_clk_sw_init:1; + uint32_t alt_emmc_clk_sel:1; + uint32_t reserved:5; + uint32_t enable:1; + uint32_t counter:8; + uint32_t reserved2:14; +#else + uint32_t reserved2:14; + uint32_t counter:8; + uint32_t enable:1; + uint32_t reserved:5; + uint32_t alt_emmc_clk_sel:1; + uint32_t observe_clk_sw_init:1; + uint32_t alt_ubus_clk_sel:1; + uint32_t ubus_soft_reset:1; + +#endif + } Bits; + uint32_t Reg32; +} BPCM_CLKRST_VREG_CONTROL; +#endif + + +#if IS_BCMCHIP(47622) || IS_BCMCHIP(6756) +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t ubus_soft_rst:1; + uint32_t alt_ubus_clk_sel:1; + uint32_t obsv_clk_swinit:1; + uint32_t reserved0:17; + uint32_t wl0_rf_enable:1; + uint32_t wl1_rf_enable:1; + uint32_t reserved1:10; +#else + uint32_t reserved1:10; + uint32_t wl1_rf_enable:1; + uint32_t wl0_rf_enable:1; + uint32_t reserved0:17; + uint32_t obsv_clk_swinit:1; + uint32_t alt_ubus_clk_sel:1; + uint32_t ubus_soft_rst:1; +#endif + } Bits; + uint32_t Reg32; +} BPCM_CLKRST_CONTROL; +#endif + +// There is a 20-bit address used to access any given BPCM register. The upper 8-bits +// is the device address and the lower 12-bits is used to represent the BPCM register +// set for that device. 32-bit registers are allocated on 4-byte boundaries +// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...) +// Thus, to get the actual address of any given register within the device's address +// space, I'll use the "C" offsetof macro and divide the result by 4 +// e.g.: +// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL); // yields the byte offset of the target register +// int regAddress = regOffset/4; // yields the 32-bit word offset of the target register +// The ReadBPCMReg and WriteBPCMReg functions will always take a device address +// (address of the BPCM device) and register offset (like regOffset above). The offset +// will be divided by 4 and used as the lower 12-bits of the actual target address, while the +// device address will serve as the upper 8-bits of the actual address. +typedef struct { +#if IS_BCMCHIP(6846) || IS_BCMCHIP(6856) || IS_BCMCHIP(63178) || \ + IS_BCMCHIP(47622) || IS_BCMCHIP(6878) || IS_BCMCHIP(63146) || \ + IS_BCMCHIP(4912) || IS_BCMCHIP(6855) || IS_BCMCHIP(6756) + // PMB-slave: + BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0 + BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1 + uint32_t reserved0[2]; // offset 0x08, PMB reg index 2/3 + // BPCM + uint32_t control; // offset 0x10, PMB reg index 4 + BPCM_SR_CONTROL sr_control; // offset 0x14, PMB reg index 5 + uint32_t reserved1[2]; // offset 0x18, PMB reg index 6/7 + // Client-specific registers + uint32_t client_specific[24]; // offset 0x20, PMB reg index 8..31 + // Zones + BPCM_ZONE zones[]; // offset 0x80..(0x20 + MAX_ZONES*32)), PMB reg index 32..(32+(MAX_ZONES*8-1)) +#else + BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1 + uint32_t control; // offset = 0x08, actual offset = 2 + BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3 + BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4 + BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5 + BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6 + BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7 + BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8 + BPCM_PWD_ACCUM_CONTROL pwd_accum_control; // offset = 0x24, actual offset = 9 + BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10 + +#if IS_BCMCHIP(63158) + uint32_t reserved; // offset = 0x2c, actual offset = 11 + BPCM_GLOBAL_CNTL_0 global_control; // offset = 0x30, actual offset = 12 + BPCM_GLOBAL_CNTL_1 global_control_1; // offset = 0x34, actual offset = 13 + BPCM_GLOBAL_CNTL_2 global_control_2; // offset = 0x38, actual offset = 14 + uint32_t global_status; // offset = 0x3c, actual offset = 15 +#else + BPCM_GLOBAL_CNTL global_control; // offset = 0x2c, actual offset = 11 + BPCM_MISC_CONTROL misc_control; // offset = 0x30, actual offset = 12 + BPCM_MISC_CONTROL2 misc_control2; // offset = 0x34, actual offset = 13 + BPCM_SGPHY_CNTL sgphy_cntl; // offset = 0x38, actual offset = 14 + BPCM_SGPHY_STATUS sgphy_status; // offset = 0x3c, actual offset = 15 +#endif + BPCM_ZONE zones[1020]; // offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096) +#endif +} BPCM_REGS; // total offset space = 4096 + +#define BPCM_OFFSET(reg) (offsetof(BPCM_REGS,reg)>>2) + +#if !IS_BCMCHIP(6878) && !IS_BCMCHIP(6846) && !IS_BCMCHIP(6856) && !IS_BCMCHIP(6855) +typedef struct { +#if !IS_BCMCHIP(63178) && !IS_BCMCHIP(63146) + BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1 + uint32_t control; // offset = 0x08, actual offset = 2 + BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3 + BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4 + BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5 + BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6 + BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7 + BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8 + BPCM_PWD_ACCUM_CONTROL pwd_accum_control; // offset = 0x24, actual offset = 9 + BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10 + BPCM_GLOBAL_CNTL global_control; // offset = 0x2c, actual offset = 11 + BPCM_MISC_CONTROL misc_control; // offset = 0x30, actual offset = 12 + BPCM_MISC_CONTROL2 misc_control2; // offset = 0x34, actual offset = 13 + uint32_t rvrsd[2]; + BPCM_ZONE zones[1020]; // offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096) +#else + BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1 + uint32_t reserved0[2]; // offset = 0x08, actual offset = 2 + uint32_t cfg_control; // offset = 0x10, actual offset = 4 + BPCM_SR_CONTROL sr_control; // offset = 0x14, actual offset = 5 +#if IS_BCMCHIP(63146) + uint32_t reserved1[2]; // offset = 0x18, actual offset = 6 + uint32_t vdsl_arm_sr; // offset = 0x20, actual offset = 8 + BPCM_VDSL_ARM_RST_CTL vdsl_arm_rst_control; // offset = 0x24, actual offset = 9 + uint32_t reserved2[2]; // offset = 0x28, actual offset = 10 + uint32_t vdsl_afe_config0; // offset = 0x30, actual offset = 12 + uint32_t vdsl_afe_config1; // offset = 0x34, actual offset = 13 + uint32_t reserved3[18]; // offset = 0x38, actual offset = 14 +#else + uint32_t reserved1[10]; // offset = 0x18, actual offset = 6 + BPCM_MISC_CONTROL misc_control; // offset = 0x40, actual offset = 16 + uint32_t vdsl_phy_ctl; // offset = 0x44, actual offset = 17 + uint32_t vdsl_afe_ctl; // offset = 0x48, actual offset = 18 + uint32_t reserved2[13]; // offset = 0x4c, actual offset = 19 +#endif + BPCM_ZONE zones; // offset = 0x80, actual offset = 32 +#endif +} BPCM_VDSL_REGS; // total offset space = 4096 + +#define BPCMVDSLOffset(reg) offsetof(BPCM_VDSL_REGS,reg) +#define BPCMVDSLRegOffset(reg) (BPCMVDSLOffset(reg) >> 2) + +#endif + +#define BPCMOffset(reg) offsetof(BPCM_REGS,reg) +#define BPCMRegOffset(reg) (BPCMOffset(reg) >> 2) + +#if IS_BCMCHIP(63138) || IS_BCMCHIP(63148) || IS_BCMCHIP(6858) || \ + IS_BCMCHIP(63158) +// ARM BPCM addresses as used by 63138/63148 and possibly others (28nm) +typedef struct { + BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1 + uint32_t control; // offset = 0x08, actual offset = 2 + BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3 + BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4 + BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5 + BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6 + BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7 + BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8 + BPCM_PWD_ACCUM_CONTROL pwd_accum_control; // offset = 0x24, actual offset = 9 + BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10 + uint32_t reserved; // offset = 0x2c, actual offset = 11 + ARM_CONTROL_REG arm_control; // offset = 0x30, actual offset = 12 +#if IS_BCMCHIP(63138) + ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl_0; // offset = 0x34, actual offset = 13 + ARM_CPUx_PWR_CTRL_REG arm_pwr_ctrl_1; // offset = 0x38, actual offset = 14 + ARM_CPUx_PWR_CTRL_REG arm_neon_l2; // offset = 0x3c, actua; offset = 15 +#elif IS_BCMCHIP(63148) + uint32_t reserved1[3]; // offset = 0x34, actual offset = 13..15 +#elif IS_BCMCHIP(6858) + uint32_t biu_clk_control0; // offset = 0x34, actual offset = 13 + uint32_t reserved1[2]; // offset = 0x38, actual offset = 13..14 +#endif + BPCM_ZONE zones[1020]; // offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096) +} ARM_BPCM_REGS; +#define ARMBPCMOffset(reg) offsetof(ARM_BPCM_REGS,reg) +#define ARMBPCMRegOffset(reg) (ARMBPCMOffset(reg) >> 2) + +#elif IS_BCMCHIP(6846) || IS_BCMCHIP(6856) +typedef struct { + CLASSIC_BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1 + uint32_t control; // offset = 0x08, actual offset = 2 + BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3 + BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4 + BPCM_AVS_ROSC_THRESHOLD rosc_thresh; // offset = 0x14, actual offset = 5 + BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x18, actual offset = 6 + BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x1c, actual offset = 7 + BPCM_SR_CONTROL sr_control; // offset = 0x20, actual offset = 8 + uint32_t reserved0[3]; // offset = 0x24, actual offset = 9 + ARM_CONTROL_REG arm_control; // offset = 0x30, actual offset = 12 + uint32_t biu_clk_control0; // offset = 0x34, actual offset = 13 + uint32_t reserved1[2]; // offset = 0x38, actual offset = 14 + BPCM_ZONE zones; // offset = 0x40, actual offset = 16 +} ARM_BPCM_REGS; + +#define ARMBPCMOffset(reg) offsetof(ARM_BPCM_REGS,reg) +#define ARMBPCMRegOffset(reg) (ARMBPCMOffset(reg) >> 2) + +#elif IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(6878) || IS_BCMCHIP(6855) || IS_BCMCHIP(6756) +typedef struct { + BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1 + uint32_t reserved0[2]; // offset = 0x08, actual offset = 2 + uint32_t cfg_control; // offset = 0x10, actual offset = 4 + BPCM_SR_CONTROL sr_control; // offset = 0x14, actual offset = 5 + uint32_t reserved1[6]; // offset = 0x18, actual offset = 6 + ARM_CONTROL_REG arm_control; // offset = 0x30, actual offset = 12 + uint32_t biu_clk_control0; // offset = 0x34, actual offset = 13 + uint32_t tbd[18]; // offset = 0x38, actual offset = 14 + BPCM_ZONE zones; // offset = 0x80, actual offset = 32 +} ARM_BPCM_REGS; +#define ARMBPCMOffset(reg) offsetof(ARM_BPCM_REGS,reg) +#define ARMBPCMRegOffset(reg) (ARMBPCMOffset(reg) >> 2) + +#elif IS_BCMCHIP(63146) || IS_BCMCHIP(4912) +typedef struct { + BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1 + uint32_t reserved0[2]; // offset = 0x08, actual offset = 2 + uint32_t cfg_control; // offset = 0x10, actual offset = 4 + BPCM_SR_CONTROL sr_control; // offset = 0x14, actual offset = 5 + uint32_t reserved1[2]; // offset = 0x18, actual offset = 6 + BPCM_ZONE zones; // offset = 0x20, actual offset = 8 + ARM_CONTROL_REG arm_control; // offset = 0x40, actual offset = 16 +} ARM_BPCM_REGS; +#define ARMBPCMOffset(reg) offsetof(ARM_BPCM_REGS,reg) +#define ARMBPCMRegOffset(reg) (ARMBPCMOffset(reg) >> 2) + +#endif + +#if IS_BCMCHIP(6846) || IS_BCMCHIP(6856) +typedef struct { + BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1 + uint32_t reserved0[2]; // offset = 0x08..0x0c, actual offset 2..3 + PLL_CTRL_REG resets; // offset = 0x10, actual offset = 4 + PLL_CFG0_REG cfg0; // offset = 0x14, actual offset = 5 + PLL_CFG1_REG cfg1; // offset = 0x18, actual offset = 6 + PLL_NDIV_REG ndiv; // offset = 0x1c, actual offset = 7 + PLL_PDIV_REG pdiv; // offset = 0x20, actual offset = 8 + PLL_LOOP0_REG loop0; // offset = 0x24, actual offset = 9 + PLL_LOOP1_REG loop1; // offset = 0x28, actual offset = a + PLL_CHCFG_REG ch01_cfg; // offset = 0x2c, actual offset = b + PLL_CHCFG_REG ch23_cfg; // offset = 0x30, actual offset = c + PLL_CHCFG_REG ch45_cfg; // offset = 0x34, actual offset = d + PLL_OCTRL_REG octrl; // offset = 0x38, actual offset = e + PLL_STAT_REG stat; // offset = 0x3c, actual offset = f + uint32_t strap; // offset = 0x40, actual offset = 0x10 + PLL_DECNDIV_REG decndiv; // offset = 0x44, actual offset = 0x11 + PLL_DECPDIV_REG decpdiv; // offset = 0x48, actual offset = 0x12 + PLL_DECCH25_REG decch25; // offset = 0x4c, actual offset = 0x13 +} PLL_CLASSIC_BPCM_REGS; + +#define PLLCLASSICBPCMOffset(reg) offsetof(PLL_CLASSIC_BPCM_REGS,reg) +#define PLLCLASSICBPCMRegOffset(reg) (PLLCLASSICBPCMOffset(reg) >> 2) + +#elif IS_BCMCHIP(6878) +typedef struct { + BPCM_ID_REG id_reg; // offset = 0x00 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04 + uint32_t reserved0[6]; // offset = 0x08 + PLL_CTRL_REG resets; // offset = 0x20 + PLL_CFG0_REG cfg0; // offset = 0x24 + PLL_CFG1_REG cfg1; // offset = 0x28 + PLL_NDIV_REG ndiv; // offset = 0x2c + PLL_PDIV_REG pdiv; // offset = 0x30 + PLL_LOOP0_REG loop0; // offset = 0x34 + uint32_t reserved1; // offset = 0x38 + PLL_LOOP1_REG loop1; // offset = 0x3c + PLL_CHCFG_REG ch01_cfg; // offset = 0x40 + PLL_CHCFG_REG ch23_cfg; // offset = 0x44 + PLL_CHCFG_REG ch45_cfg; // offset = 0x48 + PLL_STAT_REG stat; // offset = 0x4c + uint32_t strap; // offset = 0x50 + PLL_DECNDIV_REG decndiv; // offset = 0x54 + PLL_DECPDIV_REG decpdiv; // offset = 0x58 + PLL_DECCH25_REG decch25; // offset = 0x5c +} PLL_CLASSIC_BPCM_REGS; + +#define PLLCLASSICBPCMOffset(reg) offsetof(PLL_CLASSIC_BPCM_REGS,reg) +#define PLLCLASSICBPCMRegOffset(reg) (PLLCLASSICBPCMOffset(reg) >> 2) + +#endif + +typedef struct { +#if IS_BCMCHIP(6846) || IS_BCMCHIP(6856) + BPCM_ID_REG id_reg; // offset = 0x00 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04 + uint32_t reserved0[6]; // offset = 0x08 + PLL_CTRL_REG resets; // offset = 0x20 + PLL_CFG0_REG cfg0; // offset = 0x24 + PLL_CFG1_REG cfg1; // offset = 0x28 + PLL_NDIV_REG ndiv; // offset = 0x2c + PLL_PDIV_REG pdiv; // offset = 0x30 + PLL_LOOP0_REG loop0; // offset = 0x34 + uint32_t reserved1; // offset = 0x38 + PLL_LOOP1_REG loop1; // offset = 0x3c + PLL_CHCFG_REG ch01_cfg; // offset = 0x40 + PLL_CHCFG_REG ch23_cfg; // offset = 0x44 + PLL_CHCFG_REG ch45_cfg; // offset = 0x48 + PLL_STAT_REG stat; // offset = 0x4c + uint32_t strap; // offset = 0x50 + PLL_DECNDIV_REG decndiv; // offset = 0x54 + PLL_DECPDIV_REG decpdiv; // offset = 0x58 + PLL_DECCH25_REG decch25; // offset = 0x5c +#elif IS_BCMCHIP(63146) || IS_BCMCHIP(4912) + /* BIU PLL BCPM definition */ + BPCM_ID_REG id_reg; // offset = 0x00 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04 + uint32_t reserved0[2]; // offset = 0x08..0x0c + PLL_CTRL_REG resets; // offset = 0x10 + uint32_t reserved1[2]; // offset = 0x14 + PLL_NDIV_REG ndiv; // offset = 0x1c + PLL_PDIV_REG pdiv; // offset = 0x20 + PLL_LOOP0_REG loop0; // offset = 0x24 + PLL_LOOP1_REG loop1; // offset = 0x28 + PLL_CHCFG_REG ch01_cfg; // offset = 0x2c + PLL_CHCFG_REG ch23_cfg; // offset = 0x30 + PLL_CHCFG_REG ch45_cfg; // offset = 0x34 + uint32_t reserved2; // offset = 0x38 + PLL_STAT_REG stat; // offset = 0x3c + uint32_t strap; // offset = 0x40 + PLL_DECNDIV_REG decndiv;// offset = 0x44 + PLL_DECPDIV_REG decpdiv;// offset = 0x48 + PLL_DECCH25_REG decch25;// offset = 0x4c +#else + BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1 + uint32_t reserved0[2]; // offset = 0x08..0x0c, actual offset 2..3 + PLL_CTRL_REG resets; // offset = 0x10, actual offset = 4 + PLL_CFG0_REG cfg0; // offset = 0x14, actual offset = 5 + PLL_CFG1_REG cfg1; // offset = 0x18, actual offset = 6 + PLL_NDIV_REG ndiv; // offset = 0x1c, actual offset = 7 + PLL_PDIV_REG pdiv; // offset = 0x20, actual offset = 8 + PLL_LOOP0_REG loop0; // offset = 0x24, actual offset = 9 + PLL_LOOP1_REG loop1; // offset = 0x28, actual offset = a + PLL_CHCFG_REG ch01_cfg; // offset = 0x2c, actual offset = b + PLL_CHCFG_REG ch23_cfg; // offset = 0x30, actual offset = c + PLL_CHCFG_REG ch45_cfg; // offset = 0x34, actual offset = d + PLL_OCTRL_REG octrl; // offset = 0x38, actual offset = e + PLL_STAT_REG stat; // offset = 0x3c, actual offset = f + uint32_t strap; // offset = 0x40, actual offset = 0x10 +#if IS_BCMCHIP(6858) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || \ + IS_BCMCHIP(6878) || IS_BCMCHIP(6855) || IS_BCMCHIP(6756) + PLL_DECNDIV_REG decndiv; // offset = 0x44, actual offset = 0x11 + PLL_DECPDIV_REG decpdiv; // offset = 0x48, actual offset = 0x12 + PLL_DECCH25_REG decch25; // offset = 0x4c, actual offset = 0x13 +#else + uint32_t decndiv; // offset = 0x44, actual offset = 0x11 + uint32_t decpdiv; // offset = 0x48, actual offset = 0x12 + uint32_t decch25; // offset = 0x4c, actual offset = 0x13 +#endif +#endif +} PLL_BPCM_REGS; + +#define PLLBPCMOffset(reg) offsetof(PLL_BPCM_REGS,reg) +#define PLLBPCMRegOffset(reg) (PLLBPCMOffset(reg) >> 2) + +#if IS_BCMCHIP(63146) +typedef struct { + BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1 + uint32_t reserved0[2]; // offset = 0x08..0x0c, actual offset 2..3 + PLL_CTRL_REG resets; // offset = 0x10, actual offset = 4 + uint32_t reserved1[5]; // offset = 0x14, actual offset = 5 + PLL_NDIV_REG ndiv; // offset = 0x28, actual offset = a + PLL_PDIV_REG pdiv; // offset = 0x2c, actual offset = b + PLL_CHCFG_REG ch01_cfg; // offset = 0x30, actual offset = c + PLL_CHCFG_REG ch23_cfg; // offset = 0x34, actual offset = d + PLL_CHCFG_REG ch45_cfg; // offset = 0x38, actual offset = e + PLL_LOOP0_REG loop0; // offset = 0x3c, actual offset = f + PLL_LOOP1_REG loop1; // offset = 0x40, actual offset = 0x10 + PLL_STAT_REG stat; // offset = 0x44, actual offset = 0x11 + uint32_t strap; // offset = 0x48, actual offset = 0x12 + PLL_DECNDIV_REG decndiv;// offset = 0x4c, actual offset = 0x13 + PLL_DECPDIV_REG decpdiv;// offset = 0x50, actual offset = 0x14 + PLL_DECCH25_REG decch25;// offset = 0x54, actual offset = 0x15 +} AFEPLL_BPCM_REGS; + +#define AFEPLLBPCMOffset(reg) offsetof(AFEPLL_BPCM_REGS,reg) +#define AFEPLLBPCMRegOffset(reg) (AFEPLLBPCMOffset(reg) >> 2) +#endif + +#if IS_BCMCHIP(63146) || IS_BCMCHIP(4912) +typedef struct { + BPCM_ID_REG id_reg; // offset = 0x00 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04 + uint32_t reserved0[2]; // offset = 0x08..0x0c + PLL_CTRL_REG resets; // offset = 0x10 + uint32_t reserved1[5]; // offset = 0x14 + PLL_NDIV_REG ndiv; // offset = 0x28 + PLL_PDIV_REG pdiv; // offset = 0x2c + PLL_CHCFG_REG ch01_cfg; // offset = 0x30 + PLL_CHCFG_REG ch23_cfg; // offset = 0x34 + PLL_CHCFG_REG ch45_cfg; // offset = 0x38 + PLL_STAT_REG stat; // offset = 0x3c + uint32_t strap; // offset = 0x40 + PLL_DECNDIV_REG decndiv;// offset = 0x44 + PLL_DECPDIV_REG decpdiv;// offset = 0x48 + PLL_DECCH25_REG decch25;// offset = 0x4c +} RDPPLL_BPCM_REGS; + +#define RDPPLLBPCMOffset(reg) offsetof(RDPPLL_BPCM_REGS,reg) +#define RDPPLLBPCMRegOffset(reg) (RDPPLLBPCMOffset(reg) >> 2) + +#endif + +#if IS_BCMCHIP(6878) || IS_BCMCHIP(6855) +typedef union { + struct { + uint32_t dac_data:10; // [09:00] + uint32_t vavs_minb0:1; // [10:10] - R/O iVDDC <= Vmin0 + uint32_t vavs_minb1:1; // [11:11] - R/O iVDDC <= Vmin1 + uint32_t vavs_warnb0:1; // [12:12] - R/O iVDDC <= Vwarn0 + uint32_t vavs_warnb1:1; // [13:13] - R/O iVDDC <= Vwarn1 + uint32_t vavs_maxb0:1; // [14:14] - R/O iVDDC <= Vmax0 + uint32_t vavs_maxb1:1; // [15:15] - R/O iVDDC <= Vmax1 + uint32_t adc_data:10; // [25:16] - R/O ADC output data in offset binary format + uint32_t adc_data_valid:1; // [26:26] - R/O + uint32_t reserved:5; // [31:27] - R/O + } Bits; + uint32_t Reg32; +} APVTMON_DATA_REG; + +typedef union { + // little endian - from page 5 of "ANA_VTMON_TS16FF_S0 & ANA_VTMON_PAD_TS16FF_Sx Module Specification" + // defaut value = 0x00000001 + struct { + uint32_t bg_adj:3; // [02:00] - default = 1 + uint32_t vtest_sel:4; // [06:03] - VTest = i_VDCC * (+1)/20, default = 0 + uint32_t rmon_sel:3; // [09:07] + uint32_t mode:3; // [12:10] + uint32_t adc_insel:2; // [14:13] - only used in expert mode (mode = 0b111) + uint32_t dac_en:1; // [15:15] - only used in expert mode (mode = 0b111) + uint32_t con_pad:1; // [16:16] - only used in expert mode (mode = 0b111) + uint32_t burnin_en:1; // [17:17] - only used in expert mode (mode = 0b111) + uint32_t reserved:1; // [18:18] + uint32_t vdccmon_refadj_max1:1; // [19:19] + uint32_t vdccmon_refadj_min0:4; // [23:20] + uint32_t vdccmon_refadj_min1:3; // [26:24] + uint32_t dac_reset:1; // [27:27] + uint32_t dac_set:1; // [28:28] + uint32_t vdccmon_refadj_max0:3; // [31:29] + } Bits; + uint32_t Reg32; +} APVTMON_CONTROL_REG; + +typedef union { + struct { + uint32_t rstb:1; // [00:00] - low active. default = 0 (i.e. in reset) + uint32_t pwr_dn:1; // [01:01] - high-active. default = 1 (i.e. powered down) + uint32_t clk_en:1; // [02:02] + uint32_t reserved0:1; // [03:03] + uint32_t sel:3; // [06:04] - see enum below - reset value = 0 + uint32_t reserved1:1; // [07:07] + uint32_t clk_div:5; // [12:08] - value needed to divide pm_clk by (2*clk_div) to generate a 5MHz clock + uint32_t reserved2:19; // [31:13] + } Bits; + uint32_t Reg32; +} APVTMON_CONFIG_STATUS_REG; + +typedef union { + struct { + uint32_t accum_en:1; // [00:00] + uint32_t round_en:1; // [01:01] defaults to 1 (rounding enabled) + uint32_t reserved1:6; // [07:02] + uint32_t skip_len:4; // [11:08] how many samples to skip prior to starting averaging, default = 3 + uint32_t reserved0:20; // [31:12] + } Bits; + uint32_t Reg32; +} APVTMON_ACQ_CONFIG_REG; + +typedef union { + struct { + uint32_t warn_threshold:10; // [09:00] - in ADC counts + uint32_t warn_en:1; // [10:10] + uint32_t reserved0:3; // [13:11] + uint32_t clear_warn:1; // [14:14] - Write only + uint32_t warn:1; // [15:15] - Read only + uint32_t reset_threshold:10; // [25:16] - in ADC counts + uint32_t reset_en:1; // [26:26] + uint32_t reserved1:3; // [29:27] + uint32_t clear_reset:1; // [30:30] - Write only + uint32_t reset:1; // [31:31] - Read only + } Bits; + uint32_t Reg32; +} APVTMON_TEMP_WARN_RESET_REG; + +typedef union { + struct { + uint32_t reset_value:10; // [09:00] + uint32_t reserved:22; // [31:10] + } Bits; + uint32_t Reg32; +} APVTMON_RESET_TEMP_REG; + +typedef union { + struct { + uint32_t value:10; // [09:00] - there are fractional bits + uint32_t reserved0:8; // [17:10] + uint32_t valid:1; // [18:18] + uint32_t busy:1; // [19:19] + uint32_t reserved1:4; // [23:20] + uint32_t meas_len:3; // [26:24] #samples = 2^ + uint32_t reserved2:4; // [30:27] + uint32_t enable:1; // [31:31] + } Bits; + uint32_t Reg32; +} APVTMON_ACCUM_REG; + +typedef union { + struct { + uint32_t sel:6; // [05:00] - ring oscillator select (0..35) + uint32_t reserved2:2; // [07:06] + uint32_t srm_ind_en:1; // [08:08] + uint32_t srm_ind_od:1; // [09:09] + uint32_t srm_ind_sel:2; // [11:10] + uint32_t reserved1:4; // [15:12] + uint32_t out:1; // [16:16] + uint32_t all_idl_low_oscs:1; // [17:17] + uint32_t all_idl_hi_oscs:1; // [18:18] + uint32_t reserved0:13; // [31:19] + } Bits; + uint32_t Reg32; +} ROSC_CTRL_STS_REG; + +typedef union { + struct { + uint32_t count:16; // [15:00] + uint32_t valid:1; // [16:16] + uint32_t too_lo:1; // [17:17] - count <= thresh_lo (only when THRESH_EN == 1) + uint32_t too_hi:1; // [18:18] - count <= thresh_hi (only when THRESH_EN == 1) + uint32_t reserved0:5; // [23:19] + uint32_t continuous:1; // [24:24] + uint32_t thresh_en:1; // [25:25] - enable threshold detection + uint32_t ectr_en:1; // [26:26] - enable counter + uint32_t src_en:1; // [27:27] - enable event source (may not do anything???) + uint32_t meas_len:4; // [31:28] - interval = 2^(+1) + } Bits; + uint32_t Reg32; +} ECTR_CTRL_STS_REG; + +typedef union { + struct { + uint32_t thresh_lo:16; // [15:00] + uint32_t thresh_hi:16; // [31:16] + } Bits; + uint32_t Reg32; +} ECTR_THRESH_REG; + +typedef struct { + ECTR_CTRL_STS_REG count_reg; + ECTR_THRESH_REG thresh_reg; +} ROSC_REGS; + +typedef struct { + BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0 + BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1 + uint32_t reserved0[2]; // offset 0x08, PMB reg index 2/3 + uint32_t reserved1[12]; // offset 0x10, PMB reg index 4-15 (future proofing ) + APVTMON_CONTROL_REG control; // offset 0x40, PMB reg index 16 + APVTMON_CONFIG_STATUS_REG config; // offset 0x44, PMB reg index 17 + APVTMON_DATA_REG adc_data; // offset 0x48, PMB reg index 18 + uint32_t reserved2; // offset 0x4c, PMB reg index 19 + APVTMON_ACQ_CONFIG_REG accum_config; // offset 0x50, PMB reg index 20 + APVTMON_TEMP_WARN_RESET_REG warn_rst; // offset 0x54, PMB reg index 21 + uint32_t reserved3[2]; // offset 0x58, PMB reg index 23 + APVTMON_ACCUM_REG acq_accum_regs[8]; // offset 0x60, PMB reg index 24-31 + ROSC_CTRL_STS_REG rosc_ctrl_sts; // offset 0x80, PMB reg index 32 + uint32_t rosc_en_lo; // offset 0x84, PMB reg index 33 + uint32_t rosc_en_hi; // offset 0x88, PMB reg index 34 + uint32_t rosc_idle_lo; // offset 0x8c, PMB reg index 35 + uint32_t rosc_idle_hi; // offset 0x90, PMB reg index 36 + uint32_t reserved4[3]; // offset 0x94, PMB reg index 37-39 + ROSC_REGS ectr_regs; // offset 0xa0, PMB reg index 40/41 +} PVTMON_REGS; +// retrieves the BYTE offset of a PVTMON register: +#define PVTMON_OFFSET(reg) (offsetof(PVTMON_REGS,reg)>>2) + +typedef struct { +// PMB-slave + BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0 + BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1 + uint32_t reserved0[6]; // offset 0x08, PMB reg index 2-7 + // ROSC registers + BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset 0x20, PMB reg index 8 + BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset 0x24, PMB reg index 9 + BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset 0x28, PMB reg index 10 + BPCM_AVS_ROSC_COUNT rosc_count; // offset 0x2c, PMB reg index 11 + BPCM_AVS_PWD_CONTROL pwd_ctrl; // offset 0x30, PMB reg index 12 + BPCM_PWD_ACCUM_CONTROL pwd_accum; // offset 0x34, PMB reg index 13 +} ARS_REGS; +// retrieves the BYTE offset of an ARS register: +#define ARS_OFFSET(reg) (offsetof(ARS_REGS, reg)>>2) + +#endif + +typedef struct { + BPCM_UBUS_ID_REG id_reg; /* offset = 0x00, actual offset = 0 */ + BPCM_UBUS_CAPABILITES_REG capabilities; /* offset = 0x04, actual offset = 1 */ + uint32_t reserved0; /* offset = 0x08, actual offset = 2 */ + BPCM_UBUS_CTRL_REG ctrl; /* offset = 0x0c, actual offset = 3 */ + BPCM_UBUS_CFG_REG cfg[4]; /* offset = 0x10..0x2c, actual offset = 4..11 */ +} BPCM_UBUS_REG; + +#define UBUSBPCMOffset(reg) offsetof(BPCM_UBUS_REG,reg) +#define UBUSBPCMRegOffset(reg) (UBUSBPCMOffset(reg) >> 2) + +#if IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(6756) +typedef struct { + // PMB-slave: + BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0 + BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1 + uint32_t reserved0[7]; // offset 0x08-0x20, PMB reg index 2-8 + uint32_t control; // offset 0x24, PMB reg index 9 +#if IS_BCMCHIP(47622) || IS_BCMCHIP(6756) + uint32_t observe_cntrl; // offset 0x28, PMB reg index 10 + uint32_t observe_div; // offset 0x2c, PMB reg index 11 + uint32_t observe_enable; // offset 0x30, PMB reg index 12 + BPCM_CLKRST_CONTROL clkrst_control; // offset 0x34, PMB reg index 13 +#elif IS_BCMCHIP(63146) + uint32_t unused[3]; // offset 0x28, PMB reg index 10 + BPCM_CLKRST_VREG_CONTROL vreg_control; // offset 0x34, PMB reg index ?? +#elif IS_BCMCHIP(63178) + uint32_t unused[10]; // offset 0x28, PMB reg index 10 + BPCM_CLKRST_VREG_CONTROL vreg_control; // offset 0x50, PMB reg index 19 +#endif +} BPCM_CLKRST_REGS; +#else +typedef struct { + BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0 + BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1 + uint32_t control; // offset = 0x08, actual offset = 2 + BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3 + BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4 + BPCM_AVS_ROSC_THRESHOLD rosc_thresh_h; // offset = 0x14, actual offset = 5 + BPCM_AVS_ROSC_THRESHOLD rosc_thresh_s; // offset = 0x18, actual offset = 6 + BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x1c, actual offset = 7 + BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x20, actual offset = 8 +#if IS_BCMCHIP(6878) + uint32_t bpcm_ctrl; // offset = 0x24, actual offset = 9 + uint32_t clkrst_control; // offset = 0x28, actual offset = 10 + uint32_t ext_observe_ctrl; // offset = 0x2c, actual offset = 11 + uint32_t reserved0[2]; // offset = 0x30-0x34, actual offset 12-13 + uint32_t xtal_control; // offset = 0x38, actual offset = 14 + uint32_t clkrst_stat; // offset = 0x3c, actual offset = 15 + uint32_t reserved1; // offset = 0x40, actual offset = 16 + uint32_t clkrst_ena_clk_31_0; // offset = 0x44, actual offset = 17 + uint32_t clkrst_ena_clk_63_32; // offset = 0x48, actual offset = 18 + uint32_t clkrst_ena_clk_95_64; // offset = 0x4c, actual offset = 19 + uint32_t reserved2[11]; // offset = 0x50-0x78, actual offset = 20-30 + uint32_t clkrst_ena_reset_31_0; // offset = 0x7c, actual offset = 31 + uint32_t clkrst_ena_reset_63_32; // offset = 0x80, actual offset = 32 + uint32_t clkrst_pll_observe_clk; // offset = 0x84, actual offset = 33 + uint32_t clkrst_ref_cnt_thresh; // offset = 0x88, actual offset = 34 + uint32_t clkrst_pll_clk_low_th; // offset = 0x8c, actual offset = 35 + uint32_t clkrst_pll_clk_hi_th; // offset = 0x90, actual offset = 36 + uint32_t clkrst_pll_clk_stat; // offset = 0x94, actual offset = 37 + uint32_t clkrst_sticky_bit_stat; // offset = 0x98, actual offset = 38 + uint32_t clkrst_clk250_src_sel; // offset = 0x9c, actual offset = 39 + uint32_t clkrst_ena_force; // offset = 0xa0, actual offset = 40 + uint32_t reserved3; // offset = 0xa4, actual offset = 41 + uint32_t pmd_xtal_cntl; // offset = 0xa8, actual offset = 42 + uint32_t pmd_xtal_cntl2; // offset = 0xac, actual offset = 43 +#else + uint32_t reserved0; // offset = 0x24, actual offset = 9 + BPCM_SR_CONTROL sr_control; // offset = 0x28, actual offset = 10 + uint32_t reserved1; // offset = 0x2c, actual offset = 11 + uint32_t clkrst_cfg; // offset = 0x30, actual offset = 12 +#if IS_BCMCHIP(63146) + BPCM_CLKRST_VREG_CONTROL vreg_control; // offset 0x50, PMB reg index 19 +#else + uint32_t clkrst_control; // offset = 0x34, actual offset = 13 +#endif + uint32_t xtal_control; // offset = 0x38, actual offset = 14 + uint32_t clkrst_stat; // offset = 0x3c, actual offset = 15 +#endif +} BPCM_CLKRST_REGS; +#endif + +#define CLKRSTBPCMOffset(reg) offsetof(BPCM_CLKRST_REGS, reg) +#define CLKRSTBPCMRegOffset(reg) (CLKRSTBPCMOffset(reg) >> 2) + +#if IS_BCMCHIP(47622) || IS_BCMCHIP(6756) +typedef struct { + BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0 + BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1 + uint32_t reserved0[2]; // offset 0x08, PMB reg index 2/3 + // BPCM + uint32_t control; // offset 0x10, PMB reg index 4 + BPCM_SR_CONTROL sr_control; // offset 0x14, PMB reg index 5 + + uint32_t z0_pm_cntl; // offset 0x18 + uint32_t z0_pm_status; // offset 0x1c + uint32_t z1_pm_cntl; // offset 0x20 + uint32_t z2_pm_cntl; // offset 0x24 + uint32_t reserved1[22]; // reserved from 0x28 to 0x7F + BPCM_ZONE zones[]; + +} BPCM_SYSPORT_REGS; + +#define SYSPOffset(reg) offsetof(BPCM_SYSPORT_REGS,reg) +#define SYSPRegOffset(reg) (SYSPOffset(reg) >> 2) + +#endif + +#if IS_BCMCHIP(63146) || IS_BCMCHIP(4912) +typedef struct { + // ETH_PMB + BPCM_ID_REG id_reg; // offset 0x00, PMB reg index 0 + BPCM_CAPABILITES_REG capabilities; // offset 0x04, PMB reg index 1 + uint32_t reserved8[2]; // offset 0x08, PMB reg index 2/3 + // ETH_CFG + uint32_t dpg_zones; // offset 0x10, PMB reg index 4 + uint32_t soft_rst;; // offset 0x14, PMB reg index 5 + uint32_t reserved18[2]; // offset 0x18, PMB reg index 6/7 + // ETH_CORE +#if IS_BCMCHIP(63146) + uint32_t qphy_cntrl; // offset 0x20 + uint32_t qphy_status; // offset 0x24 + uint32_t sphy_cntrl; // offset 0x28 + uint32_t sphy_status; // offset 0x2c + uint32_t serdes0_cntrl; // offset 0x30 + uint32_t serdes0_status;// offset 0x34 + uint32_t serdes0_an_st; // offset 0x38 + uint32_t serdes1_cntrl; // offset 0x3c + uint32_t serdes1_status;// offset 0x40 + uint32_t serdes1_an_st; // offset 0x44 + uint32_t reserved48[3]; + uint32_t rgmii_cntrl; // offset 0x54 + uint32_t reserved58[2]; + uint32_t serdes0_st1; // offset 0x60 + uint32_t serdes1_st1; // offset 0x64 + uint32_t reserved68; + uint32_t serdes0_pwr_cntrl;// offset 0x6c + uint32_t serdes1_pwr_cntrl;// offset 0x70 +#endif +#if IS_BCMCHIP(4912) + uint32_t qphy_cntrl; // offset 0x20 + uint32_t qphy_status; // offset 0x24 + uint32_t reserved28[2]; + uint32_t serdes0_cntrl; // offset 0x30 + uint32_t serdes0_status;// offset 0x34 + uint32_t serdes0_an_st; // offset 0x38 + uint32_t serdes1_cntrl; // offset 0x3c + uint32_t serdes1_status;// offset 0x40 + uint32_t serdes1_an_st; // offset 0x44 + uint32_t serdes2_cntrl; // offset 0x48 + uint32_t serdes2_status;// offset 0x4c + uint32_t serdes2_an_st; // offset 0x50 + uint32_t rgmii_cntrl; // offset 0x54 + uint32_t xport0_cntrl; // offset 0x58 + uint32_t xport1_cntrl; // offset 0x5c + uint32_t serdes0_st1; // offset 0x60 + uint32_t serdes1_st1; // offset 0x64 + uint32_t serdes2_st1; // offset 0x68 + uint32_t serdes0_pwr_cntrl;// offset 0x6c + uint32_t serdes1_pwr_cntrl;// offset 0x70 + uint32_t serdes2_pwr_cntrl;// offset 0x74 +#endif +} BPCM_ETH_REGS; + +#define BPCMETHOffset(reg) offsetof(BPCM_ETH_REGS,reg) +#define BPCMETHRegOffset(reg) (BPCMETHOffset(reg) >> 2) + +#endif + +// *************************** macros ****************************** +#ifndef offsetof +#define offsetof(TYPE, MEMBER) ((unsigned long) &((TYPE *)0)->MEMBER) +#endif + +#endif diff --git a/plat/bcm/include/bcm963xx/47622_map_part.h b/plat/bcm/include/bcm963xx/47622_map_part.h new file mode 100644 index 00000000..c8c47ac0 --- /dev/null +++ b/plat/bcm/include/bcm963xx/47622_map_part.h @@ -0,0 +1,494 @@ +/* +<:copyright-BRCM:2015:DUAL/GPL:standard + + Copyright (c) 2015 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> + +*/ + +#ifndef __BCM47622_MAP_PART_H +#define __BCM47622_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define MEMC_PHYS_BASE 0x80180000 +#define MEMC_SIZE 0x24000 + +#define PMC_PHYS_BASE 0x80200000 +#define PMC_SIZE 0x00200000 +#define PMC_OFFSET 0x00100000 +#define PROC_MON_OFFSET 0x00100000 +#define PMB_OFFSET 0x00120100 + +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x13000 +#define TIMR_OFFSET 0x0400 +#define WDTIMR0_OFFSET 0x0480 +#define WDTIMR1_OFFSET 0x04c0 + +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define BOOTLUT_PHYS_BASE 0xffff0000 +#define BOOTLUT_SIZE 0x1000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + +#define PMC_BASE (PMC_PHYS_BASE + PMC_OFFSET) +#define PROC_MON_BASE (PMC_PHYS_BASE + PROC_MON_OFFSET) +#define PMB_BASE (PMC_PHYS_BASE + PMB_OFFSET) +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) + +#ifndef __ASSEMBLER__ +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + uint32 gpTmr0Ctl; /* 0x018 */ + uint32 gpTmr0Cnt; /* 0x01c */ + uint32 gpTmr1Ctl; /* 0x020 */ + uint32 gpTmr1Cnt; /* 0x024 */ + uint32 hostMboxIn; /* 0x028 */ + uint32 hostMboxOut; /* 0x02c */ + uint32 reserved[4]; /* 0x030 */ + uint32 dmaCtrl; /* 0x040 */ + uint32 dmaStatus; /* 0x044 */ + uint32 dma0_3FifoStatus; /* 0x048 */ + uint32 reserved1[4]; /* 0x04c */ + uint32 diagControl; /* 0x05c */ + uint32 diagHigh; /* 0x060 */ + uint32 diagLow; /* 0x064 */ + uint32 reserved8; /* 0x068 */ + uint32 addr1WndwMask; /* 0x06c */ + uint32 addr1WndwBaseIn; /* 0x070 */ + uint32 addr1WndwBaseOut; /* 0x074 */ + uint32 addr2WndwMask; /* 0x078 */ + uint32 addr2WndwBaseIn; /* 0x07c */ + uint32 addr2WndwBaseOut; /* 0x080 */ + uint32 scratch; /* 0x084 */ + uint32 reserved9; /* 0x088 */ + uint32 softResets; /* 0x08c */ + uint32 reserved2; /* 0x090 */ + uint32 m4keCoreStatus; /* 0x094 */ + uint32 reserved3; /* 0x098 */ + uint32 ubSlaveTimeout; /* 0x09c */ + uint32 diagEn; /* 0x0a0 */ + uint32 devTimeout; /* 0x0a4 */ + uint32 ubusErrorOutMask; /* 0x0a8 */ + uint32 diagCaptStopMask; /* 0x0ac */ + uint32 revId; /* 0x0b0 */ + uint32 reserved4[4]; /* 0x0b4 */ + uint32 diagCtrl; /* 0x0c4 */ + uint32 diagStat; /* 0x0c8 */ + uint32 diagMask; /* 0x0cc */ + uint32 diagRslt; /* 0x0d0 */ + uint32 diagCmp; /* 0x0d4 */ + uint32 diagCapt; /* 0x0d8 */ + uint32 diagCnt; /* 0x0dc */ + uint32 diagEdgeCnt; /* 0x0e0 */ + uint32 reserved5[4]; /* 0x0e4 */ + uint32 smisc_bus_config; /* 0x0f4 */ + uint32 lfsr; /* 0x0f8 */ + uint32 dqm_pac_lock; /* 0x0fc */ + uint32 l1_irq_4ke_mask; /* 0x100 */ + uint32 l1_irq_4ke_status; /* 0x104 */ + uint32 l1_irq_mips_mask; /* 0x108 */ + uint32 l1_irq_mips_status; /* 0x10c */ + uint32 l1_irq_mips1_mask; /* 0x110 */ + uint32 reserved6[3]; /* 0x114 */ + uint32 l2_irq_gp_mask; /* 0x120 */ + uint32 l2_irq_gp_status; /* 0x124 */ + uint32 l2_irq_gp_set; /* 0x128 */ + uint32 reserved7; /* 0x12c */ + uint32 gp_in_irq_mask; /* 0x130 */ + uint32 gp_in_irq_status; /* 0x134 */ + uint32 gp_in_irq_set; /* 0x138 */ + uint32 gp_in_irq_sense; /* 0x13c */ + uint32 gp_in; /* 0x140 */ + uint32 gp_out; /* 0x144 */ +} PmcCtrlReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + uint32 freqScalarCtrl; /* 0x3c */ + uint32 freqScalarMask; /* 0x40 */ +} PmcPerfPowReg; + +typedef struct PmcDQMPac { + uint32 dqmPac[32]; +} PmcDQMPac; + +typedef struct PmcDQMReg { + uint32 cfg; /* 0x1c00 */ + uint32 _4keLowWtmkIrqMask; /* 0x1c04 */ + uint32 mipsLowWtmkIrqMask; /* 0x1c08 */ + uint32 lowWtmkIrqMask; /* 0x1c0c */ + uint32 _4keNotEmptyIrqMask; /* 0x1c10 */ + uint32 mipsNotEmptyIrqMask; /* 0x1c14 */ + uint32 notEmptyIrqSts; /* 0x1c18 */ + uint32 queueRst; /* 0x1c1c */ + uint32 notEmptySts; /* 0x1c20 */ + uint32 nextAvailMask; /* 0x1c24 */ + uint32 nextAvailQueue; /* 0x1c28 */ + uint32 mips1LowWtmkIrqMask; /* 0x1c2c */ + uint32 mips1NotEmptyIrqMask; /* 0x1c30 */ + uint32 autoSrcPidInsert; /* 0x1c34 */ + uint32 timerIrqStatus; /* 0x1c38 */ + uint32 timerStatus; /* 0x1c3c */ + uint32 _4keTimerIrqMask; /* 0x1c40 */ + uint32 mipsTimerIrqMask; /* 0x1c44 */ + uint32 mips1TimerIrqMask; /* 0x1c48 */ +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct SSBMaster { + uint32 ssbmControl; /* 0x0060 */ + uint32 ssbmWrData; /* 0x0064 */ + uint32 ssbmRdData; /* 0x0068 */ + uint32 ssbmStatus; /* 0x006c */ +} SSBMaster; + +typedef struct PmmReg { + uint32 memPowerCtrl; /* 0x0000 */ + uint32 regSecurityConfig; /* 0x0004 */ +} PmmReg; + +typedef struct keyholeReg { + uint32 ctrlSts; + uint32 wrData; + uint32 mutex; + uint32 rdData; +} keyholeReg; + +typedef struct PmbBus { + uint32 config; /* 0x0100 */ + uint32 arbiter; /* 0x0104 */ + uint32 timeout; /* 0x0108 */ + uint32 unused1; /* 0x010c */ + keyholeReg keyhole[4]; /* 0x0110-0x014f */ + uint32 unused2[44]; /* 0x0150-0x01ff */ + uint32 map[64]; /* 0x0200-0x02ff */ +}PmbBus; + +typedef struct CoreCtrl { + uint32 coreEnable; /* 0x0400 */ + uint32 autoresetControl; /* 0x0404 */ + uint32 coreIdle; /* 0x0408 */ + uint32 coreResetCause; /* 0x040c */ + uint32 memPwrDownCtrl0; /* 0x0410 */ + uint32 memPwrDownSts0; /* 0x0414 */ + uint32 memPwrDownCtrl1; /* 0x0418 */ + uint32 memPwrDownSts1; /* 0x041c */ + uint32 sysFlg0Status; /* 0x0420 */ + uint32 sysFlg0Set; /* 0x0424 */ + uint32 sysFlg0Clear; /* 0x0428 */ + uint32 unused1; /* 0x042c */ + uint32 usrFlg0Status; /* 0x0430 */ + uint32 usrFlg0Set; /* 0x0434 */ + uint32 usrFlg0Clear; /* 0x0438 */ + uint32 unused2; /* 0x043c */ + uint32 subsystemRev; /* 0x0440 */ + uint32 resetVector; /* 0x0444 */ +} CoreCtrl; + +typedef struct CoreState { + uint32 sysMbx[8]; /* 0x0480 */ + uint32 usrMbx[8]; /* 0x04a0 */ + uint32 sysMtx[4]; /* 0x04c0 */ + uint32 usrMtx[8]; /* 0x04d0 */ +} CoreState; + +typedef struct CoreIntr { + uint32 irqStatus; /* 0x0500 */ + uint32 irqSet; /* 0x0504 */ + uint32 irqClear; /* 0x0508 */ + uint32 unused1; /* 0x050c */ + uint32 srqStatus; /* 0x0510 */ + uint32 srqSet; /* 0x0514 */ + uint32 srqClear; /* 0x0518 */ + uint32 unused2; /* 0x051c */ + uint32 drqStatus; /* 0x0520 */ + uint32 drqSet; /* 0x0524 */ + uint32 drqClear; /* 0x0528 */ + uint32 unused3; /* 0x052c */ + uint32 frqStatus; /* 0x0530 */ + uint32 frqSet; /* 0x0534 */ + uint32 frqClear; /* 0x0538 */ + uint32 unused4; /* 0x053c */ + uint32 hostIrqLatched; /* 0x0540 */ + uint32 hostIrqSet; /* 0x0544 */ + uint32 hostIrqClear; /* 0x0548 */ + uint32 hostIrqEnable; /* 0x054c */ + uint32 obusFaultStatus; /* 0x0550 */ + uint32 obusFaultClear; /* 0x0554 */ + uint32 obusFaultAddr; /* 0x0558 */ +} CoreIntr; + +typedef struct CoreProfile { + uint32 mutex; /* 0x0580 */ + uint32 lastConfPcLo; /* 0x0584 */ + uint32 lastConfPcHi; /* 0x0588 */ + uint32 lastPcLo; /* 0x058c */ + uint32 lastPcHi; /* 0x0590 */ + uint32 braTargetPc0Lo; /* 0x0594 */ + uint32 braTargetPc0Hi; /* 0x0598 */ + uint32 braTargetPc1Lo; /* 0x059c */ + uint32 braTargetPc1Hi; /* 0x05a0 */ + uint32 braTargetPc2Lo; /* 0x05a4 */ + uint32 braTargetPc2Hi; /* 0x05a8 */ + uint32 braTargetPc3Lo; /* 0x05ac */ + uint32 braTargetPc3Hi; /* 0x05b0 */ + uint32 unused[3]; /* 0x05b4-0x05bf */ + uint32 profSampleW[4]; /* 0x05c0 */ +} CoreProfile; + +typedef struct MaestroMisc { + CoreCtrl coreCtrl; /* 0x0400 */ + uint32 unused1[14]; /* 0x0448-0x047f */ + CoreState coreState; /* 0x0480 */ + uint32 unused2[4]; /* 0x04f0-0x04ff */ + CoreIntr interrupt; /* 0x0500 */ + uint32 unused3[9]; /* 0x055c-0x057f */ + CoreProfile profile; /* 0x0580 */ +} MaestroMisc; + +typedef struct Pmc { + uint32 unused0[1030]; + PmcCtrlReg ctrl; /* 0x1018 */ + uint32 unused1[622]; /* 0x1148-0x1cff */ + PmcDQMPac dqmPac; /* 0x1b00 */ + uint32 unused5[32]; /* 0x1b80-0x1bff */ + PmcDQMReg dqm; /* 0x1c00 */ + uint32 unused6[749]; /* 0x1c4c-0x27ff */ + uint32 qStatus[32]; /* 0x2800 */ + uint32 unused7[480]; /* 0x2880-0x2fff */ + PmcDqmQMibReg qMib; /* 0x3000 */ + uint32 unused8[928]; /* 0x3180-0x3fff */ + PmcDqmQCtrlReg dqmQCtrl[8]; /* 0x4000 */ + uint32 unused9[992]; /* 0x4080-0x4fff */ + PmcDqmQDataReg dqmQData[8]; /* 0x5000 */ +} Pmc; + +#define PMC ((volatile Pmc * const) PMC_BASE) +typedef struct Procmon { + uint32 unused00[256]; + MaestroMisc maestroReg; /* 0x00400 */ + uint32 unused10[32396]; /* 0x005d0-0x1ffff */ + PmmReg pmm; /* 0x20000 */ + uint32 unused11[22]; /* 0x20008-0x2005f */ + SSBMaster ssbMasterCtrl; /* 0x20060 */ + uint32 unused12[36]; /* 0x20070-0x200ff */ + PmbBus pmb; /* 0x20100 */ + uint32 unused13[32576]; /* 0x20300-0x3ffff */ + uint32 qsm[128]; /* 0x40000-0x401ff */ + uint32 unused14[65408]; /* 0x40200-0x7ffff */ + uint32 dtcm[1024]; /* 0x80000-0x80fff */ +} Procmon; +#define PROCMON ((volatile Procmon * const) PROC_MON_BASE) + +typedef struct PMSSBMasterControl { + uint32 control; + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct +{ + uint32 control; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_BUS_SHIFT (20) +#define PMC_PMBM_Read (0 << 24) +#define PMC_PMBM_Write (1 << 24) + uint32 wr_data; + uint32 mutex; + uint32 rd_data; +} PMB_keyhole_reg; + +typedef struct PMBMaster { + uint32 config; +#define PMB_NUM_REGS_SHIFT (20) +#define PMB_NUM_REGS_MASK (0x3ff) + uint32 arbitger; + uint32 timeout; + uint32 reserved; + PMB_keyhole_reg keyhole[4]; + uint32 reserved1[44]; + uint32 map[64]; +} PMBMaster; +#define PMB ((volatile PMBMaster * const) PMB_BASE) + +typedef struct WDTimer { + uint32 WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * * * Read from this register returns current watch dog count + * * */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + +#define SOFT_RESET 0x00000001 + uint32 WDTimerCtl; + + uint32 WDAccessCtl; +} WDTimer; + +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + +typedef struct BIUCFG_Access { + uint32 permission; /* 0x0 */ + uint32 sbox; /* 0x4 */ + uint32 cpu_defeature; /* 0x8 */ + uint32 dbg_security; /* 0xc */ + uint32 rsvd1[32]; /* 0x10 - 0x8f */ + uint64 violation[2]; /* 0x90 - 0x9f */ + uint32 ts_access[2]; /* 0xa0 - 0xa7 */ + uint32 rsvd2[22]; +}BIUCFG_Access; + +typedef struct BIUCFG_Cluster { + uint32 permission; /* 0x0 */ + uint32 config; /* 0x4 */ + uint32 status; /* 0x8 */ + uint32 control; /* 0xc */ + uint32 cpucfg; /* 0x10 */ + uint32 dbgrom; /* 0x14 */ + uint32 rsvd1[2]; /* 0x18 - 0x1f */ + uint64 rvbar_addr[4]; /* 0x20 - 0x3f */ + uint32 rsvd2[48]; /* 0x40 - 0xff */ +}BIUCFG_Cluster; + +typedef struct BIUCFG_Bac { + uint32 bac_permission; /* 0x00 */ + uint32 bac_periphbase; /* 0x04 */ + uint32 rsvd[2]; /* 0x08 - 0x0f */ + uint32 bac_event; /* 0x10 */ + uint32 rsvd_1[3]; /* 0x14 - 0x1f */ + uint32 bac_ccicfg; /* 0x20 */ + uint32 bac_cciaddr; /* 0x24 */ + uint32 rsvd_2[4]; /* 0x28 - 0x37 */ + uint32 bac_ccievs2; /* 0x38 */ + uint32 bac_ccievs3; /* 0x3c */ + uint32 bac_ccievs4; /* 0x40 */ + uint32 rsvd_3[3]; /* 0x44 - 0x4f */ + uint32 bac_ccievm0; /* 0x50 */ + uint32 bac_ccievm1; /* 0x54 */ + uint32 rsvd_4[2]; /* 0x58 - 0x5f */ + uint32 bac_dapapbcfg; /* 0x60 */ + uint32 bac_status; /* 0x64 */ + uint32 rsvd_5[2]; /* 0x68 - 0x6f */ + uint32 cpu_therm_irq_cfg; /* 0x70 */ + uint32 cpu_therm_threshold_cfg; /* 0x74 */ + uint32 rsvd_6; /* 0x78 */ + uint32 cpu_therm_temp; /* 0x7c */ + uint32 rsvd_7[32]; /* 0x80 - 0xff */ +} BIUCFG_Bac; + +typedef struct BIUCFG_Aux { + uint32 aux_permission; /* 0x00 */ + uint32 rsvd[3]; /* 0x04 - 0x0f */ + uint32 c0_clk_control; /* 0x10 */ + uint32 c0_clk_ramp; /* 0x14 */ + uint32 c0_clk_pattern; /* 0x18 */ + uint32 rsvd_1; /* 0x1c */ + uint32 c1_clk_control; /* 0x20 */ + uint32 c1_clk_ramp; /* 0x24 */ + uint32 c1_clk_pattern; /* 0x28 */ + uint32 rsvd_2[53]; /* 0x2c - 0xff */ +} BIUCFG_Aux; + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff*/ + BIUCFG_Cluster cluster[2]; /* 0x100 - 0x2ff*/ + BIUCFG_Bac bac; /* 0x300 - 0x3ff */ + uint32 anonymous[192]; /* 0x400 - 0x6ff */ + BIUCFG_Aux aux; /* 0x700 - 0x7ff */ + uint32 anonymous_1[2560]; /* 0x800 - 0x2fff */ +}BIUCFG; +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + + + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/plat/bcm/include/bcm963xx/4908_map_part.h b/plat/bcm/include/bcm963xx/4908_map_part.h new file mode 100644 index 00000000..02aa9cc8 --- /dev/null +++ b/plat/bcm/include/bcm963xx/4908_map_part.h @@ -0,0 +1,552 @@ +/* +<:copyright-BRCM:2013:DUAL/GPL:standard + + Copyright (c) 2013 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef __BCM4908_MAP_PART_H +#define __BCM4908_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define MEMC_PHYS_BASE 0x80018000 /* DDR IO Buf Control */ +#define MEMC_SIZE 0x4000 + +#define PMC_PHYS_BASE 0x80200000 +#define PMC_SIZE 0x5000 +#define PMC_OFFSET 0x0000 +#define PROC_MON_PHYS_BASE 0x80280000 +#define PROC_MON_SIZE 0x1000 +#define PROC_MON_OFFSET 0x0000 + +/* Perf block base address and size */ +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x3000 +#define TIMR_OFFSET 0x0400 /* timer registers */ + +#define URB_PHYS_BASE 0x81060000 +#define URB_SIZE 0x4000 +#define URB_OFFSET 0x0000 +#define URB_BIUARCH_OFFSET 0x1000 +#define URB_BIUCTRL_OFFSET 0x2000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + +#define PMC_BASE (PMC_PHYS_BASE + PMC_OFFSET) +#define PROC_MON_BASE (PROC_MON_PHYS_BASE + PROC_MON_OFFSET) + +#define URB_BASE (URB_PHYS_BASE + URB_OFFSET) +#define BIUARCH_BASE (URB_PHYS_BASE + URB_BIUARCH_OFFSET) +#define BIUCTRL_BASE (URB_PHYS_BASE + URB_BIUCTRL_OFFSET) + +#ifndef __ASSEMBLER__ + +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + /* 0x00 */ + uint32 l1Irq4keMask; + uint32 l1Irq4keStatus; + uint32 l1IrqMipsMask; + uint32 l1IrqMipsStatus; + /* 0x10 */ + uint32 l2IrqGpMask; + uint32 l2IrqGpStatus; + uint32 gpTmr0Ctl; + uint32 gpTmr0Cnt; + /* 0x20 */ + uint32 gpTmr1Ctl; + uint32 gpTmr1Cnt; + uint32 hostMboxIn; + uint32 hostMboxOut; + /* 0x30 */ +#define PMC_CTRL_GP_FLASH_BOOT_STALL 0x00000080 + uint32 gpOut; + uint32 gpIn; + uint32 gpInIrqMask; + uint32 gpInIrqStatus; + /* 0x40 */ + uint32 dmaCtrl; + uint32 dmaStatus; + uint32 dma0_3FifoStatus; + uint32 unused0[3]; /* 0x4c-0x57 */ + /* 0x58 */ + uint32 l1IrqMips1Mask; + uint32 diagControl; + /* 0x60 */ + uint32 diagHigh; + uint32 diagLow; + uint32 badAddr; + uint32 addr1WndwMask; + /* 0x70 */ + uint32 addr1WndwBaseIn; + uint32 addr1WndwBaseOut; + uint32 addr2WndwMask; + uint32 addr2WndwBaseIn; + /* 0x80 */ + uint32 addr2WndwBaseOut; + uint32 scratch; + uint32 tm; + uint32 softResets; + /* 0x90 */ + uint32 eb2ubusTimeout; + uint32 m4keCoreStatus; + uint32 gpInIrqSense; + uint32 ubSlaveTimeout; + /* 0xa0 */ + uint32 diagEn; + uint32 devTimeout; + uint32 ubusErrorOutMask; + uint32 diagCaptStopMask; + /* 0xb0 */ + uint32 revId; + uint32 gpTmr2Ctl; + uint32 gpTmr2Cnt; + uint32 legacyMode; + /* 0xc0 */ + uint32 smisbMonitor; + uint32 diagCtrl; + uint32 diagStat; + uint32 diagMask; + /* 0xd0 */ + uint32 diagRslt; + uint32 diagCmp; + uint32 diagCapt; + uint32 diagCnt; + /* 0xe0 */ + uint32 diagEdgeCnt; + uint32 unused1[4]; /* 0xe4-0xf3 */ + /* 0xf4 */ + uint32 iopPeriphBaseAddr; + uint32 lfsr; + uint32 unused2; /* 0xfc-0xff */ +} PmcCtrlReg; + +typedef struct PmcOutFifoReg { + uint32 msgCtrl; /* 0x00 */ + uint32 msgSts; /* 0x04 */ + uint32 unused[14]; /* 0x08-0x3f */ + uint32 msgData[16]; /* 0x40-0x7c */ +} PmcOutFifoReg; + +typedef struct PmcInFifoReg { + uint32 msgCtrl; /* 0x00 */ + uint32 msgSts; /* 0x04 */ + uint32 unused[13]; /* 0x08-0x3b */ + uint32 msgLast; /* 0x3c */ + uint32 msgData[16]; /* 0x40-0x7c */ +} PmcInFifoReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + /* 0x00 */ + uint32 dcacheHit; + uint32 dcacheMiss; + uint32 icacheHit; + uint32 icacheMiss; + /* 0x10 */ + uint32 instnComplete; + uint32 wtbMerge; + uint32 wtbNoMerge; + uint32 itlbHit; + /* 0x20 */ + uint32 itlbMiss; + uint32 dtlbHit; + uint32 dtlbMiss; + uint32 jtlbHit; + /* 0x30 */ + uint32 jtlbMiss; + uint32 powerSubZone; + uint32 powerMemPda; + uint32 freqScalarCtrl; + /* 0x40 */ + uint32 freqScalarMask; +} PmcPerfPowReg; + +typedef struct PmcDQMReg { + /* 0x00 */ + uint32 cfg; + uint32 _4keLowWtmkIrqMask; + uint32 mipsLowWtmkIrqMask; + uint32 lowWtmkIrqMask; + /* 0x10 */ + uint32 _4keNotEmptyIrqMask; + uint32 mipsNotEmptyIrqMask; + uint32 notEmptyIrqSts; + uint32 queueRst; + /* 0x20 */ + uint32 notEmptySts; + uint32 nextAvailMask; + uint32 nextAvailQueue; + uint32 mips1LowWtmkIrqMask; + /* 0x30 */ + uint32 mips1NotEmptyIrqMask; + uint32 autoSrcPidInsert; +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct Pmc { + uint32 baseReserved; /* 0x0000 */ + uint32 unused0[1023]; + PmcCtrlReg ctrl; /* 0x1000 */ + + PmcOutFifoReg outFifo; /* 0x1100 */ + uint32 unused1[32]; /* 0x1180-0x11ff */ + PmcInFifoReg inFifo; /* 0x1200 */ + uint32 unused2[32]; /* 0x1280-0x12ff */ + + PmcDmaReg dma[2]; /* 0x1300 */ + uint32 unused3[48]; /* 0x1340-0x13ff */ + + PmcTokenReg token; /* 0x1400 */ + uint32 unused4[121]; /* 0x141c-0x15ff */ + + PmcPerfPowReg perfPower; /* 0x1600 */ + uint32 unused5[47]; /* 0x1644-0x16ff */ + + uint32 msgId[32]; /* 0x1700 */ + uint32 unused6[32]; /* 0x1780-0x17ff */ + + PmcDQMReg dqm; /* 0x1800 */ + uint32 unused7[50]; /* 0x1838-0x18ff */ + + PmcCntReg hwCounter; /* 0x1900 */ + uint32 unused8[46]; /* 0x1948-0x19ff */ + + PmcDqmQCtrlReg dqmQCtrl[32]; /* 0x1a00 */ + PmcDqmQDataReg dqmQData[32]; /* 0x1c00 */ + uint32 unused9[64]; /* 0x1e00-0x1eff */ + + uint32 qStatus[32]; /* 0x1f00 */ + uint32 unused10[32]; /* 0x1f80-0x1fff */ + + PmcDqmQMibReg qMib; /* 0x2000 */ + uint32 unused11[1952]; /* 0x2180-0x3ffff */ + + uint32 sharedMem[512]; /* 0x4000-0x47ff */ +} Pmc; + +#define PMC ((volatile Pmc * const) PMC_BASE) + +/* + * Process Monitor Module + */ +typedef struct PMRingOscillatorControl { + uint32 control; + uint32 en_lo; + uint32 en_mid; + uint32 en_hi; + uint32 idle_lo; + uint32 idle_mid; + uint32 idle_hi; +} PMRingOscillatorControl; + +#define RCAL_0P25UM_HORZ 0 +#define RCAL_0P25UM_VERT 1 +#define RCAL_0P5UM_HORZ 2 +#define RCAL_0P5UM_VERT 3 +#define RCAL_1UM_HORZ 4 +#define RCAL_1UM_VERT 5 +#define PMMISC_RMON_EXT_REG ((RCAL_1UM_VERT + 1)/2) +#define PMMISC_RMON_VALID_MASK (0x1<<16) +typedef struct PMMiscControl { + uint32 gp_out; + uint32 clock_select; + uint32 unused[2]; + uint32 misc[4]; +} PMMiscControl; + +typedef struct PMSSBMasterControl { + uint32 control; +#define PMC_SSBM_CONTROL_SSB_START (1<<15) +#define PMC_SSBM_CONTROL_SSB_ADPRE (1<<13) +#define PMC_SSBM_CONTROL_SSB_EN (1<<12) +#define PMC_SSBM_CONTROL_SSB_CMD_SHIFT (10) +#define PMC_SSBM_CONTROL_SSB_CMD_MASK (0x3 << PMC_SSBM_CONTROL_SSB_CMD_SHIFT) +#define PMC_SSBM_CONTROL_SSB_CMD_READ (2) +#define PMC_SSBM_CONTROL_SSB_CMD_WRITE (1) +#define PMC_SSBM_CONTROL_SSB_ADDR_SHIFT (0) +#define PMC_SSBM_CONTROL_SSB_ADDR_MASK (0x3ff << PMC_SSBM_CONTROL_SSB_ADDR_SHIFT) + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct PMEctrControl { + uint32 control; + uint32 interval; + uint32 thresh_lo; + uint32 thresh_hi; + uint32 count; +} PMEctrControl; + +typedef struct PMBMaster { + uint32 ctrl; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_Read (0 << 20) +#define PMC_PMBM_Write (1 << 20) + uint32 wr_data; + uint32 timeout; + uint32 rd_data; + uint32 unused[4]; +} PMBMaster; + +typedef struct PMAPVTMONControl { + uint32 control; + uint32 reserved; + uint32 cfg_lo; + uint32 cfg_hi; + uint32 data; + uint32 vref_data; + uint32 unused[2]; + uint32 ascan_cfg; + uint32 warn_temp; + uint32 reset_temp; + uint32 temp_value; + uint32 data1_value; + uint32 data2_value; + uint32 data3_value; +} PMAPVTMONControl; + +typedef struct PMUBUSCfg { + uint32 window[8]; + uint32 control; +} PMUBUSCfg; + +typedef struct ProcessMonitorRegs { + uint32 MonitorCtrl; /* 0x00 */ + uint32 unused0[7]; + PMRingOscillatorControl ROSC; /* 0x20 */ + uint32 unused1; + PMMiscControl Misc; /* 0x40 */ + PMSSBMasterControl SSBMaster; /* 0x60 */ + uint32 unused2[5]; + PMEctrControl Ectr; /* 0x80 */ + uint32 unused3[11]; + PMBMaster PMBM[2]; /* 0xc0 */ + PMAPVTMONControl APvtmonCtrl; /* 0x100 */ + uint32 unused4[9]; + PMUBUSCfg UBUSCfg; /* 0x160 */ +} ProcessMonitorRegs; + +#define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE) + +/* + * URB UBUS RBUS Block register + */ +typedef struct BIUArchRegion { + uint32 addr_ulimit; + uint32 addr_llimit; + uint32 permission; + uint32 access_right_ctrl; +} BIUArchRegion; + +typedef struct BIUArch { + BIUArchRegion region[8]; /* 0x0 */ + uint32 unused[95]; /* 0x80 */ + uint32 scratch; /* 0x1fc */ +} BIUArch; + +#define BIUARCH ((volatile BIUArch * const) BIUARCH_BASE) + +typedef struct BIUCpuBusRange { +#define ULIMIT_SHIFT 4 +#define BUSNUM_MASK 0x0000000FU + +#define BUSNUM_UBUS 1 +#define BUSNUM_RBUS 2 +#define BUSNUM_RSVD 3 +#define BUSNUM_MCP0 4 +#define BUSNUM_MCP1 5 +#define BUSNUM_MCP2 6 + + uint32 ulimit; + uint32 llimit; +} BIUCpuBusRange; + +typedef struct BIUCpuAccessRightViol { + uint32 addr; + uint32 upper_addr; + uint32 detail_addr; +} BIUCpuAccessRightViol; + +typedef struct BIUCpuBPCMAVS { + uint32 bpcm_id; + uint32 bpcm_capability; +} BIUCpuBPCMAVS; + +typedef struct BIUCtrl { + BIUCpuBusRange bus_range[11]; /* 0x0 */ + uint32 secure_reset_hndshake; + uint32 secure_soft_reset; + BIUCpuAccessRightViol access_right_viol[2]; /* 0x60 */ + uint32 rac_cfg0; + uint32 rac_cfg1; + uint32 rac_cfg2; /* 0x80 */ + uint32 rac_flush; + uint32 power_cfg; +#define BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON_SHIFT 4 +#define BIU_CPU_CTRL_PWR_CFG_CPU0_BPCM_INIT_ON (0x1< +*/ + +#ifndef __BCM4912_MAP_PART_H +#define __BCM4912_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define MEMC_PHYS_BASE 0x80040000 /* MC2 TOP */ +#define MEMC_SIZE 0x00040000 + +#define PMC_PHYS_BASE 0xffa00000 +#define PMC_SIZE 0x00200000 +#define PMC_OFFSET 0x00100000 +#define PROC_MON_OFFSET 0x00100000 +#define PMB_OFFSET 0x00120100 + + +/* Perf block base address and size */ +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x3500 +#define TIMR_OFFSET 0x0400 /* 64 bit timer registers */ +#define WDTIMR0_OFFSET 0x0480 +#define WDTIMR1_OFFSET 0x04c0 + + +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + +#define PMC_BASE (PMC_PHYS_BASE + PMC_OFFSET) +#define PROC_MON_BASE (PMC_PHYS_BASE + PROC_MON_OFFSET) +#define PMB_BASE (PMC_PHYS_BASE+ PMB_OFFSET) +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) + +#ifndef __ASSEMBLER__ +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + uint32 gpTmr0Ctl; /* 0x018 */ + uint32 gpTmr0Cnt; /* 0x01c */ + uint32 gpTmr1Ctl; /* 0x020 */ + uint32 gpTmr1Cnt; /* 0x024 */ + uint32 hostMboxIn; /* 0x028 */ + uint32 hostMboxOut; /* 0x02c */ + uint32 reserved[4]; /* 0x030 */ + uint32 dmaCtrl; /* 0x040 */ + uint32 dmaStatus; /* 0x044 */ + uint32 dma0_3FifoStatus; /* 0x048 */ + uint32 reserved1[4]; /* 0x04c */ + uint32 diagControl; /* 0x05c */ + uint32 diagHigh; /* 0x060 */ + uint32 diagLow; /* 0x064 */ + uint32 reserved8; /* 0x068 */ + uint32 addr1WndwMask; /* 0x06c */ + uint32 addr1WndwBaseIn; /* 0x070 */ + uint32 addr1WndwBaseOut; /* 0x074 */ + uint32 addr2WndwMask; /* 0x078 */ + uint32 addr2WndwBaseIn; /* 0x07c */ + uint32 addr2WndwBaseOut; /* 0x080 */ + uint32 scratch; /* 0x084 */ + uint32 reserved9; /* 0x088 */ + uint32 softResets; /* 0x08c */ + uint32 reserved2; /* 0x090 */ + uint32 m4keCoreStatus; /* 0x094 */ + uint32 reserved3; /* 0x098 */ + uint32 ubSlaveTimeout; /* 0x09c */ + uint32 diagEn; /* 0x0a0 */ + uint32 devTimeout; /* 0x0a4 */ + uint32 ubusErrorOutMask; /* 0x0a8 */ + uint32 diagCaptStopMask; /* 0x0ac */ + uint32 revId; /* 0x0b0 */ + uint32 reserved4[4]; /* 0x0b4 */ + uint32 diagCtrl; /* 0x0c4 */ + uint32 diagStat; /* 0x0c8 */ + uint32 diagMask; /* 0x0cc */ + uint32 diagRslt; /* 0x0d0 */ + uint32 diagCmp; /* 0x0d4 */ + uint32 diagCapt; /* 0x0d8 */ + uint32 diagCnt; /* 0x0dc */ + uint32 diagEdgeCnt; /* 0x0e0 */ + uint32 reserved5[4]; /* 0x0e4 */ + uint32 smisc_bus_config; /* 0x0f4 */ + uint32 lfsr; /* 0x0f8 */ + uint32 dqm_pac_lock; /* 0x0fc */ + uint32 l1_irq_4ke_mask; /* 0x100 */ + uint32 l1_irq_4ke_status; /* 0x104 */ + uint32 l1_irq_mips_mask; /* 0x108 */ + uint32 l1_irq_mips_status; /* 0x10c */ + uint32 l1_irq_mips1_mask; /* 0x110 */ + uint32 reserved6[3]; /* 0x114 */ + uint32 l2_irq_gp_mask; /* 0x120 */ + uint32 l2_irq_gp_status; /* 0x124 */ + uint32 l2_irq_gp_set; /* 0x128 */ + uint32 reserved7; /* 0x12c */ + uint32 gp_in_irq_mask; /* 0x130 */ + uint32 gp_in_irq_status; /* 0x134 */ + uint32 gp_in_irq_set; /* 0x138 */ + uint32 gp_in_irq_sense; /* 0x13c */ + uint32 gp_in; /* 0x140 */ + uint32 gp_out; /* 0x144 */ +} PmcCtrlReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + uint32 freqScalarCtrl; /* 0x3c */ + uint32 freqScalarMask; /* 0x40 */ +} PmcPerfPowReg; + +typedef struct PmcDQMPac { + uint32 dqmPac[32]; +} PmcDQMPac; + +typedef struct PmcDQMReg { + uint32 cfg; /* 0x1c00 */ + uint32 _4keLowWtmkIrqMask; /* 0x1c04 */ + uint32 mipsLowWtmkIrqMask; /* 0x1c08 */ + uint32 lowWtmkIrqMask; /* 0x1c0c */ + uint32 _4keNotEmptyIrqMask; /* 0x1c10 */ + uint32 mipsNotEmptyIrqMask; /* 0x1c14 */ + uint32 notEmptyIrqSts; /* 0x1c18 */ + uint32 queueRst; /* 0x1c1c */ + uint32 notEmptySts; /* 0x1c20 */ + uint32 nextAvailMask; /* 0x1c24 */ + uint32 nextAvailQueue; /* 0x1c28 */ + uint32 mips1LowWtmkIrqMask; /* 0x1c2c */ + uint32 mips1NotEmptyIrqMask; /* 0x1c30 */ + uint32 autoSrcPidInsert; /* 0x1c34 */ + uint32 timerIrqStatus; /* 0x1c38 */ + uint32 timerStatus; /* 0x1c3c */ + uint32 _4keTimerIrqMask; /* 0x1c40 */ + uint32 mipsTimerIrqMask; /* 0x1c44 */ + uint32 mips1TimerIrqMask; /* 0x1c48 */ +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct SSBMaster { + uint32 ssbmControl; /* 0x0060 */ + uint32 ssbmWrData; /* 0x0064 */ + uint32 ssbmRdData; /* 0x0068 */ + uint32 ssbmStatus; /* 0x006c */ +} SSBMaster; + +typedef struct PmmReg { + uint32 memPowerCtrl; /* 0x0000 */ + uint32 regSecurityConfig; /* 0x0004 */ +} PmmReg; + +typedef struct keyholeReg { + uint32 ctrlSts; + uint32 wrData; + uint32 mutex; + uint32 rdData; +} keyholeReg; + +typedef struct PmbBus { + uint32 config; /* 0x0100 */ + uint32 arbiter; /* 0x0104 */ + uint32 timeout; /* 0x0108 */ + uint32 unused1; /* 0x010c */ + keyholeReg keyhole[4]; /* 0x0110-0x014f */ + uint32 unused2[44]; /* 0x0150-0x01ff */ + uint32 map[64]; /* 0x0200-0x02ff */ +}PmbBus; + +typedef struct CoreCtrl { + uint32 coreEnable; /* 0x0400 */ + uint32 autoresetControl; /* 0x0404 */ + uint32 coreIdle; /* 0x0408 */ + uint32 coreResetCause; /* 0x040c */ + uint32 memPwrDownCtrl0; /* 0x0410 */ + uint32 memPwrDownSts0; /* 0x0414 */ + uint32 memPwrDownCtrl1; /* 0x0418 */ + uint32 memPwrDownSts1; /* 0x041c */ + uint32 sysFlg0Status; /* 0x0420 */ + uint32 sysFlg0Set; /* 0x0424 */ + uint32 sysFlg0Clear; /* 0x0428 */ + uint32 unused1; /* 0x042c */ + uint32 usrFlg0Status; /* 0x0430 */ + uint32 usrFlg0Set; /* 0x0434 */ + uint32 usrFlg0Clear; /* 0x0438 */ + uint32 unused2; /* 0x043c */ + uint32 subsystemRev; /* 0x0440 */ + uint32 resetVector; /* 0x0444 */ +} CoreCtrl; + +typedef struct CoreState { + uint32 sysMbx[8]; /* 0x0480 */ + uint32 usrMbx[8]; /* 0x04a0 */ + uint32 sysMtx[4]; /* 0x04c0 */ + uint32 usrMtx[8]; /* 0x04d0 */ +} CoreState; + +typedef struct CoreIntr { + uint32 irqStatus; /* 0x0500 */ + uint32 irqSet; /* 0x0504 */ + uint32 irqClear; /* 0x0508 */ + uint32 unused1; /* 0x050c */ + uint32 srqStatus; /* 0x0510 */ + uint32 srqSet; /* 0x0514 */ + uint32 srqClear; /* 0x0518 */ + uint32 unused2; /* 0x051c */ + uint32 drqStatus; /* 0x0520 */ + uint32 drqSet; /* 0x0524 */ + uint32 drqClear; /* 0x0528 */ + uint32 unused3; /* 0x052c */ + uint32 frqStatus; /* 0x0530 */ + uint32 frqSet; /* 0x0534 */ + uint32 frqClear; /* 0x0538 */ + uint32 unused4; /* 0x053c */ + uint32 hostIrqLatched; /* 0x0540 */ + uint32 hostIrqSet; /* 0x0544 */ + uint32 hostIrqClear; /* 0x0548 */ + uint32 hostIrqEnable; /* 0x054c */ + uint32 obusFaultStatus; /* 0x0550 */ + uint32 obusFaultClear; /* 0x0554 */ + uint32 obusFaultAddr; /* 0x0558 */ +} CoreIntr; + +typedef struct CoreProfile { + uint32 mutex; /* 0x0580 */ + uint32 lastConfPcLo; /* 0x0584 */ + uint32 lastConfPcHi; /* 0x0588 */ + uint32 lastPcLo; /* 0x058c */ + uint32 lastPcHi; /* 0x0590 */ + uint32 braTargetPc0Lo; /* 0x0594 */ + uint32 braTargetPc0Hi; /* 0x0598 */ + uint32 braTargetPc1Lo; /* 0x059c */ + uint32 braTargetPc1Hi; /* 0x05a0 */ + uint32 braTargetPc2Lo; /* 0x05a4 */ + uint32 braTargetPc2Hi; /* 0x05a8 */ + uint32 braTargetPc3Lo; /* 0x05ac */ + uint32 braTargetPc3Hi; /* 0x05b0 */ + uint32 unused[3]; /* 0x05b4-0x05bf */ + uint32 profSampleW[4]; /* 0x05c0 */ +} CoreProfile; + +typedef struct MaestroMisc { + CoreCtrl coreCtrl; /* 0x0400 */ + uint32 unused1[14]; /* 0x0448-0x047f */ + CoreState coreState; /* 0x0480 */ + uint32 unused2[4]; /* 0x04f0-0x04ff */ + CoreIntr interrupt; /* 0x0500 */ + uint32 unused3[9]; /* 0x055c-0x057f */ + CoreProfile profile; /* 0x0580 */ +} MaestroMisc; + +typedef struct Pmc { + uint32 unused0[1030]; + PmcCtrlReg ctrl; /* 0x1018 */ + uint32 unused1[622]; /* 0x1148-0x1cff */ + PmcDQMPac dqmPac; /* 0x1b00 */ + uint32 unused5[32]; /* 0x1b80-0x1bff */ + PmcDQMReg dqm; /* 0x1c00 */ + uint32 unused6[749]; /* 0x1c4c-0x27ff */ + uint32 qStatus[32]; /* 0x2800 */ + uint32 unused7[480]; /* 0x2880-0x2fff */ + PmcDqmQMibReg qMib; /* 0x3000 */ + uint32 unused8[928]; /* 0x3180-0x3fff */ + PmcDqmQCtrlReg dqmQCtrl[8]; /* 0x4000 */ + uint32 unused9[992]; /* 0x4080-0x4fff */ + PmcDqmQDataReg dqmQData[8]; /* 0x5000 */ +} Pmc; +#define PMC ((volatile Pmc * const) PMC_BASE) + +typedef struct Procmon { + uint32 unused00[256]; + MaestroMisc maestroReg; /* 0x00400 */ + uint32 unused10[32396]; /* 0x005d0-0x1ffff */ + PmmReg pmm; /* 0x20000 */ + uint32 unused11[22]; /* 0x20008-0x2005f */ + SSBMaster ssbMasterCtrl; /* 0x20060 */ + uint32 unused12[36]; /* 0x20070-0x200ff */ + PmbBus pmb; /* 0x20100 */ + uint32 unused13[32576]; /* 0x20300-0x3ffff */ + uint32 qsm[128]; /* 0x40000-0x401ff */ + uint32 unused14[65408]; /* 0x40200-0x7ffff */ + uint32 dtcm[1024]; /* 0x80000-0x80fff */ + uint32 unused15[64512]; /* 0x81000-0xbffff */ + uint32 itcm[4096]; /* 0xc0000-0xc3fff */ +} Procmon; +#define PROCMON ((volatile Procmon * const) PROC_MON_BASE) + +typedef struct PMSSBMasterControl { + uint32 control; + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct +{ + uint32 control; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_BUS_SHIFT (20) +#define PMC_PMBM_Read (0 << 24) +#define PMC_PMBM_Write (1 << 24) + uint32 wr_data; + uint32 mutex; + uint32 rd_data; +} PMB_keyhole_reg; + +typedef struct PMBMaster { + uint32 config; +#define PMB_NUM_REGS_SHIFT (20) +#define PMB_NUM_REGS_MASK (0x3ff) + uint32 arbitger; + uint32 timeout; + uint32 reserved; + PMB_keyhole_reg keyhole[4]; + uint32 reserved1[44]; + uint32 map[64]; +} PMBMaster; +#define PMB ((volatile PMBMaster * const) PMB_BASE) + + +typedef struct WDTimer { + uint32 WatchDogDefCount; + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 SoftRst; +#define SOFT_RESET 0x00000001 + uint32 WDAccessCtl; +} WDTimer; + +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + + +typedef struct BIUCFG_Access { + uint32 permission; /* 0x0 */ + uint32 sbox; /* 0x4 */ + uint32 cpu_defeature; /* 0x8 */ + uint32 dbg_security; /* 0xc */ + uint32 rsvd1[32]; /* 0x10 - 0x8f */ + uint64 violation[2]; /* 0x90 - 0x9f */ + uint32 ts_access[2]; /* 0xa0 - 0xa7 */ + uint32 rsvd2[22]; /* 0xa8 - 0xff */ +}BIUCFG_Access; + +typedef struct BIUCFG_Cluster { + uint32 permission; /* 0x0 */ + uint32 config; /* 0x4 */ + uint32 status; /* 0x8 */ + uint32 control; /* 0xc */ + uint32 cpucfg; /* 0x10 */ + uint32 dbgrom; /* 0x14 */ + uint32 rsvd1[2]; /* 0x18 - 0x1f */ + uint64 rvbar_addr[4]; /* 0x20 - 0x3f */ + uint32 rsvd2[48]; /* 0x40 - 0xff */ +}BIUCFG_Cluster; + +typedef struct BIUCFG_Bac { + uint32 bac_permission; /* 0x00 */ + uint32 bac_periphbase; /* 0x04 */ + uint32 rsvd[2]; /* 0x08 - 0x0f */ + uint32 bac_event; /* 0x10 */ + uint32 rsvd_1[3]; /* 0x14 - 0x1f */ + uint32 bac_ccicfg; /* 0x20 */ + uint32 bac_cciaddr; /* 0x24 */ + uint32 rsvd_2[4]; /* 0x28 - 0x37 */ + uint32 bac_ccievs2; /* 0x38 */ + uint32 bac_ccievs3; /* 0x3c */ + uint32 bac_ccievs4; /* 0x40 */ + uint32 rsvd_3[3]; /* 0x44 - 0x4f */ + uint32 bac_ccievm0; /* 0x50 */ + uint32 bac_ccievm1; /* 0x54 */ + uint32 rsvd_4[2]; /* 0x58 - 0x5f */ + uint32 bac_dapapbcfg; /* 0x60 */ + uint32 bac_status; /* 0x64 */ + uint32 rsvd_5[2]; /* 0x68 - 0x6f */ + uint32 cpu_therm_irq_cfg; /* 0x70 */ + uint32 cpu_therm_threshold_cfg; /* 0x74 */ + uint32 rsvd_6; /* 0x78 */ + uint32 cpu_therm_temp; /* 0x7c */ + uint32 rsvd_7[32]; /* 0x80 - 0xff */ +} BIUCFG_Bac; + +typedef struct BIUCFG_Aux { + uint32 aux_permission; /* 0x00 */ + uint32 rsvd[3]; /* 0x04 - 0x0f */ + uint32 c0_clk_control; /* 0x10 */ + uint32 c0_clk_ramp; /* 0x14 */ + uint32 c0_clk_pattern; /* 0x18 */ + uint32 rsvd_1; /* 0x1c */ + uint32 c1_clk_control; /* 0x20 */ + uint32 c1_clk_ramp; /* 0x24 */ + uint32 c1_clk_pattern; /* 0x28 */ + uint32 rsvd_2[53]; /* 0x2c - 0xff */ +} BIUCFG_Aux; + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff*/ + BIUCFG_Cluster cluster[2]; /* 0x100 - 0x2ff*/ + BIUCFG_Bac bac; /* 0x300 - 0x3ff */ + uint32 anonymous[192]; /* 0x400 - 0x6ff */ + BIUCFG_Aux aux; /* 0x700 - 0x7ff */ + uint32 anonymous_1[2560]; /* 0x800 - 0x2fff */ +}BIUCFG; + +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/plat/bcm/include/bcm963xx/63138_map_part.h b/plat/bcm/include/bcm963xx/63138_map_part.h new file mode 100644 index 00000000..b6b1be56 --- /dev/null +++ b/plat/bcm/include/bcm963xx/63138_map_part.h @@ -0,0 +1,458 @@ +/* +<:copyright-BRCM:2013:DUAL/GPL:standard + + Copyright (c) 2013 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef __BCM63138_MAP_PART_H +#define __BCM63138_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define PER_BASE 0xfffe0000 +#define REG_BASE 0x80000000 + +#define MEMC_PHYS_BASE (REG_BASE + 0x00002000) /* DDR IO Buf Control */ +#define MEMC_SIZE 0x20000 + +#define PMC_PHYS_BASE (REG_BASE + 0x00400000) +#define PROC_MON_PHYS_BASE (REG_BASE + 0x00480000) +#define GICC_PHYS_BASE (REG_BASE + 0x0001e100) +#define GICD_PHYS_BASE (REG_BASE + 0x0001f000) + +#define PERF_PHYS_BASE (PER_BASE + 0x00008000) /* chip control */ +#define TIMR_PHYS_BASE (PER_BASE + 0x00008080) /* timer registers */ +#define BOOTLUT_PHYS_BASE (PER_BASE + 0x00010000) + +#define PMC_BASE PMC_PHYS_BASE +#define PROC_MON_BASE PROC_MON_PHYS_BASE +#define TIMR_BASE TIMR_PHYS_BASE +#define BOOTLUT_BASE BOOTLUT_PHYS_BASE +#define GICC_BASE GICC_PHYS_BASE +#define GICD_BASE GICD_PHYS_BASE + + +#ifndef __ASSEMBLER__ + +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + /* 0x00 */ + uint32 l1Irq4keMask; + uint32 l1Irq4keStatus; + uint32 l1IrqMipsMask; + uint32 l1IrqMipsStatus; + /* 0x10 */ + uint32 l2IrqGpMask; + uint32 l2IrqGpStatus; + uint32 gpTmr0Ctl; + uint32 gpTmr0Cnt; + /* 0x20 */ + uint32 gpTmr1Ctl; + uint32 gpTmr1Cnt; + uint32 hostMboxIn; + uint32 hostMboxOut; + /* 0x30 */ +#define PMC_CTRL_GP_FLASH_BOOT_STALL 0x00000080 + uint32 gpOut; + uint32 gpIn; + uint32 gpInIrqMask; + uint32 gpInIrqStatus; + /* 0x40 */ + uint32 dmaCtrl; + uint32 dmaStatus; + uint32 dma0_3FifoStatus; + uint32 unused0[3]; /* 0x4c-0x57 */ + /* 0x58 */ + uint32 l1IrqMips1Mask; + uint32 diagControl; + /* 0x60 */ + uint32 diagHigh; + uint32 diagLow; + uint32 badAddr; + uint32 addr1WndwMask; + /* 0x70 */ + uint32 addr1WndwBaseIn; + uint32 addr1WndwBaseOut; + uint32 addr2WndwMask; + uint32 addr2WndwBaseIn; + /* 0x80 */ + uint32 addr2WndwBaseOut; + uint32 scratch; + uint32 tm; + uint32 softResets; + /* 0x90 */ + uint32 eb2ubusTimeout; + uint32 m4keCoreStatus; + uint32 gpInIrqSense; + uint32 ubSlaveTimeout; + /* 0xa0 */ + uint32 diagEn; + uint32 devTimeout; + uint32 ubusErrorOutMask; + uint32 diagCaptStopMask; + /* 0xb0 */ + uint32 revId; + uint32 gpTmr2Ctl; + uint32 gpTmr2Cnt; + uint32 legacyMode; + /* 0xc0 */ + uint32 smisbMonitor; + uint32 diagCtrl; + uint32 diagStat; + uint32 diagMask; + /* 0xd0 */ + uint32 diagRslt; + uint32 diagCmp; + uint32 diagCapt; + uint32 diagCnt; + /* 0xe0 */ + uint32 diagEdgeCnt; + uint32 unused1[4]; /* 0xe4-0xf3 */ + /* 0xf4 */ + uint32 iopPeriphBaseAddr; + uint32 lfsr; + uint32 unused2; /* 0xfc-0xff */ +} PmcCtrlReg; + +typedef struct PmcOutFifoReg { + uint32 msgCtrl; /* 0x00 */ + uint32 msgSts; /* 0x04 */ + uint32 unused[14]; /* 0x08-0x3f */ + uint32 msgData[16]; /* 0x40-0x7c */ +} PmcOutFifoReg; + +typedef struct PmcInFifoReg { + uint32 msgCtrl; /* 0x00 */ + uint32 msgSts; /* 0x04 */ + uint32 unused[13]; /* 0x08-0x3b */ + uint32 msgLast; /* 0x3c */ + uint32 msgData[16]; /* 0x40-0x7c */ +} PmcInFifoReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + /* 0x00 */ + uint32 dcacheHit; + uint32 dcacheMiss; + uint32 icacheHit; + uint32 icacheMiss; + /* 0x10 */ + uint32 instnComplete; + uint32 wtbMerge; + uint32 wtbNoMerge; + uint32 itlbHit; + /* 0x20 */ + uint32 itlbMiss; + uint32 dtlbHit; + uint32 dtlbMiss; + uint32 jtlbHit; + /* 0x30 */ + uint32 jtlbMiss; + uint32 powerSubZone; + uint32 powerMemPda; + uint32 freqScalarCtrl; + /* 0x40 */ + uint32 freqScalarMask; +} PmcPerfPowReg; + +typedef struct PmcDQMReg { + /* 0x00 */ + uint32 cfg; + uint32 _4keLowWtmkIrqMask; + uint32 mipsLowWtmkIrqMask; + uint32 lowWtmkIrqMask; + /* 0x10 */ + uint32 _4keNotEmptyIrqMask; + uint32 mipsNotEmptyIrqMask; + uint32 notEmptyIrqSts; + uint32 queueRst; + /* 0x20 */ + uint32 notEmptySts; + uint32 nextAvailMask; + uint32 nextAvailQueue; + uint32 mips1LowWtmkIrqMask; + /* 0x30 */ + uint32 mips1NotEmptyIrqMask; + uint32 autoSrcPidInsert; +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct Pmc { + uint32 baseReserved; /* 0x0000 */ + uint32 unused0[1023]; + PmcCtrlReg ctrl; /* 0x1000 */ + + PmcOutFifoReg outFifo; /* 0x1100 */ + uint32 unused1[32]; /* 0x1180-0x11ff */ + PmcInFifoReg inFifo; /* 0x1200 */ + uint32 unused2[32]; /* 0x1280-0x12ff */ + + PmcDmaReg dma[2]; /* 0x1300 */ + uint32 unused3[48]; /* 0x1340-0x13ff */ + + PmcTokenReg token; /* 0x1400 */ + uint32 unused4[121]; /* 0x141c-0x15ff */ + + PmcPerfPowReg perfPower; /* 0x1600 */ + uint32 unused5[47]; /* 0x1644-0x16ff */ + + uint32 msgId[32]; /* 0x1700 */ + uint32 unused6[32]; /* 0x1780-0x17ff */ + + PmcDQMReg dqm; /* 0x1800 */ + uint32 unused7[50]; /* 0x1838-0x18ff */ + + PmcCntReg hwCounter; /* 0x1900 */ + uint32 unused8[46]; /* 0x1948-0x19ff */ + + PmcDqmQCtrlReg dqmQCtrl[32]; /* 0x1a00 */ + PmcDqmQDataReg dqmQData[32]; /* 0x1c00 */ + uint32 unused9[64]; /* 0x1e00-0x1eff */ + + uint32 qStatus[32]; /* 0x1f00 */ + uint32 unused10[32]; /* 0x1f80-0x1fff */ + + PmcDqmQMibReg qMib; /* 0x2000 */ + uint32 unused11[1952]; /* 0x2180-0x3ffff */ + + uint32 sharedMem[8192]; /* 0x4000-0xbffc */ +} Pmc; + +#define PMC ((volatile Pmc * const) PMC_BASE) + + + +/* + * Process Monitor Module + */ +typedef struct PMRingOscillatorControl { + uint32 control; + uint32 en_lo; + uint32 en_mid; + uint32 en_hi; + uint32 idle_lo; + uint32 idle_mid; + uint32 idle_hi; +} PMRingOscillatorControl; + +#define RCAL_0P25UM_HORZ 0 +#define RCAL_0P25UM_VERT 1 +#define RCAL_0P5UM_HORZ 2 +#define RCAL_0P5UM_VERT 3 +#define RCAL_1UM_HORZ 4 +#define RCAL_1UM_VERT 5 +#define PMMISC_RMON_EXT_REG ((RCAL_1UM_VERT + 1)/2) +#define PMMISC_RMON_VALID_MASK (0x1<<16) +typedef struct PMMiscControl { + uint32 gp_out; + uint32 clock_select; + uint32 unused[2]; + uint32 misc[4]; +} PMMiscControl; + +typedef struct PMSSBMasterControl { + uint32 control; +#define PMC_SSBM_CONTROL_SSB_START (1<<15) +#define PMC_SSBM_CONTROL_SSB_ADPRE (1<<13) +#define PMC_SSBM_CONTROL_SSB_EN (1<<12) +#define PMC_SSBM_CONTROL_SSB_CMD_SHIFT (10) +#define PMC_SSBM_CONTROL_SSB_CMD_MASK (0x3 << PMC_SSBM_CONTROL_SSB_CMD_SHIFT) +#define PMC_SSBM_CONTROL_SSB_CMD_READ (2) +#define PMC_SSBM_CONTROL_SSB_CMD_WRITE (1) +#define PMC_SSBM_CONTROL_SSB_ADDR_SHIFT (0) +#define PMC_SSBM_CONTROL_SSB_ADDR_MASK (0x3ff << PMC_SSBM_CONTROL_SSB_ADDR_SHIFT) + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct PMEctrControl { + uint32 control; + uint32 interval; + uint32 thresh_lo; + uint32 thresh_hi; + uint32 count; +} PMEctrControl; + +typedef struct PMBMaster { + uint32 ctrl; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_Read (0 << 20) +#define PMC_PMBM_Write (1 << 20) + uint32 wr_data; + uint32 timeout; + uint32 rd_data; + uint32 unused[4]; +} PMBMaster; + +typedef struct PMAPVTMONControl { + uint32 control; + uint32 reserved; + uint32 cfg_lo; + uint32 cfg_hi; + uint32 data; + uint32 vref_data; + uint32 unused[2]; + uint32 ascan_cfg; + uint32 warn_temp; + uint32 reset_temp; + uint32 temp_value; + uint32 data1_value; + uint32 data2_value; + uint32 data3_value; +} PMAPVTMONControl; + +typedef struct PMUBUSCfg { + uint32 window[8]; + uint32 control; +} PMUBUSCfg; + +typedef struct ProcessMonitorRegs { + uint32 MonitorCtrl; /* 0x00 */ + uint32 unused0[7]; + PMRingOscillatorControl ROSC; /* 0x20 */ + uint32 unused1; + PMMiscControl Misc; /* 0x40 */ + PMSSBMasterControl SSBMaster; /* 0x60 */ + uint32 unused2[5]; + PMEctrControl Ectr; /* 0x80 */ + uint32 unused3[11]; + PMBMaster PMBM[2]; /* 0xc0 */ + PMAPVTMONControl APvtmonCtrl; /* 0x100 */ + uint32 unused4[9]; + PMUBUSCfg UBUSCfg; /* 0x160 */ +} ProcessMonitorRegs; + +#define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE) + + +/* + * Timer + */ +typedef struct Timer { + uint32 TimerCtl0; /* 0x00 */ + uint32 TimerCtl1; /* 0x04 */ + uint32 TimerCtl2; /* 0x08 */ + uint32 TimerCtl3; /* 0x0c */ +#define TIMERENABLE (1 << 31) +#define RSTCNTCLR (1 << 30) + + uint32 TimerCnt0; /* 0x10 */ + uint32 TimerCnt1; /* 0x14 */ + uint32 TimerCnt2; /* 0x18 */ + uint32 TimerCnt3; /* 0x1c */ +#define TIMER_COUNT_MASK 0x3FFFFFFF + + uint32 TimerMask; /* 0x20 */ +#define TIMER0EN (1 << 0) +#define TIMER1EN (1 << 1) +#define TIMER2EN (1 << 2) +#define TIMER3EN (1 << 3) + + uint32 TimerInts; /* 0x24 */ +#define TIMER0 (1 << 0) +#define TIMER1 (1 << 1) +#define TIMER2 (1 << 2) +#define TIMER3 (1 << 3) +#define WATCHDOG (1 << 4) + + uint32 WatchDogDefCount; /* 0x28 */ + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; /* 0x2c */ + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; /* 0x30 */ + uint32 SoftRst; /* 0x34 */ +#define SOFT_RESET (1 << 0) + uint32 ResetStatus; /* 0x38 */ +#define PCIE_RESET_STATUS 0x10000000 +#define SW_RESET_STATUS 0x20000000 +#define HW_RESET_STATUS 0x40000000 +#define POR_RESET_STATUS 0x80000000 +#define RESET_STATUS_MASK 0xF0000000 +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/plat/bcm/include/bcm963xx/63146_map_part.h b/plat/bcm/include/bcm963xx/63146_map_part.h new file mode 100755 index 00000000..a7e52c43 --- /dev/null +++ b/plat/bcm/include/bcm963xx/63146_map_part.h @@ -0,0 +1,530 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef __BCM63146_MAP_PART_H +#define __BCM63146_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + + +#define MEMC_PHYS_BASE 0x80040000 /* MC2 TOP */ +#define MEMC_SIZE 0x00040000 + +#define PMC_PHYS_BASE 0xffa00000 +#define PMC_SIZE 0x00200000 +#define PMC_OFFSET 0x00100000 +#define PROC_MON_OFFSET 0x00100000 +#define PMB_OFFSET 0x00120100 + +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x3000 +#define TIMR_OFFSET 0x0400 /* 64 bit timer registers */ +#define WDTIMR0_OFFSET 0x0480 +#define WDTIMR1_OFFSET 0x04c0 + +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + +#define PMC_BASE (PMC_PHYS_BASE + PMC_OFFSET) +#define PROC_MON_BASE (PMC_PHYS_BASE + PROC_MON_OFFSET) +#define PMB_BASE (PMC_PHYS_BASE + PMB_OFFSET) +#define TIMR_BASE (PERF_PHYS_BASE + TIMR_OFFSET +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) + +#ifndef __ASSEMBLER__ + +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + uint32 gpTmr0Ctl; /* 0x018 */ + uint32 gpTmr0Cnt; /* 0x01c */ + uint32 gpTmr1Ctl; /* 0x020 */ + uint32 gpTmr1Cnt; /* 0x024 */ + uint32 hostMboxIn; /* 0x028 */ + uint32 hostMboxOut; /* 0x02c */ + uint32 reserved[4]; /* 0x030 */ + uint32 dmaCtrl; /* 0x040 */ + uint32 dmaStatus; /* 0x044 */ + uint32 dma0_3FifoStatus; /* 0x048 */ + uint32 reserved1[4]; /* 0x04c */ + uint32 diagControl; /* 0x05c */ + uint32 diagHigh; /* 0x060 */ + uint32 diagLow; /* 0x064 */ + uint32 reserved8; /* 0x068 */ + uint32 addr1WndwMask; /* 0x06c */ + uint32 addr1WndwBaseIn; /* 0x070 */ + uint32 addr1WndwBaseOut; /* 0x074 */ + uint32 addr2WndwMask; /* 0x078 */ + uint32 addr2WndwBaseIn; /* 0x07c */ + uint32 addr2WndwBaseOut; /* 0x080 */ + uint32 scratch; /* 0x084 */ + uint32 reserved9; /* 0x088 */ + uint32 softResets; /* 0x08c */ + uint32 reserved2; /* 0x090 */ + uint32 m4keCoreStatus; /* 0x094 */ + uint32 reserved3; /* 0x098 */ + uint32 ubSlaveTimeout; /* 0x09c */ + uint32 diagEn; /* 0x0a0 */ + uint32 devTimeout; /* 0x0a4 */ + uint32 ubusErrorOutMask; /* 0x0a8 */ + uint32 diagCaptStopMask; /* 0x0ac */ + uint32 revId; /* 0x0b0 */ + uint32 reserved4[4]; /* 0x0b4 */ + uint32 diagCtrl; /* 0x0c4 */ + uint32 diagStat; /* 0x0c8 */ + uint32 diagMask; /* 0x0cc */ + uint32 diagRslt; /* 0x0d0 */ + uint32 diagCmp; /* 0x0d4 */ + uint32 diagCapt; /* 0x0d8 */ + uint32 diagCnt; /* 0x0dc */ + uint32 diagEdgeCnt; /* 0x0e0 */ + uint32 reserved5[4]; /* 0x0e4 */ + uint32 smisc_bus_config; /* 0x0f4 */ + uint32 lfsr; /* 0x0f8 */ + uint32 dqm_pac_lock; /* 0x0fc */ + uint32 l1_irq_4ke_mask; /* 0x100 */ + uint32 l1_irq_4ke_status; /* 0x104 */ + uint32 l1_irq_mips_mask; /* 0x108 */ + uint32 l1_irq_mips_status; /* 0x10c */ + uint32 l1_irq_mips1_mask; /* 0x110 */ + uint32 reserved6[3]; /* 0x114 */ + uint32 l2_irq_gp_mask; /* 0x120 */ + uint32 l2_irq_gp_status; /* 0x124 */ + uint32 l2_irq_gp_set; /* 0x128 */ + uint32 reserved7; /* 0x12c */ + uint32 gp_in_irq_mask; /* 0x130 */ + uint32 gp_in_irq_status; /* 0x134 */ + uint32 gp_in_irq_set; /* 0x138 */ + uint32 gp_in_irq_sense; /* 0x13c */ + uint32 gp_in; /* 0x140 */ + uint32 gp_out; /* 0x144 */ +} PmcCtrlReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + uint32 freqScalarCtrl; /* 0x3c */ + uint32 freqScalarMask; /* 0x40 */ +} PmcPerfPowReg; + +typedef struct PmcDQMPac { + uint32 dqmPac[32]; +} PmcDQMPac; + +typedef struct PmcDQMReg { + uint32 cfg; /* 0x1c00 */ + uint32 _4keLowWtmkIrqMask; /* 0x1c04 */ + uint32 mipsLowWtmkIrqMask; /* 0x1c08 */ + uint32 lowWtmkIrqMask; /* 0x1c0c */ + uint32 _4keNotEmptyIrqMask; /* 0x1c10 */ + uint32 mipsNotEmptyIrqMask; /* 0x1c14 */ + uint32 notEmptyIrqSts; /* 0x1c18 */ + uint32 queueRst; /* 0x1c1c */ + uint32 notEmptySts; /* 0x1c20 */ + uint32 nextAvailMask; /* 0x1c24 */ + uint32 nextAvailQueue; /* 0x1c28 */ + uint32 mips1LowWtmkIrqMask; /* 0x1c2c */ + uint32 mips1NotEmptyIrqMask; /* 0x1c30 */ + uint32 autoSrcPidInsert; /* 0x1c34 */ + uint32 timerIrqStatus; /* 0x1c38 */ + uint32 timerStatus; /* 0x1c3c */ + uint32 _4keTimerIrqMask; /* 0x1c40 */ + uint32 mipsTimerIrqMask; /* 0x1c44 */ + uint32 mips1TimerIrqMask; /* 0x1c48 */ +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct SSBMaster { + uint32 ssbmControl; /* 0x0060 */ + uint32 ssbmWrData; /* 0x0064 */ + uint32 ssbmRdData; /* 0x0068 */ + uint32 ssbmStatus; /* 0x006c */ +} SSBMaster; + +typedef struct PmmReg { + uint32 memPowerCtrl; /* 0x0000 */ + uint32 regSecurityConfig; /* 0x0004 */ +} PmmReg; + +typedef struct keyholeReg { + uint32 ctrlSts; + uint32 wrData; + uint32 mutex; + uint32 rdData; +} keyholeReg; + +typedef struct PmbBus { + uint32 config; /* 0x0100 */ + uint32 arbiter; /* 0x0104 */ + uint32 timeout; /* 0x0108 */ + uint32 unused1; /* 0x010c */ + keyholeReg keyhole[4]; /* 0x0110-0x014f */ + uint32 unused2[44]; /* 0x0150-0x01ff */ + uint32 map[64]; /* 0x0200-0x02ff */ +}PmbBus; + +typedef struct CoreCtrl { + uint32 coreEnable; /* 0x0400 */ + uint32 autoresetControl; /* 0x0404 */ + uint32 coreIdle; /* 0x0408 */ + uint32 coreResetCause; /* 0x040c */ + uint32 memPwrDownCtrl0; /* 0x0410 */ + uint32 memPwrDownSts0; /* 0x0414 */ + uint32 memPwrDownCtrl1; /* 0x0418 */ + uint32 memPwrDownSts1; /* 0x041c */ + uint32 sysFlg0Status; /* 0x0420 */ + uint32 sysFlg0Set; /* 0x0424 */ + uint32 sysFlg0Clear; /* 0x0428 */ + uint32 unused1; /* 0x042c */ + uint32 usrFlg0Status; /* 0x0430 */ + uint32 usrFlg0Set; /* 0x0434 */ + uint32 usrFlg0Clear; /* 0x0438 */ + uint32 unused2; /* 0x043c */ + uint32 subsystemRev; /* 0x0440 */ + uint32 resetVector; /* 0x0444 */ +} CoreCtrl; + +typedef struct CoreState { + uint32 sysMbx[8]; /* 0x0480 */ + uint32 usrMbx[8]; /* 0x04a0 */ + uint32 sysMtx[4]; /* 0x04c0 */ + uint32 usrMtx[8]; /* 0x04d0 */ +} CoreState; + +typedef struct CoreIntr { + uint32 irqStatus; /* 0x0500 */ + uint32 irqSet; /* 0x0504 */ + uint32 irqClear; /* 0x0508 */ + uint32 unused1; /* 0x050c */ + uint32 srqStatus; /* 0x0510 */ + uint32 srqSet; /* 0x0514 */ + uint32 srqClear; /* 0x0518 */ + uint32 unused2; /* 0x051c */ + uint32 drqStatus; /* 0x0520 */ + uint32 drqSet; /* 0x0524 */ + uint32 drqClear; /* 0x0528 */ + uint32 unused3; /* 0x052c */ + uint32 frqStatus; /* 0x0530 */ + uint32 frqSet; /* 0x0534 */ + uint32 frqClear; /* 0x0538 */ + uint32 unused4; /* 0x053c */ + uint32 hostIrqLatched; /* 0x0540 */ + uint32 hostIrqSet; /* 0x0544 */ + uint32 hostIrqClear; /* 0x0548 */ + uint32 hostIrqEnable; /* 0x054c */ + uint32 obusFaultStatus; /* 0x0550 */ + uint32 obusFaultClear; /* 0x0554 */ + uint32 obusFaultAddr; /* 0x0558 */ +} CoreIntr; + +typedef struct CoreProfile { + uint32 mutex; /* 0x0580 */ + uint32 lastConfPcLo; /* 0x0584 */ + uint32 lastConfPcHi; /* 0x0588 */ + uint32 lastPcLo; /* 0x058c */ + uint32 lastPcHi; /* 0x0590 */ + uint32 braTargetPc0Lo; /* 0x0594 */ + uint32 braTargetPc0Hi; /* 0x0598 */ + uint32 braTargetPc1Lo; /* 0x059c */ + uint32 braTargetPc1Hi; /* 0x05a0 */ + uint32 braTargetPc2Lo; /* 0x05a4 */ + uint32 braTargetPc2Hi; /* 0x05a8 */ + uint32 braTargetPc3Lo; /* 0x05ac */ + uint32 braTargetPc3Hi; /* 0x05b0 */ + uint32 unused[3]; /* 0x05b4-0x05bf */ + uint32 profSampleW[4]; /* 0x05c0 */ +} CoreProfile; + +typedef struct MaestroMisc { + CoreCtrl coreCtrl; /* 0x0400 */ + uint32 unused1[14]; /* 0x0448-0x047f */ + CoreState coreState; /* 0x0480 */ + uint32 unused2[4]; /* 0x04f0-0x04ff */ + CoreIntr interrupt; /* 0x0500 */ + uint32 unused3[9]; /* 0x055c-0x057f */ + CoreProfile profile; /* 0x0580 */ +} MaestroMisc; + +typedef struct Pmc { + uint32 unused0[1030]; + PmcCtrlReg ctrl; /* 0x1018 */ + uint32 unused1[622]; /* 0x1148-0x1cff */ + PmcDQMPac dqmPac; /* 0x1b00 */ + uint32 unused5[32]; /* 0x1b80-0x1bff */ + PmcDQMReg dqm; /* 0x1c00 */ + uint32 unused6[749]; /* 0x1c4c-0x27ff */ + uint32 qStatus[32]; /* 0x2800 */ + uint32 unused7[480]; /* 0x2880-0x2fff */ + PmcDqmQMibReg qMib; /* 0x3000 */ + uint32 unused8[928]; /* 0x3180-0x3fff */ + PmcDqmQCtrlReg dqmQCtrl[8]; /* 0x4000 */ + uint32 unused9[992]; /* 0x4080-0x4fff */ + PmcDqmQDataReg dqmQData[8]; /* 0x5000 */ +} Pmc; +#define PMC ((volatile Pmc * const) PMC_BASE) + +typedef struct Procmon { + uint32 unused00[256]; + MaestroMisc maestroReg; /* 0x00400 */ + uint32 unused10[32396]; /* 0x005d0-0x1ffff */ + PmmReg pmm; /* 0x20000 */ + uint32 unused11[22]; /* 0x20008-0x2005f */ + SSBMaster ssbMasterCtrl; /* 0x20060 */ + uint32 unused12[36]; /* 0x20070-0x200ff */ + PmbBus pmb; /* 0x20100 */ + uint32 unused13[32576]; /* 0x20300-0x3ffff */ + uint32 qsm[128]; /* 0x40000-0x401ff */ + uint32 unused14[65408]; /* 0x40200-0x7ffff */ + uint32 dtcm[1024]; /* 0x80000-0x80fff */ + uint32 unused15[64512]; /* 0x81000-0xbffff */ + uint32 itcm[4096]; /* 0xc0000-0xc3fff */ +} Procmon; +#define PROCMON ((volatile Procmon * const) PROC_MON_BASE) + +typedef struct PMSSBMasterControl { + uint32 control; + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct +{ + uint32 control; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_BUS_SHIFT (20) +#define PMC_PMBM_Read (0 << 24) +#define PMC_PMBM_Write (1 << 24) + uint32 wr_data; + uint32 mutex; + uint32 rd_data; +} PMB_keyhole_reg; + +typedef struct PMBMaster { + uint32 config; +#define PMB_NUM_REGS_SHIFT (20) +#define PMB_NUM_REGS_MASK (0x3ff) + uint32 arbitger; + uint32 timeout; + uint32 reserved; + PMB_keyhole_reg keyhole[4]; + uint32 reserved1[44]; + uint32 map[64]; +} PMBMaster; +#define PMB ((volatile PMBMaster * const) PMB_BASE) + + +/* + * Timer + */ +#define TIMER_64BIT +typedef struct Timer { + uint64 TimerCtl0; /* 0x00 */ + uint64 TimerCtl1; /* 0x08 */ + uint64 TimerCtl2; /* 0x10 */ + uint64 TimerCtl3; /* 0x18 */ +#define TIMERENABLE (1ULL << 63) +#define RSTCNTCLR (1ULL << 62) + uint64 TimerCnt0; /* 0x20 */ + uint64 TimerCnt1; /* 0x28 */ + uint64 TimerCnt2; /* 0x30 */ + uint64 TimerCnt3; /* 0x38 */ +#define TIMER_COUNT_MASK 0x3FFFFFFFFFFFFFFFULL + uint32 TimerMask; /* 0x40 */ +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 +#define TIMER3EN 0x08 + uint32 TimerInts; /* 0x44 */ +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define TIMER3 0x08 + uint32 ResetReason;/* 0x4c */ + uint32 spare[3]; /* 0x50 - 0x5b */ + uint32 reserved1[9]; /* 0x5c - 0x7f */ +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + + +typedef struct WDTimer { + uint32 WatchDogDefCount; + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 SoftRst; +#define SOFT_RESET 0x00000001 + uint32 WDAccessCtl; +} WDTimer; + +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + +typedef struct BIUCFG_Access { + uint32 permission; /* 0x0 */ + uint32 sbox; /* 0x4 */ + uint32 cpu_defeature; /* 0x8 */ + uint32 dbg_security; /* 0xc */ + uint32 rsvd1[32]; /* 0x10 - 0x8f */ + uint64 violation[2]; /* 0x90 - 0x9f */ + uint32 ts_access[2]; /* 0xa0 - 0xa7 */ + uint32 rsvd2[22]; /* 0xa8 - 0xff */ +}BIUCFG_Access; + +typedef struct BIUCFG_Cluster { + uint32 permission; /* 0x0 */ + uint32 config; /* 0x4 */ + uint32 status; /* 0x8 */ + uint32 control; /* 0xc */ + uint32 cpucfg; /* 0x10 */ + uint32 dbgrom; /* 0x14 */ + uint32 rsvd1[2]; /* 0x18 - 0x1f */ + uint64 rvbar_addr[4]; /* 0x20 - 0x3f */ + uint32 rsvd2[48]; /* 0x40 - 0xff */ +}BIUCFG_Cluster; + +typedef struct BIUCFG_Bac { + uint32 bac_permission; /* 0x00 */ + uint32 bac_periphbase; /* 0x04 */ + uint32 rsvd[2]; /* 0x08 - 0x0f */ + uint32 bac_event; /* 0x10 */ + uint32 rsvd_1[3]; /* 0x14 - 0x1f */ + uint32 bac_ccicfg; /* 0x20 */ + uint32 bac_cciaddr; /* 0x24 */ + uint32 rsvd_2[4]; /* 0x28 - 0x37 */ + uint32 bac_ccievs2; /* 0x38 */ + uint32 bac_ccievs3; /* 0x3c */ + uint32 bac_ccievs4; /* 0x40 */ + uint32 rsvd_3[3]; /* 0x44 - 0x4f */ + uint32 bac_ccievm0; /* 0x50 */ + uint32 bac_ccievm1; /* 0x54 */ + uint32 rsvd_4[2]; /* 0x58 - 0x5f */ + uint32 bac_dapapbcfg; /* 0x60 */ + uint32 bac_status; /* 0x64 */ + uint32 rsvd_5[2]; /* 0x68 - 0x6f */ + uint32 cpu_therm_irq_cfg; /* 0x70 */ + uint32 cpu_therm_threshold_cfg; /* 0x74 */ + uint32 rsvd_6; /* 0x78 */ + uint32 cpu_therm_temp; /* 0x7c */ + uint32 rsvd_7[32]; /* 0x80 - 0xff */ +} BIUCFG_Bac; + +typedef struct BIUCFG_Aux { + uint32 aux_permission; /* 0x00 */ + uint32 rsvd[3]; /* 0x04 - 0x0f */ + uint32 c0_clk_control; /* 0x10 */ + uint32 c0_clk_ramp; /* 0x14 */ + uint32 c0_clk_pattern; /* 0x18 */ + uint32 rsvd_1; /* 0x1c */ + uint32 c1_clk_control; /* 0x20 */ + uint32 c1_clk_ramp; /* 0x24 */ + uint32 c1_clk_pattern; /* 0x28 */ + uint32 rsvd_2[53]; /* 0x2c - 0xff */ +} BIUCFG_Aux; + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff*/ + BIUCFG_Cluster cluster[2]; /* 0x100 - 0x2ff*/ + BIUCFG_Bac bac; /* 0x300 - 0x3ff */ + uint32 anonymous[192]; /* 0x400 - 0x6ff */ + BIUCFG_Aux aux; /* 0x700 - 0x7ff */ + uint32 anonymous_1[2560]; /* 0x800 - 0x2fff */ +}BIUCFG; + +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/plat/bcm/include/bcm963xx/63148_map_part.h b/plat/bcm/include/bcm963xx/63148_map_part.h new file mode 100644 index 00000000..6f23e24c --- /dev/null +++ b/plat/bcm/include/bcm963xx/63148_map_part.h @@ -0,0 +1,571 @@ +/* +<:copyright-BRCM:2013:DUAL/GPL:standard + + Copyright (c) 2013 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef __BCM63148_MAP_PART_H +#define __BCM63148_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define PER_BASE 0xfffe0000 +#define REG_BASE 0x80000000 + +#define MEMC_PHYS_BASE (REG_BASE + 0x00002000) /* DDR IO Buf Control */ +#define MEMC_SIZE 0x20000 + +#define PMC_PHYS_BASE (REG_BASE + 0x00400000) +#define PROC_MON_PHYS_BASE (REG_BASE + 0x00480000) +#define GICD_PHYS_BASE (REG_BASE + 0x00031000) +#define GICC_PHYS_BASE (REG_BASE + 0x00032000) + +#define B15_CTRL_PHYS_BASE (REG_BASE + 0x00020000) +#define B15_PHYS_BASE (REG_BASE + 0x00030000) + + +#define PERF_PHYS_BASE (PER_BASE + 0x00008000) /* chip control */ +#define TIMR_PHYS_BASE (PER_BASE + 0x00008080) /* timer registers */ +#define BOOTLUT_PHYS_BASE (PER_BASE + 0x00010000) + +#define PMC_BASE PMC_PHYS_BASE +#define PROC_MON_BASE PROC_MON_PHYS_BASE +#define TIMR_BASE TIMR_PHYS_BASE +#define BOOTLUT_BASE BOOTLUT_PHYS_BASE +#define B15_CTRL_BASE B15_CTRL_PHYS_BASE +#define B15_BASE B15_PHYS_BASE +#define GICC_BASE GICC_PHYS_BASE +#define GICD_BASE GICD_PHYS_BASE + +#ifndef __ASSEMBLER__ +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + /* 0x00 */ + uint32 l1Irq4keMask; + uint32 l1Irq4keStatus; + uint32 l1IrqMipsMask; + uint32 l1IrqMipsStatus; + /* 0x10 */ + uint32 l2IrqGpMask; + uint32 l2IrqGpStatus; + uint32 gpTmr0Ctl; + uint32 gpTmr0Cnt; + /* 0x20 */ + uint32 gpTmr1Ctl; + uint32 gpTmr1Cnt; + uint32 hostMboxIn; + uint32 hostMboxOut; + /* 0x30 */ +#define PMC_CTRL_GP_FLASH_BOOT_STALL 0x00000080 + uint32 gpOut; + uint32 gpIn; + uint32 gpInIrqMask; + uint32 gpInIrqStatus; + /* 0x40 */ + uint32 dmaCtrl; + uint32 dmaStatus; + uint32 dma0_3FifoStatus; + uint32 unused0[3]; /* 0x4c-0x57 */ + /* 0x58 */ + uint32 l1IrqMips1Mask; + uint32 diagControl; + /* 0x60 */ + uint32 diagHigh; + uint32 diagLow; + uint32 badAddr; + uint32 addr1WndwMask; + /* 0x70 */ + uint32 addr1WndwBaseIn; + uint32 addr1WndwBaseOut; + uint32 addr2WndwMask; + uint32 addr2WndwBaseIn; + /* 0x80 */ + uint32 addr2WndwBaseOut; + uint32 scratch; + uint32 tm; + uint32 softResets; + /* 0x90 */ + uint32 eb2ubusTimeout; + uint32 m4keCoreStatus; + uint32 gpInIrqSense; + uint32 ubSlaveTimeout; + /* 0xa0 */ + uint32 diagEn; + uint32 devTimeout; + uint32 ubusErrorOutMask; + uint32 diagCaptStopMask; + /* 0xb0 */ + uint32 revId; + uint32 gpTmr2Ctl; + uint32 gpTmr2Cnt; + uint32 legacyMode; + /* 0xc0 */ + uint32 smisbMonitor; + uint32 diagCtrl; + uint32 diagStat; + uint32 diagMask; + /* 0xd0 */ + uint32 diagRslt; + uint32 diagCmp; + uint32 diagCapt; + uint32 diagCnt; + /* 0xe0 */ + uint32 diagEdgeCnt; + uint32 unused1[4]; /* 0xe4-0xf3 */ + /* 0xf4 */ + uint32 iopPeriphBaseAddr; + uint32 lfsr; + uint32 unused2; /* 0xfc-0xff */ +} PmcCtrlReg; + +typedef struct PmcOutFifoReg { + uint32 msgCtrl; /* 0x00 */ + uint32 msgSts; /* 0x04 */ + uint32 unused[14]; /* 0x08-0x3f */ + uint32 msgData[16]; /* 0x40-0x7c */ +} PmcOutFifoReg; + +typedef struct PmcInFifoReg { + uint32 msgCtrl; /* 0x00 */ + uint32 msgSts; /* 0x04 */ + uint32 unused[13]; /* 0x08-0x3b */ + uint32 msgLast; /* 0x3c */ + uint32 msgData[16]; /* 0x40-0x7c */ +} PmcInFifoReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + /* 0x00 */ + uint32 dcacheHit; + uint32 dcacheMiss; + uint32 icacheHit; + uint32 icacheMiss; + /* 0x10 */ + uint32 instnComplete; + uint32 wtbMerge; + uint32 wtbNoMerge; + uint32 itlbHit; + /* 0x20 */ + uint32 itlbMiss; + uint32 dtlbHit; + uint32 dtlbMiss; + uint32 jtlbHit; + /* 0x30 */ + uint32 jtlbMiss; + uint32 powerSubZone; + uint32 powerMemPda; + uint32 freqScalarCtrl; + /* 0x40 */ + uint32 freqScalarMask; +} PmcPerfPowReg; + +typedef struct PmcDQMReg { + /* 0x00 */ + uint32 cfg; + uint32 _4keLowWtmkIrqMask; + uint32 mipsLowWtmkIrqMask; + uint32 lowWtmkIrqMask; + /* 0x10 */ + uint32 _4keNotEmptyIrqMask; + uint32 mipsNotEmptyIrqMask; + uint32 notEmptyIrqSts; + uint32 queueRst; + /* 0x20 */ + uint32 notEmptySts; + uint32 nextAvailMask; + uint32 nextAvailQueue; + uint32 mips1LowWtmkIrqMask; + /* 0x30 */ + uint32 mips1NotEmptyIrqMask; + uint32 autoSrcPidInsert; +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct Pmc { + uint32 baseReserved; /* 0x0000 */ + uint32 unused0[1023]; + PmcCtrlReg ctrl; /* 0x1000 */ + + PmcOutFifoReg outFifo; /* 0x1100 */ + uint32 unused1[32]; /* 0x1180-0x11ff */ + PmcInFifoReg inFifo; /* 0x1200 */ + uint32 unused2[32]; /* 0x1280-0x12ff */ + + PmcDmaReg dma[2]; /* 0x1300 */ + uint32 unused3[48]; /* 0x1340-0x13ff */ + + PmcTokenReg token; /* 0x1400 */ + uint32 unused4[121]; /* 0x141c-0x15ff */ + + PmcPerfPowReg perfPower; /* 0x1600 */ + uint32 unused5[47]; /* 0x1644-0x16ff */ + + uint32 msgId[32]; /* 0x1700 */ + uint32 unused6[32]; /* 0x1780-0x17ff */ + + PmcDQMReg dqm; /* 0x1800 */ + uint32 unused7[50]; /* 0x1838-0x18ff */ + + PmcCntReg hwCounter; /* 0x1900 */ + uint32 unused8[46]; /* 0x1948-0x19ff */ + + PmcDqmQCtrlReg dqmQCtrl[32]; /* 0x1a00 */ + PmcDqmQDataReg dqmQData[32]; /* 0x1c00 */ + uint32 unused9[64]; /* 0x1e00-0x1eff */ + + uint32 qStatus[32]; /* 0x1f00 */ + uint32 unused10[32]; /* 0x1f80-0x1fff */ + + PmcDqmQMibReg qMib; /* 0x2000 */ + uint32 unused11[1952]; /* 0x2180-0x3ffff */ + + uint32 sharedMem[8192]; /* 0x4000-0xbffc */ +} Pmc; + +#define PMC ((volatile Pmc * const) PMC_BASE) + +/* + * Process Monitor Module + */ +typedef struct PMRingOscillatorControl { + uint32 control; + uint32 en_lo; + uint32 en_mid; + uint32 en_hi; + uint32 idle_lo; + uint32 idle_mid; + uint32 idle_hi; +} PMRingOscillatorControl; + +#define RCAL_0P25UM_HORZ 0 +#define RCAL_0P25UM_VERT 1 +#define RCAL_0P5UM_HORZ 2 +#define RCAL_0P5UM_VERT 3 +#define RCAL_1UM_HORZ 4 +#define RCAL_1UM_VERT 5 +#define PMMISC_RMON_EXT_REG ((RCAL_1UM_VERT + 1)/2) +#define PMMISC_RMON_VALID_MASK (0x1<<16) +typedef struct PMMiscControl { + uint32 gp_out; + uint32 clock_select; + uint32 unused[2]; + uint32 misc[4]; +} PMMiscControl; + +typedef struct PMSSBMasterControl { + uint32 control; +#define PMC_SSBM_CONTROL_SSB_START (1<<15) +#define PMC_SSBM_CONTROL_SSB_ADPRE (1<<13) +#define PMC_SSBM_CONTROL_SSB_EN (1<<12) +#define PMC_SSBM_CONTROL_SSB_CMD_SHIFT (10) +#define PMC_SSBM_CONTROL_SSB_CMD_MASK (0x3 << PMC_SSBM_CONTROL_SSB_CMD_SHIFT) +#define PMC_SSBM_CONTROL_SSB_CMD_READ (2) +#define PMC_SSBM_CONTROL_SSB_CMD_WRITE (1) +#define PMC_SSBM_CONTROL_SSB_ADDR_SHIFT (0) +#define PMC_SSBM_CONTROL_SSB_ADDR_MASK (0x3ff << PMC_SSBM_CONTROL_SSB_ADDR_SHIFT) + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct PMEctrControl { + uint32 control; + uint32 interval; + uint32 thresh_lo; + uint32 thresh_hi; + uint32 count; +} PMEctrControl; + +typedef struct PMBMaster { + uint32 ctrl; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_Read (0 << 20) +#define PMC_PMBM_Write (1 << 20) + uint32 wr_data; + uint32 timeout; + uint32 rd_data; + uint32 unused[4]; +} PMBMaster; + +typedef struct PMAPVTMONControl { + uint32 control; + uint32 reserved; + uint32 cfg_lo; + uint32 cfg_hi; + uint32 data; + uint32 vref_data; + uint32 unused[2]; + uint32 ascan_cfg; + uint32 warn_temp; + uint32 reset_temp; + uint32 temp_value; + uint32 data1_value; + uint32 data2_value; + uint32 data3_value; +} PMAPVTMONControl; + +typedef struct PMUBUSCfg { + uint32 window[8]; + uint32 control; +} PMUBUSCfg; + +typedef struct ProcessMonitorRegs { + uint32 MonitorCtrl; /* 0x00 */ + uint32 unused0[7]; + PMRingOscillatorControl ROSC; /* 0x20 */ + uint32 unused1; + PMMiscControl Misc; /* 0x40 */ + PMSSBMasterControl SSBMaster; /* 0x60 */ + uint32 unused2[5]; + PMEctrControl Ectr; /* 0x80 */ + uint32 unused3[11]; + PMBMaster PMBM[2]; /* 0xc0 */ + PMAPVTMONControl APvtmonCtrl; /* 0x100 */ + uint32 unused4[9]; + PMUBUSCfg UBUSCfg; /* 0x160 */ +} ProcessMonitorRegs; + +#define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE) + + +/* + * Timer + */ +typedef struct Timer { + uint32 TimerCtl0; /* 0x00 */ + uint32 TimerCtl1; /* 0x04 */ + uint32 TimerCtl2; /* 0x08 */ + uint32 TimerCtl3; /* 0x0c */ +#define TIMERENABLE (1 << 31) +#define RSTCNTCLR (1 << 30) + + uint32 TimerCnt0; /* 0x10 */ + uint32 TimerCnt1; /* 0x14 */ + uint32 TimerCnt2; /* 0x18 */ + uint32 TimerCnt3; /* 0x1c */ +#define TIMER_COUNT_MASK 0x3FFFFFFF + + uint32 TimerMask; /* 0x20 */ +#define TIMER0EN (1 << 0) +#define TIMER1EN (1 << 1) +#define TIMER2EN (1 << 2) +#define TIMER3EN (1 << 3) + + uint32 TimerInts; /* 0x24 */ +#define TIMER0 (1 << 0) +#define TIMER1 (1 << 1) +#define TIMER2 (1 << 2) +#define TIMER3 (1 << 3) +#define WATCHDOG (1 << 4) + + uint32 WatchDogDefCount; /* 0x28 */ + + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; /* 0x2c */ + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; /* 0x30 */ + uint32 SoftRst; /* 0x34 */ +#define SOFT_RESET (1 << 0) + uint32 ResetStatus; /* 0x38 */ +#define PCIE_RESET_STATUS 0x10000000 +#define SW_RESET_STATUS 0x20000000 +#define HW_RESET_STATUS 0x40000000 +#define POR_RESET_STATUS 0x80000000 +#define RESET_STATUS_MASK 0xF0000000 +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +/* + * B15 CFG + */ +typedef struct B15ArchRegion { + uint32 addr_ulimit; + uint32 addr_llimit; + uint32 permission; + uint32 access_right_ctrl; +} B15ArchRegion; + +typedef struct B15Arch { + B15ArchRegion region[8]; + uint32 unused[95]; + uint32 scratch; +} B15Arch; + +typedef struct B15CpuBusRange { +#define ULIMIT_SHIFT 4 +#define BUSNUM_MASK 0x0000000FU + +#define BUSNUM_UBUS 1 +#define BUSNUM_RBUS 2 +#define BUSNUM_RSVD 3 +#define BUSNUM_MCP0 4 +#define BUSNUM_MCP1 5 +#define BUSNUM_MCP2 6 + + uint32 ulimit; + uint32 llimit; +} B15CpuBusRange; + +typedef struct B15CpuAccessRightViol { + uint32 addr; + uint32 upper_addr; + uint32 detail_addr; +} B15CpuAccessRightViol; + +typedef struct B15CpuBPCMAVS { + uint32 bpcm_id; + uint32 bpcm_capability; + uint32 bpcm_ctrl; + uint32 bpcm_status; + uint32 avs_rosc_ctrl; + uint32 avs_rosc_threshold; + uint32 avs_rosc_cnt; + uint32 avs_pwd_ctrl; +} B15CpuBPCMAVS; + +typedef struct B15CpuCtrl { + B15CpuBusRange bus_range[11]; /* 0x0 */ + uint32 secure_reset_hndshake; + uint32 secure_soft_reset; + B15CpuAccessRightViol access_right_viol[2]; /* 0x60 */ + uint32 rac_cfg0; + uint32 rac_cfg1; + uint32 rac_flush; /* 0x80 */ + uint32 cpu_power_cfg; + uint32 cpu0_pwr_zone_ctrl; + uint32 cpu1_pwr_zone_ctrl; + uint32 cpu2_pwr_zone_ctrl; /* 0x90 */ + uint32 cpu3_pwr_zone_ctrl; + uint32 l2biu_pwr_zone_ctrl; + uint32 cpu0_pwr_zone_cfg1; + uint32 cpu0_pwr_zone_cfg2; /* 0xa0 */ + uint32 cpu1_pwr_zone_cfg1; + uint32 cpu1_pwr_zone_cfg2; + uint32 cpu2_pwr_zone_cfg1; + uint32 cpu2_pwr_zone_cfg2; /* 0xb0 */ + uint32 cpu3_pwr_zone_cfg1; + uint32 cpu3_pwr_zone_cfg2; + uint32 l2biu_pwr_zone_cfg1; + uint32 l2biu_pwr_zone_cfg2; /* 0xc0 */ + uint32 cpu0_pwr_freq_scalar_ctrl; + uint32 cpu1_pwr_freq_scalar_ctrl; + uint32 cpu2_pwr_freq_scalar_ctrl; + uint32 cpu3_pwr_freq_scalar_ctrl; /* 0xd0 */ + uint32 l2biu_pwr_freq_scalar_ctrl; + B15CpuBPCMAVS cpu_bpcm_avs[4]; /* 0xd8 */ + B15CpuBPCMAVS l2biu_bpcm_avs; /* 0x158 */ + uint32 reset_cfg; /* 0x178 */ + uint32 clock_cfg; + uint32 misc_cfg; /* 0x180 */ + uint32 credit; + uint32 therm_throttle_temp; + uint32 term_throttle_irq_cfg; + uint32 therm_irq_high; /* 0x190 */ + uint32 therm_irq_low; + uint32 therm_misc_threshold; + uint32 therm_irq_misc; + uint32 defeature; /* 0x1a0 */ + uint32 defeature_key; + uint32 debug_rom_addr; + uint32 debug_self_addr; + uint32 debug_tracectrl; /* 0x1b0 */ + uint32 axi_cfg; + uint32 revision; + uint32 ubus_cfg_window[8]; /* 0x1bc */ + uint32 ubus_cfg; /* 0x1dc */ + uint32 unused[135]; + uint32 scratch; /* 0x3fc */ +} B15CpuCtrl; + +typedef struct B15Ctrl { + uint32 unused0[1024]; + B15Arch arch; /* 0x1000 */ + uint32 unused1[896]; + B15CpuCtrl cpu_ctrl; /* 0x2000 */ +} B15Ctrl; + +#define B15CTRL ((volatile B15Ctrl *const) B15_CTRL_BASE) + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/plat/bcm/include/bcm963xx/63158_map_part.h b/plat/bcm/include/bcm963xx/63158_map_part.h new file mode 100644 index 00000000..051021e0 --- /dev/null +++ b/plat/bcm/include/bcm963xx/63158_map_part.h @@ -0,0 +1,554 @@ +/* +<:copyright-BRCM:2016:DUAL/GPL:standard + + Copyright (c) 2016 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef __BCM63158_MAP_PART_H +#define __BCM63158_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define MEMC_PHYS_BASE 0x80180000 /* DDR IO Buf Control */ +#define MEMC_SIZE 0x40000 + +#define PMC_PHYS_BASE 0x80200000 +#define PMC_SIZE 0x81000 +#define PMC_OFFSET 0x0000 +#define PROC_MON_PHYS_BASE 0x80280000 +#define PROC_MON_SIZE 0x1000 +#define PROC_MON_OFFSET 0x0000 + +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x3000 +#define TIMR_OFFSET 0x0400 /* 64 bit timer registers */ +#define WDTIMR0_OFFSET 0x0480 +#define WDTIMR1_OFFSET 0x04c0 + +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + +#define PMC_BASE (PMC_PHYS_BASE + PMC_OFFSET) +#define PROC_MON_BASE (PROC_MON_PHYS_BASE + PROC_MON_OFFSET) + +#define TIMR_BASE (PERF_PHYS_BASE + TIMR_OFFSET) +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) + +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) + +#ifndef __ASSEMBLER__ + +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + /* 0x00 */ + uint32 l1Irq4keMask; + uint32 l1Irq4keStatus; + uint32 l1IrqMipsMask; + uint32 l1IrqMipsStatus; + /* 0x10 */ + uint32 l2IrqGpMask; + uint32 l2IrqGpStatus; + uint32 gpTmr0Ctl; + uint32 gpTmr0Cnt; + /* 0x20 */ + uint32 gpTmr1Ctl; + uint32 gpTmr1Cnt; + uint32 hostMboxIn; + uint32 hostMboxOut; + /* 0x30 */ +#define PMC_CTRL_GP_FLASH_BOOT_STALL 0x00000080 + uint32 gpOut; + uint32 gpIn; + uint32 gpInIrqMask; + uint32 gpInIrqStatus; + /* 0x40 */ + uint32 dmaCtrl; + uint32 dmaStatus; + uint32 dma0_3FifoStatus; + uint32 unused0[3]; /* 0x4c-0x57 */ + /* 0x58 */ + uint32 l1IrqMips1Mask; + uint32 diagControl; + /* 0x60 */ + uint32 diagHigh; + uint32 diagLow; + uint32 badAddr; + uint32 addr1WndwMask; + /* 0x70 */ + uint32 addr1WndwBaseIn; + uint32 addr1WndwBaseOut; + uint32 addr2WndwMask; + uint32 addr2WndwBaseIn; + /* 0x80 */ + uint32 addr2WndwBaseOut; + uint32 scratch; + uint32 tm; + uint32 softResets; + /* 0x90 */ + uint32 eb2ubusTimeout; + uint32 m4keCoreStatus; + uint32 gpInIrqSense; + uint32 ubSlaveTimeout; + /* 0xa0 */ + uint32 diagEn; + uint32 devTimeout; + uint32 ubusErrorOutMask; + uint32 diagCaptStopMask; + /* 0xb0 */ + uint32 revId; + uint32 gpTmr2Ctl; + uint32 gpTmr2Cnt; + uint32 legacyMode; + /* 0xc0 */ + uint32 smisbMonitor; + uint32 diagCtrl; + uint32 diagStat; + uint32 diagMask; + /* 0xd0 */ + uint32 diagRslt; + uint32 diagCmp; + uint32 diagCapt; + uint32 diagCnt; + /* 0xe0 */ + uint32 diagEdgeCnt; + uint32 unused1[4]; /* 0xe4-0xf3 */ + /* 0xf4 */ + uint32 iopPeriphBaseAddr; + uint32 lfsr; + uint32 unused2; /* 0xfc-0xff */ +} PmcCtrlReg; + +typedef struct PmcOutFifoReg { + uint32 msgCtrl; /* 0x00 */ + uint32 msgSts; /* 0x04 */ + uint32 unused[14]; /* 0x08-0x3f */ + uint32 msgData[16]; /* 0x40-0x7c */ +} PmcOutFifoReg; + +typedef struct PmcInFifoReg { + uint32 msgCtrl; /* 0x00 */ + uint32 msgSts; /* 0x04 */ + uint32 unused[13]; /* 0x08-0x3b */ + uint32 msgLast; /* 0x3c */ + uint32 msgData[16]; /* 0x40-0x7c */ +} PmcInFifoReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + /* 0x00 */ + uint32 dcacheHit; + uint32 dcacheMiss; + uint32 icacheHit; + uint32 icacheMiss; + /* 0x10 */ + uint32 instnComplete; + uint32 wtbMerge; + uint32 wtbNoMerge; + uint32 itlbHit; + /* 0x20 */ + uint32 itlbMiss; + uint32 dtlbHit; + uint32 dtlbMiss; + uint32 jtlbHit; + /* 0x30 */ + uint32 jtlbMiss; + uint32 powerSubZone; + uint32 powerMemPda; + uint32 freqScalarCtrl; + /* 0x40 */ + uint32 freqScalarMask; +} PmcPerfPowReg; + +typedef struct PmcDQMReg { + /* 0x00 */ + uint32 cfg; + uint32 _4keLowWtmkIrqMask; + uint32 mipsLowWtmkIrqMask; + uint32 lowWtmkIrqMask; + /* 0x10 */ + uint32 _4keNotEmptyIrqMask; + uint32 mipsNotEmptyIrqMask; + uint32 notEmptyIrqSts; + uint32 queueRst; + /* 0x20 */ + uint32 notEmptySts; + uint32 nextAvailMask; + uint32 nextAvailQueue; + uint32 mips1LowWtmkIrqMask; + /* 0x30 */ + uint32 mips1NotEmptyIrqMask; + uint32 autoSrcPidInsert; +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +#define PVTMON_REG +typedef struct { + uint32 control; // 0x100 + uint32 reserved; // 0x104 + uint32 cfg_lo; // 0x108 + uint32 reserved1; // 0x10c + uint32 adc_data; // 0x110 + uint32 vref_data; // 0x114 + uint32 reserved2[2]; // 0x118 + uint32 ascan_config; // 0x120 + uint32 reserved3[119]; +} pvtmon_regs; + +typedef struct Pmc { + uint32 baseReserved; /* 0x0000 */ + uint32 unused0[1023]; + PmcCtrlReg ctrl; /* 0x1000 */ + + PmcOutFifoReg outFifo; /* 0x1100 */ + uint32 unused1[32]; /* 0x1180-0x11ff */ + PmcInFifoReg inFifo; /* 0x1200 */ + uint32 unused2[32]; /* 0x1280-0x12ff */ + + PmcDmaReg dma[2]; /* 0x1300 */ + uint32 unused3[48]; /* 0x1340-0x13ff */ + + PmcTokenReg token; /* 0x1400 */ + uint32 unused4[121]; /* 0x141c-0x15ff */ + + PmcPerfPowReg perfPower; /* 0x1600 */ + uint32 unused5[47]; /* 0x1644-0x16ff */ + + uint32 msgId[32]; /* 0x1700 */ + uint32 unused6[32]; /* 0x1780-0x17ff */ + + PmcDQMReg dqm; /* 0x1800 */ + uint32 unused7[50]; /* 0x1838-0x18ff */ + + PmcCntReg hwCounter; /* 0x1900 */ + uint32 unused8[46]; /* 0x1948-0x19ff */ + + PmcDqmQCtrlReg dqmQCtrl[32]; /* 0x1a00 */ + PmcDqmQDataReg dqmQData[32]; /* 0x1c00 */ + uint32 unused9[64]; /* 0x1e00-0x1eff */ + + uint32 qStatus[32]; /* 0x1f00 */ + uint32 unused10[32]; /* 0x1f80-0x1fff */ + + PmcDqmQMibReg qMib; /* 0x2000 */ + uint32 unused11[1952]; /* 0x2180-0x3ffff */ + + uint32 sharedMem[512]; /* 0x4000-0x47ff */ + uint32 unused12[126528]; /* 0x4800-0x80100 */ + + pvtmon_regs pvtmon[2]; +} Pmc; + +#define PMC ((volatile Pmc * const) PMC_BASE) + +/* + * Process Monitor Module + */ +typedef struct PMRingOscillatorControl { + uint32 control; + uint32 en_lo; + uint32 en_mid; + uint32 en_hi; + uint32 idle_lo; + uint32 idle_mid; + uint32 idle_hi; +} PMRingOscillatorControl; + +#define RCAL_0P25UM_HORZ 0 +#define RCAL_0P25UM_VERT 1 +#define RCAL_0P5UM_HORZ 2 +#define RCAL_0P5UM_VERT 3 +#define RCAL_1UM_HORZ 4 +#define RCAL_1UM_VERT 5 +#define PMMISC_RMON_EXT_REG ((RCAL_1UM_VERT + 1)/2) +#define PMMISC_RMON_VALID_MASK (0x1<<16) +typedef struct PMMiscControl { + uint32 gp_out; + uint32 clock_select; + uint32 unused[2]; + uint32 misc[4]; +} PMMiscControl; + +typedef struct PMSSBMasterControl { + uint32 control; +#define PMC_SSBM_CONTROL_SSB_START (1<<15) +#define PMC_SSBM_CONTROL_SSB_ADPRE (1<<13) +#define PMC_SSBM_CONTROL_SSB_EN (1<<12) +#define PMC_SSBM_CONTROL_SSB_CMD_SHIFT (10) +#define PMC_SSBM_CONTROL_SSB_CMD_MASK (0x3 << PMC_SSBM_CONTROL_SSB_CMD_SHIFT) +#define PMC_SSBM_CONTROL_SSB_CMD_READ (2) +#define PMC_SSBM_CONTROL_SSB_CMD_WRITE (1) +#define PMC_SSBM_CONTROL_SSB_ADDR_SHIFT (0) +#define PMC_SSBM_CONTROL_SSB_ADDR_MASK (0x3ff << PMC_SSBM_CONTROL_SSB_ADDR_SHIFT) + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct PMEctrControl { + uint32 control; + uint32 interval; + uint32 thresh_lo; + uint32 thresh_hi; + uint32 count; +} PMEctrControl; + +typedef struct PMBMaster { + uint32 ctrl; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_Read (0 << 20) +#define PMC_PMBM_Write (1 << 20) + uint32 wr_data; + uint32 timeout; + uint32 rd_data; + uint32 unused[4]; +} PMBMaster; + +typedef struct PMAPVTMONControl { + uint32 control; + uint32 reserved; + uint32 cfg_lo; + uint32 cfg_hi; + uint32 data; + uint32 vref_data; + uint32 unused[2]; + uint32 ascan_cfg; + uint32 warn_temp; + uint32 reset_temp; + uint32 temp_value; + uint32 data1_value; + uint32 data2_value; + uint32 data3_value; +} PMAPVTMONControl; + +typedef struct PMUBUSCfg { + uint32 window[8]; + uint32 control; +} PMUBUSCfg; + +typedef struct ProcessMonitorRegs { + uint32 MonitorCtrl; /* 0x00 */ + uint32 unused0[7]; + PMRingOscillatorControl ROSC; /* 0x20 */ + uint32 unused1; + PMMiscControl Misc; /* 0x40 */ + PMSSBMasterControl SSBMaster; /* 0x60 */ + uint32 unused2[5]; + PMEctrControl Ectr; /* 0x80 */ + uint32 unused3[11]; + PMBMaster PMBM[2]; /* 0xc0 */ + PMAPVTMONControl APvtmonCtrl; /* 0x100 - 0x13b */ + uint32 unused4[41]; + PMUBUSCfg UBUSCfg; /* 0x1e0 */ +} ProcessMonitorRegs; + +#define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE) + +/* + * Timer + */ +#define TIMER_64BIT +typedef struct Timer { + uint64 TimerCtl0; /* 0x00 */ + uint64 TimerCtl1; /* 0x08 */ + uint64 TimerCtl2; /* 0x10 */ + uint64 TimerCtl3; /* 0x18 */ +#define TIMERENABLE (1ULL << 63) +#define RSTCNTCLR (1ULL << 62) + uint64 TimerCnt0; /* 0x20 */ + uint64 TimerCnt1; /* 0x28 */ + uint64 TimerCnt2; /* 0x30 */ + uint64 TimerCnt3; /* 0x38 */ +#define TIMER_COUNT_MASK 0x3FFFFFFFFFFFFFFFULL + uint32 TimerMask; /* 0x40 */ +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 +#define TIMER3EN 0x08 + uint32 TimerInts; /* 0x44 */ +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define TIMER3 0x08 + uint32 ResetReason;/* 0x4c */ + uint32 spare[3]; /* 0x50 - 0x5b */ + uint32 reserved1[9]; /* 0x5c - 0x7f */ +} Timer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) + +typedef struct WDTimer { + uint32 WatchDogDefCount; + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 SoftRst; +#define SOFT_RESET 0x00000001 + uint32 WDAccessCtl; +} WDTimer; + +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + +typedef struct BIUCFG_Access { + uint32 permission; /* 0x0 */ + uint32 sbox; /* 0x4 */ + uint32 cpu_defeature; /* 0x8 */ + uint32 dbg_security; /* 0xc */ + uint32 rsvd1[32]; /* 0x10 - 0x8f */ + uint64 violation[2]; /* 0x90 - 0x9f */ + uint32 ts_access[2]; /* 0xa0 - 0xa7 */ + uint32 rsvd2[22]; /* 0xa8 - 0xff */ +}BIUCFG_Access; + +typedef struct BIUCFG_Cluster { + uint32 permission; /* 0x0 */ + uint32 config; /* 0x4 */ + uint32 status; /* 0x8 */ + uint32 control; /* 0xc */ + uint32 cpucfg; /* 0x10 */ + uint32 dbgrom; /* 0x14 */ + uint32 rsvd1[2]; /* 0x18 - 0x1f */ + uint64 rvbar_addr[4]; /* 0x20 - 0x3f */ + uint32 rsvd2[48]; /* 0x40 - 0xff */ +}BIUCFG_Cluster; + +typedef struct BIUCFG_Bac { + uint32 bac_permission; /* 0x00 */ + uint32 bac_periphbase; /* 0x04 */ + uint32 rsvd[2]; /* 0x08 - 0x0f */ + uint32 bac_event; /* 0x10 */ + uint32 rsvd_1[3]; /* 0x14 - 0x1f */ + uint32 bac_ccicfg; /* 0x20 */ + uint32 bac_cciaddr; /* 0x24 */ + uint32 rsvd_2[4]; /* 0x28 - 0x37 */ + uint32 bac_ccievs2; /* 0x38 */ + uint32 bac_ccievs3; /* 0x3c */ + uint32 bac_ccievs4; /* 0x40 */ + uint32 rsvd_3[3]; /* 0x44 - 0x4f */ + uint32 bac_ccievm0; /* 0x50 */ + uint32 bac_ccievm1; /* 0x54 */ + uint32 rsvd_4[2]; /* 0x58 - 0x5f */ + uint32 bac_dapapbcfg; /* 0x60 */ + uint32 bac_status; /* 0x64 */ + uint32 rsvd_5[2]; /* 0x68 - 0x6f */ + uint32 cpu_therm_irq_cfg; /* 0x70 */ + uint32 cpu_therm_threshold_cfg; /* 0x74 */ + uint32 rsvd_6; /* 0x78 */ + uint32 cpu_therm_temp; /* 0x7c */ + uint32 rsvd_7[32]; /* 0x80 - 0xff */ +} BIUCFG_Bac; + +typedef struct BIUCFG_Aux { + uint32 aux_permission; /* 0x00 */ + uint32 rsvd[3]; /* 0x04 - 0x0f */ + uint32 c0_clk_control; /* 0x10 */ + uint32 c0_clk_ramp; /* 0x14 */ + uint32 c0_clk_pattern; /* 0x18 */ + uint32 rsvd_1; /* 0x1c */ + uint32 c1_clk_control; /* 0x20 */ + uint32 c1_clk_ramp; /* 0x24 */ + uint32 c1_clk_pattern; /* 0x28 */ + uint32 rsvd_2[53]; /* 0x2c - 0xff */ +} BIUCFG_Aux; + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff*/ + BIUCFG_Cluster cluster[2]; /* 0x100 - 0x2ff*/ + BIUCFG_Bac bac; /* 0x300 - 0x3ff */ + uint32 anonymous[192]; /* 0x400 - 0x6ff */ + BIUCFG_Aux aux; /* 0x700 - 0x7ff */ + uint32 anonymous_1[2560]; /* 0x800 - 0x2fff */ +}BIUCFG; + +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/plat/bcm/include/bcm963xx/63178_map_part.h b/plat/bcm/include/bcm963xx/63178_map_part.h new file mode 100755 index 00000000..6fcd3d8c --- /dev/null +++ b/plat/bcm/include/bcm963xx/63178_map_part.h @@ -0,0 +1,503 @@ +/* +<:copyright-BRCM:2015:DUAL/GPL:standard + + Copyright (c) 2015 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> + +*/ + +#ifndef __BCM63178_MAP_PART_H +#define __BCM63178_MAP_PART_H +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define MEMC_PHYS_BASE 0x80180000 +#define MEMC_SIZE 0x24000 + +#define PMC_PHYS_BASE 0x80200000 +#define PMC_SIZE 0x00200000 +#define PMC_OFFSET 0x00100000 +#define PROC_MON_OFFSET 0x00100000 +#define PMB_OFFSET 0x00120100 + +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x13000 +#define TIMR_OFFSET 0x0400 +#define WDTIMR0_OFFSET 0x0480 +#define WDTIMR1_OFFSET 0x04c0 + +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define BOOTLUT_PHYS_BASE 0xffff0000 +#define BOOTLUT_SIZE 0x1000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + +#define PMC_BASE (PMC_PHYS_BASE + PMC_OFFSET) +#define PMB_BASE (PMC_PHYS_BASE + PMB_OFFSET) +#define PROC_MON_BASE (PMC_PHYS_BASE + PROC_MON_OFFSET) + +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) +#define TIMR_BASE (PERF_PHYS_BASE + TIMR_OFFSET) + +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) + + +#ifndef __ASSEMBLER__ + +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + uint32 gpTmr0Ctl; /* 0x018 */ + uint32 gpTmr0Cnt; /* 0x01c */ + uint32 gpTmr1Ctl; /* 0x020 */ + uint32 gpTmr1Cnt; /* 0x024 */ + uint32 hostMboxIn; /* 0x028 */ + uint32 hostMboxOut; /* 0x02c */ + uint32 reserved[4]; /* 0x030 */ + uint32 dmaCtrl; /* 0x040 */ + uint32 dmaStatus; /* 0x044 */ + uint32 dma0_3FifoStatus; /* 0x048 */ + uint32 reserved1[4]; /* 0x04c */ + uint32 diagControl; /* 0x05c */ + uint32 diagHigh; /* 0x060 */ + uint32 diagLow; /* 0x064 */ + uint32 reserved8; /* 0x068 */ + uint32 addr1WndwMask; /* 0x06c */ + uint32 addr1WndwBaseIn; /* 0x070 */ + uint32 addr1WndwBaseOut; /* 0x074 */ + uint32 addr2WndwMask; /* 0x078 */ + uint32 addr2WndwBaseIn; /* 0x07c */ + uint32 addr2WndwBaseOut; /* 0x080 */ + uint32 scratch; /* 0x084 */ + uint32 reserved9; /* 0x088 */ + uint32 softResets; /* 0x08c */ + uint32 reserved2; /* 0x090 */ + uint32 m4keCoreStatus; /* 0x094 */ + uint32 reserved3; /* 0x098 */ + uint32 ubSlaveTimeout; /* 0x09c */ + uint32 diagEn; /* 0x0a0 */ + uint32 devTimeout; /* 0x0a4 */ + uint32 ubusErrorOutMask; /* 0x0a8 */ + uint32 diagCaptStopMask; /* 0x0ac */ + uint32 revId; /* 0x0b0 */ + uint32 reserved4[4]; /* 0x0b4 */ + uint32 diagCtrl; /* 0x0c4 */ + uint32 diagStat; /* 0x0c8 */ + uint32 diagMask; /* 0x0cc */ + uint32 diagRslt; /* 0x0d0 */ + uint32 diagCmp; /* 0x0d4 */ + uint32 diagCapt; /* 0x0d8 */ + uint32 diagCnt; /* 0x0dc */ + uint32 diagEdgeCnt; /* 0x0e0 */ + uint32 reserved5[4]; /* 0x0e4 */ + uint32 smisc_bus_config; /* 0x0f4 */ + uint32 lfsr; /* 0x0f8 */ + uint32 dqm_pac_lock; /* 0x0fc */ + uint32 l1_irq_4ke_mask; /* 0x100 */ + uint32 l1_irq_4ke_status; /* 0x104 */ + uint32 l1_irq_mips_mask; /* 0x108 */ + uint32 l1_irq_mips_status; /* 0x10c */ + uint32 l1_irq_mips1_mask; /* 0x110 */ + uint32 reserved6[3]; /* 0x114 */ + uint32 l2_irq_gp_mask; /* 0x120 */ + uint32 l2_irq_gp_status; /* 0x124 */ + uint32 l2_irq_gp_set; /* 0x128 */ + uint32 reserved7; /* 0x12c */ + uint32 gp_in_irq_mask; /* 0x130 */ + uint32 gp_in_irq_status; /* 0x134 */ + uint32 gp_in_irq_set; /* 0x138 */ + uint32 gp_in_irq_sense; /* 0x13c */ + uint32 gp_in; /* 0x140 */ + uint32 gp_out; /* 0x144 */ +} PmcCtrlReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + uint32 freqScalarCtrl; /* 0x3c */ + uint32 freqScalarMask; /* 0x40 */ +} PmcPerfPowReg; + +typedef struct PmcDQMPac { + uint32 dqmPac[32]; +} PmcDQMPac; + +typedef struct PmcDQMReg { + uint32 cfg; /* 0x1c00 */ + uint32 _4keLowWtmkIrqMask; /* 0x1c04 */ + uint32 mipsLowWtmkIrqMask; /* 0x1c08 */ + uint32 lowWtmkIrqMask; /* 0x1c0c */ + uint32 _4keNotEmptyIrqMask; /* 0x1c10 */ + uint32 mipsNotEmptyIrqMask; /* 0x1c14 */ + uint32 notEmptyIrqSts; /* 0x1c18 */ + uint32 queueRst; /* 0x1c1c */ + uint32 notEmptySts; /* 0x1c20 */ + uint32 nextAvailMask; /* 0x1c24 */ + uint32 nextAvailQueue; /* 0x1c28 */ + uint32 mips1LowWtmkIrqMask; /* 0x1c2c */ + uint32 mips1NotEmptyIrqMask; /* 0x1c30 */ + uint32 autoSrcPidInsert; /* 0x1c34 */ + uint32 timerIrqStatus; /* 0x1c38 */ + uint32 timerStatus; /* 0x1c3c */ + uint32 _4keTimerIrqMask; /* 0x1c40 */ + uint32 mipsTimerIrqMask; /* 0x1c44 */ + uint32 mips1TimerIrqMask; /* 0x1c48 */ +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct SSBMaster { + uint32 ssbmControl; /* 0x0060 */ + uint32 ssbmWrData; /* 0x0064 */ + uint32 ssbmRdData; /* 0x0068 */ + uint32 ssbmStatus; /* 0x006c */ +} SSBMaster; + +typedef struct PmmReg { + uint32 memPowerCtrl; /* 0x0000 */ + uint32 regSecurityConfig; /* 0x0004 */ +} PmmReg; + +typedef struct keyholeReg { + uint32 ctrlSts; + uint32 wrData; + uint32 mutex; + uint32 rdData; +} keyholeReg; + +typedef struct PmbBus { + uint32 config; /* 0x0100 */ + uint32 arbiter; /* 0x0104 */ + uint32 timeout; /* 0x0108 */ + uint32 unused1; /* 0x010c */ + keyholeReg keyhole[4]; /* 0x0110-0x014f */ + uint32 unused2[44]; /* 0x0150-0x01ff */ + uint32 map[64]; /* 0x0200-0x02ff */ +}PmbBus; + +typedef struct CoreCtrl { + uint32 coreEnable; /* 0x0400 */ + uint32 autoresetControl; /* 0x0404 */ + uint32 coreIdle; /* 0x0408 */ + uint32 coreResetCause; /* 0x040c */ + uint32 memPwrDownCtrl0; /* 0x0410 */ + uint32 memPwrDownSts0; /* 0x0414 */ + uint32 memPwrDownCtrl1; /* 0x0418 */ + uint32 memPwrDownSts1; /* 0x041c */ + uint32 sysFlg0Status; /* 0x0420 */ + uint32 sysFlg0Set; /* 0x0424 */ + uint32 sysFlg0Clear; /* 0x0428 */ + uint32 unused1; /* 0x042c */ + uint32 usrFlg0Status; /* 0x0430 */ + uint32 usrFlg0Set; /* 0x0434 */ + uint32 usrFlg0Clear; /* 0x0438 */ + uint32 unused2; /* 0x043c */ + uint32 subsystemRev; /* 0x0440 */ + uint32 resetVector; /* 0x0444 */ +} CoreCtrl; + +typedef struct CoreState { + uint32 sysMbx[8]; /* 0x0480 */ + uint32 usrMbx[8]; /* 0x04a0 */ + uint32 sysMtx[4]; /* 0x04c0 */ + uint32 usrMtx[8]; /* 0x04d0 */ +} CoreState; + +typedef struct CoreIntr { + uint32 irqStatus; /* 0x0500 */ + uint32 irqSet; /* 0x0504 */ + uint32 irqClear; /* 0x0508 */ + uint32 unused1; /* 0x050c */ + uint32 srqStatus; /* 0x0510 */ + uint32 srqSet; /* 0x0514 */ + uint32 srqClear; /* 0x0518 */ + uint32 unused2; /* 0x051c */ + uint32 drqStatus; /* 0x0520 */ + uint32 drqSet; /* 0x0524 */ + uint32 drqClear; /* 0x0528 */ + uint32 unused3; /* 0x052c */ + uint32 frqStatus; /* 0x0530 */ + uint32 frqSet; /* 0x0534 */ + uint32 frqClear; /* 0x0538 */ + uint32 unused4; /* 0x053c */ + uint32 hostIrqLatched; /* 0x0540 */ + uint32 hostIrqSet; /* 0x0544 */ + uint32 hostIrqClear; /* 0x0548 */ + uint32 hostIrqEnable; /* 0x054c */ + uint32 obusFaultStatus; /* 0x0550 */ + uint32 obusFaultClear; /* 0x0554 */ + uint32 obusFaultAddr; /* 0x0558 */ +} CoreIntr; + +typedef struct CoreProfile { + uint32 mutex; /* 0x0580 */ + uint32 lastConfPcLo; /* 0x0584 */ + uint32 lastConfPcHi; /* 0x0588 */ + uint32 lastPcLo; /* 0x058c */ + uint32 lastPcHi; /* 0x0590 */ + uint32 braTargetPc0Lo; /* 0x0594 */ + uint32 braTargetPc0Hi; /* 0x0598 */ + uint32 braTargetPc1Lo; /* 0x059c */ + uint32 braTargetPc1Hi; /* 0x05a0 */ + uint32 braTargetPc2Lo; /* 0x05a4 */ + uint32 braTargetPc2Hi; /* 0x05a8 */ + uint32 braTargetPc3Lo; /* 0x05ac */ + uint32 braTargetPc3Hi; /* 0x05b0 */ + uint32 unused[3]; /* 0x05b4-0x05bf */ + uint32 profSampleW[4]; /* 0x05c0 */ +} CoreProfile; + +typedef struct MaestroMisc { + CoreCtrl coreCtrl; /* 0x0400 */ + uint32 unused1[14]; /* 0x0448-0x047f */ + CoreState coreState; /* 0x0480 */ + uint32 unused2[4]; /* 0x04f0-0x04ff */ + CoreIntr interrupt; /* 0x0500 */ + uint32 unused3[9]; /* 0x055c-0x057f */ + CoreProfile profile; /* 0x0580 */ +} MaestroMisc; + +typedef struct Pmc { + uint32 unused0[1030]; + PmcCtrlReg ctrl; /* 0x1018 */ + uint32 unused1[622]; /* 0x1148-0x1cff */ + PmcDQMPac dqmPac; /* 0x1b00 */ + uint32 unused5[32]; /* 0x1b80-0x1bff */ + PmcDQMReg dqm; /* 0x1c00 */ + uint32 unused6[749]; /* 0x1c4c-0x27ff */ + uint32 qStatus[32]; /* 0x2800 */ + uint32 unused7[480]; /* 0x2880-0x2fff */ + PmcDqmQMibReg qMib; /* 0x3000 */ + uint32 unused8[928]; /* 0x3180-0x3fff */ + PmcDqmQCtrlReg dqmQCtrl[8]; /* 0x4000 */ + uint32 unused9[992]; /* 0x4080-0x4fff */ + PmcDqmQDataReg dqmQData[8]; /* 0x5000 */ +} Pmc; +#define PMC ((volatile Pmc * const) PMC_BASE) + +typedef struct Procmon { + uint32 unused00[256]; + MaestroMisc maestroReg; /* 0x00400 */ + uint32 unused10[32396]; /* 0x005d0-0x1ffff */ + PmmReg pmm; /* 0x20000 */ + uint32 unused11[22]; /* 0x20008-0x2005f */ + SSBMaster ssbMasterCtrl; /* 0x20060 */ + uint32 unused12[36]; /* 0x20070-0x200ff */ + PmbBus pmb; /* 0x20100 */ + uint32 unused13[32576]; /* 0x20300-0x3ffff */ + uint32 qsm[128]; /* 0x40000-0x401ff */ + uint32 unused14[65408]; /* 0x40200-0x7ffff */ + uint32 dtcm[1024]; /* 0x80000-0x80fff */ +} Procmon; +#define PROCMON ((volatile Procmon * const) PROC_MON_BASE) + +typedef struct PMSSBMasterControl { + uint32 control; + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct +{ + uint32 control; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_BUS_SHIFT (20) +#define PMC_PMBM_Read (0 << 24) +#define PMC_PMBM_Write (1 << 24) + uint32 wr_data; + uint32 mutex; + uint32 rd_data; +} PMB_keyhole_reg; + +typedef struct PMBMaster { + uint32 config; +#define PMB_NUM_REGS_SHIFT (20) +#define PMB_NUM_REGS_MASK (0x3ff) + uint32 arbitger; + uint32 timeout; + uint32 reserved; + PMB_keyhole_reg keyhole[4]; + uint32 reserved1[44]; + uint32 map[64]; +} PMBMaster; +#define PMB ((volatile PMBMaster * const) PMB_BASE) + +/* WatchDog */ +typedef struct WDTimer { + uint32 WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * * * Read from this register returns current watch dog count + * * */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + +#define SOFT_RESET 0x00000001 + uint32 WDTimerCtl; + + uint32 WDAccessCtl; +} WDTimer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + + +/* BIU - Bus Interface Unit */ +typedef struct BIUCFG_Access { + uint32 permission; /* 0x0 */ + uint32 sbox; /* 0x4 */ + uint32 cpu_defeature; /* 0x8 */ + uint32 dbg_security; /* 0xc */ + uint32 rsvd1[32]; /* 0x10 - 0x8f */ + uint64 violation[2]; /* 0x90 - 0x9f */ + uint32 ts_access[2]; /* 0xa0 - 0xa7 */ + uint32 rsvd2[22]; /* 0xa8 - 0xff */ +}BIUCFG_Access; + + + + +typedef struct BIUCFG_Cluster { + uint32 permission; /* 0x0 */ + uint32 config; /* 0x4 */ + uint32 status; /* 0x8 */ + uint32 control; /* 0xc */ + uint32 cpucfg; /* 0x10 */ + uint32 dbgrom; /* 0x14 */ + uint32 rsvd1[2]; /* 0x18 - 0x1f */ + uint64 rvbar_addr[4]; /* 0x20 - 0x3f */ + uint32 rsvd2[48]; /* 0x40 - 0xff */ +}BIUCFG_Cluster; + +typedef struct BIUCFG_Bac { + uint32 bac_permission; /* 0x00 */ + uint32 bac_periphbase; /* 0x04 */ + uint32 rsvd[2]; /* 0x08 - 0x0f */ + uint32 bac_event; /* 0x10 */ + uint32 rsvd_1[3]; /* 0x14 - 0x1f */ + uint32 bac_ccicfg; /* 0x20 */ + uint32 bac_cciaddr; /* 0x24 */ + uint32 rsvd_2[4]; /* 0x28 - 0x37 */ + uint32 bac_ccievs2; /* 0x38 */ + uint32 bac_ccievs3; /* 0x3c */ + uint32 bac_ccievs4; /* 0x40 */ + uint32 rsvd_3[3]; /* 0x44 - 0x4f */ + uint32 bac_ccievm0; /* 0x50 */ + uint32 bac_ccievm1; /* 0x54 */ + uint32 rsvd_4[2]; /* 0x58 - 0x5f */ + uint32 bac_dapapbcfg; /* 0x60 */ + uint32 bac_status; /* 0x64 */ + uint32 rsvd_5[2]; /* 0x68 - 0x6f */ + uint32 cpu_therm_irq_cfg; /* 0x70 */ + uint32 cpu_therm_threshold_cfg; /* 0x74 */ + uint32 rsvd_6; /* 0x78 */ + uint32 cpu_therm_temp; /* 0x7c */ + uint32 rsvd_7[32]; /* 0x80 - 0xff */ +} BIUCFG_Bac; + +typedef struct BIUCFG_Aux { + uint32 aux_permission; /* 0x00 */ + uint32 rsvd[3]; /* 0x04 - 0x0f */ + uint32 c0_clk_control; /* 0x10 */ + uint32 c0_clk_ramp; /* 0x14 */ + uint32 c0_clk_pattern; /* 0x18 */ + uint32 rsvd_1; /* 0x1c */ + uint32 c1_clk_control; /* 0x20 */ + uint32 c1_clk_ramp; /* 0x24 */ + uint32 c1_clk_pattern; /* 0x28 */ + uint32 rsvd_2[53]; /* 0x2c - 0xff */ +} BIUCFG_Aux; + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff*/ + BIUCFG_Cluster cluster[2]; /* 0x100 - 0x2ff*/ + BIUCFG_Bac bac; /* 0x300 - 0x3ff */ + uint32 anonymous[192]; /* 0x400 - 0x6ff */ + BIUCFG_Aux aux; /* 0x700 - 0x7ff */ + uint32 anonymous_1[2560]; /* 0x800 - 0x2fff */ +}BIUCFG; +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/plat/bcm/include/bcm963xx/6756_map_part.h b/plat/bcm/include/bcm963xx/6756_map_part.h new file mode 100644 index 00000000..af314b08 --- /dev/null +++ b/plat/bcm/include/bcm963xx/6756_map_part.h @@ -0,0 +1,504 @@ +/* +<:copyright-BRCM:2020:DUAL/GPL:standard + + Copyright (c) 2020 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> + +*/ + +#ifndef __BCM6756_MAP_PART_H +#define __BCM6756_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define CHIP_FAMILY_ID_HEX 0x6756 + +#define MEMC_PHYS_BASE 0x80180000 +#define MEMC_SIZE 0x24000 + +#define PMC_PHYS_BASE 0x80200000 +#define PMC_SIZE 0x00200000 +#define PMC_OFFSET 0x00100000 +#define PROC_MON_OFFSET 0x00100000 +#define PMB_OFFSET 0x00120100 + +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x13000 +#define TIMR_OFFSET 0x0400 +#define WDTIMR0_OFFSET 0x0480 +#define WDTIMR1_OFFSET 0x04c0 + +#define BIU_PHYS_BASE 0x81000000 +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define BOOTLUT_PHYS_BASE 0xffff0000 +#define BOOTLUT_SIZE 0x1000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + +#define PMC_BASE (PMC_PHYS_BASE + PMC_OFFSET) +#define PROC_MON_BASE (PMC_PHYS_BASE + PROC_MON_OFFSET) +#define PMB_BASE (PMC_PHYS_BASE + PMB_OFFSET) +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) + + + +#ifndef __ASSEMBLER__ + +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + uint32 gpTmr0Ctl; /* 0x018 */ + uint32 gpTmr0Cnt; /* 0x01c */ + uint32 gpTmr1Ctl; /* 0x020 */ + uint32 gpTmr1Cnt; /* 0x024 */ + uint32 hostMboxIn; /* 0x028 */ + uint32 hostMboxOut; /* 0x02c */ + uint32 reserved[4]; /* 0x030 */ + uint32 dmaCtrl; /* 0x040 */ + uint32 dmaStatus; /* 0x044 */ + uint32 dma0_3FifoStatus; /* 0x048 */ + uint32 reserved1[4]; /* 0x04c */ + uint32 diagControl; /* 0x05c */ + uint32 diagHigh; /* 0x060 */ + uint32 diagLow; /* 0x064 */ + uint32 reserved8; /* 0x068 */ + uint32 addr1WndwMask; /* 0x06c */ + uint32 addr1WndwBaseIn; /* 0x070 */ + uint32 addr1WndwBaseOut; /* 0x074 */ + uint32 addr2WndwMask; /* 0x078 */ + uint32 addr2WndwBaseIn; /* 0x07c */ + uint32 addr2WndwBaseOut; /* 0x080 */ + uint32 scratch; /* 0x084 */ + uint32 reserved9; /* 0x088 */ + uint32 softResets; /* 0x08c */ + uint32 reserved2; /* 0x090 */ + uint32 m4keCoreStatus; /* 0x094 */ + uint32 reserved3; /* 0x098 */ + uint32 ubSlaveTimeout; /* 0x09c */ + uint32 diagEn; /* 0x0a0 */ + uint32 devTimeout; /* 0x0a4 */ + uint32 ubusErrorOutMask; /* 0x0a8 */ + uint32 diagCaptStopMask; /* 0x0ac */ + uint32 revId; /* 0x0b0 */ + uint32 reserved4[4]; /* 0x0b4 */ + uint32 diagCtrl; /* 0x0c4 */ + uint32 diagStat; /* 0x0c8 */ + uint32 diagMask; /* 0x0cc */ + uint32 diagRslt; /* 0x0d0 */ + uint32 diagCmp; /* 0x0d4 */ + uint32 diagCapt; /* 0x0d8 */ + uint32 diagCnt; /* 0x0dc */ + uint32 diagEdgeCnt; /* 0x0e0 */ + uint32 reserved5[4]; /* 0x0e4 */ + uint32 smisc_bus_config; /* 0x0f4 */ + uint32 lfsr; /* 0x0f8 */ + uint32 dqm_pac_lock; /* 0x0fc */ + uint32 l1_irq_4ke_mask; /* 0x100 */ + uint32 l1_irq_4ke_status; /* 0x104 */ + uint32 l1_irq_mips_mask; /* 0x108 */ + uint32 l1_irq_mips_status; /* 0x10c */ + uint32 l1_irq_mips1_mask; /* 0x110 */ + uint32 reserved6[3]; /* 0x114 */ + uint32 l2_irq_gp_mask; /* 0x120 */ + uint32 l2_irq_gp_status; /* 0x124 */ + uint32 l2_irq_gp_set; /* 0x128 */ + uint32 reserved7; /* 0x12c */ + uint32 gp_in_irq_mask; /* 0x130 */ + uint32 gp_in_irq_status; /* 0x134 */ + uint32 gp_in_irq_set; /* 0x138 */ + uint32 gp_in_irq_sense; /* 0x13c */ + uint32 gp_in; /* 0x140 */ + uint32 gp_out; /* 0x144 */ +} PmcCtrlReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + uint32 freqScalarCtrl; /* 0x3c */ + uint32 freqScalarMask; /* 0x40 */ +} PmcPerfPowReg; + +typedef struct PmcDQMPac { + uint32 dqmPac[32]; +} PmcDQMPac; + +typedef struct PmcDQMReg { + uint32 cfg; /* 0x1c00 */ + uint32 _4keLowWtmkIrqMask; /* 0x1c04 */ + uint32 mipsLowWtmkIrqMask; /* 0x1c08 */ + uint32 lowWtmkIrqMask; /* 0x1c0c */ + uint32 _4keNotEmptyIrqMask; /* 0x1c10 */ + uint32 mipsNotEmptyIrqMask; /* 0x1c14 */ + uint32 notEmptyIrqSts; /* 0x1c18 */ + uint32 queueRst; /* 0x1c1c */ + uint32 notEmptySts; /* 0x1c20 */ + uint32 nextAvailMask; /* 0x1c24 */ + uint32 nextAvailQueue; /* 0x1c28 */ + uint32 mips1LowWtmkIrqMask; /* 0x1c2c */ + uint32 mips1NotEmptyIrqMask; /* 0x1c30 */ + uint32 autoSrcPidInsert; /* 0x1c34 */ + uint32 timerIrqStatus; /* 0x1c38 */ + uint32 timerStatus; /* 0x1c3c */ + uint32 _4keTimerIrqMask; /* 0x1c40 */ + uint32 mipsTimerIrqMask; /* 0x1c44 */ + uint32 mips1TimerIrqMask; /* 0x1c48 */ +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct SSBMaster { + uint32 ssbmControl; /* 0x0060 */ + uint32 ssbmWrData; /* 0x0064 */ + uint32 ssbmRdData; /* 0x0068 */ + uint32 ssbmStatus; /* 0x006c */ +} SSBMaster; + +typedef struct PmmReg { + uint32 memPowerCtrl; /* 0x0000 */ + uint32 regSecurityConfig; /* 0x0004 */ +} PmmReg; + +typedef struct keyholeReg { + uint32 ctrlSts; + uint32 wrData; + uint32 mutex; + uint32 rdData; +} keyholeReg; + +typedef struct PmbBus { + uint32 config; /* 0x0100 */ + uint32 arbiter; /* 0x0104 */ + uint32 timeout; /* 0x0108 */ + uint32 unused1; /* 0x010c */ + keyholeReg keyhole[4]; /* 0x0110-0x014f */ + uint32 unused2[44]; /* 0x0150-0x01ff */ + uint32 map[64]; /* 0x0200-0x02ff */ +}PmbBus; + +typedef struct CoreCtrl { + uint32 coreEnable; /* 0x0400 */ + uint32 autoresetControl; /* 0x0404 */ + uint32 coreIdle; /* 0x0408 */ + uint32 coreResetCause; /* 0x040c */ + uint32 memPwrDownCtrl0; /* 0x0410 */ + uint32 memPwrDownSts0; /* 0x0414 */ + uint32 memPwrDownCtrl1; /* 0x0418 */ + uint32 memPwrDownSts1; /* 0x041c */ + uint32 sysFlg0Status; /* 0x0420 */ + uint32 sysFlg0Set; /* 0x0424 */ + uint32 sysFlg0Clear; /* 0x0428 */ + uint32 unused1; /* 0x042c */ + uint32 usrFlg0Status; /* 0x0430 */ + uint32 usrFlg0Set; /* 0x0434 */ + uint32 usrFlg0Clear; /* 0x0438 */ + uint32 unused2; /* 0x043c */ + uint32 subsystemRev; /* 0x0440 */ + uint32 resetVector; /* 0x0444 */ +} CoreCtrl; + +typedef struct CoreState { + uint32 sysMbx[8]; /* 0x0480 */ + uint32 usrMbx[8]; /* 0x04a0 */ + uint32 sysMtx[4]; /* 0x04c0 */ + uint32 usrMtx[8]; /* 0x04d0 */ +} CoreState; + +typedef struct CoreIntr { + uint32 irqStatus; /* 0x0500 */ + uint32 irqSet; /* 0x0504 */ + uint32 irqClear; /* 0x0508 */ + uint32 unused1; /* 0x050c */ + uint32 srqStatus; /* 0x0510 */ + uint32 srqSet; /* 0x0514 */ + uint32 srqClear; /* 0x0518 */ + uint32 unused2; /* 0x051c */ + uint32 drqStatus; /* 0x0520 */ + uint32 drqSet; /* 0x0524 */ + uint32 drqClear; /* 0x0528 */ + uint32 unused3; /* 0x052c */ + uint32 frqStatus; /* 0x0530 */ + uint32 frqSet; /* 0x0534 */ + uint32 frqClear; /* 0x0538 */ + uint32 unused4; /* 0x053c */ + uint32 hostIrqLatched; /* 0x0540 */ + uint32 hostIrqSet; /* 0x0544 */ + uint32 hostIrqClear; /* 0x0548 */ + uint32 hostIrqEnable; /* 0x054c */ + uint32 obusFaultStatus; /* 0x0550 */ + uint32 obusFaultClear; /* 0x0554 */ + uint32 obusFaultAddr; /* 0x0558 */ +} CoreIntr; + +typedef struct CoreProfile { + uint32 mutex; /* 0x0580 */ + uint32 lastConfPcLo; /* 0x0584 */ + uint32 lastConfPcHi; /* 0x0588 */ + uint32 lastPcLo; /* 0x058c */ + uint32 lastPcHi; /* 0x0590 */ + uint32 braTargetPc0Lo; /* 0x0594 */ + uint32 braTargetPc0Hi; /* 0x0598 */ + uint32 braTargetPc1Lo; /* 0x059c */ + uint32 braTargetPc1Hi; /* 0x05a0 */ + uint32 braTargetPc2Lo; /* 0x05a4 */ + uint32 braTargetPc2Hi; /* 0x05a8 */ + uint32 braTargetPc3Lo; /* 0x05ac */ + uint32 braTargetPc3Hi; /* 0x05b0 */ + uint32 unused[3]; /* 0x05b4-0x05bf */ + uint32 profSampleW[4]; /* 0x05c0 */ +} CoreProfile; + +typedef struct MaestroMisc { + CoreCtrl coreCtrl; /* 0x0400 */ + uint32 unused1[14]; /* 0x0448-0x047f */ + CoreState coreState; /* 0x0480 */ + uint32 unused2[4]; /* 0x04f0-0x04ff */ + CoreIntr interrupt; /* 0x0500 */ + uint32 unused3[9]; /* 0x055c-0x057f */ + CoreProfile profile; /* 0x0580 */ +} MaestroMisc; + +typedef struct Pmc { + uint32 unused0[1030]; + PmcCtrlReg ctrl; /* 0x1018 */ + uint32 unused1[622]; /* 0x1148-0x1cff */ + PmcDQMPac dqmPac; /* 0x1b00 */ + uint32 unused5[32]; /* 0x1b80-0x1bff */ + PmcDQMReg dqm; /* 0x1c00 */ + uint32 unused6[749]; /* 0x1c4c-0x27ff */ + uint32 qStatus[32]; /* 0x2800 */ + uint32 unused7[480]; /* 0x2880-0x2fff */ + PmcDqmQMibReg qMib; /* 0x3000 */ + uint32 unused8[928]; /* 0x3180-0x3fff */ + PmcDqmQCtrlReg dqmQCtrl[8]; /* 0x4000 */ + uint32 unused9[992]; /* 0x4080-0x4fff */ + PmcDqmQDataReg dqmQData[8]; /* 0x5000 */ +} Pmc; + +#define PMC ((volatile Pmc * const) PMC_BASE) +typedef struct Procmon { + uint32 unused00[256]; + MaestroMisc maestroReg; /* 0x00400 */ + uint32 unused10[32396]; /* 0x005d0-0x1ffff */ + PmmReg pmm; /* 0x20000 */ + uint32 unused11[22]; /* 0x20008-0x2005f */ + SSBMaster ssbMasterCtrl; /* 0x20060 */ + uint32 unused12[36]; /* 0x20070-0x200ff */ + PmbBus pmb; /* 0x20100 */ + uint32 unused13[32576]; /* 0x20300-0x3ffff */ + uint32 qsm[128]; /* 0x40000-0x401ff */ + uint32 unused14[65408]; /* 0x40200-0x7ffff */ + uint32 dtcm[1024]; /* 0x80000-0x80fff */ +} Procmon; +#define PROCMON ((volatile Procmon * const) PROC_MON_BASE) + +typedef struct PMSSBMasterControl { + uint32 control; + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct +{ + uint32 control; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_BUS_SHIFT (20) +#define PMC_PMBM_Read (0 << 24) +#define PMC_PMBM_Write (1 << 24) + uint32 wr_data; + uint32 mutex; + uint32 rd_data; +} PMB_keyhole_reg; + +typedef struct PMBMaster { + uint32 config; +#define PMB_NUM_REGS_SHIFT (20) +#define PMB_NUM_REGS_MASK (0x3ff) + uint32 arbitger; + uint32 timeout; + uint32 reserved; + PMB_keyhole_reg keyhole[4]; + uint32 reserved1[44]; + uint32 map[64]; +} PMBMaster; +#define PMB ((volatile PMBMaster * const) PMB_BASE) + +typedef struct WDTimer { + uint32 WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + +#define SOFT_RESET 0x00000001 + uint32 WDTimerCtl; + + uint32 WDAccessCtl; +} WDTimer; + +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + +typedef struct BIUCFG_Access { + uint32_t permission; /* 0x0 */ + uint32_t sbox; /* 0x4 */ + uint32_t cpu_defeature; /* 0x8 */ + uint32_t dbg_security; /* 0xc */ + uint32_t rsvd1[32]; /* 0x10 - 0x8f */ + uint64_t violation[2]; /* 0x90 - 0x9f */ + uint32_t ts_access[2]; /* 0xa0 - 0xa7 */ + uint32_t rsvd2[22]; /* 0xa8 - 0xff */ +} BIUCFG_Access; + +typedef struct BIUCFG_Cluster { + uint32_t permission; /* 0x0 */ + uint32_t config; /* 0x4 */ + uint32_t status; /* 0x8 */ + uint32_t control; /* 0xc */ + uint32_t cpucfg; /* 0x10 */ + uint32_t dbgrom; /* 0x14 */ + uint32_t rsvd1[2]; /* 0x18 - 0x1f */ + uint32_t rvbar_addr[4]; /* 0x20 - 0x2f */ + uint32_t rsvd2[52]; /* 0x30 - 0xff */ +} BIUCFG_Cluster; + +typedef struct BIUCFG_AuxClkCtrl { + uint32_t clk_control; /* 0x0 */ + uint32_t clk_ramp; /* 0x4 */ + uint32_t clk_pattern; /* 0x8 */ + uint32_t rsvd; /* 0xC */ +} BIUCFG_AuxClkCtrl; + +typedef struct BIUCFGux { + uint32_t permission; /* 0 */ + uint32_t rsvd1[3]; /* 0x04 - 0x0c */ + BIUCFG_AuxClkCtrl cluster_clkctrl[2];/* 0x10 - 0x2c */ + uint32_t rsvd2[52]; /* 0x30 - 0xFF */ +} BIUCFG_Aux; + +typedef struct BIUCFG_Bac { + uint32_t bac_permission; /* 0x00 */ + uint32_t bac_periphbase; /* 0x04 */ + uint32_t rsvd[2]; /* 0x08 - 0x0f */ + uint32_t bac_event; /* 0x10 */ + uint32_t rsvd_1[3]; /* 0x14 - 0x1f */ + uint32_t bac_ccicfg; /* 0x20 */ + uint32_t bac_cciaddr; /* 0x24 */ + uint32_t rsvd_2[4]; /* 0x28 - 0x37 */ + uint32_t bac_ccievs2; /* 0x38 */ + uint32_t bac_ccievs3; /* 0x3c */ + uint32_t bac_ccievs4; /* 0x40 */ + uint32_t rsvd_3[3]; /* 0x44 - 0x4f */ + uint32_t bac_ccievm0; /* 0x50 */ + uint32_t bac_ccievm1; /* 0x54 */ + uint32_t rsvd_4[2]; /* 0x58 - 0x5f */ + uint32_t bac_dapapbcfg; /* 0x60 */ + uint32_t bac_status; /* 0x64 */ + uint32_t rsvd_5[2]; /* 0x68 - 0x6f */ + uint32_t cpu_therm_irq_cfg;/* 0x70 */ + uint32_t cpu_therm_threshold_cfg; /* 0x74 */ + uint32_t rsvd_6; /* 0x78 */ + uint32_t cpu_therm_temp; /* 0x7c */ + uint32_t rsvd_7[32]; /* 0x80 - 0xff */ +} BIUCFG_Bac; + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff */ + BIUCFG_Cluster cluster[2]; /* 0x100 - 0x2ff */ + BIUCFG_Bac bac; /* 0x300 - 0x3ff */ + uint32_t rsvd1[192]; /* 0x400 - 0x6ff */ + BIUCFG_Aux aux; /* 0x700 - 0x7ff */ + uint32_t rsrvd2[512]; /* 0x800 - 0xfff */ + uint32_t TSO_CNTCR; /* 0x1000 */ + uint32_t rsvd2[2047]; /* 0x1004 - 0x2fff */ +} BIUCFG; + +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif + + + diff --git a/plat/bcm/include/bcm963xx/6813_map_part.h b/plat/bcm/include/bcm963xx/6813_map_part.h new file mode 100644 index 00000000..9f58e04f --- /dev/null +++ b/plat/bcm/include/bcm963xx/6813_map_part.h @@ -0,0 +1,503 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +Unless you and Broadcom execute a separate written software license +agreement governing use of this software, this software is licensed +to you under the terms of the GNU General Public License version 2 +(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, +with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and + to copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + +Not withstanding the above, under no circumstances may you combine +this software in any way with any other Broadcom software provided +under a license other than the GPL, without Broadcom's express prior +written consent. + +:> +*/ + +#ifndef __BCM6813_MAP_PART_H +#define __BCM6813_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define MEMC_PHYS_BASE 0x80040000 /* MC2 TOP */ +#define MEMC_SIZE 0x00040000 + +#define PMC_PHYS_BASE 0xffa00000 +#define PMC_SIZE 0x00200000 +#define PMC_OFFSET 0x00100000 +#define PROC_MON_OFFSET 0x00100000 +#define PMB_OFFSET 0x00120100 + + +/* Perf block base address and size */ +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x3500 +#define TIMR_OFFSET 0x0400 /* 64 bit timer registers */ +#define WDTIMR0_OFFSET 0x0480 +#define WDTIMR1_OFFSET 0x04c0 + + +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + +#define PMC_BASE (PMC_PHYS_BASE + PMC_OFFSET) +#define PROC_MON_BASE (PMC_PHYS_BASE + PROC_MON_OFFSET) +#define PMB_BASE (PMC_PHYS_BASE+ PMB_OFFSET) +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) + +#ifndef __ASSEMBLER__ +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + uint32 gpTmr0Ctl; /* 0x018 */ + uint32 gpTmr0Cnt; /* 0x01c */ + uint32 gpTmr1Ctl; /* 0x020 */ + uint32 gpTmr1Cnt; /* 0x024 */ + uint32 hostMboxIn; /* 0x028 */ + uint32 hostMboxOut; /* 0x02c */ + uint32 reserved[4]; /* 0x030 */ + uint32 dmaCtrl; /* 0x040 */ + uint32 dmaStatus; /* 0x044 */ + uint32 dma0_3FifoStatus; /* 0x048 */ + uint32 reserved1[4]; /* 0x04c */ + uint32 diagControl; /* 0x05c */ + uint32 diagHigh; /* 0x060 */ + uint32 diagLow; /* 0x064 */ + uint32 reserved8; /* 0x068 */ + uint32 addr1WndwMask; /* 0x06c */ + uint32 addr1WndwBaseIn; /* 0x070 */ + uint32 addr1WndwBaseOut; /* 0x074 */ + uint32 addr2WndwMask; /* 0x078 */ + uint32 addr2WndwBaseIn; /* 0x07c */ + uint32 addr2WndwBaseOut; /* 0x080 */ + uint32 scratch; /* 0x084 */ + uint32 reserved9; /* 0x088 */ + uint32 softResets; /* 0x08c */ + uint32 reserved2; /* 0x090 */ + uint32 m4keCoreStatus; /* 0x094 */ + uint32 reserved3; /* 0x098 */ + uint32 ubSlaveTimeout; /* 0x09c */ + uint32 diagEn; /* 0x0a0 */ + uint32 devTimeout; /* 0x0a4 */ + uint32 ubusErrorOutMask; /* 0x0a8 */ + uint32 diagCaptStopMask; /* 0x0ac */ + uint32 revId; /* 0x0b0 */ + uint32 reserved4[4]; /* 0x0b4 */ + uint32 diagCtrl; /* 0x0c4 */ + uint32 diagStat; /* 0x0c8 */ + uint32 diagMask; /* 0x0cc */ + uint32 diagRslt; /* 0x0d0 */ + uint32 diagCmp; /* 0x0d4 */ + uint32 diagCapt; /* 0x0d8 */ + uint32 diagCnt; /* 0x0dc */ + uint32 diagEdgeCnt; /* 0x0e0 */ + uint32 reserved5[4]; /* 0x0e4 */ + uint32 smisc_bus_config; /* 0x0f4 */ + uint32 lfsr; /* 0x0f8 */ + uint32 dqm_pac_lock; /* 0x0fc */ + uint32 l1_irq_4ke_mask; /* 0x100 */ + uint32 l1_irq_4ke_status; /* 0x104 */ + uint32 l1_irq_mips_mask; /* 0x108 */ + uint32 l1_irq_mips_status; /* 0x10c */ + uint32 l1_irq_mips1_mask; /* 0x110 */ + uint32 reserved6[3]; /* 0x114 */ + uint32 l2_irq_gp_mask; /* 0x120 */ + uint32 l2_irq_gp_status; /* 0x124 */ + uint32 l2_irq_gp_set; /* 0x128 */ + uint32 reserved7; /* 0x12c */ + uint32 gp_in_irq_mask; /* 0x130 */ + uint32 gp_in_irq_status; /* 0x134 */ + uint32 gp_in_irq_set; /* 0x138 */ + uint32 gp_in_irq_sense; /* 0x13c */ + uint32 gp_in; /* 0x140 */ + uint32 gp_out; /* 0x144 */ +} PmcCtrlReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + uint32 freqScalarCtrl; /* 0x3c */ + uint32 freqScalarMask; /* 0x40 */ +} PmcPerfPowReg; + +typedef struct PmcDQMPac { + uint32 dqmPac[32]; +} PmcDQMPac; + +typedef struct PmcDQMReg { + uint32 cfg; /* 0x1c00 */ + uint32 _4keLowWtmkIrqMask; /* 0x1c04 */ + uint32 mipsLowWtmkIrqMask; /* 0x1c08 */ + uint32 lowWtmkIrqMask; /* 0x1c0c */ + uint32 _4keNotEmptyIrqMask; /* 0x1c10 */ + uint32 mipsNotEmptyIrqMask; /* 0x1c14 */ + uint32 notEmptyIrqSts; /* 0x1c18 */ + uint32 queueRst; /* 0x1c1c */ + uint32 notEmptySts; /* 0x1c20 */ + uint32 nextAvailMask; /* 0x1c24 */ + uint32 nextAvailQueue; /* 0x1c28 */ + uint32 mips1LowWtmkIrqMask; /* 0x1c2c */ + uint32 mips1NotEmptyIrqMask; /* 0x1c30 */ + uint32 autoSrcPidInsert; /* 0x1c34 */ + uint32 timerIrqStatus; /* 0x1c38 */ + uint32 timerStatus; /* 0x1c3c */ + uint32 _4keTimerIrqMask; /* 0x1c40 */ + uint32 mipsTimerIrqMask; /* 0x1c44 */ + uint32 mips1TimerIrqMask; /* 0x1c48 */ +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct SSBMaster { + uint32 ssbmControl; /* 0x0060 */ + uint32 ssbmWrData; /* 0x0064 */ + uint32 ssbmRdData; /* 0x0068 */ + uint32 ssbmStatus; /* 0x006c */ +} SSBMaster; + +typedef struct PmmReg { + uint32 memPowerCtrl; /* 0x0000 */ + uint32 regSecurityConfig; /* 0x0004 */ +} PmmReg; + +typedef struct keyholeReg { + uint32 ctrlSts; + uint32 wrData; + uint32 mutex; + uint32 rdData; +} keyholeReg; + +typedef struct PmbBus { + uint32 config; /* 0x0100 */ + uint32 arbiter; /* 0x0104 */ + uint32 timeout; /* 0x0108 */ + uint32 unused1; /* 0x010c */ + keyholeReg keyhole[4]; /* 0x0110-0x014f */ + uint32 unused2[44]; /* 0x0150-0x01ff */ + uint32 map[64]; /* 0x0200-0x02ff */ +}PmbBus; + +typedef struct CoreCtrl { + uint32 coreEnable; /* 0x0400 */ + uint32 autoresetControl; /* 0x0404 */ + uint32 coreIdle; /* 0x0408 */ + uint32 coreResetCause; /* 0x040c */ + uint32 memPwrDownCtrl0; /* 0x0410 */ + uint32 memPwrDownSts0; /* 0x0414 */ + uint32 memPwrDownCtrl1; /* 0x0418 */ + uint32 memPwrDownSts1; /* 0x041c */ + uint32 sysFlg0Status; /* 0x0420 */ + uint32 sysFlg0Set; /* 0x0424 */ + uint32 sysFlg0Clear; /* 0x0428 */ + uint32 unused1; /* 0x042c */ + uint32 usrFlg0Status; /* 0x0430 */ + uint32 usrFlg0Set; /* 0x0434 */ + uint32 usrFlg0Clear; /* 0x0438 */ + uint32 unused2; /* 0x043c */ + uint32 subsystemRev; /* 0x0440 */ + uint32 resetVector; /* 0x0444 */ +} CoreCtrl; + +typedef struct CoreState { + uint32 sysMbx[8]; /* 0x0480 */ + uint32 usrMbx[8]; /* 0x04a0 */ + uint32 sysMtx[4]; /* 0x04c0 */ + uint32 usrMtx[8]; /* 0x04d0 */ +} CoreState; + +typedef struct CoreIntr { + uint32 irqStatus; /* 0x0500 */ + uint32 irqSet; /* 0x0504 */ + uint32 irqClear; /* 0x0508 */ + uint32 unused1; /* 0x050c */ + uint32 srqStatus; /* 0x0510 */ + uint32 srqSet; /* 0x0514 */ + uint32 srqClear; /* 0x0518 */ + uint32 unused2; /* 0x051c */ + uint32 drqStatus; /* 0x0520 */ + uint32 drqSet; /* 0x0524 */ + uint32 drqClear; /* 0x0528 */ + uint32 unused3; /* 0x052c */ + uint32 frqStatus; /* 0x0530 */ + uint32 frqSet; /* 0x0534 */ + uint32 frqClear; /* 0x0538 */ + uint32 unused4; /* 0x053c */ + uint32 hostIrqLatched; /* 0x0540 */ + uint32 hostIrqSet; /* 0x0544 */ + uint32 hostIrqClear; /* 0x0548 */ + uint32 hostIrqEnable; /* 0x054c */ + uint32 obusFaultStatus; /* 0x0550 */ + uint32 obusFaultClear; /* 0x0554 */ + uint32 obusFaultAddr; /* 0x0558 */ +} CoreIntr; + +typedef struct CoreProfile { + uint32 mutex; /* 0x0580 */ + uint32 lastConfPcLo; /* 0x0584 */ + uint32 lastConfPcHi; /* 0x0588 */ + uint32 lastPcLo; /* 0x058c */ + uint32 lastPcHi; /* 0x0590 */ + uint32 braTargetPc0Lo; /* 0x0594 */ + uint32 braTargetPc0Hi; /* 0x0598 */ + uint32 braTargetPc1Lo; /* 0x059c */ + uint32 braTargetPc1Hi; /* 0x05a0 */ + uint32 braTargetPc2Lo; /* 0x05a4 */ + uint32 braTargetPc2Hi; /* 0x05a8 */ + uint32 braTargetPc3Lo; /* 0x05ac */ + uint32 braTargetPc3Hi; /* 0x05b0 */ + uint32 unused[3]; /* 0x05b4-0x05bf */ + uint32 profSampleW[4]; /* 0x05c0 */ +} CoreProfile; + +typedef struct MaestroMisc { + CoreCtrl coreCtrl; /* 0x0400 */ + uint32 unused1[14]; /* 0x0448-0x047f */ + CoreState coreState; /* 0x0480 */ + uint32 unused2[4]; /* 0x04f0-0x04ff */ + CoreIntr interrupt; /* 0x0500 */ + uint32 unused3[9]; /* 0x055c-0x057f */ + CoreProfile profile; /* 0x0580 */ +} MaestroMisc; + +typedef struct Pmc { + uint32 unused0[1030]; + PmcCtrlReg ctrl; /* 0x1018 */ + uint32 unused1[622]; /* 0x1148-0x1cff */ + PmcDQMPac dqmPac; /* 0x1b00 */ + uint32 unused5[32]; /* 0x1b80-0x1bff */ + PmcDQMReg dqm; /* 0x1c00 */ + uint32 unused6[749]; /* 0x1c4c-0x27ff */ + uint32 qStatus[32]; /* 0x2800 */ + uint32 unused7[480]; /* 0x2880-0x2fff */ + PmcDqmQMibReg qMib; /* 0x3000 */ + uint32 unused8[928]; /* 0x3180-0x3fff */ + PmcDqmQCtrlReg dqmQCtrl[8]; /* 0x4000 */ + uint32 unused9[992]; /* 0x4080-0x4fff */ + PmcDqmQDataReg dqmQData[8]; /* 0x5000 */ +} Pmc; +#define PMC ((volatile Pmc * const) PMC_BASE) + +typedef struct Procmon { + uint32 unused00[256]; + MaestroMisc maestroReg; /* 0x00400 */ + uint32 unused10[32396]; /* 0x005d0-0x1ffff */ + PmmReg pmm; /* 0x20000 */ + uint32 unused11[22]; /* 0x20008-0x2005f */ + SSBMaster ssbMasterCtrl; /* 0x20060 */ + uint32 unused12[36]; /* 0x20070-0x200ff */ + PmbBus pmb; /* 0x20100 */ + uint32 unused13[32576]; /* 0x20300-0x3ffff */ + uint32 qsm[128]; /* 0x40000-0x401ff */ + uint32 unused14[65408]; /* 0x40200-0x7ffff */ + uint32 dtcm[1024]; /* 0x80000-0x80fff */ + uint32 unused15[64512]; /* 0x81000-0xbffff */ + uint32 itcm[4096]; /* 0xc0000-0xc3fff */ +} Procmon; +#define PROCMON ((volatile Procmon * const) PROC_MON_BASE) + +typedef struct PMSSBMasterControl { + uint32 control; + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct +{ + uint32 control; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_BUS_SHIFT (20) +#define PMC_PMBM_Read (0 << 24) +#define PMC_PMBM_Write (1 << 24) + uint32 wr_data; + uint32 mutex; + uint32 rd_data; +} PMB_keyhole_reg; + +typedef struct PMBMaster { + uint32 config; +#define PMB_NUM_REGS_SHIFT (20) +#define PMB_NUM_REGS_MASK (0x3ff) + uint32 arbitger; + uint32 timeout; + uint32 reserved; + PMB_keyhole_reg keyhole[4]; + uint32 reserved1[44]; + uint32 map[64]; +} PMBMaster; +#define PMB ((volatile PMBMaster * const) PMB_BASE) + + +typedef struct WDTimer { + uint32 WatchDogDefCount; + /* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * Read from this register returns current watch dog count + */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 SoftRst; +#define SOFT_RESET 0x00000001 + uint32 WDAccessCtl; +} WDTimer; + +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + + +typedef struct BIUCFG_Access { + uint32 permission; /* 0x0 */ + uint32 sbox; /* 0x4 */ + uint32 cpu_defeature; /* 0x8 */ + uint32 dbg_security; /* 0xc */ + uint32 rsvd1[32]; /* 0x10 - 0x8f */ + uint64 violation[2]; /* 0x90 - 0x9f */ + uint32 ts_access[2]; /* 0xa0 - 0xa7 */ + uint32 rsvd2[22]; /* 0xa8 - 0xff */ +}BIUCFG_Access; + +typedef struct BIUCFG_Cluster { + uint32 permission; /* 0x0 */ + uint32 config; /* 0x4 */ + uint32 status; /* 0x8 */ + uint32 control; /* 0xc */ + uint32 cpucfg; /* 0x10 */ + uint32 dbgrom; /* 0x14 */ + uint32 rsvd1[2]; /* 0x18 - 0x1f */ + uint64 rvbar_addr[4]; /* 0x20 - 0x3f */ + uint32 rsvd2[48]; /* 0x40 - 0xff */ +}BIUCFG_Cluster; + +typedef struct BIUCFG_Bac { + uint32 bac_permission; /* 0x00 */ + uint32 bac_periphbase; /* 0x04 */ + uint32 rsvd[2]; /* 0x08 - 0x0f */ + uint32 bac_event; /* 0x10 */ + uint32 rsvd_1[3]; /* 0x14 - 0x1f */ + uint32 bac_ccicfg; /* 0x20 */ + uint32 bac_cciaddr; /* 0x24 */ + uint32 rsvd_2[4]; /* 0x28 - 0x37 */ + uint32 bac_ccievs2; /* 0x38 */ + uint32 bac_ccievs3; /* 0x3c */ + uint32 bac_ccievs4; /* 0x40 */ + uint32 rsvd_3[3]; /* 0x44 - 0x4f */ + uint32 bac_ccievm0; /* 0x50 */ + uint32 bac_ccievm1; /* 0x54 */ + uint32 rsvd_4[2]; /* 0x58 - 0x5f */ + uint32 bac_dapapbcfg; /* 0x60 */ + uint32 bac_status; /* 0x64 */ + uint32 rsvd_5[2]; /* 0x68 - 0x6f */ + uint32 cpu_therm_irq_cfg; /* 0x70 */ + uint32 cpu_therm_threshold_cfg; /* 0x74 */ + uint32 rsvd_6; /* 0x78 */ + uint32 cpu_therm_temp; /* 0x7c */ + uint32 rsvd_7[32]; /* 0x80 - 0xff */ +} BIUCFG_Bac; + +typedef struct BIUCFG_Aux { + uint32 aux_permission; /* 0x00 */ + uint32 rsvd[3]; /* 0x04 - 0x0f */ + uint32 c0_clk_control; /* 0x10 */ + uint32 c0_clk_ramp; /* 0x14 */ + uint32 c0_clk_pattern; /* 0x18 */ + uint32 rsvd_1; /* 0x1c */ + uint32 c1_clk_control; /* 0x20 */ + uint32 c1_clk_ramp; /* 0x24 */ + uint32 c1_clk_pattern; /* 0x28 */ + uint32 rsvd_2[53]; /* 0x2c - 0xff */ +} BIUCFG_Aux; + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff*/ + BIUCFG_Cluster cluster[2]; /* 0x100 - 0x2ff*/ + BIUCFG_Bac bac; /* 0x300 - 0x3ff */ + uint32 anonymous[192]; /* 0x400 - 0x6ff */ + BIUCFG_Aux aux; /* 0x700 - 0x7ff */ + uint32 anonymous_1[2560]; /* 0x800 - 0x2fff */ +}BIUCFG; + +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/plat/bcm/include/bcm963xx/6846_map_part.h b/plat/bcm/include/bcm963xx/6846_map_part.h new file mode 100755 index 00000000..a08e97c2 --- /dev/null +++ b/plat/bcm/include/bcm963xx/6846_map_part.h @@ -0,0 +1,489 @@ +/* +<:copyright-BRCM:2015:DUAL/GPL:standard + + Copyright (c) 2015 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> + +*/ + +#ifndef __BCM6846_MAP_PART_H +#define __BCM6846_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define MEMC_PHYS_BASE 0x80180000 +#define MEMC_SIZE 0x24000 + +#define PMC_PHYS_BASE 0xffb00000 +#define PMC_SIZE 0x6000 +#define PROC_MON_PHYS_BASE 0xffb20000 +#define PROC_MON_SIZE 0x1000 +#define PMB_OFFSET 0x0100 + +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x3000 +#define TIMR_OFFSET 0x0400 +#define WDTIMR0_OFFSET 0x0480 +#define WDTIMR1_OFFSET 0x04c0 + +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define BOOTLUT_PHYS_BASE 0xffff0000 +#define BOOTLUT_SIZE 0x1000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + +#define PMC_BASE (PMC_PHYS_BASE + 0) +#define PROC_MON_BASE (PROC_MON_PHYS_BASE + 0) +#define PMB_BASE (PROC_MON_PHYS_BASE + PMB_OFFSET) + +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) +#define TIMR_BASE (PERF_PHYS_BASE + TIMR_OFFSET) + +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) + +#ifndef __ASSEMBLER__ + +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + uint32 gpTmr0Ctl; /* 0x018 */ + uint32 gpTmr0Cnt; /* 0x01c */ + uint32 gpTmr1Ctl; /* 0x020 */ + uint32 gpTmr1Cnt; /* 0x024 */ + uint32 hostMboxIn; /* 0x028 */ + uint32 hostMboxOut; /* 0x02c */ + uint32 reserved[4]; /* 0x030 */ + uint32 dmaCtrl; /* 0x040 */ + uint32 dmaStatus; /* 0x044 */ + uint32 dma0_3FifoStatus; /* 0x048 */ + uint32 reserved1[4]; /* 0x04c */ + uint32 diagControl; /* 0x05c */ + uint32 diagHigh; /* 0x060 */ + uint32 diagLow; /* 0x064 */ + uint32 reserved8; /* 0x068 */ + uint32 addr1WndwMask; /* 0x06c */ + uint32 addr1WndwBaseIn; /* 0x070 */ + uint32 addr1WndwBaseOut; /* 0x074 */ + uint32 addr2WndwMask; /* 0x078 */ + uint32 addr2WndwBaseIn; /* 0x07c */ + uint32 addr2WndwBaseOut; /* 0x080 */ + uint32 scratch; /* 0x084 */ + uint32 reserved9; /* 0x088 */ + uint32 softResets; /* 0x08c */ + uint32 reserved2; /* 0x090 */ + uint32 m4keCoreStatus; /* 0x094 */ + uint32 reserved3; /* 0x098 */ + uint32 ubSlaveTimeout; /* 0x09c */ + uint32 diagEn; /* 0x0a0 */ + uint32 devTimeout; /* 0x0a4 */ + uint32 ubusErrorOutMask; /* 0x0a8 */ + uint32 diagCaptStopMask; /* 0x0ac */ + uint32 revId; /* 0x0b0 */ + uint32 gpTmr2Ctl; /* 0x0b4 */ + uint32 gpTmr2Cnt; /* 0x0b8 */ + uint32 reserved4[2]; /* 0x0bc */ + uint32 diagCtrl; /* 0x0c4 */ + uint32 diagStat; /* 0x0c8 */ + uint32 diagMask; /* 0x0cc */ + uint32 diagRslt; /* 0x0d0 */ + uint32 diagCmp; /* 0x0d4 */ + uint32 diagCapt; /* 0x0d8 */ + uint32 diagCnt; /* 0x0dc */ + uint32 diagEdgeCnt; /* 0x0e0 */ + uint32 reserved5[4]; /* 0x0e4 */ + uint32 smisc_bus_config; /* 0x0f4 */ + uint32 lfsr; /* 0x0f8 */ + uint32 dqm_pac_lock; /* 0x0fc */ + uint32 l1_irq_4ke_mask; /* 0x100 */ + uint32 l1_irq_4ke_status; /* 0x104 */ + uint32 l1_irq_mips_mask; /* 0x108 */ + uint32 l1_irq_mips_status; /* 0x10c */ + uint32 l1_irq_mips1_mask; /* 0x110 */ + uint32 reserved6[3]; /* 0x114 */ + uint32 l2_irq_gp_mask; /* 0x120 */ + uint32 l2_irq_gp_status; /* 0x124 */ + uint32 l2_irq_gp_set; /* 0x128 */ + uint32 reserved7; /* 0x12c */ + uint32 gp_in_irq_mask; /* 0x130 */ + uint32 gp_in_irq_status; /* 0x134 */ + uint32 gp_in_irq_set; /* 0x138 */ + uint32 gp_in_irq_sense; /* 0x13c */ + uint32 gp_in; /* 0x140 */ + uint32 gp_out; /* 0x144 */ +} PmcCtrlReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + uint32 freqScalarCtrl; /* 0x3c */ + uint32 freqScalarMask; /* 0x40 */ +} PmcPerfPowReg; + +typedef struct PmcDQMPac { + uint32 dqmPac[32]; +} PmcDQMPac; + +typedef struct PmcDQMReg { + uint32 cfg; /* 0x1c00 */ + uint32 _4keLowWtmkIrqMask; /* 0x1c04 */ + uint32 mipsLowWtmkIrqMask; /* 0x1c08 */ + uint32 lowWtmkIrqMask; /* 0x1c0c */ + uint32 _4keNotEmptyIrqMask; /* 0x1c10 */ + uint32 mipsNotEmptyIrqMask; /* 0x1c14 */ + uint32 notEmptyIrqSts; /* 0x1c18 */ + uint32 queueRst; /* 0x1c1c */ + uint32 notEmptySts; /* 0x1c20 */ + uint32 nextAvailMask; /* 0x1c24 */ + uint32 nextAvailQueue; /* 0x1c28 */ + uint32 mips1LowWtmkIrqMask; /* 0x1c2c */ + uint32 mips1NotEmptyIrqMask; /* 0x1c30 */ + uint32 autoSrcPidInsert; /* 0x1c34 */ + uint32 timerIrqStatus; /* 0x1c38 */ + uint32 timerStatus; /* 0x1c3c */ + uint32 _4keTimerIrqMask; /* 0x1c40 */ + uint32 mipsTimerIrqMask; /* 0x1c44 */ + uint32 mips1TimerIrqMask; /* 0x1c48 */ +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct SSBMaster { + uint32 ssbmControl; /* 0x0060 */ + uint32 ssbmWrData; /* 0x0064 */ + uint32 ssbmRdData; /* 0x0068 */ + uint32 ssbmStatus; /* 0x006c */ +} SSBMaster; + +typedef struct PmmReg { + uint32 memPowerCtrl; /* 0x0000 */ + uint32 regSecurityConfig; /* 0x0004 */ +} PmmReg; + +typedef struct keyholeReg { + uint32 ctrlSts; + uint32 wrData; + uint32 mutex; + uint32 rdData; +} keyholeReg; + +typedef struct PmbBus { + uint32 config; /* 0x0100 */ + uint32 arbiter; /* 0x0104 */ + uint32 timeout; /* 0x0108 */ + uint32 unused1; /* 0x010c */ + keyholeReg keyhole[4]; /* 0x0110-0x014f */ + uint32 unused2[44]; /* 0x0150-0x01ff */ + uint32 map[64]; /* 0x0200-0x02ff */ +}PmbBus; + +typedef struct CoreCtrl { + uint32 coreEnable; /* 0x0400 */ + uint32 autoresetControl; /* 0x0404 */ + uint32 coreIdle; /* 0x0408 */ + uint32 coreResetCause; /* 0x040c */ + uint32 memPwrDownCtrl0; /* 0x0410 */ + uint32 memPwrDownSts0; /* 0x0414 */ + uint32 memPwrDownCtrl1; /* 0x0418 */ + uint32 memPwrDownSts1; /* 0x041c */ + uint32 sysFlg0Status; /* 0x0420 */ + uint32 sysFlg0Set; /* 0x0424 */ + uint32 sysFlg0Clear; /* 0x0428 */ + uint32 unused1; /* 0x042c */ + uint32 usrFlg0Status; /* 0x0430 */ + uint32 usrFlg0Set; /* 0x0434 */ + uint32 usrFlg0Clear; /* 0x0438 */ + uint32 unused2; /* 0x043c */ + uint32 subsystemRev; /* 0x0440 */ + uint32 resetVector; /* 0x0444 */ +} CoreCtrl; + +typedef struct CoreState { + uint32 sysMbx[8]; /* 0x0480 */ + uint32 usrMbx[8]; /* 0x04a0 */ + uint32 sysMtx[4]; /* 0x04c0 */ + uint32 usrMtx[8]; /* 0x04d0 */ +} CoreState; + +typedef struct CoreIntr { + uint32 irqStatus; /* 0x0500 */ + uint32 irqSet; /* 0x0504 */ + uint32 irqClear; /* 0x0508 */ + uint32 unused1; /* 0x050c */ + uint32 srqStatus; /* 0x0510 */ + uint32 srqSet; /* 0x0514 */ + uint32 srqClear; /* 0x0518 */ + uint32 unused2; /* 0x051c */ + uint32 drqStatus; /* 0x0520 */ + uint32 drqSet; /* 0x0524 */ + uint32 drqClear; /* 0x0528 */ + uint32 unused3; /* 0x052c */ + uint32 frqStatus; /* 0x0530 */ + uint32 frqSet; /* 0x0534 */ + uint32 frqClear; /* 0x0538 */ + uint32 unused4; /* 0x053c */ + uint32 hostIrqLatched; /* 0x0540 */ + uint32 hostIrqSet; /* 0x0544 */ + uint32 hostIrqClear; /* 0x0548 */ + uint32 hostIrqEnable; /* 0x054c */ + uint32 obusFaultStatus; /* 0x0550 */ + uint32 obusFaultClear; /* 0x0554 */ + uint32 obusFaultAddr; /* 0x0558 */ +} CoreIntr; + +typedef struct CoreProfile { + uint32 mutex; /* 0x0580 */ + uint32 lastConfPcLo; /* 0x0584 */ + uint32 lastConfPcHi; /* 0x0588 */ + uint32 lastPcLo; /* 0x058c */ + uint32 lastPcHi; /* 0x0590 */ + uint32 braTargetPc0Lo; /* 0x0594 */ + uint32 braTargetPc0Hi; /* 0x0598 */ + uint32 braTargetPc1Lo; /* 0x059c */ + uint32 braTargetPc1Hi; /* 0x05a0 */ + uint32 braTargetPc2Lo; /* 0x05a4 */ + uint32 braTargetPc2Hi; /* 0x05a8 */ + uint32 braTargetPc3Lo; /* 0x05ac */ + uint32 braTargetPc3Hi; /* 0x05b0 */ + uint32 unused[3]; /* 0x05b4-0x05bf */ + uint32 profSampleW[4]; /* 0x05c0 */ +} CoreProfile; + +typedef struct MaestroMisc { + CoreCtrl coreCtrl; /* 0x0400 */ + uint32 unused1[14]; /* 0x0448-0x047f */ + CoreState coreState; /* 0x0480 */ + uint32 unused2[4]; /* 0x04f0-0x04ff */ + CoreIntr interrupt; /* 0x0500 */ + uint32 unused3[9]; /* 0x055c-0x057f */ + CoreProfile profile; /* 0x0580 */ +} MaestroMisc; + +typedef struct Pmc { + uint32 baseReserved; /* 0x0000 */ + uint32 unused0[1029]; + PmcCtrlReg ctrl; /* 0x1018 */ + uint32 unused1[174]; /* 0x1148-0x13ff */ + PmcTokenReg token; /* 0x1400 */ + uint32 unused2[136]; /* 0x141c-0x163b */ + PmcPerfPowReg perfPower; /* 0x163c */ + uint32 unused3[175]; /* 0x1644-0x18ff */ + PmcCntReg hwCounter; /* 0x1900 */ + uint32 unused4[110]; /* 0x1948-0x1aff */ + PmcDQMPac dqmPac; /* 0x1b00 */ + uint32 unused5[32]; /* 0x1b80-0x1bff */ + PmcDQMReg dqm; /* 0x1c00 */ + uint32 unused6[749]; /* 0x1c4c-0x27ff */ + uint32 qStatus[32]; /* 0x2800 */ + uint32 unused7[480]; /* 0x2880-0x2fff */ + PmcDqmQMibReg qMib; /* 0x3000 */ + uint32 unused8[928]; /* 0x3180-0x3fff */ + PmcDqmQCtrlReg dqmQCtrl[8]; /* 0x4000 */ + uint32 unused9[992]; /* 0x4080-0x4fff */ + PmcDqmQDataReg dqmQData[8]; /* 0x5000 */ +} Pmc; +#define PMC ((volatile Pmc * const) PMC_BASE) + +typedef struct Procmon { + PmmReg pmm; /* 0x20000 */ + uint32 unused11[22]; /* 0x20008-0x2005f */ + SSBMaster ssbMasterCtrl; /* 0x20060 */ + uint32 unused12[36]; /* 0x20070-0x200ff */ + PmbBus pmb; /* 0x20100 */ + uint32 unused13[64]; /* 0x20300-0x203ff */ + MaestroMisc maestroReg; /* 0x20400 */ +} Procmon; +#define PROCMON ((volatile Procmon * const) PROC_MON_BASE) + +typedef struct PMSSBMasterControl { + uint32 control; + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct +{ + uint32 control; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_BUS_SHIFT (20) +#define PMC_PMBM_Read (0 << 24) +#define PMC_PMBM_Write (1 << 24) + uint32 wr_data; + uint32 mutex; + uint32 rd_data; +} PMB_keyhole_reg; + +typedef struct PMBMaster { + uint32 config; +#define PMB_NUM_REGS_SHIFT (20) +#define PMB_NUM_REGS_MASK (0x3ff) + uint32 arbitger; + uint32 timeout; + uint32 reserved; + PMB_keyhole_reg keyhole[4]; + uint32 reserved1[44]; + uint32 map[64]; +} PMBMaster; +#define PMB ((volatile PMBMaster * const) PMB_BASE) + +/* +** Timer +*/ +#define TIMER_64BIT +typedef struct Timer { + uint64 TimerCtl0; + uint64 TimerCtl1; + uint64 TimerCtl2; + uint64 TimerCtl3; +#define TIMERENABLE (1ULL << 63) +#define RSTCNTCLR (1ULL << 62) + uint64 TimerCnt0; + uint64 TimerCnt1; + uint64 TimerCnt2; + uint64 TimerCnt3; +#define TIMER_COUNT_MASK 0x3FFFFFFFFFFFFFFFULL + uint32 TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 +#define TIMER3EN 0x08 + uint32 TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define TIMER3 0x08 + uint32 ResetReason; +#define SW_INI_RESET 0x00000001 + uint32 spare[3]; +} Timer; + +typedef struct WDTimer { + uint32 WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * * * Read from this register returns current watch dog count + * * */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 SoftRst; +#define SOFT_RESET 0x00000001 + uint32 WDAccessCtl; +} WDTimer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + +typedef struct BIUCFG_Access { + uint32 permission; /* 0x0 */ + uint32 sbox; /* 0x4 */ + uint32 cpu_defeature; /* 0x8 */ + uint32 dbg_security; /* 0xc */ + uint32 rsvd1[32]; /* 0x10 - 0x8f */ + uint64 violation[2]; /* 0x90 - 0x9f */ + uint32 ts_access[2]; /* 0xa0 - 0xa7 */ + uint32 rsvd2[22]; /* 0xa8 - 0xff */ +}BIUCFG_Access; + + +typedef struct BIUCFG_Cluster { + uint32 permission; /* 0x0 */ + uint32 config; /* 0x4 */ + uint32 status; /* 0x8 */ + uint32 control; /* 0xc */ + uint32 cpucfg; /* 0x10 */ + uint32 dbgrom; /* 0x14 */ + uint32 rsvd1[2]; /* 0x18 - 0x1f */ + uint64 rvbar_addr[4]; /* 0x20 - 0x3f */ + uint32 rsvd2[48]; /* 0x40 - 0xff */ +}BIUCFG_Cluster; + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff*/ + BIUCFG_Cluster cluster[2]; /* 0x100 - 0x2ff*/ + uint32 anonymous[2880]; /* 0x300 - 0x2fff*/ +}BIUCFG; +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/plat/bcm/include/bcm963xx/6855_map_part.h b/plat/bcm/include/bcm963xx/6855_map_part.h new file mode 100755 index 00000000..9d5d1f0c --- /dev/null +++ b/plat/bcm/include/bcm963xx/6855_map_part.h @@ -0,0 +1,307 @@ +/* +<:copyright-BRCM:2015:DUAL/GPL:standard + + Copyright (c) 2015 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> + +*/ + +#ifndef __BCM6855_MAP_PART_H +#define __BCM6855_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define MEMC_PHYS_BASE 0x80180000 +#define MEMC_SIZE 0x24000 + +#define PMC_PHYS_BASE 0xffb20000 +#define PMC_SIZE 0x1000 +#define PMB_OFFSET 0x100 + +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x14000 +#define TIMR_OFFSET 0x0400 +#define WDTIMR0_OFFSET 0x0480 +#define WDTIMR1_OFFSET 0x04c0 + +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define BOOTLUT_PHYS_BASE 0xffff0000 +#define BOOTLUT_SIZE 0x1000 + + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + + +#define PMC_BASE (PMC_PHYS_BASE + 0) +#define PMB_BASE (PMC_PHYS_BASE + PMB_OFFSET) + +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) +#define TIMR_BASE (PERF_PHYS_BASE + TIMR_OFFSET) +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) + +#ifndef __ASSEMBLER__ + +/* + * Power Management Control + */ + +typedef union +{ + struct + { + uint32 propagate_to_err : 1; // [00:00] -+ + uint32 propagate_slv_err : 1; // [01:01] | - these are potentially dangerous and MAY cause a system crash + uint32 pmbus_reset_n : 1; // [02:02] -+ + uint32 reserved0 : 1; // [03:03] + uint32 maxPmbIdx : 3; // [06:04] 0-based (0-7) + uint32 reserved1 : 1; // [07:07] + uint32 maxClientId : 12; // [19:08] 0-based (theoreticaly 0-4095, but code limits this to 256 devices - 0-255) + uint32 numRegsPerClient : 10; // [29:20] some power of 2 - number of 32-bit registers in each client (max = 512) + uint32 startDiscovery : 1; // [30:30] kicks off H/W discovery of clients and fills in the map (see PMB_REGS below) + uint32 discoveryBusy : 1; // [31:31] whether or not H/W discovery is still busy creating the map + } Bits; + uint32 Reg32; +} PMB_CONFIG_REG; + +typedef union +{ + struct { + uint32 data : 16; // [15:00] + uint32 reserved1 : 16; // [31:16] + } Bits; + uint32 Reg32; +} SSBM_data_reg; + +typedef union +{ + struct { + uint32 ssb_addr : 10; // [09:00] + uint32 ssb_cmd : 2; // [11:10] + uint32 ssb_en : 1; // [12:12] + uint32 ssb_add_pre : 1; // [13:13] + uint32 reserved2 : 1; // [14:14] + uint32 ssb_start : 1; // [15:15] + uint32 reserved1 : 16; // [31:16] + } Bits; + uint32 Reg32; +} SSBM_control_reg; + +typedef union +{ + struct { + uint32 busy : 1; // [00:00] + uint32 reserved1 : 31; // [31:01] + } Bits; + uint32 Reg32; +} SSBM_status_reg; + +typedef union +{ + struct { + uint32 swreg_th_lo : 8; // [07:00] + uint32 swreg_th_hi : 8; // [15:08] + uint32 reserved :16; // [31:16] + } Bits; + uint32 Reg32; +} SSBM_SWREG_th_hilo_reg; + + +typedef union +{ + struct { + uint32 ssb_lock_addr : 10; // [09:00] + uint32 lock_bit : 1; // [10:10] + uint32 lock_mode : 1; // [11:11] + uint32 reserved : 20; // [31:12] + } Bits; + uint32 Reg32; +} SSBM_SWREG_lock_reg; + +#define kSSBWrite 0x01 +#define kSSBRead 0x02 +#define kSSBEn (1 << 12) +#define kSSBStart (1 << 15) + +typedef struct SSBMaster { + SSBM_control_reg ssbmControl; /* 0x0060 */ + SSBM_data_reg ssbmWrData; /* 0x0064 */ + SSBM_data_reg ssbmRdData; /* 0x0068 */ + SSBM_status_reg ssbmStatus; /* 0x006c */ + SSBM_SWREG_th_hilo_reg ssbmThHiLo; /* 0x0070 */ + SSBM_SWREG_lock_reg ssbmSwLock; /* 0x0074 */ +} SSBMaster; + +typedef struct PmmReg { + uint32 memPowerCtrl; /* 0x0000 */ + uint32 regSecurityConfig; /* 0x0004 */ +} PmmReg; + +typedef struct keyholeReg { + uint32 ctrlSts; + uint32 wrData; + uint32 mutex; + uint32 rdData; +} keyholeReg; + +typedef struct PmbBus { + PMB_CONFIG_REG config; /* 0x0100 */ + uint32 arbiter; /* 0x0104 */ + uint32 timeout; /* 0x0108 */ + uint32 unused1; /* 0x010c */ + keyholeReg keyhole[4]; /* 0x0110-0x014f */ + uint32 unused2[44]; /* 0x0150-0x01ff */ + uint32 map[64]; /* 0x0200-0x02ff */ +}PmbBus; + +typedef struct Pmc { + PmmReg pmm; /* 0x20000 */ + uint32 unused11[22]; /* 0x20008-0x2005f */ + SSBMaster ssbMasterCtrl; /* 0x20060-0x20077 */ + uint32 unused12[34]; /* 0x20078-0x200ff */ + PmbBus pmb; /* 0x20100 */ +} Pmc; +#define PMC ((volatile Pmc * const) PMC_BASE) + +typedef struct +{ + uint32 control; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_BUS_SHIFT (20) +#define PMC_PMBM_Read (0 << 24) +#define PMC_PMBM_Write (1 << 24) + uint32 wr_data; + uint32 mutex; + uint32 rd_data; +} PMB_keyhole_reg; + +typedef struct PMBMaster { + uint32 config; +#define PMB_NUM_REGS_SHIFT (20) +#define PMB_NUM_REGS_MASK (0x3ff) + uint32 arbitger; + uint32 timeout; + uint32 reserved; + PMB_keyhole_reg keyhole[4]; + uint32 reserved1[44]; + uint32 map[64]; +} PMBMaster; +#define PMB ((volatile PMBMaster * const) PMB_BASE) + +/* +** Timer +*/ +#define TIMER_64BIT +typedef struct Timer { + uint64 TimerCtl0; + uint64 TimerCtl1; + uint64 TimerCtl2; + uint64 TimerCtl3; +#define TIMERENABLE (1ULL << 63) +#define RSTCNTCLR (1ULL << 62) + uint64 TimerCnt0; + uint64 TimerCnt1; + uint64 TimerCnt2; + uint64 TimerCnt3; +#define TIMER_COUNT_MASK 0x3FFFFFFFFFFFFFFFULL + uint32 TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 +#define TIMER3EN 0x08 + uint32 TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define TIMER3 0x08 + uint32 ResetReason; +#define SW_INI_RESET 0x00000001 + uint32 spare[3]; +} Timer; + +typedef struct WDTimer { + uint32 WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * * * Read from this register returns current watch dog count + * * */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 WDTimerCtl; +#define SOFT_RESET 0x00000001 + uint32 WDAccessCtl; +} WDTimer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + +typedef struct BIUCFG_Access { + uint32 permission; /* 0x0 */ + uint32 revd0; /* 0x4 */ + uint32 cpu_defeature; /* 0x8 */ + uint32 dbg_security; /* 0xc */ + uint32 rsvd1[36]; /* 0x10 - 0x9f */ + uint32 ts_access; /* 0xa0 - 0xa3 */ + uint32 rsvd2[23]; /* 0xa4 - 0xff */ +}BIUCFG_Access; + + +typedef struct BIUCFG_Cluster { + uint32 permission; /* 0x0 */ + uint32 config; /* 0x4 */ + uint32 status; /* 0x8 */ + uint32 control; /* 0xc */ + uint32 cpucfg; /* 0x10 */ + uint32 dbgrom; /* 0x14 */ + uint32 rsvd1[2]; /* 0x18 - 0x1f */ + uint64 rvbar_addr[4]; /* 0x20 - 0x3f */ + uint32 rsvd2[48]; /* 0x40 - 0xff */ +}BIUCFG_Cluster; + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff*/ + BIUCFG_Cluster cluster[2]; /* 0x100 - 0x2ff*/ + uint32 anonymous[2880]; /* 0x300 - 0x2fff*/ +}BIUCFG; +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/plat/bcm/include/bcm963xx/6856_map_part.h b/plat/bcm/include/bcm963xx/6856_map_part.h new file mode 100755 index 00000000..6c74f3cf --- /dev/null +++ b/plat/bcm/include/bcm963xx/6856_map_part.h @@ -0,0 +1,517 @@ +/* +<:copyright-BRCM:2015:DUAL/GPL:standard + + Copyright (c) 2015 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> + +*/ + +#ifndef __BCM6856_MAP_PART_H +#define __BCM6856_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define MEMC_PHYS_BASE 0x80180000 +#define MEMC_SIZE 0x24000 + +#define PMC_PHYS_BASE 0xffb00000 +#define PMC_SIZE 0x6000 +#define PROC_MON_PHYS_BASE 0xffb20000 +#define PROC_MON_SIZE 0x1000 +#define PMB_OFFSET 0x0100 + +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x3000 +#define TIMR_OFFSET 0x0400 +#define WDTIMR0_OFFSET 0x0480 +#define WDTIMR1_OFFSET 0x04c0 + +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + + +#define PMC_BASE (PMC_PHYS_BASE + 0) +#define PROC_MON_BASE (PROC_MON_PHYS_BASE + 0) +#define PMB_BASE (PROC_MON_PHYS_BASE + PMB_OFFSET) + +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) +#define TIMR_BASE (PERF_PHYS_BASE + TIMR_OFFSET) +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) + +#ifndef __ASSEMBLER__ +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + uint32 gpTmr0Ctl; /* 0x018 */ + uint32 gpTmr0Cnt; /* 0x01c */ + uint32 gpTmr1Ctl; /* 0x020 */ + uint32 gpTmr1Cnt; /* 0x024 */ + uint32 hostMboxIn; /* 0x028 */ + uint32 hostMboxOut; /* 0x02c */ + uint32 reserved[4]; /* 0x030 */ + uint32 dmaCtrl; /* 0x040 */ + uint32 dmaStatus; /* 0x044 */ + uint32 dma0_3FifoStatus; /* 0x048 */ + uint32 reserved1[4]; /* 0x04c */ + uint32 diagControl; /* 0x05c */ + uint32 diagHigh; /* 0x060 */ + uint32 diagLow; /* 0x064 */ + uint32 reserved8; /* 0x068 */ + uint32 addr1WndwMask; /* 0x06c */ + uint32 addr1WndwBaseIn; /* 0x070 */ + uint32 addr1WndwBaseOut; /* 0x074 */ + uint32 addr2WndwMask; /* 0x078 */ + uint32 addr2WndwBaseIn; /* 0x07c */ + uint32 addr2WndwBaseOut; /* 0x080 */ + uint32 scratch; /* 0x084 */ + uint32 reserved9; /* 0x088 */ + uint32 softResets; /* 0x08c */ + uint32 reserved2; /* 0x090 */ + uint32 m4keCoreStatus; /* 0x094 */ + uint32 reserved3; /* 0x098 */ + uint32 ubSlaveTimeout; /* 0x09c */ + uint32 diagEn; /* 0x0a0 */ + uint32 devTimeout; /* 0x0a4 */ + uint32 ubusErrorOutMask; /* 0x0a8 */ + uint32 diagCaptStopMask; /* 0x0ac */ + uint32 revId; /* 0x0b0 */ + uint32 gpTmr2Ctl; /* 0x0b4 */ + uint32 gpTmr2Cnt; /* 0x0b8 */ + uint32 reserved4[2]; /* 0x0bc */ + uint32 diagCtrl; /* 0x0c4 */ + uint32 diagStat; /* 0x0c8 */ + uint32 diagMask; /* 0x0cc */ + uint32 diagRslt; /* 0x0d0 */ + uint32 diagCmp; /* 0x0d4 */ + uint32 diagCapt; /* 0x0d8 */ + uint32 diagCnt; /* 0x0dc */ + uint32 diagEdgeCnt; /* 0x0e0 */ + uint32 reserved5[4]; /* 0x0e4 */ + uint32 smisc_bus_config; /* 0x0f4 */ + uint32 lfsr; /* 0x0f8 */ + uint32 dqm_pac_lock; /* 0x0fc */ + uint32 l1_irq_4ke_mask; /* 0x100 */ + uint32 l1_irq_4ke_status; /* 0x104 */ + uint32 l1_irq_mips_mask; /* 0x108 */ + uint32 l1_irq_mips_status; /* 0x10c */ + uint32 l1_irq_mips1_mask; /* 0x110 */ + uint32 reserved6[3]; /* 0x114 */ + uint32 l2_irq_gp_mask; /* 0x120 */ + uint32 l2_irq_gp_status; /* 0x124 */ + uint32 l2_irq_gp_set; /* 0x128 */ + uint32 reserved7; /* 0x12c */ + uint32 gp_in_irq_mask; /* 0x130 */ + uint32 gp_in_irq_status; /* 0x134 */ + uint32 gp_in_irq_set; /* 0x138 */ + uint32 gp_in_irq_sense; /* 0x13c */ + uint32 gp_in; /* 0x140 */ + uint32 gp_out; /* 0x144 */ +} PmcCtrlReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + uint32 freqScalarCtrl; /* 0x3c */ + uint32 freqScalarMask; /* 0x40 */ +} PmcPerfPowReg; + +typedef struct PmcDQMPac { + uint32 dqmPac[32]; +} PmcDQMPac; + +typedef struct PmcDQMReg { + uint32 cfg; /* 0x1c00 */ + uint32 _4keLowWtmkIrqMask; /* 0x1c04 */ + uint32 mipsLowWtmkIrqMask; /* 0x1c08 */ + uint32 lowWtmkIrqMask; /* 0x1c0c */ + uint32 _4keNotEmptyIrqMask; /* 0x1c10 */ + uint32 mipsNotEmptyIrqMask; /* 0x1c14 */ + uint32 notEmptyIrqSts; /* 0x1c18 */ + uint32 queueRst; /* 0x1c1c */ + uint32 notEmptySts; /* 0x1c20 */ + uint32 nextAvailMask; /* 0x1c24 */ + uint32 nextAvailQueue; /* 0x1c28 */ + uint32 mips1LowWtmkIrqMask; /* 0x1c2c */ + uint32 mips1NotEmptyIrqMask; /* 0x1c30 */ + uint32 autoSrcPidInsert; /* 0x1c34 */ + uint32 timerIrqStatus; /* 0x1c38 */ + uint32 timerStatus; /* 0x1c3c */ + uint32 _4keTimerIrqMask; /* 0x1c40 */ + uint32 mipsTimerIrqMask; /* 0x1c44 */ + uint32 mips1TimerIrqMask; /* 0x1c48 */ +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct SSBMaster { + uint32 ssbmControl; /* 0x0060 */ + uint32 ssbmWrData; /* 0x0064 */ + uint32 ssbmRdData; /* 0x0068 */ + uint32 ssbmStatus; /* 0x006c */ +} SSBMaster; + +typedef struct PmmReg { + uint32 memPowerCtrl; /* 0x0000 */ + uint32 regSecurityConfig; /* 0x0004 */ +} PmmReg; + +typedef struct keyholeReg { + uint32 ctrlSts; + uint32 wrData; + uint32 mutex; + uint32 rdData; +} keyholeReg; + +typedef struct PmbBus { + uint32 config; /* 0x0100 */ + uint32 arbiter; /* 0x0104 */ + uint32 timeout; /* 0x0108 */ + uint32 unused1; /* 0x010c */ + keyholeReg keyhole[4]; /* 0x0110-0x014f */ + uint32 unused2[44]; /* 0x0150-0x01ff */ + uint32 map[64]; /* 0x0200-0x02ff */ +}PmbBus; + +typedef struct CoreCtrl { + uint32 coreEnable; /* 0x0400 */ + uint32 autoresetControl; /* 0x0404 */ + uint32 coreIdle; /* 0x0408 */ + uint32 coreResetCause; /* 0x040c */ + uint32 memPwrDownCtrl0; /* 0x0410 */ + uint32 memPwrDownSts0; /* 0x0414 */ + uint32 memPwrDownCtrl1; /* 0x0418 */ + uint32 memPwrDownSts1; /* 0x041c */ + uint32 sysFlg0Status; /* 0x0420 */ + uint32 sysFlg0Set; /* 0x0424 */ + uint32 sysFlg0Clear; /* 0x0428 */ + uint32 unused1; /* 0x042c */ + uint32 usrFlg0Status; /* 0x0430 */ + uint32 usrFlg0Set; /* 0x0434 */ + uint32 usrFlg0Clear; /* 0x0438 */ + uint32 unused2; /* 0x043c */ + uint32 subsystemRev; /* 0x0440 */ + uint32 resetVector; /* 0x0444 */ +} CoreCtrl; + +typedef struct CoreState { + uint32 sysMbx[8]; /* 0x0480 */ + uint32 usrMbx[8]; /* 0x04a0 */ + uint32 sysMtx[4]; /* 0x04c0 */ + uint32 usrMtx[8]; /* 0x04d0 */ +} CoreState; + +typedef struct CoreIntr { + uint32 irqStatus; /* 0x0500 */ + uint32 irqSet; /* 0x0504 */ + uint32 irqClear; /* 0x0508 */ + uint32 unused1; /* 0x050c */ + uint32 srqStatus; /* 0x0510 */ + uint32 srqSet; /* 0x0514 */ + uint32 srqClear; /* 0x0518 */ + uint32 unused2; /* 0x051c */ + uint32 drqStatus; /* 0x0520 */ + uint32 drqSet; /* 0x0524 */ + uint32 drqClear; /* 0x0528 */ + uint32 unused3; /* 0x052c */ + uint32 frqStatus; /* 0x0530 */ + uint32 frqSet; /* 0x0534 */ + uint32 frqClear; /* 0x0538 */ + uint32 unused4; /* 0x053c */ + uint32 hostIrqLatched; /* 0x0540 */ + uint32 hostIrqSet; /* 0x0544 */ + uint32 hostIrqClear; /* 0x0548 */ + uint32 hostIrqEnable; /* 0x054c */ + uint32 obusFaultStatus; /* 0x0550 */ + uint32 obusFaultClear; /* 0x0554 */ + uint32 obusFaultAddr; /* 0x0558 */ +} CoreIntr; + +typedef struct CoreProfile { + uint32 mutex; /* 0x0580 */ + uint32 lastConfPcLo; /* 0x0584 */ + uint32 lastConfPcHi; /* 0x0588 */ + uint32 lastPcLo; /* 0x058c */ + uint32 lastPcHi; /* 0x0590 */ + uint32 braTargetPc0Lo; /* 0x0594 */ + uint32 braTargetPc0Hi; /* 0x0598 */ + uint32 braTargetPc1Lo; /* 0x059c */ + uint32 braTargetPc1Hi; /* 0x05a0 */ + uint32 braTargetPc2Lo; /* 0x05a4 */ + uint32 braTargetPc2Hi; /* 0x05a8 */ + uint32 braTargetPc3Lo; /* 0x05ac */ + uint32 braTargetPc3Hi; /* 0x05b0 */ + uint32 unused[3]; /* 0x05b4-0x05bf */ + uint32 profSampleW[4]; /* 0x05c0 */ +} CoreProfile; + +typedef struct MaestroMisc { + CoreCtrl coreCtrl; /* 0x0400 */ + uint32 unused1[14]; /* 0x0448-0x047f */ + CoreState coreState; /* 0x0480 */ + uint32 unused2[4]; /* 0x04f0-0x04ff */ + CoreIntr interrupt; /* 0x0500 */ + uint32 unused3[9]; /* 0x055c-0x057f */ + CoreProfile profile; /* 0x0580 */ +} MaestroMisc; + +typedef struct Pmc { + uint32 baseReserved; /* 0x0000 */ + uint32 unused0[1029]; + PmcCtrlReg ctrl; /* 0x1018 */ + + uint32 unused1[174]; /* 0x1148-0x13ff */ + + PmcTokenReg token; /* 0x1400 */ + uint32 unused2[136]; /* 0x141c-0x163b */ + + PmcPerfPowReg perfPower; /* 0x163c */ + uint32 unused3[175]; /* 0x1644-0x18ff */ + + PmcCntReg hwCounter; /* 0x1900 */ + uint32 unused4[110]; /* 0x1948-0x1aff */ + + PmcDQMPac dqmPac; /* 0x1b00 */ + uint32 unused5[32]; /* 0x1b80-0x1bff */ + + PmcDQMReg dqm; /* 0x1c00 */ + uint32 unused6[749]; /* 0x1c4c-0x27ff */ + + uint32 qStatus[32]; /* 0x2800 */ + uint32 unused7[480]; /* 0x2880-0x2fff */ + + PmcDqmQMibReg qMib; /* 0x3000 */ + uint32 unused8[928]; /* 0x3180-0x3fff */ + + PmcDqmQCtrlReg dqmQCtrl[8]; /* 0x4000 */ + uint32 unused9[992]; /* 0x4080-0x4fff */ + + PmcDqmQDataReg dqmQData[8]; /* 0x5000 */ +} Pmc; +#define PMC ((volatile Pmc * const) PMC_BASE) + +typedef struct Procmon { + PmmReg pmm; /* 0x20000 */ + uint32 unused11[22]; /* 0x20008-0x2005f */ + + SSBMaster ssbMasterCtrl; /* 0x20060 */ + uint32 unused12[36]; /* 0x20070-0x200ff */ + + PmbBus pmb; /* 0x20100 */ + uint32 unused13[64]; /* 0x20300-0x203ff */ + + MaestroMisc maestroReg; /* 0x20400 */ +} Procmon; +#define PROCMON ((volatile Procmon * const) PROC_MON_BASE) + +typedef struct +{ + uint32 control; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_BUS_SHIFT (20) +#define PMC_PMBM_Read (0 << 24) +#define PMC_PMBM_Write (1 << 24) + uint32 wr_data; + uint32 mutex; + uint32 rd_data; +} PMB_keyhole_reg; + +typedef struct PMBMaster { + uint32 config; +#define PMB_NUM_REGS_SHIFT (20) +#define PMB_NUM_REGS_MASK (0x3ff) + uint32 arbitger; + uint32 timeout; + uint32 reserved; + PMB_keyhole_reg keyhole[4]; + uint32 reserved1[44]; + uint32 map[64]; +} PMBMaster; +#define PMB ((volatile PMBMaster * const) PMB_BASE) + +/* +** Timer +*/ + +#define TIMER_64BIT +typedef struct Timer { + uint64 TimerCtl0; + uint64 TimerCtl1; + uint64 TimerCtl2; + uint64 TimerCtl3; +#define TIMERENABLE (1ULL << 63) +#define RSTCNTCLR (1ULL << 62) + uint64 TimerCnt0; + uint64 TimerCnt1; + uint64 TimerCnt2; + uint64 TimerCnt3; +#define TIMER_COUNT_MASK 0x3FFFFFFFFFFFFFFFULL + uint32 TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 +#define TIMER3EN 0x08 + uint32 TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define TIMER3 0x08 + uint32 ResetStatus; +#define PCIE_RESET_STATUS 0x10000000 +#define SW_RESET_STATUS 0x20000000 +#define HW_RESET_STATUS 0x40000000 +#define POR_RESET_STATUS 0x80000000 +#define RESET_STATUS_MASK 0xF0000000 + uint32 ResetReason; +#define SW_INI_RESET 0x00000001 + uint32 spare[3]; +} Timer; + +typedef struct WDTimer { + uint32 WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * * Read from this register returns current watch dog count + * */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 SoftRst; +#define SOFT_RESET 0x00000001 + uint32 WDAccessCtl; +} WDTimer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + +typedef struct BIUCFG_Access { + uint32 permission; /* 0x0 */ + uint32 sbox; /* 0x4 */ + uint32 cpu_defeature; /* 0x8 */ + uint32 dbg_security; /* 0xc */ + uint32 rsvd1[32]; /* 0x10 - 0x8f */ + uint64 violation[2]; /* 0x90 - 0x9f */ + uint32 ts_access[2]; /* 0xa0 - 0xa7 */ + uint32 rsvd2[22]; /* 0xa8 - 0xff */ +}BIUCFG_Access; + +typedef struct BIUCFG_Cluster { + uint32 permission; /* 0x0 */ + uint32 config; /* 0x4 */ + uint32 status; /* 0x8 */ + uint32 control; /* 0xc */ + uint32 cpucfg; /* 0x10 */ + uint32 dbgrom; /* 0x14 */ + uint32 rsvd1[2]; /* 0x18 - 0x1f */ + uint64 rvbar_addr[4]; /* 0x20 - 0x3f */ + uint32 rsvd2[48]; /* 0x40 - 0xff */ +}BIUCFG_Cluster; + +typedef struct BIUCFG_AuxClkCtrl { + uint32 clk_control; /* 0x0 */ + uint32 clk_ramp; /* 0x4 */ + uint32 clk_pattern; /* 0x8 */ + uint32 rsvd; /* 0xC */ +} BIUCFG_AuxClkCtrl; + +typedef struct BIUCFG_Aux { + uint32 permission; /* 0 */ + uint32 rsvd1[3]; /* 0x04 - 0x0c */ + BIUCFG_AuxClkCtrl cluster_clkctrl[2]; /* 0x10 - 0x2c */ + uint32 rsvd2[52]; /* 0x30 - 0xFF */ +} BIUCFG_Aux; + + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff*/ + BIUCFG_Cluster cluster[1]; /* 0x100 - 0x1ff*/ + uint32 rsvd1[320]; /* 0x200 - 0x6ff */ + BIUCFG_Aux aux; /* 0x700 - 0x7ff */ + uint32 rsvd2[2560]; /* 0x800 - 0x2fff */ + +}BIUCFG; + +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/plat/bcm/include/bcm963xx/6858_map_part.h b/plat/bcm/include/bcm963xx/6858_map_part.h new file mode 100755 index 00000000..fd09161f --- /dev/null +++ b/plat/bcm/include/bcm963xx/6858_map_part.h @@ -0,0 +1,506 @@ +/* +<:copyright-BRCM:2015:DUAL/GPL:standard + + Copyright (c) 2015 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> + +*/ + +#ifndef __BCM6858_MAP_PART_H +#define __BCM6858_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define MEMC_PHYS_BASE 0x80180000 +#define MEMC_SIZE 0x24000 + +#define PMC_PHYS_BASE 0x80200000 +#define PMC_SIZE 0x5000 +#define PROC_MON_PHYS_BASE 0x80280000 +#define PROC_MON_SIZE 0x1000 + +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x3000 +#define TIMR_OFFSET 0x2700 +#define WDTIMR0_OFFSET 0x2780 +#define WDTIMR1_OFFSET 0x27c0 + +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + +#define PMC_BASE (PMC_PHYS_BASE + 0) +#define PROC_MON_BASE (PROC_MON_PHYS_BASE + 0) + +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) +#define TIMR_BASE (PERF_PHYS_BASE + TIMR_OFFSET) + +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) + +#ifndef __ASSEMBLER__ +/* + * Power Management Control + */ +typedef struct PmcCtrlReg { + /* 0x00 */ + uint32 l1Irq4keMask; + uint32 l1Irq4keStatus; + uint32 l1IrqMipsMask; + uint32 l1IrqMipsStatus; + /* 0x10 */ + uint32 l2IrqGpMask; + uint32 l2IrqGpStatus; + uint32 gpTmr0Ctl; + uint32 gpTmr0Cnt; + /* 0x20 */ + uint32 gpTmr1Ctl; + uint32 gpTmr1Cnt; + uint32 hostMboxIn; + uint32 hostMboxOut; + /* 0x30 */ +#define PMC_CTRL_GP_FLASH_BOOT_STALL 0x00000080 + uint32 gpOut; + uint32 gpIn; + uint32 gpInIrqMask; + uint32 gpInIrqStatus; + /* 0x40 */ + uint32 dmaCtrl; + uint32 dmaStatus; + uint32 dma0_3FifoStatus; + uint32 unused0[3]; /* 0x4c-0x57 */ + /* 0x58 */ + uint32 l1IrqMips1Mask; + uint32 diagControl; + /* 0x60 */ + uint32 diagHigh; + uint32 diagLow; + uint32 badAddr; + uint32 addr1WndwMask; + /* 0x70 */ + uint32 addr1WndwBaseIn; + uint32 addr1WndwBaseOut; + uint32 addr2WndwMask; + uint32 addr2WndwBaseIn; + /* 0x80 */ + uint32 addr2WndwBaseOut; + uint32 scratch; + uint32 tm; + uint32 softResets; + /* 0x90 */ + uint32 eb2ubusTimeout; + uint32 m4keCoreStatus; + uint32 gpInIrqSense; + uint32 ubSlaveTimeout; + /* 0xa0 */ + uint32 diagEn; + uint32 devTimeout; + uint32 ubusErrorOutMask; + uint32 diagCaptStopMask; + /* 0xb0 */ + uint32 revId; + uint32 gpTmr2Ctl; + uint32 gpTmr2Cnt; + uint32 legacyMode; + /* 0xc0 */ + uint32 smisbMonitor; + uint32 diagCtrl; + uint32 diagStat; + uint32 diagMask; + /* 0xd0 */ + uint32 diagRslt; + uint32 diagCmp; + uint32 diagCapt; + uint32 diagCnt; + /* 0xe0 */ + uint32 diagEdgeCnt; + uint32 unused1[4]; /* 0xe4-0xf3 */ + /* 0xf4 */ + uint32 iopPeriphBaseAddr; + uint32 lfsr; + uint32 unused2; /* 0xfc-0xff */ +} PmcCtrlReg; + +typedef struct PmcOutFifoReg { + uint32 msgCtrl; /* 0x00 */ + uint32 msgSts; /* 0x04 */ + uint32 unused[14]; /* 0x08-0x3f */ + uint32 msgData[16]; /* 0x40-0x7c */ +} PmcOutFifoReg; + +typedef struct PmcInFifoReg { + uint32 msgCtrl; /* 0x00 */ + uint32 msgSts; /* 0x04 */ + uint32 unused[13]; /* 0x08-0x3b */ + uint32 msgLast; /* 0x3c */ + uint32 msgData[16]; /* 0x40-0x7c */ +} PmcInFifoReg; + +typedef struct PmcDmaReg { + /* 0x00 */ + uint32 src; + uint32 dest; + uint32 cmdList; + uint32 lenCtl; + /* 0x10 */ + uint32 rsltSrc; + uint32 rsltDest; + uint32 rsltHcs; + uint32 rsltLenStat; +} PmcDmaReg; + +typedef struct PmcTokenReg { + /* 0x00 */ + uint32 bufSize; + uint32 bufBase; + uint32 idx2ptrIdx; + uint32 idx2ptrPtr; + /* 0x10 */ + uint32 unused[2]; + uint32 bufSize2; +} PmcTokenReg; + +typedef struct PmcPerfPowReg { + /* 0x00 */ + uint32 dcacheHit; + uint32 dcacheMiss; + uint32 icacheHit; + uint32 icacheMiss; + /* 0x10 */ + uint32 instnComplete; + uint32 wtbMerge; + uint32 wtbNoMerge; + uint32 itlbHit; + /* 0x20 */ + uint32 itlbMiss; + uint32 dtlbHit; + uint32 dtlbMiss; + uint32 jtlbHit; + /* 0x30 */ + uint32 jtlbMiss; + uint32 powerSubZone; + uint32 powerMemPda; + uint32 freqScalarCtrl; + /* 0x40 */ + uint32 freqScalarMask; +} PmcPerfPowReg; + +typedef struct PmcDQMReg { + /* 0x00 */ + uint32 cfg; + uint32 _4keLowWtmkIrqMask; + uint32 mipsLowWtmkIrqMask; + uint32 lowWtmkIrqMask; + /* 0x10 */ + uint32 _4keNotEmptyIrqMask; + uint32 mipsNotEmptyIrqMask; + uint32 notEmptyIrqSts; + uint32 queueRst; + /* 0x20 */ + uint32 notEmptySts; + uint32 nextAvailMask; + uint32 nextAvailQueue; + uint32 mips1LowWtmkIrqMask; + /* 0x30 */ + uint32 mips1NotEmptyIrqMask; + uint32 autoSrcPidInsert; +} PmcDQMReg; + +typedef struct PmcCntReg { + uint32 cntr[10]; + uint32 unused[6]; /* 0x28-0x3f */ + uint32 cntrIrqMask; + uint32 cntrIrqSts; +} PmcCntReg; + +typedef struct PmcDqmQCtrlReg { + uint32 size; + uint32 cfga; + uint32 cfgb; + uint32 cfgc; +} PmcDqmQCtrlReg; + +typedef struct PmcDqmQDataReg { + uint32 word[4]; +} PmcDqmQDataReg; + +typedef struct PmcDqmQMibReg { + uint32 qNumFull[32]; + uint32 qNumEmpty[32]; + uint32 qNumPushed[32]; +} PmcDqmQMibReg; + +typedef struct Pmc { + uint32 baseReserved; /* 0x0000 */ + uint32 unused0[1023]; + PmcCtrlReg ctrl; /* 0x1000 */ + + PmcOutFifoReg outFifo; /* 0x1100 */ + uint32 unused1[32]; /* 0x1180-0x11ff */ + PmcInFifoReg inFifo; /* 0x1200 */ + uint32 unused2[32]; /* 0x1280-0x12ff */ + + PmcDmaReg dma[2]; /* 0x1300 */ + uint32 unused3[48]; /* 0x1340-0x13ff */ + + PmcTokenReg token; /* 0x1400 */ + uint32 unused4[121]; /* 0x141c-0x15ff */ + + PmcPerfPowReg perfPower; /* 0x1600 */ + uint32 unused5[47]; /* 0x1644-0x16ff */ + + uint32 msgId[32]; /* 0x1700 */ + uint32 unused6[32]; /* 0x1780-0x17ff */ + + PmcDQMReg dqm; /* 0x1800 */ + uint32 unused7[50]; /* 0x1838-0x18ff */ + + PmcCntReg hwCounter; /* 0x1900 */ + uint32 unused8[46]; /* 0x1948-0x19ff */ + + PmcDqmQCtrlReg dqmQCtrl[32]; /* 0x1a00 */ + PmcDqmQDataReg dqmQData[32]; /* 0x1c00 */ + uint32 unused9[64]; /* 0x1e00-0x1eff */ + + uint32 qStatus[32]; /* 0x1f00 */ + uint32 unused10[32]; /* 0x1f80-0x1fff */ + + PmcDqmQMibReg qMib; /* 0x2000 */ + uint32 unused11[1952]; /* 0x2180-0x3ffff */ + + uint32 sharedMem[8192]; /* 0x4000-0xbffc */ +} Pmc; + +#define PMC ((volatile Pmc * const) PMC_BASE) + +/* + * Process Monitor Module + */ +typedef struct PMRingOscillatorControl { + uint32 control; + uint32 en_lo; + uint32 en_mid; + uint32 en_hi; + uint32 idle_lo; + uint32 idle_mid; + uint32 idle_hi; +} PMRingOscillatorControl; + +#define RCAL_0P25UM_HORZ 0 +#define RCAL_0P25UM_VERT 1 +#define RCAL_0P5UM_HORZ 2 +#define RCAL_0P5UM_VERT 3 +#define RCAL_1UM_HORZ 4 +#define RCAL_1UM_VERT 5 +#define PMMISC_RMON_EXT_REG ((RCAL_1UM_VERT + 1)/2) +#define PMMISC_RMON_VALID_MASK (0x1<<16) +typedef struct PMMiscControl { + uint32 gp_out; + uint32 clock_select; + uint32 unused[2]; + uint32 misc[4]; +} PMMiscControl; + +typedef struct PMSSBMasterControl { + uint32 control; + uint32 wr_data; + uint32 rd_data; +} PMSSBMasterControl; + +typedef struct PMEctrControl { + uint32 control; + uint32 interval; + uint32 thresh_lo; + uint32 thresh_hi; + uint32 count; +} PMEctrControl; + +typedef struct PMBMaster { + uint32 ctrl; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_Read (0 << 20) +#define PMC_PMBM_Write (1 << 20) + uint32 wr_data; + uint32 timeout; + uint32 rd_data; + uint32 unused[4]; +} PMBMaster; + +typedef struct PMAPVTMONControl { + uint32 control; + uint32 reserved; + uint32 cfg_lo; + uint32 cfg_hi; + uint32 data; + uint32 vref_data; + uint32 unused[2]; + uint32 ascan_cfg; + uint32 warn_temp; + uint32 reset_temp; + uint32 temp_value; + uint32 data1_value; + uint32 data2_value; + uint32 data3_value; +} PMAPVTMONControl; + +typedef struct PMUBUSCfg { + uint32 window[8]; + uint32 control; +} PMUBUSCfg; + +typedef struct ProcessMonitorRegs { + uint32 MonitorCtrl; /* 0x00 */ + uint32 unused0[7]; + PMRingOscillatorControl ROSC; /* 0x20 */ + uint32 unused1; + PMMiscControl Misc; /* 0x40 */ + PMSSBMasterControl SSBMaster; /* 0x60 */ + uint32 unused2[5]; + PMEctrControl Ectr; /* 0x80 */ + uint32 unused3[11]; + PMBMaster PMBM[2]; /* 0xc0 */ + PMAPVTMONControl APvtmonCtrl; /* 0x100 */ + uint32 unused4[9]; + PMUBUSCfg UBUSCfg; /* 0x160 */ +} ProcessMonitorRegs; + +#define PROCMON ((volatile ProcessMonitorRegs * const) PROC_MON_BASE) + + +/* +** Timer +*/ +#define TIMER_64BIT +typedef struct Timer { + uint64 TimerCtl0; + uint64 TimerCtl1; + uint64 TimerCtl2; + uint64 TimerCtl3; +#define TIMERENABLE (1ULL << 63) +#define RSTCNTCLR (1ULL << 62) + uint64 TimerCnt0; + uint64 TimerCnt1; + uint64 TimerCnt2; + uint64 TimerCnt3; +#define TIMER_COUNT_MASK 0x3FFFFFFFFFFFFFFFULL + uint32 TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 +#define TIMER3EN 0x08 + uint32 TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define TIMER3 0x08 + uint32 ResetStatus; +#define PCIE_RESET_STATUS 0x10000000 +#define SW_RESET_STATUS 0x20000000 +#define HW_RESET_STATUS 0x40000000 +#define POR_RESET_STATUS 0x80000000 +#define RESET_STATUS_MASK 0xF0000000 + uint32 ResetReason; +#define SW_INI_RESET 0x00000001 + uint32 spare[3]; +} Timer; + +typedef struct WDTimer { + uint32 WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * * Read from this register returns current watch dog count + * */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 SoftRst; +#define SOFT_RESET 0x00000001 + uint32 WDAccessCtl; +} WDTimer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + +typedef struct BIUCFG_Access { + uint32 permission; /* 0x0 */ + uint32 sbox; /* 0x4 */ + uint32 cpu_defeature; /* 0x8 */ + uint32 dbg_security; /* 0xc */ + uint32 rsvd1[32]; /* 0x10 - 0x8f */ + uint64 violation[2]; /* 0x90 - 0x9f */ + uint32 ts_access[2]; /* 0xa0 - 0xa7 */ + uint32 rsvd2[22]; /* 0xa8 - 0xff */ +}BIUCFG_Access; + +typedef struct BIUCFG_Cluster { + uint32 permission; /* 0x0 */ + uint32 config; /* 0x4 */ + uint32 status; /* 0x8 */ + uint32 control; /* 0xc */ + uint32 cpucfg; /* 0x10 */ + uint32 dbgrom; /* 0x14 */ + uint32 rsvd1[2]; /* 0x18 - 0x1f */ + uint32 rvbar_addr[4]; /* 0x20 - 0x2f */ + uint32 rsvd2[52]; /* 0x30 - 0xff */ +}BIUCFG_Cluster; + +typedef struct BIUCFG_AuxClkCtrl { + uint32 clk_control; /* 0x0 */ + uint32 clk_ramp; /* 0x4 */ + uint32 clk_pattern; /* 0x8 */ + uint32 rsvd; /* 0xC */ +} BIUCFG_AuxClkCtrl; + +typedef struct BIUCFG_Aux { + uint32 permission; /* 0 */ + uint32 rsvd1[3]; /* 0x04 - 0x0c */ + BIUCFG_AuxClkCtrl cluster_clkctrl[2]; /* 0x10 - 0x2c */ + uint32 rsvd2[52]; /* 0x30 - 0xFF */ +} BIUCFG_Aux; + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff*/ + BIUCFG_Cluster cluster[1]; /* 0x100 - 0x1ff*/ + uint32 rsvd1[320]; /* 0x200 - 0x6ff */ + BIUCFG_Aux aux; /* 0x700 - 0x7ff */ + uint32 rsvd2[2560]; /* 0x800 - 0x2fff */ + +}BIUCFG; +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + +#endif /* __ASSEMBLER__ */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/plat/bcm/include/bcm963xx/6878_map_part.h b/plat/bcm/include/bcm963xx/6878_map_part.h new file mode 100755 index 00000000..599aed06 --- /dev/null +++ b/plat/bcm/include/bcm963xx/6878_map_part.h @@ -0,0 +1,305 @@ +/* +<:copyright-BRCM:2015:DUAL/GPL:standard + + Copyright (c) 2015 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> + +*/ + +#ifndef __BCM6878_MAP_PART_H +#define __BCM6878_MAP_PART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bcmtypes.h" + +#define MEMC_PHYS_BASE 0x80180000 +#define MEMC_SIZE 0x24000 + +#define PMC_PHYS_BASE 0xffb20000 +#define PMC_SIZE 0x1000 +#define PMB_OFFSET 0x100 + +#define PERF_PHYS_BASE 0xff800000 +#define PERF_SIZE 0x13000 +#define TIMR_OFFSET 0x0400 +#define WDTIMR0_OFFSET 0x0480 +#define WDTIMR1_OFFSET 0x04c0 + +#define BIUCFG_PHYS_BASE 0x81060000 +#define BIUCFG_SIZE 0x3000 +#define BIUCFG_OFFSET 0x0000 + +#define BOOTLUT_PHYS_BASE 0xffff0000 +#define BOOTLUT_SIZE 0x1000 + +#define GIC_PHYS_BASE 0x81000000 +#define GIC_SIZE 0x10000 +#define GIC_OFFSET 0x0000 +#define GICD_OFFSET 0x1000 +#define GICC_OFFSET 0x2000 + +#define PMC_BASE (PMC_PHYS_BASE + 0) +#define PMB_BASE (PMC_PHYS_BASE + PMB_OFFSET) + +#define WDTIMR0_BASE (PERF_PHYS_BASE + WDTIMR0_OFFSET) +#define TIMR_BASE (PERF_PHYS_BASE + TIMR_OFFSET) + +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) + + +#ifndef __ASSEMBLER__ + +/* + * Power Management Control + */ + +typedef union +{ + struct + { + uint32 propagate_to_err : 1; // [00:00] -+ + uint32 propagate_slv_err : 1; // [01:01] | - these are potentially dangerous and MAY cause a system crash + uint32 pmbus_reset_n : 1; // [02:02] -+ + uint32 reserved0 : 1; // [03:03] + uint32 maxPmbIdx : 3; // [06:04] 0-based (0-7) + uint32 reserved1 : 1; // [07:07] + uint32 maxClientId : 12; // [19:08] 0-based (theoreticaly 0-4095, but code limits this to 256 devices - 0-255) + uint32 numRegsPerClient : 10; // [29:20] some power of 2 - number of 32-bit registers in each client (max = 512) + uint32 startDiscovery : 1; // [30:30] kicks off H/W discovery of clients and fills in the map (see PMB_REGS below) + uint32 discoveryBusy : 1; // [31:31] whether or not H/W discovery is still busy creating the map + } Bits; + uint32 Reg32; +} PMB_CONFIG_REG; + +typedef union +{ + struct { + uint32 data : 16; // [15:00] + uint32 reserved1 : 16; // [31:16] + } Bits; + uint32 Reg32; +} SSBM_data_reg; + +typedef union +{ + struct { + uint32 ssb_addr : 10; // [09:00] + uint32 ssb_cmd : 2; // [11:10] + uint32 ssb_en : 1; // [12:12] + uint32 ssb_add_pre : 1; // [13:13] + uint32 reserved2 : 1; // [14:14] + uint32 ssb_start : 1; // [15:15] + uint32 reserved1 : 16; // [31:16] + } Bits; + uint32 Reg32; +} SSBM_control_reg; + +typedef union +{ + struct { + uint32 busy : 1; // [00:00] + uint32 reserved1 : 31; // [31:01] + } Bits; + uint32 Reg32; +} SSBM_status_reg; + +typedef union +{ + struct { + uint32 swreg_th_lo : 8; // [07:00] + uint32 swreg_th_hi : 8; // [15:08] + uint32 reserved :16; // [31:16] + } Bits; + uint32 Reg32; +} SSBM_SWREG_th_hilo_reg; + +typedef union +{ + struct { + uint32 ssb_lock_addr : 10; // [09:00] + uint32 lock_bit : 1; // [10:10] + uint32 lock_mode : 1; // [11:11] + uint32 reserved : 20; // [31:12] + } Bits; + uint32 Reg32; +} SSBM_SWREG_lock_reg; + +#define kSSBWrite 0x01 +#define kSSBRead 0x02 +#define kSSBEn (1 << 12) +#define kSSBStart (1 << 15) + +typedef struct SSBMaster { + SSBM_control_reg ssbmControl; /* 0x0060 */ + SSBM_data_reg ssbmWrData; /* 0x0064 */ + SSBM_data_reg ssbmRdData; /* 0x0068 */ + SSBM_status_reg ssbmStatus; /* 0x006c */ + SSBM_SWREG_th_hilo_reg ssbmThHiLo; /* 0x0070 */ + SSBM_SWREG_lock_reg ssbmSwLock; /* 0x0074 */ +} SSBMaster; + +typedef struct PmmReg { + uint32 memPowerCtrl; /* 0x0000 */ + uint32 regSecurityConfig; /* 0x0004 */ +} PmmReg; + +typedef struct keyholeReg { + uint32 ctrlSts; + uint32 wrData; + uint32 mutex; + uint32 rdData; +} keyholeReg; + +typedef struct PmbBus { + PMB_CONFIG_REG config; /* 0x0100 */ + uint32 arbiter; /* 0x0104 */ + uint32 timeout; /* 0x0108 */ + uint32 unused1; /* 0x010c */ + keyholeReg keyhole[4]; /* 0x0110-0x014f */ + uint32 unused2[44]; /* 0x0150-0x01ff */ + uint32 map[64]; /* 0x0200-0x02ff */ +}PmbBus; + +typedef struct Pmc { + PmmReg pmm; /* 0x20000 */ + uint32 unused11[22]; /* 0x20008-0x2005f */ + SSBMaster ssbMasterCtrl; /* 0x20060-0x20077 */ + uint32 unused12[34]; /* 0x20078-0x200ff */ + PmbBus pmb; /* 0x20100 */ +} Pmc; +#define PMC ((volatile Pmc * const) PMC_BASE) + +typedef struct +{ + uint32 control; +#define PMC_PMBM_START (1 << 31) +#define PMC_PMBM_TIMEOUT (1 << 30) +#define PMC_PMBM_SLAVE_ERR (1 << 29) +#define PMC_PMBM_BUSY (1 << 28) +#define PMC_PMBM_BUS_SHIFT (20) +#define PMC_PMBM_Read (0 << 24) +#define PMC_PMBM_Write (1 << 24) + uint32 wr_data; + uint32 mutex; + uint32 rd_data; +} PMB_keyhole_reg; + +typedef struct PMBMaster { + uint32 config; +#define PMB_NUM_REGS_SHIFT (20) +#define PMB_NUM_REGS_MASK (0x3ff) + uint32 arbitger; + uint32 timeout; + uint32 reserved; + PMB_keyhole_reg keyhole[4]; + uint32 reserved1[44]; + uint32 map[64]; +} PMBMaster; +#define PMB ((volatile PMBMaster * const) PMB_BASE) + +/* +** Timer +*/ +#define TIMER_64BIT +typedef struct Timer { + uint64 TimerCtl0; + uint64 TimerCtl1; + uint64 TimerCtl2; + uint64 TimerCtl3; +#define TIMERENABLE (1ULL << 63) +#define RSTCNTCLR (1ULL << 62) + uint64 TimerCnt0; + uint64 TimerCnt1; + uint64 TimerCnt2; + uint64 TimerCnt3; +#define TIMER_COUNT_MASK 0x3FFFFFFFFFFFFFFFULL + uint32 TimerMask; +#define TIMER0EN 0x01 +#define TIMER1EN 0x02 +#define TIMER2EN 0x04 +#define TIMER3EN 0x08 + uint32 TimerInts; +#define TIMER0 0x01 +#define TIMER1 0x02 +#define TIMER2 0x04 +#define TIMER3 0x08 + uint32 ResetReason; +#define SW_INI_RESET 0x00000001 + uint32 spare[3]; +} Timer; + +typedef struct WDTimer { + uint32 WatchDogDefCount;/* Write 0xff00 0x00ff to Start timer + * Write 0xee00 0x00ee to Stop and re-load default count + * * * Read from this register returns current watch dog count + * * */ + uint32 WatchDogCtl; + + /* Number of 50-MHz ticks for WD Reset pulse to last */ + uint32 WDResetCount; + + uint32 WDTimerCtl; +#define SOFT_RESET 0x00000001 + uint32 WDAccessCtl; +} WDTimer; + +#define TIMER ((volatile Timer * const) TIMR_BASE) +#define WDTIMER0 ((volatile WDTimer * const) WDTIMR0_BASE) + +typedef struct BIUCFG_Access { + uint32 permission; /* 0x0 */ + uint32 revd0; /* 0x4 */ + uint32 cpu_defeature; /* 0x8 */ + uint32 dbg_security; /* 0xc */ + uint32 rsvd1[36]; /* 0x10 - 0x9f */ + uint32 ts_access; /* 0xa0 - 0xa3 */ + uint32 rsvd2[23]; /* 0xa4 - 0xff */ +}BIUCFG_Access; + + +typedef struct BIUCFG_Cluster { + uint32 permission; /* 0x0 */ + uint32 config; /* 0x4 */ + uint32 status; /* 0x8 */ + uint32 control; /* 0xc */ + uint32 cpucfg; /* 0x10 */ + uint32 dbgrom; /* 0x14 */ + uint32 rsvd1[2]; /* 0x18 - 0x1f */ + uint64 rvbar_addr[4]; /* 0x20 - 0x3f */ + uint32 rsvd2[48]; /* 0x40 - 0xff */ +}BIUCFG_Cluster; + +typedef struct BIUCFG { + BIUCFG_Access access; /* 0x0 - 0xff*/ + BIUCFG_Cluster cluster[2]; /* 0x100 - 0x2ff*/ + uint32 anonymous[2880]; /* 0x300 - 0x2fff*/ +}BIUCFG; +#define BIUCFG ((volatile BIUCFG * const) BIUCFG_BASE) + +#endif /* __ASSEMBLER__ */ + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/plat/bcm/include/bcm963xx/bcm_mem_reserve.h b/plat/bcm/include/bcm963xx/bcm_mem_reserve.h new file mode 100644 index 00000000..58a25030 --- /dev/null +++ b/plat/bcm/include/bcm963xx/bcm_mem_reserve.h @@ -0,0 +1,96 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> + +*/ +#ifndef _BCM_MEM_RESERVE_H +#define _BCM_MEM_RESERVE_H + + +/* Push DTB higher as it will be removed by Linux alter on */ +/* Address range Size(KB) + 0x00000000:0x00004000 16 to boot secondary ARM CPU + 0x00004000:0x000C0000 752 to keep ATF firmware + 0x000C0000:0x000F0000 192 to keep PMC firmware + 0x000F0000:0x00100000 64 to keep PMC firmware log + + Any change in the following defines must be reflected in Linux device tree (/memreserve) +*/ +#if defined(CONFIG_ARM64) +#define CFG_BOOT_AREA_ADDR 0 +#else +#define CFG_BOOT_AREA_ADDR 0x1000 +#define ARM_ATAG_LOC CFG_DTB_ADDRESS +#endif +#define CFG_BOOT_AREA_SIZE (0x4000 - CFG_BOOT_AREA_ADDR) + +/* ATF reserved memory */ +#define CFG_ATF_AREA_ADDR (CFG_BOOT_AREA_ADDR + CFG_BOOT_AREA_SIZE) +#define CFG_ATF_AREA_SIZE 0xBC000 // Total ATF reserved memory size 752KB + +/* PMC reserved memory */ +#define PMC_RESERVED_MEM_START (CFG_ATF_AREA_ADDR + CFG_ATF_AREA_SIZE) +#define PMC_RESERVED_MEM_SIZE 0x40000 // Total PMC reserved memory size 256KB + +#ifdef CONFIG_BCM963148 +/* Reuse unused PMC reserved memory for DSL */ +#define DSL_RESERVED_MEM_START PMC_RESERVED_MEM_START +#define DSL_RESERVED_MEM_SIZE PMC_RESERVED_MEM_SIZE +#endif + +#define CFG_BOOT_PMC_LOG_SIZE 0x10000 // Leave 64K reserved memory for PMC log +#define CFG_BOOT_PMC_ADDR (PMC_RESERVED_MEM_START) +#define CFG_BOOT_PMC_SIZE (PMC_RESERVED_MEM_SIZE - CFG_BOOT_PMC_LOG_SIZE) // Memory reserved for PMC firmware +#define CFG_BOOT_PMC_LOG_ADDR (PMC_RESERVED_MEM_START + CFG_BOOT_PMC_SIZE) + + +/* **NOTE** any change in CFG_BOOT_PMC_ADDR must be reflected in PMC makefiles */ + +/* OPTEE reserved memory */ +#define CFG_OPTEE_AREA_ADDR (PMC_RESERVED_MEM_START + PMC_RESERVED_MEM_SIZE) +#define CFG_OPTEE_CORE_SIZE 0x400000 // Total OPTEE reserved memory size 4096KB +#define CFG_OPTEE_SHRM_SIZE 0x100000 // Shared memory 1024KB between OPTEE and Linux +#define CFG_OPTEE_SHRM_ADDR (CFG_OPTEE_AREA_ADDR + CFG_OPTEE_CORE_SIZE) +#define CFG_OPTEE_AREA_SIZE (CFG_OPTEE_CORE_SIZE + CFG_OPTEE_SHRM_SIZE) + +#ifdef CONFIG_OPTEE +#define CFG_MAX_RESV_AREA (CFG_OPTEE_AREA_ADDR + CFG_OPTEE_AREA_SIZE) +#else +#define CFG_MAX_RESV_AREA (PMC_RESERVED_MEM_START + PMC_RESERVED_MEM_SIZE) +#endif + +#if ( CFG_MAX_RESV_AREA > 0x600000 ) +#error "Reserved memory exceeded the allowed (6MB) limit" +#endif + + +#if ( CFG_MAX_RESV_AREA != 0x100000 ) && ( CFG_MAX_RESV_AREA != 0x600000 ) +#error "Time to update kernel/linux-4.x/arch/armxx/Makefile" +#endif + +#if defined(CONFIG_ARM64) +#define LINUX_START_ADDR CFG_MAX_RESV_AREA +#else +/* For 32 bit ARM, Linux needs extra 32K head room for MMU table */ +#define LINUX_START_ADDR (CFG_MAX_RESV_AREA + 0x8000) +#endif + +#endif /* _BCM_MEM_RESERVE_H */ diff --git a/plat/bcm/include/bcm963xx/bcmtypes.h b/plat/bcm/include/bcm963xx/bcmtypes.h new file mode 100644 index 00000000..3e71c66c --- /dev/null +++ b/plat/bcm/include/bcm963xx/bcmtypes.h @@ -0,0 +1,162 @@ +/* + Copyright 2007-2015 Broadcom Corporation + + <:label-BRCM:2015:DUAL/GPL:standard + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License, version 2, as published by + the Free Software Foundation (the "GPL"). + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + + A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by + writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + :> +*/ + +// +// bcmtypes.h - misc useful typedefs +// +#ifndef BCMTYPES_H +#define BCMTYPES_H + +#ifndef __ASSEMBLER__ + +// These are also defined in typedefs.h in the application area, so I need to +// protect against re-definition. + +#ifndef _TYPEDEFS_H_ + +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned int uint32; +typedef unsigned long long uint64; +typedef signed char int8; +typedef signed short int16; +typedef signed int int32; +typedef signed long long int64; +typedef unsigned long BcmHandle; + +#if !defined(__cplusplus) && !defined(__KERNEL__) && !defined(_LINUX_TYPES_H) && !defined(_LINUX_IF_H) && !defined(_ATF_) +typedef int bool; +#endif + +#endif + +typedef unsigned char byte; + +typedef unsigned long HANDLE,*PULONG; +typedef int DWORD,*PDWORD; +#ifndef LONG +typedef signed long LONG,*PLONG; +#endif + +typedef unsigned int *PUINT; +typedef signed int INT; + +typedef unsigned short *PUSHORT; +typedef signed short SHORT,*PSHORT; +typedef unsigned short WORD,*PWORD; + +typedef unsigned char *PUCHAR; +typedef signed char *PCHAR; + +typedef void *PVOID; + +typedef unsigned char BOOLEAN, *PBOOL, *PBOOLEAN; + +typedef unsigned char BYTE,*PBYTE; + +typedef signed int *PINT; + +#ifndef NUMBER_TYPES_ALREADY_DEFINED +#define NUMBER_TYPES_ALREADY_DEFINED +typedef signed char INT8; +typedef signed char SINT8; +typedef signed short INT16; +typedef signed short SINT16; +typedef signed int INT32; +typedef signed int sint32; +typedef signed int SINT32; +typedef signed long long SINT64; + +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef unsigned long long UINT64; +#endif + +#ifndef BOOL_TYPE_ALREADY_DEFINED +#define BOOL_TYPE_ALREADY_DEFINED +typedef unsigned char UBOOL8; +#endif + +#ifndef BASE_TYPE_ALREADY_DEFINED +#define BASE_TYPE_ALREADY_DEFINED +typedef unsigned char UCHAR; +typedef unsigned short USHORT; +typedef unsigned int UINT; +typedef unsigned long ULONG; +#endif + +typedef void VOID; +typedef unsigned char BOOL; + +// These are also defined in typedefs.h in the application area, so I need to +// protect against re-definition. +#ifndef TYPEDEFS_H + +// Maximum and minimum values for a signed 16 bit integer. +#define MAX_INT16 32767 +#define MIN_INT16 -32768 + +// Useful for true/false return values. This uses the +// Taligent notation (k for constant). +typedef enum +{ + kFalse = 0, + kTrue = 1 +} Bool; + +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#define READ32(addr) (*(volatile UINT32 *)((ULONG)&addr)) +#define READ16(addr) (*(volatile UINT16 *)((ULONG)&addr)) +#define READ8(addr) (*(volatile UINT8 *)((ULONG)&addr)) + +typedef unsigned long long uint64_aligned __attribute__((aligned(8))); +typedef signed long long int64_aligned __attribute__((aligned(8))); + +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ +#define BCM_IOC_PTR(ptr_t, ptr) union { ptr_t ptr; uint64_aligned ptr##64; } +#define BCM_IOC_PTR_ZERO_EXT(ptr) if (is_compat_task()) ((ptr##64) = (uint64_aligned)(uint32_t)(ptr##64)) +#else +#define BCM_IOC_PTR(ptr_t, ptr) ptr_t ptr; +#define BCM_IOC_PTR_ZERO_EXT(ptr) +#endif + +/*Example usage of above types/macro to a create 32/64-bit compatible ioctl message: + typedef struct { + uint8 exByte; + BCM_IOC_PTR(void*, exPtr); + uint32 exWord; /.Never use long. Always use (u)int32./ + uint64_aligned ex64bitValue; /.Never use long long. Always use (u)int64_aligned../ + } ExampleIoctlMsg; +*/ +#endif + +#endif diff --git a/plat/bcm/include/bcm_map_part.h b/plat/bcm/include/bcm_map_part.h new file mode 100644 index 00000000..85a79ba8 --- /dev/null +++ b/plat/bcm/include/bcm_map_part.h @@ -0,0 +1,69 @@ +/* + <:copyright-BRCM:2011:DUAL/GPL:standard + + Copyright (c) 2011 Broadcom + All Rights Reserved + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License, version 2, as published by + the Free Software Foundation (the "GPL"). + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + + A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by + writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. + + :> +*/ + +#ifndef __BCM_MAP_H +#define __BCM_MAP_H + +#if defined (_BCM963138_) +#include "63138_map_part.h" +#endif +#if defined (_BCM963148_) +#include "63148_map_part.h" +#endif +#if defined (_BCM94908_) +#include "4908_map_part.h" +#endif +#if defined (_BCM96858_) +#include "6858_map_part.h" +#endif +#if defined (_BCM947189_) +#include "47189_map_part.h" +#endif +#if defined (_BCM963158_) +#include "63158_map_part.h" +#endif +#if defined (_BCM96846_) +#include "6846_map_part.h" +#endif +#if defined (_BCM96856_) +#include "6856_map_part.h" +#endif +#if defined (_BCM963178_) +#include "63178_map_part.h" +#endif +#if defined (_BCM963146_) +#include "63146_map_part.h" +#endif +#if defined (_BCM947622_) +#include "47622_map_part.h" +#endif +#if defined (_BCM96878_) +#include "6878_map_part.h" +#endif +#if defined (_BCM94912_) +#include "4912_map_part.h" +#endif +#if defined (_BCM96756_) +#include "6756_map_part.h" +#endif +#endif diff --git a/plat/bcm/include/clk_rst.h b/plat/bcm/include/clk_rst.h new file mode 100644 index 00000000..be4d5bc7 --- /dev/null +++ b/plat/bcm/include/clk_rst.h @@ -0,0 +1,85 @@ +/* +<:copyright-BRCM:2013:DUAL/GPL:standard + + Copyright (c) 2013 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef CLK_RST_H +#define CLK_RST_H + +#ifndef IS_BCMCHIP +#define IS_BCMCHIP(num) (defined(_BCM9##num##_)||defined(CONFIG_BCM9##num)||\ + defined(CONFIG_BCM##num)) +#endif + +/* pll dividers */ +struct PLL_DIVIDERS { + unsigned int pdiv; + unsigned int ndiv_int; + unsigned int ndiv_frac; + unsigned int ka; + unsigned int ki; + unsigned int kp; +}; + +int pll_vco_freq_set(unsigned int pll_addr, struct PLL_DIVIDERS *divs); +int pll_ch_freq_set(unsigned int pll_addr, unsigned int ch, unsigned int mdiv); +int pll_ch_freq_get(unsigned int pll_addr, unsigned int ch, unsigned int *freq); +int ddr_freq_set(unsigned long freq); +int viper_freq_set(unsigned long freq); +int rdp_freq_set(unsigned long freq); +unsigned long get_rdp_freq(unsigned int *rdp_freq); +#if IS_BCMCHIP(6858) || IS_BCMCHIP(6856) || IS_BCMCHIP(6878) || IS_BCMCHIP(6855) +int pll_vco_freq_get(unsigned int pll_addr, unsigned int *fvco); +int pll_ch_freq_vco_set(unsigned int pll_addr, unsigned int ch, + unsigned int mdiv, unsigned int use_vco); +#endif + +#if IS_BCMCHIP(6855) +int pll_vco_config(unsigned int pll_addr, unsigned int ndivider, unsigned int pdivider); +#endif + +void set_vreg_clk(void); + +#if IS_BCMCHIP(6858) + +typedef enum { + BCM_CPU_CLK_HIGH, + BCM_CPU_CLK_LOW +} BCM_CPU_CLK; + +int bcm_change_cpu_clk(BCM_CPU_CLK clock); + +#endif + +#if IS_BCMCHIP(6858) || IS_BCMCHIP(6855) +#define XRDPPLL_RUNNER_CHANNEL 0 +#endif +#if IS_BCMCHIP(6856) || IS_BCMCHIP(6846) +#define XRDPPLL_RUNNER_CHANNEL 1 +#endif +#if IS_BCMCHIP(6878) +#define SYSPLL_RUNNER_CHANNEL 0 +#endif +#if IS_BCMCHIP(63158) +/* TBD. Verify value. */ +#define XRDPPLL_RUNNER_CHANNEL 1 +#endif +#endif /* #ifndef CLK_RST_H */ diff --git a/plat/bcm/include/command.h b/plat/bcm/include/command.h new file mode 100644 index 00000000..4c254937 --- /dev/null +++ b/plat/bcm/include/command.h @@ -0,0 +1,307 @@ +/* +<:copyright-BRCM:2013:DUAL/GPL:standard + + Copyright (c) 2013 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMCCOMMAND_H +#define PMCCOMMAND_H + +#include "pmc_drv.h" + +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t cmdID:8; + uint32_t error:8; + uint32_t msgID:8; + uint32_t srcPort:8; +#else + uint32_t srcPort:8; + uint32_t msgID:8; + uint32_t error:8; + uint32_t cmdID:8; +#endif + } Bits; + uint32_t Reg32; +} TCommandWord0; + +#ifdef PMC_IMPL_3_X +typedef union { + struct { + uint32_t devAddr:16; // [15:00] bus in upper nibble (only values of 0-7 are allowed), device address in lower 12 bits (4096 devices = 0..4095) + uint32_t zoneIdx:10; // [25:16] maximum 1023 registers/zone (0..1022) + uint32_t island:4; // [27:26] maximum 15 power islands (0..15) (island 15 = ALL islands! + uint32_t reserved:2; // [31:28] + } Bits; + uint32_t Reg32; +} TCommandWord1; +#else +typedef union { + struct { +#ifdef PMC_LITTLE_ENDIAN + uint32_t zoneIdx:10; + uint32_t devAddr:10; + uint32_t island:4; + uint32_t logNum:8; +#else + uint32_t logNum:8; + uint32_t island:4; + uint32_t devAddr:10; + uint32_t zoneIdx:10; +#endif + } Bits; + uint32_t Reg32; +} TCommandWord1; +#endif + +// Ping, GetNextLogEntry, GetRMON and Sigma +typedef struct { + uint32_t unused[2]; +} TCommandNoParams; + +typedef struct { + uint32_t params[2]; +} TCommandGenericParams; + +// PowerZoneOnOff, SetRunState, SetPowerState +typedef struct { +#if defined(PMC_LITTLE_ENDIAN) && defined(PMC_CPU_BIG_ENDIAN) + uint8_t reserved[3]; + uint8_t state; +#else + uint8_t state; + uint8_t reserved[3]; +#endif + uint32_t unused; +} TCommandStateOnly; + +// PowerDevOnOff +typedef struct { +#if defined(PMC_LITTLE_ENDIAN) && defined(PMC_CPU_BIG_ENDIAN) + uint8_t reserved[2]; + uint8_t restore; + uint8_t state; +#else + uint8_t state; + uint8_t restore; + uint8_t reserved[2]; +#endif + uint32_t unused; +} TCommandPowerDevice; + +// PowerOffIsland +typedef struct { +#if defined(PMC_LITTLE_ENDIAN) && defined(PMC_CPU_BIG_ENDIAN) + uint8_t reserved[3]; + uint8_t restore; +#else + uint8_t restore; + uint8_t reserved[3]; +#endif + uint32_t unused; +} TCommandPowerIsland; + +// SetClockLowGear, SetClockHighGear +typedef struct { +#if defined(PMC_LITTLE_ENDIAN) && defined(PMC_CPU_BIG_ENDIAN) + uint8_t reserved[3]; + uint8_t clkN; +#else + uint8_t clkN; + uint8_t reserved[3]; +#endif + uint32_t unused; +} TCommandSetClockN; + +// SetClockGear +typedef struct { +#if defined(PMC_LITTLE_ENDIAN) && defined(PMC_CPU_BIG_ENDIAN) + uint8_t reserved[3]; + uint8_t gear; +#else + uint8_t gear; + uint8_t reserved[3]; +#endif + uint32_t unused; +} TCommandSetClockGear; + +typedef struct { +#if defined(PMC_LITTLE_ENDIAN) && defined(PMC_CPU_BIG_ENDIAN) + uint8_t unused1; + uint8_t numTokens; + uint8_t tokenSize; + uint8_t queueNumber; + uint16_t unused2; + uint8_t high_watermark; + uint8_t low_watermark; +#else + uint8_t queueNumber; + uint8_t tokenSize; + uint8_t numTokens; + uint8_t unused1; + uint8_t low_watermark; + uint8_t high_watermark; + uint16_t unused2; +#endif +} TCommandAllocDQM; + +typedef struct { + uint32_t phy_src_addr; + uint32_t dest_addr; // lower 8 bits **may** be log2 window size +} TCommandJumpApp; + +typedef struct { +#if defined(PMC_IMPL_3_X) || IS_BCMCHIP(63158) + union { + uint32_t word2; + struct { + uint16_t margin_mv_slow; + uint16_t maximum_mv; + }; + }; + union { + uint32_t word3; + struct { + uint16_t margin_mv_fast; + uint16_t minimum_mv; + }; + }; +#else + uint32_t margin_mv_slow; + uint32_t margin_mv_fast; +#endif +} TCommandCloseAVS; + +typedef struct { + uint32_t word2; + uint32_t word3; +} TCommandResponse; + +typedef struct { + TCommandWord0 word0; + TCommandWord1 word1; + union { + TCommandNoParams cmdNoParams; + TCommandGenericParams cmdGenericParams; + TCommandStateOnly cmdStateOnlyParam; + TCommandPowerDevice cmdPowerDevice; + TCommandPowerIsland cmdPowerIsland; + TCommandSetClockN cmdSetClockN; + TCommandSetClockGear cmdSetClockGear; + TCommandAllocDQM cmdAllocDqm; + TCommandJumpApp cmdJumpApp; + TCommandCloseAVS cmdCloseAVS; + TCommandResponse cmdResponse; + } u; +} TCommand; + +// special values to select all devices/zones +#define ALL_DEVICES 0x3ff +#define ALL_ZONES 0x3ff + +// used in validate caller to prevent/allow restrictions on island, device and/or zone +#define ANY_ISLAND 998 +#define ANY_DEVICE 1024 +#define ANY_ZONE 1024 +#define NO_ISLAND 999 +#define NO_DEVICE 1025 +#define NO_ZONE 1025 + +// error codes +enum { + NO_ERROR = 0, + INVALID_ISLAND, + INVALID_DEVICE, + INVALID_ZONE, + INVALID_STATE, + INVALID_COMMAND, + LOG_EMPTY, + INVALID_PARAM, + BPCM_READ_TIMEOUT, + INVALID_BUS, + INVALID_QUEUE_NUMBER, + QUEUE_NOT_AVAILABLE, + INVALID_TOKEN_SIZE, + INVALID_WATERMARKS, + INSUFFIENT_QSM_MEMORY_AVAILABLE, + INVALID_BOOT_COMMAND, + BPCM_WRITE_TIMEOUT, + CMD_TABLE_FULL, + CMD_TABLE_LOCKED, +}; + +// command codes +enum { + // low-level commands + cmdReserved = 0, + cmdGetDevPresence, + cmdGetSWStrap, + cmdGetHWRev, + cmdGetNumZones, + cmdPing, + cmdGetNextLogEntry, + cmdGetRMON, + cmdSetClockHighGear, + cmdSetClockLowGear, + cmdSetClockGear, + cmdReadBpcmReg, + cmdReadZoneReg, + cmdWriteBpcmReg, + cmdWriteZoneReg, + // general-purpose high-level commands + cmdSetRunState, + cmdSetPowerState, + cmdShutdownAllowed, + cmdGetSelect0, + cmdGetSelect3, + cmdGetAvsDisableState, + cmdGetPVT, + // specific-purpose high-level commands + cmdPowerDevOnOff, + cmdPowerZoneOnOff, + cmdResetDevice, + cmdResetZone, + cmdAllocateG2UDQM, + cmdQSMAvailable, + cmdRevision, + cmdRegisterCmdHandler, + cmdFindUnusedCommand, + cmdLockCmdTable, + cmdJumpApp, + cmdStall, + cmdCloseAVS, + cmdReadROs, + cmdGetTrackTemp, + cmdSetTrackTemp, +#ifdef PMC_IMPL_3_X + cmdGetIslandStatus, + cmdGetTMON, + cmdSetTemperatureThresholds, + cmdResetTemperatureWarning, +#endif +}; + +extern void ProcessCommand(TCommand * cmd, TCommand * response); +extern int SendCommand(int cmdID, int devAddr, int zone, int island, uint32_t word2, + uint32_t word3, TCommand *rsp); + + +#endif // PMCCOMMAND_H diff --git a/plat/bcm/include/plat_macros.S b/plat/bcm/include/plat_macros.S new file mode 100644 index 00000000..93cded2b --- /dev/null +++ b/plat/bcm/include/plat_macros.S @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __PLAT_MACROS_S__ +#define __PLAT_MACROS_S__ + +#include +#include + + /* --------------------------------------------- + * The below required platform porting macro + * prints out relevant GIC and CCI registers + * whenever an unhandled exception is taken in + * BL31. + * Clobbers: x0 - x10, x16, x17, sp + * --------------------------------------------- + */ + .macro plat_crash_print_regs + mov_imm x17, GICC_BASE + mov_imm x16, GICD_BASE + arm_print_gic_regs + .endm + +#endif /* __PLAT_MACROS_S__ */ diff --git a/plat/bcm/include/platform_def.h b/plat/bcm/include/platform_def.h new file mode 100644 index 00000000..2509e822 --- /dev/null +++ b/plat/bcm/include/platform_def.h @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __PLATFORM_DEF_H__ +#define __PLATFORM_DEF_H__ + +/* Following two defines needed to makes use of shared PMC driver code */ +#define _CFE_ +#define _ATF_ + +#include +#include +#include +#include +#include + +#define PLAT_ARM_NS_IMAGE_BASE 0x0 + +#define PLATFORM_STACK_SIZE 0x1000 + +#define PLATFORM_MAX_CPUS_PER_CLUSTER 4 +#define PLATFORM_CLUSTER_COUNT 1 +#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER +#define PLATFORM_CLUSTER1_CORE_COUNT 0 +#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \ + PLATFORM_CLUSTER1_CORE_COUNT) + +#define BRCM_PRIMARY_CPU 0 + +#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \ + PLATFORM_CORE_COUNT) +#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1 + +#define PLAT_MAX_RET_STATE 1 +#define PLAT_MAX_OFF_STATE 2 + +/* Local power state for power domains in Run state. */ +#define PLAT_LOCAL_STATE_RUN 0 +/* Local power state for retention. Valid only for CPU power domains */ +#define PLAT_LOCAL_STATE_RET 1 +/* + * Local power state for OFF/power-down. Valid for CPU and cluster power + * domains. + */ +#define PLAT_LOCAL_STATE_OFF 2 + +/* + * Macros used to parse state information from State-ID if it is using the + * recommended encoding for State-ID. + */ +#define PLAT_LOCAL_PSTATE_WIDTH 4 +#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1) + +/* + * Some data must be aligned on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + */ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + + +/* + * BL3-1 specific defines. + * + * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the + * current BL3-1 debug size plus a little space for growth. + */ +#define BL31_BASE (CFG_ATF_AREA_ADDR) +#define BL31_LIMIT (CFG_ATF_AREA_ADDR + CFG_ATF_AREA_SIZE) + + +#define PLAT_ARM_NS_IMAGE_OFFSET (0x0) +#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) +#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) + +/* + * BL3-2 specific defines. + * + */ +#if defined(AARCH32) +#define BL32_BASE BL31_BASE +#define BL32_SIZE CFG_ATF_AREA_SIZE +#define BL32_LIMIT BL31_LIMIT +#define BL322_BASE (CFG_OPTEE_AREA_ADDR) +#else +#define BL32_BASE (CFG_OPTEE_AREA_ADDR) +#define BL32_SIZE (CFG_OPTEE_AREA_SIZE) +#define BL32_LIMIT (CFG_OPTEE_AREA_ADDR + CFG_OPTEE_AREA_SIZE) +#endif + +#define ADDR_SPACE_SIZE (1ull << 32) +#define MAX_MMAP_REGIONS 10 +#define MAX_XLAT_TABLES 16 +#define MAX_IO_DEVICES 3 +#define MAX_IO_HANDLES 4 + +#if defined BOOTLUT_PHYS_BASE +#undef BOOTLUT_BASE +#define BOOTLUT_BASE BOOTLUT_PHYS_BASE +#else +#define BOOTLUT_BASE 0xffff0000 +#endif + +#if !defined(BOOTLUT_SIZE) +#define BOOTLUT_SIZE 0x1000 +#endif + +#if defined (BIUCFG_BASE) +#undef BIUCFG_BASE +#define BIUCFG_BASE (BIUCFG_PHYS_BASE + BIUCFG_OFFSET) +#elif defined (BIUCTRL_BASE) +#undef BIUCTRL_BASE +#define BIUCTRL_BASE (URB_PHYS_BASE + URB_BIUCTRL_OFFSET) +#define BIUCTRL_SIZE URB_SIZE +#endif + +#if defined (B15_CTRL_BASE) +#undef B15_CTRL_BASE +#define B15_CTRL_BASE B15_CTRL_PHYS_BASE +#define B15_CTRL_SIZE 0x3000 +#endif + +#undef TIMR_BASE +#if defined (PLATFORM_FLAVOR_63158) || defined (PLATFORM_FLAVOR_63178) || defined (PLATFORM_FLAVOR_47622) || defined (PLATFORM_FLAVOR_6878) || defined (PLATFORM_FLAVOR_63146) || defined (PLATFORM_FLAVOR_4912) || defined (PLATFORM_FLAVOR_6756) +#define UART0_BASE 0xff812000 +#elif defined (PLATFORM_FLAVOR_6858) || defined (PLATFORM_FLAVOR_6856) || defined (PLATFORM_FLAVOR_4908) || defined (PLATFORM_FLAVOR_6846) +#define UART0_BASE 0xff800000 +#elif defined (PLATFORM_FLAVOR_63138) || defined (PLATFORM_FLAVOR_63148) +#define TIMR_BASE PERF_PHYS_BASE +#define TIMR_SIZE 0x10000 +#define TIMR_OFFSET 0x80 + +#undef UART0_BASE +/* 63138 and 63148 do not support PL011 UART. + UART is needed only for debug print. + For now, just use JTAG to debug these platforms. +*/ +#define UART0_BASE 0x0 +#endif +#define UART0_SIZE 0x1000 +#define UART0_CLK_IN_HZ (50 * 1000 * 1000) + + +#undef PMC_BASE +#if defined (PMC_OFFSET) +#define PMC_BASE (PMC_PHYS_BASE + PMC_OFFSET) +#else +#define PMC_BASE (PMC_PHYS_BASE) +#endif + +#if defined(PROC_MON_BASE) +#undef PROC_MON_BASE +#if defined(PROC_MON_PHYS_BASE) +#define PROC_MON_BASE (PROC_MON_PHYS_BASE) +#else +#define PROC_MON_BASE (PMC_PHYS_BASE + PROC_MON_OFFSET) +#endif +#endif + +#undef PMC_SIZE +#define PMC_SIZE 0x00200000 + +#define PLAT_BCM_CRASH_UART_BASE UART0_BASE +#define PLAT_BCM_CRASH_UART_CLK_IN_HZ UART0_CLK_IN_HZ +#define PLAT_BCM_CONSOLE_BAUDRATE 115200 + +#define PLAT_ARM_CRASH_UART_BASE PLAT_BCM_CRASH_UART_BASE +#define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_BCM_CRASH_UART_CLK_IN_HZ +#define ARM_CONSOLE_BAUDRATE PLAT_BCM_CONSOLE_BAUDRATE + +#define DEVICE0_BASE 0x08000000 +#define DEVICE0_SIZE 0x00021000 +#define DEVICE1_BASE 0x09000000 +#define DEVICE1_SIZE 0x00011000 + + +#if defined(WDTIMR0_BASE) +#undef WDTIMR0_BASE +#define WDTIMR0_BASE (PERF_PHYS_BASE+WDTIMR0_OFFSET) +#define WDTIMR_BASE (PERF_PHYS_BASE) +#define WDTIMR_SIZE 0x4000 +#endif + +/* + * GIC related constants + */ + +#undef GICD_BASE +#undef GICC_BASE +#undef SCU_BASE +#if defined (PLATFORM_FLAVOR_63138) || defined (PLATFORM_FLAVOR_63148) +#define GICD_BASE GICD_PHYS_BASE +#define GICC_BASE GICC_PHYS_BASE +#if defined (PLATFORM_FLAVOR_63138) +#define SCU_BASE SCU_PHYS_BASE +#endif +#else +#define GICD_BASE (GIC_PHYS_BASE + GICD_OFFSET) +#define GICC_BASE (GIC_PHYS_BASE + GICC_OFFSET) +#endif + +#define GICR_BASE 0 + + +#define BRCM_IRQ_SEC_SGI_0 8 +#define BRCM_IRQ_SEC_SGI_1 9 +#define BRCM_IRQ_SEC_SGI_2 10 +#define BRCM_IRQ_SEC_SGI_3 11 +#define BRCM_IRQ_SEC_SGI_4 12 +#define BRCM_IRQ_SEC_SGI_5 13 +#define BRCM_IRQ_SEC_SGI_6 14 +#define BRCM_IRQ_SEC_SGI_7 15 + +#if defined (PLATFORM_FLAVOR_63138) +#define PL310_BASE 0x8001D000 +#define PL310_MAP_SIZE 0x00002000 + +#undef SCU_BASE +#define SCU_BASE 0x8001E000 +#define SCU_ERRATA744369 0x30 + +#define BIT32(nr) (1 << (nr)) +/* + * Outer cache iomem + */ +#define PL310_LINE_SIZE 32 +#define PL310_8_WAYS 8 + +/* reg1 */ +#define PL310_CTRL 0x100 +#define PL310_AUX_CTRL 0x104 +#define PL310_TAG_RAM_CTRL 0x108 +#define PL310_DATA_RAM_CTRL 0x10C +/* reg7 */ +#define PL310_SYNC 0x730 +#define PL310_INV_BY_WAY 0x77C +#define PL310_CLEAN_BY_WAY 0x7BC +#define PL310_FLUSH_BY_WAY 0x7FC +#define PL310_INV_BY_PA 0x770 +#define PL310_CLEAN_BY_PA 0x7B0 +#define PL310_FLUSH_BY_PA 0x7F0 +#define PL310_FLUSH_BY_INDEXWAY 0x7F8 +/* reg9 */ +#define PL310_DCACHE_LOCKDOWN_BASE 0x900 +#define PL310_ICACHE_LOCKDOWN_BASE 0x904 +/* reg12 */ +#define PL310_ADDR_FILT_START 0xC00 +#define PL310_ADDR_FILT_END 0xC04 +/* reg15 */ +#define PL310_DEBUG_CTRL 0xF40 +#define PL310_PREFETCH_CTRL 0xF60 +#define PL310_POWER_CTRL 0xF80 + +#define PL310_CTRL_ENABLE_BIT BIT32(0) +#define PL310_AUX_16WAY_BIT BIT32(16) + +/* + * PL310 TAG RAM Control Register + * + * bit[10:8]:1 - 2 cycle of write accesses latency + * bit[6:4]:1 - 2 cycle of read accesses latency + * bit[2:0]:1 - 2 cycle of setup latency + */ +#ifndef PL310_TAG_RAM_CTRL_INIT +#define PL310_TAG_RAM_CTRL_INIT 0x00000111 +#endif + +/* + * PL310 DATA RAM Control Register + * + * bit[10:8]:2 - 3 cycle of write accesses latency + * bit[6:4]:2 - 3 cycle of read accesses latency + * bit[2:0]:2 - 3 cycle of setup latency + */ +#ifndef PL310_DATA_RAM_CTRL_INIT +#define PL310_DATA_RAM_CTRL_INIT 0x00000111 +#endif + +/* + * PL310 Auxiliary Control Register + * + * I/Dcache prefetch enabled (bit29:28=2b11) + * NS can access interrupts (bit27=1) + * NS can lockown cache lines (bit26=1) + * Pseudo-random replacement policy (bit25=0) + * Force write allocated (default) + * Shared attribute internally ignored (bit22=1, bit13=0) + * Parity disabled (bit21=0) + * Event monitor disabled (bit20=0) + * Platform fmavor specific way config (dual / quad): + * - 64kb way size (bit19:17=3b011) + * - 16-way associciativity (bit16=1) + * Platform fmavor specific way config (dual lite / solo): + * - 32kb way size (bit19:17=3b010) + * - no 16-way associciativity (bit16=0) + * Store buffer device limitation enabled (bit11=1) + * Cacheable accesses have high prio (bit10=0) + * Full Line Zero (FLZ) disabled (bit0=0) + */ + +#define PL310_AUX_CTRL_INIT 0x4e450001 + +/* + * PL310 Prefetch Control Register + * + * Double linefill disabled (bit30=0) + * I/D prefetch enabled (bit29:28=2b11) + * Prefetch drop enabled (bit24=1) + * Incr double linefill disable (bit23=0) + * Prefetch offset = 7 (bit4:0) + */ +#define PL310_PREFETCH_CTRL_INIT 0x31000007 + +/* + * PL310 Power Register + * + * Dynamic clock gating enabled + * Standby mode enabled + */ +#define PL310_POWER_CTRL_INIT 0x00000003 + +#define GICC_CTLR_OFFSET 0x0 +#define GICC_PMR_OFFSET 0x4 +#define GICD_CTLR_OFFSET 0x0 +#define GICD_TYPER_OFFSET 0x4 +#define GICD_IGROUPR0_OFFSET 0x80 + +#endif + +/* + * System counter + */ +#define SYS_COUNTER_FREQ_IN_TICKS (50 * 1000 * 1000) + +#endif /* __PLATFORM_DEF_H__ */ diff --git a/plat/bcm/include/pmc_addr_47622.h b/plat/bcm/include/pmc_addr_47622.h new file mode 100644 index 00000000..415eb8c6 --- /dev/null +++ b/plat/bcm/include/pmc_addr_47622.h @@ -0,0 +1,134 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_47622_H__ +#define PMC_ADDR_47622_H__ + +#define PMB_BUS_ID_SHIFT 12 + +#define PMB_BUS_PERIPH 1 +#define PMB_ADDR_PERIPH (16 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 4 + +#define PMB_BUS_CRYPTO 0 +#define PMB_ADDR_CRYPTO (1 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CRYPTO 1 + +#define PMB_BUS_PVTMON 0 +#define PMB_ADDR_PVTMON (2 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PVTMON 0 + +#define PMB_BUS_CHIP_CLKRST 0 +#define PMB_ADDR_CHIP_CLKRST (3 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_USB31_20 0 +#define PMB_ADDR_USB31_20 (4 | PMB_BUS_USB31_20 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB31_20 3 + +#define PMB_BUS_WLAN0 0 +#define PMB_ADDR_WLAN0 (5 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0 1 + +#define PMB_BUS_WLAN0_PHY1 0 +#define PMB_ADDR_WLAN0_PHY1 (6 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0_PHY1 1 + +#define PMB_BUS_WLAN0_PHY2 0 +#define PMB_ADDR_WLAN0_PHY2 (7 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0_PHY2 1 + +#define PMB_BUS_WLAN1 0 +#define PMB_ADDR_WLAN1 (8 | PMB_BUS_WLAN1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN1 1 + +#define PMB_BUS_WLAN1_PHY1 0 +#define PMB_ADDR_WLAN1_PHY1 (9 | PMB_BUS_WLAN1_PHY1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN1_PHY1 1 + +#define PMB_BUS_WLAN1_PHY2 0 +#define PMB_ADDR_WLAN1_PHY2 (10 | PMB_BUS_WLAN1_PHY2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN1_PHY2 1 + +#define PMB_BUS_MEMC 0 +#define PMB_ADDR_MEMC (11 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_SYSP 0 +#define PMB_ADDR_SYSP (0 | PMB_BUS_SYSP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSP 3 + +#define PMB_BUS_PCIE0 1 +#define PMB_ADDR_PCIE0 (17 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_ORION_CPU0 0 +#define PMB_ADDR_ORION_CPU0 (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU0 1 + +#define PMB_BUS_ORION_CPU1 0 +#define PMB_ADDR_ORION_CPU1 (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU1 1 + +#define PMB_BUS_ORION_CPU2 0 +#define PMB_ADDR_ORION_CPU2 (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU2 1 + +#define PMB_BUS_ORION_CPU3 0 +#define PMB_ADDR_ORION_CPU3 (35 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU3 1 + +#define PMB_BUS_ORION_NONCPU 0 +#define PMB_ADDR_ORION_NONCPU (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_NONCPU 1 + +#define PMB_BUS_BIU_PLL 0 +#define PMB_ADDR_BIU_PLL (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_PLL 0 + +#define PMB_BUS_BIU_BPCM 0 +#define PMB_ADDR_BIU_BPCM (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_BPCM 1 + +#define PMB_BUS_PCM PMB_BUS_PERIPH +#define PMB_ADDR_PCM (16 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCM 4 + +enum { + PCM_Zone_Main, + PCM_Zone_PCM = 3 +}; + +//--------- SOFT Reset bits for PCM ------------------------ +#define BPCM_PCM_SRESET_PCM_N 0x00000040 + +#define RCAL_0P25UM_HORZ 0 +#define RCAL_0P25UM_VERT 1 +#define RCAL_0P5UM_HORZ 2 +#define RCAL_0P5UM_VERT 3 +#define RCAL_1UM_HORZ 4 +#define RCAL_1UM_VERT 5 +#define PMMISC_RMON_EXT_REG ((RCAL_1UM_VERT + 1)/2) +#define PMMISC_RMON_VALID_MASK (0x1<<16) + +#endif diff --git a/plat/bcm/include/pmc_addr_4908.h b/plat/bcm/include/pmc_addr_4908.h new file mode 100644 index 00000000..c90218bb --- /dev/null +++ b/plat/bcm/include/pmc_addr_4908.h @@ -0,0 +1,126 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_4908_H__ +#define PMC_ADDR_4908_H__ + +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 8 + +#define PMB_BUS_PERIPH 0 +#define PMB_ADDR_PERIPH (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 4 + +#define PMB_BUS_CRYPTO 0 +#define PMB_ADDR_CRYPTO (1 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CRYPTO 1 + +#define PMB_BUS_PCIE2 0 +#define PMB_ADDR_PCIE2 (2 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE2 1 + +#define PMB_BUS_RDP 0 +#define PMB_ADDR_RDP (3 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_RDP 2 + +#define PMB_BUS_FPM 0 +#define PMB_ADDR_FPM (4 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_FPM 1 + +#define PMB_BUS_DQM 0 +#define PMB_ADDR_DQM (5 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_DQM 1 + +#define PMB_BUS_URB 0 +#define PMB_ADDR_URB (6 | PMB_BUS_URB << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_URB 1 + +#define PMB_BUS_MEMC 0 +#define PMB_ADDR_MEMC (7 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_RDPPLL 0 +#define PMB_ADDR_RDPPLL (8 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_RDPPLL 0 + +#define PMB_BUS_B53PLL 0 +#define PMB_ADDR_B53PLL (9 | PMB_BUS_B53PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_B53PLL 0 + +#define PMB_BUS_SWITCH 1 +#define PMB_ADDR_SWITCH (10 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SWITCH 3 + +#define PMB_BUS_PCM 1 +#define PMB_ADDR_PCM (11 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCM 2 +enum { + PCM_Zone_Main, + PCM_Zone_PCM, +}; +//--------- SOFT Reset bits for PCM ------------------------ +#define BPCM_PCM_SRESET_HARDRST_N 0x00000004 +#define BPCM_PCM_SRESET_PCM_N 0x00000002 +#define BPCM_PCM_SRESET_200_N 0x00000001 + +#define PMB_BUS_SGMII 1 +#define PMB_ADDR_SGMII (12 | PMB_BUS_SGMII << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SGMII 0 + +#define PMB_BUS_CHIP_CLKRST 1 +#define PMB_ADDR_CHIP_CLKRST (13 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_PCIE0 1 +#define PMB_ADDR_PCIE0 (14 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_PCIE1 1 +#define PMB_ADDR_PCIE1 (15 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1 1 + +#define PMB_BUS_SATA 1 +#define PMB_ADDR_SATA (16 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SATA 1 + +#define PMB_BUS_USB 1 +#define PMB_ADDR_USB30_2X (17 | PMB_BUS_USB << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB 4 + +#define PMB_BUS_SYSPLL 1 +#define PMB_ADDR_SYSPLL (18 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL 0 + +#define PMB_BUS_SWTPLL 1 +#define PMB_ADDR_SWTPLL (19 | PMB_BUS_SWTPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SWTPLL 0 + +#define PMB_BUS_I2SPLL 1 +#define PMB_ADDR_I2SPLL (20 | PMB_BUS_I2SPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_I2SPLL 0 + +#define PMB_BUS_GMAC 1 +#define PMB_ADDR_GMAC (21 | PMB_BUS_GMAC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_GMAC 1 + +#endif diff --git a/plat/bcm/include/pmc_addr_4912.h b/plat/bcm/include/pmc_addr_4912.h new file mode 100755 index 00000000..11eda634 --- /dev/null +++ b/plat/bcm/include/pmc_addr_4912.h @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Broadcom Ltd. + */ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef _4912_PMC_ADDR_H +#define _4912_PMC_ADDR_H + +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 12 + +#define PMB_BUS_PERIPH 0 +#define PMB_ADDR_PERIPH (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 4 + +#define PMB_BUS_CHIP_CLKRST 0 +#define PMB_ADDR_CHIP_CLKRST (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_PVTMON 1 +#define PMB_ADDR_PVTMON (3 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PVTMON 0 + +#define PMB_BUS_CRYPTO 1 +#define PMB_ADDR_CRYPTO (4 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CRYPTO 0 + +#define PMB_BUS_USB30_2X 0 +#define PMB_ADDR_USB30_2X (5 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB30_2X 4 + +#define PMB_BUS_PCIE1 1 +#define PMB_ADDR_PCIE1 (6 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1 4 + +// referring to PCIEG3 +#define PMB_BUS_PCIE3 1 +#define PMB_ADDR_PCIE3 (7 | PMB_BUS_PCIE3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE3 1 + +#define PMB_BUS_MEMC 1 +#define PMB_ADDR_MEMC (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_XRDP 1 +#define PMB_ADDR_XRDP (9 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP 1 + +#define PMB_BUS_PCIE2 1 +#define PMB_ADDR_PCIE2 (11 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE2 1 + +#define PMB_BUS_PCIE0 0 +#define PMB_ADDR_PCIE0 (12 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_ETH 1 +#define PMB_ADDR_ETH (13 | PMB_BUS_ETH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ETH 1 + +#define PMB_BUS_MPM 1 +#define PMB_ADDR_MPM (14 | PMB_BUS_MPM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MPM 1 + +#define PMB_BUS_XRDPPLL 0 +#define PMB_ADDR_XRDPPLL (15 | PMB_BUS_XRDPPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDPPLL 0 + +#define PMB_BUS_PERIPH_ARS 0 +#define PMB_ADDR_PERIPH_ARS (16 | PMB_BUS_PERIPH_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH_ARS 0 + +#define PMB_BUS_PCIE0_UBUS_ARS 0 +#define PMB_ADDR_PCIE0_UBUS_ARS (17 | PMB_BUS_PCIE0_UBUS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0_UBUS_ARS 0 + +#define PMB_BUS_USB30_2X_ARS 0 +#define PMB_ADDR_USB30_2X_ARS (18 | PMB_BUS_USB30_2X_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB30_2X_ARS 0 + +#define PMB_BUS_SYS_ARS 0 +#define PMB_ADDR_SYS_ARS (19 | PMB_BUS_SYS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYS_ARS 0 + +#define PMB_BUS_CRYPTO2_ARS 1 +#define PMB_ADDR_CRYPTO2_ARS (20 | PMB_BUS_CRYPTO2_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CRYPTO2_ARS 0 + +#define PMB_BUS_XRDP_ARS 1 +#define PMB_ADDR_XRDP_ARS (21 | PMB_BUS_XRDP_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_ARS 0 + +#define PMB_BUS_MPM_ARS 1 +#define PMB_ADDR_MPM_ARS (22 | PMB_BUS_MPM_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MPM_ARS 0 + +#define PMB_BUS_MEMC_ARS 1 +#define PMB_ADDR_MEMC_ARS (23 | PMB_BUS_MEMC_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC_ARS 0 + +#define PMB_BUS_ETH_ARS 1 +#define PMB_ADDR_ETH_ARS (24 | PMB_BUS_ETH_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ETH_ARS 0 + +#define PMB_BUS_PCIE1_UBUS_ARS 1 +#define PMB_ADDR_PCIE1_UBUS_ARS (25 | PMB_BUS_PCIE1_UBUS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1_UBUS_ARS 0 + +#define PMB_BUS_PCIE3_ARS 1 +#define PMB_ADDR_PCIE3_ARS (26 | PMB_BUS_PCIE3_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE3_ARS 0 + +#define PMB_BUS_MERLIN0_UBUS_ARS 1 +#define PMB_ADDR_MERLIN0_UBUS_ARS (27 | PMB_BUS_MERLIN0_UBUS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MERLIN0_UBUS_ARS 0 + +#define PMB_BUS_MERLIN1_UBUS_ARS 1 +#define PMB_ADDR_MERLIN1_UBUS_ARS (28 | PMB_BUS_MERLIN1_UBUS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MERLIN1_UBUS_ARS 0 + +#define PMB_BUS_MERLIN2_UBUS_ARS 1 +#define PMB_ADDR_MERLIN2_UBUS_ARS (29 | PMB_BUS_MERLIN2_UBUS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MERLIN2_UBUS_ARS 0 + +#define PMB_BUS_ORION_PLL 1 +#define PMB_ADDR_ORION_PLL (32 | PMB_BUS_ORION_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_PLL 0 +#define PMB_BUS_BIU_PLL PMB_BUS_ORION_PLL +#define PMB_ADDR_BIU_PLL PMB_ADDR_ORION_PLL +#define PMB_ZONES_BIU_PLL PMB_ZONES_ORION_PLL + +#define PMB_BUS_ORION_BPCM 1 +#define PMB_ADDR_ORION_BPCM (33 | PMB_BUS_ORION_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_BPCM 1 +#define PMB_BUS_BIU_BPCM PMB_BUS_ORION_BPCM +#define PMB_ADDR_BIU_BPCM PMB_ADDR_ORION_BPCM +#define PMB_ZONES_BIU_BPCM PMB_ZONES_ORION_BPCM + +#define PMB_BUS_ORION_CPU0 1 +#define PMB_ADDR_ORION_CPU0 (34 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU0 1 + +#define PMB_BUS_ORION_CPU1 1 +#define PMB_ADDR_ORION_CPU1 (35 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU1 1 + +#define PMB_BUS_ORION_CPU2 1 +#define PMB_ADDR_ORION_CPU2 (36 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU2 1 + +#define PMB_BUS_ORION_CPU3 1 +#define PMB_ADDR_ORION_CPU3 (37 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU3 1 + +#define PMB_BUS_ORION_NONCPU 1 +#define PMB_ADDR_ORION_NONCPU (38 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_NONCPU 1 + +#define PMB_BUS_ORION_ARS 1 +#define PMB_ADDR_ORION_ARS (39 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_ARS 0 + +#define PMB_BUS_ORION_ACEBIU_ARS 1 +#define PMB_ADDR_ORION_ACEBIU_ARS (40 | PMB_BUS_ORION_ACEBIU_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_ACEBIU_ARS 0 +#endif diff --git a/plat/bcm/include/pmc_addr_63138.h b/plat/bcm/include/pmc_addr_63138.h new file mode 100644 index 00000000..2e5cfa26 --- /dev/null +++ b/plat/bcm/include/pmc_addr_63138.h @@ -0,0 +1,218 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_63138_H__ +#define PMC_ADDR_63138_H__ + +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 8 + +#define PMB_BUS_APM 1 +#define PMB_ADDR_APM (0 | PMB_BUS_APM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_APM 5 + +//--------- SOFT Reset bits for APM ------------------------ +#define BPCM_APM_SRESET_HARDRST_N 0x00000040 +#define BPCM_APM_SRESET_AUDIO_N 0x00000020 +#define BPCM_APM_SRESET_PCM_N 0x00000010 +#define BPCM_APM_SRESET_HVGA_N 0x00000008 +#define BPCM_APM_SRESET_HVGB_N 0x00000004 +#define BPCM_APM_SRESET_BMU_N 0x00000002 +#define BPCM_APM_SRESET_200_N 0x00000001 + +#define PMB_BUS_SWITCH 1 +#define PMB_ADDR_SWITCH (1 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SWITCH 3 + +#define PMB_BUS_CHIP_CLKRST 1 +#define PMB_ADDR_CHIP_CLKRST (2 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_SATA 0 +#define PMB_ADDR_SATA (3 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SATA 1 + +#define PMB_BUS_AIP 0 +#define PMB_ADDR_AIP (4 | PMB_BUS_AIP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_AIP 1 + +#define PMB_BUS_DECT_UBUS 0 +#define PMB_ADDR_DECT_UBUS (5 | PMB_BUS_DECT_UBUS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_DECT_UBUS 1 + +#define PMB_BUS_SAR 1 +#define PMB_ADDR_SAR (6 | PMB_BUS_SAR << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SAR 1 + +#define PMB_BUS_RDP 1 +#define PMB_ADDR_RDP (7 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_RDP 2 + +#define PMB_BUS_MEMC 0 +#define PMB_ADDR_MEMC (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_PERIPH 0 +#define PMB_ADDR_PERIPH (9 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 3 + +#define PMB_BUS_SYSPLL 1 +#define PMB_ADDR_SYSPLL (10 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL 0 + +#define PMB_BUS_RDPPLL 1 +#define PMB_ADDR_RDPPLL (11 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_RDPPLL 0 + +#define PMB_BUS_SYSPLL2 0 +#define PMB_ADDR_SYSPLL2 (12 | PMB_BUS_SYSPLL2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL2 0 + +#define PMB_BUS_SYSPLL3 0 +#define PMB_ADDR_SYSPLL3 (13 | PMB_BUS_SYSPLL3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL3 0 + +#define PMB_BUS_SYSPLL4 0 +#define PMB_ADDR_SYSPLL4 (14 | PMB_BUS_SYSPLL4 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL4 0 + +#define PMB_BUS_PCIE0 0 +#define PMB_ADDR_PCIE0 (15 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_PCIE1 0 +#define PMB_ADDR_PCIE1 (16 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1 1 + +#define PMB_BUS_USB30_2X 1 +#define PMB_ADDR_USB30_2X (17 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB30_2X 4 + +#define PMB_BUS_PSAB 0 +#define PMB_ADDR_PSAB (18 | PMB_BUS_PSAB << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PSAB 1 // not shown in spreadsheet + +#define PMB_BUS_PSBC 0 +#define PMB_ADDR_PSBC (19 | PMB_BUS_PSBC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PSBC 1 // not shown in spreadsheet + +#define PMB_BUS_EGPHY 0 +#define PMB_ADDR_EGPHY (20 | PMB_BUS_EGPHY << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_EGPHY 1 // not shown in spreadsheet + +#define PMB_BUS_VDSL3_MIPS 0 +#define PMB_ADDR_VDSL3_MIPS (21 | PMB_BUS_VDSL3_MIPS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_VDSL3_MIPS 1 + +#define PMB_BUS_VDSL3_CORE 0 +#define PMB_ADDR_VDSL3_CORE (22 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_VDSL3_CORE 3 + +#define AFEPLL_PMB_BUS_VDSL3_CORE 0 +#define AFEPLL_PMB_ADDR_VDSL3_CORE (23 | AFEPLL_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT) +#define AFEPLL_PMB_ZONES_VDSL3_CORE 0 + +#define UBUS_PMB_BUS_VDSL3_CORE PMB_BUS_VDSL3_CORE +#define UBUS_PMB_ADDR_VDSL3_CORE (24 | UBUS_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT) +#define UBUS_PMB_ZONES_VDSL3_CORE 0 + +#define UBUS_PMB_BUS_VDSL3_MIPS PMB_BUS_VDSL3_MIPS +#define UBUS_PMB_ADDR_VDSL3_MIPS (25 | UBUS_PMB_BUS_VDSL3_MIPS << PMB_BUS_ID_SHIFT) +#define UBUS_PMB_ZONES_VDSL3_MIPS 0 + +#define UBUS_PMB_BUS_DECT PMB_BUS_DECT_UBUS +#define UBUS_PMB_ADDR_DECT (26 | UBUS_PMB_BUS_DECT << PMB_BUS_ID_SHIFT) +#define UBUS_PMB_ZONES_DECT 0 + +#define UBUS_PMB_BUS_ARM PMB_BUS_AIP +#define UBUS_PMB_ADDR_ARM (27 | UBUS_PMB_BUS_ARM << PMB_BUS_ID_SHIFT) +#define UBUS_PMB_ZONES_ARM 0 + +#define UBUS_PMB_BUS_DAP PMB_BUS_AIP +#define UBUS_PMB_ADDR_DAP (28 | UBUS_PMB_BUS_DAP << PMB_BUS_ID_SHIFT) +#define UBUS_PMB_ZONES_DAP 0 + +#define UBUS_CFG0_PMB_BUS_SAR PMB_BUS_SAR +#define UBUS_CFG0_PMB_ADDR_SAR (29 | UBUS_CFG0_PMB_BUS_SAR << PMB_BUS_ID_SHIFT) +#define UBUS_CFG0_PMB_ZONES_SAR 0 + +#define UBUS_CFG1_PMB_BUS_SAR PMB_BUS_SAR +#define UBUS_CFG1_PMB_ADDR_SAR (30 | UBUS_CFG1_PMB_BUS_SAR << PMB_BUS_ID_SHIFT) +#define UBUS_CFG1_PMB_ZONES_SAR 0 + +#define UBUS_CFG_PMB_BUS_DBR PMB_BUS_RDP +#define UBUS_CFG_PMB_ADDR_DBR (31 | UBUS_CFG_PMB_BUS_DBR << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_DBR 0 + +#define UBUS_CFG_PMB_BUS_RABR PMB_BUS_RDP +#define UBUS_CFG_PMB_ADDR_RABR (32 | UBUS_CFG_PMB_BUS_RABR << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_RABR 0 + +#define UBUS_CFG_PMB_BUS_RBBR PMB_BUS_RDP +#define UBUS_CFG_PMB_ADDR_RBBR (33 | UBUS_CFG_PMB_BUS_RBBR << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_RBBR 0 + +#define UBUS_CFG_PMB_BUS_APM PMB_BUS_APM +#define UBUS_CFG_PMB_ADDR_APM (34 | UBUS_CFG_PMB_BUS_APM << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_APM 0 + +#define UBUS_CFG_PMB_BUS_PCIE0 PMB_BUS_PCIE0 +#define UBUS_CFG_PMB_ADDR_PCIE0 (35 | UBUS_CFG_PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_PCIE0 0 + +#define UBUS_CFG_PMB_BUS_PCIE1 PMB_BUS_PCIE1 +#define UBUS_CFG_PMB_ADDR_PCIE1 (36 | UBUS_CFG_PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_PCIE1 0 + +#define UBUS_CFG_PMB_BUS_USBH PMB_BUS_USB30_2X +#define UBUS_CFG_PMB_ADDR_USBH (37 | UBUS_CFG_PMB_BUS_USBH << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_USBH 0 + +#define UBUS_CFG_PMB_BUS_USBD PMB_BUS_USB30_2X +#define UBUS_CFG_PMB_ADDR_USBD (38 | UBUS_CFG_PMB_BUS_USBD << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_USBD 0 + +#define UBUS_CFG_PMB_BUS_SWITCH PMB_BUS_SWITCH +#define UBUS_CFG_PMB_ADDR_SWITCH (39 | UBUS_CFG_PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_SWITCH 0 + +#define UBUS_CFG_PMB_BUS_PERIPH PMB_BUS_PERIPH +#define UBUS_CFG_PMB_ADDR_PERIPH (40 | UBUS_CFG_PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_PERIPH 0 + +#define UBUS_CFG_PMB_BUS_SATA PMB_BUS_SATA +#define UBUS_CFG_PMB_ADDR_SATA (41 | UBUS_CFG_PMB_BUS_SATA << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_SATA 0 + +/* define Zone enum for each block here */ +#ifndef _LANGUAGE_ASSEMBLY +enum { + APM_Zone_Main, + APM_Zone_Audio, + APM_Zone_PCM, + APM_Zone_HVG, + APM_Zone_BMU, +}; +#endif + +#endif diff --git a/plat/bcm/include/pmc_addr_63146.h b/plat/bcm/include/pmc_addr_63146.h new file mode 100644 index 00000000..20de9da0 --- /dev/null +++ b/plat/bcm/include/pmc_addr_63146.h @@ -0,0 +1,122 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_63146_H__ +#define PMC_ADDR_63146_H__ + +/* FIXME! only fill those that I found from RTL */ +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 12 + +#define PMB_BUS_PCIE0 0 +#define PMB_ADDR_PCIE0 (0 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_VDSL3_CORE 0 +#define PMB_ADDR_VDSL3_CORE (1 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_VDSL3_CORE 1 + +#define PMB_BUS_EGPHY 0 +#define PMB_ADDR_EGPHY (2 | PMB_BUS_EGPHY << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_EGPHY 1 // not shown in spreadsheet + +#define PMB_BUS_XRDP 0 +#define PMB_ADDR_XRDP (3 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP 3 + +#define PMB_BUS_USB30_2X 0 +#define PMB_ADDR_USB30_2X (4 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB30_2X 4 + +#define PMB_BUS_MEMC 0 +#define PMB_ADDR_MEMC (5 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_PVTMON 0 +#define PMB_ADDR_PVTMON (6 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PVTMON 0 + +#define PMB_BUS_PCIE1 0 +#define PMB_ADDR_PCIE1 (7 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1 1 + +#define PMB_BUS_PCIE2 0 +#define PMB_ADDR_PCIE2 (8 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE2 1 + +#define PMB_BUS_PERIPH 1 +#define PMB_ADDR_PERIPH (9 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 4 + +#define PMB_BUS_VDSL3_PMD 1 +#define PMB_ADDR_VDSL3_PMD (10 | PMB_BUS_VDSL3_PMD << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_VDSL3_PMD 1 + +//--------- DGASP related bits/Offsets ------------------------ +#define BPCM_PHY_CNTL_OVERRIDE 0x00000002 +#define BPCM_PHY_CNTL_AFE_PWRDWN 0x00000001 +#define PMB_ADDR_VDSL_DGASP_PMD PMB_ADDR_VDSL3_PMD +#define BPCM_VDSL_PHY_CTL_REG vdsl_afe_config1 // Alias for register containing DGASP override inside the VDSL PMD +#define BPCM_VDSL_AFE_CTL_REG vdsl_afe_config0 // Alias for register containing DGASP configuration inside the VDSL PMD + +#define PMB_BUS_AFEPLL 1 +#define PMB_ADDR_AFEPLL (11 | PMB_BUS_AFEPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_AFEPLL 1 + +#define AFEPLL_PMB_BUS_VDSL3_CORE PMB_BUS_AFEPLL +#define AFEPLL_PMB_ADDR_VDSL3_CORE PMB_ADDR_AFEPLL +#define AFEPLL_PMB_ZONES_VDSL3_CORE PMB_ZONES_AFEPLL + +#define PMB_BUS_CHIP_CLKRST 1 +#define PMB_ADDR_CHIP_CLKRST (12 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_RDPPLL 1 +#define PMB_ADDR_RDPPLL (13 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_RDPPLL 0 + +#define PMB_BUS_BIU_PLL 1 +#define PMB_ADDR_BIU_PLL (32 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_PLL 0 + +#define PMB_BUS_BIU_BPCM 1 +#define PMB_ADDR_BIU_BPCM (33 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_BPCM 1 + +#define PMB_BUS_ORION_CPU0 1 +#define PMB_ADDR_ORION_CPU0 (34 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU0 1 + +#define PMB_BUS_ORION_CPU1 1 +#define PMB_ADDR_ORION_CPU1 (35 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU1 1 + +#define PMB_BUS_ORION_NONCPU 1 +#define PMB_ADDR_ORION_NONCPU (38 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_NONCPU 1 + +#define PMB_BUS_ORION_ARS 1 +#define PMB_ADDR_ORION_ARS (39 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_ARS 0 + +#endif diff --git a/plat/bcm/include/pmc_addr_63148.h b/plat/bcm/include/pmc_addr_63148.h new file mode 100644 index 00000000..2e262263 --- /dev/null +++ b/plat/bcm/include/pmc_addr_63148.h @@ -0,0 +1,230 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_63148_H__ +#define PMC_ADDR_63148_H__ + +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 8 + +#define PMB_BUS_APM 1 +#define PMB_ADDR_APM (0 | PMB_BUS_APM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_APM 5 + +//--------- SOFT Reset bits for APM ------------------------ +#define BPCM_APM_SRESET_HARDRST_N 0x00000040 +#define BPCM_APM_SRESET_AUDIO_N 0x00000020 +#define BPCM_APM_SRESET_PCM_N 0x00000010 +#define BPCM_APM_SRESET_HVGA_N 0x00000008 +#define BPCM_APM_SRESET_HVGB_N 0x00000004 +#define BPCM_APM_SRESET_BMU_N 0x00000002 +#define BPCM_APM_SRESET_200_N 0x00000001 + +#define PMB_BUS_SWITCH 1 +#define PMB_ADDR_SWITCH (1 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SWITCH 3 + +#define PMB_BUS_CHIP_CLKRST 1 +#define PMB_ADDR_CHIP_CLKRST (2 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_SATA 0 +#define PMB_ADDR_SATA (3 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SATA 1 + +#define PMB_BUS_URB 0 +#define PMB_ADDR_URB (4 | PMB_BUS_URB << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_URB 1 + +#define PMB_BUS_DECT_UBUS 0 +#define PMB_ADDR_DECT_UBUS (5 | PMB_BUS_DECT_UBUS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_DECT_UBUS 1 + +#define PMB_BUS_SAR 1 +#define PMB_ADDR_SAR (6 | PMB_BUS_SAR << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SAR 1 + +#define PMB_BUS_RDP 1 +#define PMB_ADDR_RDP (7 | PMB_BUS_RDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_RDP 2 + +#define PMB_BUS_MEMC 0 +#define PMB_ADDR_MEMC (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_PERIPH 0 +#define PMB_ADDR_PERIPH (9 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 1 + +#define PMB_BUS_SYSPLL 1 +#define PMB_ADDR_SYSPLL (10 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL 0 + +#define PMB_BUS_RDPPLL 1 +#define PMB_ADDR_RDPPLL (11 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_RDPPLL 0 + +#define PMB_BUS_B15_PLL 1 +#define PMB_ADDR_B15_PLL (12 | PMB_BUS_B15_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_B15_PLL 0 + +#define PMB_BUS_SYSPLL3 0 +#define PMB_ADDR_SYSPLL3 (13 | PMB_BUS_SYSPLL3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL3 0 + +#define PMB_BUS_SYSPLL4 0 +#define PMB_ADDR_SYSPLL4 (14 | PMB_BUS_SYSPLL4 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL4 0 + +#define PMB_BUS_PCIE0 0 +#define PMB_ADDR_PCIE0 (15 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_PCIE1 0 +#define PMB_ADDR_PCIE1 (16 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1 1 + +#define PMB_BUS_USB30_2X 1 +#define PMB_ADDR_USB30_2X (17 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB30_2X 4 + +#define PMB_BUS_PSAB 0 +#define PMB_ADDR_PSAB (18 | PMB_BUS_PSAB << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PSAB 1 // not shown in spreadsheet + +#define PMB_BUS_PSBC 0 +#define PMB_ADDR_PSBC (19 | PMB_BUS_PSBC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PSBC 1 // not shown in spreadsheet + +#define PMB_BUS_EGPHY 0 +#define PMB_ADDR_EGPHY (20 | PMB_BUS_EGPHY << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_EGPHY 1 // not shown in spreadsheet + +#define PMB_BUS_VDSL3_MIPS 0 +#define PMB_ADDR_VDSL3_MIPS (21 | PMB_BUS_VDSL3_MIPS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_VDSL3_MIPS 1 + +#define PMB_BUS_VDSL3_CORE 0 +#define PMB_ADDR_VDSL3_CORE (22 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_VDSL3_CORE 3 + +#define AFEPLL_PMB_BUS_VDSL3_CORE 0 +#define AFEPLL_PMB_ADDR_VDSL3_CORE (23 | AFEPLL_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT) +#define AFEPLL_PMB_ZONES_VDSL3_CORE 0 + +#define UBUS_PMB_BUS_VDSL3_CORE PMB_BUS_VDSL3_CORE +#define UBUS_PMB_ADDR_VDSL3_CORE (24 | UBUS_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT) +#define UBUS_PMB_ZONES_VDSL3_CORE 0 + +#define UBUS_PMB_BUS_VDSL3_MIPS PMB_BUS_VDSL3_MIPS +#define UBUS_PMB_ADDR_VDSL3_MIPS (25 | UBUS_PMB_BUS_VDSL3_MIPS << PMB_BUS_ID_SHIFT) +#define UBUS_PMB_ZONES_VDSL3_MIPS 0 + +#define UBUS_PMB_BUS_DECT PMB_BUS_DECT_UBUS +#define UBUS_PMB_ADDR_DECT (26 | UBUS_PMB_BUS_DECT << PMB_BUS_ID_SHIFT) +#define UBUS_PMB_ZONES_DECT 0 + +#define UBUS_PMB_BUS_ARM PMB_BUS_URB +#define UBUS_PMB_ADDR_ARM (27 | UBUS_PMB_BUS_ARM << PMB_BUS_ID_SHIFT) +#define UBUS_PMB_ZONES_ARM 0 + +#define UBUS_PMB_BUS_DAP PMB_BUS_URB +#define UBUS_PMB_ADDR_DAP (28 | UBUS_PMB_BUS_DAP << PMB_BUS_ID_SHIFT) +#define UBUS_PMB_ZONES_DAP 0 + +#define UBUS_CFG0_PMB_BUS_SAR PMB_BUS_SAR +#define UBUS_CFG0_PMB_ADDR_SAR (29 | UBUS_CFG0_PMB_BUS_SAR << PMB_BUS_ID_SHIFT) +#define UBUS_CFG0_PMB_ZONES_SAR 0 + +#define UBUS_CFG1_PMB_BUS_SAR PMB_BUS_SAR +#define UBUS_CFG1_PMB_ADDR_SAR (30 | UBUS_CFG1_PMB_BUS_SAR << PMB_BUS_ID_SHIFT) +#define UBUS_CFG1_PMB_ZONES_SAR 0 + +#define UBUS_CFG_PMB_BUS_DBR PMB_BUS_RDP +#define UBUS_CFG_PMB_ADDR_DBR (31 | UBUS_CFG_PMB_BUS_DBR << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_DBR 0 + +#define UBUS_CFG_PMB_BUS_RABR PMB_BUS_RDP +#define UBUS_CFG_PMB_ADDR_RABR (32 | UBUS_CFG_PMB_BUS_RABR << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_RABR 0 + +#define UBUS_CFG_PMB_BUS_RBBR PMB_BUS_RDP +#define UBUS_CFG_PMB_ADDR_RBBR (33 | UBUS_CFG_PMB_BUS_RBBR << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_RBBR 0 + +#define UBUS_CFG_PMB_BUS_APM PMB_BUS_APM +#define UBUS_CFG_PMB_ADDR_APM (34 | UBUS_CFG_PMB_BUS_APM << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_APM 0 + +#define UBUS_CFG_PMB_BUS_PCIE0 PMB_BUS_PCIE0 +#define UBUS_CFG_PMB_ADDR_PCIE0 (35 | UBUS_CFG_PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_PCIE0 0 + +#define UBUS_CFG_PMB_BUS_PCIE1 PMB_BUS_PCIE1 +#define UBUS_CFG_PMB_ADDR_PCIE1 (36 | UBUS_CFG_PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_PCIE1 0 + +#define UBUS_CFG_PMB_BUS_USBH PMB_BUS_USB30_2X +#define UBUS_CFG_PMB_ADDR_USBH (37 | UBUS_CFG_PMB_BUS_USBH << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_USBH 0 + +#define UBUS_CFG_PMB_BUS_USBD PMB_BUS_USB30_2X +#define UBUS_CFG_PMB_ADDR_USBD (38 | UBUS_CFG_PMB_BUS_USBD << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_USBD 0 + +#define UBUS_CFG_PMB_BUS_SWITCH PMB_BUS_SWITCH +#define UBUS_CFG_PMB_ADDR_SWITCH (39 | UBUS_CFG_PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_SWITCH 0 + +#define UBUS_CFG_PMB_BUS_PERIPH PMB_BUS_PERIPH +#define UBUS_CFG_PMB_ADDR_PERIPH (40 | UBUS_CFG_PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_PERIPH 0 + +#define UBUS_CFG_PMB_BUS_SATA PMB_BUS_SATA +#define UBUS_CFG_PMB_ADDR_SATA (41 | UBUS_CFG_PMB_BUS_SATA << PMB_BUS_ID_SHIFT) +#define UBUS_CFG_PMB_ZONES_SATA 0 + +#define PMB_BUS_B15_CPU0 0 // can't find it yet +#define PMB_ADDR_B15_CPU0 (42 | PMB_BUS_B15_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_B15_CPU0 1 + +#define PMB_BUS_B15_CPU1 0 // can't find it yet +#define PMB_ADDR_B15_CPU1 (43 | PMB_BUS_B15_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_B15_CPU1 1 + +#define PMB_BUS_B15_L2 0 // can't find it yet +#define PMB_ADDR_B15_L2 (44 | PMB_BUS_B15_L2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_B15_L2 1 + +/* define Zone enum for each block here */ +#ifndef _LANGUAGE_ASSEMBLY +enum { + APM_Zone_Main, + APM_Zone_Audio, + APM_Zone_PCM, + APM_Zone_HVG, + APM_Zone_BMU, +}; +#endif + +#endif diff --git a/plat/bcm/include/pmc_addr_63158.h b/plat/bcm/include/pmc_addr_63158.h new file mode 100644 index 00000000..e4bbdfb5 --- /dev/null +++ b/plat/bcm/include/pmc_addr_63158.h @@ -0,0 +1,197 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_63158_H__ +#define PMC_ADDR_63158_H__ + +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 8 + +#define PMB_BUS_PERIPH 1 +#define PMB_ADDR_PERIPH (3 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 4 + +#define PMB_BUS_CHIP_CLKRST 0 +#define PMB_ADDR_CHIP_CLKRST (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define BPCM_CLKRST_AFE_PWRDWN 0x80000000 + +#define PMB_BUS_SYSPLL 0 +#define PMB_ADDR_SYSPLL (4 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL 0 + +#define PMB_BUS_RDPPLL 0 +#define PMB_ADDR_RDPPLL (6 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_RDPPLL 0 + +#define PMB_BUS_UBUSPLL 0 +#define PMB_ADDR_UBUSPLL (5 | PMB_BUS_UBUSPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_UBUSPLL 0 + +#define PMB_BUS_MEMC 0 +#define PMB_ADDR_MEMC (2 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_SYNC_PLL 1 +#define PMB_ADDR_SYNC_PLL (7 | PMB_BUS_SYNC_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYNC_PLL 1 + +#define PMB_BUS_USB30_2X 1 +#define PMB_ADDR_USB30_2X (13 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB30_2X 4 + +#define PMB_BUS_WAN 1 +#define PMB_ADDR_WAN (15 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WAN 7 + +#define PMB_BUS_XRDP 1 +#define PMB_ADDR_XRDP (16 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP 3 + +#define PMB_BUS_PCIE0 0 +#define PMB_ADDR_PCIE0 (8 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_PCIE1 0 +#define PMB_ADDR_PCIE1 (9 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1 1 + +#define PMB_BUS_PCIE2 0 +#define PMB_ADDR_PCIE2 (10 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE2 1 + +#define PMB_BUS_PCIE3 1 +#define PMB_ADDR_PCIE3 (12 | PMB_BUS_PCIE3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE3 1 + +#define PMB_BUS_SATA 0 +#define PMB_ADDR_SATA (11 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SATA 1 + +#define PMB_BUS_SGMII 1 +#define PMB_ADDR_SGMII (14 | PMB_BUS_SGMII << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SGMII 0 + +#define PMB_BUS_SWITCH 1 +#define PMB_ADDR_SWITCH (0 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SWITCH 4 + +#define PMB_BUS_XRDP_RC0 1 +#define PMB_ADDR_XRDP_RC0 (17 | PMB_BUS_XRDP_RC0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC0 1 + +#define PMB_BUS_XRDP_RC1 1 +#define PMB_ADDR_XRDP_RC1 (18 | PMB_BUS_XRDP_RC1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC1 1 + +#define PMB_BUS_XRDP_RC2 1 +#define PMB_ADDR_XRDP_RC2 (19 | PMB_BUS_XRDP_RC2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC2 1 + +#define PMB_BUS_XRDP_RC3 1 +#define PMB_ADDR_XRDP_RC3 (20 | PMB_BUS_XRDP_RC3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC3 1 + +#define PMB_BUS_XRDP_RC4 1 +#define PMB_ADDR_XRDP_RC4 (21 | PMB_BUS_XRDP_RC4 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC4 1 + +#define PMB_BUS_XRDP_RC5 1 +#define PMB_ADDR_XRDP_RC5 (22 | PMB_BUS_XRDP_RC5 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC5 1 + +#define PMB_BUS_VDSL3_CORE 0 +#define PMB_ADDR_VDSL3_CORE (23 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_VDSL3_CORE 1 + +#define PMB_BUS_VDSL3_MIPS PMB_BUS_VDSL3_CORE +#define PMB_ADDR_VDSL3_MIPS PMB_ADDR_VDSL3_CORE +#define PMB_ZONES_VDSL3_MIPS PMB_ZONES_VDSL3_CORE + +#define PMB_BUS_VDSL3_PMD 0 +#define PMB_ADDR_VDSL3_PMD (24 | PMB_BUS_VDSL3_PMD << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_VDSL3_PMD 1 + +//--------- DGASP related bits/Offsets ------------------------ +#define BPCM_PHY_CNTL_OVERRIDE 0x08000000 +#define PMB_ADDR_VDSL_DGASP_PMD PMB_ADDR_VDSL3_PMD +#define BPCM_VDSL_PHY_CTL_REG global_control // Alias for register containing DGASP override inside the VDSL PMD +#define BPCM_VDSL_AFE_CTL_REG misc_control // Alias for register containing DGASP configuration inside the VDSL PMD + +#define PMB_BUS_CRYPTO 0 +#define PMB_ADDR_CRYPTO (25 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CRYPTO 1 + +#define AFEPLL_PMB_BUS_VDSL3_CORE 0 +#define AFEPLL_PMB_ADDR_VDSL3_CORE (26 | AFEPLL_PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT) +#define AFEPLL_PMB_ZONES_VDSL3_CORE 0 + +#define PMB_BUS_ORION_CPU0 0 +#define PMB_ADDR_ORION_CPU0 (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU0 1 + +#define PMB_BUS_ORION_CPU1 0 +#define PMB_ADDR_ORION_CPU1 (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU1 1 + +#define PMB_BUS_ORION_CPU2 0 +#define PMB_ADDR_ORION_CPU2 (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU2 1 + +#define PMB_BUS_ORION_CPU3 0 +#define PMB_ADDR_ORION_CPU3 (35 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU3 1 + +#define PMB_BUS_ORION_NONCPU 0 +#define PMB_ADDR_ORION_NONCPU (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_NONCPU 1 + +#define PMB_BUS_ORION_ARS 0 +#define PMB_ADDR_ORION_ARS (37 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_ARS 0 + +#define PMB_BUS_BIU_PLL 0 +#define PMB_ADDR_BIU_PLL (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_PLL 0 + +#define PMB_BUS_BIU_BPCM 0 +#define PMB_ADDR_BIU_BPCM (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_BPCM 1 + +#define PMB_BUS_ORION_C0_ARS 0 +#define PMB_ADDR_ORION_C0_ARS (45 | PMB_BUS_ORION_C0_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_C0_ARS 0 + +#define PMB_BUS_PCM 1 +#define PMB_ADDR_PCM (3 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCM 4 + +enum { + PCM_Zone_Main, + PCM_Zone_PCM = 3 +}; +//--------- SOFT Reset bits for PCM ------------------------ +#define BPCM_PCM_SRESET_PCM_N 0x00000040 + +#endif diff --git a/plat/bcm/include/pmc_addr_63178.h b/plat/bcm/include/pmc_addr_63178.h new file mode 100644 index 00000000..3f5855a9 --- /dev/null +++ b/plat/bcm/include/pmc_addr_63178.h @@ -0,0 +1,137 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_63178_H__ +#define PMC_ADDR_63178_H__ + +#define PMB_BUS_ID_SHIFT 12 + +#define PMB_BUS_PERIPH 0 +#define PMB_ADDR_PERIPH (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 4 + +#define PMB_BUS_CHIP_CLKRST 0 +#define PMB_ADDR_CHIP_CLKRST (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define BPCM_CLKRST_AFE_PWRDWN 0x20000000 + +#define PMB_BUS_AFEPLL 0 +#define PMB_ADDR_AFEPLL (2 | PMB_BUS_AFEPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_AFEPLL 0 + +#define AFEPLL_PMB_BUS_VDSL3_CORE PMB_BUS_AFEPLL +#define AFEPLL_PMB_ADDR_VDSL3_CORE PMB_ADDR_AFEPLL +#define AFEPLL_PMB_ZONES_VDSL3_CORE PMB_ZONES_AFEPLL + +#define PMB_BUS_PVTMON 0 +#define PMB_ADDR_PVTMON (3 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PVTMON 0 + +#define PMB_BUS_SWITCH 0 +#define PMB_ADDR_SWITCH (4 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SWITCH 4 + +#define PMB_BUS_USB30_2X 0 +#define PMB_ADDR_USB30_2X (5 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB30_2X 4 + +#define PMB_BUS_PCIE0 1 +#define PMB_ADDR_PCIE0 (6 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_VDSL3_CORE 1 +#define PMB_ADDR_VDSL3_CORE (7 | PMB_BUS_VDSL3_CORE << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_VDSL3_CORE 2 + +#define PMB_BUS_VDSL3_MIPS PMB_BUS_VDSL3_CORE +#define PMB_ADDR_VDSL3_MIPS PMB_ADDR_VDSL3_CORE +#define PMB_ZONES_VDSL3_MIPS PMB_ZONES_VDSL3_CORE + +//--------- DGASP related bits/Offsets ------------------------ +#define BPCM_PHY_CNTL_OVERRIDE 0x08000000 +#define PMB_ADDR_VDSL_DGASP_PMD PMB_ADDR_VDSL3_CORE +#define BPCM_VDSL_PHY_CTL_REG vdsl_phy_ctl // Alias for register containing DGASP override inside the VDSL PMD +#define BPCM_VDSL_AFE_CTL_REG vdsl_afe_ctl // Alias for register containing DGASP configuration inside the VDSL PMD + +#define PMB_BUS_MEMC 1 +#define PMB_ADDR_MEMC (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_WLAN0_PHY1 0 +#define PMB_ADDR_WLAN0_PHY1 (9 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0_PHY1 1 + +#define PMB_BUS_WLAN0_PHY2 0 +#define PMB_ADDR_WLAN0_PHY2 (10 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0_PHY2 1 + +#define PMB_BUS_WLAN0 0 +#define PMB_ADDR_WLAN0 (11 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0 1 + +#define PMB_BUS_ORION_CPU0 1 +#define PMB_ADDR_ORION_CPU0 (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU0 1 + +#define PMB_BUS_ORION_CPU1 1 +#define PMB_ADDR_ORION_CPU1 (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU1 1 + +#define PMB_BUS_ORION_CPU2 1 +#define PMB_ADDR_ORION_CPU2 (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU2 1 + +#define PMB_BUS_ORION_NONCPU 1 +#define PMB_ADDR_ORION_NONCPU (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_NONCPU 1 + +#define PMB_BUS_BIU_PLL 1 +#define PMB_ADDR_BIU_PLL (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_PLL 0 + +#define PMB_BUS_BIU_BPCM 1 +#define PMB_ADDR_BIU_BPCM (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_BPCM 1 + +#define PMB_BUS_PCM PMB_BUS_PERIPH +#define PMB_ADDR_PCM (0 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCM 4 + +enum { + PCM_Zone_Main, + PCM_Zone_PCM = 3 +}; +//--------- SOFT Reset bits for PCM ------------------------ +#define BPCM_PCM_SRESET_PCM_N 0x00000040 + +#define RCAL_0P25UM_HORZ 0 +#define RCAL_0P25UM_VERT 1 +#define RCAL_0P5UM_HORZ 2 +#define RCAL_0P5UM_VERT 3 +#define RCAL_1UM_HORZ 4 +#define RCAL_1UM_VERT 5 +#define PMMISC_RMON_EXT_REG ((RCAL_1UM_VERT + 1)/2) +#define PMMISC_RMON_VALID_MASK (0x1<<16) + +#endif diff --git a/plat/bcm/include/pmc_addr_6756.h b/plat/bcm/include/pmc_addr_6756.h new file mode 100644 index 00000000..d93e7568 --- /dev/null +++ b/plat/bcm/include/pmc_addr_6756.h @@ -0,0 +1,122 @@ +/* +<:copyright-BRCM:2020:DUAL/GPL:standard + + Copyright (c) 2020 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> + +*/ +#ifndef PMC_ADDR_6756_H__ +#define PMC_ADDR_6756_H__ + +#define PMB_BUS_ID_SHIFT 12 + +#define PMB_BUS_PERIPH 1 +#define PMB_ADDR_PERIPH (16 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 4 + +#define PMB_BUS_CRYPTO 0 +#define PMB_ADDR_CRYPTO (1 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CRYPTO 1 + +#define PMB_BUS_PVTMON 0 +#define PMB_ADDR_PVTMON (2 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PVTMON 0 + +#define PMB_BUS_CHIP_CLKRST 0 +#define PMB_ADDR_CHIP_CLKRST (3 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_USB31_20 0 +#define PMB_ADDR_USB31_20 (4 | PMB_BUS_USB31_20 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB31_20 4 + +#define PMB_BUS_WLAN0 0 +#define PMB_ADDR_WLAN0 (5 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0 1 + +#define PMB_BUS_WLAN0_PHY1 0 +#define PMB_ADDR_WLAN0_PHY1 (6 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0_PHY1 1 + +#define PMB_BUS_WLAN0_PHY2 0 +#define PMB_ADDR_WLAN0_PHY2 (7 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0_PHY2 1 + +#define PMB_BUS_WLAN1 0 +#define PMB_ADDR_WLAN1 (8 | PMB_BUS_WLAN1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN1 1 + +#define PMB_BUS_WLAN1_PHY1 0 +#define PMB_ADDR_WLAN1_PHY1 (9 | PMB_BUS_WLAN1_PHY1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN1_PHY1 1 + +#define PMB_BUS_WLAN1_PHY2 0 +#define PMB_ADDR_WLAN1_PHY2 (10 | PMB_BUS_WLAN1_PHY2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN1_PHY2 1 + +#define PMB_BUS_MEMC 0 +#define PMB_ADDR_MEMC (11 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_SWITCH 0 +#define PMB_ADDR_SWITCH (12 | PMB_BUS_SWITCH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SWITCH 5 + +#define PMB_BUS_PCIE0 1 +#define PMB_ADDR_PCIE0 (17 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_ORION_CPU0 0 +#define PMB_ADDR_ORION_CPU0 (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU0 1 + +#define PMB_BUS_ORION_CPU1 0 +#define PMB_ADDR_ORION_CPU1 (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU1 1 + +#define PMB_BUS_ORION_CPU2 0 +#define PMB_ADDR_ORION_CPU2 (34 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU2 1 + +#define PMB_BUS_ORION_CPU3 0 +#define PMB_ADDR_ORION_CPU3 (35 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU3 1 + +#define PMB_BUS_ORION_NONCPU 0 +#define PMB_ADDR_ORION_NONCPU (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_NONCPU 1 + +#define PMB_BUS_BIU_PLL 0 +#define PMB_ADDR_BIU_PLL (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_PLL 0 + +#define PMB_BUS_BIU_BPCM 0 +#define PMB_ADDR_BIU_BPCM (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_BPCM 1 + +#define RCAL_0P25UM_HORZ 0 +#define RCAL_0P25UM_VERT 1 +#define RCAL_0P5UM_HORZ 2 +#define RCAL_0P5UM_VERT 3 +#define RCAL_1UM_HORZ 4 +#define RCAL_1UM_VERT 5 +#define PMMISC_RMON_EXT_REG ((RCAL_1UM_VERT + 1)/2) +#define PMMISC_RMON_VALID_MASK (0x1<<16) + +#endif diff --git a/plat/bcm/include/pmc_addr_6813.h b/plat/bcm/include/pmc_addr_6813.h new file mode 100644 index 00000000..5fa03e47 --- /dev/null +++ b/plat/bcm/include/pmc_addr_6813.h @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Broadcom Ltd. + */ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +Unless you and Broadcom execute a separate written software license +agreement governing use of this software, this software is licensed +to you under the terms of the GNU General Public License version 2 +(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php, +with the following added to such license: + + As a special exception, the copyright holders of this software give + you permission to link this software with independent modules, and + to copy and distribute the resulting executable under terms of your + choice, provided that you also meet, for each linked independent + module, the terms and conditions of the license of that module. + An independent module is a module which is not derived from this + software. The special exception does not apply to any modifications + of the software. + +Not withstanding the above, under no circumstances may you combine +this software in any way with any other Broadcom software provided +under a license other than the GPL, without Broadcom's express prior +written consent. + +:> +*/ + +#ifndef _6813_PMC_ADDR_H +#define _6813_PMC_ADDR_H + +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 12 + +#define PMB_BUS_PERIPH 0 +#define PMB_ADDR_PERIPH (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 4 + +#define PMB_BUS_CHIP_CLKRST 0 +#define PMB_ADDR_CHIP_CLKRST (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_PVTMON 1 +#define PMB_ADDR_PVTMON (3 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PVTMON 0 + +#define PMB_BUS_CRYPTO 1 +#define PMB_ADDR_CRYPTO (4 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CRYPTO 0 + +#define PMB_BUS_USB30_2X 0 +#define PMB_ADDR_USB30_2X (5 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB30_2X 4 + +#define PMB_BUS_PCIE1 1 +#define PMB_ADDR_PCIE1 (6 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1 4 + +// referring to PCIEG3 +#define PMB_BUS_PCIE3 1 +#define PMB_ADDR_PCIE3 (7 | PMB_BUS_PCIE3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE3 1 + +#define PMB_BUS_MEMC 1 +#define PMB_ADDR_MEMC (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_XRDP 1 +#define PMB_ADDR_XRDP (9 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP 1 + +#define PMB_BUS_PCIE2 1 +#define PMB_ADDR_PCIE2 (11 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE2 1 + +#define PMB_BUS_PCIE0 0 +#define PMB_ADDR_PCIE0 (12 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_ETH 1 +#define PMB_ADDR_ETH (13 | PMB_BUS_ETH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ETH 1 + +#define PMB_BUS_MPM 1 +#define PMB_ADDR_MPM (14 | PMB_BUS_MPM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MPM 1 + +#define PMB_BUS_XRDPPLL 0 +#define PMB_ADDR_XRDPPLL (15 | PMB_BUS_XRDPPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDPPLL 0 + +#define PMB_BUS_PERIPH_ARS 0 +#define PMB_ADDR_PERIPH_ARS (16 | PMB_BUS_PERIPH_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH_ARS 0 + +#define PMB_BUS_PCIE0_UBUS_ARS 0 +#define PMB_ADDR_PCIE0_UBUS_ARS (17 | PMB_BUS_PCIE0_UBUS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0_UBUS_ARS 0 + +#define PMB_BUS_USB30_2X_ARS 0 +#define PMB_ADDR_USB30_2X_ARS (18 | PMB_BUS_USB30_2X_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB30_2X_ARS 0 + +#define PMB_BUS_SYS_ARS 0 +#define PMB_ADDR_SYS_ARS (19 | PMB_BUS_SYS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYS_ARS 0 + +#define PMB_BUS_CRYPTO2_ARS 1 +#define PMB_ADDR_CRYPTO2_ARS (20 | PMB_BUS_CRYPTO2_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CRYPTO2_ARS 0 + +#define PMB_BUS_XRDP_ARS 1 +#define PMB_ADDR_XRDP_ARS (21 | PMB_BUS_XRDP_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_ARS 0 + +#define PMB_BUS_MPM_ARS 1 +#define PMB_ADDR_MPM_ARS (22 | PMB_BUS_MPM_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MPM_ARS 0 + +#define PMB_BUS_MEMC_ARS 1 +#define PMB_ADDR_MEMC_ARS (23 | PMB_BUS_MEMC_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC_ARS 0 + +#define PMB_BUS_ETH_ARS 1 +#define PMB_ADDR_ETH_ARS (24 | PMB_BUS_ETH_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ETH_ARS 0 + +#define PMB_BUS_PCIE1_UBUS_ARS 1 +#define PMB_ADDR_PCIE1_UBUS_ARS (25 | PMB_BUS_PCIE1_UBUS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1_UBUS_ARS 0 + +#define PMB_BUS_PCIE3_ARS 1 +#define PMB_ADDR_PCIE3_ARS (26 | PMB_BUS_PCIE3_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE3_ARS 0 + +#define PMB_BUS_MERLIN0_UBUS_ARS 1 +#define PMB_ADDR_MERLIN0_UBUS_ARS (27 | PMB_BUS_MERLIN0_UBUS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MERLIN0_UBUS_ARS 0 + +#define PMB_BUS_MERLIN1_UBUS_ARS 1 +#define PMB_ADDR_MERLIN1_UBUS_ARS (28 | PMB_BUS_MERLIN1_UBUS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MERLIN1_UBUS_ARS 0 + +#define PMB_BUS_MERLIN2_UBUS_ARS 1 +#define PMB_ADDR_MERLIN2_UBUS_ARS (29 | PMB_BUS_MERLIN2_UBUS_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MERLIN2_UBUS_ARS 0 + +#define PMB_BUS_ORION_PLL 1 +#define PMB_ADDR_ORION_PLL (32 | PMB_BUS_ORION_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_PLL 0 +#define PMB_BUS_BIU_PLL PMB_BUS_ORION_PLL +#define PMB_ADDR_BIU_PLL PMB_ADDR_ORION_PLL +#define PMB_ZONES_BIU_PLL PMB_ZONES_ORION_PLL + +#define PMB_BUS_ORION_BPCM 1 +#define PMB_ADDR_ORION_BPCM (33 | PMB_BUS_ORION_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_BPCM 1 +#define PMB_BUS_BIU_BPCM PMB_BUS_ORION_BPCM +#define PMB_ADDR_BIU_BPCM PMB_ADDR_ORION_BPCM +#define PMB_ZONES_BIU_BPCM PMB_ZONES_ORION_BPCM + +#define PMB_BUS_ORION_CPU0 1 +#define PMB_ADDR_ORION_CPU0 (34 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU0 1 + +#define PMB_BUS_ORION_CPU1 1 +#define PMB_ADDR_ORION_CPU1 (35 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU1 1 + +#define PMB_BUS_ORION_CPU2 1 +#define PMB_ADDR_ORION_CPU2 (36 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU2 1 + +#define PMB_BUS_ORION_CPU3 1 +#define PMB_ADDR_ORION_CPU3 (37 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU3 1 + +#define PMB_BUS_ORION_NONCPU 1 +#define PMB_ADDR_ORION_NONCPU (38 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_NONCPU 1 + +#define PMB_BUS_ORION_ARS 1 +#define PMB_ADDR_ORION_ARS (39 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_ARS 0 + +#define PMB_BUS_ORION_ACEBIU_ARS 1 +#define PMB_ADDR_ORION_ACEBIU_ARS (40 | PMB_BUS_ORION_ACEBIU_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_ACEBIU_ARS 0 +#endif diff --git a/plat/bcm/include/pmc_addr_6846.h b/plat/bcm/include/pmc_addr_6846.h new file mode 100644 index 00000000..a61d31b9 --- /dev/null +++ b/plat/bcm/include/pmc_addr_6846.h @@ -0,0 +1,90 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_6846_H__ +#define PMC_ADDR_6846_H__ + +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 12 + +#define PMB_BUS_PERIPH 0 +#define PMB_ADDR_PERIPH (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 4 + +#define PMB_BUS_CHIP_CLKRST 1 +#define PMB_ADDR_CHIP_CLKRST (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_RDPPLL 1 +#define PMB_ADDR_RDPPLL (3 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_RDPPLL 0 + +#define PMB_BUS_PVTMON 1 +#define PMB_ADDR_PVTMON (6 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PVTMON 0 + +#define PMB_BUS_MEMC 1 +#define PMB_ADDR_MEMC (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_USB20_2X 1 +#define PMB_ADDR_USB20_2X (10 | PMB_BUS_USB20_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB20_2X 4 + +#define PMB_BUS_WAN 1 +#define PMB_ADDR_WAN (11 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WAN 3 + +#define PMB_BUS_XRDP 1 +#define PMB_ADDR_XRDP (12 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP 3 + +#define PMB_BUS_XRDP_RC0 1 +#define PMB_ADDR_XRDP_RC0 (14 | PMB_BUS_XRDP_RC0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC0 1 + +#define PMB_BUS_XRDP_RC1 1 +#define PMB_ADDR_XRDP_RC1 (15 | PMB_BUS_XRDP_RC1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC1 1 + +#define PMB_BUS_XRDP_RC2 1 +#define PMB_ADDR_XRDP_RC2 (16 | PMB_BUS_XRDP_RC2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC2 1 + +#define PMB_BUS_PCIE0 0 +#define PMB_ADDR_PCIE0 (18 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_PCIE1 0 +#define PMB_ADDR_PCIE1 (19 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1 1 + +#define PMB_BUS_BIU_PLL 1 +#define PMB_ADDR_BIU_PLL (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_PLL 1 + +#define PMB_BUS_BIU_BPCM 1 +#define PMB_ADDR_BIU_BPCM (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_BPCM 1 + +#endif diff --git a/plat/bcm/include/pmc_addr_6855.h b/plat/bcm/include/pmc_addr_6855.h new file mode 100644 index 00000000..2f24616c --- /dev/null +++ b/plat/bcm/include/pmc_addr_6855.h @@ -0,0 +1,106 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_6855_H__ +#define PMC_ADDR_6855_H__ + +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 12 + +#define PMB_BUS_PERIPH 0 +#define PMB_ADDR_PERIPH (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 4 + +#define PMB_BUS_CHIP_CLKRST 0 +#define PMB_ADDR_CHIP_CLKRST (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_SYSPLL 0 +#define PMB_ADDR_SYSPLL (3 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL 0 + +#define PMB_BUS_PVTMON 0 +#define PMB_ADDR_PVTMON (6 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PVTMON 0 + +#define PMB_BUS_MEMC 0 +#define PMB_ADDR_MEMC (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_USB20_2X 1 +#define PMB_ADDR_USB20_2X (10 | PMB_BUS_USB20_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB20_2X 4 + +#define PMB_BUS_WAN 1 +#define PMB_ADDR_WAN (11 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WAN 3 + +#define PMB_BUS_XRDP 1 +#define PMB_ADDR_XRDP (12 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP 3 + +#define PMB_BUS_PCIE0 1 +#define PMB_ADDR_PCIE0 (17 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_PCIE1 1 +#define PMB_ADDR_PCIE1 (18 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1 1 + +#define PMB_BUS_WLAN0 1 +#define PMB_ADDR_WLAN0 (19 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0 1 + +#define PMB_BUS_WLAN0_PHY1 1 +#define PMB_ADDR_WLAN0_PHY1 (20 | PMB_BUS_WLAN0_PHY1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0_PHY1 1 + +#define PMB_BUS_WLAN0_PHY2 1 +#define PMB_ADDR_WLAN0_PHY2 (21 | PMB_BUS_WLAN0_PHY2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0_PHY2 1 + +#define PMB_BUS_ORION_CPU0 0 +#define PMB_ADDR_ORION_CPU0 (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU0 1 + +#define PMB_BUS_ORION_CPU1 0 +#define PMB_ADDR_ORION_CPU1 (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU1 1 + +#define PMB_BUS_ORION_CPU2 0 +#define PMB_ADDR_ORION_CPU2 (33 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU2 1 + +#define PMB_BUS_ORION_NONCPU 0 +#define PMB_ADDR_ORION_NONCPU (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_NONCPU 1 + +#define PMB_BUS_BIU_PLL 0 +#define PMB_ADDR_BIU_PLL (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_PLL 0 + +#define PMB_BUS_BIU_BPCM 0 +#define PMB_ADDR_BIU_BPCM (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_BPCM 1 + +#endif diff --git a/plat/bcm/include/pmc_addr_6856.h b/plat/bcm/include/pmc_addr_6856.h new file mode 100644 index 00000000..44246bad --- /dev/null +++ b/plat/bcm/include/pmc_addr_6856.h @@ -0,0 +1,132 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_6856_H__ +#define PMC_ADDR_6856_H__ + +/* TODO: FIXME Verify the correctness of the bpcms*/ + +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 12 + +#define PMB_BUS_PERIPH 0 +#define PMB_ADDR_PERIPH (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 4 + +#define PMB_BUS_MEMC 0 +#define PMB_ADDR_MEMC (1 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_PVTMON 0 +#define PMB_ADDR_PVTMON (2 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PVTMON 0 + +#define PMB_BUS_CHIP_CLKRST 0 +#define PMB_ADDR_CHIP_CLKRST (3 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_USB30_2X 0 +#define PMB_ADDR_USB30_2X (4 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB30_2X 4 + +#define PMB_BUS_SYSPLL 0 +#define PMB_ADDR_SYSPLL (5 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL 0 + +#define PMB_BUS_RDPPLL 0 +#define PMB_ADDR_RDPPLL (6 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_RDPPLL 0 + +#define PMB_BUS_PCIE0 1 +#define PMB_ADDR_PCIE0 (7 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_PCIE1 1 +#define PMB_ADDR_PCIE1 (8 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1 1 + +#define PMB_BUS_PCIE2 1 +#define PMB_ADDR_PCIE2 (9 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE2 1 + +#define PMB_BUS_XRDP 1 +#define PMB_ADDR_XRDP (10 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP 3 + +#define PMB_BUS_XRDP_RC0 1 +#define PMB_ADDR_XRDP_RC0 (11 | PMB_BUS_XRDP_RC0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC0 1 + +#define PMB_BUS_XRDP_RC1 1 +#define PMB_ADDR_XRDP_RC1 (12 | PMB_BUS_XRDP_RC1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC1 1 + +#define PMB_BUS_XRDP_RC2 1 +#define PMB_ADDR_XRDP_RC2 (13 | PMB_BUS_XRDP_RC2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC2 1 + +#define PMB_BUS_XRDP_RC3 1 +#define PMB_ADDR_XRDP_RC3 (14 | PMB_BUS_XRDP_RC3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC3 1 + +#define PMB_BUS_XRDP_RC4 1 +#define PMB_ADDR_XRDP_RC4 (15 | PMB_BUS_XRDP_RC4 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC4 1 + +#define PMB_BUS_XRDP_RC5 1 +#define PMB_ADDR_XRDP_RC5 (16 | PMB_BUS_XRDP_RC5 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC5 1 + +#define PMB_BUS_XRDP_RC6 1 +#define PMB_ADDR_XRDP_RC6 (17 | PMB_BUS_XRDP_RC6 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC6 1 + +#define PMB_BUS_XRDP_RC7 1 +#define PMB_ADDR_XRDP_RC7 (18 | PMB_BUS_XRDP_RC7 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC7 1 + +#define PMB_BUS_WAN 1 +#define PMB_ADDR_WAN (19 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WAN 6 + +#define PMB_BUS_ORION_CPU0 0 +#define PMB_ADDR_ORION_CPU0 (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU0 1 + +#define PMB_BUS_ORION_CPU1 0 +#define PMB_ADDR_ORION_CPU1 (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU1 1 + +#define PMB_BUS_ORION_NONCPU 0 +#define PMB_ADDR_ORION_NONCPU (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_NONCPU 1 + +#define PMB_BUS_BIU_PLL 0 +#define PMB_ADDR_BIU_PLL (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_PLL 1 + +#define PMB_BUS_BIU_BPCM 0 +#define PMB_ADDR_BIU_BPCM (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_BPCM 1 + +#endif diff --git a/plat/bcm/include/pmc_addr_6858.h b/plat/bcm/include/pmc_addr_6858.h new file mode 100644 index 00000000..5e7f0a4c --- /dev/null +++ b/plat/bcm/include/pmc_addr_6858.h @@ -0,0 +1,162 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_6858_H__ +#define PMC_ADDR_6858_H__ + +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 8 + +#define PMB_BUS_PERIPH 0 +#define PMB_ADDR_PERIPH (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 3 + +#define PMB_BUS_CHIP_CLKRST 0 +#define PMB_ADDR_CHIP_CLKRST (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_SYSPLL 0 +#define PMB_ADDR_SYSPLL (2 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL 0 + +#define PMB_BUS_RDPPLL 0 +#define PMB_ADDR_RDPPLL (3 | PMB_BUS_RDPPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_RDPPLL 0 + +#define PMB_BUS_UNIPLL 0 +#define PMB_ADDR_UNIPLL (5 | PMB_BUS_UNIPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_UNIPLL 0 + +#define PMB_BUS_CRYPTO 1 +#define PMB_ADDR_CRYPTO (6 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CRYPTO 0 + +#define PMB_BUS_APM 0 +#define PMB_ADDR_APM (7 | PMB_BUS_APM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_APM 2 + +#define PMB_BUS_MEMC 0 +#define PMB_ADDR_MEMC (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_LPORT 1 +#define PMB_ADDR_LPORT (9 | PMB_BUS_LPORT << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_LPORT 3 + +#define PMB_BUS_USB30_2X 1 +#define PMB_ADDR_USB30_2X (10 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB30_2X 4 + +#define PMB_BUS_WAN 1 +#define PMB_ADDR_WAN (11 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WAN 7 + +#define PMB_BUS_XRDP 1 +#define PMB_ADDR_XRDP (12 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP 3 + +#define PMB_BUS_XRDP_QM 1 +#define PMB_ADDR_XRDP_QM (13 | PMB_BUS_XRDP_QM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_QM 1 + +#define PMB_BUS_XRDP_RC_QUAD0 1 +#define PMB_ADDR_XRDP_RC_QUAD0 (14 | PMB_BUS_XRDP_RC_QUAD0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC_QUAD0 1 + +#define PMB_BUS_XRDP_RC_QUAD1 1 +#define PMB_ADDR_XRDP_RC_QUAD1 (15 | PMB_BUS_XRDP_RC_QUAD1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC_QUAD1 1 + +#define PMB_BUS_XRDP_RC_QUAD2 1 +#define PMB_ADDR_XRDP_RC_QUAD2 (16 | PMB_BUS_XRDP_RC_QUAD2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC_QUAD2 1 + +#define PMB_BUS_XRDP_RC_QUAD3 1 +#define PMB_ADDR_XRDP_RC_QUAD3 (17 | PMB_BUS_XRDP_RC_QUAD3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP_RC_QUAD3 1 + +#define PMB_BUS_PCIE0 1 +#define PMB_ADDR_PCIE0 (18 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_PCIE1 1 +#define PMB_ADDR_PCIE1 (19 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE1 1 + +#define PMB_BUS_SATA 1 +#define PMB_ADDR_SATA (20 | PMB_BUS_SATA << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SATA 1 + +#define PMB_BUS_PCIE_UBUS 1 +#define PMB_ADDR_PCIE_UBUS (21 | PMB_BUS_PCIE_UBUS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE_UBUS 1 + +#define PMB_BUS_ORION_CPU0 0 +#define PMB_ADDR_ORION_CPU0 (24 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU0 1 + +#define PMB_BUS_ORION_CPU1 0 +#define PMB_ADDR_ORION_CPU1 (25 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU1 1 + +#define PMB_BUS_ORION_CPU2 0 +#define PMB_ADDR_ORION_CPU2 (26 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU2 1 + +#define PMB_BUS_ORION_CPU3 0 +#define PMB_ADDR_ORION_CPU3 (27 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU3 1 + +#define PMB_BUS_ORION_NONCPU 0 +#define PMB_ADDR_ORION_NONCPU (28 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_NONCPU 1 + +#define PMB_BUS_ORION_ARS 0 +#define PMB_ADDR_ORION_ARS (29 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_ARS 1 + +#define PMB_BUS_BIU_PLL 0 +#define PMB_ADDR_BIU_PLL (30 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_PLL 1 // FIXMET + +#define PMB_BUS_BIU_BPCM 0 +#define PMB_ADDR_BIU_BPCM (31 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_BPCM 1 + +#define PMB_BUS_PCM 0 + +#define PMB_ADDR_PCM (0 | PMB_BUS_PCM << PMB_BUS_ID_SHIFT) + +#define PMB_ZONES_PCM 2 +enum { + PCM_Zone_Main, + PCM_Zone_PCM = 3, +}; +//--------- SOFT Reset bits for PCM ------------------------ +#define BPCM_PCM_SRESET_HARDRST_N 0x00000004 + +#define BPCM_PCM_SRESET_PCM_N 0x00000040 + +#define BPCM_PCM_SRESET_BUS_N 0x00000001 + +#endif diff --git a/plat/bcm/include/pmc_addr_6878.h b/plat/bcm/include/pmc_addr_6878.h new file mode 100644 index 00000000..d798cd56 --- /dev/null +++ b/plat/bcm/include/pmc_addr_6878.h @@ -0,0 +1,90 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_ADDR_6878_H__ +#define PMC_ADDR_6878_H__ + +#define PMB_BUS_MAX 2 +#define PMB_BUS_ID_SHIFT 12 + +#define PMB_BUS_PERIPH 0 +#define PMB_ADDR_PERIPH (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PERIPH 3 + +#define PMB_BUS_CHIP_CLKRST 1 +#define PMB_ADDR_CHIP_CLKRST (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_CHIP_CLKRST 0 + +#define PMB_BUS_SYSPLL 1 +#define PMB_ADDR_SYSPLL (3 | PMB_BUS_SYSPLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_SYSPLL 0 + +#define PMB_BUS_PVTMON 1 +#define PMB_ADDR_PVTMON (6 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PVTMON 0 + +#define PMB_BUS_MEMC 1 +#define PMB_ADDR_MEMC (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_MEMC 1 + +#define PMB_BUS_USB20_2X 1 +#define PMB_ADDR_USB20_2X (10 | PMB_BUS_USB20_2X << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_USB20_2X 4 + +#define PMB_BUS_WAN 1 +#define PMB_ADDR_WAN (11 | PMB_BUS_WAN << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WAN 3 + +#define PMB_BUS_XRDP 1 +#define PMB_ADDR_XRDP (12 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_XRDP 3 + +#define PMB_BUS_PCIE0 1 +#define PMB_ADDR_PCIE0 (18 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_PCIE0 1 + +#define PMB_BUS_WLAN0 0 +#define PMB_ADDR_WLAN0 (19 | PMB_BUS_WLAN0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_WLAN0 1 + +#define PMB_BUS_ORION_CPU0 1 +#define PMB_ADDR_ORION_CPU0 (32 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU0 1 + +#define PMB_BUS_ORION_CPU1 1 +#define PMB_ADDR_ORION_CPU1 (33 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_CPU1 1 + +#define PMB_BUS_ORION_NONCPU 1 +#define PMB_ADDR_ORION_NONCPU (36 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_ORION_NONCPU 1 + +#define PMB_BUS_BIU_PLL 1 +#define PMB_ADDR_BIU_PLL (38 | PMB_BUS_BIU_PLL << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_PLL 0 + +#define PMB_BUS_BIU_BPCM 1 +#define PMB_ADDR_BIU_BPCM (39 | PMB_BUS_BIU_BPCM << PMB_BUS_ID_SHIFT) +#define PMB_ZONES_BIU_BPCM 1 + +#endif diff --git a/plat/bcm/include/pmc_cpu_core.h b/plat/bcm/include/pmc_cpu_core.h new file mode 100644 index 00000000..fa8478de --- /dev/null +++ b/plat/bcm/include/pmc_cpu_core.h @@ -0,0 +1,32 @@ +/* +<:copyright-BRCM:2013:DUAL/GPL:standard + + Copyright (c) 2013 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#ifndef PMC_CPU_CORE_H +#define PMC_CPU_CORE_H + +int pmc_cpu_core_power_up(unsigned cpu); +int pmc_cpu_core_power_down(unsigned cpu); +int pmc_cpu_l2cache_power_up(void); +int pmc_cpu_l2cache_power_down(void); + +#endif //#ifndef PMC_CPU_CORE_H diff --git a/plat/bcm/include/pmc_drv.h b/plat/bcm/include/pmc_drv.h new file mode 100644 index 00000000..46902841 --- /dev/null +++ b/plat/bcm/include/pmc_drv.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright 2019 Broadcom Ltd. + */ +/* +<:copyright-BRCM:2013:DUAL/GPL:standard + + Copyright (c) 2013 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +/***************************************************************************** + * Description: + * This contains header for PMC driver. + *****************************************************************************/ + +#ifndef PMC_DRV_H +#define PMC_DRV_H + +#include "pmc_drv_special.h" + +// this is for the host +#define PMC_LITTLE_ENDIAN 1 + +#if IS_BCMCHIP(6846) || IS_BCMCHIP(6856) || IS_BCMCHIP(63178) || \ + IS_BCMCHIP(47622) || IS_BCMCHIP(63146) || IS_BCMCHIP(4912) || \ + IS_BCMCHIP(6756) +#define PMC_IMPL_3_X +#elif IS_BCMCHIP(6878) || IS_BCMCHIP(6855) +#define PMC_ON_HOSTCPU 1 +#else +#define PMC_CPU_BIG_ENDIAN 1 +#endif + +#if IS_BCMCHIP(63178) || IS_BCMCHIP(47622) || IS_BCMCHIP(63146) || \ + IS_BCMCHIP(4912) +#define PMC_LOG_IN_DTCM 1 +#endif + +#if IS_BCMCHIP(63146) || IS_BCMCHIP(4912) +#define PMC_FW_IN_ITCM 1 +#endif + +#if IS_BCMCHIP(6756) +#define PMC_BOOT_TMO_SECONDS 2 +#else +#define PMC_BOOT_TMO_SECONDS 0 +#endif + +#if defined(CFG_RAMAPP) && (defined(PMC_IMPL_3_X) || IS_BCMCHIP(63158)) && \ + !defined(CONFIG_BRCM_IKOS) +#define PMC_RAM_BOOT +//#if defined(PMC_IMPL_3_X) +//#define AVS_DEBUG +//#endif +#if IS_BCMCHIP(63158) +#define PMC_IN_MAIN_LOOP kPMCRunStateRunning +#else +#define PMC_IN_MAIN_LOOP 6 +#endif +#endif + +/* there are 32 DQM, since REPLY DQM will always be one after the REQUEST + * DQM, we should use use 0 to 30 for REQ DQM, so RPL DQM will be 1 to 31 */ +/* 63138 has pair of DQM#0+DQM#1, #2+#3, #4+#5, and #6+#7. We will use + * DQM#0+DQM#1 pair */ +#define PMC_DQM_REQ_NUM 0 + +#define PMC_DQM_RPL_NUM (PMC_DQM_REQ_NUM + 1) +#define PMC_DQM_RPL_STS (1 << PMC_DQM_RPL_NUM) + +#define PMC_MODE_DQM 0 +#define PMC_MODE_PMB_DIRECT 1 +#ifdef PMC_IMPL_3_X +#define PMC_ACCESS_BPCM_DIRECT 1 +#else +#define PMC_ACCESS_BPCM_DIRECT 0 +#endif + +#ifndef _LANGUAGE_ASSEMBLY +// ---------------------------- Returned error codes -------------------------- +enum { + // 0..15 may come from either the interface or from the PMC command handler + // 256 or greater only come from the interface + kPMC_NO_ERROR, + kPMC_INVALID_ISLAND, + kPMC_INVALID_DEVICE, + kPMC_INVALID_ZONE, + kPMC_INVALID_STATE, + kPMC_INVALID_COMMAND, + kPMC_LOG_EMPTY, + kPMC_INVALID_PARAM, + kPMC_BPCM_READ_TIMEOUT, + kPMC_INVALID_BUS, + kPMC_INVALID_QUEUE_NUMBER, + kPMC_QUEUE_NOT_AVAILABLE, + kPMC_INVALID_TOKEN_SIZE, + kPMC_INVALID_WATERMARKS, + kPMC_INSUFFICIENT_QSM_MEMORY, + kPMC_INVALID_BOOT_COMMAND, + kPMC_BOOT_FAILED, + kPMC_COMMAND_TIMEOUT = 256, + kPMC_MESSAGE_ID_MISMATCH, +}; + +// ---------------------------- Returned log entry structure -------------------------- +typedef struct { + uint8_t reserved; + uint8_t logMsgID; + uint8_t errorCode; + uint8_t logCmdID; + uint8_t srcPort; + uint8_t e_msgID; + uint8_t e_errorCode; + uint8_t e_cmdID; + struct { + uint32_t logReplyNum:8; + uint32_t e_Island:4; + uint32_t e_Bus:2; + uint32_t e_DevAddr:8; + uint32_t e_Zone:10; + } s; + uint32_t e_Data0; +} TErrorLogEntry; + +// ---------------------------- Power states -------------------------- +enum { + kPMCPowerState_Unknown, + kPMCPowerState_NoPower, + kPMCPowerState_LowPower, + kPMCPowerState_FullPower, +}; + +// PMC run-state: +enum { + kPMCRunStateExecutingBootROM = 0, + kPMCRunStateWaitingBMUComplete, + kPMCRunStateAVSCompleteWaitingForImage, + kPMCRunStateAuthenticatingImage, + kPMCRunStateAuthenticationFailed, + kPMCRunStateReserved, + kPMCRunStateStalled, + kPMCRunStateRunning +}; + +// the only valid "gear" values for "SetClockGear" function +enum { + kClockGearLow, + kClockGearHigh, + kClockGearDynamic, + kClockGearBypass +}; + +// PMC Boot options ( parameter for pmc_boot function ) +enum { + kPMCBootDefault = 0, + kPMCBootAVSDisable, + kPMCBootAVSTrackDisable, + kPMCBootLogBuffer, + kPMCBootLogSize +}; + +// int TuneRunner(void); +// int GetSelect0(void); +// int GetSelect3(void); +int pmc_init(void); +void pmc_reset(void); +void pmc_initmode(void); +// int get_pmc_boot_param(unsigned boot_option, unsigned *boot_param); +void pmc_log(int log_type); +void pmc_save_log_item(void); +void pmc_show_log_item(void); +int read_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t * value); +int write_bpcm_reg_direct(int devAddr, int wordOffset, uint32_t value); +int GetRevision(unsigned int *change, unsigned int *revision); +int GetPVT(int sel, int island, int *value); +#if (!defined(PMC_IMPL_3_X) && !defined(PMC_ON_HOSTCPU)) || IS_BCMCHIP(63178) || IS_BCMCHIP(47622) +int GetRCalSetting(int resistor, int *rcal); +#endif +int GetDevPresence(int devAddr, int *value); +int GetSWStrap(int devAddr, int *value); +int GetHWRev(int devAddr, int *value); +int GetNumZones(int devAddr, int *value); +int GetAvsDisableState(int island, int *state); +int Ping(void); +int GetErrorLogEntry(TErrorLogEntry * logEntry); +int SetClockHighGear(int devAddr, int zone, int clkN); +int SetClockLowGear(int devAddr, int zone, int clkN); +int SetClockGear(int devAddr, int zone, int gear); +int SetRunState(int island, int state); +int SetPowerState(int island, int state); +#if !defined(PMC_ON_HOSTCPU) +void BootPmcNoRom(unsigned long physAddr); +#endif +int ReadBPCMRegister(int devAddr, int wordOffset, uint32_t * value); +int WriteBPCMRegister(int devAddr, int wordOffset, uint32_t value); +int ReadZoneRegister(int devAddr, int zone, int wordOffset, uint32_t * value); +int WriteZoneRegister(int devAddr, int zone, int wordOffset, uint32_t value); +int PowerOnDevice(int devAddr); +int PowerOffDevice(int devAddr, int repower); +int PowerOnZone(int devAddr, int zone); +int PowerOffZone(int devAddr, int zone); +int ResetDevice(int devAddr); +int ResetZone(int devAddr, int zone); +int CloseAVS(int island, unsigned short margin_mv_slow, + unsigned short margin_mv_fast, unsigned short maximum_mv, + unsigned short minimum_mv); +#if IS_BCMCHIP(4908) +int RecloseAVS(int iscold); +#endif +void WaitPmc(int runState, void* pmc_log); +#if IS_BCMCHIP(63138) || IS_BCMCHIP(63148) || IS_BCMCHIP(6858) || \ + IS_BCMCHIP(4908) +int StallPmc(void); +int UnstallPmc(void); +#endif +#if IS_BCMCHIP(6856) +int GetAllROs(uint32_t pa); +#endif +enum pvtctl_sel { + kTEMPERATURE = 0, + kV_0p85_0 = 1, + kV_0p85_1 = 2, + kV_VIN = 3, + kV_1p00_1 = 4, + kV_1p80 = 5, + kV_3p30 = 6, + kTEST = 7, +}; +int pmc_convert_pvtmon(int sel, int value); +int pmc_get_tracktemp(int *status); +int pmc_set_tracktemp(int enable); +#endif //_LANGUAGE_ASSEMBLY + +#endif // PMC_DRV_H diff --git a/plat/bcm/include/pmc_drv_special.h b/plat/bcm/include/pmc_drv_special.h new file mode 100644 index 00000000..b182dd63 --- /dev/null +++ b/plat/bcm/include/pmc_drv_special.h @@ -0,0 +1,128 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +/***************************************************************************** + * Description: + * This contains special header for different flavors of PMC drivers. + *****************************************************************************/ + +#ifndef PMC_DRV_SPECIAL_H__ +#define PMC_DRV_SPECIAL_H__ + +#if defined(__KERNEL__) || defined(_ATF_) +#define CFG_RAMAPP +#endif + +#include "bcm_map_part.h" +#include "bcm_mem_reserve.h" + +#ifndef IS_BCMCHIP +#define IS_BCMCHIP(num) (defined(_BCM9##num##_) || \ + defined(CONFIG_BCM9##num) || defined(CONFIG_BCM##num)) +#endif + +#if IS_BCMCHIP(63138) +#include "pmc_addr_63138.h" +#elif IS_BCMCHIP(63148) +#include "pmc_addr_63148.h" +#elif IS_BCMCHIP(6858) +#include "pmc_addr_6858.h" +#elif IS_BCMCHIP(6846) +#include "pmc_addr_6846.h" +#elif IS_BCMCHIP(6878) +#include "pmc_addr_6878.h" +#elif IS_BCMCHIP(4908) +#include "pmc_addr_4908.h" +#elif IS_BCMCHIP(63158) +#include "pmc_addr_63158.h" +#elif IS_BCMCHIP(63178) +#include "pmc_addr_63178.h" +#elif IS_BCMCHIP(47622) +#include "pmc_addr_47622.h" +#elif IS_BCMCHIP(6856) +#include "pmc_addr_6856.h" +#elif IS_BCMCHIP(63146) +#include "pmc_addr_63146.h" +#elif IS_BCMCHIP(4912) +#include "pmc_addr_4912.h" +#elif IS_BCMCHIP(6855) +#include "pmc_addr_6855.h" +#elif IS_BCMCHIP(6756) +#include "pmc_addr_6756.h" +#endif + +#ifndef __ASSEMBLER__ +#if defined(_CFE_) && !defined(_ATF_) +#include "lib_printf.h" +#include "lib_types.h" +#include "lib_string.h" +#include "cfe_iocb.h" +#include "bsp_config.h" +#include "bcm63xx_util.h" +#include "shared_utils.h" + +#define MAX_PMC_ROM_SIZE 0x8000 +#define MAX_PMC_LOG_SIZE 0x8000 + +#if defined(_BCM963158_) && !defined(CONFIG_BRCM_IKOS) +#define PMC_SHARED_MEMORY 0x80204000 + +#if MAX_PMC_ROM_SIZE + MAX_PMC_LOG_SIZE > CFG_BOOT_PMC_SIZE +#error ROM and LOG buffer size needs to be re-adjusted +#endif +#endif /* _BCM963158_ */ + +extern void _cfe_flushcache(int, uint8_t *, uint8_t *); +extern int getAVSConfig(void); +#define is_pmcfw_code_loaded(void) (0) +#define is_pmcfw_data_loaded(void) (0) +#endif /* _CFE_ */ + +#ifdef __KERNEL__ +#include +#include +void pmc_spin_lock(void); +void pmc_spin_unlock(void); +#if defined(CONFIG_BCM96878) || defined(CONFIG_BCM96855) +void keyhole_spin_lock(void); +void keyhole_spin_unlock(void); +#endif +#else // #ifdef __KERNEL__ +#ifndef EXPORT_SYMBOL +#define EXPORT_SYMBOL(a) +#endif +#define pmc_spin_lock(...) do { } while (0) +#define pmc_spin_unlock(...) do { } while (0) +#if defined(CONFIG_BCM96878) || defined(CONFIG_BCM96855) +#define keyhole_spin_lock(...) do { } while (0) +#define keyhole_spin_unlock(...) do { } while (0) +#endif +#define printk printf + +#ifndef phys_to_virt +#define phys_to_virt(a) (a) +#endif +#endif // #ifdef __KERNEL__ +#endif // #ifndef __ASSEMBLER__ + +#endif // #ifndef PMC_DRV_SPECIAL_H__ diff --git a/plat/bcm/platform.mk b/plat/bcm/platform.mk new file mode 100644 index 00000000..76873c6a --- /dev/null +++ b/plat/bcm/platform.mk @@ -0,0 +1,88 @@ +include lib/libfdt/libfdt.mk + +PLAT_INCLUDES := -Iinclude/plat/arm/common/ \ + -Iinclude/plat/common/ \ + -Iinclude/plat/arm/common/aarch64/ \ + -Iplat/bcm/include \ + -Iplat/bcm/include/bcm963xx \ + -Iplat/bcm/drivers \ + -Iinclude/drivers/ \ + -Iinclude/drivers/arm/ \ + -Iinclude/common/ \ + -Iinclude/common/tbbr \ + -Iinclude/lib/ \ + -Iinclude/lib/psci/ \ + -Iinclude/bl31/ + + +ifeq ($(strip $(KERNEL_ARCH)),arm) +PLAT_BL_A9_SOURCE := plat/bcm/aarch32/pl310_a32.S \ + plat/bcm/aarch32/cortexa9_mmu.S + +PLAT_BL_COMMON_SOURCES := drivers/arm/gic/v2/gicv2_helpers.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/common/gic_common.c \ + drivers/arm/pl011/aarch32/pl011_console.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + lib/xlat_tables/xlat_tables_common.c \ + lib/xlat_tables/aarch32/xlat_tables.c \ + plat/common/plat_psci_common.c \ + plat/common/aarch32/platform_mp_stack.S \ + plat/bcm/aarch32/plat_helpers.S \ + plat/arm/common/aarch32/arm_helpers.S \ + plat/arm/common/arm_common.c \ + plat/bcm/brcm_bl32_setup.c \ + plat/bcm/brcm_pm.c \ + plat/bcm/topology.c \ + plat/bcm/drivers/pmc_drv.c \ + plat/bcm/drivers/pmc_cpu_core.c \ + plat/bcm/sp_min/src/opteed_main.c \ + plat/bcm/aarch32/opteed_helper.S + +ifeq ($(strip $(BRCM_CHIP)),63138) +PLAT_BL_COMMON_SOURCES += $(PLAT_BL_A9_SOURCE) +# following is needed to compile out code that A9 does not support +PL011_GENERIC_UART := 1 +endif + +else +PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \ + lib/xlat_tables/xlat_tables_common.c \ + lib/xlat_tables/aarch64/xlat_tables.c + +BL31_SOURCES += \ + lib/cpus/aarch64/cortex_a53.S \ + drivers/arm/gic/v2/gicv2_helpers.c \ + drivers/arm/gic/v2/gicv2_main.c \ + drivers/arm/gic/common/gic_common.c \ + plat/common/plat_psci_common.c \ + plat/bcm/brcm_pm.c \ + plat/bcm/topology.c \ + plat/bcm/aarch64/plat_helpers.S \ + plat/bcm/brcm_bl31_setup.c \ + plat/bcm/bcm_gic.c \ + plat/bcm/drivers/pmc_drv.c \ + plat/bcm/drivers/pmc_cpu_core.c \ + plat/arm/common/arm_common.c \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c +endif + +override WARMBOOT_ENABLE_DCACHE_EARLY := 1 +override PROGRAMMABLE_RESET_ADDRESS := 1 + +# Disable the PSCI platform compatibility layer +ENABLE_PLAT_COMPAT := 0 + +BL32_RAM_LOCATION := tdram +ifeq (${BL32_RAM_LOCATION}, tsram) + BL32_RAM_LOCATION_ID = SEC_SRAM_ID +else ifeq (${BL32_RAM_LOCATION}, tdram) + BL32_RAM_LOCATION_ID = SEC_DRAM_ID +else + $(error "Unsupported BL32_RAM_LOCATION value") +endif + +# Process flags +$(eval $(call add_define,BL32_RAM_LOCATION_ID)) diff --git a/plat/bcm/sp_min/sp_min-bcm.mk b/plat/bcm/sp_min/sp_min-bcm.mk new file mode 100644 index 00000000..68dab90f --- /dev/null +++ b/plat/bcm/sp_min/sp_min-bcm.mk @@ -0,0 +1 @@ +LOAD_IMAGE_V2 := 1 diff --git a/plat/bcm/sp_min/src/opteed_main.c b/plat/bcm/sp_min/src/opteed_main.c new file mode 100644 index 00000000..48f7df98 --- /dev/null +++ b/plat/bcm/sp_min/src/opteed_main.c @@ -0,0 +1,210 @@ +/* +<:copyright-BRCM:2019:DUAL/GPL:standard + + Copyright (c) 2019 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ +#if defined(SPD_opteed) +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static volatile uint32_t optee_smc_entry = 0; + +static uint32_t monitor_stack_pointer [PLATFORM_MAX_CPUS_PER_CLUSTER]; +static uint32_t optee_params_register [PLATFORM_MAX_CPUS_PER_CLUSTER][8]; + +extern void save_atf_sysreg(void); +extern void restore_atf_sysreg(void); + +__attribute__((naked)) void opteed_jump(uint32_t jump, uint32_t *monitor_stack, uint32_t *params) +{ + /* Save all GP registers */ + asm("push {r0-r12, r14}"); + + /* Find OPTEE's entry address and place to save ATF's monitor stack*/ + asm volatile ("mov r10, %0" "\n\t" + "mov r11, %1" "\n\t" + "mov r12, %2" "\n\t" + : : "r" (params), "r" (monitor_stack), "r" (jump)); + + /* Save ATF's monitor's stack in cache memory */ + asm("str sp, [r11]"); + save_atf_sysreg(); + + /* Load OPTEE's parameters */ + asm("ldm r10, {r0-r7}"); + + /* Turn off MMU and Cache needed to initialize OPTEE */ + asm("mrc p15, 0, r8, c1, c0, 0"); + asm("bic r8, r8, #0x5"); // (SCTLR_M_BIT | SCTLR_C_BIT) = 0x5 + asm("mcr p15, 0, r8, c1, c0, 0"); + + /* Save ATF's monitor's stack in non-cache memory */ + asm("str sp, [r11]"); + save_atf_sysreg(); + + /* Jump to OPTEE */ + asm("cps #0x13"); // switch to secure MODE_SVC mode (0x13) + asm("blx r12"); + asm("nop"); + /* Returned from OPTEE with OPTEE's smc entry point in r12. ** DO NOT corrupt r12 ** */ + + /* Load ATF's monitor stack from non-cached memory */ + asm("ldr r9,=monitor_stack_pointer"); + /* Point to the monitor stack pointer for this CPU */ + asm("mrc p15, 0, r10, c0, c0, 5"); + asm("and r10, r10, #0xff"); + asm("lsl r10, r10, #2"); + asm("add r9, r10, r9"); + asm("ldr sp, [r9]"); + + /* Restore ATF's system registers */ + restore_atf_sysreg(); + + /* Turn ON MMU */ + asm("mrc p15, 0, r8, c1, c0, 0"); + asm("ldr r9,=0x5"); // SCTLR_M_BIT | SCTLR_C_BIT + asm("orr r8, r8, r9"); + asm("mcr p15, 0, r8, c1, c0, 0"); + asm("nop"); + asm("nop"); + /* Save optee's SMC entry in cached memory */ + asm("ldr r8,=optee_smc_entry"); + asm("str r12,[r8]"); + /* Save the OPTEE's return registers r0-r7 in cached memory */ + asm("ldr r8,=optee_params_register"); + asm("lsl r10, r10, #3"); + asm("add r8, r10, r8"); + asm("stm r8, {r0-r7}"); + /* Restore all GP registers */ + asm("pop {r0-r12, r14}"); + asm("bx lr"); +} + +/******************************************************************************* + * OPTEE Dispatcher setup. The OPTEED finds out the OPTEE entrypoint and type + * (aarch32/aarch64) if not already known and initialises the context for entry + * into OPTEE for its initialization. + ******************************************************************************/ +int32_t opteed_setup(void) +{ + entry_point_info_t *optee_ep_info; + uint32_t cpu_id = plat_my_core_pos(); + uint32_t *monitor_stack = &monitor_stack_pointer[cpu_id]; + uint32_t *optee_params = &optee_params_register[cpu_id][0]; + /* + * Get information about the Secure Payload (BL32) image. Its + * absence is a critical failure. TODO: Add support to + * conditionally include the SPD service + */ + + optee_ep_info = bl31_plat_get_next_image_ep_info(SECURE); + if (!optee_ep_info) { + WARN("No OPTEE provided by BL2 boot loader, Booting device" + " without OPTEE initialization. SMC`s destined for OPTEE" + " will return SMC_UNK\n"); + return 1; + } + + /* + * If there's no valid entry point for SP, we return a non-zero value + * signalling failure initializing the service. We bail out without + * registering any handlers + */ + if (!optee_ep_info->pc) + return 1; + + opteed_jump(optee_ep_info->pc, monitor_stack, optee_params); + + return 0; +} + + + +/******************************************************************************* + * This function is responsible for handling all SMCs in the Trusted OS/App + * range from the non-secure state as defined in the SMC Calling Convention + * Document. It is also responsible for communicating with the Secure + * payload to delegate work and return results back to the non-secure + * state. Lastly it will also return any information that OPTEE needs to do + * the work assigned to it. + ******************************************************************************/ + uintptr_t opteed_smc_handler(uint32_t smc_fid, + u_register_t x1, + u_register_t x2, + u_register_t x3, + u_register_t x4, + void *cookie, + void *handle, + u_register_t flags) +{ + uint32_t cpu_id = plat_my_core_pos(); + uint32_t *monitor_stack = &monitor_stack_pointer[cpu_id]; + uint32_t *optee_params = &optee_params_register[cpu_id][0]; + cookie = cookie; + handle = handle; + flags = flags; + + /* Extract r0-r7 from saved context and pass to OPTEE */ + optee_params[0] = ((smc_ctx_t *)handle)->r0; // smc_fid; + optee_params[1] = ((smc_ctx_t *)handle)->r1; // x1; + optee_params[2] = ((smc_ctx_t *)handle)->r2; // x2; + optee_params[3] = ((smc_ctx_t *)handle)->r3; // x3; + optee_params[4] = ((smc_ctx_t *)handle)->r4; // x4; + optee_params[5] = ((smc_ctx_t *)handle)->r5; + optee_params[6] = ((smc_ctx_t *)handle)->r6; + optee_params[7] = ((smc_ctx_t *)handle)->r7; + + assert(optee_params[0] == smc_fid); + + opteed_jump(optee_smc_entry, monitor_stack, optee_params); + + /* Return the response from OPTEE */ + SMC_RET4(handle, optee_params[0], optee_params[1], optee_params[2], optee_params[3]); +} + +/* Define an OPTEED runtime service descriptor for fast SMC calls */ +DECLARE_RT_SVC( + opteed_fast, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_FAST, + opteed_setup, + opteed_smc_handler + ); + +/* Define an OPTEED runtime service descriptor for yielding SMC calls */ +DECLARE_RT_SVC( + opteed_std, + + OEN_TOS_START, + OEN_TOS_END, + SMC_TYPE_YIELD, + NULL, + opteed_smc_handler +); +#endif diff --git a/plat/bcm/topology.c b/plat/bcm/topology.c new file mode 100644 index 00000000..50ff1106 --- /dev/null +++ b/plat/bcm/topology.c @@ -0,0 +1,74 @@ +/* +<:copyright-BRCM:2012:DUAL/GPL:standard + + Copyright (c) 2012 Broadcom + All Rights Reserved + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License, version 2, as published by +the Free Software Foundation (the "GPL"). + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + + +A copy of the GPL is available at http://www.broadcom.com/licenses/GPLv2.php, or by +writing to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. + +:> +*/ + +#include +#include +#include "bcm_private.h" + +/* The power domain tree descriptor */ +static unsigned char power_domain_tree_desc[] = { + /* Number of root nodes */ + PLATFORM_CLUSTER_COUNT, + /* Number of children for the first node */ + PLATFORM_CLUSTER0_CORE_COUNT, + /* Number of children for the second node */ + PLATFORM_CLUSTER1_CORE_COUNT, +}; + +/******************************************************************************* + * This function returns the ARM default topology tree information. + ******************************************************************************/ +const unsigned char *plat_get_power_domain_tree_desc(void) +{ + return power_domain_tree_desc; +} + +/******************************************************************************* + * This function implements a part of the critical interface between the psci + * generic layer and the platform that allows the former to query the platform + * to convert an MPIDR to a unique linear index. An error code (-1) is returned + * in case the MPIDR is invalid. + ******************************************************************************/ +int plat_core_pos_by_mpidr(u_register_t mpidr) +{ + unsigned int cluster_id, cpu_id; + + mpidr &= MPIDR_AFFINITY_MASK; + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) + return -1; + + cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; + cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; + + if (cluster_id >= PLATFORM_CLUSTER_COUNT) + return -1; + + if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER) + return -1; + + return plat_bcm_calc_core_pos(mpidr); +} + +/* Needed for floating point lib */ +void raise (void) { asm("b ."); } +