realtek: clock driver: add switch clock

The internal switch clock will become relevant when we add RTL930X support.
Add it to the list.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>

diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
index 1789e4f33e24e1aaece346fa8d49f1dda8778b07..0488517f80a633878bf03a9ce9c212c70048d76d 100644 (file)
--- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
+++ b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.c
@@ -43,20 +43,24 @@
 static const int rtcl_regs[RTCL_SOCCNT][RTCL_REGCNT][CLK_COUNT] = {
        {
                {
+                       RTL_SW_CORE_BASE + RTL838X_PLL_SW_CTRL0,
                        RTL_SW_CORE_BASE + RTL838X_PLL_CPU_CTRL0,
                        RTL_SW_CORE_BASE + RTL838X_PLL_MEM_CTRL0,
                        RTL_SW_CORE_BASE + RTL838X_PLL_LXB_CTRL0,
                }, {
+                       RTL_SW_CORE_BASE + RTL838X_PLL_SW_CTRL1,
                        RTL_SW_CORE_BASE + RTL838X_PLL_CPU_CTRL1,
                        RTL_SW_CORE_BASE + RTL838X_PLL_MEM_CTRL1,
                        RTL_SW_CORE_BASE + RTL838X_PLL_LXB_CTRL1
                }
        }, {
                {
+                       RTL_SW_CORE_BASE + RTL839X_PLL_SW_CTRL,
                        RTL_SW_CORE_BASE + RTL839X_PLL_CPU_CTRL0,
                        RTL_SW_CORE_BASE + RTL839X_PLL_MEM_CTRL0,
                        RTL_SW_CORE_BASE + RTL839X_PLL_LXB_CTRL0
                }, {
+                       RTL_SW_CORE_BASE + RTL839X_PLL_SW_CTRL,
                        RTL_SW_CORE_BASE + RTL839X_PLL_CPU_CTRL1,
                        RTL_SW_CORE_BASE + RTL839X_PLL_MEM_CTRL1,
                        RTL_SW_CORE_BASE + RTL839X_PLL_LXB_CTRL1
@@ -174,13 +178,16 @@ struct rtcl_rtab_set {
 };
 
 #define RTCL_RTAB_SET(_rset) { .count = ARRAY_SIZE(_rset), .rset = _rset }
+#define RTCL_RTAB_SET_NONE { .count = 0, .rset = NULL }
 
 static const struct rtcl_rtab_set rtcl_rtab_set[RTCL_SOCCNT][CLK_COUNT] = {
        {
+               RTCL_RTAB_SET_NONE,
                RTCL_RTAB_SET(rtcl_838x_cpu_reg_set),
                RTCL_RTAB_SET(rtcl_838x_mem_reg_set),
                RTCL_RTAB_SET(rtcl_838x_lxb_reg_set)
        }, {
+               RTCL_RTAB_SET_NONE,
                RTCL_RTAB_SET(rtcl_839x_cpu_reg_set),
                RTCL_RTAB_SET(rtcl_839x_mem_reg_set),
                RTCL_RTAB_SET(rtcl_839x_lxb_reg_set)
@@ -188,6 +195,7 @@ static const struct rtcl_rtab_set rtcl_rtab_set[RTCL_SOCCNT][CLK_COUNT] = {
 };
 
 #define RTCL_ROUND_SET(_min, _max, _s) { .min = _min, .max = _max, .step = _s }
+#define RTCL_ROUND_SET_NONE { .min = 0, .max = 0, .step = 1 }
 
 struct rtcl_round_set {
        unsigned long min;
@@ -197,10 +205,12 @@ struct rtcl_round_set {
 
 static const struct rtcl_round_set rtcl_round_set[RTCL_SOCCNT][CLK_COUNT] = {
        {
+               RTCL_ROUND_SET_NONE,
                RTCL_ROUND_SET(300000000,       625000000,      25000000),
                RTCL_ROUND_SET(200000000,       375000000,      25000000),
                RTCL_ROUND_SET(100000000,       200000000,      25000000)
        }, {
+               RTCL_ROUND_SET_NONE,
                RTCL_ROUND_SET(400000000,       850000000,      25000000),
                RTCL_ROUND_SET(100000000,       400000000,      25000000),
                RTCL_ROUND_SET(50000000,        200000000,      50000000)
@@ -208,7 +218,7 @@ static const struct rtcl_round_set rtcl_round_set[RTCL_SOCCNT][CLK_COUNT] = {
 };
 
 static const int rtcl_divn3[] = { 2, 3, 4, 6 };
-static const int rtcl_xdiv[] = { 2, 4, 2 };
+static const int rtcl_xdiv[] = { 1, 2, 4, 2 };
 
 /*
  * module data structures
@@ -239,6 +249,7 @@ struct rtcl_clk {
 };
 
 static const struct rtcl_clk_info rtcl_clk_info[CLK_COUNT] = {
+       RTCL_CLK_INFO(CLK_SW, "sw_clk", "xtal_clk", "xtal_clk", "SW"),
        RTCL_CLK_INFO(CLK_CPU, "cpu_clk", "xtal_clk", "xtal_clk", "CPU"),
        RTCL_CLK_INFO(CLK_MEM, "mem_clk", "xtal_clk", "xtal_clk", "MEM"),
        RTCL_CLK_INFO(CLK_LXB, "lxb_clk", "xtal_clk", "xtal_clk", "LXB")
@@ -329,6 +340,12 @@ static unsigned long rtcl_recalc_rate(struct clk_hw *hw, unsigned long parent_ra
                div2 = cmu_divn2_selb ? cmu_divn3_sel : cmu_divn2;
                div3 = rtcl_xdiv[clk->idx];
                break;
+       case RTCL_SOC_CLK(RTCL_SOC838X, CLK_SW):
+       case RTCL_SOC_CLK(RTCL_SOC839X, CLK_SW):
+               mul1 = RTL_PLL_CTRL0_CMU_NCODE_IN(read0) + 4;
+               mul2 = RTL_PLL_CTRL0_CMU_SEL_DIV4(read0) ? 4 : 1;
+               div1 = 1 << RTL_PLL_CTRL0_CMU_SEL_PREDIV(read0);
+               break;
        }
 /*
  * Do the math in a way that interim values stay inside 32 bit bounds

diff --git a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.h b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.h
index 015d15572b9f98b4d148a120dde645243769cdac..4e2afee911c5dde1aa683ade2d2ca2c5fb7ac9b7 100644 (file)
--- a/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.h
+++ b/target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl83xx.h
@@ -14,18 +14,29 @@
 #define RTL838X_PLL_GLB_CTRL                   (0x0fc0)
 #define RTL838X_PLL_CPU_CTRL0                  (0x0fc4)
 #define RTL838X_PLL_CPU_CTRL1                  (0x0fc8)
+#define RTL838X_PLL_CPU_MISC_CTRL              (0x0fcc)
 #define RTL838X_PLL_LXB_CTRL0                  (0x0fd0)
 #define RTL838X_PLL_LXB_CTRL1                  (0x0fd4)
+#define RTL838X_PLL_LXB_MISC_CTRL              (0x0fd8)
 #define RTL838X_PLL_MEM_CTRL0                  (0x0fdc)
 #define RTL838X_PLL_MEM_CTRL1                  (0x0fe0)
+#define RTL838X_PLL_MEM_MISC_CTRL              (0x0fe4)
+#define RTL838X_PLL_SW_CTRL0                   (0x0fe8)
+#define RTL838X_PLL_SW_CTRL1                   (0x0fec)
+#define RTL838X_PLL_SW_MISC_CTRL               (0x0ff0)
 
 #define RTL839X_PLL_GLB_CTRL                   (0x0024)
 #define RTL839X_PLL_CPU_CTRL0                  (0x0028)
 #define RTL839X_PLL_CPU_CTRL1                  (0x002c)
+#define RTL839X_PLL_CPU_MISC_CTRL              (0x0034)
 #define RTL839X_PLL_LXB_CTRL0                  (0x0038)
 #define RTL839X_PLL_LXB_CTRL1                  (0x003c)
+#define RTL839X_PLL_LXB_MISC_CTRL              (0x0044)
 #define RTL839X_PLL_MEM_CTRL0                  (0x0048)
 #define RTL839X_PLL_MEM_CTRL1                  (0x004c)
+#define RTL839X_PLL_MEM_MISC_CTRL              (0x0054)
+#define RTL839X_PLL_SW_CTRL                    (0x0058)
+#define RTL839X_PLL_SW_MISC_CTRL               (0x005c)
 
 #define RTL_PLL_CTRL0_CMU_SEL_PREDIV(v)                (((v) >> 0) & 0x3)
 #define RTL_PLL_CTRL0_CMU_SEL_DIV4(v)          (((v) >> 2) & 0x1)

diff --git a/target/linux/realtek/files-5.10/include/dt-bindings/clock/rtl83xx-clk.h b/target/linux/realtek/files-5.10/include/dt-bindings/clock/rtl83xx-clk.h
index 3937052cc50ff415ecf5ee40e35246a6c5418665..5d30bb7f7d6cb28e8ada2abaf207f5ac346715da 100644 (file)
--- a/target/linux/realtek/files-5.10/include/dt-bindings/clock/rtl83xx-clk.h
+++ b/target/linux/realtek/files-5.10/include/dt-bindings/clock/rtl83xx-clk.h
@@ -7,9 +7,10 @@
 #ifndef __DT_BINDINGS_CLOCK_RTL83XX_H
 #define __DT_BINDINGS_CLOCK_RTL83XX_H
 
-#define CLK_CPU                0
-#define CLK_MEM                1
-#define CLK_LXB                2
-#define CLK_COUNT      3
+#define CLK_SW         0
+#define CLK_CPU                1
+#define CLK_MEM                2
+#define CLK_LXB                3
+#define CLK_COUNT      4
 
 #endif /* __DT_BINDINGS_CLOCK_RTL83XX_H */