target/linux/starfive/patches-6.1/1015-pwm-sifive-ptc-Add-SiFive-PWM-PTC-driver.patch

   1 From 8b3a02992094b5995d5a3e0d6d575aa852961c61 Mon Sep 17 00:00:00 2001
   2 From: Chenjieqin <Jessica.Chen@starfivetech.com>
   3 Date: Fri, 8 Jan 2021 03:56:54 +0800
   4 Subject: [PATCH 1015/1024] pwm: sifive-ptc: Add SiFive PWM PTC driver
   5
   6 yiming.li: clear CNTR of PWM after setting period & duty_cycle
   7 Emil: cleanups, clock, reset and div_u64
   8
   9 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
  10 ---
  11  drivers/pwm/Kconfig          |  11 ++
  12  drivers/pwm/Makefile         |   1 +
  13  drivers/pwm/pwm-sifive-ptc.c | 260 +++++++++++++++++++++++++++++++++++
  14  3 files changed, 272 insertions(+)
  15  create mode 100644 drivers/pwm/pwm-sifive-ptc.c
  16
  17 --- a/drivers/pwm/Kconfig
  18 +++ b/drivers/pwm/Kconfig
  19 @@ -504,6 +504,17 @@ config PWM_SIFIVE
  20           To compile this driver as a module, choose M here: the module
  21           will be called pwm-sifive.
  22
  23 +config PWM_SIFIVE_PTC
  24 +       tristate "SiFive PWM PTC support"
  25 +       depends on SOC_SIFIVE || SOC_STARFIVE || COMPILE_TEST
  26 +       depends on OF
  27 +       depends on COMMON_CLK
  28 +       help
  29 +         Generic PWM framework driver for SiFive SoCs.
  30 +
  31 +         To compile this driver as a module, choose M here: the module
  32 +         will be called pwm-sifive-ptc.
  33 +
  34  config PWM_SL28CPLD
  35         tristate "Kontron sl28cpld PWM support"
  36         depends on MFD_SL28CPLD || COMPILE_TEST
  37 --- a/drivers/pwm/Makefile
  38 +++ b/drivers/pwm/Makefile
  39 @@ -46,6 +46,7 @@ obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-ren
  40  obj-$(CONFIG_PWM_ROCKCHIP)     += pwm-rockchip.o
  41  obj-$(CONFIG_PWM_SAMSUNG)      += pwm-samsung.o
  42  obj-$(CONFIG_PWM_SIFIVE)       += pwm-sifive.o
  43 +obj-$(CONFIG_PWM_SIFIVE_PTC)   += pwm-sifive-ptc.o
  44  obj-$(CONFIG_PWM_SL28CPLD)     += pwm-sl28cpld.o
  45  obj-$(CONFIG_PWM_SPEAR)                += pwm-spear.o
  46  obj-$(CONFIG_PWM_SPRD)         += pwm-sprd.o
  47 --- /dev/null
  48 +++ b/drivers/pwm/pwm-sifive-ptc.c
  49 @@ -0,0 +1,260 @@
  50 +/*
  51 + * Copyright (C) 2018 SiFive, Inc
  52 + *
  53 + * This program is free software; you can redistribute it and/or modify it
  54 + * under the terms of the GNU General Public License version 2, as published by
  55 + * the Free Software Foundation.
  56 + */
  57 +
  58 +#include <linux/clk.h>
  59 +#include <linux/io.h>
  60 +#include <linux/math64.h>
  61 +#include <linux/module.h>
  62 +#include <linux/platform_device.h>
  63 +#include <linux/pwm.h>
  64 +#include <linux/reset.h>
  65 +
  66 +#include <dt-bindings/pwm/pwm.h>
  67 +
  68 +/* max channel of pwm */
  69 +#define MAX_PWM                                8
  70 +
  71 +/* PTC Register offsets */
  72 +#define REG_RPTC_CNTR                  0x0
  73 +#define REG_RPTC_HRC                   0x4
  74 +#define REG_RPTC_LRC                   0x8
  75 +#define REG_RPTC_CTRL                  0xC
  76 +
  77 +/* Bit for PWM clock */
  78 +#define BIT_PWM_CLOCK_EN               31
  79 +
  80 +/* Bit for clock gen soft reset */
  81 +#define BIT_CLK_GEN_SOFT_RESET         13
  82 +
  83 +#define NS_1                           1000000000U
  84 +
  85 +/* Access PTC register (cntr hrc lrc and ctrl), need to replace PWM_BASE_ADDR */
  86 +#define REG_PTC_BASE_ADDR_SUB(base, N) \
  87 +       ((base) + (((N) > 3) ? (((N) - 4) * 0x10 + (1 << 15)) : ((N) * 0x10)))
  88 +#define REG_PTC_RPTC_CNTR(base, N)     (REG_PTC_BASE_ADDR_SUB(base, N))
  89 +#define REG_PTC_RPTC_HRC(base, N)      (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4)
  90 +#define REG_PTC_RPTC_LRC(base, N)      (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8)
  91 +#define REG_PTC_RPTC_CTRL(base, N)     (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC)
  92 +
  93 +/* pwm ptc device */
  94 +struct sifive_pwm_ptc_device {
  95 +       struct pwm_chip chip;
  96 +       struct clk      *clk;
  97 +       void __iomem    *regs;
  98 +};
  99 +
 100 +static inline struct sifive_pwm_ptc_device *chip_to_sifive_ptc(struct pwm_chip *c)
 101 +{
 102 +       return container_of(c, struct sifive_pwm_ptc_device, chip);
 103 +}
 104 +
 105 +static int sifive_pwm_ptc_get_state(struct pwm_chip *chip, struct pwm_device *dev,
 106 +                                   struct pwm_state *state)
 107 +{
 108 +       struct sifive_pwm_ptc_device *pwm = chip_to_sifive_ptc(chip);
 109 +       u32 data_lrc;
 110 +       u32 data_hrc;
 111 +       u32 pwm_clk_ns = 0;
 112 +
 113 +       /* get lrc and hrc data from registe */
 114 +       data_lrc = ioread32(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm));
 115 +       data_hrc = ioread32(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm));
 116 +
 117 +       /* how many ns does apb clock elapse */
 118 +       pwm_clk_ns = NS_1 / clk_get_rate(pwm->clk);
 119 +
 120 +       /* pwm period(ns) */
 121 +       state->period     = data_lrc * pwm_clk_ns;
 122 +
 123 +       /* duty cycle(ns) means high level eclapse ns if it is normal polarity */
 124 +       state->duty_cycle = data_hrc * pwm_clk_ns;
 125 +
 126 +       /* polarity, we don't use it now because it is not in dts */
 127 +       state->polarity   = PWM_POLARITY_NORMAL;
 128 +
 129 +       /* enabled or not */
 130 +       state->enabled    = 1;
 131 +
 132 +       dev_dbg(pwm->chip.dev, "%s: no:%d\n", __func__, dev->hwpwm);
 133 +       dev_dbg(pwm->chip.dev, "data_hrc:0x%x 0x%x\n", data_hrc, data_lrc);
 134 +       dev_dbg(pwm->chip.dev, "period:%llu\n", state->period);
 135 +       dev_dbg(pwm->chip.dev, "duty_cycle:%llu\n", state->duty_cycle);
 136 +       dev_dbg(pwm->chip.dev, "polarity:%d\n", state->polarity);
 137 +       dev_dbg(pwm->chip.dev, "enabled:%d\n", state->enabled);
 138 +
 139 +       return 0;
 140 +}
 141 +
 142 +static int sifive_pwm_ptc_apply(struct pwm_chip *chip, struct pwm_device *dev,
 143 +                               const struct pwm_state *state)
 144 +{
 145 +       struct sifive_pwm_ptc_device *pwm = chip_to_sifive_ptc(chip);
 146 +       void __iomem *reg_addr;
 147 +       u32 pwm_clk_ns = 0;
 148 +       u32 data_hrc = 0;
 149 +       u32 data_lrc = 0;
 150 +       u32 period_data = 0;
 151 +       u32 duty_data = 0;
 152 +
 153 +       dev_dbg(pwm->chip.dev, "%s: no:%d\n", __func__, dev->hwpwm);
 154 +       dev_dbg(pwm->chip.dev, "period:%llu\n", state->period);
 155 +       dev_dbg(pwm->chip.dev, "duty_cycle:%llu\n", state->duty_cycle);
 156 +       dev_dbg(pwm->chip.dev, "polarity:%d\n", state->polarity);
 157 +       dev_dbg(pwm->chip.dev, "enabled:%d\n", state->enabled);
 158 +
 159 +       /* duty_cycle should be less or equal than period */
 160 +       if (state->duty_cycle > state->period)
 161 +               return -EINVAL;
 162 +
 163 +       /* calculate pwm real period (ns) */
 164 +       pwm_clk_ns = NS_1 / clk_get_rate(pwm->clk);
 165 +
 166 +       dev_dbg(pwm->chip.dev, "pwm_clk_ns:%u\n", pwm_clk_ns);
 167 +
 168 +       /* calculate period count */
 169 +       period_data = div_u64(state->period, pwm_clk_ns);
 170 +
 171 +       if (!state->enabled)
 172 +               /* if disabled, just set duty_data to 0, which means low level always */
 173 +               duty_data = 0;
 174 +       else
 175 +               /* calculate duty count */
 176 +               duty_data = div_u64(state->duty_cycle, pwm_clk_ns);
 177 +
 178 +       dev_dbg(pwm->chip.dev, "period_data:%u, duty_data:%u\n",
 179 +               period_data, duty_data);
 180 +
 181 +       if (state->polarity == PWM_POLARITY_NORMAL)
 182 +               /* calculate data_hrc */
 183 +               data_hrc = period_data - duty_data;
 184 +       else
 185 +               /* calculate data_hrc */
 186 +               data_hrc = duty_data;
 187 +
 188 +       data_lrc = period_data;
 189 +
 190 +       /* set hrc */
 191 +       reg_addr = REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm);
 192 +       dev_dbg(pwm->chip.dev, "%s: reg_addr:%p, data:%u\n",
 193 +               __func__, reg_addr, data_hrc);
 194 +
 195 +       iowrite32(data_hrc, reg_addr);
 196 +
 197 +       dev_dbg(pwm->chip.dev, "%s: hrc ok\n", __func__);
 198 +
 199 +       /* set lrc */
 200 +       reg_addr = REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm);
 201 +       dev_dbg(pwm->chip.dev, "%s: reg_addr:%p, data:%u\n",
 202 +               __func__, reg_addr, data_lrc);
 203 +
 204 +       iowrite32(data_lrc, reg_addr);
 205 +       dev_dbg(pwm->chip.dev, "%s: lrc ok\n", __func__);
 206 +
 207 +       /* Clear REG_RPTC_CNTR after setting period & duty_cycle */
 208 +       reg_addr = REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm);
 209 +       iowrite32(0, reg_addr);
 210 +       return 0;
 211 +}
 212 +
 213 +static const struct pwm_ops sifive_pwm_ptc_ops = {
 214 +       .get_state      = sifive_pwm_ptc_get_state,
 215 +       .apply          = sifive_pwm_ptc_apply,
 216 +       .owner          = THIS_MODULE,
 217 +};
 218 +
 219 +static void sifive_pwm_ptc_disable_action(void *data)
 220 +{
 221 +       clk_disable_unprepare(data);
 222 +}
 223 +
 224 +static int sifive_pwm_ptc_probe(struct platform_device *pdev)
 225 +{
 226 +       struct device *dev = &pdev->dev;
 227 +       struct device_node *node = pdev->dev.of_node;
 228 +       struct sifive_pwm_ptc_device *pwm;
 229 +       struct pwm_chip *chip;
 230 +       struct reset_control *rst;
 231 +       int ret;
 232 +
 233 +       pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL);
 234 +       if (!pwm)
 235 +               return -ENOMEM;
 236 +
 237 +       platform_set_drvdata(pdev, pwm);
 238 +
 239 +       chip = &pwm->chip;
 240 +       chip->dev = dev;
 241 +       chip->ops = &sifive_pwm_ptc_ops;
 242 +
 243 +       /* how many parameters can be transferred to ptc, need to fix */
 244 +       chip->of_pwm_n_cells = 3;
 245 +       chip->base = -1;
 246 +
 247 +       /* get pwm channels count, max value is 8 */
 248 +       ret = of_property_read_u32(node, "starfive,npwm", &chip->npwm);
 249 +       if (ret < 0 || chip->npwm > MAX_PWM)
 250 +               chip->npwm = MAX_PWM;
 251 +
 252 +       dev_dbg(dev, "%s: npwm:0x%x\n", __func__, chip->npwm);
 253 +
 254 +       /* get IO base address */
 255 +       pwm->regs = devm_platform_ioremap_resource(pdev, 0);
 256 +       if (IS_ERR(pwm->regs))
 257 +               return dev_err_probe(dev, PTR_ERR(pwm->regs),
 258 +                                    "Unable to map IO resources\n");
 259 +
 260 +       pwm->clk = devm_clk_get(dev, NULL);
 261 +       if (IS_ERR(pwm->clk))
 262 +               return dev_err_probe(dev, PTR_ERR(pwm->clk),
 263 +                                    "Unable to get controller clock\n");
 264 +
 265 +       ret = clk_prepare_enable(pwm->clk);
 266 +       if (ret)
 267 +               return dev_err_probe(dev, ret, "Unable to enable clock\n");
 268 +
 269 +       ret = devm_add_action_or_reset(dev, sifive_pwm_ptc_disable_action, pwm->clk);
 270 +       if (ret)
 271 +               return ret;
 272 +
 273 +       rst = devm_reset_control_get_exclusive(dev, NULL);
 274 +       if (IS_ERR(rst))
 275 +               return dev_err_probe(dev, PTR_ERR(rst), "Unable to get reset\n");
 276 +
 277 +       ret = reset_control_deassert(rst);
 278 +       if (ret)
 279 +               return dev_err_probe(dev, ret, "Unable to deassert reset\n");
 280 +
 281 +       /*
 282 +        * after pwmchip_add it will show up as /sys/class/pwm/pwmchip0,
 283 +        * 0 is chip->base, pwm0 can be seen after running echo 0 > export
 284 +        */
 285 +       ret = devm_pwmchip_add(dev, chip);
 286 +       if (ret)
 287 +               return dev_err_probe(dev, ret, "cannot register PTC: %d\n", ret);
 288 +
 289 +       dev_dbg(dev, "SiFive PWM PTC chip registered %d PWMs\n", chip->npwm);
 290 +       return 0;
 291 +}
 292 +
 293 +static const struct of_device_id sifive_pwm_ptc_of_match[] = {
 294 +       { .compatible = "starfive,pwm0" },
 295 +       { /* sentinel */ }
 296 +};
 297 +MODULE_DEVICE_TABLE(of, sifive_pwm_ptc_of_match);
 298 +
 299 +static struct platform_driver sifive_pwm_ptc_driver = {
 300 +       .probe = sifive_pwm_ptc_probe,
 301 +       .driver = {
 302 +               .name = "pwm-sifive-ptc",
 303 +               .of_match_table = sifive_pwm_ptc_of_match,
 304 +       },
 305 +};
 306 +module_platform_driver(sifive_pwm_ptc_driver);
 307 +
 308 +MODULE_DESCRIPTION("SiFive PWM PTC driver");
 309 +MODULE_LICENSE("GPL v2");