starfive: add new target for StarFive JH7100/7110 SoC
[openwrt/staging/981213.git] / target / linux / starfive / patches-6.1 / 0108-mmc-starfive-Add-sdio-emmc-driver-support.patch
1 From ee990c664fad993275b2615d0ff06af5d04922f0 Mon Sep 17 00:00:00 2001
2 From: William Qiu <william.qiu@starfivetech.com>
3 Date: Wed, 15 Feb 2023 19:32:47 +0800
4 Subject: [PATCH 108/122] mmc: starfive: Add sdio/emmc driver support
5
6 Add sdio/emmc driver support for StarFive JH7110 soc.
7
8 Tested-by: Conor Dooley <conor.dooley@microchip.com>
9 Signed-off-by: William Qiu <william.qiu@starfivetech.com>
10 ---
11 MAINTAINERS | 6 +
12 drivers/mmc/host/Kconfig | 10 ++
13 drivers/mmc/host/Makefile | 1 +
14 drivers/mmc/host/dw_mmc-starfive.c | 186 +++++++++++++++++++++++++++++
15 4 files changed, 203 insertions(+)
16 create mode 100644 drivers/mmc/host/dw_mmc-starfive.c
17
18 --- a/MAINTAINERS
19 +++ b/MAINTAINERS
20 @@ -19657,6 +19657,12 @@ S: Maintained
21 F: Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml
22 F: drivers/net/ethernet/stmicro/stmmac/dwmac-starfive.c
23
24 +STARFIVE JH7110 MMC/SD/SDIO DRIVER
25 +M: William Qiu <william.qiu@starfivetech.com>
26 +S: Supported
27 +F: Documentation/devicetree/bindings/mmc/starfive*
28 +F: drivers/mmc/host/dw_mmc-starfive.c
29 +
30 STARFIVE JH7110 PLL CLOCK DRIVER
31 M: Xingyu Wu <xingyu.wu@starfivetech.com>
32 S: Supported
33 --- a/drivers/mmc/host/Kconfig
34 +++ b/drivers/mmc/host/Kconfig
35 @@ -872,6 +872,16 @@ config MMC_DW_ROCKCHIP
36 Synopsys DesignWare Memory Card Interface driver. Select this option
37 for platforms based on RK3066, RK3188 and RK3288 SoC's.
38
39 +config MMC_DW_STARFIVE
40 + tristate "StarFive specific extensions for Synopsys DW Memory Card Interface"
41 + depends on SOC_STARFIVE
42 + depends on MMC_DW
43 + select MMC_DW_PLTFM
44 + help
45 + This selects support for StarFive JH7110 SoC specific extensions to the
46 + Synopsys DesignWare Memory Card Interface driver. Select this option
47 + for platforms based on StarFive JH7110 SoC.
48 +
49 config MMC_SH_MMCIF
50 tristate "SuperH Internal MMCIF support"
51 depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
52 --- a/drivers/mmc/host/Makefile
53 +++ b/drivers/mmc/host/Makefile
54 @@ -56,6 +56,7 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_m
55 obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
56 obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
57 obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
58 +obj-$(CONFIG_MMC_DW_STARFIVE) += dw_mmc-starfive.o
59 obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
60 obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
61 obj-$(CONFIG_MMC_VUB300) += vub300.o
62 --- /dev/null
63 +++ b/drivers/mmc/host/dw_mmc-starfive.c
64 @@ -0,0 +1,186 @@
65 +// SPDX-License-Identifier: GPL-2.0
66 +/*
67 + * StarFive Designware Mobile Storage Host Controller Driver
68 + *
69 + * Copyright (c) 2022 StarFive Technology Co., Ltd.
70 + */
71 +
72 +#include <linux/clk.h>
73 +#include <linux/delay.h>
74 +#include <linux/mfd/syscon.h>
75 +#include <linux/mmc/host.h>
76 +#include <linux/module.h>
77 +#include <linux/of_address.h>
78 +#include <linux/platform_device.h>
79 +#include <linux/regmap.h>
80 +
81 +#include "dw_mmc.h"
82 +#include "dw_mmc-pltfm.h"
83 +
84 +#define ALL_INT_CLR 0x1ffff
85 +#define MAX_DELAY_CHAIN 32
86 +
87 +struct starfive_priv {
88 + struct device *dev;
89 + struct regmap *reg_syscon;
90 + u32 syscon_offset;
91 + u32 syscon_shift;
92 + u32 syscon_mask;
93 +};
94 +
95 +static void dw_mci_starfive_set_ios(struct dw_mci *host, struct mmc_ios *ios)
96 +{
97 + int ret;
98 + unsigned int clock;
99 +
100 + if (ios->timing == MMC_TIMING_MMC_DDR52 || ios->timing == MMC_TIMING_UHS_DDR50) {
101 + clock = (ios->clock > 50000000 && ios->clock <= 52000000) ? 100000000 : ios->clock;
102 + ret = clk_set_rate(host->ciu_clk, clock);
103 + if (ret)
104 + dev_dbg(host->dev, "Use an external frequency divider %uHz\n", ios->clock);
105 + host->bus_hz = clk_get_rate(host->ciu_clk);
106 + } else {
107 + dev_dbg(host->dev, "Using the internal divider\n");
108 + }
109 +}
110 +
111 +static int dw_mci_starfive_execute_tuning(struct dw_mci_slot *slot,
112 + u32 opcode)
113 +{
114 + static const int grade = MAX_DELAY_CHAIN;
115 + struct dw_mci *host = slot->host;
116 + struct starfive_priv *priv = host->priv;
117 + int rise_point = -1, fall_point = -1;
118 + int err, prev_err;
119 + int i;
120 + bool found = 0;
121 + u32 regval;
122 +
123 + /*
124 + * Use grade as the max delay chain, and use the rise_point and
125 + * fall_point to ensure the best sampling point of a data input
126 + * signals.
127 + */
128 + for (i = 0; i < grade; i++) {
129 + regval = i << priv->syscon_shift;
130 + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
131 + priv->syscon_mask, regval);
132 + if (err)
133 + return err;
134 + mci_writel(host, RINTSTS, ALL_INT_CLR);
135 +
136 + err = mmc_send_tuning(slot->mmc, opcode, NULL);
137 + if (!err)
138 + found = 1;
139 +
140 + if (i > 0) {
141 + if (err && !prev_err)
142 + fall_point = i - 1;
143 + if (!err && prev_err)
144 + rise_point = i;
145 + }
146 +
147 + if (rise_point != -1 && fall_point != -1)
148 + goto tuning_out;
149 +
150 + prev_err = err;
151 + err = 0;
152 + }
153 +
154 +tuning_out:
155 + if (found) {
156 + if (rise_point == -1)
157 + rise_point = 0;
158 + if (fall_point == -1)
159 + fall_point = grade - 1;
160 + if (fall_point < rise_point) {
161 + if ((rise_point + fall_point) >
162 + (grade - 1))
163 + i = fall_point / 2;
164 + else
165 + i = (rise_point + grade - 1) / 2;
166 + } else {
167 + i = (rise_point + fall_point) / 2;
168 + }
169 +
170 + regval = i << priv->syscon_shift;
171 + err = regmap_update_bits(priv->reg_syscon, priv->syscon_offset,
172 + priv->syscon_mask, regval);
173 + if (err)
174 + return err;
175 + mci_writel(host, RINTSTS, ALL_INT_CLR);
176 +
177 + dev_info(host->dev, "Found valid delay chain! use it [delay=%d]\n", i);
178 + } else {
179 + dev_err(host->dev, "No valid delay chain! use default\n");
180 + err = -EINVAL;
181 + }
182 +
183 + mci_writel(host, RINTSTS, ALL_INT_CLR);
184 + return err;
185 +}
186 +
187 +static int dw_mci_starfive_parse_dt(struct dw_mci *host)
188 +{
189 + struct of_phandle_args args;
190 + struct starfive_priv *priv;
191 + int ret;
192 +
193 + priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
194 + if (!priv)
195 + return -ENOMEM;
196 +
197 + ret = of_parse_phandle_with_fixed_args(host->dev->of_node,
198 + "starfive,sysreg", 3, 0, &args);
199 + if (ret) {
200 + dev_err(host->dev, "Failed to parse starfive,sysreg\n");
201 + return -EINVAL;
202 + }
203 +
204 + priv->reg_syscon = syscon_node_to_regmap(args.np);
205 + of_node_put(args.np);
206 + if (IS_ERR(priv->reg_syscon))
207 + return PTR_ERR(priv->reg_syscon);
208 +
209 + priv->syscon_offset = args.args[0];
210 + priv->syscon_shift = args.args[1];
211 + priv->syscon_mask = args.args[2];
212 +
213 + host->priv = priv;
214 +
215 + return 0;
216 +}
217 +
218 +static const struct dw_mci_drv_data starfive_data = {
219 + .common_caps = MMC_CAP_CMD23,
220 + .set_ios = dw_mci_starfive_set_ios,
221 + .parse_dt = dw_mci_starfive_parse_dt,
222 + .execute_tuning = dw_mci_starfive_execute_tuning,
223 +};
224 +
225 +static const struct of_device_id dw_mci_starfive_match[] = {
226 + { .compatible = "starfive,jh7110-mmc",
227 + .data = &starfive_data },
228 + {},
229 +};
230 +MODULE_DEVICE_TABLE(of, dw_mci_starfive_match);
231 +
232 +static int dw_mci_starfive_probe(struct platform_device *pdev)
233 +{
234 + return dw_mci_pltfm_register(pdev, &starfive_data);
235 +}
236 +
237 +static struct platform_driver dw_mci_starfive_driver = {
238 + .probe = dw_mci_starfive_probe,
239 + .remove = dw_mci_pltfm_remove,
240 + .driver = {
241 + .name = "dwmmc_starfive",
242 + .probe_type = PROBE_PREFER_ASYNCHRONOUS,
243 + .of_match_table = dw_mci_starfive_match,
244 + },
245 +};
246 +module_platform_driver(dw_mci_starfive_driver);
247 +
248 +MODULE_DESCRIPTION("StarFive JH7110 Specific DW-MSHC Driver Extension");
249 +MODULE_LICENSE("GPL");
250 +MODULE_ALIAS("platform:dwmmc_starfive");