starfive: add new target for StarFive JH7100/7110 SoC
[openwrt/staging/981213.git] / target / linux / starfive / patches-6.1 / 0101-dt-bindings-rng-Add-StarFive-TRNG-module.patch
1 From 0b99a4626c7e148df128c6a8cb686d500431189b Mon Sep 17 00:00:00 2001
2 From: Jia Jie Ho <jiajie.ho@starfivetech.com>
3 Date: Tue, 17 Jan 2023 09:54:43 +0800
4 Subject: [PATCH 101/122] dt-bindings: rng: Add StarFive TRNG module
5
6 Add documentation to describe Starfive true random number generator
7 module.
8
9 Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
10 Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
11 Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
12 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13 Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
14 ---
15 .../bindings/rng/starfive,jh7110-trng.yaml | 55 +++++++++++++++++++
16 1 file changed, 55 insertions(+)
17 create mode 100644 Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml
18
19 --- /dev/null
20 +++ b/Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml
21 @@ -0,0 +1,55 @@
22 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
23 +%YAML 1.2
24 +---
25 +$id: http://devicetree.org/schemas/rng/starfive,jh7110-trng.yaml#
26 +$schema: http://devicetree.org/meta-schemas/core.yaml#
27 +
28 +title: StarFive SoC TRNG Module
29 +
30 +maintainers:
31 + - Jia Jie Ho <jiajie.ho@starfivetech.com>
32 +
33 +properties:
34 + compatible:
35 + const: starfive,jh7110-trng
36 +
37 + reg:
38 + maxItems: 1
39 +
40 + clocks:
41 + items:
42 + - description: Hardware reference clock
43 + - description: AHB reference clock
44 +
45 + clock-names:
46 + items:
47 + - const: hclk
48 + - const: ahb
49 +
50 + resets:
51 + maxItems: 1
52 +
53 + interrupts:
54 + maxItems: 1
55 +
56 +required:
57 + - compatible
58 + - reg
59 + - clocks
60 + - clock-names
61 + - resets
62 + - interrupts
63 +
64 +additionalProperties: false
65 +
66 +examples:
67 + - |
68 + rng: rng@1600C000 {
69 + compatible = "starfive,jh7110-trng";
70 + reg = <0x1600C000 0x4000>;
71 + clocks = <&clk 15>, <&clk 16>;
72 + clock-names = "hclk", "ahb";
73 + resets = <&reset 3>;
74 + interrupts = <30>;
75 + };
76 +...