target/linux/starfive/patches-6.1/0094-dt-binding-pci-add-JH7110-PCIe-dt-binding-documents.patch

   1 From 3d555cfd72df1a02849565f281149d321e0f8425 Mon Sep 17 00:00:00 2001
   2 From: Minda Chen <minda.chen@starfivetech.com>
   3 Date: Thu, 6 Apr 2023 19:11:40 +0800
   4 Subject: [PATCH 094/122] dt-binding: pci: add JH7110 PCIe dt-binding
   5  documents.
   6
   7 Add PCIe controller driver dt-binding documents
   8 for StarFive JH7110 SoC platform.
   9
  10 Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
  11 ---
  12  .../bindings/pci/starfive,jh7110-pcie.yaml    | 163 ++++++++++++++++++
  13  1 file changed, 163 insertions(+)
  14  create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
  15
  16 --- /dev/null
  17 +++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
  18 @@ -0,0 +1,163 @@
  19 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  20 +%YAML 1.2
  21 +---
  22 +$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml#
  23 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  24 +
  25 +title: StarFive JH7110 PCIe 2.0 host controller
  26 +
  27 +maintainers:
  28 +  - Minda Chen <minda.chen@starfivetech.com>
  29 +
  30 +allOf:
  31 +  - $ref: /schemas/pci/pci-bus.yaml#
  32 +  - $ref: /schemas/interrupt-controller/msi-controller.yaml#
  33 +
  34 +properties:
  35 +  compatible:
  36 +    const: starfive,jh7110-pcie
  37 +
  38 +  reg:
  39 +    maxItems: 2
  40 +
  41 +  reg-names:
  42 +    items:
  43 +      - const: reg
  44 +      - const: config
  45 +
  46 +  msi-parent: true
  47 +
  48 +  interrupts:
  49 +    maxItems: 1
  50 +
  51 +  clocks:
  52 +    maxItems: 4
  53 +
  54 +  clock-names:
  55 +    items:
  56 +      - const: noc
  57 +      - const: tl
  58 +      - const: axi_mst0
  59 +      - const: apb
  60 +
  61 +  resets:
  62 +    items:
  63 +      - description: AXI MST0 reset
  64 +      - description: AXI SLAVE reset
  65 +      - description: AXI SLAVE0 reset
  66 +      - description: PCIE BRIDGE reset
  67 +      - description: PCIE CORE reset
  68 +      - description: PCIE APB reset
  69 +
  70 +  reset-names:
  71 +    items:
  72 +      - const: mst0
  73 +      - const: slv0
  74 +      - const: slv
  75 +      - const: brg
  76 +      - const: core
  77 +      - const: apb
  78 +
  79 +  starfive,stg-syscon:
  80 +    $ref: /schemas/types.yaml#/definitions/phandle-array
  81 +    items:
  82 +      items:
  83 +        - description: phandle to System Register Controller stg_syscon node.
  84 +        - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
  85 +        - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
  86 +        - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
  87 +        - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for PCIe.
  88 +    description:
  89 +      The phandle to System Register Controller syscon node and the offset
  90 +      of STG_SYSCONSAIF__SYSCFG register for PCIe. Total 4 regsisters offset
  91 +      for PCIe.
  92 +
  93 +  pwren-gpios:
  94 +    description: Should specify the GPIO for controlling the PCI bus device power on.
  95 +    maxItems: 1
  96 +
  97 +  reset-gpios:
  98 +    maxItems: 1
  99 +
 100 +  phys:
 101 +    maxItems: 1
 102 +
 103 +  interrupt-controller:
 104 +    type: object
 105 +    properties:
 106 +      '#address-cells':
 107 +        const: 0
 108 +
 109 +      '#interrupt-cells':
 110 +        const: 1
 111 +
 112 +      interrupt-controller: true
 113 +
 114 +    required:
 115 +      - '#address-cells'
 116 +      - '#interrupt-cells'
 117 +      - interrupt-controller
 118 +
 119 +    additionalProperties: false
 120 +
 121 +required:
 122 +  - reg
 123 +  - reg-names
 124 +  - "#interrupt-cells"
 125 +  - interrupts
 126 +  - interrupt-map-mask
 127 +  - interrupt-map
 128 +  - clocks
 129 +  - clock-names
 130 +  - resets
 131 +  - msi-controller
 132 +
 133 +unevaluatedProperties: false
 134 +
 135 +examples:
 136 +  - |
 137 +    bus {
 138 +        #address-cells = <2>;
 139 +        #size-cells = <2>;
 140 +
 141 +        pcie0: pcie@2B000000 {
 142 +            compatible = "starfive,jh7110-pcie";
 143 +            #address-cells = <3>;
 144 +            #size-cells = <2>;
 145 +            #interrupt-cells = <1>;
 146 +            reg = <0x0 0x2B000000 0x0 0x1000000>,
 147 +                  <0x9 0x40000000 0x0 0x10000000>;
 148 +            reg-names = "reg", "config";
 149 +            device_type = "pci";
 150 +            starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
 151 +            bus-range = <0x0 0xff>;
 152 +            ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
 153 +                     <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
 154 +            interrupt-parent = <&plic>;
 155 +            interrupts = <56>;
 156 +            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 157 +            interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
 158 +                            <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
 159 +                            <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
 160 +                            <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
 161 +            msi-parent = <&pcie0>;
 162 +            msi-controller;
 163 +            clocks = <&syscrg 86>,
 164 +                     <&stgcrg 10>,
 165 +                     <&stgcrg 8>,
 166 +                     <&stgcrg 9>;
 167 +            clock-names = "noc", "tl", "axi_mst0", "apb";
 168 +            resets = <&stgcrg 11>,
 169 +                     <&stgcrg 12>,
 170 +                     <&stgcrg 13>,
 171 +                     <&stgcrg 14>,
 172 +                     <&stgcrg 15>,
 173 +                     <&stgcrg 16>;
 174 +
 175 +            pcie_intc0: interrupt-controller {
 176 +                #address-cells = <0>;
 177 +                #interrupt-cells = <1>;
 178 +                interrupt-controller;
 179 +            };
 180 +        };
 181 +    };