target/linux/starfive/patches-6.1/0090-phy-starfive-Add-JH7110-PCIE-2.0-PHY-driver.patch

   1 From d900724fdae7c41a663b31e1ed9b8ba10b998e6f Mon Sep 17 00:00:00 2001
   2 From: Minda Chen <minda.chen@starfivetech.com>
   3 Date: Thu, 18 May 2023 19:27:47 +0800
   4 Subject: [PATCH 090/122] phy: starfive: Add JH7110 PCIE 2.0 PHY driver
   5
   6 Add Starfive JH7110 SoC PCIe 2.0 PHY driver support.
   7 PCIe 2.0 PHY default connect to PCIe controller.
   8 PCIe PHY can connect to USB 3.0 controller.
   9
  10 Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
  11 ---
  12  drivers/phy/starfive/Kconfig           |  10 ++
  13  drivers/phy/starfive/Makefile          |   1 +
  14  drivers/phy/starfive/phy-jh7110-pcie.c | 204 +++++++++++++++++++++++++
  15  3 files changed, 215 insertions(+)
  16  create mode 100644 drivers/phy/starfive/phy-jh7110-pcie.c
  17
  18 --- a/drivers/phy/starfive/Kconfig
  19 +++ b/drivers/phy/starfive/Kconfig
  20 @@ -12,6 +12,16 @@ config PHY_STARFIVE_DPHY_RX
  21           system. If M is selected, the module will be called
  22           phy-starfive-dphy-rx.
  23
  24 +config PHY_STARFIVE_JH7110_PCIE
  25 +       tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
  26 +       select GENERIC_PHY
  27 +       select USB_PHY
  28 +       help
  29 +         Enable this to support the StarFive PCIe 2.0 PHY,
  30 +         or used as USB 3.0 PHY.
  31 +         If M is selected, the module will be called
  32 +         phy-jh7110-pcie.ko.
  33 +
  34  config PHY_STARFIVE_JH7110_USB
  35         tristate "Starfive JH7110 USB 2.0 PHY support"
  36         depends on USB_SUPPORT
  37 --- a/drivers/phy/starfive/Makefile
  38 +++ b/drivers/phy/starfive/Makefile
  39 @@ -1,3 +1,4 @@
  40  # SPDX-License-Identifier: GPL-2.0
  41  obj-$(CONFIG_PHY_STARFIVE_DPHY_RX)      += phy-starfive-dphy-rx.o
  42 +obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
  43  obj-$(CONFIG_PHY_STARFIVE_JH7110_USB)  += phy-jh7110-usb.o
  44 --- /dev/null
  45 +++ b/drivers/phy/starfive/phy-jh7110-pcie.c
  46 @@ -0,0 +1,204 @@
  47 +// SPDX-License-Identifier: GPL-2.0+
  48 +/*
  49 + * StarFive JH7110 PCIe 2.0 PHY driver
  50 + *
  51 + * Copyright (C) 2023 StarFive Technology Co., Ltd.
  52 + * Author: Minda Chen <minda.chen@starfivetech.com>
  53 + */
  54 +
  55 +#include <linux/bits.h>
  56 +#include <linux/clk.h>
  57 +#include <linux/err.h>
  58 +#include <linux/io.h>
  59 +#include <linux/module.h>
  60 +#include <linux/mfd/syscon.h>
  61 +#include <linux/phy/phy.h>
  62 +#include <linux/platform_device.h>
  63 +#include <linux/regmap.h>
  64 +
  65 +#define PCIE_KVCO_LEVEL_OFF            0x28
  66 +#define PCIE_USB3_PHY_PLL_CTL_OFF      0x7c
  67 +#define PCIE_KVCO_TUNE_SIGNAL_OFF      0x80
  68 +#define PCIE_USB3_PHY_ENABLE           BIT(4)
  69 +#define PHY_KVCO_FINE_TUNE_LEVEL       0x91
  70 +#define PHY_KVCO_FINE_TUNE_SIGNALS     0xc
  71 +
  72 +#define USB_PDRSTN_SPLIT               BIT(17)
  73 +
  74 +#define PCIE_PHY_MODE                  BIT(20)
  75 +#define PCIE_PHY_MODE_MASK             GENMASK(21, 20)
  76 +#define PCIE_USB3_BUS_WIDTH_MASK       GENMASK(3, 2)
  77 +#define PCIE_USB3_BUS_WIDTH            BIT(3)
  78 +#define PCIE_USB3_RATE_MASK            GENMASK(6, 5)
  79 +#define PCIE_USB3_RX_STANDBY_MASK      BIT(7)
  80 +#define PCIE_USB3_PHY_ENABLE           BIT(4)
  81 +
  82 +struct jh7110_pcie_phy {
  83 +       struct phy *phy;
  84 +       struct regmap *stg_syscon;
  85 +       struct regmap *sys_syscon;
  86 +       void __iomem *regs;
  87 +       u32 sys_phy_connect;
  88 +       u32 stg_pcie_mode;
  89 +       u32 stg_pcie_usb;
  90 +       enum phy_mode mode;
  91 +};
  92 +
  93 +static int phy_usb3_mode_set(struct jh7110_pcie_phy *data)
  94 +{
  95 +       if (!data->stg_syscon || !data->sys_syscon) {
  96 +               dev_err(&data->phy->dev, "doesn't support usb3 mode\n");
  97 +               return -EINVAL;
  98 +       }
  99 +
 100 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
 101 +                          PCIE_PHY_MODE_MASK, PCIE_PHY_MODE);
 102 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
 103 +                          PCIE_USB3_BUS_WIDTH_MASK, 0);
 104 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
 105 +                          PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE);
 106 +
 107 +       /* Connect usb 3.0 phy mode */
 108 +       regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
 109 +                          USB_PDRSTN_SPLIT, 0);
 110 +
 111 +       /* Configuare spread-spectrum mode: down-spread-spectrum */
 112 +       writel(PCIE_USB3_PHY_ENABLE, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
 113 +
 114 +       return 0;
 115 +}
 116 +
 117 +static void phy_pcie_mode_set(struct jh7110_pcie_phy *data)
 118 +{
 119 +       u32 val;
 120 +
 121 +       /* default is PCIe mode */
 122 +       if (!data->stg_syscon || !data->sys_syscon)
 123 +               return;
 124 +
 125 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_mode,
 126 +                          PCIE_PHY_MODE_MASK, 0);
 127 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
 128 +                          PCIE_USB3_BUS_WIDTH_MASK,
 129 +                          PCIE_USB3_BUS_WIDTH);
 130 +       regmap_update_bits(data->stg_syscon, data->stg_pcie_usb,
 131 +                          PCIE_USB3_PHY_ENABLE, 0);
 132 +
 133 +       regmap_update_bits(data->sys_syscon, data->sys_phy_connect,
 134 +                          USB_PDRSTN_SPLIT, 0);
 135 +
 136 +       val = readl(data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
 137 +       val &= ~PCIE_USB3_PHY_ENABLE;
 138 +       writel(val, data->regs + PCIE_USB3_PHY_PLL_CTL_OFF);
 139 +}
 140 +
 141 +static void phy_kvco_gain_set(struct jh7110_pcie_phy *phy)
 142 +{
 143 +       /* PCIe Multi-PHY PLL KVCO Gain fine tune settings: */
 144 +       writel(PHY_KVCO_FINE_TUNE_LEVEL, phy->regs + PCIE_KVCO_LEVEL_OFF);
 145 +       writel(PHY_KVCO_FINE_TUNE_SIGNALS, phy->regs + PCIE_KVCO_TUNE_SIGNAL_OFF);
 146 +}
 147 +
 148 +static int jh7110_pcie_phy_set_mode(struct phy *_phy,
 149 +                                   enum phy_mode mode, int submode)
 150 +{
 151 +       struct jh7110_pcie_phy *phy = phy_get_drvdata(_phy);
 152 +       int ret;
 153 +
 154 +       if (mode == phy->mode)
 155 +               return 0;
 156 +
 157 +       switch (mode) {
 158 +       case PHY_MODE_USB_HOST:
 159 +       case PHY_MODE_USB_DEVICE:
 160 +       case PHY_MODE_USB_OTG:
 161 +               ret = phy_usb3_mode_set(phy);
 162 +               if (ret)
 163 +                       return ret;
 164 +               break;
 165 +       case PHY_MODE_PCIE:
 166 +               phy_pcie_mode_set(phy);
 167 +               break;
 168 +       default:
 169 +               return -EINVAL;
 170 +       }
 171 +
 172 +       dev_dbg(&_phy->dev, "Changing phy mode to %d\n", mode);
 173 +       phy->mode = mode;
 174 +
 175 +       return 0;
 176 +}
 177 +
 178 +static const struct phy_ops jh7110_pcie_phy_ops = {
 179 +       .set_mode       = jh7110_pcie_phy_set_mode,
 180 +       .owner          = THIS_MODULE,
 181 +};
 182 +
 183 +static int jh7110_pcie_phy_probe(struct platform_device *pdev)
 184 +{
 185 +       struct jh7110_pcie_phy *phy;
 186 +       struct device *dev = &pdev->dev;
 187 +       struct phy_provider *phy_provider;
 188 +       u32 args[2];
 189 +
 190 +       phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
 191 +       if (!phy)
 192 +               return -ENOMEM;
 193 +
 194 +       phy->regs = devm_platform_ioremap_resource(pdev, 0);
 195 +       if (IS_ERR(phy->regs))
 196 +               return PTR_ERR(phy->regs);
 197 +
 198 +       phy->phy = devm_phy_create(dev, NULL, &jh7110_pcie_phy_ops);
 199 +       if (IS_ERR(phy->phy))
 200 +               return dev_err_probe(dev, PTR_ERR(phy->regs),
 201 +                                    "Failed to map phy base\n");
 202 +
 203 +       phy->sys_syscon =
 204 +               syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
 205 +                                                    "starfive,sys-syscon",
 206 +                                                    1, args);
 207 +
 208 +       if (!IS_ERR_OR_NULL(phy->sys_syscon))
 209 +               phy->sys_phy_connect = args[0];
 210 +       else
 211 +               phy->sys_syscon = NULL;
 212 +
 213 +       phy->stg_syscon =
 214 +               syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
 215 +                                                    "starfive,stg-syscon",
 216 +                                                    2, args);
 217 +
 218 +       if (!IS_ERR_OR_NULL(phy->stg_syscon)) {
 219 +               phy->stg_pcie_mode = args[0];
 220 +               phy->stg_pcie_usb = args[1];
 221 +       } else {
 222 +               phy->stg_syscon = NULL;
 223 +       }
 224 +
 225 +       phy_kvco_gain_set(phy);
 226 +
 227 +       phy_set_drvdata(phy->phy, phy);
 228 +       phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 229 +
 230 +       return PTR_ERR_OR_ZERO(phy_provider);
 231 +}
 232 +
 233 +static const struct of_device_id jh7110_pcie_phy_of_match[] = {
 234 +       { .compatible = "starfive,jh7110-pcie-phy" },
 235 +       { /* sentinel */ },
 236 +};
 237 +MODULE_DEVICE_TABLE(of, jh7110_pcie_phy_of_match);
 238 +
 239 +static struct platform_driver jh7110_pcie_phy_driver = {
 240 +       .probe  = jh7110_pcie_phy_probe,
 241 +       .driver = {
 242 +               .of_match_table = jh7110_pcie_phy_of_match,
 243 +               .name  = "jh7110-pcie-phy",
 244 +       }
 245 +};
 246 +module_platform_driver(jh7110_pcie_phy_driver);
 247 +
 248 +MODULE_DESCRIPTION("StarFive JH7110 PCIe 2.0 PHY driver");
 249 +MODULE_AUTHOR("Minda Chen <minda.chen@starfivetech.com>");
 250 +MODULE_LICENSE("GPL");