target/linux/starfive/patches-6.1/0088-dt-bindings-phy-Add-StarFive-JH7110-PCIe-PHY.patch

   1 From d57245d420a2ced6a588cc6e03e2eaacbbf1bfb2 Mon Sep 17 00:00:00 2001
   2 From: Minda Chen <minda.chen@starfivetech.com>
   3 Date: Thu, 18 May 2023 19:27:45 +0800
   4 Subject: [PATCH 088/122] dt-bindings: phy: Add StarFive JH7110 PCIe PHY
   5
   6 Add StarFive JH7110 SoC PCIe 2.0 PHY dt-binding.
   7 PCIe PHY0 (phy@10210000) can be used as USB 3.0 PHY.
   8
   9 Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
  10 Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
  11 Reviewed-by: Rob Herring <robh@kernel.org>
  12 ---
  13  .../phy/starfive,jh7110-pcie-phy.yaml         | 58 +++++++++++++++++++
  14  1 file changed, 58 insertions(+)
  15  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
  16
  17 --- /dev/null
  18 +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-pcie-phy.yaml
  19 @@ -0,0 +1,58 @@
  20 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  21 +%YAML 1.2
  22 +---
  23 +$id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
  24 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  25 +
  26 +title: StarFive JH7110 PCIe 2.0 PHY
  27 +
  28 +maintainers:
  29 +  - Minda Chen <minda.chen@starfivetech.com>
  30 +
  31 +properties:
  32 +  compatible:
  33 +    const: starfive,jh7110-pcie-phy
  34 +
  35 +  reg:
  36 +    maxItems: 1
  37 +
  38 +  "#phy-cells":
  39 +    const: 0
  40 +
  41 +  starfive,sys-syscon:
  42 +    $ref: /schemas/types.yaml#/definitions/phandle-array
  43 +    items:
  44 +      - items:
  45 +          - description: phandle to System Register Controller sys_syscon node.
  46 +          - description: PHY connect offset of SYS_SYSCONSAIF__SYSCFG register for USB PHY.
  47 +    description:
  48 +      The phandle to System Register Controller syscon node and the PHY connect offset
  49 +      of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB3 controller.
  50 +
  51 +  starfive,stg-syscon:
  52 +    $ref: /schemas/types.yaml#/definitions/phandle-array
  53 +    items:
  54 +      - items:
  55 +          - description: phandle to System Register Controller stg_syscon node.
  56 +          - description: PHY mode offset of STG_SYSCONSAIF__SYSCFG register.
  57 +          - description: PHY enable for USB offset of STG_SYSCONSAIF__SYSCFG register.
  58 +    description:
  59 +      The phandle to System Register Controller syscon node and the offset
  60 +      of STG_SYSCONSAIF__SYSCFG register for PCIe PHY. Total 2 regsisters offset.
  61 +
  62 +required:
  63 +  - compatible
  64 +  - reg
  65 +  - "#phy-cells"
  66 +
  67 +additionalProperties: false
  68 +
  69 +examples:
  70 +  - |
  71 +    phy@10210000 {
  72 +        compatible = "starfive,jh7110-pcie-phy";
  73 +        reg = <0x10210000 0x10000>;
  74 +        #phy-cells = <0>;
  75 +        starfive,sys-syscon = <&sys_syscon 0x18>;
  76 +        starfive,stg-syscon = <&stg_syscon 0x148 0x1f4>;
  77 +    };