target/linux/starfive/patches-6.1/0060-clocksource-Add-StarFive-timer-driver.patch

   1 From 3fbdabd59bac0978536fb11b1b9deb81559f1c54 Mon Sep 17 00:00:00 2001
   2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
   3 Date: Mon, 20 Mar 2023 21:54:32 +0800
   4 Subject: [PATCH 060/122] clocksource: Add StarFive timer driver
   5
   6 Add timer driver for the StarFive JH7110 SoC.
   7
   8 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
   9 ---
  10  drivers/clocksource/Kconfig          |  12 +
  11  drivers/clocksource/Makefile         |   1 +
  12  drivers/clocksource/timer-starfive.c | 390 +++++++++++++++++++++++++++
  13  drivers/clocksource/timer-starfive.h |  96 +++++++
  14  4 files changed, 499 insertions(+)
  15  create mode 100644 drivers/clocksource/timer-starfive.c
  16  create mode 100644 drivers/clocksource/timer-starfive.h
  17
  18 --- a/drivers/clocksource/Kconfig
  19 +++ b/drivers/clocksource/Kconfig
  20 @@ -630,6 +630,18 @@ config RISCV_TIMER
  21           is accessed via both the SBI and the rdcycle instruction.  This is
  22           required for all RISC-V systems.
  23
  24 +config STARFIVE_TIMER
  25 +       bool "Timer for the STARFIVE SoCs"
  26 +       depends on ARCH_STARFIVE || COMPILE_TEST
  27 +       select TIMER_OF
  28 +       select CLKSRC_MMIO
  29 +       default ARCH_STARFIVE
  30 +       help
  31 +         This enables the timer for StarFive SoCs. On RISC-V platform,
  32 +         the system has started RISCV_TIMER. But you can also use this timer
  33 +         to do a lot more on StarFive SoCs. This timer can provide high
  34 +         precision and four channels to use in JH7110 SoC.
  35 +
  36  config CLINT_TIMER
  37         bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
  38         depends on GENERIC_SCHED_CLOCK && RISCV
  39 --- a/drivers/clocksource/Makefile
  40 +++ b/drivers/clocksource/Makefile
  41 @@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER)           += ingenic-
  42  obj-$(CONFIG_CLKSRC_ST_LPC)            += clksrc_st_lpc.o
  43  obj-$(CONFIG_X86_NUMACHIP)             += numachip.o
  44  obj-$(CONFIG_RISCV_TIMER)              += timer-riscv.o
  45 +obj-$(CONFIG_STARFIVE_TIMER)           += timer-starfive.o
  46  obj-$(CONFIG_CLINT_TIMER)              += timer-clint.o
  47  obj-$(CONFIG_CSKY_MP_TIMER)            += timer-mp-csky.o
  48  obj-$(CONFIG_GX6605S_TIMER)            += timer-gx6605s.o
  49 --- /dev/null
  50 +++ b/drivers/clocksource/timer-starfive.c
  51 @@ -0,0 +1,390 @@
  52 +// SPDX-License-Identifier: GPL-2.0
  53 +/*
  54 + * Starfive Timer driver
  55 + *
  56 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
  57 + *
  58 + * Author:
  59 + * Xingyu Wu <xingyu.wu@starfivetech.com>
  60 + * Samin Guo <samin.guo@starfivetech.com>
  61 + */
  62 +
  63 +#include <linux/clk.h>
  64 +#include <linux/clockchips.h>
  65 +#include <linux/clocksource.h>
  66 +#include <linux/err.h>
  67 +#include <linux/interrupt.h>
  68 +#include <linux/io.h>
  69 +#include <linux/iopoll.h>
  70 +#include <linux/irq.h>
  71 +#include <linux/kernel.h>
  72 +#include <linux/module.h>
  73 +#include <linux/of.h>
  74 +#include <linux/of_device.h>
  75 +#include <linux/platform_device.h>
  76 +#include <linux/reset.h>
  77 +#include <linux/sched_clock.h>
  78 +
  79 +#include "timer-starfive.h"
  80 +
  81 +static const struct starfive_timer_chan_base starfive_timer_jh7110_base = {
  82 +       .ctrl           = STARFIVE_TIMER_JH7110_CTL,
  83 +       .load           = STARFIVE_TIMER_JH7110_LOAD,
  84 +       .enable         = STARFIVE_TIMER_JH7110_ENABLE,
  85 +       .reload         = STARFIVE_TIMER_JH7110_RELOAD,
  86 +       .value          = STARFIVE_TIMER_JH7110_VALUE,
  87 +       .intclr         = STARFIVE_TIMER_JH7110_INT_CLR,
  88 +       .intmask        = STARFIVE_TIMER_JH7110_INT_MASK,
  89 +       .channel_num    = STARFIVE_TIMER_CH_4,
  90 +       .channel_base   = {STARFIVE_TIMER_CH_BASE(0), STARFIVE_TIMER_CH_BASE(1),
  91 +                          STARFIVE_TIMER_CH_BASE(2), STARFIVE_TIMER_CH_BASE(3)},
  92 +};
  93 +
  94 +static inline struct starfive_clkevt *to_starfive_clkevt(struct clock_event_device *evt)
  95 +{
  96 +       return container_of(evt, struct starfive_clkevt, evt);
  97 +}
  98 +
  99 +/* 0:continuous-run mode, 1:single-run mode */
 100 +static inline void starfive_timer_set_mod(struct starfive_clkevt *clkevt, int mod)
 101 +{
 102 +       writel(mod, clkevt->ctrl);
 103 +}
 104 +
 105 +/* Interrupt Mask Register, 0:Unmask, 1:Mask */
 106 +static inline void starfive_timer_int_enable(struct starfive_clkevt *clkevt)
 107 +{
 108 +       writel(STARFIVE_TIMER_INTMASK_DIS, clkevt->intmask);
 109 +}
 110 +
 111 +static inline void starfive_timer_int_disable(struct starfive_clkevt *clkevt)
 112 +{
 113 +       writel(STARFIVE_TIMER_INTMASK_ENA, clkevt->intmask);
 114 +}
 115 +
 116 +/*
 117 + * BIT(0): Read value represent channel intr status.
 118 + * Write 1 to this bit to clear interrupt. Write 0 has no effects.
 119 + * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written.
 120 + */
 121 +static inline int starfive_timer_int_clear(struct starfive_clkevt *clkevt)
 122 +{
 123 +       u32 value;
 124 +       int ret;
 125 +
 126 +       /* waiting interrupt can be to clearing */
 127 +       ret = readl_poll_timeout_atomic(clkevt->intclr, value,
 128 +                                       !(value & STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK),
 129 +                                       STARFIVE_DELAY_US, STARFIVE_TIMEOUT_US);
 130 +       if (!ret)
 131 +               writel(0x1, clkevt->intclr);
 132 +
 133 +       return ret;
 134 +}
 135 +
 136 +/*
 137 + * The initial value to be loaded into the
 138 + * counter and is also used as the reload value.
 139 + * val = clock rate --> 1s
 140 + */
 141 +static inline void starfive_timer_set_load(struct starfive_clkevt *clkevt, u32 val)
 142 +{
 143 +       writel(val, clkevt->load);
 144 +}
 145 +
 146 +static inline u32 starfive_timer_get_val(struct starfive_clkevt *clkevt)
 147 +{
 148 +       return readl(clkevt->value);
 149 +}
 150 +
 151 +/*
 152 + * Write RELOAD register to reload preset value to counter.
 153 + * (Write 0 and write 1 are both ok)
 154 + */
 155 +static inline void starfive_timer_set_reload(struct starfive_clkevt *clkevt)
 156 +{
 157 +       writel(0, clkevt->reload);
 158 +}
 159 +
 160 +static inline void starfive_timer_enable(struct starfive_clkevt *clkevt)
 161 +{
 162 +       writel(STARFIVE_TIMER_ENA, clkevt->enable);
 163 +}
 164 +
 165 +static inline void starfive_timer_disable(struct starfive_clkevt *clkevt)
 166 +{
 167 +       writel(STARFIVE_TIMER_DIS, clkevt->enable);
 168 +}
 169 +
 170 +static int starfive_timer_int_init_enable(struct starfive_clkevt *clkevt)
 171 +{
 172 +       int ret;
 173 +
 174 +       starfive_timer_int_disable(clkevt);
 175 +       ret = starfive_timer_int_clear(clkevt);
 176 +       if (ret)
 177 +               return ret;
 178 +
 179 +       starfive_timer_int_enable(clkevt);
 180 +       starfive_timer_enable(clkevt);
 181 +
 182 +       return 0;
 183 +}
 184 +
 185 +static int starfive_timer_shutdown(struct clock_event_device *evt)
 186 +{
 187 +       struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
 188 +
 189 +       starfive_timer_disable(clkevt);
 190 +       return starfive_timer_int_clear(clkevt);
 191 +}
 192 +
 193 +static void starfive_timer_suspend(struct clock_event_device *evt)
 194 +{
 195 +       struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
 196 +
 197 +       clkevt->reload_val = starfive_timer_get_val(clkevt);
 198 +       starfive_timer_shutdown(evt);
 199 +}
 200 +
 201 +static void starfive_timer_resume(struct clock_event_device *evt)
 202 +{
 203 +       struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
 204 +
 205 +       starfive_timer_set_load(clkevt, clkevt->reload_val);
 206 +       starfive_timer_set_reload(clkevt);
 207 +       starfive_timer_int_enable(clkevt);
 208 +       starfive_timer_enable(clkevt);
 209 +}
 210 +
 211 +static int starfive_timer_tick_resume(struct clock_event_device *evt)
 212 +{
 213 +       starfive_timer_resume(evt);
 214 +
 215 +       return 0;
 216 +}
 217 +
 218 +static int starfive_clocksource_init(struct starfive_clkevt *clkevt)
 219 +{
 220 +       int ret;
 221 +
 222 +       starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
 223 +       starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
 224 +       ret = starfive_timer_int_init_enable(clkevt);
 225 +       if (ret)
 226 +               return ret;
 227 +
 228 +       return clocksource_mmio_init(clkevt->value, clkevt->name, clkevt->rate,
 229 +                                    STARFIVE_CLOCK_SOURCE_RATING, STARFIVE_VALID_BITS,
 230 +                                    clocksource_mmio_readl_down);
 231 +}
 232 +
 233 +/* IRQ handler for the timer */
 234 +static irqreturn_t starfive_timer_interrupt(int irq, void *priv)
 235 +{
 236 +       struct clock_event_device *evt = (struct clock_event_device *)priv;
 237 +       struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
 238 +
 239 +       if (starfive_timer_int_clear(clkevt))
 240 +               return IRQ_NONE;
 241 +
 242 +       if (evt->event_handler)
 243 +               evt->event_handler(evt);
 244 +
 245 +       return IRQ_HANDLED;
 246 +}
 247 +
 248 +static int starfive_timer_set_periodic(struct clock_event_device *evt)
 249 +{
 250 +       struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
 251 +
 252 +       starfive_timer_disable(clkevt);
 253 +       starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_CONTIN);
 254 +       starfive_timer_set_load(clkevt, clkevt->periodic);
 255 +
 256 +       return starfive_timer_int_init_enable(clkevt);
 257 +}
 258 +
 259 +static int starfive_timer_set_oneshot(struct clock_event_device *evt)
 260 +{
 261 +       struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
 262 +
 263 +       starfive_timer_disable(clkevt);
 264 +       starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
 265 +       starfive_timer_set_load(clkevt, STARFIVE_TIMER_MAX_TICKS);
 266 +
 267 +       return starfive_timer_int_init_enable(clkevt);
 268 +}
 269 +
 270 +static int starfive_timer_set_next_event(unsigned long next,
 271 +                                        struct clock_event_device *evt)
 272 +{
 273 +       struct starfive_clkevt *clkevt = to_starfive_clkevt(evt);
 274 +
 275 +       starfive_timer_disable(clkevt);
 276 +       starfive_timer_set_mod(clkevt, STARFIVE_TIMER_MOD_SINGLE);
 277 +       starfive_timer_set_load(clkevt, next);
 278 +       starfive_timer_enable(clkevt);
 279 +
 280 +       return 0;
 281 +}
 282 +
 283 +static void starfive_set_clockevent(struct clock_event_device *evt)
 284 +{
 285 +       evt->features = CLOCK_EVT_FEAT_PERIODIC |
 286 +                       CLOCK_EVT_FEAT_ONESHOT |
 287 +                       CLOCK_EVT_FEAT_DYNIRQ;
 288 +       evt->set_state_shutdown = starfive_timer_shutdown;
 289 +       evt->set_state_periodic = starfive_timer_set_periodic;
 290 +       evt->set_state_oneshot = starfive_timer_set_oneshot;
 291 +       evt->set_state_oneshot_stopped = starfive_timer_shutdown;
 292 +       evt->tick_resume = starfive_timer_tick_resume;
 293 +       evt->set_next_event = starfive_timer_set_next_event;
 294 +       evt->suspend = starfive_timer_suspend;
 295 +       evt->resume = starfive_timer_resume;
 296 +       evt->rating = STARFIVE_CLOCKEVENT_RATING;
 297 +}
 298 +
 299 +static void starfive_clockevents_register(struct starfive_clkevt *clkevt)
 300 +{
 301 +       clkevt->rate = clk_get_rate(clkevt->clk);
 302 +       clkevt->periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ);
 303 +
 304 +       starfive_set_clockevent(&clkevt->evt);
 305 +       clkevt->evt.name = clkevt->name;
 306 +       clkevt->evt.irq = clkevt->irq;
 307 +       clkevt->evt.cpumask = cpu_possible_mask;
 308 +
 309 +       clockevents_config_and_register(&clkevt->evt, clkevt->rate,
 310 +                                       STARFIVE_TIMER_MIN_TICKS, STARFIVE_TIMER_MAX_TICKS);
 311 +}
 312 +
 313 +static void __init starfive_clkevt_base_init(const struct starfive_timer_chan_base *timer,
 314 +                                            struct starfive_clkevt *clkevt,
 315 +                                            void __iomem *base, int ch)
 316 +{
 317 +       void __iomem *channel_base;
 318 +
 319 +       channel_base = base + timer->channel_base[ch];
 320 +       clkevt->base = channel_base;
 321 +       clkevt->ctrl = channel_base + timer->ctrl;
 322 +       clkevt->load = channel_base + timer->load;
 323 +       clkevt->enable = channel_base + timer->enable;
 324 +       clkevt->reload = channel_base + timer->reload;
 325 +       clkevt->value = channel_base + timer->value;
 326 +       clkevt->intclr = channel_base + timer->intclr;
 327 +       clkevt->intmask = channel_base + timer->intmask;
 328 +}
 329 +
 330 +static int __init starfive_timer_probe(struct platform_device *pdev)
 331 +{
 332 +       const struct starfive_timer_chan_base *timer_base = of_device_get_match_data(&pdev->dev);
 333 +       char name[10];
 334 +       struct starfive_timer_priv *priv;
 335 +       struct starfive_clkevt *clkevt;
 336 +       struct clk *pclk;
 337 +       struct reset_control *rst;
 338 +       int ch;
 339 +       int ret;
 340 +
 341 +       priv = devm_kzalloc(&pdev->dev, struct_size(priv, clkevt, timer_base->channel_num),
 342 +                           GFP_KERNEL);
 343 +       if (!priv)
 344 +               return -ENOMEM;
 345 +
 346 +       priv->base = devm_platform_ioremap_resource(pdev, 0);
 347 +       if (IS_ERR(priv->base))
 348 +               return dev_err_probe(&pdev->dev, PTR_ERR(priv->base),
 349 +                                    "failed to map registers\n");
 350 +
 351 +       rst = devm_reset_control_get_exclusive(&pdev->dev, "apb");
 352 +       if (IS_ERR(rst))
 353 +               return dev_err_probe(&pdev->dev, PTR_ERR(rst), "failed to get apb reset\n");
 354 +
 355 +       pclk = devm_clk_get_enabled(&pdev->dev, "apb");
 356 +       if (IS_ERR(pclk))
 357 +               return dev_err_probe(&pdev->dev, PTR_ERR(pclk),
 358 +                                    "failed to get & enable apb clock\n");
 359 +
 360 +       ret = reset_control_deassert(rst);
 361 +       if (ret)
 362 +               goto err;
 363 +
 364 +       priv->dev = &pdev->dev;
 365 +       platform_set_drvdata(pdev, priv);
 366 +
 367 +       for (ch = 0; ch < timer_base->channel_num; ch++) {
 368 +               clkevt = &priv->clkevt[ch];
 369 +               snprintf(name, sizeof(name), "ch%d", ch);
 370 +
 371 +               starfive_clkevt_base_init(timer_base, clkevt, priv->base, ch);
 372 +               /* Ensure timers are disabled */
 373 +               starfive_timer_disable(clkevt);
 374 +
 375 +               rst = devm_reset_control_get_exclusive(&pdev->dev, name);
 376 +               if (IS_ERR(rst)) {
 377 +                       ret = PTR_ERR(rst);
 378 +                       goto err;
 379 +               }
 380 +
 381 +               clkevt->clk = devm_clk_get_enabled(&pdev->dev, name);
 382 +               if (IS_ERR(clkevt->clk)) {
 383 +                       ret = PTR_ERR(clkevt->clk);
 384 +                       goto err;
 385 +               }
 386 +
 387 +               ret = reset_control_deassert(rst);
 388 +               if (ret)
 389 +                       goto ch_err;
 390 +
 391 +               clkevt->irq = platform_get_irq(pdev, ch);
 392 +               if (clkevt->irq < 0) {
 393 +                       ret = clkevt->irq;
 394 +                       goto ch_err;
 395 +               }
 396 +
 397 +               snprintf(clkevt->name, sizeof(clkevt->name), "%s.ch%d", pdev->name, ch);
 398 +               starfive_clockevents_register(clkevt);
 399 +
 400 +               ret = devm_request_irq(&pdev->dev, clkevt->irq, starfive_timer_interrupt,
 401 +                                      IRQF_TIMER | IRQF_IRQPOLL,
 402 +                                      clkevt->name, &clkevt->evt);
 403 +               if (ret)
 404 +                       goto ch_err;
 405 +
 406 +               ret = starfive_clocksource_init(clkevt);
 407 +               if (ret)
 408 +                       goto ch_err;
 409 +       }
 410 +
 411 +       return 0;
 412 +
 413 +ch_err:
 414 +       /* Only unregister the failed channel and the rest timer channels continue to work. */
 415 +       clk_disable_unprepare(clkevt->clk);
 416 +err:
 417 +       /* If no other channel successfully registers, pclk should be disabled. */
 418 +       if (!ch)
 419 +               clk_disable_unprepare(pclk);
 420 +
 421 +       return ret;
 422 +}
 423 +
 424 +static const struct of_device_id starfive_timer_match[] = {
 425 +       { .compatible = "starfive,jh7110-timer", .data = &starfive_timer_jh7110_base },
 426 +       { /* sentinel */ }
 427 +};
 428 +MODULE_DEVICE_TABLE(of, starfive_timer_match);
 429 +
 430 +static struct platform_driver starfive_timer_driver = {
 431 +       .probe = starfive_timer_probe,
 432 +       .driver = {
 433 +               .name = "starfive-timer",
 434 +               .of_match_table = starfive_timer_match,
 435 +       },
 436 +};
 437 +module_platform_driver(starfive_timer_driver);
 438 +
 439 +MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
 440 +MODULE_DESCRIPTION("StarFive timer driver");
 441 +MODULE_LICENSE("GPL");
 442 --- /dev/null
 443 +++ b/drivers/clocksource/timer-starfive.h
 444 @@ -0,0 +1,96 @@
 445 +/* SPDX-License-Identifier: GPL-2.0 */
 446 +/*
 447 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
 448 + */
 449 +
 450 +#ifndef __STARFIVE_TIMER_H__
 451 +#define __STARFIVE_TIMER_H__
 452 +
 453 +/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */
 454 +#define STARFIVE_TIMER_CH_LEN                  0x40
 455 +#define STARFIVE_TIMER_CH_BASE(x)              ((STARFIVE_TIMER_CH_##x) * STARFIVE_TIMER_CH_LEN)
 456 +
 457 +#define STARFIVE_CLOCK_SOURCE_RATING           200
 458 +#define STARFIVE_VALID_BITS                    32
 459 +#define STARFIVE_DELAY_US                      0
 460 +#define STARFIVE_TIMEOUT_US                    10000
 461 +#define STARFIVE_CLOCKEVENT_RATING             300
 462 +#define STARFIVE_TIMER_MAX_TICKS               0xffffffff
 463 +#define STARFIVE_TIMER_MIN_TICKS               0xf
 464 +
 465 +#define STARFIVE_TIMER_JH7110_INT_STATUS       0x00 /* RO[0:4]: Interrupt Status for channel0~4 */
 466 +#define STARFIVE_TIMER_JH7110_CTL              0x04 /* RW[0]: 0-continuous run, 1-single run */
 467 +#define STARFIVE_TIMER_JH7110_LOAD             0x08 /* RW: load value to counter */
 468 +#define STARFIVE_TIMER_JH7110_ENABLE           0x10 /* RW[0]: timer enable register */
 469 +#define STARFIVE_TIMER_JH7110_RELOAD           0x14 /* RW: write 1 or 0 both reload counter */
 470 +#define STARFIVE_TIMER_JH7110_VALUE            0x18 /* RO: timer value register */
 471 +#define STARFIVE_TIMER_JH7110_INT_CLR          0x20 /* RW: timer interrupt clear register */
 472 +#define STARFIVE_TIMER_JH7110_INT_MASK         0x24 /* RW[0]: timer interrupt mask register */
 473 +#define STARFIVE_TIMER_JH7110_INT_CLR_AVA_MASK BIT(1)
 474 +
 475 +enum STARFIVE_TIMER_CH {
 476 +       STARFIVE_TIMER_CH_0 = 0,
 477 +       STARFIVE_TIMER_CH_1,
 478 +       STARFIVE_TIMER_CH_2,
 479 +       STARFIVE_TIMER_CH_3,
 480 +       STARFIVE_TIMER_CH_4,
 481 +       STARFIVE_TIMER_CH_5,
 482 +       STARFIVE_TIMER_CH_6,
 483 +       STARFIVE_TIMER_CH_7,
 484 +       STARFIVE_TIMER_CH_MAX
 485 +};
 486 +
 487 +enum STARFIVE_TIMER_INTMASK {
 488 +       STARFIVE_TIMER_INTMASK_DIS = 0,
 489 +       STARFIVE_TIMER_INTMASK_ENA = 1
 490 +};
 491 +
 492 +enum STARFIVE_TIMER_MOD {
 493 +       STARFIVE_TIMER_MOD_CONTIN = 0,
 494 +       STARFIVE_TIMER_MOD_SINGLE = 1
 495 +};
 496 +
 497 +enum STARFIVE_TIMER_CTL_EN {
 498 +       STARFIVE_TIMER_DIS = 0,
 499 +       STARFIVE_TIMER_ENA = 1
 500 +};
 501 +
 502 +struct starfive_timer_chan_base {
 503 +       /* Resgister */
 504 +       unsigned int ctrl;
 505 +       unsigned int load;
 506 +       unsigned int enable;
 507 +       unsigned int reload;
 508 +       unsigned int value;
 509 +       unsigned int intclr;
 510 +       unsigned int intmask;
 511 +
 512 +       unsigned int channel_num;       /* timer channel numbers */
 513 +       unsigned int channel_base[];
 514 +};
 515 +
 516 +struct starfive_clkevt {
 517 +       struct clock_event_device evt;
 518 +       struct clk *clk;
 519 +       char name[20];
 520 +       int irq;
 521 +       u32 periodic;
 522 +       u32 rate;
 523 +       u32 reload_val;
 524 +       void __iomem *base;
 525 +       void __iomem *ctrl;
 526 +       void __iomem *load;
 527 +       void __iomem *enable;
 528 +       void __iomem *reload;
 529 +       void __iomem *value;
 530 +       void __iomem *intclr;
 531 +       void __iomem *intmask;
 532 +};
 533 +
 534 +struct starfive_timer_priv {
 535 +       struct device *dev;
 536 +       void __iomem *base;
 537 +       struct starfive_clkevt clkevt[];
 538 +};
 539 +
 540 +#endif /* __STARFIVE_TIMER_H__ */