target/linux/starfive/patches-6.1/0053-dt-bindings-clock-Add-StarFive-JH7110-Image-Signal-P.patch

   1 From 70df2590923e262ce8bf2b4f497f3481511d4fd6 Mon Sep 17 00:00:00 2001
   2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
   3 Date: Thu, 18 May 2023 18:12:26 +0800
   4 Subject: [PATCH 053/122] dt-bindings: clock: Add StarFive JH7110
   5  Image-Signal-Process clock and reset generator
   6
   7 Add bindings for the Image-Signal-Process clock and reset
   8 generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.
   9
  10 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  11 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
  12 ---
  13  .../clock/starfive,jh7110-ispcrg.yaml         | 87 +++++++++++++++++++
  14  .../dt-bindings/clock/starfive,jh7110-crg.h   | 18 ++++
  15  .../dt-bindings/reset/starfive,jh7110-crg.h   | 16 ++++
  16  3 files changed, 121 insertions(+)
  17  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
  18
  19 --- /dev/null
  20 +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-ispcrg.yaml
  21 @@ -0,0 +1,87 @@
  22 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  23 +%YAML 1.2
  24 +---
  25 +$id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
  26 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  27 +
  28 +title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
  29 +
  30 +maintainers:
  31 +  - Xingyu Wu <xingyu.wu@starfivetech.com>
  32 +
  33 +properties:
  34 +  compatible:
  35 +    const: starfive,jh7110-ispcrg
  36 +
  37 +  reg:
  38 +    maxItems: 1
  39 +
  40 +  clocks:
  41 +    items:
  42 +      - description: ISP Top core
  43 +      - description: ISP Top Axi
  44 +      - description: NOC ISP Bus
  45 +      - description: external DVP
  46 +
  47 +  clock-names:
  48 +    items:
  49 +      - const: isp_top_core
  50 +      - const: isp_top_axi
  51 +      - const: noc_bus_isp_axi
  52 +      - const: dvp_clk
  53 +
  54 +  resets:
  55 +    items:
  56 +      - description: ISP Top core
  57 +      - description: ISP Top Axi
  58 +      - description: NOC ISP Bus
  59 +
  60 +  '#clock-cells':
  61 +    const: 1
  62 +    description:
  63 +      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
  64 +
  65 +  '#reset-cells':
  66 +    const: 1
  67 +    description:
  68 +      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
  69 +
  70 +  power-domains:
  71 +    maxItems: 1
  72 +    description:
  73 +      ISP domain power
  74 +
  75 +required:
  76 +  - compatible
  77 +  - reg
  78 +  - clocks
  79 +  - clock-names
  80 +  - resets
  81 +  - '#clock-cells'
  82 +  - '#reset-cells'
  83 +  - power-domains
  84 +
  85 +additionalProperties: false
  86 +
  87 +examples:
  88 +  - |
  89 +    #include <dt-bindings/clock/starfive,jh7110-crg.h>
  90 +    #include <dt-bindings/power/starfive,jh7110-pmu.h>
  91 +    #include <dt-bindings/reset/starfive,jh7110-crg.h>
  92 +
  93 +    ispcrg: clock-controller@19810000 {
  94 +        compatible = "starfive,jh7110-ispcrg";
  95 +        reg = <0x19810000 0x10000>;
  96 +        clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
  97 +                 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
  98 +                 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
  99 +                 <&dvp_clk>;
 100 +        clock-names = "isp_top_core", "isp_top_axi",
 101 +                      "noc_bus_isp_axi", "dvp_clk";
 102 +        resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
 103 +                 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
 104 +                 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
 105 +        #clock-cells = <1>;
 106 +        #reset-cells = <1>;
 107 +        power-domains = <&pwrc JH7110_PD_ISP>;
 108 +    };
 109 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
 110 +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
 111 @@ -258,4 +258,22 @@
 112
 113  #define JH7110_STGCLK_END                      29
 114
 115 +/* ISPCRG clocks */
 116 +#define JH7110_ISPCLK_DOM4_APB_FUNC            0
 117 +#define JH7110_ISPCLK_MIPI_RX0_PXL             1
 118 +#define JH7110_ISPCLK_DVP_INV                  2
 119 +#define JH7110_ISPCLK_M31DPHY_CFG_IN           3
 120 +#define JH7110_ISPCLK_M31DPHY_REF_IN           4
 121 +#define JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0      5
 122 +#define JH7110_ISPCLK_VIN_APB                  6
 123 +#define JH7110_ISPCLK_VIN_SYS                  7
 124 +#define JH7110_ISPCLK_VIN_PIXEL_IF0            8
 125 +#define JH7110_ISPCLK_VIN_PIXEL_IF1            9
 126 +#define JH7110_ISPCLK_VIN_PIXEL_IF2            10
 127 +#define JH7110_ISPCLK_VIN_PIXEL_IF3            11
 128 +#define JH7110_ISPCLK_VIN_P_AXI_WR             12
 129 +#define JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C      13
 130 +
 131 +#define JH7110_ISPCLK_END                      14
 132 +
 133  #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
 134 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h
 135 +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
 136 @@ -179,4 +179,20 @@
 137
 138  #define JH7110_STGRST_END                      23
 139
 140 +/* ISPCRG resets */
 141 +#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_P      0
 142 +#define JH7110_ISPRST_ISPV2_TOP_WRAPPER_C      1
 143 +#define JH7110_ISPRST_M31DPHY_HW               2
 144 +#define JH7110_ISPRST_M31DPHY_B09_AON          3
 145 +#define JH7110_ISPRST_VIN_APB                  4
 146 +#define JH7110_ISPRST_VIN_PIXEL_IF0            5
 147 +#define JH7110_ISPRST_VIN_PIXEL_IF1            6
 148 +#define JH7110_ISPRST_VIN_PIXEL_IF2            7
 149 +#define JH7110_ISPRST_VIN_PIXEL_IF3            8
 150 +#define JH7110_ISPRST_VIN_SYS                  9
 151 +#define JH7110_ISPRST_VIN_P_AXI_RD             10
 152 +#define JH7110_ISPRST_VIN_P_AXI_WR             11
 153 +
 154 +#define JH7110_ISPRST_END                      12
 155 +
 156  #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */