target/linux/starfive/patches-6.1/0047-riscv-dts-starfive-visionfive-2-Add-configuration-of.patch

   1 From 6fd84cb9cceaa711671500a92dcee5b1072ab95a Mon Sep 17 00:00:00 2001
   2 From: Samin Guo <samin.guo@starfivetech.com>
   3 Date: Tue, 1 Nov 2022 18:11:02 +0800
   4 Subject: [PATCH 047/122] riscv: dts: starfive: visionfive 2: Add configuration
   5  of gmac and phy
   6
   7 v1.3B:
   8   v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and
   9   inverse configurations.
  10   The tx_clk of v1.3B uses an external clock and needs to be
  11   switched to an external clock source.
  12
  13 v1.2A:
  14   v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay
  15   configurations.
  16   v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to
  17   switch rx and rx to external clock sources.
  18
  19 Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
  20 Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
  21 ---
  22  .../jh7110-starfive-visionfive-2-v1.2a.dts    | 13 +++++++
  23  .../jh7110-starfive-visionfive-2-v1.3b.dts    | 27 +++++++++++++++
  24  .../jh7110-starfive-visionfive-2.dtsi         | 34 +++++++++++++++++++
  25  3 files changed, 74 insertions(+)
  26
  27 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
  28 +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
  29 @@ -11,3 +11,16 @@
  30         model = "StarFive VisionFive 2 v1.2A";
  31         compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
  32  };
  33 +
  34 +&gmac1 {
  35 +       phy-mode = "rmii";
  36 +       assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>,
  37 +                         <&syscrg JH7110_SYSCLK_GMAC1_RX>;
  38 +       assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>,
  39 +                                <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
  40 +};
  41 +
  42 +&phy0 {
  43 +       rx-internal-delay-ps = <1900>;
  44 +       tx-internal-delay-ps = <1350>;
  45 +};
  46 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
  47 +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
  48 @@ -11,3 +11,30 @@
  49         model = "StarFive VisionFive 2 v1.3B";
  50         compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
  51  };
  52 +
  53 +&gmac0 {
  54 +       starfive,tx-use-rgmii-clk;
  55 +       assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
  56 +       assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
  57 +};
  58 +
  59 +&gmac1 {
  60 +       starfive,tx-use-rgmii-clk;
  61 +       assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
  62 +       assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
  63 +};
  64 +
  65 +&phy0 {
  66 +       motorcomm,tx-clk-adj-enabled;
  67 +       motorcomm,tx-clk-100-inverted;
  68 +       motorcomm,tx-clk-1000-inverted;
  69 +       rx-internal-delay-ps = <1500>;
  70 +       tx-internal-delay-ps = <1500>;
  71 +};
  72 +
  73 +&phy1 {
  74 +       motorcomm,tx-clk-adj-enabled;
  75 +       motorcomm,tx-clk-100-inverted;
  76 +       rx-internal-delay-ps = <300>;
  77 +       tx-internal-delay-ps = <0>;
  78 +};
  79 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
  80 +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
  81 @@ -11,6 +11,8 @@
  82
  83  / {
  84         aliases {
  85 +               ethernet0 = &gmac0;
  86 +               ethernet1 = &gmac1;
  87                 i2c0 = &i2c0;
  88                 i2c2 = &i2c2;
  89                 i2c5 = &i2c5;
  90 @@ -86,6 +88,38 @@
  91         clock-frequency = <49152000>;
  92  };
  93
  94 +&gmac0 {
  95 +       phy-handle = <&phy0>;
  96 +       phy-mode = "rgmii-id";
  97 +       status = "okay";
  98 +
  99 +       mdio {
 100 +               #address-cells = <1>;
 101 +               #size-cells = <0>;
 102 +               compatible = "snps,dwmac-mdio";
 103 +
 104 +               phy0: ethernet-phy@0 {
 105 +                       reg = <0>;
 106 +               };
 107 +       };
 108 +};
 109 +
 110 +&gmac1 {
 111 +       phy-handle = <&phy1>;
 112 +       phy-mode = "rgmii-id";
 113 +       status = "okay";
 114 +
 115 +       mdio {
 116 +               #address-cells = <1>;
 117 +               #size-cells = <0>;
 118 +               compatible = "snps,dwmac-mdio";
 119 +
 120 +               phy1: ethernet-phy@1 {
 121 +                       reg = <0>;
 122 +               };
 123 +       };
 124 +};
 125 +
 126  &i2c0 {
 127         clock-frequency = <100000>;
 128         i2c-sda-hold-time-ns = <300>;