target/linux/starfive/patches-6.1/0039-riscv-dts-starfive-jh7110-Add-PLL-clock-node-and-mod.patch

   1 From f0548ab9212ef35abe79f46e5f509f4fc9d78699 Mon Sep 17 00:00:00 2001
   2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
   3 Date: Mon, 20 Feb 2023 14:33:33 +0800
   4 Subject: [PATCH 039/122] riscv: dts: starfive: jh7110: Add PLL clock node and
   5  modify syscrg node
   6
   7 Add the PLL clock node for the Starfive JH7110 SoC and
   8 modify the SYSCRG node to add PLL clocks input.
   9
  10 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
  11 ---
  12  arch/riscv/boot/dts/starfive/jh7110.dtsi | 14 ++++++++++++--
  13  1 file changed, 12 insertions(+), 2 deletions(-)
  14
  15 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
  16 +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
  17 @@ -452,12 +452,16 @@
  18                                  <&gmac1_rgmii_rxin>,
  19                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
  20                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
  21 -                                <&tdm_ext>, <&mclk_ext>;
  22 +                                <&tdm_ext>, <&mclk_ext>,
  23 +                                <&pllclk JH7110_CLK_PLL0_OUT>,
  24 +                                <&pllclk JH7110_CLK_PLL1_OUT>,
  25 +                                <&pllclk JH7110_CLK_PLL2_OUT>;
  26                         clock-names = "osc", "gmac1_rmii_refin",
  27                                       "gmac1_rgmii_rxin",
  28                                       "i2stx_bclk_ext", "i2stx_lrck_ext",
  29                                       "i2srx_bclk_ext", "i2srx_lrck_ext",
  30 -                                     "tdm_ext", "mclk_ext";
  31 +                                     "tdm_ext", "mclk_ext",
  32 +                                     "pll0_out", "pll1_out", "pll2_out";
  33                         #clock-cells = <1>;
  34                         #reset-cells = <1>;
  35                 };
  36 @@ -465,6 +469,12 @@
  37                 sys_syscon: syscon@13030000 {
  38                         compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
  39                         reg = <0x0 0x13030000 0x0 0x1000>;
  40 +
  41 +                       pllclk: clock-controller {
  42 +                               compatible = "starfive,jh7110-pll";
  43 +                               clocks = <&osc>;
  44 +                               #clock-cells = <1>;
  45 +                       };
  46                 };
  47
  48                 sysgpio: pinctrl@13040000 {