target/linux/starfive/patches-6.1/0031-dt-bindings-clock-Add-StarFive-JH7110-PLL-clock-gene.patch

   1 From 07f62b08668c0295b1c6342f9708b7e36093ff59 Mon Sep 17 00:00:00 2001
   2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
   3 Date: Tue, 21 Feb 2023 17:13:48 +0800
   4 Subject: [PATCH 031/122] dt-bindings: clock: Add StarFive JH7110 PLL clock
   5  generator
   6
   7 Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.
   8
   9 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  10 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
  11 ---
  12  .../bindings/clock/starfive,jh7110-pll.yaml   | 46 +++++++++++++++++++
  13  .../dt-bindings/clock/starfive,jh7110-crg.h   |  6 +++
  14  2 files changed, 52 insertions(+)
  15  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
  16
  17 --- /dev/null
  18 +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
  19 @@ -0,0 +1,46 @@
  20 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  21 +%YAML 1.2
  22 +---
  23 +$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
  24 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  25 +
  26 +title: StarFive JH7110 PLL Clock Generator
  27 +
  28 +description:
  29 +  This PLL are high speed, low jitter frequency synthesizers in JH7110.
  30 +  Each PLL clocks work in integer mode or fraction mode by some dividers,
  31 +  and the configuration registers and dividers are set in several syscon
  32 +  registers. So pll node should be a child of SYS-SYSCON node.
  33 +  The formula for calculating frequency is that,
  34 +  Fvco = Fref * (NI + NF) / M / Q1
  35 +
  36 +maintainers:
  37 +  - Xingyu Wu <xingyu.wu@starfivetech.com>
  38 +
  39 +properties:
  40 +  compatible:
  41 +    const: starfive,jh7110-pll
  42 +
  43 +  clocks:
  44 +    maxItems: 1
  45 +    description: Main Oscillator (24 MHz)
  46 +
  47 +  '#clock-cells':
  48 +    const: 1
  49 +    description:
  50 +      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
  51 +
  52 +required:
  53 +  - compatible
  54 +  - clocks
  55 +  - '#clock-cells'
  56 +
  57 +additionalProperties: false
  58 +
  59 +examples:
  60 +  - |
  61 +    pll-clock-controller {
  62 +      compatible = "starfive,jh7110-pll";
  63 +      clocks = <&osc>;
  64 +      #clock-cells = <1>;
  65 +    };
  66 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
  67 +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
  68 @@ -6,6 +6,12 @@
  69  #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
  70  #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
  71
  72 +/* PLL clocks */
  73 +#define JH7110_CLK_PLL0_OUT                    0
  74 +#define JH7110_CLK_PLL1_OUT                    1
  75 +#define JH7110_CLK_PLL2_OUT                    2
  76 +#define JH7110_PLLCLK_END                      3
  77 +
  78  /* SYSCRG clocks */
  79  #define JH7110_SYSCLK_CPU_ROOT                 0
  80  #define JH7110_SYSCLK_CPU_CORE                 1