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starfive: add new target for StarFive JH7100/7110 SoC
[openwrt/staging/981213.git] / target / linux / starfive / patches-6.1 / 0021-riscv-dts-starfive-Add-initial-StarFive-JH7110-devic.patch
1 From ca57ce82224c21f93ad43754474fb8de1baf5caa Mon Sep 17 00:00:00 2001
2 From: Emil Renner Berthing <kernel@esmil.dk>
3 Date: Sat, 1 Apr 2023 19:19:31 +0800
4 Subject: [PATCH 021/122] riscv: dts: starfive: Add initial StarFive JH7110
5 device tree
6
7 Add initial device tree for the JH7110 RISC-V SoC by StarFive
8 Technology Ltd.
9
10 Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
11 Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
12 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
13 Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
14 Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
15 Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
16 Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
17 [conor: squashed in the removal of the S7's non-existent mmu]
18 Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
19 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
20 ---
21 arch/riscv/Kconfig.socs | 5 +
22 arch/riscv/boot/dts/starfive/jh7110.dtsi | 500 +++++++++++++++++++++++
23 2 files changed, 505 insertions(+)
24 create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
25
26 --- a/arch/riscv/Kconfig.socs
27 +++ b/arch/riscv/Kconfig.socs
28 @@ -7,6 +7,8 @@ config SOC_MICROCHIP_POLARFIRE
29 help
30 This enables support for Microchip PolarFire SoC platforms.
31
32 +config ARCH_SIFIVE
33 + def_bool SOC_SIFIVE
34 config SOC_SIFIVE
35 bool "SiFive SoCs"
36 select SERIAL_SIFIVE if TTY
37 @@ -18,6 +20,9 @@ config SOC_SIFIVE
38 help
39 This enables support for SiFive SoC platform hardware.
40
41 +config ARCH_STARFIVE
42 + def_bool SOC_STARFIVE
43 +
44 config SOC_STARFIVE
45 bool "StarFive SoCs"
46 select PINCTRL
47 --- /dev/null
48 +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
49 @@ -0,0 +1,500 @@
50 +// SPDX-License-Identifier: GPL-2.0 OR MIT
51 +/*
52 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
53 + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
54 + */
55 +
56 +/dts-v1/;
57 +#include <dt-bindings/clock/starfive,jh7110-crg.h>
58 +#include <dt-bindings/reset/starfive,jh7110-crg.h>
59 +
60 +/ {
61 + compatible = "starfive,jh7110";
62 + #address-cells = <2>;
63 + #size-cells = <2>;
64 +
65 + cpus {
66 + #address-cells = <1>;
67 + #size-cells = <0>;
68 +
69 + S7_0: cpu@0 {
70 + compatible = "sifive,s7", "riscv";
71 + reg = <0>;
72 + device_type = "cpu";
73 + i-cache-block-size = <64>;
74 + i-cache-sets = <64>;
75 + i-cache-size = <16384>;
76 + next-level-cache = <&ccache>;
77 + riscv,isa = "rv64imac_zba_zbb";
78 + status = "disabled";
79 +
80 + cpu0_intc: interrupt-controller {
81 + compatible = "riscv,cpu-intc";
82 + interrupt-controller;
83 + #interrupt-cells = <1>;
84 + };
85 + };
86 +
87 + U74_1: cpu@1 {
88 + compatible = "sifive,u74-mc", "riscv";
89 + reg = <1>;
90 + d-cache-block-size = <64>;
91 + d-cache-sets = <64>;
92 + d-cache-size = <32768>;
93 + d-tlb-sets = <1>;
94 + d-tlb-size = <40>;
95 + device_type = "cpu";
96 + i-cache-block-size = <64>;
97 + i-cache-sets = <64>;
98 + i-cache-size = <32768>;
99 + i-tlb-sets = <1>;
100 + i-tlb-size = <40>;
101 + mmu-type = "riscv,sv39";
102 + next-level-cache = <&ccache>;
103 + riscv,isa = "rv64imafdc_zba_zbb";
104 + tlb-split;
105 +
106 + cpu1_intc: interrupt-controller {
107 + compatible = "riscv,cpu-intc";
108 + interrupt-controller;
109 + #interrupt-cells = <1>;
110 + };
111 + };
112 +
113 + U74_2: cpu@2 {
114 + compatible = "sifive,u74-mc", "riscv";
115 + reg = <2>;
116 + d-cache-block-size = <64>;
117 + d-cache-sets = <64>;
118 + d-cache-size = <32768>;
119 + d-tlb-sets = <1>;
120 + d-tlb-size = <40>;
121 + device_type = "cpu";
122 + i-cache-block-size = <64>;
123 + i-cache-sets = <64>;
124 + i-cache-size = <32768>;
125 + i-tlb-sets = <1>;
126 + i-tlb-size = <40>;
127 + mmu-type = "riscv,sv39";
128 + next-level-cache = <&ccache>;
129 + riscv,isa = "rv64imafdc_zba_zbb";
130 + tlb-split;
131 +
132 + cpu2_intc: interrupt-controller {
133 + compatible = "riscv,cpu-intc";
134 + interrupt-controller;
135 + #interrupt-cells = <1>;
136 + };
137 + };
138 +
139 + U74_3: cpu@3 {
140 + compatible = "sifive,u74-mc", "riscv";
141 + reg = <3>;
142 + d-cache-block-size = <64>;
143 + d-cache-sets = <64>;
144 + d-cache-size = <32768>;
145 + d-tlb-sets = <1>;
146 + d-tlb-size = <40>;
147 + device_type = "cpu";
148 + i-cache-block-size = <64>;
149 + i-cache-sets = <64>;
150 + i-cache-size = <32768>;
151 + i-tlb-sets = <1>;
152 + i-tlb-size = <40>;
153 + mmu-type = "riscv,sv39";
154 + next-level-cache = <&ccache>;
155 + riscv,isa = "rv64imafdc_zba_zbb";
156 + tlb-split;
157 +
158 + cpu3_intc: interrupt-controller {
159 + compatible = "riscv,cpu-intc";
160 + interrupt-controller;
161 + #interrupt-cells = <1>;
162 + };
163 + };
164 +
165 + U74_4: cpu@4 {
166 + compatible = "sifive,u74-mc", "riscv";
167 + reg = <4>;
168 + d-cache-block-size = <64>;
169 + d-cache-sets = <64>;
170 + d-cache-size = <32768>;
171 + d-tlb-sets = <1>;
172 + d-tlb-size = <40>;
173 + device_type = "cpu";
174 + i-cache-block-size = <64>;
175 + i-cache-sets = <64>;
176 + i-cache-size = <32768>;
177 + i-tlb-sets = <1>;
178 + i-tlb-size = <40>;
179 + mmu-type = "riscv,sv39";
180 + next-level-cache = <&ccache>;
181 + riscv,isa = "rv64imafdc_zba_zbb";
182 + tlb-split;
183 +
184 + cpu4_intc: interrupt-controller {
185 + compatible = "riscv,cpu-intc";
186 + interrupt-controller;
187 + #interrupt-cells = <1>;
188 + };
189 + };
190 +
191 + cpu-map {
192 + cluster0 {
193 + core0 {
194 + cpu = <&S7_0>;
195 + };
196 +
197 + core1 {
198 + cpu = <&U74_1>;
199 + };
200 +
201 + core2 {
202 + cpu = <&U74_2>;
203 + };
204 +
205 + core3 {
206 + cpu = <&U74_3>;
207 + };
208 +
209 + core4 {
210 + cpu = <&U74_4>;
211 + };
212 + };
213 + };
214 + };
215 +
216 + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
217 + compatible = "fixed-clock";
218 + clock-output-names = "gmac0_rgmii_rxin";
219 + #clock-cells = <0>;
220 + };
221 +
222 + gmac0_rmii_refin: gmac0-rmii-refin-clock {
223 + compatible = "fixed-clock";
224 + clock-output-names = "gmac0_rmii_refin";
225 + #clock-cells = <0>;
226 + };
227 +
228 + gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
229 + compatible = "fixed-clock";
230 + clock-output-names = "gmac1_rgmii_rxin";
231 + #clock-cells = <0>;
232 + };
233 +
234 + gmac1_rmii_refin: gmac1-rmii-refin-clock {
235 + compatible = "fixed-clock";
236 + clock-output-names = "gmac1_rmii_refin";
237 + #clock-cells = <0>;
238 + };
239 +
240 + i2srx_bclk_ext: i2srx-bclk-ext-clock {
241 + compatible = "fixed-clock";
242 + clock-output-names = "i2srx_bclk_ext";
243 + #clock-cells = <0>;
244 + };
245 +
246 + i2srx_lrck_ext: i2srx-lrck-ext-clock {
247 + compatible = "fixed-clock";
248 + clock-output-names = "i2srx_lrck_ext";
249 + #clock-cells = <0>;
250 + };
251 +
252 + i2stx_bclk_ext: i2stx-bclk-ext-clock {
253 + compatible = "fixed-clock";
254 + clock-output-names = "i2stx_bclk_ext";
255 + #clock-cells = <0>;
256 + };
257 +
258 + i2stx_lrck_ext: i2stx-lrck-ext-clock {
259 + compatible = "fixed-clock";
260 + clock-output-names = "i2stx_lrck_ext";
261 + #clock-cells = <0>;
262 + };
263 +
264 + mclk_ext: mclk-ext-clock {
265 + compatible = "fixed-clock";
266 + clock-output-names = "mclk_ext";
267 + #clock-cells = <0>;
268 + };
269 +
270 + osc: oscillator {
271 + compatible = "fixed-clock";
272 + clock-output-names = "osc";
273 + #clock-cells = <0>;
274 + };
275 +
276 + rtc_osc: rtc-oscillator {
277 + compatible = "fixed-clock";
278 + clock-output-names = "rtc_osc";
279 + #clock-cells = <0>;
280 + };
281 +
282 + tdm_ext: tdm-ext-clock {
283 + compatible = "fixed-clock";
284 + clock-output-names = "tdm_ext";
285 + #clock-cells = <0>;
286 + };
287 +
288 + soc {
289 + compatible = "simple-bus";
290 + interrupt-parent = <&plic>;
291 + #address-cells = <2>;
292 + #size-cells = <2>;
293 + ranges;
294 +
295 + clint: timer@2000000 {
296 + compatible = "starfive,jh7110-clint", "sifive,clint0";
297 + reg = <0x0 0x2000000 0x0 0x10000>;
298 + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
299 + <&cpu1_intc 3>, <&cpu1_intc 7>,
300 + <&cpu2_intc 3>, <&cpu2_intc 7>,
301 + <&cpu3_intc 3>, <&cpu3_intc 7>,
302 + <&cpu4_intc 3>, <&cpu4_intc 7>;
303 + };
304 +
305 + ccache: cache-controller@2010000 {
306 + compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
307 + reg = <0x0 0x2010000 0x0 0x4000>;
308 + interrupts = <1>, <3>, <4>, <2>;
309 + cache-block-size = <64>;
310 + cache-level = <2>;
311 + cache-sets = <2048>;
312 + cache-size = <2097152>;
313 + cache-unified;
314 + };
315 +
316 + plic: interrupt-controller@c000000 {
317 + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
318 + reg = <0x0 0xc000000 0x0 0x4000000>;
319 + interrupts-extended = <&cpu0_intc 11>,
320 + <&cpu1_intc 11>, <&cpu1_intc 9>,
321 + <&cpu2_intc 11>, <&cpu2_intc 9>,
322 + <&cpu3_intc 11>, <&cpu3_intc 9>,
323 + <&cpu4_intc 11>, <&cpu4_intc 9>;
324 + interrupt-controller;
325 + #interrupt-cells = <1>;
326 + #address-cells = <0>;
327 + riscv,ndev = <136>;
328 + };
329 +
330 + uart0: serial@10000000 {
331 + compatible = "snps,dw-apb-uart";
332 + reg = <0x0 0x10000000 0x0 0x10000>;
333 + clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
334 + <&syscrg JH7110_SYSCLK_UART0_APB>;
335 + clock-names = "baudclk", "apb_pclk";
336 + resets = <&syscrg JH7110_SYSRST_UART0_APB>;
337 + interrupts = <32>;
338 + reg-io-width = <4>;
339 + reg-shift = <2>;
340 + status = "disabled";
341 + };
342 +
343 + uart1: serial@10010000 {
344 + compatible = "snps,dw-apb-uart";
345 + reg = <0x0 0x10010000 0x0 0x10000>;
346 + clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
347 + <&syscrg JH7110_SYSCLK_UART1_APB>;
348 + clock-names = "baudclk", "apb_pclk";
349 + resets = <&syscrg JH7110_SYSRST_UART1_APB>;
350 + interrupts = <33>;
351 + reg-io-width = <4>;
352 + reg-shift = <2>;
353 + status = "disabled";
354 + };
355 +
356 + uart2: serial@10020000 {
357 + compatible = "snps,dw-apb-uart";
358 + reg = <0x0 0x10020000 0x0 0x10000>;
359 + clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
360 + <&syscrg JH7110_SYSCLK_UART2_APB>;
361 + clock-names = "baudclk", "apb_pclk";
362 + resets = <&syscrg JH7110_SYSRST_UART2_APB>;
363 + interrupts = <34>;
364 + reg-io-width = <4>;
365 + reg-shift = <2>;
366 + status = "disabled";
367 + };
368 +
369 + i2c0: i2c@10030000 {
370 + compatible = "snps,designware-i2c";
371 + reg = <0x0 0x10030000 0x0 0x10000>;
372 + clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
373 + clock-names = "ref";
374 + resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
375 + interrupts = <35>;
376 + #address-cells = <1>;
377 + #size-cells = <0>;
378 + status = "disabled";
379 + };
380 +
381 + i2c1: i2c@10040000 {
382 + compatible = "snps,designware-i2c";
383 + reg = <0x0 0x10040000 0x0 0x10000>;
384 + clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
385 + clock-names = "ref";
386 + resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
387 + interrupts = <36>;
388 + #address-cells = <1>;
389 + #size-cells = <0>;
390 + status = "disabled";
391 + };
392 +
393 + i2c2: i2c@10050000 {
394 + compatible = "snps,designware-i2c";
395 + reg = <0x0 0x10050000 0x0 0x10000>;
396 + clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
397 + clock-names = "ref";
398 + resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
399 + interrupts = <37>;
400 + #address-cells = <1>;
401 + #size-cells = <0>;
402 + status = "disabled";
403 + };
404 +
405 + uart3: serial@12000000 {
406 + compatible = "snps,dw-apb-uart";
407 + reg = <0x0 0x12000000 0x0 0x10000>;
408 + clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
409 + <&syscrg JH7110_SYSCLK_UART3_APB>;
410 + clock-names = "baudclk", "apb_pclk";
411 + resets = <&syscrg JH7110_SYSRST_UART3_APB>;
412 + interrupts = <45>;
413 + reg-io-width = <4>;
414 + reg-shift = <2>;
415 + status = "disabled";
416 + };
417 +
418 + uart4: serial@12010000 {
419 + compatible = "snps,dw-apb-uart";
420 + reg = <0x0 0x12010000 0x0 0x10000>;
421 + clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
422 + <&syscrg JH7110_SYSCLK_UART4_APB>;
423 + clock-names = "baudclk", "apb_pclk";
424 + resets = <&syscrg JH7110_SYSRST_UART4_APB>;
425 + interrupts = <46>;
426 + reg-io-width = <4>;
427 + reg-shift = <2>;
428 + status = "disabled";
429 + };
430 +
431 + uart5: serial@12020000 {
432 + compatible = "snps,dw-apb-uart";
433 + reg = <0x0 0x12020000 0x0 0x10000>;
434 + clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
435 + <&syscrg JH7110_SYSCLK_UART5_APB>;
436 + clock-names = "baudclk", "apb_pclk";
437 + resets = <&syscrg JH7110_SYSRST_UART5_APB>;
438 + interrupts = <47>;
439 + reg-io-width = <4>;
440 + reg-shift = <2>;
441 + status = "disabled";
442 + };
443 +
444 + i2c3: i2c@12030000 {
445 + compatible = "snps,designware-i2c";
446 + reg = <0x0 0x12030000 0x0 0x10000>;
447 + clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
448 + clock-names = "ref";
449 + resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
450 + interrupts = <48>;
451 + #address-cells = <1>;
452 + #size-cells = <0>;
453 + status = "disabled";
454 + };
455 +
456 + i2c4: i2c@12040000 {
457 + compatible = "snps,designware-i2c";
458 + reg = <0x0 0x12040000 0x0 0x10000>;
459 + clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
460 + clock-names = "ref";
461 + resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
462 + interrupts = <49>;
463 + #address-cells = <1>;
464 + #size-cells = <0>;
465 + status = "disabled";
466 + };
467 +
468 + i2c5: i2c@12050000 {
469 + compatible = "snps,designware-i2c";
470 + reg = <0x0 0x12050000 0x0 0x10000>;
471 + clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
472 + clock-names = "ref";
473 + resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
474 + interrupts = <50>;
475 + #address-cells = <1>;
476 + #size-cells = <0>;
477 + status = "disabled";
478 + };
479 +
480 + i2c6: i2c@12060000 {
481 + compatible = "snps,designware-i2c";
482 + reg = <0x0 0x12060000 0x0 0x10000>;
483 + clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
484 + clock-names = "ref";
485 + resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
486 + interrupts = <51>;
487 + #address-cells = <1>;
488 + #size-cells = <0>;
489 + status = "disabled";
490 + };
491 +
492 + syscrg: clock-controller@13020000 {
493 + compatible = "starfive,jh7110-syscrg";
494 + reg = <0x0 0x13020000 0x0 0x10000>;
495 + clocks = <&osc>, <&gmac1_rmii_refin>,
496 + <&gmac1_rgmii_rxin>,
497 + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
498 + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
499 + <&tdm_ext>, <&mclk_ext>;
500 + clock-names = "osc", "gmac1_rmii_refin",
501 + "gmac1_rgmii_rxin",
502 + "i2stx_bclk_ext", "i2stx_lrck_ext",
503 + "i2srx_bclk_ext", "i2srx_lrck_ext",
504 + "tdm_ext", "mclk_ext";
505 + #clock-cells = <1>;
506 + #reset-cells = <1>;
507 + };
508 +
509 + sysgpio: pinctrl@13040000 {
510 + compatible = "starfive,jh7110-sys-pinctrl";
511 + reg = <0x0 0x13040000 0x0 0x10000>;
512 + clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
513 + resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
514 + interrupts = <86>;
515 + interrupt-controller;
516 + #interrupt-cells = <2>;
517 + gpio-controller;
518 + #gpio-cells = <2>;
519 + };
520 +
521 + aoncrg: clock-controller@17000000 {
522 + compatible = "starfive,jh7110-aoncrg";
523 + reg = <0x0 0x17000000 0x0 0x10000>;
524 + clocks = <&osc>, <&gmac0_rmii_refin>,
525 + <&gmac0_rgmii_rxin>,
526 + <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
527 + <&syscrg JH7110_SYSCLK_APB_BUS>,
528 + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
529 + <&rtc_osc>;
530 + clock-names = "osc", "gmac0_rmii_refin",
531 + "gmac0_rgmii_rxin", "stg_axiahb",
532 + "apb_bus", "gmac0_gtxclk",
533 + "rtc_osc";
534 + #clock-cells = <1>;
535 + #reset-cells = <1>;
536 + };
537 +
538 + aongpio: pinctrl@17020000 {
539 + compatible = "starfive,jh7110-aon-pinctrl";
540 + reg = <0x0 0x17020000 0x0 0x10000>;
541 + resets = <&aoncrg JH7110_AONRST_IOMUX>;
542 + interrupts = <85>;
543 + interrupt-controller;
544 + #interrupt-cells = <2>;
545 + gpio-controller;
546 + #gpio-cells = <2>;
547 + };
548 + };
549 +};
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