target/linux/qualcommax/patches-6.1/0059-v6.9-arm64-dts-qcom-ipq6018-add-thermal-zones.patch

   1 From 8f053e5616352943e16966f195f5a7a161e6fe7d Mon Sep 17 00:00:00 2001
   2 From: Mantas Pucka <mantas@8devices.com>
   3 Date: Thu, 25 Jan 2024 11:04:12 +0200
   4 Subject: [PATCH] arm64: dts: qcom: ipq6018: add thermal zones
   5
   6 Add thermal zones to make use of thermal sensors data. For CPU zone,
   7 add cooling device that uses CPU frequency scaling.
   8
   9 Signed-off-by: Mantas Pucka <mantas@8devices.com>
  10 Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com
  11 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  12 ---
  13  arch/arm64/boot/dts/qcom/ipq6018.dtsi | 121 ++++++++++++++++++++++++++
  14  1 file changed, 121 insertions(+)
  15
  16 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  17 +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
  18 @@ -9,6 +9,7 @@
  19  #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
  20  #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
  21  #include <dt-bindings/clock/qcom,apss-ipq.h>
  22 +#include <dt-bindings/thermal/thermal.h>
  23
  24  / {
  25         #address-cells = <2>;
  26 @@ -43,6 +44,7 @@
  27                         clock-names = "cpu";
  28                         operating-points-v2 = <&cpu_opp_table>;
  29                         cpu-supply = <&ipq6018_s2>;
  30 +                       #cooling-cells = <2>;
  31                 };
  32
  33                 CPU1: cpu@1 {
  34 @@ -55,6 +57,7 @@
  35                         clock-names = "cpu";
  36                         operating-points-v2 = <&cpu_opp_table>;
  37                         cpu-supply = <&ipq6018_s2>;
  38 +                       #cooling-cells = <2>;
  39                 };
  40
  41                 CPU2: cpu@2 {
  42 @@ -67,6 +70,7 @@
  43                         clock-names = "cpu";
  44                         operating-points-v2 = <&cpu_opp_table>;
  45                         cpu-supply = <&ipq6018_s2>;
  46 +                       #cooling-cells = <2>;
  47                 };
  48
  49                 CPU3: cpu@3 {
  50 @@ -79,6 +83,7 @@
  51                         clock-names = "cpu";
  52                         operating-points-v2 = <&cpu_opp_table>;
  53                         cpu-supply = <&ipq6018_s2>;
  54 +                       #cooling-cells = <2>;
  55                 };
  56
  57                 L2_0: l2-cache {
  58 @@ -888,6 +893,122 @@
  59                 };
  60         };
  61
  62 +       thermal-zones {
  63 +               nss-top-thermal {
  64 +                       polling-delay-passive = <250>;
  65 +                       polling-delay = <1000>;
  66 +                       thermal-sensors = <&tsens 4>;
  67 +
  68 +                       trips {
  69 +                               nss-top-critical {
  70 +                                       temperature = <125000>;
  71 +                                       hysteresis = <1000>;
  72 +                                       type = "critical";
  73 +                               };
  74 +                       };
  75 +               };
  76 +
  77 +               nss-thermal {
  78 +                       polling-delay-passive = <250>;
  79 +                       polling-delay = <1000>;
  80 +                       thermal-sensors = <&tsens 5>;
  81 +
  82 +                       trips {
  83 +                               nss-critical {
  84 +                                       temperature = <125000>;
  85 +                                       hysteresis = <1000>;
  86 +                                       type = "critical";
  87 +                               };
  88 +                       };
  89 +               };
  90 +
  91 +               wcss-phya0-thermal {
  92 +                       polling-delay-passive = <250>;
  93 +                       polling-delay = <1000>;
  94 +                       thermal-sensors = <&tsens 7>;
  95 +
  96 +                       trips {
  97 +                               wcss-phya0-critical {
  98 +                                       temperature = <125000>;
  99 +                                       hysteresis = <1000>;
 100 +                                       type = "critical";
 101 +                               };
 102 +                       };
 103 +               };
 104 +
 105 +               wcss-phya1-thermal {
 106 +                       polling-delay-passive = <250>;
 107 +                       polling-delay = <1000>;
 108 +                       thermal-sensors = <&tsens 8>;
 109 +
 110 +                       trips {
 111 +                               wcss-phya1-critical {
 112 +                                       temperature = <125000>;
 113 +                                       hysteresis = <1000>;
 114 +                                       type = "critical";
 115 +                               };
 116 +                       };
 117 +               };
 118 +
 119 +               cpu-thermal {
 120 +                       polling-delay-passive = <250>;
 121 +                       polling-delay = <1000>;
 122 +                       thermal-sensors = <&tsens 13>;
 123 +
 124 +                       trips {
 125 +                               cpu-critical {
 126 +                                       temperature = <125000>;
 127 +                                       hysteresis = <1000>;
 128 +                                       type = "critical";
 129 +                               };
 130 +
 131 +                               cpu_alert: cpu-passive {
 132 +                                       temperature = <110000>;
 133 +                                       hysteresis = <1000>;
 134 +                                       type = "passive";
 135 +                               };
 136 +                       };
 137 +
 138 +                       cooling-maps {
 139 +                               map0 {
 140 +                                       trip = <&cpu_alert>;
 141 +                                       cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 142 +                                                        <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 143 +                                                        <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 144 +                                                        <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 145 +                               };
 146 +                       };
 147 +               };
 148 +
 149 +               lpass-thermal {
 150 +                       polling-delay-passive = <250>;
 151 +                       polling-delay = <1000>;
 152 +                       thermal-sensors = <&tsens 14>;
 153 +
 154 +                       trips {
 155 +                               lpass-critical {
 156 +                                       temperature = <125000>;
 157 +                                       hysteresis = <1000>;
 158 +                                       type = "critical";
 159 +                               };
 160 +                       };
 161 +               };
 162 +
 163 +               ddrss-top-thermal {
 164 +                       polling-delay-passive = <250>;
 165 +                       polling-delay = <1000>;
 166 +                       thermal-sensors = <&tsens 15>;
 167 +
 168 +                       trips {
 169 +                               ddrss-top-critical {
 170 +                                       temperature = <125000>;
 171 +                                       hysteresis = <1000>;
 172 +                                       type = "critical";
 173 +                               };
 174 +                       };
 175 +               };
 176 +       };
 177 +
 178         timer {
 179                 compatible = "arm,armv8-timer";
 180                 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,