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mediatek: backport a hell of thermal commits
[openwrt/staging/wigyori.git] / target / linux / mediatek / files-6.1 / arch / arm64 / boot / dts / mediatek / mt7988a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/reset/ti-syscon.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 compatible = "mediatek,mt7988";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 cci: cci {
23 compatible = "mediatek,mt7988-cci",
24 "mediatek,mt8183-cci";
25 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
26 <&topckgen CLK_TOP_XTAL>;
27 clock-names = "cci", "intermediate";
28 operating-points-v2 = <&cci_opp>;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu0: cpu@0 {
36 compatible = "arm,cortex-a73";
37 reg = <0x0>;
38 device_type = "cpu";
39 enable-method = "psci";
40 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
41 <&topckgen CLK_TOP_XTAL>;
42 clock-names = "cpu", "intermediate";
43 operating-points-v2 = <&cluster0_opp>;
44 mediatek,cci = <&cci>;
45 };
46
47 cpu1: cpu@1 {
48 compatible = "arm,cortex-a73";
49 reg = <0x1>;
50 device_type = "cpu";
51 enable-method = "psci";
52 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
53 <&topckgen CLK_TOP_XTAL>;
54 clock-names = "cpu", "intermediate";
55 operating-points-v2 = <&cluster0_opp>;
56 mediatek,cci = <&cci>;
57 };
58
59 cpu2: cpu@2 {
60 compatible = "arm,cortex-a73";
61 reg = <0x2>;
62 device_type = "cpu";
63 enable-method = "psci";
64 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
65 <&topckgen CLK_TOP_XTAL>;
66 clock-names = "cpu", "intermediate";
67 operating-points-v2 = <&cluster0_opp>;
68 mediatek,cci = <&cci>;
69 };
70
71 cpu3: cpu@3 {
72 compatible = "arm,cortex-a73";
73 reg = <0x3>;
74 device_type = "cpu";
75 enable-method = "psci";
76 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
77 <&topckgen CLK_TOP_XTAL>;
78 clock-names = "cpu", "intermediate";
79 operating-points-v2 = <&cluster0_opp>;
80 mediatek,cci = <&cci>;
81 };
82
83 cluster0_opp: opp_table0 {
84 compatible = "operating-points-v2";
85 opp-shared;
86
87 opp00 {
88 opp-hz = /bits/ 64 <800000000>;
89 opp-microvolt = <850000>;
90 };
91
92 opp01 {
93 opp-hz = /bits/ 64 <1100000000>;
94 opp-microvolt = <850000>;
95 };
96
97 opp02 {
98 opp-hz = /bits/ 64 <1500000000>;
99 opp-microvolt = <850000>;
100 };
101
102 opp03 {
103 opp-hz = /bits/ 64 <1800000000>;
104 opp-microvolt = <900000>;
105 };
106 };
107 };
108
109 cci_opp: opp_table_cci {
110 compatible = "operating-points-v2";
111 opp-shared;
112
113 opp00 {
114 opp-hz = /bits/ 64 <480000000>;
115 opp-microvolt = <850000>;
116 };
117
118 opp01 {
119 opp-hz = /bits/ 64 <660000000>;
120 opp-microvolt = <850000>;
121 };
122
123 opp02 {
124 opp-hz = /bits/ 64 <900000000>;
125 opp-microvolt = <850000>;
126 };
127
128 opp03 {
129 opp-hz = /bits/ 64 <1080000000>;
130 opp-microvolt = <900000>;
131 };
132 };
133
134 clk40m: oscillator@0 {
135 compatible = "fixed-clock";
136 clock-frequency = <40000000>;
137 #clock-cells = <0>;
138 clock-output-names = "clkxtal";
139 };
140
141 fan: pwm-fan {
142 compatible = "pwm-fan";
143 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
144 cooling-levels = <0 128 255>;
145 #cooling-cells = <2>;
146 #thermal-sensor-cells = <1>;
147 status = "disabled";
148 };
149
150 pmu {
151 compatible = "arm,cortex-a73-pmu";
152 interrupt-parent = <&gic>;
153 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
154 };
155
156 psci {
157 compatible = "arm,psci-0.2";
158 method = "smc";
159 };
160
161 reg_1p8v: regulator-1p8v {
162 compatible = "regulator-fixed";
163 regulator-name = "fixed-1.8V";
164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <1800000>;
166 regulator-boot-on;
167 regulator-always-on;
168 };
169
170 reg_3p3v: regulator-3p3v {
171 compatible = "regulator-fixed";
172 regulator-name = "fixed-3.3V";
173 regulator-min-microvolt = <3300000>;
174 regulator-max-microvolt = <3300000>;
175 regulator-boot-on;
176 regulator-always-on;
177 };
178
179 reserved-memory {
180 ranges;
181 #address-cells = <2>;
182 #size-cells = <2>;
183
184 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
185 secmon_reserved: secmon@43000000 {
186 reg = <0 0x43000000 0 0x50000>;
187 no-map;
188 };
189 };
190
191 soc {
192 compatible = "simple-bus";
193 ranges;
194 #address-cells = <2>;
195 #size-cells = <2>;
196
197 gic: interrupt-controller@c000000 {
198 compatible = "arm,gic-v3";
199 reg = <0 0x0c000000 0 0x40000>, /* GICD */
200 <0 0x0c080000 0 0x200000>, /* GICR */
201 <0 0x0c400000 0 0x2000>, /* GICC */
202 <0 0x0c410000 0 0x1000>, /* GICH */
203 <0 0x0c420000 0 0x2000>; /* GICV */
204 interrupt-parent = <&gic>;
205 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
206 interrupt-controller;
207 #interrupt-cells = <3>;
208 };
209
210 phyfw: phy-firmware@f000000 {
211 compatible = "mediatek,2p5gphy-fw";
212 reg = <0 0x0f000000 0 0x8000>,
213 <0 0x0f100000 0 0x20000>,
214 <0 0x0f0f0000 0 0x200>;
215 };
216
217 infracfg: infracfg@10001000 {
218 compatible = "mediatek,mt7988-infracfg", "syscon";
219 reg = <0 0x10001000 0 0x1000>;
220 #clock-cells = <1>;
221 };
222
223 topckgen: topckgen@1001b000 {
224 compatible = "mediatek,mt7988-topckgen", "syscon";
225 reg = <0 0x1001b000 0 0x1000>;
226 #clock-cells = <1>;
227 };
228
229 watchdog: watchdog@1001c000 {
230 compatible = "mediatek,mt7988-wdt",
231 "mediatek,mt6589-wdt",
232 "syscon";
233 reg = <0 0x1001c000 0 0x1000>;
234 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
235 #reset-cells = <1>;
236 };
237
238 apmixedsys: apmixedsys@1001e000 {
239 compatible = "mediatek,mt7988-apmixedsys";
240 reg = <0 0x1001e000 0 0x1000>;
241 #clock-cells = <1>;
242 };
243
244 pio: pinctrl@1001f000 {
245 compatible = "mediatek,mt7988-pinctrl", "syscon";
246 reg = <0 0x1001f000 0 0x1000>,
247 <0 0x11c10000 0 0x1000>,
248 <0 0x11d00000 0 0x1000>,
249 <0 0x11d20000 0 0x1000>,
250 <0 0x11e00000 0 0x1000>,
251 <0 0x11f00000 0 0x1000>,
252 <0 0x1000b000 0 0x1000>;
253 reg-names = "gpio_base", "iocfg_tr_base",
254 "iocfg_br_base", "iocfg_rb_base",
255 "iocfg_lb_base", "iocfg_tl_base", "eint";
256 gpio-controller;
257 #gpio-cells = <2>;
258 gpio-ranges = <&pio 0 0 84>;
259 interrupt-controller;
260 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
261 interrupt-parent = <&gic>;
262 #interrupt-cells = <2>;
263
264 mdio0_pins: mdio0-pins {
265 mux {
266 function = "eth";
267 groups = "mdc_mdio0";
268 };
269
270 conf {
271 groups = "mdc_mdio0";
272 drive-strength = <MTK_DRIVE_8mA>;
273 };
274 };
275
276 i2c0_pins: i2c0-pins-g0 {
277 mux {
278 function = "i2c";
279 groups = "i2c0_1";
280 };
281 };
282
283 i2c1_pins: i2c1-pins-g0 {
284 mux {
285 function = "i2c";
286 groups = "i2c1_0";
287 };
288 };
289
290 i2c1_sfp_pins: i2c1-sfp-pins-g0 {
291 mux {
292 function = "i2c";
293 groups = "i2c1_sfp";
294 };
295 };
296
297 i2c2_pins: i2c2-pins {
298 mux {
299 function = "i2c";
300 groups = "i2c2";
301 };
302 };
303
304 i2c2_0_pins: i2c2-pins-g0 {
305 mux {
306 function = "i2c";
307 groups = "i2c2_0";
308 };
309 };
310
311 i2c2_1_pins: i2c2-pins-g1 {
312 mux {
313 function = "i2c";
314 groups = "i2c2_1";
315 };
316 };
317
318 gbe0_led0_pins: gbe0-led0-pins {
319 mux {
320 function = "led";
321 groups = "gbe0_led0";
322 };
323 };
324
325 gbe1_led0_pins: gbe1-led0-pins {
326 mux {
327 function = "led";
328 groups = "gbe1_led0";
329 };
330 };
331
332 gbe2_led0_pins: gbe2-led0-pins {
333 mux {
334 function = "led";
335 groups = "gbe2_led0";
336 };
337 };
338
339 gbe3_led0_pins: gbe3-led0-pins {
340 mux {
341 function = "led";
342 groups = "gbe3_led0";
343 };
344 };
345
346 gbe0_led1_pins: gbe0-led1-pins {
347 mux {
348 function = "led";
349 groups = "gbe0_led1";
350 };
351 };
352
353 gbe1_led1_pins: gbe1-led1-pins {
354 mux {
355 function = "led";
356 groups = "gbe1_led1";
357 };
358 };
359
360 gbe2_led1_pins: gbe2-led1-pins {
361 mux {
362 function = "led";
363 groups = "gbe2_led1";
364 };
365 };
366
367 gbe3_led1_pins: gbe3-led1-pins {
368 mux {
369 function = "led";
370 groups = "gbe3_led1";
371 };
372 };
373
374 i2p5gbe_led0_pins: 2p5gbe-led0-pins {
375 mux {
376 function = "led";
377 groups = "2p5gbe_led0";
378 };
379 };
380
381 i2p5gbe_led1_pins: 2p5gbe-led1-pins {
382 mux {
383 function = "led";
384 groups = "2p5gbe_led1";
385 };
386 };
387
388 mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
389 mux {
390 function = "flash";
391 groups = "emmc_45";
392 };
393 };
394
395 mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
396 mux {
397 function = "flash";
398 groups = "emmc_51";
399 };
400 };
401
402 mmc0_pins_sdcard: mmc0-pins-sdcard {
403 mux {
404 function = "flash";
405 groups = "sdcard";
406 };
407 };
408
409 uart0_pins: uart0-pins {
410 mux {
411 function = "uart";
412 groups = "uart0";
413 };
414 };
415
416 snfi_pins: snfi-pins {
417 mux {
418 function = "flash";
419 groups = "snfi";
420 };
421 };
422
423 spi0_pins: spi0-pins {
424 mux {
425 function = "spi";
426 groups = "spi0";
427 };
428 };
429
430 spi0_flash_pins: spi0-flash-pins {
431 mux {
432 function = "spi";
433 groups = "spi0", "spi0_wp_hold";
434 };
435 };
436
437 spi1_pins: spi1-pins {
438 mux {
439 function = "spi";
440 groups = "spi1";
441 };
442 };
443
444 spi2_pins: spi2-pins {
445 mux {
446 function = "spi";
447 groups = "spi2";
448 };
449 };
450
451 spi2_flash_pins: spi2-flash-pins {
452 mux {
453 function = "spi";
454 groups = "spi2", "spi2_wp_hold";
455 };
456 };
457
458 pcie0_pins: pcie0-pins {
459 mux {
460 function = "pcie";
461 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
462 "pcie_wake_n0_0";
463 };
464 };
465
466 pcie1_pins: pcie1-pins {
467 mux {
468 function = "pcie";
469 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
470 "pcie_wake_n1_0";
471 };
472 };
473
474 pcie2_pins: pcie2-pins {
475 mux {
476 function = "pcie";
477 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
478 "pcie_wake_n2_0";
479 };
480 };
481
482 pcie3_pins: pcie3-pins {
483 mux {
484 function = "pcie";
485 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
486 "pcie_wake_n3_0";
487 };
488 };
489 };
490
491 pwm: pwm@10048000 {
492 compatible = "mediatek,mt7988-pwm";
493 reg = <0 0x10048000 0 0x1000>;
494 #pwm-cells = <2>;
495 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
496 <&infracfg CLK_INFRA_66M_PWM_HCK>,
497 <&infracfg CLK_INFRA_66M_PWM_CK1>,
498 <&infracfg CLK_INFRA_66M_PWM_CK2>,
499 <&infracfg CLK_INFRA_66M_PWM_CK3>,
500 <&infracfg CLK_INFRA_66M_PWM_CK4>,
501 <&infracfg CLK_INFRA_66M_PWM_CK5>,
502 <&infracfg CLK_INFRA_66M_PWM_CK6>,
503 <&infracfg CLK_INFRA_66M_PWM_CK7>,
504 <&infracfg CLK_INFRA_66M_PWM_CK8>;
505 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
506 "pwm4","pwm5","pwm6","pwm7","pwm8";
507 status = "disabled";
508 };
509
510 sgmiisys0: syscon@10060000 {
511 compatible = "mediatek,mt7988-sgmiisys",
512 "mediatek,mt7988-sgmiisys_0",
513 "syscon";
514 reg = <0 0x10060000 0 0x1000>;
515 #clock-cells = <1>;
516 };
517
518 sgmiisys1: syscon@10070000 {
519 compatible = "mediatek,mt7988-sgmiisys",
520 "mediatek,mt7988-sgmiisys_1",
521 "syscon";
522 reg = <0 0x10070000 0 0x1000>;
523 #clock-cells = <1>;
524 };
525
526 usxgmiisys0: usxgmiisys@10080000 {
527 compatible = "mediatek,mt7988-usxgmiisys",
528 "mediatek,mt7988-usxgmiisys_0",
529 "syscon";
530 reg = <0 0x10080000 0 0x1000>;
531 #clock-cells = <1>;
532 };
533
534 usxgmiisys1: usxgmiisys@10081000 {
535 compatible = "mediatek,mt7988-usxgmiisys",
536 "mediatek,mt7988-usxgmiisys_1",
537 "syscon";
538 reg = <0 0x10081000 0 0x1000>;
539 #clock-cells = <1>;
540 };
541
542 mcusys: mcusys@100e0000 {
543 compatible = "mediatek,mt7988-mcusys", "syscon";
544 reg = <0 0x100e0000 0 0x1000>;
545 #clock-cells = <1>;
546 };
547
548 uart0: serial@11000000 {
549 compatible = "mediatek,mt7986-uart",
550 "mediatek,mt6577-uart";
551 reg = <0 0x11000000 0 0x100>;
552 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
553 /*
554 * 8250-mtk driver don't control "baud" clock since commit
555 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
556 * still need to be passed to the driver to prevent probe fail
557 */
558 clocks = <&topckgen CLK_TOP_UART_SEL>,
559 <&infracfg CLK_INFRA_52M_UART0_CK>;
560 clock-names = "baud", "bus";
561 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
562 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
563 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
564 <&topckgen CLK_TOP_UART_SEL>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&uart0_pins>;
567 status = "disabled";
568 };
569
570 snand: spi@11001000 {
571 compatible = "mediatek,mt7986-snand";
572 reg = <0 0x11001000 0 0x1000>;
573 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&infracfg CLK_INFRA_SPINFI>,
575 <&infracfg CLK_INFRA_NFI>;
576 clock-names = "pad_clk", "nfi_clk";
577 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
578 <&topckgen CLK_TOP_NFI1X_SEL>;
579 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
580 <&topckgen CLK_TOP_MPLL_D8>;
581 nand-ecc-engine = <&bch>;
582 mediatek,quad-spi;
583 #address-cells = <1>;
584 #size-cells = <0>;
585 pinctrl-names = "default";
586 pinctrl-0 = <&snfi_pins>;
587 status = "disabled";
588 };
589
590 bch: ecc@11002000 {
591 compatible = "mediatek,mt7686-ecc";
592 reg = <0 0x11002000 0 0x1000>;
593 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
595 clock-names = "nfiecc_clk";
596 status = "disabled";
597 };
598
599 i2c0: i2c@11003000 {
600 compatible = "mediatek,mt7988-i2c",
601 "mediatek,mt7981-i2c";
602 reg = <0 0x11003000 0 0x1000>,
603 <0 0x10217080 0 0x80>;
604 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
605 clock-div = <1>;
606 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
607 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
608 clock-names = "main", "dma";
609 #address-cells = <1>;
610 #size-cells = <0>;
611 status = "disabled";
612 };
613
614 i2c1: i2c@11004000 {
615 compatible = "mediatek,mt7988-i2c",
616 "mediatek,mt7981-i2c";
617 reg = <0 0x11004000 0 0x1000>,
618 <0 0x10217100 0 0x80>;
619 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
620 clock-div = <1>;
621 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
622 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
623 clock-names = "main", "dma";
624 #address-cells = <1>;
625 #size-cells = <0>;
626 status = "disabled";
627 };
628
629 i2c2: i2c@11005000 {
630 compatible = "mediatek,mt7988-i2c",
631 "mediatek,mt7981-i2c";
632 reg = <0 0x11005000 0 0x1000>,
633 <0 0x10217180 0 0x80>;
634 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
635 clock-div = <1>;
636 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
637 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
638 clock-names = "main", "dma";
639 #address-cells = <1>;
640 #size-cells = <0>;
641 status = "disabled";
642 };
643
644 spi0: spi@11007000 {
645 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
646 reg = <0 0x11007000 0 0x100>;
647 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&topckgen CLK_TOP_MPLL_D2>,
649 <&topckgen CLK_TOP_SPI_SEL>,
650 <&infracfg CLK_INFRA_104M_SPI0>,
651 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
652 clock-names = "parent-clk", "sel-clk", "spi-clk",
653 "spi-hclk";
654 #address-cells = <1>;
655 #size-cells = <0>;
656 status = "disabled";
657 };
658
659 spi1: spi@11008000 {
660 compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
661 reg = <0 0x11008000 0 0x100>;
662 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&topckgen CLK_TOP_MPLL_D2>,
664 <&topckgen CLK_TOP_SPI_SEL>,
665 <&infracfg CLK_INFRA_104M_SPI1>,
666 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
667 clock-names = "parent-clk", "sel-clk", "spi-clk",
668 "spi-hclk";
669 #address-cells = <1>;
670 #size-cells = <0>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&spi1_pins>;
673 status = "disabled";
674 };
675
676 spi2: spi@11009000 {
677 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
678 reg = <0 0x11009000 0 0x100>;
679 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&topckgen CLK_TOP_MPLL_D2>,
681 <&topckgen CLK_TOP_SPI_SEL>,
682 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
683 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
684 clock-names = "parent-clk", "sel-clk", "spi-clk",
685 "spi-hclk";
686 #address-cells = <1>;
687 #size-cells = <0>;
688 status = "disabled";
689 };
690
691 lvts: lvts@1100a000 {
692 compatible = "mediatek,mt7988-lvts-ap";
693 reg = <0 0x1100a000 0 0x1000>;
694 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
695 clock-names = "lvts_clk";
696 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
697 resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>;
698 nvmem-cells = <&lvts_calibration>;
699 nvmem-cell-names = "lvts-calib-data-1";
700 #thermal-sensor-cells = <1>;
701 };
702
703 ssusb0: usb@11190000 {
704 compatible = "mediatek,mt7988-xhci",
705 "mediatek,mtk-xhci";
706 reg = <0 0x11190000 0 0x2e00>,
707 <0 0x11193e00 0 0x0100>;
708 reg-names = "mac", "ippc";
709 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
710 phys = <&xphyu2port0 PHY_TYPE_USB2>,
711 <&xphyu3port0 PHY_TYPE_USB3>;
712 clocks = <&infracfg CLK_INFRA_USB_SYS>,
713 <&infracfg CLK_INFRA_USB_XHCI>,
714 <&infracfg CLK_INFRA_USB_REF>,
715 <&infracfg CLK_INFRA_66M_USB_HCK>,
716 <&infracfg CLK_INFRA_133M_USB_HCK>;
717 clock-names = "sys_ck",
718 "xhci_ck",
719 "ref_ck",
720 "mcu_ck",
721 "dma_ck";
722 #address-cells = <2>;
723 #size-cells = <2>;
724 mediatek,p0_speed_fixup;
725 status = "disabled";
726 };
727
728 ssusb1: usb@11200000 {
729 compatible = "mediatek,mt7988-xhci",
730 "mediatek,mtk-xhci";
731 reg = <0 0x11200000 0 0x2e00>,
732 <0 0x11203e00 0 0x0100>;
733 reg-names = "mac", "ippc";
734 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
735 phys = <&tphyu2port0 PHY_TYPE_USB2>,
736 <&tphyu3port0 PHY_TYPE_USB3>;
737 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
738 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
739 <&infracfg CLK_INFRA_USB_CK_P1>,
740 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
741 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
742 clock-names = "sys_ck",
743 "xhci_ck",
744 "ref_ck",
745 "mcu_ck",
746 "dma_ck";
747 #address-cells = <2>;
748 #size-cells = <2>;
749 status = "disabled";
750 };
751
752 afe: audio-controller@11210000 {
753 compatible = "mediatek,mt79xx-audio";
754 reg = <0 0x11210000 0 0x9000>;
755 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
757 <&infracfg CLK_INFRA_AUD_26M>,
758 <&infracfg CLK_INFRA_AUD_L>,
759 <&infracfg CLK_INFRA_AUD_AUD>,
760 <&infracfg CLK_INFRA_AUD_EG2>,
761 <&topckgen CLK_TOP_AUD_SEL>,
762 <&topckgen CLK_TOP_AUD_I2S_M>;
763 clock-names = "aud_bus_ck",
764 "aud_26m_ck",
765 "aud_l_ck",
766 "aud_aud_ck",
767 "aud_eg2_ck",
768 "aud_sel",
769 "aud_i2s_m";
770 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
771 <&topckgen CLK_TOP_A1SYS_SEL>,
772 <&topckgen CLK_TOP_AUD_L_SEL>,
773 <&topckgen CLK_TOP_A_TUNER_SEL>;
774 assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
775 <&topckgen CLK_TOP_APLL2_D4>,
776 <&apmixedsys CLK_APMIXED_APLL2>,
777 <&topckgen CLK_TOP_APLL2_D4>;
778 status = "disabled";
779 };
780
781 mmc0: mmc@11230000 {
782 compatible = "mediatek,mt7986-mmc",
783 "mediatek,mt7981-mmc";
784 reg = <0 0x11230000 0 0x1000>,
785 <0 0x11D60000 0 0x1000>;
786 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&infracfg CLK_INFRA_MSDC400>,
788 <&infracfg CLK_INFRA_MSDC2_HCK>,
789 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
790 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
791 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
792 <&topckgen CLK_TOP_EMMC_400M_SEL>;
793 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
794 <&apmixedsys CLK_APMIXED_MSDCPLL>;
795 clock-names = "source",
796 "hclk",
797 "axi_cg",
798 "ahb_cg";
799 #address-cells = <1>;
800 #size-cells = <0>;
801 status = "disabled";
802 };
803
804 pcie2: pcie@11280000 {
805 compatible = "mediatek,mt7988-pcie",
806 "mediatek,mt7986-pcie",
807 "mediatek,mt8192-pcie";
808 reg = <0 0x11280000 0 0x2000>;
809 reg-names = "pcie-mac";
810 ranges = <0x81000000 0x00 0x20000000 0x00
811 0x20000000 0x00 0x00200000>,
812 <0x82000000 0x00 0x20200000 0x00
813 0x20200000 0x00 0x07e00000>;
814 device_type = "pci";
815 linux,pci-domain = <3>;
816 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
817 bus-range = <0x00 0xff>;
818 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
819 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
820 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
821 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
822 clock-names = "pl_250m", "tl_26m", "peri_26m",
823 "top_133m";
824 pinctrl-names = "default";
825 pinctrl-0 = <&pcie2_pins>;
826 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
827 phy-names = "pcie-phy";
828 #interrupt-cells = <1>;
829 interrupt-map-mask = <0 0 0 0x7>;
830 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
831 <0 0 0 2 &pcie_intc2 1>,
832 <0 0 0 3 &pcie_intc2 2>,
833 <0 0 0 4 &pcie_intc2 3>;
834 #address-cells = <3>;
835 #size-cells = <2>;
836 status = "disabled";
837
838 pcie_intc2: interrupt-controller {
839 #address-cells = <0>;
840 #interrupt-cells = <1>;
841 interrupt-controller;
842 };
843 };
844
845 pcie3: pcie@11290000 {
846 compatible = "mediatek,mt7988-pcie",
847 "mediatek,mt7986-pcie",
848 "mediatek,mt8192-pcie";
849 reg = <0 0x11290000 0 0x2000>;
850 reg-names = "pcie-mac";
851 ranges = <0x81000000 0x00 0x28000000 0x00
852 0x28000000 0x00 0x00200000>,
853 <0x82000000 0x00 0x28200000 0x00
854 0x28200000 0x00 0x07e00000>;
855 device_type = "pci";
856 linux,pci-domain = <2>;
857 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
858 bus-range = <0x00 0xff>;
859 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
860 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
861 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
862 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
863 clock-names = "pl_250m", "tl_26m", "peri_26m",
864 "top_133m";
865 pinctrl-names = "default";
866 pinctrl-0 = <&pcie3_pins>;
867 #interrupt-cells = <1>;
868 interrupt-map-mask = <0 0 0 0x7>;
869 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
870 <0 0 0 2 &pcie_intc3 1>,
871 <0 0 0 3 &pcie_intc3 2>,
872 <0 0 0 4 &pcie_intc3 3>;
873 #address-cells = <3>;
874 #size-cells = <2>;
875 status = "disabled";
876
877 pcie_intc3: interrupt-controller {
878 #address-cells = <0>;
879 #interrupt-cells = <1>;
880 interrupt-controller;
881 };
882 };
883
884 pcie0: pcie@11300000 {
885 compatible = "mediatek,mt7988-pcie",
886 "mediatek,mt7986-pcie",
887 "mediatek,mt8192-pcie";
888 reg = <0 0x11300000 0 0x2000>;
889 reg-names = "pcie-mac";
890 ranges = <0x81000000 0x00 0x30000000 0x00
891 0x30000000 0x00 0x00200000>,
892 <0x82000000 0x00 0x30200000 0x00
893 0x30200000 0x00 0x07e00000>;
894 device_type = "pci";
895 linux,pci-domain = <0>;
896 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
897 bus-range = <0x00 0xff>;
898 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
899 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
900 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
901 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
902 clock-names = "pl_250m", "tl_26m", "peri_26m",
903 "top_133m";
904 pinctrl-names = "default";
905 pinctrl-0 = <&pcie0_pins>;
906 #interrupt-cells = <1>;
907 interrupt-map-mask = <0 0 0 0x7>;
908 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
909 <0 0 0 2 &pcie_intc0 1>,
910 <0 0 0 3 &pcie_intc0 2>,
911 <0 0 0 4 &pcie_intc0 3>;
912 #address-cells = <3>;
913 #size-cells = <2>;
914 status = "disabled";
915
916 pcie_intc0: interrupt-controller {
917 #address-cells = <0>;
918 #interrupt-cells = <1>;
919 interrupt-controller;
920 };
921 };
922
923 pcie1: pcie@11310000 {
924 compatible = "mediatek,mt7988-pcie",
925 "mediatek,mt7986-pcie",
926 "mediatek,mt8192-pcie";
927 reg = <0 0x11310000 0 0x2000>;
928 reg-names = "pcie-mac";
929 ranges = <0x81000000 0x00 0x38000000 0x00
930 0x38000000 0x00 0x00200000>,
931 <0x82000000 0x00 0x38200000 0x00
932 0x38200000 0x00 0x07e00000>;
933 device_type = "pci";
934 linux,pci-domain = <1>;
935 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
936 bus-range = <0x00 0xff>;
937 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
938 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
939 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
940 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
941 clock-names = "pl_250m", "tl_26m", "peri_26m",
942 "top_133m";
943 pinctrl-names = "default";
944 pinctrl-0 = <&pcie1_pins>;
945 #interrupt-cells = <1>;
946 interrupt-map-mask = <0 0 0 0x7>;
947 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
948 <0 0 0 2 &pcie_intc1 1>,
949 <0 0 0 3 &pcie_intc1 2>,
950 <0 0 0 4 &pcie_intc1 3>;
951 #address-cells = <3>;
952 #size-cells = <2>;
953 status = "disabled";
954
955 pcie_intc1: interrupt-controller {
956 #address-cells = <0>;
957 #interrupt-cells = <1>;
958 interrupt-controller;
959 };
960 };
961
962 tphy: tphy@11c50000 {
963 compatible = "mediatek,mt7988",
964 "mediatek,generic-tphy-v2";
965 ranges;
966 #address-cells = <2>;
967 #size-cells = <2>;
968 status = "disabled";
969
970 tphyu2port0: usb-phy@11c50000 {
971 reg = <0 0x11c50000 0 0x700>;
972 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
973 clock-names = "ref";
974 #phy-cells = <1>;
975 };
976
977 tphyu3port0: usb-phy@11c50700 {
978 reg = <0 0x11c50700 0 0x900>;
979 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
980 clock-names = "ref";
981 #phy-cells = <1>;
982 mediatek,usb3-pll-ssc-delta;
983 mediatek,usb3-pll-ssc-delta1;
984 };
985 };
986
987 topmisc: topmisc@11d10000 {
988 compatible = "mediatek,mt7988-topmisc", "syscon",
989 "mediatek,mt7988-power-controller";
990 reg = <0 0x11d10000 0 0x10000>;
991 #clock-cells = <1>;
992 #power-domain-cells = <1>;
993 #address-cells = <1>;
994 #size-cells = <0>;
995 };
996
997 xphy: xphy@11e10000 {
998 compatible = "mediatek,mt7988",
999 "mediatek,xsphy";
1000 ranges;
1001 #address-cells = <2>;
1002 #size-cells = <2>;
1003 status = "disabled";
1004
1005 xphyu2port0: usb-phy@11e10000 {
1006 reg = <0 0x11e10000 0 0x400>;
1007 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
1008 clock-names = "ref";
1009 #phy-cells = <1>;
1010 };
1011
1012 xphyu3port0: usb-phy@11e13000 {
1013 reg = <0 0x11e13400 0 0x500>;
1014 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1015 clock-names = "ref";
1016 #phy-cells = <1>;
1017 mediatek,syscon-type = <&topmisc 0x218 0>;
1018 };
1019 };
1020
1021 xfi_pextp0: xfi-pextp@11f20000 {
1022 compatible = "mediatek,mt7988-xfi-pextp",
1023 "mediatek,mt7988-xfi-pextp_0",
1024 "syscon";
1025 reg = <0 0x11f20000 0 0x10000>;
1026 #clock-cells = <1>;
1027 };
1028
1029 xfi_pextp1: xfi-pextp@11f30000 {
1030 compatible = "mediatek,mt7988-xfi-pextp",
1031 "mediatek,mt7988-xfi-pextp_1",
1032 "syscon";
1033 reg = <0 0x11f30000 0 0x10000>;
1034 #clock-cells = <1>;
1035 };
1036
1037 xfi_pll: xfi-pll@11f40000 {
1038 compatible = "mediatek,mt7988-xfi-pll", "syscon";
1039 reg = <0 0x11f40000 0 0x1000>;
1040 #clock-cells = <1>;
1041 };
1042
1043 efuse: efuse@11f50000 {
1044 compatible = "mediatek,efuse";
1045 reg = <0 0x11f50000 0 0x1000>;
1046 #address-cells = <1>;
1047 #size-cells = <1>;
1048
1049 lvts_calibration: calib@918 {
1050 reg = <0x918 0x28>;
1051 };
1052
1053 phy_calibration_p0: calib@940 {
1054 reg = <0x940 0x10>;
1055 };
1056
1057 phy_calibration_p1: calib@954 {
1058 reg = <0x954 0x10>;
1059 };
1060
1061 phy_calibration_p2: calib@968 {
1062 reg = <0x968 0x10>;
1063 };
1064
1065 phy_calibration_p3: calib@97c {
1066 reg = <0x97c 0x10>;
1067 };
1068
1069 cpufreq_calibration: calib@278 {
1070 reg = <0x278 0x1>;
1071 };
1072 };
1073
1074 ethsys: syscon@15000000 {
1075 compatible = "mediatek,mt7988-ethsys", "syscon";
1076 reg = <0 0x15000000 0 0x1000>;
1077 #clock-cells = <1>;
1078 #reset-cells = <1>;
1079 #address-cells = <1>;
1080 #size-cells = <1>;
1081 };
1082
1083 switch: switch@15020000 {
1084 compatible = "mediatek,mt7988-switch";
1085 reg = <0 0x15020000 0 0x8000>;
1086 interrupt-controller;
1087 #interrupt-cells = <1>;
1088 interrupt-parent = <&gic>;
1089 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1090 resets = <&ethrst 0>;
1091 #address-cells = <1>;
1092 #size-cells = <1>;
1093
1094 ports {
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1097
1098 port@0 {
1099 reg = <0>;
1100 label = "lan0";
1101 phy-mode = "internal";
1102 phy-handle = <&gsw_phy0>;
1103 };
1104
1105 port@1 {
1106 reg = <1>;
1107 label = "lan1";
1108 phy-mode = "internal";
1109 phy-handle = <&gsw_phy1>;
1110 };
1111
1112 port@2 {
1113 reg = <2>;
1114 label = "lan2";
1115 phy-mode = "internal";
1116 phy-handle = <&gsw_phy2>;
1117 };
1118
1119 port@3 {
1120 reg = <3>;
1121 label = "lan3";
1122 phy-mode = "internal";
1123 phy-handle = <&gsw_phy3>;
1124 };
1125
1126 port@6 {
1127 reg = <6>;
1128 ethernet = <&gmac0>;
1129 phy-mode = "internal";
1130
1131 fixed-link {
1132 speed = <10000>;
1133 full-duplex;
1134 pause;
1135 };
1136 };
1137 };
1138
1139 mdio {
1140 #address-cells = <1>;
1141 #size-cells = <0>;
1142 mediatek,pio = <&pio>;
1143
1144 gsw_phy0: ethernet-phy@0 {
1145 compatible = "ethernet-phy-ieee802.3-c22";
1146 reg = <0>;
1147 phy-mode = "internal";
1148 nvmem-cells = <&phy_calibration_p0>;
1149 nvmem-cell-names = "phy-cal-data";
1150
1151 leds {
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1154
1155 gsw_phy0_led0: gsw-phy0-led0@0 {
1156 reg = <0>;
1157 function = LED_FUNCTION_LAN;
1158 status = "disabled";
1159 };
1160
1161 gsw_phy0_led1: gsw-phy0-led1@1 {
1162 reg = <1>;
1163 function = LED_FUNCTION_LAN;
1164 status = "disabled";
1165 };
1166 };
1167 };
1168
1169 gsw_phy1: ethernet-phy@1 {
1170 compatible = "ethernet-phy-ieee802.3-c22";
1171 reg = <1>;
1172 phy-mode = "internal";
1173 nvmem-cells = <&phy_calibration_p1>;
1174 nvmem-cell-names = "phy-cal-data";
1175
1176 leds {
1177 #address-cells = <1>;
1178 #size-cells = <0>;
1179
1180 gsw_phy1_led0: gsw-phy1-led0@0 {
1181 reg = <0>;
1182 function = LED_FUNCTION_LAN;
1183 status = "disabled";
1184 };
1185
1186 gsw_phy1_led1: gsw-phy1-led1@1 {
1187 reg = <1>;
1188 function = LED_FUNCTION_LAN;
1189 status = "disabled";
1190 };
1191 };
1192 };
1193
1194 gsw_phy2: ethernet-phy@2 {
1195 compatible = "ethernet-phy-ieee802.3-c22";
1196 reg = <2>;
1197 phy-mode = "internal";
1198 nvmem-cells = <&phy_calibration_p2>;
1199 nvmem-cell-names = "phy-cal-data";
1200
1201 leds {
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1204
1205 gsw_phy2_led0: gsw-phy2-led0@0 {
1206 reg = <0>;
1207 function = LED_FUNCTION_LAN;
1208 status = "disabled";
1209 };
1210
1211 gsw_phy2_led1: gsw-phy2-led1@1 {
1212 reg = <1>;
1213 function = LED_FUNCTION_LAN;
1214 status = "disabled";
1215 };
1216 };
1217 };
1218
1219 gsw_phy3: ethernet-phy@3 {
1220 compatible = "ethernet-phy-ieee802.3-c22";
1221 reg = <3>;
1222 phy-mode = "internal";
1223 nvmem-cells = <&phy_calibration_p3>;
1224 nvmem-cell-names = "phy-cal-data";
1225
1226 leds {
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1229
1230 gsw_phy3_led0: gsw-phy3-led0@0 {
1231 reg = <0>;
1232 function = LED_FUNCTION_LAN;
1233 status = "disabled";
1234 };
1235
1236 gsw_phy3_led1: gsw-phy3-led1@1 {
1237 reg = <1>;
1238 function = LED_FUNCTION_LAN;
1239 status = "disabled";
1240 };
1241 };
1242 };
1243 };
1244 };
1245
1246 ethwarp: syscon@15031000 {
1247 compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
1248 reg = <0 0x15031000 0 0x1000>;
1249 #clock-cells = <1>;
1250
1251 ethrst: reset-controller {
1252 compatible = "ti,syscon-reset";
1253 #reset-cells = <1>;
1254 ti,reset-bits = <
1255 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
1256 >;
1257 };
1258 };
1259
1260 eth: ethernet@15100000 {
1261 compatible = "mediatek,mt7988-eth";
1262 reg = <0 0x15100000 0 0x80000>,
1263 <0 0x15400000 0 0x380000>;
1264 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
1269 <&ethsys CLK_ETHDMA_XGP2_EN>,
1270 <&ethsys CLK_ETHDMA_XGP3_EN>,
1271 <&ethsys CLK_ETHDMA_FE_EN>,
1272 <&ethsys CLK_ETHDMA_GP2_EN>,
1273 <&ethsys CLK_ETHDMA_GP1_EN>,
1274 <&ethsys CLK_ETHDMA_GP3_EN>,
1275 <&ethsys CLK_ETHDMA_ESW_EN>,
1276 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
1277 <&sgmiisys0 CLK_SGM0_TX_EN>,
1278 <&sgmiisys0 CLK_SGM0_RX_EN>,
1279 <&sgmiisys1 CLK_SGM1_TX_EN>,
1280 <&sgmiisys1 CLK_SGM1_RX_EN>,
1281 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
1282 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
1283 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
1284 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1285 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1286 <&topckgen CLK_TOP_SGM_0_SEL>,
1287 <&topckgen CLK_TOP_SGM_1_SEL>,
1288 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
1289 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
1290 <&topckgen CLK_TOP_ETH_GMII_SEL>,
1291 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1292 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1293 <&topckgen CLK_TOP_ETH_SYS_SEL>,
1294 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1295 <&topckgen CLK_TOP_ETH_MII_SEL>,
1296 <&topckgen CLK_TOP_NETSYS_SEL>,
1297 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1298 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1299 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1300 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1301 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1302 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1303 "gp3", "esw", "crypto", "sgmii_tx250m",
1304 "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
1305 "ethwarp_wocpu2", "ethwarp_wocpu1",
1306 "ethwarp_wocpu0", "top_usxgmii0_sel",
1307 "top_usxgmii1_sel", "top_sgm0_sel",
1308 "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
1309 "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
1310 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1311 "top_eth_sys_sel", "top_eth_xgmii_sel",
1312 "top_eth_mii_sel", "top_netsys_sel",
1313 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1314 "top_netsys_sync_250m_sel",
1315 "top_netsys_ppefb_250m_sel",
1316 "top_netsys_warp_sel";
1317 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1318 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1319 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1320 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1321 <&topckgen CLK_TOP_SGM_0_SEL>,
1322 <&topckgen CLK_TOP_SGM_1_SEL>;
1323 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1324 <&topckgen CLK_TOP_NET1PLL_D4>,
1325 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1326 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1327 <&apmixedsys CLK_APMIXED_SGMPLL>,
1328 <&apmixedsys CLK_APMIXED_SGMPLL>;
1329 mediatek,ethsys = <&ethsys>;
1330 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
1331 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
1332 mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
1333 mediatek,xfi-pll = <&xfi_pll>;
1334 mediatek,infracfg = <&topmisc>;
1335 mediatek,toprgu = <&watchdog>;
1336 #reset-cells = <1>;
1337 #address-cells = <1>;
1338 #size-cells = <0>;
1339
1340 gmac0: mac@0 {
1341 compatible = "mediatek,eth-mac";
1342 reg = <0>;
1343 phy-mode = "internal";
1344 status = "disabled";
1345
1346 fixed-link {
1347 speed = <10000>;
1348 full-duplex;
1349 pause;
1350 };
1351 };
1352
1353 gmac1: mac@1 {
1354 compatible = "mediatek,eth-mac";
1355 reg = <1>;
1356 status = "disabled";
1357 };
1358
1359 gmac2: mac@2 {
1360 compatible = "mediatek,eth-mac";
1361 reg = <2>;
1362 status = "disabled";
1363 };
1364
1365 mdio_bus: mdio-bus {
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1368
1369 /* internal 2.5G PHY */
1370 int_2p5g_phy: ethernet-phy@15 {
1371 compatible = "ethernet-phy-ieee802.3-c45";
1372 reg = <15>;
1373 phy-mode = "internal";
1374 };
1375 };
1376 };
1377
1378 crypto: crypto@15600000 {
1379 compatible = "inside-secure,safexcel-eip197b";
1380 reg = <0 0x15600000 0 0x180000>;
1381 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1385 interrupt-names = "ring0", "ring1", "ring2", "ring3";
1386 status = "okay";
1387 };
1388 };
1389
1390 thermal-zones {
1391 cpu_thermal: cpu-thermal {
1392 polling-delay-passive = <1000>;
1393 polling-delay = <1000>;
1394 thermal-sensors = <&lvts 0>;
1395
1396 trips {
1397 cpu_trip_crit: crit {
1398 temperature = <125000>;
1399 hysteresis = <2000>;
1400 type = "critical";
1401 };
1402
1403 cpu_trip_hot: hot {
1404 temperature = <120000>;
1405 hysteresis = <2000>;
1406 type = "hot";
1407 };
1408
1409 cpu_trip_active_high: active-high {
1410 temperature = <115000>;
1411 hysteresis = <2000>;
1412 type = "active";
1413 };
1414
1415 cpu_trip_active_med: active-med {
1416 temperature = <85000>;
1417 hysteresis = <2000>;
1418 type = "active";
1419 };
1420
1421 cpu_trip_active_low: active-low {
1422 temperature = <40000>;
1423 hysteresis = <2000>;
1424 type = "active";
1425 };
1426 };
1427
1428 cooling-maps {
1429 cpu-active-high {
1430 /* active: set fan to cooling level 2 */
1431 cooling-device = <&fan 3 3>;
1432 trip = <&cpu_trip_active_high>;
1433 };
1434
1435 cpu-active-low {
1436 /* active: set fan to cooling level 1 */
1437 cooling-device = <&fan 2 2>;
1438 trip = <&cpu_trip_active_med>;
1439 };
1440
1441 cpu-passive {
1442 /* passive: set fan to cooling level 0 */
1443 cooling-device = <&fan 1 1>;
1444 trip = <&cpu_trip_active_low>;
1445 };
1446 };
1447 };
1448 };
1449
1450 timer {
1451 compatible = "arm,armv8-timer";
1452 interrupt-parent = <&gic>;
1453 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1454 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1455 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1456 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1457 };
1458 };
Staging tree of Zoltan Herpai