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bda50936f2a8398acd3028ed943f07ac075faae2
[openwrt/staging/robimarko.git] / target / linux / mediatek / files-5.15 / arch / arm64 / boot / dts / mediatek / mt7988a.dtsi
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2023 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7 #include <dt-bindings/clock/mediatek,mt7988-clk.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy.h>
12 #include <dt-bindings/pinctrl/mt65xx.h>
13 #include <dt-bindings/reset/ti-syscon.h>
14 #include <dt-bindings/thermal/thermal.h>
15
16 / {
17 compatible = "mediatek,mt7988";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 cci: cci {
23 compatible = "mediatek,mt7988-cci",
24 "mediatek,mt8183-cci";
25 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>,
26 <&topckgen CLK_TOP_XTAL>;
27 clock-names = "cci", "intermediate";
28 operating-points-v2 = <&cci_opp>;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 cpu0: cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a73";
37 enable-method = "psci";
38 reg = <0x0>;
39 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
40 <&topckgen CLK_TOP_XTAL>;
41 clock-names = "cpu", "intermediate";
42 operating-points-v2 = <&cluster0_opp>;
43 mediatek,cci = <&cci>;
44 };
45
46 cpu1: cpu@1 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a73";
49 enable-method = "psci";
50 reg = <0x1>;
51 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
52 <&topckgen CLK_TOP_XTAL>;
53 clock-names = "cpu", "intermediate";
54 operating-points-v2 = <&cluster0_opp>;
55 mediatek,cci = <&cci>;
56 };
57
58 cpu2: cpu@2 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a73";
61 enable-method = "psci";
62 reg = <0x2>;
63 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
64 <&topckgen CLK_TOP_XTAL>;
65 clock-names = "cpu", "intermediate";
66 operating-points-v2 = <&cluster0_opp>;
67 mediatek,cci = <&cci>;
68 };
69
70 cpu3: cpu@3 {
71 device_type = "cpu";
72 compatible = "arm,cortex-a73";
73 enable-method = "psci";
74 reg = <0x3>;
75 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>,
76 <&topckgen CLK_TOP_XTAL>;
77 clock-names = "cpu", "intermediate";
78 operating-points-v2 = <&cluster0_opp>;
79 mediatek,cci = <&cci>;
80 };
81
82 cluster0_opp: opp_table0 {
83 compatible = "operating-points-v2";
84 opp-shared;
85 opp00 {
86 opp-hz = /bits/ 64 <800000000>;
87 opp-microvolt = <850000>;
88 };
89 opp01 {
90 opp-hz = /bits/ 64 <1100000000>;
91 opp-microvolt = <850000>;
92 };
93 opp02 {
94 opp-hz = /bits/ 64 <1500000000>;
95 opp-microvolt = <850000>;
96 };
97 opp03 {
98 opp-hz = /bits/ 64 <1800000000>;
99 opp-microvolt = <900000>;
100 };
101 };
102 };
103
104 cci_opp: opp_table_cci {
105 compatible = "operating-points-v2";
106 opp-shared;
107 opp00 {
108 opp-hz = /bits/ 64 <480000000>;
109 opp-microvolt = <850000>;
110 };
111 opp01 {
112 opp-hz = /bits/ 64 <660000000>;
113 opp-microvolt = <850000>;
114 };
115 opp02 {
116 opp-hz = /bits/ 64 <900000000>;
117 opp-microvolt = <850000>;
118 };
119 opp03 {
120 opp-hz = /bits/ 64 <1080000000>;
121 opp-microvolt = <900000>;
122 };
123 };
124
125 clk40m: oscillator@0 {
126 compatible = "fixed-clock";
127 clock-frequency = <40000000>;
128 #clock-cells = <0>;
129 clock-output-names = "clkxtal";
130 };
131
132 pmu {
133 compatible = "arm,cortex-a73-pmu";
134 interrupt-parent = <&gic>;
135 interrupt = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
136 };
137
138 psci {
139 compatible = "arm,psci-0.2";
140 method = "smc";
141 };
142
143 reg_1p8v: regulator-1p8v {
144 compatible = "regulator-fixed";
145 regulator-name = "fixed-1.8V";
146 regulator-min-microvolt = <1800000>;
147 regulator-max-microvolt = <1800000>;
148 regulator-boot-on;
149 regulator-always-on;
150 };
151
152 reg_3p3v: regulator-3p3v {
153 compatible = "regulator-fixed";
154 regulator-name = "fixed-3.3V";
155 regulator-min-microvolt = <3300000>;
156 regulator-max-microvolt = <3300000>;
157 regulator-boot-on;
158 regulator-always-on;
159 };
160
161 reserved-memory {
162 #address-cells = <2>;
163 #size-cells = <2>;
164 ranges;
165
166 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */
167 secmon_reserved: secmon@43000000 {
168 reg = <0 0x43000000 0 0x50000>;
169 no-map;
170 };
171 };
172
173 soc {
174 #address-cells = <2>;
175 #size-cells = <2>;
176 compatible = "simple-bus";
177 ranges;
178
179 gic: interrupt-controller@c000000 {
180 compatible = "arm,gic-v3";
181 #interrupt-cells = <3>;
182 interrupt-parent = <&gic>;
183 interrupt-controller;
184 reg = <0 0x0c000000 0 0x40000>, /* GICD */
185 <0 0x0c080000 0 0x200000>, /* GICR */
186 <0 0x0c400000 0 0x2000>, /* GICC */
187 <0 0x0c410000 0 0x1000>, /* GICH */
188 <0 0x0c420000 0 0x2000>; /* GICV */
189
190 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
191 };
192
193 phyfw: phy-firmware@f000000 {
194 compatible = "mediatek,2p5gphy-fw";
195 reg = <0 0x0f000000 0 0x8000>,
196 <0 0x0f100000 0 0x20000>,
197 <0 0x0f0f0000 0 0x200>;
198 };
199
200 infracfg: infracfg@10001000 {
201 compatible = "mediatek,mt7988-infracfg", "syscon";
202 reg = <0 0x10001000 0 0x1000>;
203 #clock-cells = <1>;
204 };
205
206 topckgen: topckgen@1001b000 {
207 compatible = "mediatek,mt7988-topckgen", "syscon";
208 reg = <0 0x1001b000 0 0x1000>;
209 #clock-cells = <1>;
210 };
211
212 watchdog: watchdog@1001c000 {
213 compatible = "mediatek,mt7988-wdt",
214 "mediatek,mt6589-wdt",
215 "syscon";
216 reg = <0 0x1001c000 0 0x1000>;
217 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
218 #reset-cells = <1>;
219 };
220
221 apmixedsys: apmixedsys@1001e000 {
222 compatible = "mediatek,mt7988-apmixedsys";
223 reg = <0 0x1001e000 0 0x1000>;
224 #clock-cells = <1>;
225 };
226
227 pio: pinctrl@1001f000 {
228 compatible = "mediatek,mt7988-pinctrl", "syscon";
229 reg = <0 0x1001f000 0 0x1000>,
230 <0 0x11c10000 0 0x1000>,
231 <0 0x11d00000 0 0x1000>,
232 <0 0x11d20000 0 0x1000>,
233 <0 0x11e00000 0 0x1000>,
234 <0 0x11f00000 0 0x1000>,
235 <0 0x1000b000 0 0x1000>;
236 reg-names = "gpio_base", "iocfg_tr_base",
237 "iocfg_br_base", "iocfg_rb_base",
238 "iocfg_lb_base", "iocfg_tl_base", "eint";
239 gpio-controller;
240 #gpio-cells = <2>;
241 gpio-ranges = <&pio 0 0 84>;
242 interrupt-controller;
243 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
244 interrupt-parent = <&gic>;
245 #interrupt-cells = <2>;
246
247 mdio0_pins: mdio0-pins {
248 mux {
249 function = "eth";
250 groups = "mdc_mdio0";
251 };
252
253 conf {
254 groups = "mdc_mdio0";
255 drive-strength = <MTK_DRIVE_8mA>;
256 };
257 };
258
259 i2c0_pins: i2c0-pins-g0 {
260 mux {
261 function = "i2c";
262 groups = "i2c0_1";
263 };
264 };
265
266 i2c1_pins: i2c1-pins-g0 {
267 mux {
268 function = "i2c";
269 groups = "i2c1_0";
270 };
271 };
272
273 i2c1_sfp_pins: i2c1-sfp-pins-g0 {
274 mux {
275 function = "i2c";
276 groups = "i2c1_sfp";
277 };
278 };
279
280 i2c2_pins: i2c2-pins {
281 mux {
282 function = "i2c";
283 groups = "i2c2";
284 };
285 };
286
287 i2c2_0_pins: i2c2-pins-g0 {
288 mux {
289 function = "i2c";
290 groups = "i2c2_0";
291 };
292 };
293
294 i2c2_1_pins: i2c2-pins-g1 {
295 mux {
296 function = "i2c";
297 groups = "i2c2_1";
298 };
299 };
300
301 gbe0_led0_pins: gbe0-led0-pins {
302 mux {
303 function = "led";
304 groups = "gbe0_led0";
305 };
306 };
307
308 gbe1_led0_pins: gbe1-led0-pins {
309 mux {
310 function = "led";
311 groups = "gbe1_led0";
312 };
313 };
314
315 gbe2_led0_pins: gbe2-led0-pins {
316 mux {
317 function = "led";
318 groups = "gbe2_led0";
319 };
320 };
321
322 gbe3_led0_pins: gbe3-led0-pins {
323 mux {
324 function = "led";
325 groups = "gbe3_led0";
326 };
327 };
328
329 gbe0_led1_pins: gbe0-led1-pins {
330 mux {
331 function = "led";
332 groups = "gbe0_led1";
333 };
334 };
335
336 gbe1_led1_pins: gbe1-led1-pins {
337 mux {
338 function = "led";
339 groups = "gbe1_led1";
340 };
341 };
342
343 gbe2_led1_pins: gbe2-led1-pins {
344 mux {
345 function = "led";
346 groups = "gbe2_led1";
347 };
348 };
349
350 gbe3_led1_pins: gbe3-led1-pins {
351 mux {
352 function = "led";
353 groups = "gbe3_led1";
354 };
355 };
356
357 i2p5gbe_led0_pins: 2p5gbe-led0-pins {
358 mux {
359 function = "led";
360 groups = "2p5gbe_led0";
361 };
362 };
363
364 i2p5gbe_led1_pins: 2p5gbe-led1-pins {
365 mux {
366 function = "led";
367 groups = "2p5gbe_led1";
368 };
369 };
370
371 mmc0_pins_emmc_45: mmc0-pins-emmc-45 {
372 mux {
373 function = "flash";
374 groups = "emmc_45";
375 };
376 };
377
378 mmc0_pins_emmc_51: mmc0-pins-emmc-51 {
379 mux {
380 function = "flash";
381 groups = "emmc_51";
382 };
383 };
384
385 mmc0_pins_sdcard: mmc0-pins-sdcard {
386 mux {
387 function = "flash";
388 groups = "sdcard";
389 };
390 };
391
392 uart0_pins: uart0-pins {
393 mux {
394 function = "uart";
395 groups = "uart0";
396 };
397 };
398
399 snfi_pins: snfi-pins {
400 mux {
401 function = "flash";
402 groups = "snfi";
403 };
404 };
405
406 spi0_pins: spi0-pins {
407 mux {
408 function = "spi";
409 groups = "spi0";
410 };
411 };
412
413 spi0_flash_pins: spi0-flash-pins {
414 mux {
415 function = "spi";
416 groups = "spi0", "spi0_wp_hold";
417 };
418 };
419
420 spi1_pins: spi1-pins {
421 mux {
422 function = "spi";
423 groups = "spi1";
424 };
425 };
426
427 spi2_pins: spi2-pins {
428 mux {
429 function = "spi";
430 groups = "spi2";
431 };
432 };
433
434 spi2_flash_pins: spi2-flash-pins {
435 mux {
436 function = "spi";
437 groups = "spi2", "spi2_wp_hold";
438 };
439 };
440
441 pcie0_pins: pcie0-pins {
442 mux {
443 function = "pcie";
444 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
445 "pcie_wake_n0_0";
446 };
447 };
448
449 pcie1_pins: pcie1-pins {
450 mux {
451 function = "pcie";
452 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
453 "pcie_wake_n1_0";
454 };
455 };
456
457 pcie2_pins: pcie2-pins {
458 mux {
459 function = "pcie";
460 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
461 "pcie_wake_n2_0";
462 };
463 };
464
465 pcie3_pins: pcie3-pins {
466 mux {
467 function = "pcie";
468 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
469 "pcie_wake_n3_0";
470 };
471 };
472 };
473
474 pwm: pwm@10048000 {
475 compatible = "mediatek,mt7988-pwm";
476 reg = <0 0x10048000 0 0x1000>;
477 #pwm-cells = <2>;
478 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>,
479 <&infracfg CLK_INFRA_66M_PWM_HCK>,
480 <&infracfg CLK_INFRA_66M_PWM_CK1>,
481 <&infracfg CLK_INFRA_66M_PWM_CK2>,
482 <&infracfg CLK_INFRA_66M_PWM_CK3>,
483 <&infracfg CLK_INFRA_66M_PWM_CK4>,
484 <&infracfg CLK_INFRA_66M_PWM_CK5>,
485 <&infracfg CLK_INFRA_66M_PWM_CK6>,
486 <&infracfg CLK_INFRA_66M_PWM_CK7>,
487 <&infracfg CLK_INFRA_66M_PWM_CK8>;
488 clock-names = "top", "main", "pwm1", "pwm2", "pwm3",
489 "pwm4","pwm5","pwm6","pwm7","pwm8";
490 status = "disabled";
491 };
492
493 sgmiisys0: syscon@10060000 {
494 compatible = "mediatek,mt7988-sgmiisys",
495 "mediatek,mt7988-sgmiisys_0",
496 "syscon";
497 reg = <0 0x10060000 0 0x1000>;
498 #clock-cells = <1>;
499 };
500
501 sgmiisys1: syscon@10070000 {
502 compatible = "mediatek,mt7988-sgmiisys",
503 "mediatek,mt7988-sgmiisys_1",
504 "syscon";
505 reg = <0 0x10070000 0 0x1000>;
506 #clock-cells = <1>;
507 };
508
509 usxgmiisys0: usxgmiisys@10080000 {
510 compatible = "mediatek,mt7988-usxgmiisys",
511 "mediatek,mt7988-usxgmiisys_0",
512 "syscon";
513 reg = <0 0x10080000 0 0x1000>;
514 #clock-cells = <1>;
515 };
516
517 usxgmiisys1: usxgmiisys@10081000 {
518 compatible = "mediatek,mt7988-usxgmiisys",
519 "mediatek,mt7988-usxgmiisys_1",
520 "syscon";
521 reg = <0 0x10081000 0 0x1000>;
522 #clock-cells = <1>;
523 };
524
525 mcusys: mcusys@100e0000 {
526 compatible = "mediatek,mt7988-mcusys", "syscon";
527 reg = <0 0x100e0000 0 0x1000>;
528 #clock-cells = <1>;
529 };
530
531 uart0: serial@11000000 {
532 compatible = "mediatek,mt7986-uart",
533 "mediatek,mt6577-uart";
534 reg = <0 0x11000000 0 0x100>;
535 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
536 /*
537 * 8250-mtk driver don't control "baud" clock since commit
538 * e32a83c70cf9 (kernel v5.7), but both "baud" and "bus" clocks
539 * still need to be passed to the driver to prevent probe fail
540 */
541 clocks = <&topckgen CLK_TOP_UART_SEL>,
542 <&infracfg CLK_INFRA_52M_UART0_CK>;
543 clock-names = "baud", "bus";
544 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
545 <&infracfg CLK_INFRA_MUX_UART0_SEL>;
546 assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
547 <&topckgen CLK_TOP_UART_SEL>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&uart0_pins>;
550 status = "disabled";
551 };
552
553 snand: spi@11001000 {
554 compatible = "mediatek,mt7986-snand";
555 reg = <0 0x11001000 0 0x1000>;
556 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
557 clocks = <&infracfg CLK_INFRA_SPINFI>,
558 <&infracfg CLK_INFRA_NFI>;
559 clock-names = "pad_clk", "nfi_clk";
560 assigned-clocks = <&topckgen CLK_TOP_SPINFI_SEL>,
561 <&topckgen CLK_TOP_NFI1X_SEL>;
562 assigned-clock-parents = <&topckgen CLK_TOP_MPLL_D8>,
563 <&topckgen CLK_TOP_MPLL_D8>;
564 nand-ecc-engine = <&bch>;
565 mediatek,quad-spi;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 pinctrl-names = "default";
569 pinctrl-0 = <&snfi_pins>;
570 status = "disabled";
571 };
572
573 bch: ecc@11002000 {
574 compatible = "mediatek,mt7686-ecc";
575 reg = <0 0x11002000 0 0x1000>;
576 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&topckgen CLK_TOP_NFI1X_SEL>;
578 clock-names = "nfiecc_clk";
579 status = "disabled";
580 };
581
582 i2c0: i2c@11003000 {
583 compatible = "mediatek,mt7988-i2c",
584 "mediatek,mt7981-i2c";
585 reg = <0 0x11003000 0 0x1000>,
586 <0 0x10217080 0 0x80>;
587 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
588 clock-div = <1>;
589 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
590 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
591 clock-names = "main", "dma";
592 #address-cells = <1>;
593 #size-cells = <0>;
594 status = "disabled";
595 };
596
597 i2c1: i2c@11004000 {
598 compatible = "mediatek,mt7988-i2c",
599 "mediatek,mt7981-i2c";
600 reg = <0 0x11004000 0 0x1000>,
601 <0 0x10217100 0 0x80>;
602 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
603 clock-div = <1>;
604 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
605 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
606 clock-names = "main", "dma";
607 #address-cells = <1>;
608 #size-cells = <0>;
609 status = "disabled";
610 };
611
612 i2c2: i2c@11005000 {
613 compatible = "mediatek,mt7988-i2c",
614 "mediatek,mt7981-i2c";
615 reg = <0 0x11005000 0 0x1000>,
616 <0 0x10217180 0 0x80>;
617 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
618 clock-div = <1>;
619 clocks = <&infracfg CLK_INFRA_I2C_BCK>,
620 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>;
621 clock-names = "main", "dma";
622 #address-cells = <1>;
623 #size-cells = <0>;
624 status = "disabled";
625 };
626
627 spi0: spi@11007000 {
628 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
629 reg = <0 0x11007000 0 0x100>;
630 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&topckgen CLK_TOP_MPLL_D2>,
632 <&topckgen CLK_TOP_SPI_SEL>,
633 <&infracfg CLK_INFRA_104M_SPI0>,
634 <&infracfg CLK_INFRA_66M_SPI0_HCK>;
635 clock-names = "parent-clk", "sel-clk", "spi-clk",
636 "spi-hclk";
637 #address-cells = <1>;
638 #size-cells = <0>;
639 status = "disabled";
640 };
641
642 spi1: spi@11008000 {
643 compatible = "mediatek,ipm-spi-single", "mediatek,spi-ipm";
644 reg = <0 0x11008000 0 0x100>;
645 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&topckgen CLK_TOP_MPLL_D2>,
647 <&topckgen CLK_TOP_SPI_SEL>,
648 <&infracfg CLK_INFRA_104M_SPI1>,
649 <&infracfg CLK_INFRA_66M_SPI1_HCK>;
650 clock-names = "parent-clk", "sel-clk", "spi-clk",
651 "spi-hclk";
652 #address-cells = <1>;
653 #size-cells = <0>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&spi1_pins>;
656 status = "disabled";
657 };
658
659 spi2: spi@11009000 {
660 compatible = "mediatek,ipm-spi-quad", "mediatek,spi-ipm";
661 reg = <0 0x11009000 0 0x100>;
662 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&topckgen CLK_TOP_MPLL_D2>,
664 <&topckgen CLK_TOP_SPI_SEL>,
665 <&infracfg CLK_INFRA_104M_SPI2_BCK>,
666 <&infracfg CLK_INFRA_66M_SPI2_HCK>;
667 clock-names = "parent-clk", "sel-clk", "spi-clk",
668 "spi-hclk";
669 #address-cells = <1>;
670 #size-cells = <0>;
671 status = "disabled";
672 };
673
674 fan: pwm-fan {
675 compatible = "pwm-fan";
676 /* cooling level (0, 1, 2) : (0% duty, 50% duty, 100% duty) */
677 cooling-levels = <0 128 255>;
678 #cooling-cells = <2>;
679 #thermal-sensor-cells = <1>;
680 status = "disabled";
681 };
682
683 lvts: lvts@1100a000 {
684 compatible = "mediatek,mt7988-lvts";
685 #thermal-sensor-cells = <1>;
686 reg = <0 0x1100a000 0 0x1000>;
687 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>;
688 clock-names = "lvts_clk";
689 nvmem-cells = <&lvts_calibration>;
690 nvmem-cell-names = "e_data1";
691 };
692
693 ssusb0: usb@11190000 {
694 compatible = "mediatek,mt7988-xhci",
695 "mediatek,mtk-xhci";
696 reg = <0 0x11190000 0 0x2e00>,
697 <0 0x11193e00 0 0x0100>;
698 reg-names = "mac", "ippc";
699 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
700 phys = <&xphyu2port0 PHY_TYPE_USB2>,
701 <&xphyu3port0 PHY_TYPE_USB3>;
702 clocks = <&infracfg CLK_INFRA_USB_SYS>,
703 <&infracfg CLK_INFRA_USB_XHCI>,
704 <&infracfg CLK_INFRA_USB_REF>,
705 <&infracfg CLK_INFRA_66M_USB_HCK>,
706 <&infracfg CLK_INFRA_133M_USB_HCK>;
707 clock-names = "sys_ck",
708 "xhci_ck",
709 "ref_ck",
710 "mcu_ck",
711 "dma_ck";
712 #address-cells = <2>;
713 #size-cells = <2>;
714 mediatek,p0_speed_fixup;
715 status = "disabled";
716 };
717
718 ssusb1: usb@11200000 {
719 compatible = "mediatek,mt7988-xhci",
720 "mediatek,mtk-xhci";
721 reg = <0 0x11200000 0 0x2e00>,
722 <0 0x11203e00 0 0x0100>;
723 reg-names = "mac", "ippc";
724 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
725 phys = <&tphyu2port0 PHY_TYPE_USB2>,
726 <&tphyu3port0 PHY_TYPE_USB3>;
727 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>,
728 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>,
729 <&infracfg CLK_INFRA_USB_CK_P1>,
730 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>,
731 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>;
732 clock-names = "sys_ck",
733 "xhci_ck",
734 "ref_ck",
735 "mcu_ck",
736 "dma_ck";
737 #address-cells = <2>;
738 #size-cells = <2>;
739 status = "disabled";
740 };
741
742 afe: audio-controller@11210000 {
743 compatible = "mediatek,mt79xx-audio";
744 reg = <0 0x11210000 0 0x9000>;
745 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
746 clocks = <&infracfg CLK_INFRA_66M_AUD_SLV_BCK>,
747 <&infracfg CLK_INFRA_AUD_26M>,
748 <&infracfg CLK_INFRA_AUD_L>,
749 <&infracfg CLK_INFRA_AUD_AUD>,
750 <&infracfg CLK_INFRA_AUD_EG2>,
751 <&topckgen CLK_TOP_AUD_SEL>,
752 <&topckgen CLK_TOP_AUD_I2S_M>;
753 clock-names = "aud_bus_ck",
754 "aud_26m_ck",
755 "aud_l_ck",
756 "aud_aud_ck",
757 "aud_eg2_ck",
758 "aud_sel",
759 "aud_i2s_m";
760 assigned-clocks = <&topckgen CLK_TOP_AUD_SEL>,
761 <&topckgen CLK_TOP_A1SYS_SEL>,
762 <&topckgen CLK_TOP_AUD_L_SEL>,
763 <&topckgen CLK_TOP_A_TUNER_SEL>;
764 assigned-clock-parents = <&apmixedsys CLK_APMIXED_APLL2>,
765 <&topckgen CLK_TOP_APLL2_D4>,
766 <&apmixedsys CLK_APMIXED_APLL2>,
767 <&topckgen CLK_TOP_APLL2_D4>;
768 status = "disabled";
769 };
770
771 mmc0: mmc@11230000 {
772 compatible = "mediatek,mt7986-mmc",
773 "mediatek,mt7981-mmc";
774 reg = <0 0x11230000 0 0x1000>,
775 <0 0x11D60000 0 0x1000>;
776 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&infracfg CLK_INFRA_MSDC400>,
778 <&infracfg CLK_INFRA_MSDC2_HCK>,
779 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>,
780 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>;
781 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>,
782 <&topckgen CLK_TOP_EMMC_400M_SEL>;
783 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>,
784 <&apmixedsys CLK_APMIXED_MSDCPLL>;
785 clock-names = "source",
786 "hclk",
787 "axi_cg",
788 "ahb_cg";
789 #address-cells = <1>;
790 #size-cells = <0>;
791 status = "disabled";
792 };
793
794 pcie2: pcie@11280000 {
795 compatible = "mediatek,mt7988-pcie",
796 "mediatek,mt7986-pcie",
797 "mediatek,mt8192-pcie";
798 device_type = "pci";
799 #address-cells = <3>;
800 #size-cells = <2>;
801 reg = <0 0x11280000 0 0x2000>;
802 reg-names = "pcie-mac";
803 linux,pci-domain = <3>;
804 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
805 bus-range = <0x00 0xff>;
806 ranges = <0x81000000 0x00 0x20000000 0x00
807 0x20000000 0x00 0x00200000>,
808 <0x82000000 0x00 0x20200000 0x00
809 0x20200000 0x00 0x07e00000>;
810 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>,
811 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>,
812 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>,
813 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>;
814 clock-names = "pl_250m", "tl_26m", "peri_26m",
815 "top_133m";
816 pinctrl-names = "default";
817 pinctrl-0 = <&pcie2_pins>;
818 status = "disabled";
819
820 phys = <&xphyu3port0 PHY_TYPE_PCIE>;
821 phy-names = "pcie-phy";
822
823 #interrupt-cells = <1>;
824 interrupt-map-mask = <0 0 0 0x7>;
825 interrupt-map = <0 0 0 1 &pcie_intc2 0>,
826 <0 0 0 2 &pcie_intc2 1>,
827 <0 0 0 3 &pcie_intc2 2>,
828 <0 0 0 4 &pcie_intc2 3>;
829 pcie_intc2: interrupt-controller {
830 #address-cells = <0>;
831 #interrupt-cells = <1>;
832 interrupt-controller;
833 };
834 };
835
836 pcie3: pcie@11290000 {
837 compatible = "mediatek,mt7988-pcie",
838 "mediatek,mt7986-pcie",
839 "mediatek,mt8192-pcie";
840 device_type = "pci";
841 #address-cells = <3>;
842 #size-cells = <2>;
843 reg = <0 0x11290000 0 0x2000>;
844 reg-names = "pcie-mac";
845 linux,pci-domain = <2>;
846 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
847 bus-range = <0x00 0xff>;
848 ranges = <0x81000000 0x00 0x28000000 0x00
849 0x28000000 0x00 0x00200000>,
850 <0x82000000 0x00 0x28200000 0x00
851 0x28200000 0x00 0x07e00000>;
852 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>,
853 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>,
854 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>,
855 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>;
856 clock-names = "pl_250m", "tl_26m", "peri_26m",
857 "top_133m";
858 pinctrl-names = "default";
859 pinctrl-0 = <&pcie3_pins>;
860 status = "disabled";
861
862 #interrupt-cells = <1>;
863 interrupt-map-mask = <0 0 0 0x7>;
864 interrupt-map = <0 0 0 1 &pcie_intc3 0>,
865 <0 0 0 2 &pcie_intc3 1>,
866 <0 0 0 3 &pcie_intc3 2>,
867 <0 0 0 4 &pcie_intc3 3>;
868 pcie_intc3: interrupt-controller {
869 #address-cells = <0>;
870 #interrupt-cells = <1>;
871 interrupt-controller;
872 };
873 };
874
875 pcie0: pcie@11300000 {
876 compatible = "mediatek,mt7988-pcie",
877 "mediatek,mt7986-pcie",
878 "mediatek,mt8192-pcie";
879 device_type = "pci";
880 #address-cells = <3>;
881 #size-cells = <2>;
882 reg = <0 0x11300000 0 0x2000>;
883 reg-names = "pcie-mac";
884 linux,pci-domain = <0>;
885 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
886 bus-range = <0x00 0xff>;
887 ranges = <0x81000000 0x00 0x30000000 0x00
888 0x30000000 0x00 0x00200000>,
889 <0x82000000 0x00 0x30200000 0x00
890 0x30200000 0x00 0x07e00000>;
891 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>,
892 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>,
893 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>,
894 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>;
895 clock-names = "pl_250m", "tl_26m", "peri_26m",
896 "top_133m";
897 pinctrl-names = "default";
898 pinctrl-0 = <&pcie0_pins>;
899 status = "disabled";
900
901 #interrupt-cells = <1>;
902 interrupt-map-mask = <0 0 0 0x7>;
903 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
904 <0 0 0 2 &pcie_intc0 1>,
905 <0 0 0 3 &pcie_intc0 2>,
906 <0 0 0 4 &pcie_intc0 3>;
907 pcie_intc0: interrupt-controller {
908 #address-cells = <0>;
909 #interrupt-cells = <1>;
910 interrupt-controller;
911 };
912 };
913
914 pcie1: pcie@11310000 {
915 compatible = "mediatek,mt7988-pcie",
916 "mediatek,mt7986-pcie",
917 "mediatek,mt8192-pcie";
918 device_type = "pci";
919 #address-cells = <3>;
920 #size-cells = <2>;
921 reg = <0 0x11310000 0 0x2000>;
922 reg-names = "pcie-mac";
923 linux,pci-domain = <1>;
924 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
925 bus-range = <0x00 0xff>;
926 ranges = <0x81000000 0x00 0x38000000 0x00
927 0x38000000 0x00 0x00200000>,
928 <0x82000000 0x00 0x38200000 0x00
929 0x38200000 0x00 0x07e00000>;
930 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>,
931 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>,
932 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>,
933 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>;
934 clock-names = "pl_250m", "tl_26m", "peri_26m",
935 "top_133m";
936 pinctrl-names = "default";
937 pinctrl-0 = <&pcie1_pins>;
938 status = "disabled";
939
940 #interrupt-cells = <1>;
941 interrupt-map-mask = <0 0 0 0x7>;
942 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
943 <0 0 0 2 &pcie_intc1 1>,
944 <0 0 0 3 &pcie_intc1 2>,
945 <0 0 0 4 &pcie_intc1 3>;
946 pcie_intc1: interrupt-controller {
947 #address-cells = <0>;
948 #interrupt-cells = <1>;
949 interrupt-controller;
950 };
951 };
952
953 tphy: tphy@11c50000 {
954 compatible = "mediatek,mt7988",
955 "mediatek,generic-tphy-v2";
956 #address-cells = <2>;
957 #size-cells = <2>;
958 ranges;
959 status = "disabled";
960 tphyu2port0: usb-phy@11c50000 {
961 reg = <0 0x11c50000 0 0x700>;
962 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>;
963 clock-names = "ref";
964 #phy-cells = <1>;
965 };
966 tphyu3port0: usb-phy@11c50700 {
967 reg = <0 0x11c50700 0 0x900>;
968 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>;
969 clock-names = "ref";
970 #phy-cells = <1>;
971 mediatek,usb3-pll-ssc-delta;
972 mediatek,usb3-pll-ssc-delta1;
973 };
974 };
975
976 topmisc: topmisc@11d10000 {
977 compatible = "mediatek,mt7988-topmisc", "syscon",
978 "mediatek,mt7988-power-controller";
979 reg = <0 0x11d10000 0 0x10000>;
980 #clock-cells = <1>;
981 #power-domain-cells = <1>;
982 #address-cells = <1>;
983 #size-cells = <0>;
984 };
985
986 xphy: xphy@11e10000 {
987 compatible = "mediatek,mt7988",
988 "mediatek,xsphy";
989 #address-cells = <2>;
990 #size-cells = <2>;
991 ranges;
992 status = "disabled";
993
994 xphyu2port0: usb-phy@11e10000 {
995 reg = <0 0x11e10000 0 0x400>;
996 clocks = <&infracfg CLK_INFRA_USB_UTMI>;
997 clock-names = "ref";
998 #phy-cells = <1>;
999 };
1000
1001 xphyu3port0: usb-phy@11e13000 {
1002 reg = <0 0x11e13400 0 0x500>;
1003 clocks = <&infracfg CLK_INFRA_USB_PIPE>;
1004 clock-names = "ref";
1005 #phy-cells = <1>;
1006 mediatek,syscon-type = <&topmisc 0x218 0>;
1007 };
1008 };
1009
1010 xfi_pextp0: xfi-pextp@11f20000 {
1011 compatible = "mediatek,mt7988-xfi-pextp",
1012 "mediatek,mt7988-xfi-pextp_0",
1013 "syscon";
1014 reg = <0 0x11f20000 0 0x10000>;
1015 #clock-cells = <1>;
1016 };
1017
1018 xfi_pextp1: xfi-pextp@11f30000 {
1019 compatible = "mediatek,mt7988-xfi-pextp",
1020 "mediatek,mt7988-xfi-pextp_1",
1021 "syscon";
1022 reg = <0 0x11f30000 0 0x10000>;
1023 #clock-cells = <1>;
1024 };
1025
1026 xfi_pll: xfi-pll@11f40000 {
1027 compatible = "mediatek,mt7988-xfi-pll", "syscon";
1028 reg = <0 0x11f40000 0 0x1000>;
1029 #clock-cells = <1>;
1030 };
1031
1032 efuse: efuse@11f50000 {
1033 compatible = "mediatek,efuse";
1034 reg = <0 0x11f50000 0 0x1000>;
1035 #address-cells = <1>;
1036 #size-cells = <1>;
1037
1038 lvts_calibration: calib@918 {
1039 reg = <0x918 0x28>;
1040 };
1041 phy_calibration_p0: calib@940 {
1042 reg = <0x940 0x10>;
1043 };
1044 phy_calibration_p1: calib@954 {
1045 reg = <0x954 0x10>;
1046 };
1047 phy_calibration_p2: calib@968 {
1048 reg = <0x968 0x10>;
1049 };
1050 phy_calibration_p3: calib@97c {
1051 reg = <0x97c 0x10>;
1052 };
1053 cpufreq_calibration: calib@278 {
1054 reg = <0x278 0x1>;
1055 };
1056 };
1057
1058 ethsys: syscon@15000000 {
1059 #address-cells = <1>;
1060 #size-cells = <1>;
1061 compatible = "mediatek,mt7988-ethsys", "syscon";
1062 reg = <0 0x15000000 0 0x1000>;
1063 #clock-cells = <1>;
1064 #reset-cells = <1>;
1065 };
1066
1067 switch: switch@15020000 {
1068 #address-cells = <1>;
1069 #size-cells = <1>;
1070 compatible = "mediatek,mt7988-switch";
1071 reg = <0 0x15020000 0 0x8000>;
1072 interrupt-controller;
1073 #interrupt-cells = <1>;
1074 interrupt-parent = <&gic>;
1075 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1076 resets = <&ethrst 0>;
1077
1078 ports {
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1081
1082 port@0 {
1083 reg = <0>;
1084 label = "lan0";
1085 phy-mode = "internal";
1086 phy-handle = <&gsw_phy0>;
1087 };
1088
1089 port@1 {
1090 reg = <1>;
1091 label = "lan1";
1092 phy-mode = "internal";
1093 phy-handle = <&gsw_phy1>;
1094 };
1095
1096 port@2 {
1097 reg = <2>;
1098 label = "lan2";
1099 phy-mode = "internal";
1100 phy-handle = <&gsw_phy2>;
1101 };
1102
1103 port@3 {
1104 reg = <3>;
1105 label = "lan3";
1106 phy-mode = "internal";
1107 phy-handle = <&gsw_phy3>;
1108 };
1109
1110 port@6 {
1111 reg = <6>;
1112 ethernet = <&gmac0>;
1113 phy-mode = "internal";
1114
1115 fixed-link {
1116 speed = <10000>;
1117 full-duplex;
1118 pause;
1119 };
1120 };
1121 };
1122
1123 mdio {
1124 #address-cells = <1>;
1125 #size-cells = <0>;
1126 mediatek,pio = <&pio>;
1127
1128 gsw_phy0: ethernet-phy@0 {
1129 compatible = "ethernet-phy-ieee802.3-c22";
1130 reg = <0>;
1131 phy-mode = "internal";
1132 nvmem-cells = <&phy_calibration_p0>;
1133 nvmem-cell-names = "phy-cal-data";
1134
1135 leds {
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138
1139 gsw_phy0_led0: gsw-phy0-led0@0 {
1140 reg = <0>;
1141 function = LED_FUNCTION_LAN;
1142 status = "disabled";
1143 };
1144
1145 gsw_phy0_led1: gsw-phy0-led1@1 {
1146 reg = <1>;
1147 function = LED_FUNCTION_LAN;
1148 status = "disabled";
1149 };
1150 };
1151 };
1152
1153 gsw_phy1: ethernet-phy@1 {
1154 compatible = "ethernet-phy-ieee802.3-c22";
1155 reg = <1>;
1156 phy-mode = "internal";
1157 nvmem-cells = <&phy_calibration_p1>;
1158 nvmem-cell-names = "phy-cal-data";
1159
1160 leds {
1161 #address-cells = <1>;
1162 #size-cells = <0>;
1163
1164 gsw_phy1_led0: gsw-phy1-led0@0 {
1165 reg = <0>;
1166 function = LED_FUNCTION_LAN;
1167 status = "disabled";
1168 };
1169
1170 gsw_phy1_led1: gsw-phy1-led1@1 {
1171 reg = <1>;
1172 function = LED_FUNCTION_LAN;
1173 status = "disabled";
1174 };
1175 };
1176 };
1177
1178 gsw_phy2: ethernet-phy@2 {
1179 compatible = "ethernet-phy-ieee802.3-c22";
1180 reg = <2>;
1181 phy-mode = "internal";
1182 nvmem-cells = <&phy_calibration_p2>;
1183 nvmem-cell-names = "phy-cal-data";
1184
1185 leds {
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188
1189 gsw_phy2_led0: gsw-phy2-led0@0 {
1190 reg = <0>;
1191 function = LED_FUNCTION_LAN;
1192 status = "disabled";
1193 };
1194
1195 gsw_phy2_led1: gsw-phy2-led1@1 {
1196 reg = <1>;
1197 function = LED_FUNCTION_LAN;
1198 status = "disabled";
1199 };
1200 };
1201 };
1202
1203 gsw_phy3: ethernet-phy@3 {
1204 compatible = "ethernet-phy-ieee802.3-c22";
1205 reg = <3>;
1206 phy-mode = "internal";
1207 nvmem-cells = <&phy_calibration_p3>;
1208 nvmem-cell-names = "phy-cal-data";
1209
1210 leds {
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1213
1214 gsw_phy3_led0: gsw-phy3-led0@0 {
1215 reg = <0>;
1216 function = LED_FUNCTION_LAN;
1217 status = "disabled";
1218 };
1219
1220 gsw_phy3_led1: gsw-phy3-led1@1 {
1221 reg = <1>;
1222 function = LED_FUNCTION_LAN;
1223 status = "disabled";
1224 };
1225 };
1226 };
1227 };
1228 };
1229
1230 ethwarp: syscon@15031000 {
1231 compatible = "mediatek,mt7988-ethwarp", "syscon", "simple-mfd";
1232 reg = <0 0x15031000 0 0x1000>;
1233 #clock-cells = <1>;
1234
1235 ethrst: reset-controller {
1236 compatible = "ti,syscon-reset";
1237 #reset-cells = <1>;
1238 ti,reset-bits = <
1239 0x8 9 0x8 9 0 0 (ASSERT_SET | DEASSERT_CLEAR | STATUS_NONE)
1240 >;
1241 };
1242 };
1243
1244 eth: ethernet@15100000 {
1245 compatible = "mediatek,mt7988-eth";
1246 reg = <0 0x15100000 0 0x80000>,
1247 <0 0x15400000 0 0x380000>;
1248 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
1252 clocks = <&ethsys CLK_ETHDMA_XGP1_EN>,
1253 <&ethsys CLK_ETHDMA_XGP2_EN>,
1254 <&ethsys CLK_ETHDMA_XGP3_EN>,
1255 <&ethsys CLK_ETHDMA_FE_EN>,
1256 <&ethsys CLK_ETHDMA_GP2_EN>,
1257 <&ethsys CLK_ETHDMA_GP1_EN>,
1258 <&ethsys CLK_ETHDMA_GP3_EN>,
1259 <&ethsys CLK_ETHDMA_ESW_EN>,
1260 <&ethsys CLK_ETHDMA_CRYPT0_EN>,
1261 <&sgmiisys0 CLK_SGM0_TX_EN>,
1262 <&sgmiisys0 CLK_SGM0_RX_EN>,
1263 <&sgmiisys1 CLK_SGM1_TX_EN>,
1264 <&sgmiisys1 CLK_SGM1_RX_EN>,
1265 <&ethwarp CLK_ETHWARP_WOCPU2_EN>,
1266 <&ethwarp CLK_ETHWARP_WOCPU1_EN>,
1267 <&ethwarp CLK_ETHWARP_WOCPU0_EN>,
1268 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1269 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1270 <&topckgen CLK_TOP_SGM_0_SEL>,
1271 <&topckgen CLK_TOP_SGM_1_SEL>,
1272 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>,
1273 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>,
1274 <&topckgen CLK_TOP_ETH_GMII_SEL>,
1275 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>,
1276 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>,
1277 <&topckgen CLK_TOP_ETH_SYS_SEL>,
1278 <&topckgen CLK_TOP_ETH_XGMII_SEL>,
1279 <&topckgen CLK_TOP_ETH_MII_SEL>,
1280 <&topckgen CLK_TOP_NETSYS_SEL>,
1281 <&topckgen CLK_TOP_NETSYS_500M_SEL>,
1282 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>,
1283 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>,
1284 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>,
1285 <&topckgen CLK_TOP_NETSYS_WARP_SEL>;
1286 clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1",
1287 "gp3", "esw", "crypto", "sgmii_tx250m",
1288 "sgmii_rx250m", "sgmii2_tx250m", "sgmii2_rx250m",
1289 "ethwarp_wocpu2", "ethwarp_wocpu1",
1290 "ethwarp_wocpu0", "top_usxgmii0_sel",
1291 "top_usxgmii1_sel", "top_sgm0_sel",
1292 "top_sgm1_sel", "top_xfi_phy0_xtal_sel",
1293 "top_xfi_phy1_xtal_sel", "top_eth_gmii_sel",
1294 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel",
1295 "top_eth_sys_sel", "top_eth_xgmii_sel",
1296 "top_eth_mii_sel", "top_netsys_sel",
1297 "top_netsys_500m_sel", "top_netsys_pao_2x_sel",
1298 "top_netsys_sync_250m_sel",
1299 "top_netsys_ppefb_250m_sel",
1300 "top_netsys_warp_sel";
1301 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
1302 <&topckgen CLK_TOP_NETSYS_GSW_SEL>,
1303 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>,
1304 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>,
1305 <&topckgen CLK_TOP_SGM_0_SEL>,
1306 <&topckgen CLK_TOP_SGM_1_SEL>;
1307 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
1308 <&topckgen CLK_TOP_NET1PLL_D4>,
1309 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1310 <&topckgen CLK_TOP_NET1PLL_D8_D4>,
1311 <&apmixedsys CLK_APMIXED_SGMPLL>,
1312 <&apmixedsys CLK_APMIXED_SGMPLL>;
1313 mediatek,ethsys = <&ethsys>;
1314 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
1315 mediatek,usxgmiisys = <&usxgmiisys0>, <&usxgmiisys1>;
1316 mediatek,xfi-pextp = <&xfi_pextp0>, <&xfi_pextp1>;
1317 mediatek,xfi-pll = <&xfi_pll>;
1318 mediatek,infracfg = <&topmisc>;
1319 mediatek,toprgu = <&watchdog>;
1320 #reset-cells = <1>;
1321 #address-cells = <1>;
1322 #size-cells = <0>;
1323
1324 gmac0: mac@0 {
1325 compatible = "mediatek,eth-mac";
1326 reg = <0>;
1327 phy-mode = "internal";
1328 status = "disabled";
1329
1330 fixed-link {
1331 speed = <10000>;
1332 full-duplex;
1333 pause;
1334 };
1335 };
1336
1337 gmac1: mac@1 {
1338 compatible = "mediatek,eth-mac";
1339 reg = <1>;
1340 status = "disabled";
1341 };
1342
1343 gmac2: mac@2 {
1344 compatible = "mediatek,eth-mac";
1345 reg = <2>;
1346 status = "disabled";
1347 };
1348
1349 mdio_bus: mdio-bus {
1350 #address-cells = <1>;
1351 #size-cells = <0>;
1352
1353 /* internal 2.5G PHY */
1354 int_2p5g_phy: ethernet-phy@15 {
1355 reg = <15>;
1356 compatible = "ethernet-phy-ieee802.3-c45";
1357 phy-mode = "internal";
1358 };
1359 };
1360 };
1361
1362 crypto: crypto@15600000 {
1363 compatible = "inside-secure,safexcel-eip197b";
1364 reg = <0 0x15600000 0 0x180000>;
1365 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
1369 interrupt-names = "ring0", "ring1", "ring2", "ring3";
1370 status = "okay";
1371 };
1372 };
1373
1374 thermal-zones {
1375 cpu_thermal: cpu-thermal {
1376 polling-delay-passive = <1000>;
1377 polling-delay = <1000>;
1378 thermal-sensors = <&lvts 0>;
1379 trips {
1380 cpu_trip_crit: crit {
1381 temperature = <125000>;
1382 hysteresis = <2000>;
1383 type = "critical";
1384 };
1385
1386 cpu_trip_hot: hot {
1387 temperature = <120000>;
1388 hysteresis = <2000>;
1389 type = "hot";
1390 };
1391
1392 cpu_trip_active_high: active-high {
1393 temperature = <115000>;
1394 hysteresis = <2000>;
1395 type = "active";
1396 };
1397
1398 cpu_trip_active_med: active-med {
1399 temperature = <85000>;
1400 hysteresis = <2000>;
1401 type = "active";
1402 };
1403
1404 cpu_trip_active_low: active-low {
1405 temperature = <40000>;
1406 hysteresis = <2000>;
1407 type = "active";
1408 };
1409 };
1410
1411 cooling-maps {
1412 cpu-active-high {
1413 /* active: set fan to cooling level 2 */
1414 cooling-device = <&fan 3 3>;
1415 trip = <&cpu_trip_active_high>;
1416 };
1417
1418 cpu-active-low {
1419 /* active: set fan to cooling level 1 */
1420 cooling-device = <&fan 2 2>;
1421 trip = <&cpu_trip_active_med>;
1422 };
1423
1424 cpu-passive {
1425 /* passive: set fan to cooling level 0 */
1426 cooling-device = <&fan 1 1>;
1427 trip = <&cpu_trip_active_low>;
1428 };
1429 };
1430 };
1431 };
1432
1433 timer {
1434 compatible = "arm,armv8-timer";
1435 interrupt-parent = <&gic>;
1436 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1437 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1438 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1439 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1440 };
1441 };
Staging tree of Robert Marko