target/linux/mediatek/dts/mt7986a-xiaomi-redmi-router-ax6000.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/leds/common.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 #include "mt7986a.dtsi"
  10
  11 / {
  12         aliases {
  13                 serial0 = &uart0;
  14                 led-boot = &led_status_rgb;
  15                 led-failsafe = &led_status_rgb;
  16                 led-running = &led_status_rgb;
  17                 led-upgrade = &led_status_rgb;
  18         };
  19
  20         chosen: chosen {
  21                 stdout-path = "serial0:115200n8";
  22         };
  23
  24         memory {
  25                 reg = <0 0x40000000 0 0x20000000>;
  26         };
  27
  28         keys {
  29                 compatible = "gpio-keys";
  30
  31                 reset {
  32                         label = "reset";
  33                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  34                         linux,code = <KEY_RESTART>;
  35                 };
  36
  37                 mesh {
  38                         label = "mesh";
  39                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  40                         linux,code = <BTN_9>;
  41                         linux,input-type = <EV_SW>;
  42                 };
  43         };
  44 };
  45
  46 &crypto {
  47         status = "okay";
  48 };
  49
  50 &eth {
  51         status = "okay";
  52
  53         gmac0: mac@0 {
  54                 compatible = "mediatek,eth-mac";
  55                 reg = <0>;
  56                 phy-mode = "2500base-x";
  57
  58                 nvmem-cells = <&macaddr_factory_4 (-1)>;
  59                 nvmem-cell-names = "mac-address";
  60
  61                 fixed-link {
  62                         speed = <2500>;
  63                         full-duplex;
  64                         pause;
  65                 };
  66         };
  67
  68         mdio: mdio-bus {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71         };
  72 };
  73
  74 &mdio {
  75         switch: switch@1f {
  76                 compatible = "mediatek,mt7531";
  77                 reg = <31>;
  78                 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
  79                 interrupt-controller;
  80                 #interrupt-cells = <1>;
  81                 interrupt-parent = <&pio>;
  82                 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
  83         };
  84 };
  85
  86 &pio {
  87         spi_flash_pins: spi-flash-pins-33-to-38 {
  88                 mux {
  89                         function = "spi";
  90                         groups = "spi0", "spi0_wp_hold";
  91                 };
  92                 conf-pu {
  93                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
  94                         drive-strength = <8>;
  95                         mediatek,pull-up-adv = <0>; /* bias-disable */
  96                 };
  97                 conf-pd {
  98                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
  99                         drive-strength = <8>;
 100                         mediatek,pull-down-adv = <0>; /* bias-disable */
 101                 };
 102         };
 103
 104         spi_led_pins: spic-pins-29-to-32 {
 105                 mux {
 106                         function = "spi";
 107                         groups = "spi1_2";
 108                 };
 109         };
 110
 111         wf_2g_5g_pins: wf_2g_5g-pins {
 112                 mux {
 113                         function = "wifi";
 114                         groups = "wf_2g", "wf_5g";
 115                 };
 116                 conf {
 117                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 118                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 119                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 120                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 121                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 122                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 123                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 124                         drive-strength = <4>;
 125                 };
 126         };
 127 };
 128
 129 &spi0 {
 130         pinctrl-names = "default";
 131         pinctrl-0 = <&spi_flash_pins>;
 132         status = "okay";
 133
 134         spi_nand_flash: flash@0 {
 135                 compatible = "spi-nand";
 136                 #address-cells = <1>;
 137                 #size-cells = <1>;
 138                 reg = <0>;
 139
 140                 spi-max-frequency = <20000000>;
 141                 spi-tx-bus-width = <4>;
 142                 spi-rx-bus-width = <4>;
 143
 144                 partitions: partitions {
 145                         compatible = "fixed-partitions";
 146                         #address-cells = <1>;
 147                         #size-cells = <1>;
 148
 149                         partition@0 {
 150                                 label = "BL2";
 151                                 reg = <0x0 0x100000>;
 152                                 read-only;
 153                         };
 154
 155                         partition@100000 {
 156                                 label = "Nvram";
 157                                 reg = <0x100000 0x40000>;
 158                         };
 159
 160                         partition@140000 {
 161                                 label = "Bdata";
 162                                 reg = <0x140000 0x40000>;
 163                         };
 164
 165                         factory: partition@180000 {
 166                                 label = "Factory";
 167                                 reg = <0x180000 0x200000>;
 168                                 read-only;
 169
 170                                 nvmem-layout {
 171                                         compatible = "fixed-layout";
 172                                         #address-cells = <1>;
 173                                         #size-cells = <1>;
 174
 175                                         macaddr_factory_4: macaddr@4 {
 176                                                 compatible = "mac-base";
 177                                                 reg = <0x4 0x6>;
 178                                                 #nvmem-cell-cells = <1>;
 179                                         };
 180                                 };
 181                         };
 182
 183                         partition@380000 {
 184                                 label = "FIP";
 185                                 reg = <0x380000 0x200000>;
 186                                 read-only;
 187                         };
 188                 };
 189         };
 190 };
 191
 192 &spi1 {
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&spi_led_pins>;
 195         status = "okay";
 196
 197         ws2812b@0 {
 198                 #address-cells = <1>;
 199                 #size-cells = <0>;
 200                 compatible = "worldsemi,ws2812b";
 201                 reg = <0>;
 202                 spi-max-frequency = <3000000>;
 203
 204                 led_status_rgb: led@0 {
 205                         reg = <0>;
 206                         function = LED_FUNCTION_STATUS;
 207                         color = <LED_COLOR_ID_RGB>;
 208                         color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
 209                 };
 210
 211                 led_network_rgb: led@1 {
 212                         reg = <1>;
 213
 214                         /* Hardcoding here for backward compatibility */
 215                         function = "network";
 216
 217                         color = <LED_COLOR_ID_RGB>;
 218                         color-index = <LED_COLOR_ID_RED LED_COLOR_ID_GREEN LED_COLOR_ID_BLUE>;
 219                 };
 220         };
 221 };
 222
 223 &switch {
 224         ports {
 225                 #address-cells = <1>;
 226                 #size-cells = <0>;
 227
 228                 port@1 {
 229                         reg = <1>;
 230                         label = "lan4";
 231                 };
 232
 233                 port@2 {
 234                         reg = <2>;
 235                         label = "lan3";
 236                 };
 237
 238                 port@3 {
 239                         reg = <3>;
 240                         label = "lan2";
 241                 };
 242
 243                 port@4 {
 244                         reg = <4>;
 245                         label = "wan";
 246                 };
 247
 248                 port@6 {
 249                         reg = <6>;
 250                         ethernet = <&gmac0>;
 251                         phy-mode = "2500base-x";
 252
 253                         fixed-link {
 254                                 speed = <2500>;
 255                                 full-duplex;
 256                                 pause;
 257                         };
 258                 };
 259         };
 260 };
 261
 262 &trng {
 263         status = "okay";
 264 };
 265
 266 &uart0 {
 267         status = "okay";
 268 };
 269
 270 &watchdog {
 271         status = "okay";
 272 };
 273
 274 &wifi {
 275         status = "okay";
 276         pinctrl-names = "default";
 277         pinctrl-0 = <&wf_2g_5g_pins>;
 278
 279         mediatek,mtd-eeprom = <&factory 0x0>;
 280 };
 281
 282 &uart0 {
 283         status = "okay";
 284 };